1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 49 #define mlx5_ib_dbg(dev, format, arg...) \ 50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_err(dev, format, arg...) \ 54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define mlx5_ib_warn(dev, format, arg...) \ 58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 59 __LINE__, current->pid, ##arg) 60 61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 62 sizeof(((type *)0)->fld) <= (sz)) 63 #define MLX5_IB_DEFAULT_UIDX 0xffffff 64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 65 66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 67 68 enum { 69 MLX5_IB_MMAP_CMD_SHIFT = 8, 70 MLX5_IB_MMAP_CMD_MASK = 0xff, 71 }; 72 73 enum mlx5_ib_mmap_cmd { 74 MLX5_IB_MMAP_REGULAR_PAGE = 0, 75 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 76 MLX5_IB_MMAP_WC_PAGE = 2, 77 MLX5_IB_MMAP_NC_PAGE = 3, 78 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 79 MLX5_IB_MMAP_CORE_CLOCK = 5, 80 }; 81 82 enum { 83 MLX5_RES_SCAT_DATA32_CQE = 0x1, 84 MLX5_RES_SCAT_DATA64_CQE = 0x2, 85 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 86 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 87 }; 88 89 enum mlx5_ib_latency_class { 90 MLX5_IB_LATENCY_CLASS_LOW, 91 MLX5_IB_LATENCY_CLASS_MEDIUM, 92 MLX5_IB_LATENCY_CLASS_HIGH, 93 }; 94 95 enum mlx5_ib_mad_ifc_flags { 96 MLX5_MAD_IFC_IGNORE_MKEY = 1, 97 MLX5_MAD_IFC_IGNORE_BKEY = 2, 98 MLX5_MAD_IFC_NET_VIEW = 4, 99 }; 100 101 enum { 102 MLX5_CROSS_CHANNEL_BFREG = 0, 103 }; 104 105 enum { 106 MLX5_CQE_VERSION_V0, 107 MLX5_CQE_VERSION_V1, 108 }; 109 110 enum { 111 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 112 MLX5_TM_MAX_SGE = 1, 113 }; 114 115 struct mlx5_ib_vma_private_data { 116 struct list_head list; 117 struct vm_area_struct *vma; 118 }; 119 120 struct mlx5_ib_ucontext { 121 struct ib_ucontext ibucontext; 122 struct list_head db_page_list; 123 124 /* protect doorbell record alloc/free 125 */ 126 struct mutex db_page_mutex; 127 struct mlx5_bfreg_info bfregi; 128 u8 cqe_version; 129 /* Transport Domain number */ 130 u32 tdn; 131 struct list_head vma_private_list; 132 133 unsigned long upd_xlt_page; 134 /* protect ODP/KSM */ 135 struct mutex upd_xlt_page_mutex; 136 u64 lib_caps; 137 }; 138 139 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 140 { 141 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 142 } 143 144 struct mlx5_ib_pd { 145 struct ib_pd ibpd; 146 u32 pdn; 147 }; 148 149 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 150 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 151 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 152 #error "Invalid number of bypass priorities" 153 #endif 154 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 155 156 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 157 #define MLX5_IB_NUM_SNIFFER_FTS 2 158 struct mlx5_ib_flow_prio { 159 struct mlx5_flow_table *flow_table; 160 unsigned int refcount; 161 }; 162 163 struct mlx5_ib_flow_handler { 164 struct list_head list; 165 struct ib_flow ibflow; 166 struct mlx5_ib_flow_prio *prio; 167 struct mlx5_flow_handle *rule; 168 }; 169 170 struct mlx5_ib_flow_db { 171 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 172 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 173 struct mlx5_flow_table *lag_demux_ft; 174 /* Protect flow steering bypass flow tables 175 * when add/del flow rules. 176 * only single add/removal of flow steering rule could be done 177 * simultaneously. 178 */ 179 struct mutex lock; 180 }; 181 182 /* Use macros here so that don't have to duplicate 183 * enum ib_send_flags and enum ib_qp_type for low-level driver 184 */ 185 186 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 187 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 188 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 189 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 190 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 191 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 192 193 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 194 /* 195 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 196 * creates the actual hardware QP. 197 */ 198 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 199 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 200 201 #define MLX5_IB_UMR_OCTOWORD 16 202 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 203 204 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 205 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 206 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 207 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 208 #define MLX5_IB_UPD_XLT_PD BIT(4) 209 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 210 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 211 212 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 213 * 214 * These flags are intended for internal use by the mlx5_ib driver, and they 215 * rely on the range reserved for that use in the ib_qp_create_flags enum. 216 */ 217 218 /* Create a UD QP whose source QP number is 1 */ 219 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 220 { 221 return IB_QP_CREATE_RESERVED_START; 222 } 223 224 struct wr_list { 225 u16 opcode; 226 u16 next; 227 }; 228 229 enum mlx5_ib_rq_flags { 230 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 231 }; 232 233 struct mlx5_ib_wq { 234 u64 *wrid; 235 u32 *wr_data; 236 struct wr_list *w_list; 237 unsigned *wqe_head; 238 u16 unsig_count; 239 240 /* serialize post to the work queue 241 */ 242 spinlock_t lock; 243 int wqe_cnt; 244 int max_post; 245 int max_gs; 246 int offset; 247 int wqe_shift; 248 unsigned head; 249 unsigned tail; 250 u16 cur_post; 251 u16 last_poll; 252 void *qend; 253 }; 254 255 enum mlx5_ib_wq_flags { 256 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 257 }; 258 259 struct mlx5_ib_rwq { 260 struct ib_wq ibwq; 261 struct mlx5_core_qp core_qp; 262 u32 rq_num_pas; 263 u32 log_rq_stride; 264 u32 log_rq_size; 265 u32 rq_page_offset; 266 u32 log_page_size; 267 struct ib_umem *umem; 268 size_t buf_size; 269 unsigned int page_shift; 270 int create_type; 271 struct mlx5_db db; 272 u32 user_index; 273 u32 wqe_count; 274 u32 wqe_shift; 275 int wq_sig; 276 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 277 }; 278 279 enum { 280 MLX5_QP_USER, 281 MLX5_QP_KERNEL, 282 MLX5_QP_EMPTY 283 }; 284 285 enum { 286 MLX5_WQ_USER, 287 MLX5_WQ_KERNEL 288 }; 289 290 struct mlx5_ib_rwq_ind_table { 291 struct ib_rwq_ind_table ib_rwq_ind_tbl; 292 u32 rqtn; 293 }; 294 295 struct mlx5_ib_ubuffer { 296 struct ib_umem *umem; 297 int buf_size; 298 u64 buf_addr; 299 }; 300 301 struct mlx5_ib_qp_base { 302 struct mlx5_ib_qp *container_mibqp; 303 struct mlx5_core_qp mqp; 304 struct mlx5_ib_ubuffer ubuffer; 305 }; 306 307 struct mlx5_ib_qp_trans { 308 struct mlx5_ib_qp_base base; 309 u16 xrcdn; 310 u8 alt_port; 311 u8 atomic_rd_en; 312 u8 resp_depth; 313 }; 314 315 struct mlx5_ib_rss_qp { 316 u32 tirn; 317 }; 318 319 struct mlx5_ib_rq { 320 struct mlx5_ib_qp_base base; 321 struct mlx5_ib_wq *rq; 322 struct mlx5_ib_ubuffer ubuffer; 323 struct mlx5_db *doorbell; 324 u32 tirn; 325 u8 state; 326 u32 flags; 327 }; 328 329 struct mlx5_ib_sq { 330 struct mlx5_ib_qp_base base; 331 struct mlx5_ib_wq *sq; 332 struct mlx5_ib_ubuffer ubuffer; 333 struct mlx5_db *doorbell; 334 u32 tisn; 335 u8 state; 336 }; 337 338 struct mlx5_ib_raw_packet_qp { 339 struct mlx5_ib_sq sq; 340 struct mlx5_ib_rq rq; 341 }; 342 343 struct mlx5_bf { 344 int buf_size; 345 unsigned long offset; 346 struct mlx5_sq_bfreg *bfreg; 347 }; 348 349 struct mlx5_ib_qp { 350 struct ib_qp ibqp; 351 union { 352 struct mlx5_ib_qp_trans trans_qp; 353 struct mlx5_ib_raw_packet_qp raw_packet_qp; 354 struct mlx5_ib_rss_qp rss_qp; 355 }; 356 struct mlx5_buf buf; 357 358 struct mlx5_db db; 359 struct mlx5_ib_wq rq; 360 361 u8 sq_signal_bits; 362 u8 next_fence; 363 struct mlx5_ib_wq sq; 364 365 /* serialize qp state modifications 366 */ 367 struct mutex mutex; 368 u32 flags; 369 u8 port; 370 u8 state; 371 int wq_sig; 372 int scat_cqe; 373 int max_inline_data; 374 struct mlx5_bf bf; 375 int has_rq; 376 377 /* only for user space QPs. For kernel 378 * we have it from the bf object 379 */ 380 int bfregn; 381 382 int create_type; 383 384 /* Store signature errors */ 385 bool signature_en; 386 387 struct list_head qps_list; 388 struct list_head cq_recv_list; 389 struct list_head cq_send_list; 390 u32 rate_limit; 391 u32 underlay_qpn; 392 }; 393 394 struct mlx5_ib_cq_buf { 395 struct mlx5_buf buf; 396 struct ib_umem *umem; 397 int cqe_size; 398 int nent; 399 }; 400 401 enum mlx5_ib_qp_flags { 402 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 403 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 404 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 405 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 406 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 407 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 408 /* QP uses 1 as its source QP number */ 409 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 410 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 411 MLX5_IB_QP_RSS = 1 << 8, 412 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 413 MLX5_IB_QP_UNDERLAY = 1 << 10, 414 }; 415 416 struct mlx5_umr_wr { 417 struct ib_send_wr wr; 418 u64 virt_addr; 419 u64 offset; 420 struct ib_pd *pd; 421 unsigned int page_shift; 422 unsigned int xlt_size; 423 u64 length; 424 int access_flags; 425 u32 mkey; 426 }; 427 428 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 429 { 430 return container_of(wr, struct mlx5_umr_wr, wr); 431 } 432 433 struct mlx5_shared_mr_info { 434 int mr_id; 435 struct ib_umem *umem; 436 }; 437 438 struct mlx5_ib_cq { 439 struct ib_cq ibcq; 440 struct mlx5_core_cq mcq; 441 struct mlx5_ib_cq_buf buf; 442 struct mlx5_db db; 443 444 /* serialize access to the CQ 445 */ 446 spinlock_t lock; 447 448 /* protect resize cq 449 */ 450 struct mutex resize_mutex; 451 struct mlx5_ib_cq_buf *resize_buf; 452 struct ib_umem *resize_umem; 453 int cqe_size; 454 struct list_head list_send_qp; 455 struct list_head list_recv_qp; 456 u32 create_flags; 457 struct list_head wc_list; 458 enum ib_cq_notify_flags notify_flags; 459 struct work_struct notify_work; 460 }; 461 462 struct mlx5_ib_wc { 463 struct ib_wc wc; 464 struct list_head list; 465 }; 466 467 struct mlx5_ib_srq { 468 struct ib_srq ibsrq; 469 struct mlx5_core_srq msrq; 470 struct mlx5_buf buf; 471 struct mlx5_db db; 472 u64 *wrid; 473 /* protect SRQ hanlding 474 */ 475 spinlock_t lock; 476 int head; 477 int tail; 478 u16 wqe_ctr; 479 struct ib_umem *umem; 480 /* serialize arming a SRQ 481 */ 482 struct mutex mutex; 483 int wq_sig; 484 }; 485 486 struct mlx5_ib_xrcd { 487 struct ib_xrcd ibxrcd; 488 u32 xrcdn; 489 }; 490 491 enum mlx5_ib_mtt_access_flags { 492 MLX5_IB_MTT_READ = (1 << 0), 493 MLX5_IB_MTT_WRITE = (1 << 1), 494 }; 495 496 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 497 498 struct mlx5_ib_mr { 499 struct ib_mr ibmr; 500 void *descs; 501 dma_addr_t desc_map; 502 int ndescs; 503 int max_descs; 504 int desc_size; 505 int access_mode; 506 struct mlx5_core_mkey mmkey; 507 struct ib_umem *umem; 508 struct mlx5_shared_mr_info *smr_info; 509 struct list_head list; 510 int order; 511 bool allocated_from_cache; 512 int npages; 513 struct mlx5_ib_dev *dev; 514 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 515 struct mlx5_core_sig_ctx *sig; 516 int live; 517 void *descs_alloc; 518 int access_flags; /* Needed for rereg MR */ 519 520 struct mlx5_ib_mr *parent; 521 atomic_t num_leaf_free; 522 wait_queue_head_t q_leaf_free; 523 }; 524 525 struct mlx5_ib_mw { 526 struct ib_mw ibmw; 527 struct mlx5_core_mkey mmkey; 528 int ndescs; 529 }; 530 531 struct mlx5_ib_umr_context { 532 struct ib_cqe cqe; 533 enum ib_wc_status status; 534 struct completion done; 535 }; 536 537 struct umr_common { 538 struct ib_pd *pd; 539 struct ib_cq *cq; 540 struct ib_qp *qp; 541 /* control access to UMR QP 542 */ 543 struct semaphore sem; 544 }; 545 546 enum { 547 MLX5_FMR_INVALID, 548 MLX5_FMR_VALID, 549 MLX5_FMR_BUSY, 550 }; 551 552 struct mlx5_cache_ent { 553 struct list_head head; 554 /* sync access to the cahce entry 555 */ 556 spinlock_t lock; 557 558 559 struct dentry *dir; 560 char name[4]; 561 u32 order; 562 u32 xlt; 563 u32 access_mode; 564 u32 page; 565 566 u32 size; 567 u32 cur; 568 u32 miss; 569 u32 limit; 570 571 struct dentry *fsize; 572 struct dentry *fcur; 573 struct dentry *fmiss; 574 struct dentry *flimit; 575 576 struct mlx5_ib_dev *dev; 577 struct work_struct work; 578 struct delayed_work dwork; 579 int pending; 580 struct completion compl; 581 }; 582 583 struct mlx5_mr_cache { 584 struct workqueue_struct *wq; 585 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 586 int stopped; 587 struct dentry *root; 588 unsigned long last_add; 589 }; 590 591 struct mlx5_ib_gsi_qp; 592 593 struct mlx5_ib_port_resources { 594 struct mlx5_ib_resources *devr; 595 struct mlx5_ib_gsi_qp *gsi; 596 struct work_struct pkey_change_work; 597 }; 598 599 struct mlx5_ib_resources { 600 struct ib_cq *c0; 601 struct ib_xrcd *x0; 602 struct ib_xrcd *x1; 603 struct ib_pd *p0; 604 struct ib_srq *s0; 605 struct ib_srq *s1; 606 struct mlx5_ib_port_resources ports[2]; 607 /* Protects changes to the port resources */ 608 struct mutex mutex; 609 }; 610 611 struct mlx5_ib_counters { 612 const char **names; 613 size_t *offsets; 614 u32 num_q_counters; 615 u32 num_cong_counters; 616 u16 set_id; 617 }; 618 619 struct mlx5_ib_port { 620 struct mlx5_ib_counters cnts; 621 }; 622 623 struct mlx5_roce { 624 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 625 * netdev pointer 626 */ 627 rwlock_t netdev_lock; 628 struct net_device *netdev; 629 struct notifier_block nb; 630 atomic_t next_port; 631 enum ib_port_state last_port_state; 632 }; 633 634 struct mlx5_ib_dbg_param { 635 int offset; 636 struct mlx5_ib_dev *dev; 637 struct dentry *dentry; 638 }; 639 640 enum mlx5_ib_dbg_cc_types { 641 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 642 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 643 MLX5_IB_DBG_CC_RP_TIME_RESET, 644 MLX5_IB_DBG_CC_RP_BYTE_RESET, 645 MLX5_IB_DBG_CC_RP_THRESHOLD, 646 MLX5_IB_DBG_CC_RP_AI_RATE, 647 MLX5_IB_DBG_CC_RP_HAI_RATE, 648 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 649 MLX5_IB_DBG_CC_RP_MIN_RATE, 650 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 651 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 652 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 653 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 654 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 655 MLX5_IB_DBG_CC_RP_GD, 656 MLX5_IB_DBG_CC_NP_CNP_DSCP, 657 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 658 MLX5_IB_DBG_CC_NP_CNP_PRIO, 659 MLX5_IB_DBG_CC_MAX, 660 }; 661 662 struct mlx5_ib_dbg_cc_params { 663 struct dentry *root; 664 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 665 }; 666 667 enum { 668 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 669 }; 670 671 struct mlx5_ib_dbg_delay_drop { 672 struct dentry *dir_debugfs; 673 struct dentry *rqs_cnt_debugfs; 674 struct dentry *events_cnt_debugfs; 675 struct dentry *timeout_debugfs; 676 }; 677 678 struct mlx5_ib_delay_drop { 679 struct mlx5_ib_dev *dev; 680 struct work_struct delay_drop_work; 681 /* serialize setting of delay drop */ 682 struct mutex lock; 683 u32 timeout; 684 bool activate; 685 atomic_t events_cnt; 686 atomic_t rqs_cnt; 687 struct mlx5_ib_dbg_delay_drop *dbg; 688 }; 689 690 struct mlx5_ib_dev { 691 struct ib_device ib_dev; 692 struct mlx5_core_dev *mdev; 693 struct mlx5_roce roce; 694 int num_ports; 695 /* serialize update of capability mask 696 */ 697 struct mutex cap_mask_mutex; 698 bool ib_active; 699 struct umr_common umrc; 700 /* sync used page count stats 701 */ 702 struct mlx5_ib_resources devr; 703 struct mlx5_mr_cache cache; 704 struct timer_list delay_timer; 705 /* Prevents soft lock on massive reg MRs */ 706 struct mutex slow_path_mutex; 707 int fill_delay; 708 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 709 struct ib_odp_caps odp_caps; 710 u64 odp_max_size; 711 /* 712 * Sleepable RCU that prevents destruction of MRs while they are still 713 * being used by a page fault handler. 714 */ 715 struct srcu_struct mr_srcu; 716 u32 null_mkey; 717 #endif 718 struct mlx5_ib_flow_db flow_db; 719 /* protect resources needed as part of reset flow */ 720 spinlock_t reset_flow_resource_lock; 721 struct list_head qp_list; 722 /* Array with num_ports elements */ 723 struct mlx5_ib_port *port; 724 struct mlx5_sq_bfreg bfreg; 725 struct mlx5_sq_bfreg fp_bfreg; 726 struct mlx5_ib_delay_drop delay_drop; 727 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 728 729 /* protect the user_td */ 730 struct mutex lb_mutex; 731 u32 user_td; 732 u8 umr_fence; 733 }; 734 735 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 736 { 737 return container_of(mcq, struct mlx5_ib_cq, mcq); 738 } 739 740 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 741 { 742 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 743 } 744 745 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 746 { 747 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 748 } 749 750 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 751 { 752 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 753 } 754 755 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 756 { 757 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 758 } 759 760 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 761 { 762 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 763 } 764 765 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 766 { 767 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 768 } 769 770 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 771 { 772 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 773 } 774 775 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 776 { 777 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 778 } 779 780 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 781 { 782 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 783 } 784 785 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 786 { 787 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 788 } 789 790 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 791 { 792 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 793 } 794 795 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 796 { 797 return container_of(msrq, struct mlx5_ib_srq, msrq); 798 } 799 800 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 801 { 802 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 803 } 804 805 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 806 { 807 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 808 } 809 810 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 811 struct mlx5_db *db); 812 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 813 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 814 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 815 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 816 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 817 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 818 const void *in_mad, void *response_mad); 819 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 820 struct ib_udata *udata); 821 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 822 int mlx5_ib_destroy_ah(struct ib_ah *ah); 823 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 824 struct ib_srq_init_attr *init_attr, 825 struct ib_udata *udata); 826 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 827 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 828 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 829 int mlx5_ib_destroy_srq(struct ib_srq *srq); 830 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 831 struct ib_recv_wr **bad_wr); 832 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 833 struct ib_qp_init_attr *init_attr, 834 struct ib_udata *udata); 835 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 836 int attr_mask, struct ib_udata *udata); 837 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 838 struct ib_qp_init_attr *qp_init_attr); 839 int mlx5_ib_destroy_qp(struct ib_qp *qp); 840 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 841 struct ib_send_wr **bad_wr); 842 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 843 struct ib_recv_wr **bad_wr); 844 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 845 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 846 void *buffer, u32 length, 847 struct mlx5_ib_qp_base *base); 848 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 849 const struct ib_cq_init_attr *attr, 850 struct ib_ucontext *context, 851 struct ib_udata *udata); 852 int mlx5_ib_destroy_cq(struct ib_cq *cq); 853 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 854 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 855 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 856 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 857 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 858 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 859 u64 virt_addr, int access_flags, 860 struct ib_udata *udata); 861 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 862 struct ib_udata *udata); 863 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 864 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 865 int page_shift, int flags); 866 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 867 int access_flags); 868 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 869 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 870 u64 length, u64 virt_addr, int access_flags, 871 struct ib_pd *pd, struct ib_udata *udata); 872 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 873 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 874 enum ib_mr_type mr_type, 875 u32 max_num_sg); 876 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 877 unsigned int *sg_offset); 878 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 879 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 880 const struct ib_mad_hdr *in, size_t in_mad_size, 881 struct ib_mad_hdr *out, size_t *out_mad_size, 882 u16 *out_mad_pkey_index); 883 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 884 struct ib_ucontext *context, 885 struct ib_udata *udata); 886 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 887 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 888 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 889 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 890 struct ib_smp *out_mad); 891 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 892 __be64 *sys_image_guid); 893 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 894 u16 *max_pkeys); 895 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 896 u32 *vendor_id); 897 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 898 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 899 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 900 u16 *pkey); 901 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 902 union ib_gid *gid); 903 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 904 struct ib_port_attr *props); 905 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 906 struct ib_port_attr *props); 907 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 908 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 909 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 910 unsigned long max_page_shift, 911 int *count, int *shift, 912 int *ncont, int *order); 913 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 914 int page_shift, size_t offset, size_t num_pages, 915 __be64 *pas, int access_flags); 916 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 917 int page_shift, __be64 *pas, int access_flags); 918 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 919 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 920 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 921 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 922 923 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 924 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 925 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 926 struct ib_mr_status *mr_status); 927 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 928 struct ib_wq_init_attr *init_attr, 929 struct ib_udata *udata); 930 int mlx5_ib_destroy_wq(struct ib_wq *wq); 931 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 932 u32 wq_attr_mask, struct ib_udata *udata); 933 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 934 struct ib_rwq_ind_table_init_attr *init_attr, 935 struct ib_udata *udata); 936 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 937 938 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 939 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 940 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 941 struct mlx5_pagefault *pfault); 942 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 943 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 944 int __init mlx5_ib_odp_init(void); 945 void mlx5_ib_odp_cleanup(void); 946 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 947 unsigned long end); 948 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 949 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 950 size_t nentries, struct mlx5_ib_mr *mr, int flags); 951 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 952 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 953 { 954 return; 955 } 956 957 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 958 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 959 static inline int mlx5_ib_odp_init(void) { return 0; } 960 static inline void mlx5_ib_odp_cleanup(void) {} 961 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 962 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 963 size_t nentries, struct mlx5_ib_mr *mr, 964 int flags) {} 965 966 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 967 968 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 969 u8 port, struct ifla_vf_info *info); 970 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 971 u8 port, int state); 972 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 973 u8 port, struct ifla_vf_stats *stats); 974 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 975 u64 guid, int type); 976 977 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 978 int index); 979 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 980 int index, enum ib_gid_type *gid_type); 981 982 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev); 983 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev); 984 985 /* GSI QP helper functions */ 986 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 987 struct ib_qp_init_attr *init_attr); 988 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 989 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 990 int attr_mask); 991 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 992 int qp_attr_mask, 993 struct ib_qp_init_attr *qp_init_attr); 994 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 995 struct ib_send_wr **bad_wr); 996 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 997 struct ib_recv_wr **bad_wr); 998 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 999 1000 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1001 1002 static inline void init_query_mad(struct ib_smp *mad) 1003 { 1004 mad->base_version = 1; 1005 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1006 mad->class_version = 1; 1007 mad->method = IB_MGMT_METHOD_GET; 1008 } 1009 1010 static inline u8 convert_access(int acc) 1011 { 1012 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1013 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1014 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1015 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1016 MLX5_PERM_LOCAL_READ; 1017 } 1018 1019 static inline int is_qp1(enum ib_qp_type qp_type) 1020 { 1021 return qp_type == MLX5_IB_QPT_HW_GSI; 1022 } 1023 1024 #define MLX5_MAX_UMR_SHIFT 16 1025 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1026 1027 static inline u32 check_cq_create_flags(u32 flags) 1028 { 1029 /* 1030 * It returns non-zero value for unsupported CQ 1031 * create flags, otherwise it returns zero. 1032 */ 1033 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 1034 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1035 } 1036 1037 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1038 u32 *user_index) 1039 { 1040 if (cqe_version) { 1041 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1042 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1043 return -EINVAL; 1044 *user_index = cmd_uidx; 1045 } else { 1046 *user_index = MLX5_IB_DEFAULT_UIDX; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1053 struct mlx5_ib_create_qp *ucmd, 1054 int inlen, 1055 u32 *user_index) 1056 { 1057 u8 cqe_version = ucontext->cqe_version; 1058 1059 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1060 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1061 return 0; 1062 1063 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1064 !!cqe_version)) 1065 return -EINVAL; 1066 1067 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1068 } 1069 1070 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1071 struct mlx5_ib_create_srq *ucmd, 1072 int inlen, 1073 u32 *user_index) 1074 { 1075 u8 cqe_version = ucontext->cqe_version; 1076 1077 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1078 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1079 return 0; 1080 1081 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1082 !!cqe_version)) 1083 return -EINVAL; 1084 1085 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1086 } 1087 1088 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1089 { 1090 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1091 MLX5_UARS_IN_PAGE : 1; 1092 } 1093 1094 static inline int get_num_uars(struct mlx5_ib_dev *dev, 1095 struct mlx5_bfreg_info *bfregi) 1096 { 1097 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_sys_pages; 1098 } 1099 1100 #endif /* MLX5_IB_H */ 1101