1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 48 #define mlx5_ib_dbg(dev, format, arg...) \ 49 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 50 __LINE__, current->pid, ##arg) 51 52 #define mlx5_ib_err(dev, format, arg...) \ 53 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 54 __LINE__, current->pid, ##arg) 55 56 #define mlx5_ib_warn(dev, format, arg...) \ 57 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 58 __LINE__, current->pid, ##arg) 59 60 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 61 sizeof(((type *)0)->fld) <= (sz)) 62 #define MLX5_IB_DEFAULT_UIDX 0xffffff 63 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 64 65 enum { 66 MLX5_IB_MMAP_CMD_SHIFT = 8, 67 MLX5_IB_MMAP_CMD_MASK = 0xff, 68 }; 69 70 enum mlx5_ib_mmap_cmd { 71 MLX5_IB_MMAP_REGULAR_PAGE = 0, 72 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 73 MLX5_IB_MMAP_WC_PAGE = 2, 74 MLX5_IB_MMAP_NC_PAGE = 3, 75 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 76 MLX5_IB_MMAP_CORE_CLOCK = 5, 77 }; 78 79 enum { 80 MLX5_RES_SCAT_DATA32_CQE = 0x1, 81 MLX5_RES_SCAT_DATA64_CQE = 0x2, 82 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 83 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 84 }; 85 86 enum mlx5_ib_latency_class { 87 MLX5_IB_LATENCY_CLASS_LOW, 88 MLX5_IB_LATENCY_CLASS_MEDIUM, 89 MLX5_IB_LATENCY_CLASS_HIGH, 90 MLX5_IB_LATENCY_CLASS_FAST_PATH 91 }; 92 93 enum mlx5_ib_mad_ifc_flags { 94 MLX5_MAD_IFC_IGNORE_MKEY = 1, 95 MLX5_MAD_IFC_IGNORE_BKEY = 2, 96 MLX5_MAD_IFC_NET_VIEW = 4, 97 }; 98 99 enum { 100 MLX5_CROSS_CHANNEL_UUAR = 0, 101 }; 102 103 enum { 104 MLX5_CQE_VERSION_V0, 105 MLX5_CQE_VERSION_V1, 106 }; 107 108 struct mlx5_ib_ucontext { 109 struct ib_ucontext ibucontext; 110 struct list_head db_page_list; 111 112 /* protect doorbell record alloc/free 113 */ 114 struct mutex db_page_mutex; 115 struct mlx5_uuar_info uuari; 116 u8 cqe_version; 117 /* Transport Domain number */ 118 u32 tdn; 119 }; 120 121 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 122 { 123 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 124 } 125 126 struct mlx5_ib_pd { 127 struct ib_pd ibpd; 128 u32 pdn; 129 }; 130 131 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 132 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 133 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 134 #error "Invalid number of bypass priorities" 135 #endif 136 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 137 138 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 139 struct mlx5_ib_flow_prio { 140 struct mlx5_flow_table *flow_table; 141 unsigned int refcount; 142 }; 143 144 struct mlx5_ib_flow_handler { 145 struct list_head list; 146 struct ib_flow ibflow; 147 unsigned int prio; 148 struct mlx5_flow_rule *rule; 149 }; 150 151 struct mlx5_ib_flow_db { 152 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 153 /* Protect flow steering bypass flow tables 154 * when add/del flow rules. 155 * only single add/removal of flow steering rule could be done 156 * simultaneously. 157 */ 158 struct mutex lock; 159 }; 160 161 /* Use macros here so that don't have to duplicate 162 * enum ib_send_flags and enum ib_qp_type for low-level driver 163 */ 164 165 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 166 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 167 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 168 169 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 170 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 171 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 172 173 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 174 /* 175 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 176 * creates the actual hardware QP. 177 */ 178 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 179 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 180 181 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 182 * 183 * These flags are intended for internal use by the mlx5_ib driver, and they 184 * rely on the range reserved for that use in the ib_qp_create_flags enum. 185 */ 186 187 /* Create a UD QP whose source QP number is 1 */ 188 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 189 { 190 return IB_QP_CREATE_RESERVED_START; 191 } 192 193 struct wr_list { 194 u16 opcode; 195 u16 next; 196 }; 197 198 struct mlx5_ib_wq { 199 u64 *wrid; 200 u32 *wr_data; 201 struct wr_list *w_list; 202 unsigned *wqe_head; 203 u16 unsig_count; 204 205 /* serialize post to the work queue 206 */ 207 spinlock_t lock; 208 int wqe_cnt; 209 int max_post; 210 int max_gs; 211 int offset; 212 int wqe_shift; 213 unsigned head; 214 unsigned tail; 215 u16 cur_post; 216 u16 last_poll; 217 void *qend; 218 }; 219 220 enum { 221 MLX5_QP_USER, 222 MLX5_QP_KERNEL, 223 MLX5_QP_EMPTY 224 }; 225 226 /* 227 * Connect-IB can trigger up to four concurrent pagefaults 228 * per-QP. 229 */ 230 enum mlx5_ib_pagefault_context { 231 MLX5_IB_PAGEFAULT_RESPONDER_READ, 232 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 233 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 234 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 235 MLX5_IB_PAGEFAULT_CONTEXTS 236 }; 237 238 static inline enum mlx5_ib_pagefault_context 239 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 240 { 241 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 242 } 243 244 struct mlx5_ib_pfault { 245 struct work_struct work; 246 struct mlx5_pagefault mpfault; 247 }; 248 249 struct mlx5_ib_ubuffer { 250 struct ib_umem *umem; 251 int buf_size; 252 u64 buf_addr; 253 }; 254 255 struct mlx5_ib_qp_base { 256 struct mlx5_ib_qp *container_mibqp; 257 struct mlx5_core_qp mqp; 258 struct mlx5_ib_ubuffer ubuffer; 259 }; 260 261 struct mlx5_ib_qp_trans { 262 struct mlx5_ib_qp_base base; 263 u16 xrcdn; 264 u8 alt_port; 265 u8 atomic_rd_en; 266 u8 resp_depth; 267 }; 268 269 struct mlx5_ib_rq { 270 struct mlx5_ib_qp_base base; 271 struct mlx5_ib_wq *rq; 272 struct mlx5_ib_ubuffer ubuffer; 273 struct mlx5_db *doorbell; 274 u32 tirn; 275 u8 state; 276 }; 277 278 struct mlx5_ib_sq { 279 struct mlx5_ib_qp_base base; 280 struct mlx5_ib_wq *sq; 281 struct mlx5_ib_ubuffer ubuffer; 282 struct mlx5_db *doorbell; 283 u32 tisn; 284 u8 state; 285 }; 286 287 struct mlx5_ib_raw_packet_qp { 288 struct mlx5_ib_sq sq; 289 struct mlx5_ib_rq rq; 290 }; 291 292 struct mlx5_ib_qp { 293 struct ib_qp ibqp; 294 union { 295 struct mlx5_ib_qp_trans trans_qp; 296 struct mlx5_ib_raw_packet_qp raw_packet_qp; 297 }; 298 struct mlx5_buf buf; 299 300 struct mlx5_db db; 301 struct mlx5_ib_wq rq; 302 303 u8 sq_signal_bits; 304 u8 fm_cache; 305 struct mlx5_ib_wq sq; 306 307 /* serialize qp state modifications 308 */ 309 struct mutex mutex; 310 u32 flags; 311 u8 port; 312 u8 state; 313 int wq_sig; 314 int scat_cqe; 315 int max_inline_data; 316 struct mlx5_bf *bf; 317 int has_rq; 318 319 /* only for user space QPs. For kernel 320 * we have it from the bf object 321 */ 322 int uuarn; 323 324 int create_type; 325 326 /* Store signature errors */ 327 bool signature_en; 328 329 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 330 /* 331 * A flag that is true for QP's that are in a state that doesn't 332 * allow page faults, and shouldn't schedule any more faults. 333 */ 334 int disable_page_faults; 335 /* 336 * The disable_page_faults_lock protects a QP's disable_page_faults 337 * field, allowing for a thread to atomically check whether the QP 338 * allows page faults, and if so schedule a page fault. 339 */ 340 spinlock_t disable_page_faults_lock; 341 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 342 #endif 343 }; 344 345 struct mlx5_ib_cq_buf { 346 struct mlx5_buf buf; 347 struct ib_umem *umem; 348 int cqe_size; 349 int nent; 350 }; 351 352 enum mlx5_ib_qp_flags { 353 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 354 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 355 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 356 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 357 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 358 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 359 /* QP uses 1 as its source QP number */ 360 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 361 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 362 }; 363 364 struct mlx5_umr_wr { 365 struct ib_send_wr wr; 366 union { 367 u64 virt_addr; 368 u64 offset; 369 } target; 370 struct ib_pd *pd; 371 unsigned int page_shift; 372 unsigned int npages; 373 u32 length; 374 int access_flags; 375 u32 mkey; 376 }; 377 378 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 379 { 380 return container_of(wr, struct mlx5_umr_wr, wr); 381 } 382 383 struct mlx5_shared_mr_info { 384 int mr_id; 385 struct ib_umem *umem; 386 }; 387 388 struct mlx5_ib_cq { 389 struct ib_cq ibcq; 390 struct mlx5_core_cq mcq; 391 struct mlx5_ib_cq_buf buf; 392 struct mlx5_db db; 393 394 /* serialize access to the CQ 395 */ 396 spinlock_t lock; 397 398 /* protect resize cq 399 */ 400 struct mutex resize_mutex; 401 struct mlx5_ib_cq_buf *resize_buf; 402 struct ib_umem *resize_umem; 403 int cqe_size; 404 u32 create_flags; 405 struct list_head wc_list; 406 enum ib_cq_notify_flags notify_flags; 407 struct work_struct notify_work; 408 }; 409 410 struct mlx5_ib_wc { 411 struct ib_wc wc; 412 struct list_head list; 413 }; 414 415 struct mlx5_ib_srq { 416 struct ib_srq ibsrq; 417 struct mlx5_core_srq msrq; 418 struct mlx5_buf buf; 419 struct mlx5_db db; 420 u64 *wrid; 421 /* protect SRQ hanlding 422 */ 423 spinlock_t lock; 424 int head; 425 int tail; 426 u16 wqe_ctr; 427 struct ib_umem *umem; 428 /* serialize arming a SRQ 429 */ 430 struct mutex mutex; 431 int wq_sig; 432 }; 433 434 struct mlx5_ib_xrcd { 435 struct ib_xrcd ibxrcd; 436 u32 xrcdn; 437 }; 438 439 enum mlx5_ib_mtt_access_flags { 440 MLX5_IB_MTT_READ = (1 << 0), 441 MLX5_IB_MTT_WRITE = (1 << 1), 442 }; 443 444 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 445 446 struct mlx5_ib_mr { 447 struct ib_mr ibmr; 448 void *descs; 449 dma_addr_t desc_map; 450 int ndescs; 451 int max_descs; 452 int desc_size; 453 int access_mode; 454 struct mlx5_core_mkey mmkey; 455 struct ib_umem *umem; 456 struct mlx5_shared_mr_info *smr_info; 457 struct list_head list; 458 int order; 459 int umred; 460 int npages; 461 struct mlx5_ib_dev *dev; 462 struct mlx5_create_mkey_mbox_out out; 463 struct mlx5_core_sig_ctx *sig; 464 int live; 465 void *descs_alloc; 466 int access_flags; /* Needed for rereg MR */ 467 }; 468 469 struct mlx5_ib_mw { 470 struct ib_mw ibmw; 471 struct mlx5_core_mkey mmkey; 472 }; 473 474 struct mlx5_ib_umr_context { 475 struct ib_cqe cqe; 476 enum ib_wc_status status; 477 struct completion done; 478 }; 479 480 struct umr_common { 481 struct ib_pd *pd; 482 struct ib_cq *cq; 483 struct ib_qp *qp; 484 /* control access to UMR QP 485 */ 486 struct semaphore sem; 487 }; 488 489 enum { 490 MLX5_FMR_INVALID, 491 MLX5_FMR_VALID, 492 MLX5_FMR_BUSY, 493 }; 494 495 struct mlx5_cache_ent { 496 struct list_head head; 497 /* sync access to the cahce entry 498 */ 499 spinlock_t lock; 500 501 502 struct dentry *dir; 503 char name[4]; 504 u32 order; 505 u32 size; 506 u32 cur; 507 u32 miss; 508 u32 limit; 509 510 struct dentry *fsize; 511 struct dentry *fcur; 512 struct dentry *fmiss; 513 struct dentry *flimit; 514 515 struct mlx5_ib_dev *dev; 516 struct work_struct work; 517 struct delayed_work dwork; 518 int pending; 519 }; 520 521 struct mlx5_mr_cache { 522 struct workqueue_struct *wq; 523 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 524 int stopped; 525 struct dentry *root; 526 unsigned long last_add; 527 }; 528 529 struct mlx5_ib_gsi_qp; 530 531 struct mlx5_ib_port_resources { 532 struct mlx5_ib_resources *devr; 533 struct mlx5_ib_gsi_qp *gsi; 534 struct work_struct pkey_change_work; 535 }; 536 537 struct mlx5_ib_resources { 538 struct ib_cq *c0; 539 struct ib_xrcd *x0; 540 struct ib_xrcd *x1; 541 struct ib_pd *p0; 542 struct ib_srq *s0; 543 struct ib_srq *s1; 544 struct mlx5_ib_port_resources ports[2]; 545 /* Protects changes to the port resources */ 546 struct mutex mutex; 547 }; 548 549 struct mlx5_roce { 550 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 551 * netdev pointer 552 */ 553 rwlock_t netdev_lock; 554 struct net_device *netdev; 555 struct notifier_block nb; 556 }; 557 558 struct mlx5_ib_dev { 559 struct ib_device ib_dev; 560 struct mlx5_core_dev *mdev; 561 struct mlx5_roce roce; 562 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 563 int num_ports; 564 /* serialize update of capability mask 565 */ 566 struct mutex cap_mask_mutex; 567 bool ib_active; 568 struct umr_common umrc; 569 /* sync used page count stats 570 */ 571 struct mlx5_ib_resources devr; 572 struct mlx5_mr_cache cache; 573 struct timer_list delay_timer; 574 int fill_delay; 575 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 576 struct ib_odp_caps odp_caps; 577 /* 578 * Sleepable RCU that prevents destruction of MRs while they are still 579 * being used by a page fault handler. 580 */ 581 struct srcu_struct mr_srcu; 582 #endif 583 struct mlx5_ib_flow_db flow_db; 584 }; 585 586 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 587 { 588 return container_of(mcq, struct mlx5_ib_cq, mcq); 589 } 590 591 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 592 { 593 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 594 } 595 596 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 597 { 598 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 599 } 600 601 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 602 { 603 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 604 } 605 606 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 607 { 608 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 609 } 610 611 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 612 { 613 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 614 } 615 616 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 617 { 618 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 619 } 620 621 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 622 { 623 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 624 } 625 626 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 627 { 628 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 629 } 630 631 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 632 { 633 return container_of(msrq, struct mlx5_ib_srq, msrq); 634 } 635 636 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 637 { 638 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 639 } 640 641 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 642 { 643 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 644 } 645 646 struct mlx5_ib_ah { 647 struct ib_ah ibah; 648 struct mlx5_av av; 649 }; 650 651 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 652 { 653 return container_of(ibah, struct mlx5_ib_ah, ibah); 654 } 655 656 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 657 struct mlx5_db *db); 658 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 659 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 660 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 661 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 662 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 663 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 664 const void *in_mad, void *response_mad); 665 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 666 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 667 int mlx5_ib_destroy_ah(struct ib_ah *ah); 668 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 669 struct ib_srq_init_attr *init_attr, 670 struct ib_udata *udata); 671 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 672 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 673 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 674 int mlx5_ib_destroy_srq(struct ib_srq *srq); 675 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 676 struct ib_recv_wr **bad_wr); 677 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 678 struct ib_qp_init_attr *init_attr, 679 struct ib_udata *udata); 680 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 681 int attr_mask, struct ib_udata *udata); 682 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 683 struct ib_qp_init_attr *qp_init_attr); 684 int mlx5_ib_destroy_qp(struct ib_qp *qp); 685 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 686 struct ib_send_wr **bad_wr); 687 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 688 struct ib_recv_wr **bad_wr); 689 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 690 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 691 void *buffer, u32 length, 692 struct mlx5_ib_qp_base *base); 693 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 694 const struct ib_cq_init_attr *attr, 695 struct ib_ucontext *context, 696 struct ib_udata *udata); 697 int mlx5_ib_destroy_cq(struct ib_cq *cq); 698 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 699 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 700 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 701 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 702 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 703 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 704 u64 virt_addr, int access_flags, 705 struct ib_udata *udata); 706 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 707 struct ib_udata *udata); 708 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 709 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 710 int npages, int zap); 711 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 712 u64 length, u64 virt_addr, int access_flags, 713 struct ib_pd *pd, struct ib_udata *udata); 714 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 715 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 716 enum ib_mr_type mr_type, 717 u32 max_num_sg); 718 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 719 unsigned int *sg_offset); 720 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 721 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 722 const struct ib_mad_hdr *in, size_t in_mad_size, 723 struct ib_mad_hdr *out, size_t *out_mad_size, 724 u16 *out_mad_pkey_index); 725 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 726 struct ib_ucontext *context, 727 struct ib_udata *udata); 728 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 729 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 730 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 731 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 732 struct ib_smp *out_mad); 733 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 734 __be64 *sys_image_guid); 735 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 736 u16 *max_pkeys); 737 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 738 u32 *vendor_id); 739 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 740 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 741 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 742 u16 *pkey); 743 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 744 union ib_gid *gid); 745 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 746 struct ib_port_attr *props); 747 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 748 struct ib_port_attr *props); 749 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 750 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 751 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 752 int *ncont, int *order); 753 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 754 int page_shift, size_t offset, size_t num_pages, 755 __be64 *pas, int access_flags); 756 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 757 int page_shift, __be64 *pas, int access_flags); 758 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 759 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 760 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 761 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 762 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 763 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 764 struct ib_mr_status *mr_status); 765 766 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 767 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 768 769 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 770 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 771 struct mlx5_ib_pfault *pfault); 772 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 773 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 774 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 775 int __init mlx5_ib_odp_init(void); 776 void mlx5_ib_odp_cleanup(void); 777 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 778 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 779 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 780 unsigned long end); 781 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 782 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 783 { 784 return; 785 } 786 787 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 788 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 789 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 790 static inline int mlx5_ib_odp_init(void) { return 0; } 791 static inline void mlx5_ib_odp_cleanup(void) {} 792 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 793 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 794 795 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 796 797 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 798 u8 port, struct ifla_vf_info *info); 799 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 800 u8 port, int state); 801 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 802 u8 port, struct ifla_vf_stats *stats); 803 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 804 u64 guid, int type); 805 806 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 807 int index); 808 809 /* GSI QP helper functions */ 810 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 811 struct ib_qp_init_attr *init_attr); 812 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 813 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 814 int attr_mask); 815 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 816 int qp_attr_mask, 817 struct ib_qp_init_attr *qp_init_attr); 818 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 819 struct ib_send_wr **bad_wr); 820 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 821 struct ib_recv_wr **bad_wr); 822 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 823 824 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 825 826 static inline void init_query_mad(struct ib_smp *mad) 827 { 828 mad->base_version = 1; 829 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 830 mad->class_version = 1; 831 mad->method = IB_MGMT_METHOD_GET; 832 } 833 834 static inline u8 convert_access(int acc) 835 { 836 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 837 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 838 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 839 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 840 MLX5_PERM_LOCAL_READ; 841 } 842 843 static inline int is_qp1(enum ib_qp_type qp_type) 844 { 845 return qp_type == MLX5_IB_QPT_HW_GSI; 846 } 847 848 #define MLX5_MAX_UMR_SHIFT 16 849 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 850 851 static inline u32 check_cq_create_flags(u32 flags) 852 { 853 /* 854 * It returns non-zero value for unsupported CQ 855 * create flags, otherwise it returns zero. 856 */ 857 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 858 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 859 } 860 861 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 862 u32 *user_index) 863 { 864 if (cqe_version) { 865 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 866 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 867 return -EINVAL; 868 *user_index = cmd_uidx; 869 } else { 870 *user_index = MLX5_IB_DEFAULT_UIDX; 871 } 872 873 return 0; 874 } 875 #endif /* MLX5_IB_H */ 876