1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 #include "qp.h" 29 30 #define mlx5_ib_dbg(_dev, format, arg...) \ 31 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 32 __LINE__, current->pid, ##arg) 33 34 #define mlx5_ib_err(_dev, format, arg...) \ 35 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 36 __LINE__, current->pid, ##arg) 37 38 #define mlx5_ib_warn(_dev, format, arg...) \ 39 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 40 __LINE__, current->pid, ##arg) 41 42 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 43 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 44 __func__, __LINE__, current->pid, ##arg) 45 46 #define MLX5_IB_DEFAULT_UIDX 0xffffff 47 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 48 49 static __always_inline unsigned long 50 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 51 unsigned int pgsz_shift) 52 { 53 unsigned int largest_pg_shift = 54 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 55 BITS_PER_LONG - 1); 56 57 /* 58 * Despite a command allowing it, the device does not support lower than 59 * 4k page size. 60 */ 61 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 62 return GENMASK(largest_pg_shift, pgsz_shift); 63 } 64 65 /* 66 * For mkc users, instead of a page_offset the command has a start_iova which 67 * specifies both the page_offset and the on-the-wire IOVA 68 */ 69 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 70 ib_umem_find_best_pgsz(umem, \ 71 __mlx5_log_page_size_to_bitmap( \ 72 __mlx5_bit_sz(typ, log_pgsz_fld), \ 73 pgsz_shift), \ 74 iova) 75 76 static __always_inline unsigned long 77 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 78 unsigned int offset_shift) 79 { 80 unsigned int largest_offset_shift = 81 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 82 BITS_PER_LONG - 1); 83 84 return GENMASK(largest_offset_shift, offset_shift); 85 } 86 87 /* 88 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 89 * page_offset_quantized * (page_size/scale) = page_offset 90 * Which restricts allowed page sizes to ones that satisify the above. 91 */ 92 unsigned long __mlx5_umem_find_best_quantized_pgoff( 93 struct ib_umem *umem, unsigned long pgsz_bitmap, 94 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 95 unsigned int *page_offset_quantized); 96 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 97 pgsz_shift, page_offset_fld, \ 98 scale, page_offset_quantized) \ 99 __mlx5_umem_find_best_quantized_pgoff( \ 100 umem, \ 101 __mlx5_log_page_size_to_bitmap( \ 102 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 103 __mlx5_bit_sz(typ, page_offset_fld), \ 104 GENMASK(31, order_base_2(scale)), scale, \ 105 page_offset_quantized) 106 107 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 108 pgsz_shift, page_offset_fld, \ 109 scale, page_offset_quantized) \ 110 __mlx5_umem_find_best_quantized_pgoff( \ 111 umem, \ 112 __mlx5_log_page_size_to_bitmap( \ 113 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 114 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 115 page_offset_quantized) 116 117 enum { 118 MLX5_IB_MMAP_OFFSET_START = 9, 119 MLX5_IB_MMAP_OFFSET_END = 255, 120 }; 121 122 enum { 123 MLX5_IB_MMAP_CMD_SHIFT = 8, 124 MLX5_IB_MMAP_CMD_MASK = 0xff, 125 }; 126 127 enum { 128 MLX5_RES_SCAT_DATA32_CQE = 0x1, 129 MLX5_RES_SCAT_DATA64_CQE = 0x2, 130 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 131 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 132 }; 133 134 enum mlx5_ib_mad_ifc_flags { 135 MLX5_MAD_IFC_IGNORE_MKEY = 1, 136 MLX5_MAD_IFC_IGNORE_BKEY = 2, 137 MLX5_MAD_IFC_NET_VIEW = 4, 138 }; 139 140 enum { 141 MLX5_CROSS_CHANNEL_BFREG = 0, 142 }; 143 144 enum { 145 MLX5_CQE_VERSION_V0, 146 MLX5_CQE_VERSION_V1, 147 }; 148 149 enum { 150 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 151 MLX5_TM_MAX_SGE = 1, 152 }; 153 154 enum { 155 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 156 MLX5_IB_INVALID_BFREG = BIT(31), 157 }; 158 159 enum { 160 MLX5_MAX_MEMIC_PAGES = 0x100, 161 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 162 }; 163 164 enum { 165 MLX5_MEMIC_BASE_ALIGN = 6, 166 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 167 }; 168 169 enum mlx5_ib_mmap_type { 170 MLX5_IB_MMAP_TYPE_MEMIC = 1, 171 MLX5_IB_MMAP_TYPE_VAR = 2, 172 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 173 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 174 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 175 }; 176 177 struct mlx5_bfreg_info { 178 u32 *sys_pages; 179 int num_low_latency_bfregs; 180 unsigned int *count; 181 182 /* 183 * protect bfreg allocation data structs 184 */ 185 struct mutex lock; 186 u32 ver; 187 u8 lib_uar_4k : 1; 188 u8 lib_uar_dyn : 1; 189 u32 num_sys_pages; 190 u32 num_static_sys_pages; 191 u32 total_num_bfregs; 192 u32 num_dyn_bfregs; 193 }; 194 195 struct mlx5_ib_ucontext { 196 struct ib_ucontext ibucontext; 197 struct list_head db_page_list; 198 199 /* protect doorbell record alloc/free 200 */ 201 struct mutex db_page_mutex; 202 struct mlx5_bfreg_info bfregi; 203 u8 cqe_version; 204 /* Transport Domain number */ 205 u32 tdn; 206 207 u64 lib_caps; 208 u16 devx_uid; 209 /* For RoCE LAG TX affinity */ 210 atomic_t tx_port_affinity; 211 }; 212 213 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 214 { 215 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 216 } 217 218 struct mlx5_ib_pd { 219 struct ib_pd ibpd; 220 u32 pdn; 221 u16 uid; 222 }; 223 224 enum { 225 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 226 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 227 MLX5_IB_FLOW_ACTION_DECAP, 228 }; 229 230 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 231 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 232 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 233 #error "Invalid number of bypass priorities" 234 #endif 235 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 236 237 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 238 #define MLX5_IB_NUM_SNIFFER_FTS 2 239 #define MLX5_IB_NUM_EGRESS_FTS 1 240 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 241 242 struct mlx5_ib_anchor { 243 struct mlx5_flow_table *ft; 244 struct mlx5_flow_group *fg_goto_table; 245 struct mlx5_flow_group *fg_drop; 246 struct mlx5_flow_handle *rule_goto_table; 247 struct mlx5_flow_handle *rule_drop; 248 unsigned int rule_goto_table_ref; 249 }; 250 251 struct mlx5_ib_flow_prio { 252 struct mlx5_flow_table *flow_table; 253 struct mlx5_ib_anchor anchor; 254 unsigned int refcount; 255 }; 256 257 struct mlx5_ib_flow_handler { 258 struct list_head list; 259 struct ib_flow ibflow; 260 struct mlx5_ib_flow_prio *prio; 261 struct mlx5_flow_handle *rule; 262 struct ib_counters *ibcounters; 263 struct mlx5_ib_dev *dev; 264 struct mlx5_ib_flow_matcher *flow_matcher; 265 }; 266 267 struct mlx5_ib_flow_matcher { 268 struct mlx5_ib_match_params matcher_mask; 269 int mask_len; 270 enum mlx5_ib_flow_type flow_type; 271 enum mlx5_flow_namespace_type ns_type; 272 u16 priority; 273 struct mlx5_core_dev *mdev; 274 atomic_t usecnt; 275 u8 match_criteria_enable; 276 }; 277 278 struct mlx5_ib_steering_anchor { 279 struct mlx5_ib_flow_prio *ft_prio; 280 struct mlx5_ib_dev *dev; 281 atomic_t usecnt; 282 }; 283 284 struct mlx5_ib_pp { 285 u16 index; 286 struct mlx5_core_dev *mdev; 287 }; 288 289 enum mlx5_ib_optional_counter_type { 290 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 291 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 292 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 293 294 MLX5_IB_OPCOUNTER_MAX, 295 }; 296 297 struct mlx5_ib_flow_db { 298 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 299 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 300 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 301 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 302 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 303 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 304 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 305 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 306 struct mlx5_flow_table *lag_demux_ft; 307 /* Protect flow steering bypass flow tables 308 * when add/del flow rules. 309 * only single add/removal of flow steering rule could be done 310 * simultaneously. 311 */ 312 struct mutex lock; 313 }; 314 315 /* Use macros here so that don't have to duplicate 316 * enum ib_qp_type for low-level driver 317 */ 318 319 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 320 /* 321 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 322 * creates the actual hardware QP. 323 */ 324 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 325 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 326 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 327 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 328 329 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 330 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 331 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 332 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 333 #define MLX5_IB_UPD_XLT_PD BIT(4) 334 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 335 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 336 337 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 338 * 339 * These flags are intended for internal use by the mlx5_ib driver, and they 340 * rely on the range reserved for that use in the ib_qp_create_flags enum. 341 */ 342 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 343 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 344 345 struct wr_list { 346 u16 opcode; 347 u16 next; 348 }; 349 350 enum mlx5_ib_rq_flags { 351 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 352 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 353 }; 354 355 struct mlx5_ib_wq { 356 struct mlx5_frag_buf_ctrl fbc; 357 u64 *wrid; 358 u32 *wr_data; 359 struct wr_list *w_list; 360 unsigned *wqe_head; 361 u16 unsig_count; 362 363 /* serialize post to the work queue 364 */ 365 spinlock_t lock; 366 int wqe_cnt; 367 int max_post; 368 int max_gs; 369 int offset; 370 int wqe_shift; 371 unsigned head; 372 unsigned tail; 373 u16 cur_post; 374 u16 last_poll; 375 void *cur_edge; 376 }; 377 378 enum mlx5_ib_wq_flags { 379 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 380 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 381 }; 382 383 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 384 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 385 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 386 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 387 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 388 389 struct mlx5_ib_rwq { 390 struct ib_wq ibwq; 391 struct mlx5_core_qp core_qp; 392 u32 rq_num_pas; 393 u32 log_rq_stride; 394 u32 log_rq_size; 395 u32 rq_page_offset; 396 u32 log_page_size; 397 u32 log_num_strides; 398 u32 two_byte_shift_en; 399 u32 single_stride_log_num_of_bytes; 400 struct ib_umem *umem; 401 size_t buf_size; 402 unsigned int page_shift; 403 struct mlx5_db db; 404 u32 user_index; 405 u32 wqe_count; 406 u32 wqe_shift; 407 int wq_sig; 408 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 409 }; 410 411 struct mlx5_ib_rwq_ind_table { 412 struct ib_rwq_ind_table ib_rwq_ind_tbl; 413 u32 rqtn; 414 u16 uid; 415 }; 416 417 struct mlx5_ib_ubuffer { 418 struct ib_umem *umem; 419 int buf_size; 420 u64 buf_addr; 421 }; 422 423 struct mlx5_ib_qp_base { 424 struct mlx5_ib_qp *container_mibqp; 425 struct mlx5_core_qp mqp; 426 struct mlx5_ib_ubuffer ubuffer; 427 }; 428 429 struct mlx5_ib_qp_trans { 430 struct mlx5_ib_qp_base base; 431 u16 xrcdn; 432 u32 alt_port; 433 u8 atomic_rd_en; 434 u8 resp_depth; 435 }; 436 437 struct mlx5_ib_rss_qp { 438 u32 tirn; 439 }; 440 441 struct mlx5_ib_rq { 442 struct mlx5_ib_qp_base base; 443 struct mlx5_ib_wq *rq; 444 struct mlx5_ib_ubuffer ubuffer; 445 struct mlx5_db *doorbell; 446 u32 tirn; 447 u8 state; 448 u32 flags; 449 }; 450 451 struct mlx5_ib_sq { 452 struct mlx5_ib_qp_base base; 453 struct mlx5_ib_wq *sq; 454 struct mlx5_ib_ubuffer ubuffer; 455 struct mlx5_db *doorbell; 456 struct mlx5_flow_handle *flow_rule; 457 u32 tisn; 458 u8 state; 459 }; 460 461 struct mlx5_ib_raw_packet_qp { 462 struct mlx5_ib_sq sq; 463 struct mlx5_ib_rq rq; 464 }; 465 466 struct mlx5_bf { 467 int buf_size; 468 unsigned long offset; 469 struct mlx5_sq_bfreg *bfreg; 470 }; 471 472 struct mlx5_ib_dct { 473 struct mlx5_core_dct mdct; 474 u32 *in; 475 }; 476 477 struct mlx5_ib_gsi_qp { 478 struct ib_qp *rx_qp; 479 u32 port_num; 480 struct ib_qp_cap cap; 481 struct ib_cq *cq; 482 struct mlx5_ib_gsi_wr *outstanding_wrs; 483 u32 outstanding_pi, outstanding_ci; 484 int num_qps; 485 /* Protects access to the tx_qps. Post send operations synchronize 486 * with tx_qp creation in setup_qp(). Also protects the 487 * outstanding_wrs array and indices. 488 */ 489 spinlock_t lock; 490 struct ib_qp **tx_qps; 491 }; 492 493 struct mlx5_ib_qp { 494 struct ib_qp ibqp; 495 union { 496 struct mlx5_ib_qp_trans trans_qp; 497 struct mlx5_ib_raw_packet_qp raw_packet_qp; 498 struct mlx5_ib_rss_qp rss_qp; 499 struct mlx5_ib_dct dct; 500 struct mlx5_ib_gsi_qp gsi; 501 }; 502 struct mlx5_frag_buf buf; 503 504 struct mlx5_db db; 505 struct mlx5_ib_wq rq; 506 507 u8 sq_signal_bits; 508 u8 next_fence; 509 struct mlx5_ib_wq sq; 510 511 /* serialize qp state modifications 512 */ 513 struct mutex mutex; 514 /* cached variant of create_flags from struct ib_qp_init_attr */ 515 u32 flags; 516 u32 port; 517 u8 state; 518 int max_inline_data; 519 struct mlx5_bf bf; 520 u8 has_rq:1; 521 u8 is_rss:1; 522 523 /* only for user space QPs. For kernel 524 * we have it from the bf object 525 */ 526 int bfregn; 527 528 struct list_head qps_list; 529 struct list_head cq_recv_list; 530 struct list_head cq_send_list; 531 struct mlx5_rate_limit rl; 532 u32 underlay_qpn; 533 u32 flags_en; 534 /* 535 * IB/core doesn't store low-level QP types, so 536 * store both MLX and IBTA types in the field below. 537 */ 538 enum ib_qp_type type; 539 /* A flag to indicate if there's a new counter is configured 540 * but not take effective 541 */ 542 u32 counter_pending; 543 u16 gsi_lag_port; 544 }; 545 546 struct mlx5_ib_cq_buf { 547 struct mlx5_frag_buf_ctrl fbc; 548 struct mlx5_frag_buf frag_buf; 549 struct ib_umem *umem; 550 int cqe_size; 551 int nent; 552 }; 553 554 enum mlx5_ib_cq_pr_flags { 555 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 556 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 557 }; 558 559 struct mlx5_ib_cq { 560 struct ib_cq ibcq; 561 struct mlx5_core_cq mcq; 562 struct mlx5_ib_cq_buf buf; 563 struct mlx5_db db; 564 565 /* serialize access to the CQ 566 */ 567 spinlock_t lock; 568 569 /* protect resize cq 570 */ 571 struct mutex resize_mutex; 572 struct mlx5_ib_cq_buf *resize_buf; 573 struct ib_umem *resize_umem; 574 int cqe_size; 575 struct list_head list_send_qp; 576 struct list_head list_recv_qp; 577 u32 create_flags; 578 struct list_head wc_list; 579 enum ib_cq_notify_flags notify_flags; 580 struct work_struct notify_work; 581 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 582 }; 583 584 struct mlx5_ib_wc { 585 struct ib_wc wc; 586 struct list_head list; 587 }; 588 589 struct mlx5_ib_srq { 590 struct ib_srq ibsrq; 591 struct mlx5_core_srq msrq; 592 struct mlx5_frag_buf buf; 593 struct mlx5_db db; 594 struct mlx5_frag_buf_ctrl fbc; 595 u64 *wrid; 596 /* protect SRQ hanlding 597 */ 598 spinlock_t lock; 599 int head; 600 int tail; 601 u16 wqe_ctr; 602 struct ib_umem *umem; 603 /* serialize arming a SRQ 604 */ 605 struct mutex mutex; 606 int wq_sig; 607 }; 608 609 struct mlx5_ib_xrcd { 610 struct ib_xrcd ibxrcd; 611 u32 xrcdn; 612 }; 613 614 enum mlx5_ib_mtt_access_flags { 615 MLX5_IB_MTT_READ = (1 << 0), 616 MLX5_IB_MTT_WRITE = (1 << 1), 617 }; 618 619 struct mlx5_user_mmap_entry { 620 struct rdma_user_mmap_entry rdma_entry; 621 u8 mmap_flag; 622 u64 address; 623 u32 page_idx; 624 }; 625 626 enum mlx5_mkey_type { 627 MLX5_MKEY_MR = 1, 628 MLX5_MKEY_MW, 629 MLX5_MKEY_INDIRECT_DEVX, 630 }; 631 632 struct mlx5r_cache_rb_key { 633 u8 ats:1; 634 unsigned int access_mode; 635 unsigned int access_flags; 636 unsigned int ndescs; 637 }; 638 639 struct mlx5_ib_mkey { 640 u32 key; 641 enum mlx5_mkey_type type; 642 unsigned int ndescs; 643 struct wait_queue_head wait; 644 refcount_t usecount; 645 /* User Mkey must hold either a rb_key or a cache_ent. */ 646 struct mlx5r_cache_rb_key rb_key; 647 struct mlx5_cache_ent *cache_ent; 648 }; 649 650 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 651 652 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 653 IB_ACCESS_REMOTE_WRITE |\ 654 IB_ACCESS_REMOTE_READ |\ 655 IB_ACCESS_REMOTE_ATOMIC |\ 656 IB_ZERO_BASED) 657 658 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 659 IB_ACCESS_REMOTE_WRITE |\ 660 IB_ACCESS_REMOTE_READ |\ 661 IB_ZERO_BASED) 662 663 #define mlx5_update_odp_stats(mr, counter_name, value) \ 664 atomic64_add(value, &((mr)->odp_stats.counter_name)) 665 666 struct mlx5_ib_mr { 667 struct ib_mr ibmr; 668 struct mlx5_ib_mkey mmkey; 669 670 struct ib_umem *umem; 671 672 union { 673 /* Used only by kernel MRs (umem == NULL) */ 674 struct { 675 void *descs; 676 void *descs_alloc; 677 dma_addr_t desc_map; 678 int max_descs; 679 int desc_size; 680 int access_mode; 681 682 /* For Kernel IB_MR_TYPE_INTEGRITY */ 683 struct mlx5_core_sig_ctx *sig; 684 struct mlx5_ib_mr *pi_mr; 685 struct mlx5_ib_mr *klm_mr; 686 struct mlx5_ib_mr *mtt_mr; 687 u64 data_iova; 688 u64 pi_iova; 689 int meta_ndescs; 690 int meta_length; 691 int data_length; 692 }; 693 694 /* Used only by User MRs (umem != NULL) */ 695 struct { 696 unsigned int page_shift; 697 /* Current access_flags */ 698 int access_flags; 699 700 /* For User ODP */ 701 struct mlx5_ib_mr *parent; 702 struct xarray implicit_children; 703 union { 704 struct work_struct work; 705 } odp_destroy; 706 struct ib_odp_counters odp_stats; 707 bool is_odp_implicit; 708 }; 709 }; 710 }; 711 712 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 713 { 714 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 715 mr->umem->is_odp; 716 } 717 718 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 719 { 720 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 721 mr->umem->is_dmabuf; 722 } 723 724 struct mlx5_ib_mw { 725 struct ib_mw ibmw; 726 struct mlx5_ib_mkey mmkey; 727 }; 728 729 struct mlx5_ib_umr_context { 730 struct ib_cqe cqe; 731 enum ib_wc_status status; 732 struct completion done; 733 }; 734 735 enum { 736 MLX5_UMR_STATE_UNINIT, 737 MLX5_UMR_STATE_ACTIVE, 738 MLX5_UMR_STATE_RECOVER, 739 MLX5_UMR_STATE_ERR, 740 }; 741 742 struct umr_common { 743 struct ib_pd *pd; 744 struct ib_cq *cq; 745 struct ib_qp *qp; 746 /* Protects from UMR QP overflow 747 */ 748 struct semaphore sem; 749 /* Protects from using UMR while the UMR is not active 750 */ 751 struct mutex lock; 752 unsigned int state; 753 }; 754 755 struct mlx5_cache_ent { 756 struct xarray mkeys; 757 unsigned long stored; 758 unsigned long reserved; 759 760 char name[4]; 761 762 struct rb_node node; 763 struct mlx5r_cache_rb_key rb_key; 764 765 u8 is_tmp:1; 766 u8 disabled:1; 767 u8 fill_to_high_water:1; 768 769 /* 770 * - limit is the low water mark for stored mkeys, 2* limit is the 771 * upper water mark. 772 */ 773 u32 in_use; 774 u32 limit; 775 776 /* Statistics */ 777 u32 miss; 778 779 struct mlx5_ib_dev *dev; 780 struct delayed_work dwork; 781 }; 782 783 struct mlx5r_async_create_mkey { 784 union { 785 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 786 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 787 }; 788 struct mlx5_async_work cb_work; 789 struct mlx5_cache_ent *ent; 790 u32 mkey; 791 }; 792 793 struct mlx5_mkey_cache { 794 struct workqueue_struct *wq; 795 struct rb_root rb_root; 796 struct mutex rb_lock; 797 struct dentry *fs_root; 798 unsigned long last_add; 799 struct delayed_work remove_ent_dwork; 800 }; 801 802 struct mlx5_ib_port_resources { 803 struct mlx5_ib_gsi_qp *gsi; 804 struct work_struct pkey_change_work; 805 }; 806 807 struct mlx5_ib_resources { 808 struct ib_cq *c0; 809 u32 xrcdn0; 810 u32 xrcdn1; 811 struct ib_pd *p0; 812 struct ib_srq *s0; 813 struct ib_srq *s1; 814 struct mlx5_ib_port_resources ports[2]; 815 }; 816 817 #define MAX_OPFC_RULES 2 818 819 struct mlx5_ib_op_fc { 820 struct mlx5_fc *fc; 821 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 822 }; 823 824 struct mlx5_ib_counters { 825 struct rdma_stat_desc *descs; 826 size_t *offsets; 827 u32 num_q_counters; 828 u32 num_cong_counters; 829 u32 num_ext_ppcnt_counters; 830 u32 num_op_counters; 831 u16 set_id; 832 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 833 }; 834 835 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 836 struct mlx5_ib_op_fc *opfc, 837 enum mlx5_ib_optional_counter_type type); 838 839 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 840 struct mlx5_ib_op_fc *opfc, 841 enum mlx5_ib_optional_counter_type type); 842 843 struct mlx5_ib_multiport_info; 844 845 struct mlx5_ib_multiport { 846 struct mlx5_ib_multiport_info *mpi; 847 /* To be held when accessing the multiport info */ 848 spinlock_t mpi_lock; 849 }; 850 851 struct mlx5_roce { 852 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 853 * netdev pointer 854 */ 855 rwlock_t netdev_lock; 856 struct net_device *netdev; 857 struct notifier_block nb; 858 struct netdev_net_notifier nn; 859 struct notifier_block mdev_nb; 860 struct net_device *tracking_netdev; 861 atomic_t tx_port_affinity; 862 enum ib_port_state last_port_state; 863 struct mlx5_ib_dev *dev; 864 u32 native_port_num; 865 }; 866 867 struct mlx5_ib_port { 868 struct mlx5_ib_counters cnts; 869 struct mlx5_ib_multiport mp; 870 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 871 struct mlx5_roce roce; 872 struct mlx5_eswitch_rep *rep; 873 }; 874 875 struct mlx5_ib_dbg_param { 876 int offset; 877 struct mlx5_ib_dev *dev; 878 struct dentry *dentry; 879 u32 port_num; 880 }; 881 882 enum mlx5_ib_dbg_cc_types { 883 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 884 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 885 MLX5_IB_DBG_CC_RP_TIME_RESET, 886 MLX5_IB_DBG_CC_RP_BYTE_RESET, 887 MLX5_IB_DBG_CC_RP_THRESHOLD, 888 MLX5_IB_DBG_CC_RP_AI_RATE, 889 MLX5_IB_DBG_CC_RP_MAX_RATE, 890 MLX5_IB_DBG_CC_RP_HAI_RATE, 891 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 892 MLX5_IB_DBG_CC_RP_MIN_RATE, 893 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 894 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 895 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 896 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 897 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 898 MLX5_IB_DBG_CC_RP_GD, 899 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 900 MLX5_IB_DBG_CC_NP_CNP_DSCP, 901 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 902 MLX5_IB_DBG_CC_NP_CNP_PRIO, 903 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 904 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 905 MLX5_IB_DBG_CC_MAX, 906 }; 907 908 struct mlx5_ib_dbg_cc_params { 909 struct dentry *root; 910 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 911 }; 912 913 enum { 914 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 915 }; 916 917 struct mlx5_ib_delay_drop { 918 struct mlx5_ib_dev *dev; 919 struct work_struct delay_drop_work; 920 /* serialize setting of delay drop */ 921 struct mutex lock; 922 u32 timeout; 923 bool activate; 924 atomic_t events_cnt; 925 atomic_t rqs_cnt; 926 struct dentry *dir_debugfs; 927 }; 928 929 enum mlx5_ib_stages { 930 MLX5_IB_STAGE_INIT, 931 MLX5_IB_STAGE_FS, 932 MLX5_IB_STAGE_CAPS, 933 MLX5_IB_STAGE_NON_DEFAULT_CB, 934 MLX5_IB_STAGE_ROCE, 935 MLX5_IB_STAGE_QP, 936 MLX5_IB_STAGE_SRQ, 937 MLX5_IB_STAGE_DEVICE_RESOURCES, 938 MLX5_IB_STAGE_DEVICE_NOTIFIER, 939 MLX5_IB_STAGE_ODP, 940 MLX5_IB_STAGE_COUNTERS, 941 MLX5_IB_STAGE_CONG_DEBUGFS, 942 MLX5_IB_STAGE_UAR, 943 MLX5_IB_STAGE_BFREG, 944 MLX5_IB_STAGE_PRE_IB_REG_UMR, 945 MLX5_IB_STAGE_WHITELIST_UID, 946 MLX5_IB_STAGE_IB_REG, 947 MLX5_IB_STAGE_POST_IB_REG_UMR, 948 MLX5_IB_STAGE_DELAY_DROP, 949 MLX5_IB_STAGE_RESTRACK, 950 MLX5_IB_STAGE_MAX, 951 }; 952 953 struct mlx5_ib_stage { 954 int (*init)(struct mlx5_ib_dev *dev); 955 void (*cleanup)(struct mlx5_ib_dev *dev); 956 }; 957 958 #define STAGE_CREATE(_stage, _init, _cleanup) \ 959 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 960 961 struct mlx5_ib_profile { 962 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 963 }; 964 965 struct mlx5_ib_multiport_info { 966 struct list_head list; 967 struct mlx5_ib_dev *ibdev; 968 struct mlx5_core_dev *mdev; 969 struct notifier_block mdev_events; 970 struct completion unref_comp; 971 u64 sys_image_guid; 972 u32 mdev_refcnt; 973 bool is_master; 974 bool unaffiliate; 975 }; 976 977 struct mlx5_ib_flow_action { 978 struct ib_flow_action ib_action; 979 union { 980 struct { 981 u64 ib_flags; 982 struct mlx5_accel_esp_xfrm *ctx; 983 } esp_aes_gcm; 984 struct { 985 struct mlx5_ib_dev *dev; 986 u32 sub_type; 987 union { 988 struct mlx5_modify_hdr *modify_hdr; 989 struct mlx5_pkt_reformat *pkt_reformat; 990 }; 991 } flow_action_raw; 992 }; 993 }; 994 995 struct mlx5_dm { 996 struct mlx5_core_dev *dev; 997 /* This lock is used to protect the access to the shared 998 * allocation map when concurrent requests by different 999 * processes are handled. 1000 */ 1001 spinlock_t lock; 1002 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 1003 }; 1004 1005 struct mlx5_read_counters_attr { 1006 struct mlx5_fc *hw_cntrs_hndl; 1007 u64 *out; 1008 u32 flags; 1009 }; 1010 1011 enum mlx5_ib_counters_type { 1012 MLX5_IB_COUNTERS_FLOW, 1013 }; 1014 1015 struct mlx5_ib_mcounters { 1016 struct ib_counters ibcntrs; 1017 enum mlx5_ib_counters_type type; 1018 /* number of counters supported for this counters type */ 1019 u32 counters_num; 1020 struct mlx5_fc *hw_cntrs_hndl; 1021 /* read function for this counters type */ 1022 int (*read_counters)(struct ib_device *ibdev, 1023 struct mlx5_read_counters_attr *read_attr); 1024 /* max index set as part of create_flow */ 1025 u32 cntrs_max_index; 1026 /* number of counters data entries (<description,index> pair) */ 1027 u32 ncounters; 1028 /* counters data array for descriptions and indexes */ 1029 struct mlx5_ib_flow_counters_desc *counters_data; 1030 /* protects access to mcounters internal data */ 1031 struct mutex mcntrs_mutex; 1032 }; 1033 1034 static inline struct mlx5_ib_mcounters * 1035 to_mcounters(struct ib_counters *ibcntrs) 1036 { 1037 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1038 } 1039 1040 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1041 bool is_egress, 1042 struct mlx5_flow_act *action); 1043 struct mlx5_ib_lb_state { 1044 /* protect the user_td */ 1045 struct mutex mutex; 1046 u32 user_td; 1047 int qps; 1048 bool enabled; 1049 }; 1050 1051 struct mlx5_ib_pf_eq { 1052 struct notifier_block irq_nb; 1053 struct mlx5_ib_dev *dev; 1054 struct mlx5_eq *core; 1055 struct work_struct work; 1056 spinlock_t lock; /* Pagefaults spinlock */ 1057 struct workqueue_struct *wq; 1058 mempool_t *pool; 1059 }; 1060 1061 struct mlx5_devx_event_table { 1062 struct mlx5_nb devx_nb; 1063 /* serialize updating the event_xa */ 1064 struct mutex event_xa_lock; 1065 struct xarray event_xa; 1066 }; 1067 1068 struct mlx5_var_table { 1069 /* serialize updating the bitmap */ 1070 struct mutex bitmap_lock; 1071 unsigned long *bitmap; 1072 u64 hw_start_addr; 1073 u32 stride_size; 1074 u64 num_var_hw_entries; 1075 }; 1076 1077 struct mlx5_port_caps { 1078 bool has_smi; 1079 u8 ext_port_cap; 1080 }; 1081 1082 1083 struct mlx5_special_mkeys { 1084 u32 dump_fill_mkey; 1085 __be32 null_mkey; 1086 __be32 terminate_scatter_list_mkey; 1087 }; 1088 1089 struct mlx5_ib_dev { 1090 struct ib_device ib_dev; 1091 struct mlx5_core_dev *mdev; 1092 struct notifier_block mdev_events; 1093 int num_ports; 1094 /* serialize update of capability mask 1095 */ 1096 struct mutex cap_mask_mutex; 1097 u8 ib_active:1; 1098 u8 is_rep:1; 1099 u8 lag_active:1; 1100 u8 wc_support:1; 1101 u8 fill_delay; 1102 struct umr_common umrc; 1103 /* sync used page count stats 1104 */ 1105 struct mlx5_ib_resources devr; 1106 1107 atomic_t mkey_var; 1108 struct mlx5_mkey_cache cache; 1109 struct timer_list delay_timer; 1110 /* Prevents soft lock on massive reg MRs */ 1111 struct mutex slow_path_mutex; 1112 struct ib_odp_caps odp_caps; 1113 u64 odp_max_size; 1114 struct mutex odp_eq_mutex; 1115 struct mlx5_ib_pf_eq odp_pf_eq; 1116 1117 struct xarray odp_mkeys; 1118 1119 struct mlx5_ib_flow_db *flow_db; 1120 /* protect resources needed as part of reset flow */ 1121 spinlock_t reset_flow_resource_lock; 1122 struct list_head qp_list; 1123 /* Array with num_ports elements */ 1124 struct mlx5_ib_port *port; 1125 struct mlx5_sq_bfreg bfreg; 1126 struct mlx5_sq_bfreg wc_bfreg; 1127 struct mlx5_sq_bfreg fp_bfreg; 1128 struct mlx5_ib_delay_drop delay_drop; 1129 const struct mlx5_ib_profile *profile; 1130 1131 struct mlx5_ib_lb_state lb; 1132 u8 umr_fence; 1133 struct list_head ib_dev_list; 1134 u64 sys_image_guid; 1135 struct mlx5_dm dm; 1136 u16 devx_whitelist_uid; 1137 struct mlx5_srq_table srq_table; 1138 struct mlx5_qp_table qp_table; 1139 struct mlx5_async_ctx async_ctx; 1140 struct mlx5_devx_event_table devx_event_table; 1141 struct mlx5_var_table var_table; 1142 1143 struct xarray sig_mrs; 1144 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1145 u16 pkey_table_len; 1146 u8 lag_ports; 1147 struct mlx5_special_mkeys mkeys; 1148 }; 1149 1150 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1151 { 1152 return container_of(mcq, struct mlx5_ib_cq, mcq); 1153 } 1154 1155 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1156 { 1157 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1158 } 1159 1160 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1161 { 1162 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1163 } 1164 1165 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1166 { 1167 return to_mdev(mr->ibmr.device); 1168 } 1169 1170 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1171 { 1172 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1173 udata, struct mlx5_ib_ucontext, ibucontext); 1174 1175 return to_mdev(context->ibucontext.device); 1176 } 1177 1178 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1179 { 1180 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1181 } 1182 1183 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1184 { 1185 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1186 } 1187 1188 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1189 { 1190 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1191 } 1192 1193 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1194 { 1195 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1196 } 1197 1198 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1199 { 1200 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1201 } 1202 1203 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1204 { 1205 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1206 } 1207 1208 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1209 { 1210 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1211 } 1212 1213 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1214 { 1215 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1216 } 1217 1218 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1219 { 1220 return container_of(msrq, struct mlx5_ib_srq, msrq); 1221 } 1222 1223 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1224 { 1225 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1226 } 1227 1228 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1229 { 1230 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1231 } 1232 1233 static inline struct mlx5_ib_flow_action * 1234 to_mflow_act(struct ib_flow_action *ibact) 1235 { 1236 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1237 } 1238 1239 static inline struct mlx5_user_mmap_entry * 1240 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1241 { 1242 return container_of(rdma_entry, 1243 struct mlx5_user_mmap_entry, rdma_entry); 1244 } 1245 1246 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1247 struct mlx5_db *db); 1248 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1249 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1250 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1251 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1252 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1253 struct ib_udata *udata); 1254 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1255 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1256 { 1257 return 0; 1258 } 1259 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1260 struct ib_udata *udata); 1261 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1262 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1263 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1264 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1265 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1266 const struct ib_recv_wr **bad_wr); 1267 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1268 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1269 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1270 struct ib_udata *udata); 1271 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1272 int attr_mask, struct ib_udata *udata); 1273 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1274 struct ib_qp_init_attr *qp_init_attr); 1275 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1276 void mlx5_ib_drain_sq(struct ib_qp *qp); 1277 void mlx5_ib_drain_rq(struct ib_qp *qp); 1278 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1279 size_t buflen, size_t *bc); 1280 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1281 size_t buflen, size_t *bc); 1282 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1283 size_t buflen, size_t *bc); 1284 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1285 struct ib_udata *udata); 1286 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1287 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1288 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1289 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1290 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1291 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1292 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1293 u64 virt_addr, int access_flags, 1294 struct ib_udata *udata); 1295 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1296 u64 length, u64 virt_addr, 1297 int fd, int access_flags, 1298 struct ib_udata *udata); 1299 int mlx5_ib_advise_mr(struct ib_pd *pd, 1300 enum ib_uverbs_advise_mr_advice advice, 1301 u32 flags, 1302 struct ib_sge *sg_list, 1303 u32 num_sge, 1304 struct uverbs_attr_bundle *attrs); 1305 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1306 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1307 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1308 int access_flags); 1309 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1310 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1311 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1312 u64 length, u64 virt_addr, int access_flags, 1313 struct ib_pd *pd, struct ib_udata *udata); 1314 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1315 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1316 u32 max_num_sg); 1317 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1318 u32 max_num_sg, 1319 u32 max_num_meta_sg); 1320 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1321 unsigned int *sg_offset); 1322 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1323 int data_sg_nents, unsigned int *data_sg_offset, 1324 struct scatterlist *meta_sg, int meta_sg_nents, 1325 unsigned int *meta_sg_offset); 1326 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1327 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1328 const struct ib_mad *in, struct ib_mad *out, 1329 size_t *out_mad_size, u16 *out_mad_pkey_index); 1330 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1331 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1332 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1333 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1334 __be64 *sys_image_guid); 1335 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1336 u16 *max_pkeys); 1337 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1338 u32 *vendor_id); 1339 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1340 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1341 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1342 u16 *pkey); 1343 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1344 union ib_gid *gid); 1345 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1346 struct ib_port_attr *props); 1347 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1348 struct ib_port_attr *props); 1349 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1350 u64 access_flags); 1351 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1352 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1353 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1354 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1355 struct mlx5_cache_ent * 1356 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 1357 struct mlx5r_cache_rb_key rb_key, 1358 bool persistent_entry); 1359 1360 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1361 int access_flags, int access_mode, 1362 int ndescs); 1363 1364 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1365 struct ib_mr_status *mr_status); 1366 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1367 struct ib_wq_init_attr *init_attr, 1368 struct ib_udata *udata); 1369 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1370 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1371 u32 wq_attr_mask, struct ib_udata *udata); 1372 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1373 struct ib_rwq_ind_table_init_attr *init_attr, 1374 struct ib_udata *udata); 1375 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1376 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1377 struct ib_dm_mr_attr *attr, 1378 struct uverbs_attr_bundle *attrs); 1379 1380 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1381 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1382 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1383 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1384 int __init mlx5_ib_odp_init(void); 1385 void mlx5_ib_odp_cleanup(void); 1386 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1387 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1388 struct mlx5_ib_mr *mr, int flags); 1389 1390 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1391 enum ib_uverbs_advise_mr_advice advice, 1392 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1393 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1394 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1395 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1396 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1397 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1398 struct mlx5_ib_pf_eq *eq) 1399 { 1400 return 0; 1401 } 1402 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1403 static inline int mlx5_ib_odp_init(void) { return 0; } 1404 static inline void mlx5_ib_odp_cleanup(void) {} 1405 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1406 { 1407 return 0; 1408 } 1409 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1410 struct mlx5_ib_mr *mr, int flags) {} 1411 1412 static inline int 1413 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1414 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1415 struct ib_sge *sg_list, u32 num_sge) 1416 { 1417 return -EOPNOTSUPP; 1418 } 1419 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1420 { 1421 return -EOPNOTSUPP; 1422 } 1423 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1424 { 1425 return -EOPNOTSUPP; 1426 } 1427 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1428 1429 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1430 1431 /* Needed for rep profile */ 1432 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1433 const struct mlx5_ib_profile *profile, 1434 int stage); 1435 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1436 const struct mlx5_ib_profile *profile); 1437 1438 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1439 u32 port, struct ifla_vf_info *info); 1440 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1441 u32 port, int state); 1442 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1443 u32 port, struct ifla_vf_stats *stats); 1444 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1445 struct ifla_vf_guid *node_guid, 1446 struct ifla_vf_guid *port_guid); 1447 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1448 u64 guid, int type); 1449 1450 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1451 const struct ib_gid_attr *attr); 1452 1453 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1454 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1455 1456 /* GSI QP helper functions */ 1457 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1458 struct ib_qp_init_attr *attr); 1459 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1460 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1461 int attr_mask); 1462 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1463 int qp_attr_mask, 1464 struct ib_qp_init_attr *qp_init_attr); 1465 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1466 const struct ib_send_wr **bad_wr); 1467 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1468 const struct ib_recv_wr **bad_wr); 1469 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1470 1471 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1472 1473 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1474 int bfregn); 1475 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1476 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1477 u32 ib_port_num, 1478 u32 *native_port_num); 1479 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1480 u32 port_num); 1481 1482 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1483 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1484 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1485 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1486 1487 static inline int is_qp1(enum ib_qp_type qp_type) 1488 { 1489 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1490 } 1491 1492 static inline u32 check_cq_create_flags(u32 flags) 1493 { 1494 /* 1495 * It returns non-zero value for unsupported CQ 1496 * create flags, otherwise it returns zero. 1497 */ 1498 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1499 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1500 } 1501 1502 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1503 u32 *user_index) 1504 { 1505 if (cqe_version) { 1506 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1507 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1508 return -EINVAL; 1509 *user_index = cmd_uidx; 1510 } else { 1511 *user_index = MLX5_IB_DEFAULT_UIDX; 1512 } 1513 1514 return 0; 1515 } 1516 1517 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1518 struct mlx5_ib_create_qp *ucmd, 1519 int inlen, 1520 u32 *user_index) 1521 { 1522 u8 cqe_version = ucontext->cqe_version; 1523 1524 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1525 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1526 return 0; 1527 1528 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1529 return -EINVAL; 1530 1531 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1532 } 1533 1534 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1535 struct mlx5_ib_create_srq *ucmd, 1536 int inlen, 1537 u32 *user_index) 1538 { 1539 u8 cqe_version = ucontext->cqe_version; 1540 1541 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1542 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1543 return 0; 1544 1545 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1546 return -EINVAL; 1547 1548 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1549 } 1550 1551 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1552 { 1553 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1554 MLX5_UARS_IN_PAGE : 1; 1555 } 1556 1557 extern void *xlt_emergency_page; 1558 1559 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1560 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1561 bool dyn_bfreg); 1562 1563 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1564 struct mlx5_ib_mkey *mmkey) 1565 { 1566 refcount_set(&mmkey->usecount, 1); 1567 1568 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1569 mmkey, GFP_KERNEL)); 1570 } 1571 1572 /* deref an mkey that can participate in ODP flow */ 1573 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1574 { 1575 if (refcount_dec_and_test(&mmkey->usecount)) 1576 wake_up(&mmkey->wait); 1577 } 1578 1579 /* deref an mkey that can participate in ODP flow and wait for relese */ 1580 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1581 { 1582 mlx5r_deref_odp_mkey(mmkey); 1583 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1584 } 1585 1586 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1587 1588 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1589 { 1590 /* 1591 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1592 * is supported, it means that the driver no longer needs to assign the port 1593 * affinity by default. If a user wants to set the port affinity explicitly, 1594 * the user has a dedicated API to do that, so there is no need to assign 1595 * the port affinity by default. 1596 */ 1597 if (dev->lag_active && 1598 mlx5_lag_mode_is_hash(dev->mdev) && 1599 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1600 return 0; 1601 1602 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1603 return 0; 1604 1605 return dev->lag_active || 1606 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1607 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1608 } 1609 1610 static inline bool rt_supported(int ts_cap) 1611 { 1612 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1613 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1614 } 1615 1616 /* 1617 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1618 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1619 * root complexes. However if a switch is present in the path, then things get 1620 * really ugly depending on how the switch is setup. This table assumes that the 1621 * root complex is strict and is validating that all req/reps are matches 1622 * perfectly - so any scenario where it sees only half the transaction is a 1623 * failure. 1624 * 1625 * CR/RR/DT ATS RO P2P 1626 * 00X X X OK 1627 * 010 X X fails (request is routed to root but root never sees comp) 1628 * 011 0 X fails (request is routed to root but root never sees comp) 1629 * 011 1 X OK 1630 * 10X X 1 OK 1631 * 101 X 0 fails (completion is routed to root but root didn't see req) 1632 * 110 X 0 SLOW 1633 * 111 0 0 SLOW 1634 * 111 1 0 fails (completion is routed to root but root didn't see req) 1635 * 111 1 1 OK 1636 * 1637 * Unfortunately we cannot reliably know if a switch is present or what the 1638 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1639 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1640 * 1641 * For now assume if the umem is a dma_buf then it is P2P. 1642 */ 1643 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1644 struct ib_umem *umem, int access_flags) 1645 { 1646 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1647 return false; 1648 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1649 } 1650 1651 #endif /* MLX5_IB_H */ 1652