1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 #include <linux/mlx5/transobj.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/mlx5-abi.h> 48 #include <rdma/uverbs_ioctl.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 51 #define mlx5_ib_dbg(dev, format, arg...) \ 52 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 53 __LINE__, current->pid, ##arg) 54 55 #define mlx5_ib_err(dev, format, arg...) \ 56 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_warn(dev, format, arg...) \ 60 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 64 sizeof(((type *)0)->fld) <= (sz)) 65 #define MLX5_IB_DEFAULT_UIDX 0xffffff 66 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 67 68 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 69 70 enum { 71 MLX5_IB_MMAP_CMD_SHIFT = 8, 72 MLX5_IB_MMAP_CMD_MASK = 0xff, 73 }; 74 75 enum { 76 MLX5_RES_SCAT_DATA32_CQE = 0x1, 77 MLX5_RES_SCAT_DATA64_CQE = 0x2, 78 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 79 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 80 }; 81 82 enum mlx5_ib_mad_ifc_flags { 83 MLX5_MAD_IFC_IGNORE_MKEY = 1, 84 MLX5_MAD_IFC_IGNORE_BKEY = 2, 85 MLX5_MAD_IFC_NET_VIEW = 4, 86 }; 87 88 enum { 89 MLX5_CROSS_CHANNEL_BFREG = 0, 90 }; 91 92 enum { 93 MLX5_CQE_VERSION_V0, 94 MLX5_CQE_VERSION_V1, 95 }; 96 97 enum { 98 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 99 MLX5_TM_MAX_SGE = 1, 100 }; 101 102 enum { 103 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 104 MLX5_IB_INVALID_BFREG = BIT(31), 105 }; 106 107 enum { 108 MLX5_MAX_MEMIC_PAGES = 0x100, 109 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 110 }; 111 112 enum { 113 MLX5_MEMIC_BASE_ALIGN = 6, 114 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 115 }; 116 117 struct mlx5_ib_vma_private_data { 118 struct list_head list; 119 struct vm_area_struct *vma; 120 /* protect vma_private_list add/del */ 121 struct mutex *vma_private_list_mutex; 122 }; 123 124 struct mlx5_ib_ucontext { 125 struct ib_ucontext ibucontext; 126 struct list_head db_page_list; 127 128 /* protect doorbell record alloc/free 129 */ 130 struct mutex db_page_mutex; 131 struct mlx5_bfreg_info bfregi; 132 u8 cqe_version; 133 /* Transport Domain number */ 134 u32 tdn; 135 struct list_head vma_private_list; 136 /* protect vma_private_list add/del */ 137 struct mutex vma_private_list_mutex; 138 139 u64 lib_caps; 140 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); 141 u16 devx_uid; 142 }; 143 144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 145 { 146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 147 } 148 149 struct mlx5_ib_pd { 150 struct ib_pd ibpd; 151 u32 pdn; 152 }; 153 154 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 155 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 156 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 157 #error "Invalid number of bypass priorities" 158 #endif 159 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 160 161 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 162 #define MLX5_IB_NUM_SNIFFER_FTS 2 163 #define MLX5_IB_NUM_EGRESS_FTS 1 164 struct mlx5_ib_flow_prio { 165 struct mlx5_flow_table *flow_table; 166 unsigned int refcount; 167 }; 168 169 struct mlx5_ib_flow_handler { 170 struct list_head list; 171 struct ib_flow ibflow; 172 struct mlx5_ib_flow_prio *prio; 173 struct mlx5_flow_handle *rule; 174 struct ib_counters *ibcounters; 175 struct mlx5_ib_dev *dev; 176 struct mlx5_ib_flow_matcher *flow_matcher; 177 }; 178 179 struct mlx5_ib_flow_matcher { 180 struct mlx5_ib_match_params matcher_mask; 181 int mask_len; 182 enum mlx5_ib_flow_type flow_type; 183 u16 priority; 184 struct mlx5_core_dev *mdev; 185 atomic_t usecnt; 186 u8 match_criteria_enable; 187 }; 188 189 struct mlx5_ib_flow_db { 190 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 191 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 192 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 193 struct mlx5_flow_table *lag_demux_ft; 194 /* Protect flow steering bypass flow tables 195 * when add/del flow rules. 196 * only single add/removal of flow steering rule could be done 197 * simultaneously. 198 */ 199 struct mutex lock; 200 }; 201 202 /* Use macros here so that don't have to duplicate 203 * enum ib_send_flags and enum ib_qp_type for low-level driver 204 */ 205 206 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 207 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 208 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 209 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 210 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 211 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 212 213 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 214 /* 215 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 216 * creates the actual hardware QP. 217 */ 218 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 219 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 220 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 221 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 222 223 #define MLX5_IB_UMR_OCTOWORD 16 224 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 225 226 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 227 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 228 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 229 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 230 #define MLX5_IB_UPD_XLT_PD BIT(4) 231 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 232 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 233 234 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 235 * 236 * These flags are intended for internal use by the mlx5_ib driver, and they 237 * rely on the range reserved for that use in the ib_qp_create_flags enum. 238 */ 239 240 /* Create a UD QP whose source QP number is 1 */ 241 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 242 { 243 return IB_QP_CREATE_RESERVED_START; 244 } 245 246 struct wr_list { 247 u16 opcode; 248 u16 next; 249 }; 250 251 enum mlx5_ib_rq_flags { 252 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 253 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 254 }; 255 256 struct mlx5_ib_wq { 257 u64 *wrid; 258 u32 *wr_data; 259 struct wr_list *w_list; 260 unsigned *wqe_head; 261 u16 unsig_count; 262 263 /* serialize post to the work queue 264 */ 265 spinlock_t lock; 266 int wqe_cnt; 267 int max_post; 268 int max_gs; 269 int offset; 270 int wqe_shift; 271 unsigned head; 272 unsigned tail; 273 u16 cur_post; 274 u16 last_poll; 275 void *qend; 276 }; 277 278 enum mlx5_ib_wq_flags { 279 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 280 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 281 }; 282 283 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 284 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 285 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 286 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 287 288 struct mlx5_ib_rwq { 289 struct ib_wq ibwq; 290 struct mlx5_core_qp core_qp; 291 u32 rq_num_pas; 292 u32 log_rq_stride; 293 u32 log_rq_size; 294 u32 rq_page_offset; 295 u32 log_page_size; 296 u32 log_num_strides; 297 u32 two_byte_shift_en; 298 u32 single_stride_log_num_of_bytes; 299 struct ib_umem *umem; 300 size_t buf_size; 301 unsigned int page_shift; 302 int create_type; 303 struct mlx5_db db; 304 u32 user_index; 305 u32 wqe_count; 306 u32 wqe_shift; 307 int wq_sig; 308 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 309 }; 310 311 enum { 312 MLX5_QP_USER, 313 MLX5_QP_KERNEL, 314 MLX5_QP_EMPTY 315 }; 316 317 enum { 318 MLX5_WQ_USER, 319 MLX5_WQ_KERNEL 320 }; 321 322 struct mlx5_ib_rwq_ind_table { 323 struct ib_rwq_ind_table ib_rwq_ind_tbl; 324 u32 rqtn; 325 }; 326 327 struct mlx5_ib_ubuffer { 328 struct ib_umem *umem; 329 int buf_size; 330 u64 buf_addr; 331 }; 332 333 struct mlx5_ib_qp_base { 334 struct mlx5_ib_qp *container_mibqp; 335 struct mlx5_core_qp mqp; 336 struct mlx5_ib_ubuffer ubuffer; 337 }; 338 339 struct mlx5_ib_qp_trans { 340 struct mlx5_ib_qp_base base; 341 u16 xrcdn; 342 u8 alt_port; 343 u8 atomic_rd_en; 344 u8 resp_depth; 345 }; 346 347 struct mlx5_ib_rss_qp { 348 u32 tirn; 349 }; 350 351 struct mlx5_ib_rq { 352 struct mlx5_ib_qp_base base; 353 struct mlx5_ib_wq *rq; 354 struct mlx5_ib_ubuffer ubuffer; 355 struct mlx5_db *doorbell; 356 u32 tirn; 357 u8 state; 358 u32 flags; 359 }; 360 361 struct mlx5_ib_sq { 362 struct mlx5_ib_qp_base base; 363 struct mlx5_ib_wq *sq; 364 struct mlx5_ib_ubuffer ubuffer; 365 struct mlx5_db *doorbell; 366 struct mlx5_flow_handle *flow_rule; 367 u32 tisn; 368 u8 state; 369 }; 370 371 struct mlx5_ib_raw_packet_qp { 372 struct mlx5_ib_sq sq; 373 struct mlx5_ib_rq rq; 374 }; 375 376 struct mlx5_bf { 377 int buf_size; 378 unsigned long offset; 379 struct mlx5_sq_bfreg *bfreg; 380 }; 381 382 struct mlx5_ib_dct { 383 struct mlx5_core_dct mdct; 384 u32 *in; 385 }; 386 387 struct mlx5_ib_qp { 388 struct ib_qp ibqp; 389 union { 390 struct mlx5_ib_qp_trans trans_qp; 391 struct mlx5_ib_raw_packet_qp raw_packet_qp; 392 struct mlx5_ib_rss_qp rss_qp; 393 struct mlx5_ib_dct dct; 394 }; 395 struct mlx5_frag_buf buf; 396 397 struct mlx5_db db; 398 struct mlx5_ib_wq rq; 399 400 u8 sq_signal_bits; 401 u8 next_fence; 402 struct mlx5_ib_wq sq; 403 404 /* serialize qp state modifications 405 */ 406 struct mutex mutex; 407 u32 flags; 408 u8 port; 409 u8 state; 410 int wq_sig; 411 int scat_cqe; 412 int max_inline_data; 413 struct mlx5_bf bf; 414 int has_rq; 415 416 /* only for user space QPs. For kernel 417 * we have it from the bf object 418 */ 419 int bfregn; 420 421 int create_type; 422 423 /* Store signature errors */ 424 bool signature_en; 425 426 struct list_head qps_list; 427 struct list_head cq_recv_list; 428 struct list_head cq_send_list; 429 struct mlx5_rate_limit rl; 430 u32 underlay_qpn; 431 bool tunnel_offload_en; 432 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 433 enum ib_qp_type qp_sub_type; 434 }; 435 436 struct mlx5_ib_cq_buf { 437 struct mlx5_frag_buf_ctrl fbc; 438 struct ib_umem *umem; 439 int cqe_size; 440 int nent; 441 }; 442 443 enum mlx5_ib_qp_flags { 444 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 445 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 446 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 447 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 448 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 449 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 450 /* QP uses 1 as its source QP number */ 451 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 452 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 453 MLX5_IB_QP_RSS = 1 << 8, 454 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 455 MLX5_IB_QP_UNDERLAY = 1 << 10, 456 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 457 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 458 }; 459 460 struct mlx5_umr_wr { 461 struct ib_send_wr wr; 462 u64 virt_addr; 463 u64 offset; 464 struct ib_pd *pd; 465 unsigned int page_shift; 466 unsigned int xlt_size; 467 u64 length; 468 int access_flags; 469 u32 mkey; 470 }; 471 472 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 473 { 474 return container_of(wr, struct mlx5_umr_wr, wr); 475 } 476 477 struct mlx5_shared_mr_info { 478 int mr_id; 479 struct ib_umem *umem; 480 }; 481 482 enum mlx5_ib_cq_pr_flags { 483 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 484 }; 485 486 struct mlx5_ib_cq { 487 struct ib_cq ibcq; 488 struct mlx5_core_cq mcq; 489 struct mlx5_ib_cq_buf buf; 490 struct mlx5_db db; 491 492 /* serialize access to the CQ 493 */ 494 spinlock_t lock; 495 496 /* protect resize cq 497 */ 498 struct mutex resize_mutex; 499 struct mlx5_ib_cq_buf *resize_buf; 500 struct ib_umem *resize_umem; 501 int cqe_size; 502 struct list_head list_send_qp; 503 struct list_head list_recv_qp; 504 u32 create_flags; 505 struct list_head wc_list; 506 enum ib_cq_notify_flags notify_flags; 507 struct work_struct notify_work; 508 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 509 }; 510 511 struct mlx5_ib_wc { 512 struct ib_wc wc; 513 struct list_head list; 514 }; 515 516 struct mlx5_ib_srq { 517 struct ib_srq ibsrq; 518 struct mlx5_core_srq msrq; 519 struct mlx5_frag_buf buf; 520 struct mlx5_db db; 521 u64 *wrid; 522 /* protect SRQ hanlding 523 */ 524 spinlock_t lock; 525 int head; 526 int tail; 527 u16 wqe_ctr; 528 struct ib_umem *umem; 529 /* serialize arming a SRQ 530 */ 531 struct mutex mutex; 532 int wq_sig; 533 }; 534 535 struct mlx5_ib_xrcd { 536 struct ib_xrcd ibxrcd; 537 u32 xrcdn; 538 }; 539 540 enum mlx5_ib_mtt_access_flags { 541 MLX5_IB_MTT_READ = (1 << 0), 542 MLX5_IB_MTT_WRITE = (1 << 1), 543 }; 544 545 struct mlx5_ib_dm { 546 struct ib_dm ibdm; 547 phys_addr_t dev_addr; 548 }; 549 550 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 551 552 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 553 IB_ACCESS_REMOTE_WRITE |\ 554 IB_ACCESS_REMOTE_READ |\ 555 IB_ACCESS_REMOTE_ATOMIC |\ 556 IB_ZERO_BASED) 557 558 struct mlx5_ib_mr { 559 struct ib_mr ibmr; 560 void *descs; 561 dma_addr_t desc_map; 562 int ndescs; 563 int max_descs; 564 int desc_size; 565 int access_mode; 566 struct mlx5_core_mkey mmkey; 567 struct ib_umem *umem; 568 struct mlx5_shared_mr_info *smr_info; 569 struct list_head list; 570 int order; 571 bool allocated_from_cache; 572 int npages; 573 struct mlx5_ib_dev *dev; 574 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 575 struct mlx5_core_sig_ctx *sig; 576 int live; 577 void *descs_alloc; 578 int access_flags; /* Needed for rereg MR */ 579 580 struct mlx5_ib_mr *parent; 581 atomic_t num_leaf_free; 582 wait_queue_head_t q_leaf_free; 583 }; 584 585 struct mlx5_ib_mw { 586 struct ib_mw ibmw; 587 struct mlx5_core_mkey mmkey; 588 int ndescs; 589 }; 590 591 struct mlx5_ib_umr_context { 592 struct ib_cqe cqe; 593 enum ib_wc_status status; 594 struct completion done; 595 }; 596 597 struct umr_common { 598 struct ib_pd *pd; 599 struct ib_cq *cq; 600 struct ib_qp *qp; 601 /* control access to UMR QP 602 */ 603 struct semaphore sem; 604 }; 605 606 enum { 607 MLX5_FMR_INVALID, 608 MLX5_FMR_VALID, 609 MLX5_FMR_BUSY, 610 }; 611 612 struct mlx5_cache_ent { 613 struct list_head head; 614 /* sync access to the cahce entry 615 */ 616 spinlock_t lock; 617 618 619 struct dentry *dir; 620 char name[4]; 621 u32 order; 622 u32 xlt; 623 u32 access_mode; 624 u32 page; 625 626 u32 size; 627 u32 cur; 628 u32 miss; 629 u32 limit; 630 631 struct dentry *fsize; 632 struct dentry *fcur; 633 struct dentry *fmiss; 634 struct dentry *flimit; 635 636 struct mlx5_ib_dev *dev; 637 struct work_struct work; 638 struct delayed_work dwork; 639 int pending; 640 struct completion compl; 641 }; 642 643 struct mlx5_mr_cache { 644 struct workqueue_struct *wq; 645 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 646 int stopped; 647 struct dentry *root; 648 unsigned long last_add; 649 }; 650 651 struct mlx5_ib_gsi_qp; 652 653 struct mlx5_ib_port_resources { 654 struct mlx5_ib_resources *devr; 655 struct mlx5_ib_gsi_qp *gsi; 656 struct work_struct pkey_change_work; 657 }; 658 659 struct mlx5_ib_resources { 660 struct ib_cq *c0; 661 struct ib_xrcd *x0; 662 struct ib_xrcd *x1; 663 struct ib_pd *p0; 664 struct ib_srq *s0; 665 struct ib_srq *s1; 666 struct mlx5_ib_port_resources ports[2]; 667 /* Protects changes to the port resources */ 668 struct mutex mutex; 669 }; 670 671 struct mlx5_ib_counters { 672 const char **names; 673 size_t *offsets; 674 u32 num_q_counters; 675 u32 num_cong_counters; 676 u32 num_ext_ppcnt_counters; 677 u16 set_id; 678 bool set_id_valid; 679 }; 680 681 struct mlx5_ib_multiport_info; 682 683 struct mlx5_ib_multiport { 684 struct mlx5_ib_multiport_info *mpi; 685 /* To be held when accessing the multiport info */ 686 spinlock_t mpi_lock; 687 }; 688 689 struct mlx5_ib_port { 690 struct mlx5_ib_counters cnts; 691 struct mlx5_ib_multiport mp; 692 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 693 }; 694 695 struct mlx5_roce { 696 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 697 * netdev pointer 698 */ 699 rwlock_t netdev_lock; 700 struct net_device *netdev; 701 struct notifier_block nb; 702 atomic_t next_port; 703 enum ib_port_state last_port_state; 704 struct mlx5_ib_dev *dev; 705 u8 native_port_num; 706 }; 707 708 struct mlx5_ib_dbg_param { 709 int offset; 710 struct mlx5_ib_dev *dev; 711 struct dentry *dentry; 712 u8 port_num; 713 }; 714 715 enum mlx5_ib_dbg_cc_types { 716 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 717 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 718 MLX5_IB_DBG_CC_RP_TIME_RESET, 719 MLX5_IB_DBG_CC_RP_BYTE_RESET, 720 MLX5_IB_DBG_CC_RP_THRESHOLD, 721 MLX5_IB_DBG_CC_RP_AI_RATE, 722 MLX5_IB_DBG_CC_RP_HAI_RATE, 723 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 724 MLX5_IB_DBG_CC_RP_MIN_RATE, 725 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 726 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 727 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 728 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 729 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 730 MLX5_IB_DBG_CC_RP_GD, 731 MLX5_IB_DBG_CC_NP_CNP_DSCP, 732 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 733 MLX5_IB_DBG_CC_NP_CNP_PRIO, 734 MLX5_IB_DBG_CC_MAX, 735 }; 736 737 struct mlx5_ib_dbg_cc_params { 738 struct dentry *root; 739 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 740 }; 741 742 enum { 743 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 744 }; 745 746 struct mlx5_ib_dbg_delay_drop { 747 struct dentry *dir_debugfs; 748 struct dentry *rqs_cnt_debugfs; 749 struct dentry *events_cnt_debugfs; 750 struct dentry *timeout_debugfs; 751 }; 752 753 struct mlx5_ib_delay_drop { 754 struct mlx5_ib_dev *dev; 755 struct work_struct delay_drop_work; 756 /* serialize setting of delay drop */ 757 struct mutex lock; 758 u32 timeout; 759 bool activate; 760 atomic_t events_cnt; 761 atomic_t rqs_cnt; 762 struct mlx5_ib_dbg_delay_drop *dbg; 763 }; 764 765 enum mlx5_ib_stages { 766 MLX5_IB_STAGE_INIT, 767 MLX5_IB_STAGE_FLOW_DB, 768 MLX5_IB_STAGE_CAPS, 769 MLX5_IB_STAGE_NON_DEFAULT_CB, 770 MLX5_IB_STAGE_ROCE, 771 MLX5_IB_STAGE_DEVICE_RESOURCES, 772 MLX5_IB_STAGE_ODP, 773 MLX5_IB_STAGE_COUNTERS, 774 MLX5_IB_STAGE_CONG_DEBUGFS, 775 MLX5_IB_STAGE_UAR, 776 MLX5_IB_STAGE_BFREG, 777 MLX5_IB_STAGE_PRE_IB_REG_UMR, 778 MLX5_IB_STAGE_SPECS, 779 MLX5_IB_STAGE_IB_REG, 780 MLX5_IB_STAGE_POST_IB_REG_UMR, 781 MLX5_IB_STAGE_DELAY_DROP, 782 MLX5_IB_STAGE_CLASS_ATTR, 783 MLX5_IB_STAGE_REP_REG, 784 MLX5_IB_STAGE_MAX, 785 }; 786 787 struct mlx5_ib_stage { 788 int (*init)(struct mlx5_ib_dev *dev); 789 void (*cleanup)(struct mlx5_ib_dev *dev); 790 }; 791 792 #define STAGE_CREATE(_stage, _init, _cleanup) \ 793 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 794 795 struct mlx5_ib_profile { 796 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 797 }; 798 799 struct mlx5_ib_multiport_info { 800 struct list_head list; 801 struct mlx5_ib_dev *ibdev; 802 struct mlx5_core_dev *mdev; 803 struct completion unref_comp; 804 u64 sys_image_guid; 805 u32 mdev_refcnt; 806 bool is_master; 807 bool unaffiliate; 808 }; 809 810 struct mlx5_ib_flow_action { 811 struct ib_flow_action ib_action; 812 union { 813 struct { 814 u64 ib_flags; 815 struct mlx5_accel_esp_xfrm *ctx; 816 } esp_aes_gcm; 817 }; 818 }; 819 820 struct mlx5_memic { 821 struct mlx5_core_dev *dev; 822 spinlock_t memic_lock; 823 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 824 }; 825 826 struct mlx5_read_counters_attr { 827 struct mlx5_fc *hw_cntrs_hndl; 828 u64 *out; 829 u32 flags; 830 }; 831 832 enum mlx5_ib_counters_type { 833 MLX5_IB_COUNTERS_FLOW, 834 }; 835 836 struct mlx5_ib_mcounters { 837 struct ib_counters ibcntrs; 838 enum mlx5_ib_counters_type type; 839 /* number of counters supported for this counters type */ 840 u32 counters_num; 841 struct mlx5_fc *hw_cntrs_hndl; 842 /* read function for this counters type */ 843 int (*read_counters)(struct ib_device *ibdev, 844 struct mlx5_read_counters_attr *read_attr); 845 /* max index set as part of create_flow */ 846 u32 cntrs_max_index; 847 /* number of counters data entries (<description,index> pair) */ 848 u32 ncounters; 849 /* counters data array for descriptions and indexes */ 850 struct mlx5_ib_flow_counters_desc *counters_data; 851 /* protects access to mcounters internal data */ 852 struct mutex mcntrs_mutex; 853 }; 854 855 static inline struct mlx5_ib_mcounters * 856 to_mcounters(struct ib_counters *ibcntrs) 857 { 858 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 859 } 860 861 struct mlx5_ib_dev { 862 struct ib_device ib_dev; 863 const struct uverbs_object_tree_def *driver_trees[6]; 864 struct mlx5_core_dev *mdev; 865 struct mlx5_roce roce[MLX5_MAX_PORTS]; 866 int num_ports; 867 /* serialize update of capability mask 868 */ 869 struct mutex cap_mask_mutex; 870 bool ib_active; 871 struct umr_common umrc; 872 /* sync used page count stats 873 */ 874 struct mlx5_ib_resources devr; 875 struct mlx5_mr_cache cache; 876 struct timer_list delay_timer; 877 /* Prevents soft lock on massive reg MRs */ 878 struct mutex slow_path_mutex; 879 int fill_delay; 880 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 881 struct ib_odp_caps odp_caps; 882 u64 odp_max_size; 883 /* 884 * Sleepable RCU that prevents destruction of MRs while they are still 885 * being used by a page fault handler. 886 */ 887 struct srcu_struct mr_srcu; 888 u32 null_mkey; 889 #endif 890 struct mlx5_ib_flow_db *flow_db; 891 /* protect resources needed as part of reset flow */ 892 spinlock_t reset_flow_resource_lock; 893 struct list_head qp_list; 894 /* Array with num_ports elements */ 895 struct mlx5_ib_port *port; 896 struct mlx5_sq_bfreg bfreg; 897 struct mlx5_sq_bfreg fp_bfreg; 898 struct mlx5_ib_delay_drop delay_drop; 899 const struct mlx5_ib_profile *profile; 900 struct mlx5_eswitch_rep *rep; 901 902 /* protect the user_td */ 903 struct mutex lb_mutex; 904 u32 user_td; 905 u8 umr_fence; 906 struct list_head ib_dev_list; 907 u64 sys_image_guid; 908 struct mlx5_memic memic; 909 }; 910 911 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 912 { 913 return container_of(mcq, struct mlx5_ib_cq, mcq); 914 } 915 916 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 917 { 918 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 919 } 920 921 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 922 { 923 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 924 } 925 926 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 927 { 928 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 929 } 930 931 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 932 { 933 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 934 } 935 936 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 937 { 938 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 939 } 940 941 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 942 { 943 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 944 } 945 946 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 947 { 948 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 949 } 950 951 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 952 { 953 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 954 } 955 956 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 957 { 958 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 959 } 960 961 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 962 { 963 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 964 } 965 966 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 967 { 968 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 969 } 970 971 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 972 { 973 return container_of(msrq, struct mlx5_ib_srq, msrq); 974 } 975 976 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 977 { 978 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 979 } 980 981 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 982 { 983 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 984 } 985 986 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 987 { 988 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 989 } 990 991 static inline struct mlx5_ib_flow_action * 992 to_mflow_act(struct ib_flow_action *ibact) 993 { 994 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 995 } 996 997 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 998 struct mlx5_db *db); 999 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1000 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1001 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1002 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1003 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 1004 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1005 const void *in_mad, void *response_mad); 1006 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 1007 struct ib_udata *udata); 1008 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1009 int mlx5_ib_destroy_ah(struct ib_ah *ah); 1010 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 1011 struct ib_srq_init_attr *init_attr, 1012 struct ib_udata *udata); 1013 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1014 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1015 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1016 int mlx5_ib_destroy_srq(struct ib_srq *srq); 1017 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1018 const struct ib_recv_wr **bad_wr); 1019 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1020 struct ib_qp_init_attr *init_attr, 1021 struct ib_udata *udata); 1022 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1023 int attr_mask, struct ib_udata *udata); 1024 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1025 struct ib_qp_init_attr *qp_init_attr); 1026 int mlx5_ib_destroy_qp(struct ib_qp *qp); 1027 void mlx5_ib_drain_sq(struct ib_qp *qp); 1028 void mlx5_ib_drain_rq(struct ib_qp *qp); 1029 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1030 const struct ib_send_wr **bad_wr); 1031 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1032 const struct ib_recv_wr **bad_wr); 1033 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 1034 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 1035 void *buffer, u32 length, 1036 struct mlx5_ib_qp_base *base); 1037 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 1038 const struct ib_cq_init_attr *attr, 1039 struct ib_ucontext *context, 1040 struct ib_udata *udata); 1041 int mlx5_ib_destroy_cq(struct ib_cq *cq); 1042 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1043 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1044 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1045 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1046 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1047 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1048 u64 virt_addr, int access_flags, 1049 struct ib_udata *udata); 1050 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1051 struct ib_udata *udata); 1052 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1053 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1054 int page_shift, int flags); 1055 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1056 int access_flags); 1057 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1058 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1059 u64 length, u64 virt_addr, int access_flags, 1060 struct ib_pd *pd, struct ib_udata *udata); 1061 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 1062 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1063 enum ib_mr_type mr_type, 1064 u32 max_num_sg); 1065 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1066 unsigned int *sg_offset); 1067 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1068 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1069 const struct ib_mad_hdr *in, size_t in_mad_size, 1070 struct ib_mad_hdr *out, size_t *out_mad_size, 1071 u16 *out_mad_pkey_index); 1072 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1073 struct ib_ucontext *context, 1074 struct ib_udata *udata); 1075 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 1076 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1077 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1078 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1079 struct ib_smp *out_mad); 1080 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1081 __be64 *sys_image_guid); 1082 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1083 u16 *max_pkeys); 1084 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1085 u32 *vendor_id); 1086 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1087 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1088 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1089 u16 *pkey); 1090 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1091 union ib_gid *gid); 1092 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1093 struct ib_port_attr *props); 1094 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1095 struct ib_port_attr *props); 1096 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1097 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1098 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1099 unsigned long max_page_shift, 1100 int *count, int *shift, 1101 int *ncont, int *order); 1102 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1103 int page_shift, size_t offset, size_t num_pages, 1104 __be64 *pas, int access_flags); 1105 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1106 int page_shift, __be64 *pas, int access_flags); 1107 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1108 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 1109 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1110 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1111 1112 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1113 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1114 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1115 struct ib_mr_status *mr_status); 1116 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1117 struct ib_wq_init_attr *init_attr, 1118 struct ib_udata *udata); 1119 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1120 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1121 u32 wq_attr_mask, struct ib_udata *udata); 1122 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1123 struct ib_rwq_ind_table_init_attr *init_attr, 1124 struct ib_udata *udata); 1125 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1126 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1127 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1128 struct ib_ucontext *context, 1129 struct ib_dm_alloc_attr *attr, 1130 struct uverbs_attr_bundle *attrs); 1131 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm); 1132 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1133 struct ib_dm_mr_attr *attr, 1134 struct uverbs_attr_bundle *attrs); 1135 1136 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1137 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1138 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, 1139 struct mlx5_pagefault *pfault); 1140 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1141 int __init mlx5_ib_odp_init(void); 1142 void mlx5_ib_odp_cleanup(void); 1143 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 1144 unsigned long end); 1145 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1146 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1147 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1148 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1149 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1150 { 1151 return; 1152 } 1153 1154 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1155 static inline int mlx5_ib_odp_init(void) { return 0; } 1156 static inline void mlx5_ib_odp_cleanup(void) {} 1157 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1158 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1159 size_t nentries, struct mlx5_ib_mr *mr, 1160 int flags) {} 1161 1162 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1163 1164 /* Needed for rep profile */ 1165 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); 1166 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); 1167 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); 1168 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); 1169 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); 1170 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); 1171 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); 1172 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); 1173 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); 1174 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); 1175 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); 1176 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); 1177 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); 1178 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); 1179 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); 1180 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); 1181 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); 1182 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev); 1183 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1184 const struct mlx5_ib_profile *profile, 1185 int stage); 1186 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1187 const struct mlx5_ib_profile *profile); 1188 1189 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1190 u8 port, struct ifla_vf_info *info); 1191 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1192 u8 port, int state); 1193 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1194 u8 port, struct ifla_vf_stats *stats); 1195 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1196 u64 guid, int type); 1197 1198 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1199 const struct ib_gid_attr *attr); 1200 1201 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1202 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1203 1204 /* GSI QP helper functions */ 1205 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1206 struct ib_qp_init_attr *init_attr); 1207 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1208 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1209 int attr_mask); 1210 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1211 int qp_attr_mask, 1212 struct ib_qp_init_attr *qp_init_attr); 1213 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1214 const struct ib_send_wr **bad_wr); 1215 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1216 const struct ib_recv_wr **bad_wr); 1217 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1218 1219 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1220 1221 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1222 int bfregn); 1223 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1224 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1225 u8 ib_port_num, 1226 u8 *native_port_num); 1227 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1228 u8 port_num); 1229 1230 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1231 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1232 struct mlx5_ib_ucontext *context); 1233 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, 1234 struct mlx5_ib_ucontext *context); 1235 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); 1236 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1237 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1238 void *cmd_in, int inlen, int dest_id, int dest_type); 1239 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1240 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root); 1241 #else 1242 static inline int 1243 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1244 struct mlx5_ib_ucontext *context) { return -EOPNOTSUPP; }; 1245 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, 1246 struct mlx5_ib_ucontext *context) {} 1247 static inline const struct uverbs_object_tree_def * 1248 mlx5_ib_get_devx_tree(void) { return NULL; } 1249 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1250 int *dest_type) 1251 { 1252 return false; 1253 } 1254 static inline int 1255 mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root) 1256 { 1257 return 0; 1258 } 1259 #endif 1260 static inline void init_query_mad(struct ib_smp *mad) 1261 { 1262 mad->base_version = 1; 1263 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1264 mad->class_version = 1; 1265 mad->method = IB_MGMT_METHOD_GET; 1266 } 1267 1268 static inline u8 convert_access(int acc) 1269 { 1270 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1271 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1272 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1273 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1274 MLX5_PERM_LOCAL_READ; 1275 } 1276 1277 static inline int is_qp1(enum ib_qp_type qp_type) 1278 { 1279 return qp_type == MLX5_IB_QPT_HW_GSI; 1280 } 1281 1282 #define MLX5_MAX_UMR_SHIFT 16 1283 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1284 1285 static inline u32 check_cq_create_flags(u32 flags) 1286 { 1287 /* 1288 * It returns non-zero value for unsupported CQ 1289 * create flags, otherwise it returns zero. 1290 */ 1291 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1292 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1293 } 1294 1295 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1296 u32 *user_index) 1297 { 1298 if (cqe_version) { 1299 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1300 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1301 return -EINVAL; 1302 *user_index = cmd_uidx; 1303 } else { 1304 *user_index = MLX5_IB_DEFAULT_UIDX; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1311 struct mlx5_ib_create_qp *ucmd, 1312 int inlen, 1313 u32 *user_index) 1314 { 1315 u8 cqe_version = ucontext->cqe_version; 1316 1317 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1318 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1319 return 0; 1320 1321 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1322 !!cqe_version)) 1323 return -EINVAL; 1324 1325 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1326 } 1327 1328 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1329 struct mlx5_ib_create_srq *ucmd, 1330 int inlen, 1331 u32 *user_index) 1332 { 1333 u8 cqe_version = ucontext->cqe_version; 1334 1335 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1336 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1337 return 0; 1338 1339 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1340 !!cqe_version)) 1341 return -EINVAL; 1342 1343 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1344 } 1345 1346 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1347 { 1348 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1349 MLX5_UARS_IN_PAGE : 1; 1350 } 1351 1352 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1353 struct mlx5_bfreg_info *bfregi) 1354 { 1355 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1356 } 1357 1358 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1359 void mlx5_ib_put_xlt_emergency_page(void); 1360 1361 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1362 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1363 bool dyn_bfreg); 1364 #endif /* MLX5_IB_H */ 1365