1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/srq.h> 44 #include <linux/types.h> 45 46 #define mlx5_ib_dbg(dev, format, arg...) \ 47 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 48 __LINE__, current->pid, ##arg) 49 50 #define mlx5_ib_err(dev, format, arg...) \ 51 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 52 __LINE__, current->pid, ##arg) 53 54 #define mlx5_ib_warn(dev, format, arg...) \ 55 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 56 __LINE__, current->pid, ##arg) 57 58 enum { 59 MLX5_IB_MMAP_CMD_SHIFT = 8, 60 MLX5_IB_MMAP_CMD_MASK = 0xff, 61 }; 62 63 enum mlx5_ib_mmap_cmd { 64 MLX5_IB_MMAP_REGULAR_PAGE = 0, 65 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, /* always last */ 66 }; 67 68 enum { 69 MLX5_RES_SCAT_DATA32_CQE = 0x1, 70 MLX5_RES_SCAT_DATA64_CQE = 0x2, 71 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 72 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 73 }; 74 75 enum mlx5_ib_latency_class { 76 MLX5_IB_LATENCY_CLASS_LOW, 77 MLX5_IB_LATENCY_CLASS_MEDIUM, 78 MLX5_IB_LATENCY_CLASS_HIGH, 79 MLX5_IB_LATENCY_CLASS_FAST_PATH 80 }; 81 82 enum mlx5_ib_mad_ifc_flags { 83 MLX5_MAD_IFC_IGNORE_MKEY = 1, 84 MLX5_MAD_IFC_IGNORE_BKEY = 2, 85 MLX5_MAD_IFC_NET_VIEW = 4, 86 }; 87 88 struct mlx5_ib_ucontext { 89 struct ib_ucontext ibucontext; 90 struct list_head db_page_list; 91 92 /* protect doorbell record alloc/free 93 */ 94 struct mutex db_page_mutex; 95 struct mlx5_uuar_info uuari; 96 }; 97 98 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 99 { 100 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 101 } 102 103 struct mlx5_ib_pd { 104 struct ib_pd ibpd; 105 u32 pdn; 106 u32 pa_lkey; 107 }; 108 109 /* Use macros here so that don't have to duplicate 110 * enum ib_send_flags and enum ib_qp_type for low-level driver 111 */ 112 113 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 114 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 115 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 116 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 117 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 118 119 struct wr_list { 120 u16 opcode; 121 u16 next; 122 }; 123 124 struct mlx5_ib_wq { 125 u64 *wrid; 126 u32 *wr_data; 127 struct wr_list *w_list; 128 unsigned *wqe_head; 129 u16 unsig_count; 130 131 /* serialize post to the work queue 132 */ 133 spinlock_t lock; 134 int wqe_cnt; 135 int max_post; 136 int max_gs; 137 int offset; 138 int wqe_shift; 139 unsigned head; 140 unsigned tail; 141 u16 cur_post; 142 u16 last_poll; 143 void *qend; 144 }; 145 146 enum { 147 MLX5_QP_USER, 148 MLX5_QP_KERNEL, 149 MLX5_QP_EMPTY 150 }; 151 152 /* 153 * Connect-IB can trigger up to four concurrent pagefaults 154 * per-QP. 155 */ 156 enum mlx5_ib_pagefault_context { 157 MLX5_IB_PAGEFAULT_RESPONDER_READ, 158 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 159 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 160 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 161 MLX5_IB_PAGEFAULT_CONTEXTS 162 }; 163 164 static inline enum mlx5_ib_pagefault_context 165 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 166 { 167 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 168 } 169 170 struct mlx5_ib_pfault { 171 struct work_struct work; 172 struct mlx5_pagefault mpfault; 173 }; 174 175 struct mlx5_ib_qp { 176 struct ib_qp ibqp; 177 struct mlx5_core_qp mqp; 178 struct mlx5_buf buf; 179 180 struct mlx5_db db; 181 struct mlx5_ib_wq rq; 182 183 u32 doorbell_qpn; 184 u8 sq_signal_bits; 185 u8 fm_cache; 186 int sq_max_wqes_per_wr; 187 int sq_spare_wqes; 188 struct mlx5_ib_wq sq; 189 190 struct ib_umem *umem; 191 int buf_size; 192 193 /* serialize qp state modifications 194 */ 195 struct mutex mutex; 196 u16 xrcdn; 197 u32 flags; 198 u8 port; 199 u8 alt_port; 200 u8 atomic_rd_en; 201 u8 resp_depth; 202 u8 state; 203 int mlx_type; 204 int wq_sig; 205 int scat_cqe; 206 int max_inline_data; 207 struct mlx5_bf *bf; 208 int has_rq; 209 210 /* only for user space QPs. For kernel 211 * we have it from the bf object 212 */ 213 int uuarn; 214 215 int create_type; 216 u32 pa_lkey; 217 218 /* Store signature errors */ 219 bool signature_en; 220 221 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 222 /* 223 * A flag that is true for QP's that are in a state that doesn't 224 * allow page faults, and shouldn't schedule any more faults. 225 */ 226 int disable_page_faults; 227 /* 228 * The disable_page_faults_lock protects a QP's disable_page_faults 229 * field, allowing for a thread to atomically check whether the QP 230 * allows page faults, and if so schedule a page fault. 231 */ 232 spinlock_t disable_page_faults_lock; 233 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 234 #endif 235 }; 236 237 struct mlx5_ib_cq_buf { 238 struct mlx5_buf buf; 239 struct ib_umem *umem; 240 int cqe_size; 241 int nent; 242 }; 243 244 enum mlx5_ib_qp_flags { 245 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0, 246 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1, 247 }; 248 249 struct mlx5_umr_wr { 250 union { 251 u64 virt_addr; 252 u64 offset; 253 } target; 254 struct ib_pd *pd; 255 unsigned int page_shift; 256 unsigned int npages; 257 u32 length; 258 int access_flags; 259 u32 mkey; 260 }; 261 262 struct mlx5_shared_mr_info { 263 int mr_id; 264 struct ib_umem *umem; 265 }; 266 267 struct mlx5_ib_cq { 268 struct ib_cq ibcq; 269 struct mlx5_core_cq mcq; 270 struct mlx5_ib_cq_buf buf; 271 struct mlx5_db db; 272 273 /* serialize access to the CQ 274 */ 275 spinlock_t lock; 276 277 /* protect resize cq 278 */ 279 struct mutex resize_mutex; 280 struct mlx5_ib_cq_buf *resize_buf; 281 struct ib_umem *resize_umem; 282 int cqe_size; 283 }; 284 285 struct mlx5_ib_srq { 286 struct ib_srq ibsrq; 287 struct mlx5_core_srq msrq; 288 struct mlx5_buf buf; 289 struct mlx5_db db; 290 u64 *wrid; 291 /* protect SRQ hanlding 292 */ 293 spinlock_t lock; 294 int head; 295 int tail; 296 u16 wqe_ctr; 297 struct ib_umem *umem; 298 /* serialize arming a SRQ 299 */ 300 struct mutex mutex; 301 int wq_sig; 302 }; 303 304 struct mlx5_ib_xrcd { 305 struct ib_xrcd ibxrcd; 306 u32 xrcdn; 307 }; 308 309 enum mlx5_ib_mtt_access_flags { 310 MLX5_IB_MTT_READ = (1 << 0), 311 MLX5_IB_MTT_WRITE = (1 << 1), 312 }; 313 314 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 315 316 struct mlx5_ib_mr { 317 struct ib_mr ibmr; 318 struct mlx5_core_mr mmr; 319 struct ib_umem *umem; 320 struct mlx5_shared_mr_info *smr_info; 321 struct list_head list; 322 int order; 323 int umred; 324 int npages; 325 struct mlx5_ib_dev *dev; 326 struct mlx5_create_mkey_mbox_out out; 327 struct mlx5_core_sig_ctx *sig; 328 int live; 329 }; 330 331 struct mlx5_ib_fast_reg_page_list { 332 struct ib_fast_reg_page_list ibfrpl; 333 __be64 *mapped_page_list; 334 dma_addr_t map; 335 }; 336 337 struct mlx5_ib_umr_context { 338 enum ib_wc_status status; 339 struct completion done; 340 }; 341 342 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) 343 { 344 context->status = -1; 345 init_completion(&context->done); 346 } 347 348 struct umr_common { 349 struct ib_pd *pd; 350 struct ib_cq *cq; 351 struct ib_qp *qp; 352 /* control access to UMR QP 353 */ 354 struct semaphore sem; 355 }; 356 357 enum { 358 MLX5_FMR_INVALID, 359 MLX5_FMR_VALID, 360 MLX5_FMR_BUSY, 361 }; 362 363 struct mlx5_ib_fmr { 364 struct ib_fmr ibfmr; 365 struct mlx5_core_mr mr; 366 int access_flags; 367 int state; 368 /* protect fmr state 369 */ 370 spinlock_t lock; 371 u64 wrid; 372 struct ib_send_wr wr[2]; 373 u8 page_shift; 374 struct ib_fast_reg_page_list page_list; 375 }; 376 377 struct mlx5_cache_ent { 378 struct list_head head; 379 /* sync access to the cahce entry 380 */ 381 spinlock_t lock; 382 383 384 struct dentry *dir; 385 char name[4]; 386 u32 order; 387 u32 size; 388 u32 cur; 389 u32 miss; 390 u32 limit; 391 392 struct dentry *fsize; 393 struct dentry *fcur; 394 struct dentry *fmiss; 395 struct dentry *flimit; 396 397 struct mlx5_ib_dev *dev; 398 struct work_struct work; 399 struct delayed_work dwork; 400 int pending; 401 }; 402 403 struct mlx5_mr_cache { 404 struct workqueue_struct *wq; 405 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 406 int stopped; 407 struct dentry *root; 408 unsigned long last_add; 409 }; 410 411 struct mlx5_ib_resources { 412 struct ib_cq *c0; 413 struct ib_xrcd *x0; 414 struct ib_xrcd *x1; 415 struct ib_pd *p0; 416 struct ib_srq *s0; 417 struct ib_srq *s1; 418 }; 419 420 struct mlx5_ib_dev { 421 struct ib_device ib_dev; 422 struct mlx5_core_dev *mdev; 423 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 424 int num_ports; 425 /* serialize update of capability mask 426 */ 427 struct mutex cap_mask_mutex; 428 bool ib_active; 429 struct umr_common umrc; 430 /* sync used page count stats 431 */ 432 struct mlx5_ib_resources devr; 433 struct mlx5_mr_cache cache; 434 struct timer_list delay_timer; 435 int fill_delay; 436 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 437 struct ib_odp_caps odp_caps; 438 /* 439 * Sleepable RCU that prevents destruction of MRs while they are still 440 * being used by a page fault handler. 441 */ 442 struct srcu_struct mr_srcu; 443 #endif 444 }; 445 446 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 447 { 448 return container_of(mcq, struct mlx5_ib_cq, mcq); 449 } 450 451 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 452 { 453 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 454 } 455 456 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 457 { 458 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 459 } 460 461 static inline struct mlx5_ib_fmr *to_mfmr(struct ib_fmr *ibfmr) 462 { 463 return container_of(ibfmr, struct mlx5_ib_fmr, ibfmr); 464 } 465 466 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 467 { 468 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 469 } 470 471 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 472 { 473 return container_of(mqp, struct mlx5_ib_qp, mqp); 474 } 475 476 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr) 477 { 478 return container_of(mmr, struct mlx5_ib_mr, mmr); 479 } 480 481 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 482 { 483 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 484 } 485 486 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 487 { 488 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 489 } 490 491 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 492 { 493 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 494 } 495 496 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 497 { 498 return container_of(msrq, struct mlx5_ib_srq, msrq); 499 } 500 501 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 502 { 503 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 504 } 505 506 static inline struct mlx5_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl) 507 { 508 return container_of(ibfrpl, struct mlx5_ib_fast_reg_page_list, ibfrpl); 509 } 510 511 struct mlx5_ib_ah { 512 struct ib_ah ibah; 513 struct mlx5_av av; 514 }; 515 516 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 517 { 518 return container_of(ibah, struct mlx5_ib_ah, ibah); 519 } 520 521 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 522 struct mlx5_db *db); 523 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 524 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 525 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 526 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 527 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 528 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 529 const void *in_mad, void *response_mad); 530 struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr, 531 struct mlx5_ib_ah *ah); 532 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 533 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 534 int mlx5_ib_destroy_ah(struct ib_ah *ah); 535 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 536 struct ib_srq_init_attr *init_attr, 537 struct ib_udata *udata); 538 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 539 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 540 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 541 int mlx5_ib_destroy_srq(struct ib_srq *srq); 542 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 543 struct ib_recv_wr **bad_wr); 544 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 545 struct ib_qp_init_attr *init_attr, 546 struct ib_udata *udata); 547 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 548 int attr_mask, struct ib_udata *udata); 549 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 550 struct ib_qp_init_attr *qp_init_attr); 551 int mlx5_ib_destroy_qp(struct ib_qp *qp); 552 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 553 struct ib_send_wr **bad_wr); 554 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 555 struct ib_recv_wr **bad_wr); 556 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 557 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 558 void *buffer, u32 length); 559 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 560 const struct ib_cq_init_attr *attr, 561 struct ib_ucontext *context, 562 struct ib_udata *udata); 563 int mlx5_ib_destroy_cq(struct ib_cq *cq); 564 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 565 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 566 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 567 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 568 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 569 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 570 u64 virt_addr, int access_flags, 571 struct ib_udata *udata); 572 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 573 int npages, int zap); 574 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 575 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 576 enum ib_mr_type mr_type, 577 u32 max_num_sg); 578 struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev, 579 int page_list_len); 580 void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list); 581 struct ib_fmr *mlx5_ib_fmr_alloc(struct ib_pd *pd, int acc, 582 struct ib_fmr_attr *fmr_attr); 583 int mlx5_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 584 int npages, u64 iova); 585 int mlx5_ib_unmap_fmr(struct list_head *fmr_list); 586 int mlx5_ib_fmr_dealloc(struct ib_fmr *ibfmr); 587 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 588 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 589 const struct ib_mad_hdr *in, size_t in_mad_size, 590 struct ib_mad_hdr *out, size_t *out_mad_size, 591 u16 *out_mad_pkey_index); 592 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 593 struct ib_ucontext *context, 594 struct ib_udata *udata); 595 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 596 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 597 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 598 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 599 struct ib_smp *out_mad); 600 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 601 __be64 *sys_image_guid); 602 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 603 u16 *max_pkeys); 604 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 605 u32 *vendor_id); 606 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 607 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 608 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 609 u16 *pkey); 610 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 611 union ib_gid *gid); 612 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 613 struct ib_port_attr *props); 614 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 615 struct ib_port_attr *props); 616 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 617 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 618 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 619 int *ncont, int *order); 620 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 621 int page_shift, size_t offset, size_t num_pages, 622 __be64 *pas, int access_flags); 623 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 624 int page_shift, __be64 *pas, int access_flags); 625 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 626 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 627 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 628 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 629 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 630 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context); 631 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 632 struct ib_mr_status *mr_status); 633 634 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 635 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 636 637 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 638 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 639 struct mlx5_ib_pfault *pfault); 640 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 641 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 642 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 643 int __init mlx5_ib_odp_init(void); 644 void mlx5_ib_odp_cleanup(void); 645 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 646 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 647 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 648 unsigned long end); 649 650 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 651 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 652 { 653 return; 654 } 655 656 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 657 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 658 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 659 static inline int mlx5_ib_odp_init(void) { return 0; } 660 static inline void mlx5_ib_odp_cleanup(void) {} 661 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 662 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 663 664 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 665 666 static inline void init_query_mad(struct ib_smp *mad) 667 { 668 mad->base_version = 1; 669 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 670 mad->class_version = 1; 671 mad->method = IB_MGMT_METHOD_GET; 672 } 673 674 static inline u8 convert_access(int acc) 675 { 676 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 677 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 678 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 679 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 680 MLX5_PERM_LOCAL_READ; 681 } 682 683 static inline int is_qp1(enum ib_qp_type qp_type) 684 { 685 return qp_type == IB_QPT_GSI; 686 } 687 688 #define MLX5_MAX_UMR_SHIFT 16 689 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 690 691 #endif /* MLX5_IB_H */ 692