1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 29 #define mlx5_ib_dbg(_dev, format, arg...) \ 30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 31 __LINE__, current->pid, ##arg) 32 33 #define mlx5_ib_err(_dev, format, arg...) \ 34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 35 __LINE__, current->pid, ##arg) 36 37 #define mlx5_ib_warn(_dev, format, arg...) \ 38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 39 __LINE__, current->pid, ##arg) 40 41 #define MLX5_IB_DEFAULT_UIDX 0xffffff 42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 43 44 static __always_inline unsigned long 45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 46 unsigned int pgsz_shift) 47 { 48 unsigned int largest_pg_shift = 49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 50 BITS_PER_LONG - 1); 51 52 /* 53 * Despite a command allowing it, the device does not support lower than 54 * 4k page size. 55 */ 56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 57 return GENMASK(largest_pg_shift, pgsz_shift); 58 } 59 60 /* 61 * For mkc users, instead of a page_offset the command has a start_iova which 62 * specifies both the page_offset and the on-the-wire IOVA 63 */ 64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ 65 ib_umem_find_best_pgsz(umem, \ 66 __mlx5_log_page_size_to_bitmap( \ 67 __mlx5_bit_sz(typ, log_pgsz_fld), \ 68 pgsz_shift), \ 69 iova) 70 71 static __always_inline unsigned long 72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 73 unsigned int offset_shift) 74 { 75 unsigned int largest_offset_shift = 76 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 77 BITS_PER_LONG - 1); 78 79 return GENMASK(largest_offset_shift, offset_shift); 80 } 81 82 /* 83 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 84 * page_offset_quantized * (page_size/scale) = page_offset 85 * Which restricts allowed page sizes to ones that satisify the above. 86 */ 87 unsigned long __mlx5_umem_find_best_quantized_pgoff( 88 struct ib_umem *umem, unsigned long pgsz_bitmap, 89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 90 unsigned int *page_offset_quantized); 91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 92 pgsz_shift, page_offset_fld, \ 93 scale, page_offset_quantized) \ 94 __mlx5_umem_find_best_quantized_pgoff( \ 95 umem, \ 96 __mlx5_log_page_size_to_bitmap( \ 97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 98 __mlx5_bit_sz(typ, page_offset_fld), \ 99 GENMASK(31, order_base_2(scale)), scale, \ 100 page_offset_quantized) 101 102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 103 pgsz_shift, page_offset_fld, \ 104 scale, page_offset_quantized) \ 105 __mlx5_umem_find_best_quantized_pgoff( \ 106 umem, \ 107 __mlx5_log_page_size_to_bitmap( \ 108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 110 page_offset_quantized) 111 112 enum { 113 MLX5_IB_MMAP_OFFSET_START = 9, 114 MLX5_IB_MMAP_OFFSET_END = 255, 115 }; 116 117 enum { 118 MLX5_IB_MMAP_CMD_SHIFT = 8, 119 MLX5_IB_MMAP_CMD_MASK = 0xff, 120 }; 121 122 enum { 123 MLX5_RES_SCAT_DATA32_CQE = 0x1, 124 MLX5_RES_SCAT_DATA64_CQE = 0x2, 125 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 126 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 127 }; 128 129 enum mlx5_ib_mad_ifc_flags { 130 MLX5_MAD_IFC_IGNORE_MKEY = 1, 131 MLX5_MAD_IFC_IGNORE_BKEY = 2, 132 MLX5_MAD_IFC_NET_VIEW = 4, 133 }; 134 135 enum { 136 MLX5_CROSS_CHANNEL_BFREG = 0, 137 }; 138 139 enum { 140 MLX5_CQE_VERSION_V0, 141 MLX5_CQE_VERSION_V1, 142 }; 143 144 enum { 145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 146 MLX5_TM_MAX_SGE = 1, 147 }; 148 149 enum { 150 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 151 MLX5_IB_INVALID_BFREG = BIT(31), 152 }; 153 154 enum { 155 MLX5_MAX_MEMIC_PAGES = 0x100, 156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 157 }; 158 159 enum { 160 MLX5_MEMIC_BASE_ALIGN = 6, 161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 162 }; 163 164 enum mlx5_ib_mmap_type { 165 MLX5_IB_MMAP_TYPE_MEMIC = 1, 166 MLX5_IB_MMAP_TYPE_VAR = 2, 167 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 168 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 169 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 170 }; 171 172 struct mlx5_bfreg_info { 173 u32 *sys_pages; 174 int num_low_latency_bfregs; 175 unsigned int *count; 176 177 /* 178 * protect bfreg allocation data structs 179 */ 180 struct mutex lock; 181 u32 ver; 182 u8 lib_uar_4k : 1; 183 u8 lib_uar_dyn : 1; 184 u32 num_sys_pages; 185 u32 num_static_sys_pages; 186 u32 total_num_bfregs; 187 u32 num_dyn_bfregs; 188 }; 189 190 struct mlx5_ib_ucontext { 191 struct ib_ucontext ibucontext; 192 struct list_head db_page_list; 193 194 /* protect doorbell record alloc/free 195 */ 196 struct mutex db_page_mutex; 197 struct mlx5_bfreg_info bfregi; 198 u8 cqe_version; 199 /* Transport Domain number */ 200 u32 tdn; 201 202 u64 lib_caps; 203 u16 devx_uid; 204 /* For RoCE LAG TX affinity */ 205 atomic_t tx_port_affinity; 206 }; 207 208 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 209 { 210 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 211 } 212 213 struct mlx5_ib_pd { 214 struct ib_pd ibpd; 215 u32 pdn; 216 u16 uid; 217 }; 218 219 enum { 220 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 221 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 222 MLX5_IB_FLOW_ACTION_DECAP, 223 }; 224 225 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 226 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 227 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 228 #error "Invalid number of bypass priorities" 229 #endif 230 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 231 232 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 233 #define MLX5_IB_NUM_SNIFFER_FTS 2 234 #define MLX5_IB_NUM_EGRESS_FTS 1 235 struct mlx5_ib_flow_prio { 236 struct mlx5_flow_table *flow_table; 237 unsigned int refcount; 238 }; 239 240 struct mlx5_ib_flow_handler { 241 struct list_head list; 242 struct ib_flow ibflow; 243 struct mlx5_ib_flow_prio *prio; 244 struct mlx5_flow_handle *rule; 245 struct ib_counters *ibcounters; 246 struct mlx5_ib_dev *dev; 247 struct mlx5_ib_flow_matcher *flow_matcher; 248 }; 249 250 struct mlx5_ib_flow_matcher { 251 struct mlx5_ib_match_params matcher_mask; 252 int mask_len; 253 enum mlx5_ib_flow_type flow_type; 254 enum mlx5_flow_namespace_type ns_type; 255 u16 priority; 256 struct mlx5_core_dev *mdev; 257 atomic_t usecnt; 258 u8 match_criteria_enable; 259 }; 260 261 struct mlx5_ib_pp { 262 u16 index; 263 struct mlx5_core_dev *mdev; 264 }; 265 266 struct mlx5_ib_flow_db { 267 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 268 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 269 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 270 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 271 struct mlx5_ib_flow_prio fdb; 272 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 273 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 274 struct mlx5_flow_table *lag_demux_ft; 275 /* Protect flow steering bypass flow tables 276 * when add/del flow rules. 277 * only single add/removal of flow steering rule could be done 278 * simultaneously. 279 */ 280 struct mutex lock; 281 }; 282 283 /* Use macros here so that don't have to duplicate 284 * enum ib_send_flags and enum ib_qp_type for low-level driver 285 */ 286 287 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 288 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 289 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 290 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 291 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 292 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 293 294 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 295 /* 296 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 297 * creates the actual hardware QP. 298 */ 299 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 300 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 301 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 302 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 303 304 #define MLX5_IB_UMR_OCTOWORD 16 305 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 306 307 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 308 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 309 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 310 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 311 #define MLX5_IB_UPD_XLT_PD BIT(4) 312 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 313 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 314 315 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 316 * 317 * These flags are intended for internal use by the mlx5_ib driver, and they 318 * rely on the range reserved for that use in the ib_qp_create_flags enum. 319 */ 320 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 321 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 322 323 struct wr_list { 324 u16 opcode; 325 u16 next; 326 }; 327 328 enum mlx5_ib_rq_flags { 329 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 330 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 331 }; 332 333 struct mlx5_ib_wq { 334 struct mlx5_frag_buf_ctrl fbc; 335 u64 *wrid; 336 u32 *wr_data; 337 struct wr_list *w_list; 338 unsigned *wqe_head; 339 u16 unsig_count; 340 341 /* serialize post to the work queue 342 */ 343 spinlock_t lock; 344 int wqe_cnt; 345 int max_post; 346 int max_gs; 347 int offset; 348 int wqe_shift; 349 unsigned head; 350 unsigned tail; 351 u16 cur_post; 352 u16 last_poll; 353 void *cur_edge; 354 }; 355 356 enum mlx5_ib_wq_flags { 357 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 358 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 359 }; 360 361 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 362 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 363 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 364 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 365 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 366 367 struct mlx5_ib_rwq { 368 struct ib_wq ibwq; 369 struct mlx5_core_qp core_qp; 370 u32 rq_num_pas; 371 u32 log_rq_stride; 372 u32 log_rq_size; 373 u32 rq_page_offset; 374 u32 log_page_size; 375 u32 log_num_strides; 376 u32 two_byte_shift_en; 377 u32 single_stride_log_num_of_bytes; 378 struct ib_umem *umem; 379 size_t buf_size; 380 unsigned int page_shift; 381 struct mlx5_db db; 382 u32 user_index; 383 u32 wqe_count; 384 u32 wqe_shift; 385 int wq_sig; 386 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 387 }; 388 389 struct mlx5_ib_rwq_ind_table { 390 struct ib_rwq_ind_table ib_rwq_ind_tbl; 391 u32 rqtn; 392 u16 uid; 393 }; 394 395 struct mlx5_ib_ubuffer { 396 struct ib_umem *umem; 397 int buf_size; 398 u64 buf_addr; 399 }; 400 401 struct mlx5_ib_qp_base { 402 struct mlx5_ib_qp *container_mibqp; 403 struct mlx5_core_qp mqp; 404 struct mlx5_ib_ubuffer ubuffer; 405 }; 406 407 struct mlx5_ib_qp_trans { 408 struct mlx5_ib_qp_base base; 409 u16 xrcdn; 410 u32 alt_port; 411 u8 atomic_rd_en; 412 u8 resp_depth; 413 }; 414 415 struct mlx5_ib_rss_qp { 416 u32 tirn; 417 }; 418 419 struct mlx5_ib_rq { 420 struct mlx5_ib_qp_base base; 421 struct mlx5_ib_wq *rq; 422 struct mlx5_ib_ubuffer ubuffer; 423 struct mlx5_db *doorbell; 424 u32 tirn; 425 u8 state; 426 u32 flags; 427 }; 428 429 struct mlx5_ib_sq { 430 struct mlx5_ib_qp_base base; 431 struct mlx5_ib_wq *sq; 432 struct mlx5_ib_ubuffer ubuffer; 433 struct mlx5_db *doorbell; 434 struct mlx5_flow_handle *flow_rule; 435 u32 tisn; 436 u8 state; 437 }; 438 439 struct mlx5_ib_raw_packet_qp { 440 struct mlx5_ib_sq sq; 441 struct mlx5_ib_rq rq; 442 }; 443 444 struct mlx5_bf { 445 int buf_size; 446 unsigned long offset; 447 struct mlx5_sq_bfreg *bfreg; 448 }; 449 450 struct mlx5_ib_dct { 451 struct mlx5_core_dct mdct; 452 u32 *in; 453 }; 454 455 struct mlx5_ib_gsi_qp { 456 struct ib_qp *rx_qp; 457 u32 port_num; 458 struct ib_qp_cap cap; 459 struct ib_cq *cq; 460 struct mlx5_ib_gsi_wr *outstanding_wrs; 461 u32 outstanding_pi, outstanding_ci; 462 int num_qps; 463 /* Protects access to the tx_qps. Post send operations synchronize 464 * with tx_qp creation in setup_qp(). Also protects the 465 * outstanding_wrs array and indices. 466 */ 467 spinlock_t lock; 468 struct ib_qp **tx_qps; 469 }; 470 471 struct mlx5_ib_qp { 472 struct ib_qp ibqp; 473 union { 474 struct mlx5_ib_qp_trans trans_qp; 475 struct mlx5_ib_raw_packet_qp raw_packet_qp; 476 struct mlx5_ib_rss_qp rss_qp; 477 struct mlx5_ib_dct dct; 478 struct mlx5_ib_gsi_qp gsi; 479 }; 480 struct mlx5_frag_buf buf; 481 482 struct mlx5_db db; 483 struct mlx5_ib_wq rq; 484 485 u8 sq_signal_bits; 486 u8 next_fence; 487 struct mlx5_ib_wq sq; 488 489 /* serialize qp state modifications 490 */ 491 struct mutex mutex; 492 /* cached variant of create_flags from struct ib_qp_init_attr */ 493 u32 flags; 494 u32 port; 495 u8 state; 496 int max_inline_data; 497 struct mlx5_bf bf; 498 u8 has_rq:1; 499 u8 is_rss:1; 500 501 /* only for user space QPs. For kernel 502 * we have it from the bf object 503 */ 504 int bfregn; 505 506 struct list_head qps_list; 507 struct list_head cq_recv_list; 508 struct list_head cq_send_list; 509 struct mlx5_rate_limit rl; 510 u32 underlay_qpn; 511 u32 flags_en; 512 /* 513 * IB/core doesn't store low-level QP types, so 514 * store both MLX and IBTA types in the field below. 515 */ 516 enum ib_qp_type type; 517 /* A flag to indicate if there's a new counter is configured 518 * but not take effective 519 */ 520 u32 counter_pending; 521 u16 gsi_lag_port; 522 }; 523 524 struct mlx5_ib_cq_buf { 525 struct mlx5_frag_buf_ctrl fbc; 526 struct mlx5_frag_buf frag_buf; 527 struct ib_umem *umem; 528 int cqe_size; 529 int nent; 530 }; 531 532 struct mlx5_umr_wr { 533 struct ib_send_wr wr; 534 u64 virt_addr; 535 u64 offset; 536 struct ib_pd *pd; 537 unsigned int page_shift; 538 unsigned int xlt_size; 539 u64 length; 540 int access_flags; 541 u32 mkey; 542 u8 ignore_free_state:1; 543 }; 544 545 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 546 { 547 return container_of(wr, struct mlx5_umr_wr, wr); 548 } 549 550 enum mlx5_ib_cq_pr_flags { 551 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 552 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 553 }; 554 555 struct mlx5_ib_cq { 556 struct ib_cq ibcq; 557 struct mlx5_core_cq mcq; 558 struct mlx5_ib_cq_buf buf; 559 struct mlx5_db db; 560 561 /* serialize access to the CQ 562 */ 563 spinlock_t lock; 564 565 /* protect resize cq 566 */ 567 struct mutex resize_mutex; 568 struct mlx5_ib_cq_buf *resize_buf; 569 struct ib_umem *resize_umem; 570 int cqe_size; 571 struct list_head list_send_qp; 572 struct list_head list_recv_qp; 573 u32 create_flags; 574 struct list_head wc_list; 575 enum ib_cq_notify_flags notify_flags; 576 struct work_struct notify_work; 577 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 578 }; 579 580 struct mlx5_ib_wc { 581 struct ib_wc wc; 582 struct list_head list; 583 }; 584 585 struct mlx5_ib_srq { 586 struct ib_srq ibsrq; 587 struct mlx5_core_srq msrq; 588 struct mlx5_frag_buf buf; 589 struct mlx5_db db; 590 struct mlx5_frag_buf_ctrl fbc; 591 u64 *wrid; 592 /* protect SRQ hanlding 593 */ 594 spinlock_t lock; 595 int head; 596 int tail; 597 u16 wqe_ctr; 598 struct ib_umem *umem; 599 /* serialize arming a SRQ 600 */ 601 struct mutex mutex; 602 int wq_sig; 603 }; 604 605 struct mlx5_ib_xrcd { 606 struct ib_xrcd ibxrcd; 607 u32 xrcdn; 608 }; 609 610 enum mlx5_ib_mtt_access_flags { 611 MLX5_IB_MTT_READ = (1 << 0), 612 MLX5_IB_MTT_WRITE = (1 << 1), 613 }; 614 615 struct mlx5_user_mmap_entry { 616 struct rdma_user_mmap_entry rdma_entry; 617 u8 mmap_flag; 618 u64 address; 619 u32 page_idx; 620 }; 621 622 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 623 624 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 625 IB_ACCESS_REMOTE_WRITE |\ 626 IB_ACCESS_REMOTE_READ |\ 627 IB_ACCESS_REMOTE_ATOMIC |\ 628 IB_ZERO_BASED) 629 630 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 631 IB_ACCESS_REMOTE_WRITE |\ 632 IB_ACCESS_REMOTE_READ |\ 633 IB_ZERO_BASED) 634 635 #define mlx5_update_odp_stats(mr, counter_name, value) \ 636 atomic64_add(value, &((mr)->odp_stats.counter_name)) 637 638 struct mlx5_ib_mr { 639 struct ib_mr ibmr; 640 struct mlx5_core_mkey mmkey; 641 642 /* User MR data */ 643 struct mlx5_cache_ent *cache_ent; 644 struct ib_umem *umem; 645 646 /* This is zero'd when the MR is allocated */ 647 union { 648 /* Used only while the MR is in the cache */ 649 struct { 650 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 651 struct mlx5_async_work cb_work; 652 /* Cache list element */ 653 struct list_head list; 654 }; 655 656 /* Used only by kernel MRs (umem == NULL) */ 657 struct { 658 void *descs; 659 void *descs_alloc; 660 dma_addr_t desc_map; 661 int max_descs; 662 int ndescs; 663 int desc_size; 664 int access_mode; 665 666 /* For Kernel IB_MR_TYPE_INTEGRITY */ 667 struct mlx5_core_sig_ctx *sig; 668 struct mlx5_ib_mr *pi_mr; 669 struct mlx5_ib_mr *klm_mr; 670 struct mlx5_ib_mr *mtt_mr; 671 u64 data_iova; 672 u64 pi_iova; 673 int meta_ndescs; 674 int meta_length; 675 int data_length; 676 }; 677 678 /* Used only by User MRs (umem != NULL) */ 679 struct { 680 unsigned int page_shift; 681 /* Current access_flags */ 682 int access_flags; 683 684 /* For User ODP */ 685 struct mlx5_ib_mr *parent; 686 struct xarray implicit_children; 687 union { 688 struct work_struct work; 689 } odp_destroy; 690 struct ib_odp_counters odp_stats; 691 bool is_odp_implicit; 692 }; 693 }; 694 }; 695 696 /* Zero the fields in the mr that are variant depending on usage */ 697 static inline void mlx5_clear_mr(struct mlx5_ib_mr *mr) 698 { 699 memset(mr->out, 0, sizeof(*mr) - offsetof(struct mlx5_ib_mr, out)); 700 } 701 702 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 703 { 704 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 705 mr->umem->is_odp; 706 } 707 708 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 709 { 710 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 711 mr->umem->is_dmabuf; 712 } 713 714 struct mlx5_ib_mw { 715 struct ib_mw ibmw; 716 struct mlx5_core_mkey mmkey; 717 int ndescs; 718 }; 719 720 struct mlx5_ib_devx_mr { 721 struct mlx5_core_mkey mmkey; 722 int ndescs; 723 }; 724 725 struct mlx5_ib_umr_context { 726 struct ib_cqe cqe; 727 enum ib_wc_status status; 728 struct completion done; 729 }; 730 731 struct umr_common { 732 struct ib_pd *pd; 733 struct ib_cq *cq; 734 struct ib_qp *qp; 735 /* control access to UMR QP 736 */ 737 struct semaphore sem; 738 }; 739 740 struct mlx5_cache_ent { 741 struct list_head head; 742 /* sync access to the cahce entry 743 */ 744 spinlock_t lock; 745 746 747 char name[4]; 748 u32 order; 749 u32 xlt; 750 u32 access_mode; 751 u32 page; 752 753 u8 disabled:1; 754 u8 fill_to_high_water:1; 755 756 /* 757 * - available_mrs is the length of list head, ie the number of MRs 758 * available for immediate allocation. 759 * - total_mrs is available_mrs plus all in use MRs that could be 760 * returned to the cache. 761 * - limit is the low water mark for available_mrs, 2* limit is the 762 * upper water mark. 763 * - pending is the number of MRs currently being created 764 */ 765 u32 total_mrs; 766 u32 available_mrs; 767 u32 limit; 768 u32 pending; 769 770 /* Statistics */ 771 u32 miss; 772 773 struct mlx5_ib_dev *dev; 774 struct work_struct work; 775 struct delayed_work dwork; 776 }; 777 778 struct mlx5_mr_cache { 779 struct workqueue_struct *wq; 780 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 781 struct dentry *root; 782 unsigned long last_add; 783 }; 784 785 struct mlx5_ib_port_resources { 786 struct mlx5_ib_gsi_qp *gsi; 787 struct work_struct pkey_change_work; 788 }; 789 790 struct mlx5_ib_resources { 791 struct ib_cq *c0; 792 u32 xrcdn0; 793 u32 xrcdn1; 794 struct ib_pd *p0; 795 struct ib_srq *s0; 796 struct ib_srq *s1; 797 struct mlx5_ib_port_resources ports[2]; 798 }; 799 800 struct mlx5_ib_counters { 801 const char **names; 802 size_t *offsets; 803 u32 num_q_counters; 804 u32 num_cong_counters; 805 u32 num_ext_ppcnt_counters; 806 u16 set_id; 807 }; 808 809 struct mlx5_ib_multiport_info; 810 811 struct mlx5_ib_multiport { 812 struct mlx5_ib_multiport_info *mpi; 813 /* To be held when accessing the multiport info */ 814 spinlock_t mpi_lock; 815 }; 816 817 struct mlx5_roce { 818 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 819 * netdev pointer 820 */ 821 rwlock_t netdev_lock; 822 struct net_device *netdev; 823 struct notifier_block nb; 824 atomic_t tx_port_affinity; 825 enum ib_port_state last_port_state; 826 struct mlx5_ib_dev *dev; 827 u32 native_port_num; 828 }; 829 830 struct mlx5_ib_port { 831 struct mlx5_ib_counters cnts; 832 struct mlx5_ib_multiport mp; 833 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 834 struct mlx5_roce roce; 835 struct mlx5_eswitch_rep *rep; 836 }; 837 838 struct mlx5_ib_dbg_param { 839 int offset; 840 struct mlx5_ib_dev *dev; 841 struct dentry *dentry; 842 u32 port_num; 843 }; 844 845 enum mlx5_ib_dbg_cc_types { 846 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 847 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 848 MLX5_IB_DBG_CC_RP_TIME_RESET, 849 MLX5_IB_DBG_CC_RP_BYTE_RESET, 850 MLX5_IB_DBG_CC_RP_THRESHOLD, 851 MLX5_IB_DBG_CC_RP_AI_RATE, 852 MLX5_IB_DBG_CC_RP_MAX_RATE, 853 MLX5_IB_DBG_CC_RP_HAI_RATE, 854 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 855 MLX5_IB_DBG_CC_RP_MIN_RATE, 856 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 857 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 858 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 859 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 860 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 861 MLX5_IB_DBG_CC_RP_GD, 862 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 863 MLX5_IB_DBG_CC_NP_CNP_DSCP, 864 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 865 MLX5_IB_DBG_CC_NP_CNP_PRIO, 866 MLX5_IB_DBG_CC_MAX, 867 }; 868 869 struct mlx5_ib_dbg_cc_params { 870 struct dentry *root; 871 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 872 }; 873 874 enum { 875 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 876 }; 877 878 struct mlx5_ib_delay_drop { 879 struct mlx5_ib_dev *dev; 880 struct work_struct delay_drop_work; 881 /* serialize setting of delay drop */ 882 struct mutex lock; 883 u32 timeout; 884 bool activate; 885 atomic_t events_cnt; 886 atomic_t rqs_cnt; 887 struct dentry *dir_debugfs; 888 }; 889 890 enum mlx5_ib_stages { 891 MLX5_IB_STAGE_INIT, 892 MLX5_IB_STAGE_FS, 893 MLX5_IB_STAGE_CAPS, 894 MLX5_IB_STAGE_NON_DEFAULT_CB, 895 MLX5_IB_STAGE_ROCE, 896 MLX5_IB_STAGE_QP, 897 MLX5_IB_STAGE_SRQ, 898 MLX5_IB_STAGE_DEVICE_RESOURCES, 899 MLX5_IB_STAGE_DEVICE_NOTIFIER, 900 MLX5_IB_STAGE_ODP, 901 MLX5_IB_STAGE_COUNTERS, 902 MLX5_IB_STAGE_CONG_DEBUGFS, 903 MLX5_IB_STAGE_UAR, 904 MLX5_IB_STAGE_BFREG, 905 MLX5_IB_STAGE_PRE_IB_REG_UMR, 906 MLX5_IB_STAGE_WHITELIST_UID, 907 MLX5_IB_STAGE_IB_REG, 908 MLX5_IB_STAGE_POST_IB_REG_UMR, 909 MLX5_IB_STAGE_DELAY_DROP, 910 MLX5_IB_STAGE_RESTRACK, 911 MLX5_IB_STAGE_MAX, 912 }; 913 914 struct mlx5_ib_stage { 915 int (*init)(struct mlx5_ib_dev *dev); 916 void (*cleanup)(struct mlx5_ib_dev *dev); 917 }; 918 919 #define STAGE_CREATE(_stage, _init, _cleanup) \ 920 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 921 922 struct mlx5_ib_profile { 923 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 924 }; 925 926 struct mlx5_ib_multiport_info { 927 struct list_head list; 928 struct mlx5_ib_dev *ibdev; 929 struct mlx5_core_dev *mdev; 930 struct notifier_block mdev_events; 931 struct completion unref_comp; 932 u64 sys_image_guid; 933 u32 mdev_refcnt; 934 bool is_master; 935 bool unaffiliate; 936 }; 937 938 struct mlx5_ib_flow_action { 939 struct ib_flow_action ib_action; 940 union { 941 struct { 942 u64 ib_flags; 943 struct mlx5_accel_esp_xfrm *ctx; 944 } esp_aes_gcm; 945 struct { 946 struct mlx5_ib_dev *dev; 947 u32 sub_type; 948 union { 949 struct mlx5_modify_hdr *modify_hdr; 950 struct mlx5_pkt_reformat *pkt_reformat; 951 }; 952 } flow_action_raw; 953 }; 954 }; 955 956 struct mlx5_dm { 957 struct mlx5_core_dev *dev; 958 /* This lock is used to protect the access to the shared 959 * allocation map when concurrent requests by different 960 * processes are handled. 961 */ 962 spinlock_t lock; 963 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 964 }; 965 966 struct mlx5_read_counters_attr { 967 struct mlx5_fc *hw_cntrs_hndl; 968 u64 *out; 969 u32 flags; 970 }; 971 972 enum mlx5_ib_counters_type { 973 MLX5_IB_COUNTERS_FLOW, 974 }; 975 976 struct mlx5_ib_mcounters { 977 struct ib_counters ibcntrs; 978 enum mlx5_ib_counters_type type; 979 /* number of counters supported for this counters type */ 980 u32 counters_num; 981 struct mlx5_fc *hw_cntrs_hndl; 982 /* read function for this counters type */ 983 int (*read_counters)(struct ib_device *ibdev, 984 struct mlx5_read_counters_attr *read_attr); 985 /* max index set as part of create_flow */ 986 u32 cntrs_max_index; 987 /* number of counters data entries (<description,index> pair) */ 988 u32 ncounters; 989 /* counters data array for descriptions and indexes */ 990 struct mlx5_ib_flow_counters_desc *counters_data; 991 /* protects access to mcounters internal data */ 992 struct mutex mcntrs_mutex; 993 }; 994 995 static inline struct mlx5_ib_mcounters * 996 to_mcounters(struct ib_counters *ibcntrs) 997 { 998 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 999 } 1000 1001 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1002 bool is_egress, 1003 struct mlx5_flow_act *action); 1004 struct mlx5_ib_lb_state { 1005 /* protect the user_td */ 1006 struct mutex mutex; 1007 u32 user_td; 1008 int qps; 1009 bool enabled; 1010 }; 1011 1012 struct mlx5_ib_pf_eq { 1013 struct notifier_block irq_nb; 1014 struct mlx5_ib_dev *dev; 1015 struct mlx5_eq *core; 1016 struct work_struct work; 1017 spinlock_t lock; /* Pagefaults spinlock */ 1018 struct workqueue_struct *wq; 1019 mempool_t *pool; 1020 }; 1021 1022 struct mlx5_devx_event_table { 1023 struct mlx5_nb devx_nb; 1024 /* serialize updating the event_xa */ 1025 struct mutex event_xa_lock; 1026 struct xarray event_xa; 1027 }; 1028 1029 struct mlx5_var_table { 1030 /* serialize updating the bitmap */ 1031 struct mutex bitmap_lock; 1032 unsigned long *bitmap; 1033 u64 hw_start_addr; 1034 u32 stride_size; 1035 u64 num_var_hw_entries; 1036 }; 1037 1038 struct mlx5_port_caps { 1039 bool has_smi; 1040 u8 ext_port_cap; 1041 }; 1042 1043 struct mlx5_ib_dev { 1044 struct ib_device ib_dev; 1045 struct mlx5_core_dev *mdev; 1046 struct notifier_block mdev_events; 1047 int num_ports; 1048 /* serialize update of capability mask 1049 */ 1050 struct mutex cap_mask_mutex; 1051 u8 ib_active:1; 1052 u8 is_rep:1; 1053 u8 lag_active:1; 1054 u8 wc_support:1; 1055 u8 fill_delay; 1056 struct umr_common umrc; 1057 /* sync used page count stats 1058 */ 1059 struct mlx5_ib_resources devr; 1060 1061 atomic_t mkey_var; 1062 struct mlx5_mr_cache cache; 1063 struct timer_list delay_timer; 1064 /* Prevents soft lock on massive reg MRs */ 1065 struct mutex slow_path_mutex; 1066 struct ib_odp_caps odp_caps; 1067 u64 odp_max_size; 1068 struct mutex odp_eq_mutex; 1069 struct mlx5_ib_pf_eq odp_pf_eq; 1070 1071 struct xarray odp_mkeys; 1072 1073 u32 null_mkey; 1074 struct mlx5_ib_flow_db *flow_db; 1075 /* protect resources needed as part of reset flow */ 1076 spinlock_t reset_flow_resource_lock; 1077 struct list_head qp_list; 1078 /* Array with num_ports elements */ 1079 struct mlx5_ib_port *port; 1080 struct mlx5_sq_bfreg bfreg; 1081 struct mlx5_sq_bfreg wc_bfreg; 1082 struct mlx5_sq_bfreg fp_bfreg; 1083 struct mlx5_ib_delay_drop delay_drop; 1084 const struct mlx5_ib_profile *profile; 1085 1086 struct mlx5_ib_lb_state lb; 1087 u8 umr_fence; 1088 struct list_head ib_dev_list; 1089 u64 sys_image_guid; 1090 struct mlx5_dm dm; 1091 u16 devx_whitelist_uid; 1092 struct mlx5_srq_table srq_table; 1093 struct mlx5_qp_table qp_table; 1094 struct mlx5_async_ctx async_ctx; 1095 struct mlx5_devx_event_table devx_event_table; 1096 struct mlx5_var_table var_table; 1097 1098 struct xarray sig_mrs; 1099 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1100 u16 pkey_table_len; 1101 }; 1102 1103 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1104 { 1105 return container_of(mcq, struct mlx5_ib_cq, mcq); 1106 } 1107 1108 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1109 { 1110 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1111 } 1112 1113 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1114 { 1115 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1116 } 1117 1118 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1119 { 1120 return to_mdev(mr->ibmr.device); 1121 } 1122 1123 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1124 { 1125 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1126 udata, struct mlx5_ib_ucontext, ibucontext); 1127 1128 return to_mdev(context->ibucontext.device); 1129 } 1130 1131 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1132 { 1133 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1134 } 1135 1136 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1137 { 1138 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1139 } 1140 1141 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1142 { 1143 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1144 } 1145 1146 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1147 { 1148 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1149 } 1150 1151 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1152 { 1153 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1154 } 1155 1156 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1157 { 1158 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1159 } 1160 1161 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1162 { 1163 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1164 } 1165 1166 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1167 { 1168 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1169 } 1170 1171 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1172 { 1173 return container_of(msrq, struct mlx5_ib_srq, msrq); 1174 } 1175 1176 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1177 { 1178 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1179 } 1180 1181 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1182 { 1183 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1184 } 1185 1186 static inline struct mlx5_ib_flow_action * 1187 to_mflow_act(struct ib_flow_action *ibact) 1188 { 1189 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1190 } 1191 1192 static inline struct mlx5_user_mmap_entry * 1193 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1194 { 1195 return container_of(rdma_entry, 1196 struct mlx5_user_mmap_entry, rdma_entry); 1197 } 1198 1199 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1200 struct mlx5_db *db); 1201 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1202 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1203 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1204 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1205 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1206 struct ib_udata *udata); 1207 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1208 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1209 { 1210 return 0; 1211 } 1212 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1213 struct ib_udata *udata); 1214 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1215 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1216 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1217 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1218 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1219 const struct ib_recv_wr **bad_wr); 1220 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1221 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1222 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1223 struct ib_udata *udata); 1224 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1225 int attr_mask, struct ib_udata *udata); 1226 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1227 struct ib_qp_init_attr *qp_init_attr); 1228 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1229 void mlx5_ib_drain_sq(struct ib_qp *qp); 1230 void mlx5_ib_drain_rq(struct ib_qp *qp); 1231 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1232 size_t buflen, size_t *bc); 1233 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1234 size_t buflen, size_t *bc); 1235 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1236 size_t buflen, size_t *bc); 1237 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1238 struct ib_udata *udata); 1239 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1240 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1241 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1242 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1243 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1244 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1245 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1246 u64 virt_addr, int access_flags, 1247 struct ib_udata *udata); 1248 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1249 u64 length, u64 virt_addr, 1250 int fd, int access_flags, 1251 struct ib_udata *udata); 1252 int mlx5_ib_advise_mr(struct ib_pd *pd, 1253 enum ib_uverbs_advise_mr_advice advice, 1254 u32 flags, 1255 struct ib_sge *sg_list, 1256 u32 num_sge, 1257 struct uverbs_attr_bundle *attrs); 1258 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1259 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1260 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1261 int page_shift, int flags); 1262 int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags); 1263 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1264 int access_flags); 1265 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1266 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1267 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1268 u64 length, u64 virt_addr, int access_flags, 1269 struct ib_pd *pd, struct ib_udata *udata); 1270 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1271 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1272 u32 max_num_sg); 1273 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1274 u32 max_num_sg, 1275 u32 max_num_meta_sg); 1276 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1277 unsigned int *sg_offset); 1278 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1279 int data_sg_nents, unsigned int *data_sg_offset, 1280 struct scatterlist *meta_sg, int meta_sg_nents, 1281 unsigned int *meta_sg_offset); 1282 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1283 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1284 const struct ib_mad *in, struct ib_mad *out, 1285 size_t *out_mad_size, u16 *out_mad_pkey_index); 1286 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1287 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1288 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1289 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1290 __be64 *sys_image_guid); 1291 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1292 u16 *max_pkeys); 1293 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1294 u32 *vendor_id); 1295 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1296 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1297 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1298 u16 *pkey); 1299 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1300 union ib_gid *gid); 1301 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1302 struct ib_port_attr *props); 1303 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1304 struct ib_port_attr *props); 1305 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1306 u64 access_flags); 1307 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1308 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1309 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1310 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1311 1312 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1313 unsigned int entry, int access_flags); 1314 1315 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1316 struct ib_mr_status *mr_status); 1317 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1318 struct ib_wq_init_attr *init_attr, 1319 struct ib_udata *udata); 1320 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1321 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1322 u32 wq_attr_mask, struct ib_udata *udata); 1323 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1324 struct ib_rwq_ind_table_init_attr *init_attr, 1325 struct ib_udata *udata); 1326 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1327 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1328 struct ib_dm_mr_attr *attr, 1329 struct uverbs_attr_bundle *attrs); 1330 1331 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1332 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1333 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1334 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1335 int __init mlx5_ib_odp_init(void); 1336 void mlx5_ib_odp_cleanup(void); 1337 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1338 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1339 struct mlx5_ib_mr *mr, int flags); 1340 1341 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1342 enum ib_uverbs_advise_mr_advice advice, 1343 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1344 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1345 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1346 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1347 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1348 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1349 struct mlx5_ib_pf_eq *eq) 1350 { 1351 return 0; 1352 } 1353 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1354 static inline int mlx5_ib_odp_init(void) { return 0; } 1355 static inline void mlx5_ib_odp_cleanup(void) {} 1356 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1357 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1358 struct mlx5_ib_mr *mr, int flags) {} 1359 1360 static inline int 1361 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1362 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1363 struct ib_sge *sg_list, u32 num_sge) 1364 { 1365 return -EOPNOTSUPP; 1366 } 1367 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1368 { 1369 return -EOPNOTSUPP; 1370 } 1371 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1372 { 1373 return -EOPNOTSUPP; 1374 } 1375 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1376 1377 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1378 1379 /* Needed for rep profile */ 1380 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1381 const struct mlx5_ib_profile *profile, 1382 int stage); 1383 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1384 const struct mlx5_ib_profile *profile); 1385 1386 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1387 u32 port, struct ifla_vf_info *info); 1388 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1389 u32 port, int state); 1390 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1391 u32 port, struct ifla_vf_stats *stats); 1392 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1393 struct ifla_vf_guid *node_guid, 1394 struct ifla_vf_guid *port_guid); 1395 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1396 u64 guid, int type); 1397 1398 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1399 const struct ib_gid_attr *attr); 1400 1401 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1402 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1403 1404 /* GSI QP helper functions */ 1405 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1406 struct ib_qp_init_attr *attr); 1407 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1408 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1409 int attr_mask); 1410 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1411 int qp_attr_mask, 1412 struct ib_qp_init_attr *qp_init_attr); 1413 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1414 const struct ib_send_wr **bad_wr); 1415 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1416 const struct ib_recv_wr **bad_wr); 1417 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1418 1419 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1420 1421 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1422 int bfregn); 1423 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1424 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1425 u32 ib_port_num, 1426 u32 *native_port_num); 1427 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1428 u32 port_num); 1429 1430 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1431 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1432 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1433 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1434 1435 static inline void init_query_mad(struct ib_smp *mad) 1436 { 1437 mad->base_version = 1; 1438 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1439 mad->class_version = 1; 1440 mad->method = IB_MGMT_METHOD_GET; 1441 } 1442 1443 static inline int is_qp1(enum ib_qp_type qp_type) 1444 { 1445 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1446 } 1447 1448 #define MLX5_MAX_UMR_SHIFT 16 1449 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1450 1451 static inline u32 check_cq_create_flags(u32 flags) 1452 { 1453 /* 1454 * It returns non-zero value for unsupported CQ 1455 * create flags, otherwise it returns zero. 1456 */ 1457 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1458 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1459 } 1460 1461 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1462 u32 *user_index) 1463 { 1464 if (cqe_version) { 1465 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1466 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1467 return -EINVAL; 1468 *user_index = cmd_uidx; 1469 } else { 1470 *user_index = MLX5_IB_DEFAULT_UIDX; 1471 } 1472 1473 return 0; 1474 } 1475 1476 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1477 struct mlx5_ib_create_qp *ucmd, 1478 int inlen, 1479 u32 *user_index) 1480 { 1481 u8 cqe_version = ucontext->cqe_version; 1482 1483 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1484 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1485 return 0; 1486 1487 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1488 return -EINVAL; 1489 1490 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1491 } 1492 1493 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1494 struct mlx5_ib_create_srq *ucmd, 1495 int inlen, 1496 u32 *user_index) 1497 { 1498 u8 cqe_version = ucontext->cqe_version; 1499 1500 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1501 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1502 return 0; 1503 1504 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1505 return -EINVAL; 1506 1507 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1508 } 1509 1510 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1511 { 1512 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1513 MLX5_UARS_IN_PAGE : 1; 1514 } 1515 1516 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1517 struct mlx5_bfreg_info *bfregi) 1518 { 1519 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1520 } 1521 1522 extern void *xlt_emergency_page; 1523 1524 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1525 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1526 bool dyn_bfreg); 1527 1528 static inline bool mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev *dev, 1529 size_t length) 1530 { 1531 /* 1532 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is 1533 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka 1534 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey 1535 * can never be enabled without this capability. Simplify this weird 1536 * quirky hardware by just saying it can't use PAS lists with UMR at 1537 * all. 1538 */ 1539 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1540 return false; 1541 1542 /* 1543 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is 1544 * used. 1545 */ 1546 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) && 1547 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE) 1548 return false; 1549 return true; 1550 } 1551 1552 /* 1553 * true if an existing MR can be reconfigured to new access_flags using UMR. 1554 * Older HW cannot use UMR to update certain elements of the MKC. See 1555 * umr_check_mkey_mask(), get_umr_update_access_mask() and umr_check_mkey_mask() 1556 */ 1557 static inline bool mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev *dev, 1558 unsigned int current_access_flags, 1559 unsigned int target_access_flags) 1560 { 1561 unsigned int diffs = current_access_flags ^ target_access_flags; 1562 1563 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) && 1564 MLX5_CAP_GEN(dev->mdev, atomic) && 1565 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1566 return false; 1567 1568 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1569 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 1570 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 1571 return false; 1572 1573 if ((diffs & IB_ACCESS_RELAXED_ORDERING) && 1574 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) && 1575 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 1576 return false; 1577 1578 return true; 1579 } 1580 1581 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1582 struct mlx5_core_mkey *mmkey) 1583 { 1584 refcount_set(&mmkey->usecount, 1); 1585 1586 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1587 mmkey, GFP_KERNEL)); 1588 } 1589 1590 /* deref an mkey that can participate in ODP flow */ 1591 static inline void mlx5r_deref_odp_mkey(struct mlx5_core_mkey *mmkey) 1592 { 1593 if (refcount_dec_and_test(&mmkey->usecount)) 1594 wake_up(&mmkey->wait); 1595 } 1596 1597 /* deref an mkey that can participate in ODP flow and wait for relese */ 1598 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_core_mkey *mmkey) 1599 { 1600 mlx5r_deref_odp_mkey(mmkey); 1601 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1602 } 1603 1604 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1605 1606 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1607 { 1608 return dev->lag_active || 1609 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1610 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1611 } 1612 1613 static inline bool rt_supported(int ts_cap) 1614 { 1615 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1616 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1617 } 1618 #endif /* MLX5_IB_H */ 1619