1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4  * Copyright (c) 2020, Intel Corporation. All rights reserved.
5  */
6 
7 #ifndef MLX5_IB_H
8 #define MLX5_IB_H
9 
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <rdma/ib_verbs.h>
13 #include <rdma/ib_umem.h>
14 #include <rdma/ib_smi.h>
15 #include <linux/mlx5/driver.h>
16 #include <linux/mlx5/cq.h>
17 #include <linux/mlx5/fs.h>
18 #include <linux/mlx5/qp.h>
19 #include <linux/types.h>
20 #include <linux/mlx5/transobj.h>
21 #include <rdma/ib_user_verbs.h>
22 #include <rdma/mlx5-abi.h>
23 #include <rdma/uverbs_ioctl.h>
24 #include <rdma/mlx5_user_ioctl_cmds.h>
25 #include <rdma/mlx5_user_ioctl_verbs.h>
26 
27 #include "srq.h"
28 
29 #define mlx5_ib_dbg(_dev, format, arg...)                                      \
30 	dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__,      \
31 		__LINE__, current->pid, ##arg)
32 
33 #define mlx5_ib_err(_dev, format, arg...)                                      \
34 	dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__,      \
35 		__LINE__, current->pid, ##arg)
36 
37 #define mlx5_ib_warn(_dev, format, arg...)                                     \
38 	dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__,     \
39 		 __LINE__, current->pid, ##arg)
40 
41 #define mlx5_ib_log(lvl, _dev, format, arg...)                                 \
42 	dev_printk(lvl, &(_dev)->ib_dev.dev,  "%s:%d:(pid %d): " format,       \
43 		   __func__, __LINE__, current->pid, ##arg)
44 
45 #define MLX5_IB_DEFAULT_UIDX 0xffffff
46 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
47 
48 static __always_inline unsigned long
49 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,
50 			       unsigned int pgsz_shift)
51 {
52 	unsigned int largest_pg_shift =
53 		min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift,
54 		      BITS_PER_LONG - 1);
55 
56 	/*
57 	 * Despite a command allowing it, the device does not support lower than
58 	 * 4k page size.
59 	 */
60 	pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift);
61 	return GENMASK(largest_pg_shift, pgsz_shift);
62 }
63 
64 /*
65  * For mkc users, instead of a page_offset the command has a start_iova which
66  * specifies both the page_offset and the on-the-wire IOVA
67  */
68 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova)    \
69 	ib_umem_find_best_pgsz(umem,                                           \
70 			       __mlx5_log_page_size_to_bitmap(                 \
71 				       __mlx5_bit_sz(typ, log_pgsz_fld),       \
72 				       pgsz_shift),                            \
73 			       iova)
74 
75 static __always_inline unsigned long
76 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,
77 			      unsigned int offset_shift)
78 {
79 	unsigned int largest_offset_shift =
80 		min_t(unsigned long, page_offset_bits - 1 + offset_shift,
81 		      BITS_PER_LONG - 1);
82 
83 	return GENMASK(largest_offset_shift, offset_shift);
84 }
85 
86 /*
87  * QP/CQ/WQ/etc type commands take a page offset that satisifies:
88  *   page_offset_quantized * (page_size/scale) = page_offset
89  * Which restricts allowed page sizes to ones that satisify the above.
90  */
91 unsigned long __mlx5_umem_find_best_quantized_pgoff(
92 	struct ib_umem *umem, unsigned long pgsz_bitmap,
93 	unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
94 	unsigned int *page_offset_quantized);
95 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld,           \
96 					    pgsz_shift, page_offset_fld,       \
97 					    scale, page_offset_quantized)      \
98 	__mlx5_umem_find_best_quantized_pgoff(                                 \
99 		umem,                                                          \
100 		__mlx5_log_page_size_to_bitmap(                                \
101 			__mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift),         \
102 		__mlx5_bit_sz(typ, page_offset_fld),                           \
103 		GENMASK(31, order_base_2(scale)), scale,                       \
104 		page_offset_quantized)
105 
106 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld,        \
107 					       pgsz_shift, page_offset_fld,    \
108 					       scale, page_offset_quantized)   \
109 	__mlx5_umem_find_best_quantized_pgoff(                                 \
110 		umem,                                                          \
111 		__mlx5_log_page_size_to_bitmap(                                \
112 			__mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift),         \
113 		__mlx5_bit_sz(typ, page_offset_fld), 0, scale,                 \
114 		page_offset_quantized)
115 
116 enum {
117 	MLX5_IB_MMAP_OFFSET_START = 9,
118 	MLX5_IB_MMAP_OFFSET_END = 255,
119 };
120 
121 enum {
122 	MLX5_IB_MMAP_CMD_SHIFT	= 8,
123 	MLX5_IB_MMAP_CMD_MASK	= 0xff,
124 };
125 
126 enum {
127 	MLX5_RES_SCAT_DATA32_CQE	= 0x1,
128 	MLX5_RES_SCAT_DATA64_CQE	= 0x2,
129 	MLX5_REQ_SCAT_DATA32_CQE	= 0x11,
130 	MLX5_REQ_SCAT_DATA64_CQE	= 0x22,
131 };
132 
133 enum mlx5_ib_mad_ifc_flags {
134 	MLX5_MAD_IFC_IGNORE_MKEY	= 1,
135 	MLX5_MAD_IFC_IGNORE_BKEY	= 2,
136 	MLX5_MAD_IFC_NET_VIEW		= 4,
137 };
138 
139 enum {
140 	MLX5_CROSS_CHANNEL_BFREG         = 0,
141 };
142 
143 enum {
144 	MLX5_CQE_VERSION_V0,
145 	MLX5_CQE_VERSION_V1,
146 };
147 
148 enum {
149 	MLX5_TM_MAX_RNDV_MSG_SIZE	= 64,
150 	MLX5_TM_MAX_SGE			= 1,
151 };
152 
153 enum {
154 	MLX5_IB_INVALID_UAR_INDEX	= BIT(31),
155 	MLX5_IB_INVALID_BFREG		= BIT(31),
156 };
157 
158 enum {
159 	MLX5_MAX_MEMIC_PAGES = 0x100,
160 	MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
161 };
162 
163 enum {
164 	MLX5_MEMIC_BASE_ALIGN	= 6,
165 	MLX5_MEMIC_BASE_SIZE	= 1 << MLX5_MEMIC_BASE_ALIGN,
166 };
167 
168 enum mlx5_ib_mmap_type {
169 	MLX5_IB_MMAP_TYPE_MEMIC = 1,
170 	MLX5_IB_MMAP_TYPE_VAR = 2,
171 	MLX5_IB_MMAP_TYPE_UAR_WC = 3,
172 	MLX5_IB_MMAP_TYPE_UAR_NC = 4,
173 	MLX5_IB_MMAP_TYPE_MEMIC_OP = 5,
174 };
175 
176 struct mlx5_bfreg_info {
177 	u32 *sys_pages;
178 	int num_low_latency_bfregs;
179 	unsigned int *count;
180 
181 	/*
182 	 * protect bfreg allocation data structs
183 	 */
184 	struct mutex lock;
185 	u32 ver;
186 	u8 lib_uar_4k : 1;
187 	u8 lib_uar_dyn : 1;
188 	u32 num_sys_pages;
189 	u32 num_static_sys_pages;
190 	u32 total_num_bfregs;
191 	u32 num_dyn_bfregs;
192 };
193 
194 struct mlx5_ib_ucontext {
195 	struct ib_ucontext	ibucontext;
196 	struct list_head	db_page_list;
197 
198 	/* protect doorbell record alloc/free
199 	 */
200 	struct mutex		db_page_mutex;
201 	struct mlx5_bfreg_info	bfregi;
202 	u8			cqe_version;
203 	/* Transport Domain number */
204 	u32			tdn;
205 
206 	u64			lib_caps;
207 	u16			devx_uid;
208 	/* For RoCE LAG TX affinity */
209 	atomic_t		tx_port_affinity;
210 };
211 
212 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
213 {
214 	return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
215 }
216 
217 struct mlx5_ib_pd {
218 	struct ib_pd		ibpd;
219 	u32			pdn;
220 	u16			uid;
221 };
222 
223 enum {
224 	MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
225 	MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
226 	MLX5_IB_FLOW_ACTION_DECAP,
227 };
228 
229 #define MLX5_IB_FLOW_MCAST_PRIO		(MLX5_BY_PASS_NUM_PRIOS - 1)
230 #define MLX5_IB_FLOW_LAST_PRIO		(MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
231 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
232 #error "Invalid number of bypass priorities"
233 #endif
234 #define MLX5_IB_FLOW_LEFTOVERS_PRIO	(MLX5_IB_FLOW_MCAST_PRIO + 1)
235 
236 #define MLX5_IB_NUM_FLOW_FT		(MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
237 #define MLX5_IB_NUM_SNIFFER_FTS		2
238 #define MLX5_IB_NUM_EGRESS_FTS		1
239 #define MLX5_IB_NUM_FDB_FTS		MLX5_BY_PASS_NUM_REGULAR_PRIOS
240 struct mlx5_ib_flow_prio {
241 	struct mlx5_flow_table		*flow_table;
242 	unsigned int			refcount;
243 };
244 
245 struct mlx5_ib_flow_handler {
246 	struct list_head		list;
247 	struct ib_flow			ibflow;
248 	struct mlx5_ib_flow_prio	*prio;
249 	struct mlx5_flow_handle		*rule;
250 	struct ib_counters		*ibcounters;
251 	struct mlx5_ib_dev		*dev;
252 	struct mlx5_ib_flow_matcher	*flow_matcher;
253 };
254 
255 struct mlx5_ib_flow_matcher {
256 	struct mlx5_ib_match_params matcher_mask;
257 	int			mask_len;
258 	enum mlx5_ib_flow_type	flow_type;
259 	enum mlx5_flow_namespace_type ns_type;
260 	u16			priority;
261 	struct mlx5_core_dev	*mdev;
262 	atomic_t		usecnt;
263 	u8			match_criteria_enable;
264 };
265 
266 struct mlx5_ib_steering_anchor {
267 	struct mlx5_ib_flow_prio *ft_prio;
268 	struct mlx5_ib_dev *dev;
269 	atomic_t usecnt;
270 };
271 
272 struct mlx5_ib_pp {
273 	u16 index;
274 	struct mlx5_core_dev *mdev;
275 };
276 
277 enum mlx5_ib_optional_counter_type {
278 	MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS,
279 	MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS,
280 	MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS,
281 
282 	MLX5_IB_OPCOUNTER_MAX,
283 };
284 
285 struct mlx5_ib_flow_db {
286 	struct mlx5_ib_flow_prio	prios[MLX5_IB_NUM_FLOW_FT];
287 	struct mlx5_ib_flow_prio	egress_prios[MLX5_IB_NUM_FLOW_FT];
288 	struct mlx5_ib_flow_prio	sniffer[MLX5_IB_NUM_SNIFFER_FTS];
289 	struct mlx5_ib_flow_prio	egress[MLX5_IB_NUM_EGRESS_FTS];
290 	struct mlx5_ib_flow_prio	fdb[MLX5_IB_NUM_FDB_FTS];
291 	struct mlx5_ib_flow_prio	rdma_rx[MLX5_IB_NUM_FLOW_FT];
292 	struct mlx5_ib_flow_prio	rdma_tx[MLX5_IB_NUM_FLOW_FT];
293 	struct mlx5_ib_flow_prio	opfcs[MLX5_IB_OPCOUNTER_MAX];
294 	struct mlx5_flow_table		*lag_demux_ft;
295 	/* Protect flow steering bypass flow tables
296 	 * when add/del flow rules.
297 	 * only single add/removal of flow steering rule could be done
298 	 * simultaneously.
299 	 */
300 	struct mutex			lock;
301 };
302 
303 /* Use macros here so that don't have to duplicate
304  * enum ib_qp_type for low-level driver
305  */
306 
307 #define MLX5_IB_QPT_REG_UMR	IB_QPT_RESERVED1
308 /*
309  * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
310  * creates the actual hardware QP.
311  */
312 #define MLX5_IB_QPT_HW_GSI	IB_QPT_RESERVED2
313 #define MLX5_IB_QPT_DCI		IB_QPT_RESERVED3
314 #define MLX5_IB_QPT_DCT		IB_QPT_RESERVED4
315 #define MLX5_IB_WR_UMR		IB_WR_RESERVED1
316 
317 #define MLX5_IB_UPD_XLT_ZAP	      BIT(0)
318 #define MLX5_IB_UPD_XLT_ENABLE	      BIT(1)
319 #define MLX5_IB_UPD_XLT_ATOMIC	      BIT(2)
320 #define MLX5_IB_UPD_XLT_ADDR	      BIT(3)
321 #define MLX5_IB_UPD_XLT_PD	      BIT(4)
322 #define MLX5_IB_UPD_XLT_ACCESS	      BIT(5)
323 #define MLX5_IB_UPD_XLT_INDIRECT      BIT(6)
324 
325 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
326  *
327  * These flags are intended for internal use by the mlx5_ib driver, and they
328  * rely on the range reserved for that use in the ib_qp_create_flags enum.
329  */
330 #define MLX5_IB_QP_CREATE_SQPN_QP1	IB_QP_CREATE_RESERVED_START
331 #define MLX5_IB_QP_CREATE_WC_TEST	(IB_QP_CREATE_RESERVED_START << 1)
332 
333 struct wr_list {
334 	u16	opcode;
335 	u16	next;
336 };
337 
338 enum mlx5_ib_rq_flags {
339 	MLX5_IB_RQ_CVLAN_STRIPPING	= 1 << 0,
340 	MLX5_IB_RQ_PCI_WRITE_END_PADDING	= 1 << 1,
341 };
342 
343 struct mlx5_ib_wq {
344 	struct mlx5_frag_buf_ctrl fbc;
345 	u64		       *wrid;
346 	u32		       *wr_data;
347 	struct wr_list	       *w_list;
348 	unsigned	       *wqe_head;
349 	u16		        unsig_count;
350 
351 	/* serialize post to the work queue
352 	 */
353 	spinlock_t		lock;
354 	int			wqe_cnt;
355 	int			max_post;
356 	int			max_gs;
357 	int			offset;
358 	int			wqe_shift;
359 	unsigned		head;
360 	unsigned		tail;
361 	u16			cur_post;
362 	u16			last_poll;
363 	void			*cur_edge;
364 };
365 
366 enum mlx5_ib_wq_flags {
367 	MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
368 	MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
369 };
370 
371 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
372 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
373 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
374 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
375 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
376 
377 struct mlx5_ib_rwq {
378 	struct ib_wq		ibwq;
379 	struct mlx5_core_qp	core_qp;
380 	u32			rq_num_pas;
381 	u32			log_rq_stride;
382 	u32			log_rq_size;
383 	u32			rq_page_offset;
384 	u32			log_page_size;
385 	u32			log_num_strides;
386 	u32			two_byte_shift_en;
387 	u32			single_stride_log_num_of_bytes;
388 	struct ib_umem		*umem;
389 	size_t			buf_size;
390 	unsigned int		page_shift;
391 	struct mlx5_db		db;
392 	u32			user_index;
393 	u32			wqe_count;
394 	u32			wqe_shift;
395 	int			wq_sig;
396 	u32			create_flags; /* Use enum mlx5_ib_wq_flags */
397 };
398 
399 struct mlx5_ib_rwq_ind_table {
400 	struct ib_rwq_ind_table ib_rwq_ind_tbl;
401 	u32			rqtn;
402 	u16			uid;
403 };
404 
405 struct mlx5_ib_ubuffer {
406 	struct ib_umem	       *umem;
407 	int			buf_size;
408 	u64			buf_addr;
409 };
410 
411 struct mlx5_ib_qp_base {
412 	struct mlx5_ib_qp	*container_mibqp;
413 	struct mlx5_core_qp	mqp;
414 	struct mlx5_ib_ubuffer	ubuffer;
415 };
416 
417 struct mlx5_ib_qp_trans {
418 	struct mlx5_ib_qp_base	base;
419 	u16			xrcdn;
420 	u32			alt_port;
421 	u8			atomic_rd_en;
422 	u8			resp_depth;
423 };
424 
425 struct mlx5_ib_rss_qp {
426 	u32	tirn;
427 };
428 
429 struct mlx5_ib_rq {
430 	struct mlx5_ib_qp_base base;
431 	struct mlx5_ib_wq	*rq;
432 	struct mlx5_ib_ubuffer	ubuffer;
433 	struct mlx5_db		*doorbell;
434 	u32			tirn;
435 	u8			state;
436 	u32			flags;
437 };
438 
439 struct mlx5_ib_sq {
440 	struct mlx5_ib_qp_base base;
441 	struct mlx5_ib_wq	*sq;
442 	struct mlx5_ib_ubuffer  ubuffer;
443 	struct mlx5_db		*doorbell;
444 	struct mlx5_flow_handle	*flow_rule;
445 	u32			tisn;
446 	u8			state;
447 };
448 
449 struct mlx5_ib_raw_packet_qp {
450 	struct mlx5_ib_sq sq;
451 	struct mlx5_ib_rq rq;
452 };
453 
454 struct mlx5_bf {
455 	int			buf_size;
456 	unsigned long		offset;
457 	struct mlx5_sq_bfreg   *bfreg;
458 };
459 
460 struct mlx5_ib_dct {
461 	struct mlx5_core_dct    mdct;
462 	u32                     *in;
463 };
464 
465 struct mlx5_ib_gsi_qp {
466 	struct ib_qp *rx_qp;
467 	u32 port_num;
468 	struct ib_qp_cap cap;
469 	struct ib_cq *cq;
470 	struct mlx5_ib_gsi_wr *outstanding_wrs;
471 	u32 outstanding_pi, outstanding_ci;
472 	int num_qps;
473 	/* Protects access to the tx_qps. Post send operations synchronize
474 	 * with tx_qp creation in setup_qp(). Also protects the
475 	 * outstanding_wrs array and indices.
476 	 */
477 	spinlock_t lock;
478 	struct ib_qp **tx_qps;
479 };
480 
481 struct mlx5_ib_qp {
482 	struct ib_qp		ibqp;
483 	union {
484 		struct mlx5_ib_qp_trans trans_qp;
485 		struct mlx5_ib_raw_packet_qp raw_packet_qp;
486 		struct mlx5_ib_rss_qp rss_qp;
487 		struct mlx5_ib_dct dct;
488 		struct mlx5_ib_gsi_qp gsi;
489 	};
490 	struct mlx5_frag_buf	buf;
491 
492 	struct mlx5_db		db;
493 	struct mlx5_ib_wq	rq;
494 
495 	u8			sq_signal_bits;
496 	u8			next_fence;
497 	struct mlx5_ib_wq	sq;
498 
499 	/* serialize qp state modifications
500 	 */
501 	struct mutex		mutex;
502 	/* cached variant of create_flags from struct ib_qp_init_attr */
503 	u32			flags;
504 	u32			port;
505 	u8			state;
506 	int			max_inline_data;
507 	struct mlx5_bf	        bf;
508 	u8			has_rq:1;
509 	u8			is_rss:1;
510 
511 	/* only for user space QPs. For kernel
512 	 * we have it from the bf object
513 	 */
514 	int			bfregn;
515 
516 	struct list_head	qps_list;
517 	struct list_head	cq_recv_list;
518 	struct list_head	cq_send_list;
519 	struct mlx5_rate_limit	rl;
520 	u32                     underlay_qpn;
521 	u32			flags_en;
522 	/*
523 	 * IB/core doesn't store low-level QP types, so
524 	 * store both MLX and IBTA types in the field below.
525 	 */
526 	enum ib_qp_type		type;
527 	/* A flag to indicate if there's a new counter is configured
528 	 * but not take effective
529 	 */
530 	u32                     counter_pending;
531 	u16			gsi_lag_port;
532 };
533 
534 struct mlx5_ib_cq_buf {
535 	struct mlx5_frag_buf_ctrl fbc;
536 	struct mlx5_frag_buf    frag_buf;
537 	struct ib_umem		*umem;
538 	int			cqe_size;
539 	int			nent;
540 };
541 
542 enum mlx5_ib_cq_pr_flags {
543 	MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD	= 1 << 0,
544 	MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1,
545 };
546 
547 struct mlx5_ib_cq {
548 	struct ib_cq		ibcq;
549 	struct mlx5_core_cq	mcq;
550 	struct mlx5_ib_cq_buf	buf;
551 	struct mlx5_db		db;
552 
553 	/* serialize access to the CQ
554 	 */
555 	spinlock_t		lock;
556 
557 	/* protect resize cq
558 	 */
559 	struct mutex		resize_mutex;
560 	struct mlx5_ib_cq_buf  *resize_buf;
561 	struct ib_umem	       *resize_umem;
562 	int			cqe_size;
563 	struct list_head	list_send_qp;
564 	struct list_head	list_recv_qp;
565 	u32			create_flags;
566 	struct list_head	wc_list;
567 	enum ib_cq_notify_flags notify_flags;
568 	struct work_struct	notify_work;
569 	u16			private_flags; /* Use mlx5_ib_cq_pr_flags */
570 };
571 
572 struct mlx5_ib_wc {
573 	struct ib_wc wc;
574 	struct list_head list;
575 };
576 
577 struct mlx5_ib_srq {
578 	struct ib_srq		ibsrq;
579 	struct mlx5_core_srq	msrq;
580 	struct mlx5_frag_buf	buf;
581 	struct mlx5_db		db;
582 	struct mlx5_frag_buf_ctrl fbc;
583 	u64		       *wrid;
584 	/* protect SRQ hanlding
585 	 */
586 	spinlock_t		lock;
587 	int			head;
588 	int			tail;
589 	u16			wqe_ctr;
590 	struct ib_umem	       *umem;
591 	/* serialize arming a SRQ
592 	 */
593 	struct mutex		mutex;
594 	int			wq_sig;
595 };
596 
597 struct mlx5_ib_xrcd {
598 	struct ib_xrcd		ibxrcd;
599 	u32			xrcdn;
600 };
601 
602 enum mlx5_ib_mtt_access_flags {
603 	MLX5_IB_MTT_READ  = (1 << 0),
604 	MLX5_IB_MTT_WRITE = (1 << 1),
605 };
606 
607 struct mlx5_user_mmap_entry {
608 	struct rdma_user_mmap_entry rdma_entry;
609 	u8 mmap_flag;
610 	u64 address;
611 	u32 page_idx;
612 };
613 
614 enum mlx5_mkey_type {
615 	MLX5_MKEY_MR = 1,
616 	MLX5_MKEY_MW,
617 	MLX5_MKEY_INDIRECT_DEVX,
618 };
619 
620 struct mlx5r_cache_rb_key {
621 	u8 ats:1;
622 	unsigned int access_mode;
623 	unsigned int access_flags;
624 	unsigned int ndescs;
625 };
626 
627 struct mlx5_ib_mkey {
628 	u32 key;
629 	enum mlx5_mkey_type type;
630 	unsigned int ndescs;
631 	struct wait_queue_head wait;
632 	refcount_t usecount;
633 	/* User Mkey must hold either a rb_key or a cache_ent. */
634 	struct mlx5r_cache_rb_key rb_key;
635 	struct mlx5_cache_ent *cache_ent;
636 };
637 
638 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
639 
640 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE   |\
641 					 IB_ACCESS_REMOTE_WRITE  |\
642 					 IB_ACCESS_REMOTE_READ   |\
643 					 IB_ACCESS_REMOTE_ATOMIC |\
644 					 IB_ZERO_BASED)
645 
646 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE   |\
647 					  IB_ACCESS_REMOTE_WRITE  |\
648 					  IB_ACCESS_REMOTE_READ   |\
649 					  IB_ZERO_BASED)
650 
651 #define mlx5_update_odp_stats(mr, counter_name, value)		\
652 	atomic64_add(value, &((mr)->odp_stats.counter_name))
653 
654 struct mlx5_ib_mr {
655 	struct ib_mr ibmr;
656 	struct mlx5_ib_mkey mmkey;
657 
658 	struct ib_umem *umem;
659 
660 	union {
661 		/* Used only by kernel MRs (umem == NULL) */
662 		struct {
663 			void *descs;
664 			void *descs_alloc;
665 			dma_addr_t desc_map;
666 			int max_descs;
667 			int desc_size;
668 			int access_mode;
669 
670 			/* For Kernel IB_MR_TYPE_INTEGRITY */
671 			struct mlx5_core_sig_ctx *sig;
672 			struct mlx5_ib_mr *pi_mr;
673 			struct mlx5_ib_mr *klm_mr;
674 			struct mlx5_ib_mr *mtt_mr;
675 			u64 data_iova;
676 			u64 pi_iova;
677 			int meta_ndescs;
678 			int meta_length;
679 			int data_length;
680 		};
681 
682 		/* Used only by User MRs (umem != NULL) */
683 		struct {
684 			unsigned int page_shift;
685 			/* Current access_flags */
686 			int access_flags;
687 
688 			/* For User ODP */
689 			struct mlx5_ib_mr *parent;
690 			struct xarray implicit_children;
691 			union {
692 				struct work_struct work;
693 			} odp_destroy;
694 			struct ib_odp_counters odp_stats;
695 			bool is_odp_implicit;
696 		};
697 	};
698 };
699 
700 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
701 {
702 	return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
703 	       mr->umem->is_odp;
704 }
705 
706 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr)
707 {
708 	return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
709 	       mr->umem->is_dmabuf;
710 }
711 
712 struct mlx5_ib_mw {
713 	struct ib_mw		ibmw;
714 	struct mlx5_ib_mkey	mmkey;
715 };
716 
717 struct mlx5_ib_umr_context {
718 	struct ib_cqe		cqe;
719 	enum ib_wc_status	status;
720 	struct completion	done;
721 };
722 
723 enum {
724 	MLX5_UMR_STATE_UNINIT,
725 	MLX5_UMR_STATE_ACTIVE,
726 	MLX5_UMR_STATE_RECOVER,
727 	MLX5_UMR_STATE_ERR,
728 };
729 
730 struct umr_common {
731 	struct ib_pd	*pd;
732 	struct ib_cq	*cq;
733 	struct ib_qp	*qp;
734 	/* Protects from UMR QP overflow
735 	 */
736 	struct semaphore	sem;
737 	/* Protects from using UMR while the UMR is not active
738 	 */
739 	struct mutex lock;
740 	unsigned int state;
741 };
742 
743 struct mlx5_cache_ent {
744 	struct xarray		mkeys;
745 	unsigned long		stored;
746 	unsigned long		reserved;
747 
748 	char                    name[4];
749 
750 	struct rb_node		node;
751 	struct mlx5r_cache_rb_key rb_key;
752 
753 	u8 is_tmp:1;
754 	u8 disabled:1;
755 	u8 fill_to_high_water:1;
756 
757 	/*
758 	 * - limit is the low water mark for stored mkeys, 2* limit is the
759 	 *   upper water mark.
760 	 */
761 	u32 in_use;
762 	u32 limit;
763 
764 	/* Statistics */
765 	u32                     miss;
766 
767 	struct mlx5_ib_dev     *dev;
768 	struct delayed_work	dwork;
769 };
770 
771 struct mlx5r_async_create_mkey {
772 	union {
773 		u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)];
774 		u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
775 	};
776 	struct mlx5_async_work cb_work;
777 	struct mlx5_cache_ent *ent;
778 	u32 mkey;
779 };
780 
781 struct mlx5_mkey_cache {
782 	struct workqueue_struct *wq;
783 	struct rb_root		rb_root;
784 	struct mutex		rb_lock;
785 	struct dentry		*fs_root;
786 	unsigned long		last_add;
787 	struct delayed_work	remove_ent_dwork;
788 };
789 
790 struct mlx5_ib_port_resources {
791 	struct mlx5_ib_gsi_qp *gsi;
792 	struct work_struct pkey_change_work;
793 };
794 
795 struct mlx5_ib_resources {
796 	struct ib_cq	*c0;
797 	u32 xrcdn0;
798 	u32 xrcdn1;
799 	struct ib_pd	*p0;
800 	struct ib_srq	*s0;
801 	struct ib_srq	*s1;
802 	struct mlx5_ib_port_resources ports[2];
803 };
804 
805 #define MAX_OPFC_RULES 2
806 
807 struct mlx5_ib_op_fc {
808 	struct mlx5_fc *fc;
809 	struct mlx5_flow_handle *rule[MAX_OPFC_RULES];
810 };
811 
812 struct mlx5_ib_counters {
813 	struct rdma_stat_desc *descs;
814 	size_t *offsets;
815 	u32 num_q_counters;
816 	u32 num_cong_counters;
817 	u32 num_ext_ppcnt_counters;
818 	u32 num_op_counters;
819 	u16 set_id;
820 	struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX];
821 };
822 
823 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num,
824 			 struct mlx5_ib_op_fc *opfc,
825 			 enum mlx5_ib_optional_counter_type type);
826 
827 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev,
828 			     struct mlx5_ib_op_fc *opfc,
829 			     enum mlx5_ib_optional_counter_type type);
830 
831 struct mlx5_ib_multiport_info;
832 
833 struct mlx5_ib_multiport {
834 	struct mlx5_ib_multiport_info *mpi;
835 	/* To be held when accessing the multiport info */
836 	spinlock_t mpi_lock;
837 };
838 
839 struct mlx5_roce {
840 	/* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
841 	 * netdev pointer
842 	 */
843 	rwlock_t		netdev_lock;
844 	struct net_device	*netdev;
845 	struct notifier_block	nb;
846 	struct netdev_net_notifier nn;
847 	struct notifier_block	mdev_nb;
848 	struct net_device	*tracking_netdev;
849 	atomic_t		tx_port_affinity;
850 	enum ib_port_state last_port_state;
851 	struct mlx5_ib_dev	*dev;
852 	u32			native_port_num;
853 };
854 
855 struct mlx5_ib_port {
856 	struct mlx5_ib_counters cnts;
857 	struct mlx5_ib_multiport mp;
858 	struct mlx5_ib_dbg_cc_params *dbg_cc_params;
859 	struct mlx5_roce roce;
860 	struct mlx5_eswitch_rep		*rep;
861 };
862 
863 struct mlx5_ib_dbg_param {
864 	int			offset;
865 	struct mlx5_ib_dev	*dev;
866 	struct dentry		*dentry;
867 	u32			port_num;
868 };
869 
870 enum mlx5_ib_dbg_cc_types {
871 	MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
872 	MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
873 	MLX5_IB_DBG_CC_RP_TIME_RESET,
874 	MLX5_IB_DBG_CC_RP_BYTE_RESET,
875 	MLX5_IB_DBG_CC_RP_THRESHOLD,
876 	MLX5_IB_DBG_CC_RP_AI_RATE,
877 	MLX5_IB_DBG_CC_RP_MAX_RATE,
878 	MLX5_IB_DBG_CC_RP_HAI_RATE,
879 	MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
880 	MLX5_IB_DBG_CC_RP_MIN_RATE,
881 	MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
882 	MLX5_IB_DBG_CC_RP_DCE_TCP_G,
883 	MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
884 	MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
885 	MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
886 	MLX5_IB_DBG_CC_RP_GD,
887 	MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
888 	MLX5_IB_DBG_CC_NP_CNP_DSCP,
889 	MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
890 	MLX5_IB_DBG_CC_NP_CNP_PRIO,
891 	MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID,
892 	MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP,
893 	MLX5_IB_DBG_CC_MAX,
894 };
895 
896 struct mlx5_ib_dbg_cc_params {
897 	struct dentry			*root;
898 	struct mlx5_ib_dbg_param	params[MLX5_IB_DBG_CC_MAX];
899 };
900 
901 enum {
902 	MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
903 };
904 
905 struct mlx5_ib_delay_drop {
906 	struct mlx5_ib_dev     *dev;
907 	struct work_struct	delay_drop_work;
908 	/* serialize setting of delay drop */
909 	struct mutex		lock;
910 	u32			timeout;
911 	bool			activate;
912 	atomic_t		events_cnt;
913 	atomic_t		rqs_cnt;
914 	struct dentry		*dir_debugfs;
915 };
916 
917 enum mlx5_ib_stages {
918 	MLX5_IB_STAGE_INIT,
919 	MLX5_IB_STAGE_FS,
920 	MLX5_IB_STAGE_CAPS,
921 	MLX5_IB_STAGE_NON_DEFAULT_CB,
922 	MLX5_IB_STAGE_ROCE,
923 	MLX5_IB_STAGE_QP,
924 	MLX5_IB_STAGE_SRQ,
925 	MLX5_IB_STAGE_DEVICE_RESOURCES,
926 	MLX5_IB_STAGE_DEVICE_NOTIFIER,
927 	MLX5_IB_STAGE_ODP,
928 	MLX5_IB_STAGE_COUNTERS,
929 	MLX5_IB_STAGE_CONG_DEBUGFS,
930 	MLX5_IB_STAGE_UAR,
931 	MLX5_IB_STAGE_BFREG,
932 	MLX5_IB_STAGE_PRE_IB_REG_UMR,
933 	MLX5_IB_STAGE_WHITELIST_UID,
934 	MLX5_IB_STAGE_IB_REG,
935 	MLX5_IB_STAGE_POST_IB_REG_UMR,
936 	MLX5_IB_STAGE_DELAY_DROP,
937 	MLX5_IB_STAGE_RESTRACK,
938 	MLX5_IB_STAGE_MAX,
939 };
940 
941 struct mlx5_ib_stage {
942 	int (*init)(struct mlx5_ib_dev *dev);
943 	void (*cleanup)(struct mlx5_ib_dev *dev);
944 };
945 
946 #define STAGE_CREATE(_stage, _init, _cleanup) \
947 	.stage[_stage] = {.init = _init, .cleanup = _cleanup}
948 
949 struct mlx5_ib_profile {
950 	struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
951 };
952 
953 struct mlx5_ib_multiport_info {
954 	struct list_head list;
955 	struct mlx5_ib_dev *ibdev;
956 	struct mlx5_core_dev *mdev;
957 	struct notifier_block mdev_events;
958 	struct completion unref_comp;
959 	u64 sys_image_guid;
960 	u32 mdev_refcnt;
961 	bool is_master;
962 	bool unaffiliate;
963 };
964 
965 struct mlx5_ib_flow_action {
966 	struct ib_flow_action		ib_action;
967 	union {
968 		struct {
969 			u64			    ib_flags;
970 			struct mlx5_accel_esp_xfrm *ctx;
971 		} esp_aes_gcm;
972 		struct {
973 			struct mlx5_ib_dev *dev;
974 			u32 sub_type;
975 			union {
976 				struct mlx5_modify_hdr *modify_hdr;
977 				struct mlx5_pkt_reformat *pkt_reformat;
978 			};
979 		} flow_action_raw;
980 	};
981 };
982 
983 struct mlx5_dm {
984 	struct mlx5_core_dev *dev;
985 	/* This lock is used to protect the access to the shared
986 	 * allocation map when concurrent requests by different
987 	 * processes are handled.
988 	 */
989 	spinlock_t lock;
990 	DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
991 };
992 
993 struct mlx5_read_counters_attr {
994 	struct mlx5_fc *hw_cntrs_hndl;
995 	u64 *out;
996 	u32 flags;
997 };
998 
999 enum mlx5_ib_counters_type {
1000 	MLX5_IB_COUNTERS_FLOW,
1001 };
1002 
1003 struct mlx5_ib_mcounters {
1004 	struct ib_counters ibcntrs;
1005 	enum mlx5_ib_counters_type type;
1006 	/* number of counters supported for this counters type */
1007 	u32 counters_num;
1008 	struct mlx5_fc *hw_cntrs_hndl;
1009 	/* read function for this counters type */
1010 	int (*read_counters)(struct ib_device *ibdev,
1011 			     struct mlx5_read_counters_attr *read_attr);
1012 	/* max index set as part of create_flow */
1013 	u32 cntrs_max_index;
1014 	/* number of counters data entries (<description,index> pair) */
1015 	u32 ncounters;
1016 	/* counters data array for descriptions and indexes */
1017 	struct mlx5_ib_flow_counters_desc *counters_data;
1018 	/* protects access to mcounters internal data */
1019 	struct mutex mcntrs_mutex;
1020 };
1021 
1022 static inline struct mlx5_ib_mcounters *
1023 to_mcounters(struct ib_counters *ibcntrs)
1024 {
1025 	return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
1026 }
1027 
1028 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
1029 			   bool is_egress,
1030 			   struct mlx5_flow_act *action);
1031 struct mlx5_ib_lb_state {
1032 	/* protect the user_td */
1033 	struct mutex		mutex;
1034 	u32			user_td;
1035 	int			qps;
1036 	bool			enabled;
1037 };
1038 
1039 struct mlx5_ib_pf_eq {
1040 	struct notifier_block irq_nb;
1041 	struct mlx5_ib_dev *dev;
1042 	struct mlx5_eq *core;
1043 	struct work_struct work;
1044 	spinlock_t lock; /* Pagefaults spinlock */
1045 	struct workqueue_struct *wq;
1046 	mempool_t *pool;
1047 };
1048 
1049 struct mlx5_devx_event_table {
1050 	struct mlx5_nb devx_nb;
1051 	/* serialize updating the event_xa */
1052 	struct mutex event_xa_lock;
1053 	struct xarray event_xa;
1054 };
1055 
1056 struct mlx5_var_table {
1057 	/* serialize updating the bitmap */
1058 	struct mutex bitmap_lock;
1059 	unsigned long *bitmap;
1060 	u64 hw_start_addr;
1061 	u32 stride_size;
1062 	u64 num_var_hw_entries;
1063 };
1064 
1065 struct mlx5_port_caps {
1066 	bool has_smi;
1067 	u8 ext_port_cap;
1068 };
1069 
1070 
1071 struct mlx5_special_mkeys {
1072 	u32 dump_fill_mkey;
1073 	__be32 null_mkey;
1074 	__be32 terminate_scatter_list_mkey;
1075 };
1076 
1077 struct mlx5_ib_dev {
1078 	struct ib_device		ib_dev;
1079 	struct mlx5_core_dev		*mdev;
1080 	struct notifier_block		mdev_events;
1081 	int				num_ports;
1082 	/* serialize update of capability mask
1083 	 */
1084 	struct mutex			cap_mask_mutex;
1085 	u8				ib_active:1;
1086 	u8				is_rep:1;
1087 	u8				lag_active:1;
1088 	u8				wc_support:1;
1089 	u8				fill_delay;
1090 	struct umr_common		umrc;
1091 	/* sync used page count stats
1092 	 */
1093 	struct mlx5_ib_resources	devr;
1094 
1095 	atomic_t			mkey_var;
1096 	struct mlx5_mkey_cache		cache;
1097 	struct timer_list		delay_timer;
1098 	/* Prevents soft lock on massive reg MRs */
1099 	struct mutex			slow_path_mutex;
1100 	struct ib_odp_caps	odp_caps;
1101 	u64			odp_max_size;
1102 	struct mutex		odp_eq_mutex;
1103 	struct mlx5_ib_pf_eq	odp_pf_eq;
1104 
1105 	struct xarray		odp_mkeys;
1106 
1107 	struct mlx5_ib_flow_db	*flow_db;
1108 	/* protect resources needed as part of reset flow */
1109 	spinlock_t		reset_flow_resource_lock;
1110 	struct list_head	qp_list;
1111 	/* Array with num_ports elements */
1112 	struct mlx5_ib_port	*port;
1113 	struct mlx5_sq_bfreg	bfreg;
1114 	struct mlx5_sq_bfreg	wc_bfreg;
1115 	struct mlx5_sq_bfreg	fp_bfreg;
1116 	struct mlx5_ib_delay_drop	delay_drop;
1117 	const struct mlx5_ib_profile	*profile;
1118 
1119 	struct mlx5_ib_lb_state		lb;
1120 	u8			umr_fence;
1121 	struct list_head	ib_dev_list;
1122 	u64			sys_image_guid;
1123 	struct mlx5_dm		dm;
1124 	u16			devx_whitelist_uid;
1125 	struct mlx5_srq_table   srq_table;
1126 	struct mlx5_qp_table    qp_table;
1127 	struct mlx5_async_ctx   async_ctx;
1128 	struct mlx5_devx_event_table devx_event_table;
1129 	struct mlx5_var_table var_table;
1130 
1131 	struct xarray sig_mrs;
1132 	struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
1133 	u16 pkey_table_len;
1134 	u8 lag_ports;
1135 	struct mlx5_special_mkeys mkeys;
1136 };
1137 
1138 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1139 {
1140 	return container_of(mcq, struct mlx5_ib_cq, mcq);
1141 }
1142 
1143 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1144 {
1145 	return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1146 }
1147 
1148 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1149 {
1150 	return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1151 }
1152 
1153 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr)
1154 {
1155 	return to_mdev(mr->ibmr.device);
1156 }
1157 
1158 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1159 {
1160 	struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1161 		udata, struct mlx5_ib_ucontext, ibucontext);
1162 
1163 	return to_mdev(context->ibucontext.device);
1164 }
1165 
1166 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1167 {
1168 	return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1169 }
1170 
1171 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1172 {
1173 	return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1174 }
1175 
1176 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1177 {
1178 	return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1179 }
1180 
1181 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1182 {
1183 	return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1184 }
1185 
1186 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1187 {
1188 	return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1189 }
1190 
1191 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1192 {
1193 	return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1194 }
1195 
1196 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1197 {
1198 	return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1199 }
1200 
1201 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1202 {
1203 	return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1204 }
1205 
1206 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1207 {
1208 	return container_of(msrq, struct mlx5_ib_srq, msrq);
1209 }
1210 
1211 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1212 {
1213 	return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1214 }
1215 
1216 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1217 {
1218 	return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1219 }
1220 
1221 static inline struct mlx5_ib_flow_action *
1222 to_mflow_act(struct ib_flow_action *ibact)
1223 {
1224 	return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1225 }
1226 
1227 static inline struct mlx5_user_mmap_entry *
1228 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1229 {
1230 	return container_of(rdma_entry,
1231 		struct mlx5_user_mmap_entry, rdma_entry);
1232 }
1233 
1234 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1235 			struct mlx5_db *db);
1236 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1237 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1238 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1239 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1240 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1241 		      struct ib_udata *udata);
1242 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1243 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1244 {
1245 	return 0;
1246 }
1247 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1248 		       struct ib_udata *udata);
1249 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1250 		       enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1251 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1252 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1253 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1254 			  const struct ib_recv_wr **bad_wr);
1255 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1256 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1257 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
1258 		      struct ib_udata *udata);
1259 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1260 		      int attr_mask, struct ib_udata *udata);
1261 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1262 		     struct ib_qp_init_attr *qp_init_attr);
1263 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1264 void mlx5_ib_drain_sq(struct ib_qp *qp);
1265 void mlx5_ib_drain_rq(struct ib_qp *qp);
1266 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1267 			size_t buflen, size_t *bc);
1268 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1269 			size_t buflen, size_t *bc);
1270 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1271 			 size_t buflen, size_t *bc);
1272 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1273 		      struct ib_udata *udata);
1274 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1275 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1276 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1277 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1278 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1279 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1280 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1281 				  u64 virt_addr, int access_flags,
1282 				  struct ib_udata *udata);
1283 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
1284 					 u64 length, u64 virt_addr,
1285 					 int fd, int access_flags,
1286 					 struct ib_udata *udata);
1287 int mlx5_ib_advise_mr(struct ib_pd *pd,
1288 		      enum ib_uverbs_advise_mr_advice advice,
1289 		      u32 flags,
1290 		      struct ib_sge *sg_list,
1291 		      u32 num_sge,
1292 		      struct uverbs_attr_bundle *attrs);
1293 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1294 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1295 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1296 					     int access_flags);
1297 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1298 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr);
1299 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1300 				    u64 length, u64 virt_addr, int access_flags,
1301 				    struct ib_pd *pd, struct ib_udata *udata);
1302 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1303 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1304 			       u32 max_num_sg);
1305 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1306 					 u32 max_num_sg,
1307 					 u32 max_num_meta_sg);
1308 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1309 		      unsigned int *sg_offset);
1310 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1311 			 int data_sg_nents, unsigned int *data_sg_offset,
1312 			 struct scatterlist *meta_sg, int meta_sg_nents,
1313 			 unsigned int *meta_sg_offset);
1314 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,
1315 			const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1316 			const struct ib_mad *in, struct ib_mad *out,
1317 			size_t *out_mad_size, u16 *out_mad_pkey_index);
1318 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1319 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1320 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port);
1321 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1322 					 __be64 *sys_image_guid);
1323 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1324 				 u16 *max_pkeys);
1325 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1326 				 u32 *vendor_id);
1327 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1328 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1329 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index,
1330 			    u16 *pkey);
1331 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index,
1332 			    union ib_gid *gid);
1333 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port,
1334 			    struct ib_port_attr *props);
1335 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1336 		       struct ib_port_attr *props);
1337 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
1338 			  u64 access_flags);
1339 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1340 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1341 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev);
1342 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev);
1343 struct mlx5_cache_ent *
1344 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev,
1345 			      struct mlx5r_cache_rb_key rb_key,
1346 			      bool persistent_entry);
1347 
1348 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1349 				       int access_flags, int access_mode,
1350 				       int ndescs);
1351 
1352 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1353 			    struct ib_mr_status *mr_status);
1354 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1355 				struct ib_wq_init_attr *init_attr,
1356 				struct ib_udata *udata);
1357 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1358 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1359 		      u32 wq_attr_mask, struct ib_udata *udata);
1360 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1361 				 struct ib_rwq_ind_table_init_attr *init_attr,
1362 				 struct ib_udata *udata);
1363 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1364 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1365 				struct ib_dm_mr_attr *attr,
1366 				struct uverbs_attr_bundle *attrs);
1367 
1368 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1369 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1370 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq);
1371 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1372 int __init mlx5_ib_odp_init(void);
1373 void mlx5_ib_odp_cleanup(void);
1374 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev);
1375 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1376 			   struct mlx5_ib_mr *mr, int flags);
1377 
1378 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1379 			       enum ib_uverbs_advise_mr_advice advice,
1380 			       u32 flags, struct ib_sge *sg_list, u32 num_sge);
1381 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr);
1382 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr);
1383 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1384 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1385 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev,
1386 				      struct mlx5_ib_pf_eq *eq)
1387 {
1388 	return 0;
1389 }
1390 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1391 static inline int mlx5_ib_odp_init(void) { return 0; }
1392 static inline void mlx5_ib_odp_cleanup(void)				    {}
1393 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev)
1394 {
1395 	return 0;
1396 }
1397 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1398 					 struct mlx5_ib_mr *mr, int flags) {}
1399 
1400 static inline int
1401 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1402 			   enum ib_uverbs_advise_mr_advice advice, u32 flags,
1403 			   struct ib_sge *sg_list, u32 num_sge)
1404 {
1405 	return -EOPNOTSUPP;
1406 }
1407 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
1408 {
1409 	return -EOPNOTSUPP;
1410 }
1411 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
1412 {
1413 	return -EOPNOTSUPP;
1414 }
1415 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1416 
1417 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1418 
1419 /* Needed for rep profile */
1420 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1421 		      const struct mlx5_ib_profile *profile,
1422 		      int stage);
1423 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
1424 		  const struct mlx5_ib_profile *profile);
1425 
1426 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1427 			  u32 port, struct ifla_vf_info *info);
1428 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1429 			      u32 port, int state);
1430 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1431 			 u32 port, struct ifla_vf_stats *stats);
1432 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port,
1433 			struct ifla_vf_guid *node_guid,
1434 			struct ifla_vf_guid *port_guid);
1435 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port,
1436 			u64 guid, int type);
1437 
1438 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1439 				   const struct ib_gid_attr *attr);
1440 
1441 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1442 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1443 
1444 /* GSI QP helper functions */
1445 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1446 		       struct ib_qp_init_attr *attr);
1447 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1448 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1449 			  int attr_mask);
1450 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1451 			 int qp_attr_mask,
1452 			 struct ib_qp_init_attr *qp_init_attr);
1453 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1454 			  const struct ib_send_wr **bad_wr);
1455 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1456 			  const struct ib_recv_wr **bad_wr);
1457 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1458 
1459 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1460 
1461 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1462 			int bfregn);
1463 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1464 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1465 						   u32 ib_port_num,
1466 						   u32 *native_port_num);
1467 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1468 				  u32 port_num);
1469 
1470 extern const struct uapi_definition mlx5_ib_devx_defs[];
1471 extern const struct uapi_definition mlx5_ib_flow_defs[];
1472 extern const struct uapi_definition mlx5_ib_qos_defs[];
1473 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1474 
1475 static inline int is_qp1(enum ib_qp_type qp_type)
1476 {
1477 	return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1478 }
1479 
1480 static inline u32 check_cq_create_flags(u32 flags)
1481 {
1482 	/*
1483 	 * It returns non-zero value for unsupported CQ
1484 	 * create flags, otherwise it returns zero.
1485 	 */
1486 	return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1487 			  IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1488 }
1489 
1490 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1491 				     u32 *user_index)
1492 {
1493 	if (cqe_version) {
1494 		if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1495 		    (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1496 			return -EINVAL;
1497 		*user_index = cmd_uidx;
1498 	} else {
1499 		*user_index = MLX5_IB_DEFAULT_UIDX;
1500 	}
1501 
1502 	return 0;
1503 }
1504 
1505 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1506 				    struct mlx5_ib_create_qp *ucmd,
1507 				    int inlen,
1508 				    u32 *user_index)
1509 {
1510 	u8 cqe_version = ucontext->cqe_version;
1511 
1512 	if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1513 	    (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1514 		return 0;
1515 
1516 	if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1517 		return -EINVAL;
1518 
1519 	return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1520 }
1521 
1522 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1523 				     struct mlx5_ib_create_srq *ucmd,
1524 				     int inlen,
1525 				     u32 *user_index)
1526 {
1527 	u8 cqe_version = ucontext->cqe_version;
1528 
1529 	if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1530 	    (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1531 		return 0;
1532 
1533 	if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1534 		return -EINVAL;
1535 
1536 	return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1537 }
1538 
1539 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1540 {
1541 	return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1542 				MLX5_UARS_IN_PAGE : 1;
1543 }
1544 
1545 extern void *xlt_emergency_page;
1546 
1547 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1548 			struct mlx5_bfreg_info *bfregi, u32 bfregn,
1549 			bool dyn_bfreg);
1550 
1551 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev,
1552 				       struct mlx5_ib_mkey *mmkey)
1553 {
1554 	refcount_set(&mmkey->usecount, 1);
1555 
1556 	return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key),
1557 			       mmkey, GFP_KERNEL));
1558 }
1559 
1560 /* deref an mkey that can participate in ODP flow */
1561 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey)
1562 {
1563 	if (refcount_dec_and_test(&mmkey->usecount))
1564 		wake_up(&mmkey->wait);
1565 }
1566 
1567 /* deref an mkey that can participate in ODP flow and wait for relese */
1568 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey)
1569 {
1570 	mlx5r_deref_odp_mkey(mmkey);
1571 	wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0);
1572 }
1573 
1574 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1575 
1576 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1577 {
1578 	/*
1579 	 * If the driver is in hash mode and the port_select_flow_table_bypass cap
1580 	 * is supported, it means that the driver no longer needs to assign the port
1581 	 * affinity by default. If a user wants to set the port affinity explicitly,
1582 	 * the user has a dedicated API to do that, so there is no need to assign
1583 	 * the port affinity by default.
1584 	 */
1585 	if (dev->lag_active &&
1586 	    mlx5_lag_mode_is_hash(dev->mdev) &&
1587 	    MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass))
1588 		return 0;
1589 
1590 	return dev->lag_active ||
1591 		(MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1592 		 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1593 }
1594 
1595 static inline bool rt_supported(int ts_cap)
1596 {
1597 	return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME ||
1598 	       ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;
1599 }
1600 
1601 /*
1602  * PCI Peer to Peer is a trainwreck. If no switch is present then things
1603  * sometimes work, depending on the pci_distance_p2p logic for excluding broken
1604  * root complexes. However if a switch is present in the path, then things get
1605  * really ugly depending on how the switch is setup. This table assumes that the
1606  * root complex is strict and is validating that all req/reps are matches
1607  * perfectly - so any scenario where it sees only half the transaction is a
1608  * failure.
1609  *
1610  * CR/RR/DT  ATS RO P2P
1611  * 00X       X   X  OK
1612  * 010       X   X  fails (request is routed to root but root never sees comp)
1613  * 011       0   X  fails (request is routed to root but root never sees comp)
1614  * 011       1   X  OK
1615  * 10X       X   1  OK
1616  * 101       X   0  fails (completion is routed to root but root didn't see req)
1617  * 110       X   0  SLOW
1618  * 111       0   0  SLOW
1619  * 111       1   0  fails (completion is routed to root but root didn't see req)
1620  * 111       1   1  OK
1621  *
1622  * Unfortunately we cannot reliably know if a switch is present or what the
1623  * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that
1624  * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows.
1625  *
1626  * For now assume if the umem is a dma_buf then it is P2P.
1627  */
1628 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev,
1629 				       struct ib_umem *umem, int access_flags)
1630 {
1631 	if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf)
1632 		return false;
1633 	return access_flags & IB_ACCESS_RELAXED_ORDERING;
1634 }
1635 
1636 #endif /* MLX5_IB_H */
1637