1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_smi.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/fs.h> 43 #include <linux/mlx5/qp.h> 44 #include <linux/mlx5/fs.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 52 #include "srq.h" 53 54 #define mlx5_ib_dbg(_dev, format, arg...) \ 55 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 56 __LINE__, current->pid, ##arg) 57 58 #define mlx5_ib_err(_dev, format, arg...) \ 59 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 60 __LINE__, current->pid, ##arg) 61 62 #define mlx5_ib_warn(_dev, format, arg...) \ 63 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 64 __LINE__, current->pid, ##arg) 65 66 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 67 sizeof(((type *)0)->fld) <= (sz)) 68 #define MLX5_IB_DEFAULT_UIDX 0xffffff 69 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 70 71 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 72 73 enum { 74 MLX5_IB_MMAP_CMD_SHIFT = 8, 75 MLX5_IB_MMAP_CMD_MASK = 0xff, 76 }; 77 78 enum { 79 MLX5_RES_SCAT_DATA32_CQE = 0x1, 80 MLX5_RES_SCAT_DATA64_CQE = 0x2, 81 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 82 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 83 }; 84 85 enum mlx5_ib_mad_ifc_flags { 86 MLX5_MAD_IFC_IGNORE_MKEY = 1, 87 MLX5_MAD_IFC_IGNORE_BKEY = 2, 88 MLX5_MAD_IFC_NET_VIEW = 4, 89 }; 90 91 enum { 92 MLX5_CROSS_CHANNEL_BFREG = 0, 93 }; 94 95 enum { 96 MLX5_CQE_VERSION_V0, 97 MLX5_CQE_VERSION_V1, 98 }; 99 100 enum { 101 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 102 MLX5_TM_MAX_SGE = 1, 103 }; 104 105 enum { 106 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 107 MLX5_IB_INVALID_BFREG = BIT(31), 108 }; 109 110 enum { 111 MLX5_MAX_MEMIC_PAGES = 0x100, 112 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 113 }; 114 115 enum { 116 MLX5_MEMIC_BASE_ALIGN = 6, 117 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 118 }; 119 120 struct mlx5_ib_ucontext { 121 struct ib_ucontext ibucontext; 122 struct list_head db_page_list; 123 124 /* protect doorbell record alloc/free 125 */ 126 struct mutex db_page_mutex; 127 struct mlx5_bfreg_info bfregi; 128 u8 cqe_version; 129 /* Transport Domain number */ 130 u32 tdn; 131 132 u64 lib_caps; 133 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); 134 u16 devx_uid; 135 /* For RoCE LAG TX affinity */ 136 atomic_t tx_port_affinity; 137 }; 138 139 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 140 { 141 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 142 } 143 144 struct mlx5_ib_pd { 145 struct ib_pd ibpd; 146 u32 pdn; 147 u16 uid; 148 }; 149 150 enum { 151 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 152 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 153 MLX5_IB_FLOW_ACTION_DECAP, 154 }; 155 156 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 157 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 158 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 159 #error "Invalid number of bypass priorities" 160 #endif 161 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 162 163 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 164 #define MLX5_IB_NUM_SNIFFER_FTS 2 165 #define MLX5_IB_NUM_EGRESS_FTS 1 166 struct mlx5_ib_flow_prio { 167 struct mlx5_flow_table *flow_table; 168 unsigned int refcount; 169 }; 170 171 struct mlx5_ib_flow_handler { 172 struct list_head list; 173 struct ib_flow ibflow; 174 struct mlx5_ib_flow_prio *prio; 175 struct mlx5_flow_handle *rule; 176 struct ib_counters *ibcounters; 177 struct mlx5_ib_dev *dev; 178 struct mlx5_ib_flow_matcher *flow_matcher; 179 }; 180 181 struct mlx5_ib_flow_matcher { 182 struct mlx5_ib_match_params matcher_mask; 183 int mask_len; 184 enum mlx5_ib_flow_type flow_type; 185 enum mlx5_flow_namespace_type ns_type; 186 u16 priority; 187 struct mlx5_core_dev *mdev; 188 atomic_t usecnt; 189 u8 match_criteria_enable; 190 }; 191 192 struct mlx5_ib_flow_db { 193 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 194 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 195 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 196 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 197 struct mlx5_flow_table *lag_demux_ft; 198 /* Protect flow steering bypass flow tables 199 * when add/del flow rules. 200 * only single add/removal of flow steering rule could be done 201 * simultaneously. 202 */ 203 struct mutex lock; 204 }; 205 206 /* Use macros here so that don't have to duplicate 207 * enum ib_send_flags and enum ib_qp_type for low-level driver 208 */ 209 210 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 211 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 212 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 213 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 214 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 215 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 216 217 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 218 /* 219 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 220 * creates the actual hardware QP. 221 */ 222 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 223 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 224 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 225 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 226 227 #define MLX5_IB_UMR_OCTOWORD 16 228 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 229 230 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 231 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 232 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 233 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 234 #define MLX5_IB_UPD_XLT_PD BIT(4) 235 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 236 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 237 238 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 239 * 240 * These flags are intended for internal use by the mlx5_ib driver, and they 241 * rely on the range reserved for that use in the ib_qp_create_flags enum. 242 */ 243 244 /* Create a UD QP whose source QP number is 1 */ 245 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) 246 { 247 return IB_QP_CREATE_RESERVED_START; 248 } 249 250 struct wr_list { 251 u16 opcode; 252 u16 next; 253 }; 254 255 enum mlx5_ib_rq_flags { 256 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 257 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 258 }; 259 260 struct mlx5_ib_wq { 261 u64 *wrid; 262 u32 *wr_data; 263 struct wr_list *w_list; 264 unsigned *wqe_head; 265 u16 unsig_count; 266 267 /* serialize post to the work queue 268 */ 269 spinlock_t lock; 270 int wqe_cnt; 271 int max_post; 272 int max_gs; 273 int offset; 274 int wqe_shift; 275 unsigned head; 276 unsigned tail; 277 u16 cur_post; 278 u16 last_poll; 279 void *qend; 280 }; 281 282 enum mlx5_ib_wq_flags { 283 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 284 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 285 }; 286 287 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 288 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 289 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 290 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 291 292 struct mlx5_ib_rwq { 293 struct ib_wq ibwq; 294 struct mlx5_core_qp core_qp; 295 u32 rq_num_pas; 296 u32 log_rq_stride; 297 u32 log_rq_size; 298 u32 rq_page_offset; 299 u32 log_page_size; 300 u32 log_num_strides; 301 u32 two_byte_shift_en; 302 u32 single_stride_log_num_of_bytes; 303 struct ib_umem *umem; 304 size_t buf_size; 305 unsigned int page_shift; 306 int create_type; 307 struct mlx5_db db; 308 u32 user_index; 309 u32 wqe_count; 310 u32 wqe_shift; 311 int wq_sig; 312 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 313 }; 314 315 enum { 316 MLX5_QP_USER, 317 MLX5_QP_KERNEL, 318 MLX5_QP_EMPTY 319 }; 320 321 enum { 322 MLX5_WQ_USER, 323 MLX5_WQ_KERNEL 324 }; 325 326 struct mlx5_ib_rwq_ind_table { 327 struct ib_rwq_ind_table ib_rwq_ind_tbl; 328 u32 rqtn; 329 u16 uid; 330 }; 331 332 struct mlx5_ib_ubuffer { 333 struct ib_umem *umem; 334 int buf_size; 335 u64 buf_addr; 336 }; 337 338 struct mlx5_ib_qp_base { 339 struct mlx5_ib_qp *container_mibqp; 340 struct mlx5_core_qp mqp; 341 struct mlx5_ib_ubuffer ubuffer; 342 }; 343 344 struct mlx5_ib_qp_trans { 345 struct mlx5_ib_qp_base base; 346 u16 xrcdn; 347 u8 alt_port; 348 u8 atomic_rd_en; 349 u8 resp_depth; 350 }; 351 352 struct mlx5_ib_rss_qp { 353 u32 tirn; 354 }; 355 356 struct mlx5_ib_rq { 357 struct mlx5_ib_qp_base base; 358 struct mlx5_ib_wq *rq; 359 struct mlx5_ib_ubuffer ubuffer; 360 struct mlx5_db *doorbell; 361 u32 tirn; 362 u8 state; 363 u32 flags; 364 }; 365 366 struct mlx5_ib_sq { 367 struct mlx5_ib_qp_base base; 368 struct mlx5_ib_wq *sq; 369 struct mlx5_ib_ubuffer ubuffer; 370 struct mlx5_db *doorbell; 371 struct mlx5_flow_handle *flow_rule; 372 u32 tisn; 373 u8 state; 374 }; 375 376 struct mlx5_ib_raw_packet_qp { 377 struct mlx5_ib_sq sq; 378 struct mlx5_ib_rq rq; 379 }; 380 381 struct mlx5_bf { 382 int buf_size; 383 unsigned long offset; 384 struct mlx5_sq_bfreg *bfreg; 385 }; 386 387 struct mlx5_ib_dct { 388 struct mlx5_core_dct mdct; 389 u32 *in; 390 }; 391 392 struct mlx5_ib_qp { 393 struct ib_qp ibqp; 394 union { 395 struct mlx5_ib_qp_trans trans_qp; 396 struct mlx5_ib_raw_packet_qp raw_packet_qp; 397 struct mlx5_ib_rss_qp rss_qp; 398 struct mlx5_ib_dct dct; 399 }; 400 struct mlx5_frag_buf buf; 401 402 struct mlx5_db db; 403 struct mlx5_ib_wq rq; 404 405 u8 sq_signal_bits; 406 u8 next_fence; 407 struct mlx5_ib_wq sq; 408 409 /* serialize qp state modifications 410 */ 411 struct mutex mutex; 412 u32 flags; 413 u8 port; 414 u8 state; 415 int wq_sig; 416 int scat_cqe; 417 int max_inline_data; 418 struct mlx5_bf bf; 419 int has_rq; 420 421 /* only for user space QPs. For kernel 422 * we have it from the bf object 423 */ 424 int bfregn; 425 426 int create_type; 427 428 /* Store signature errors */ 429 bool signature_en; 430 431 struct list_head qps_list; 432 struct list_head cq_recv_list; 433 struct list_head cq_send_list; 434 struct mlx5_rate_limit rl; 435 u32 underlay_qpn; 436 u32 flags_en; 437 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 438 enum ib_qp_type qp_sub_type; 439 }; 440 441 struct mlx5_ib_cq_buf { 442 struct mlx5_frag_buf_ctrl fbc; 443 struct mlx5_frag_buf frag_buf; 444 struct ib_umem *umem; 445 int cqe_size; 446 int nent; 447 }; 448 449 enum mlx5_ib_qp_flags { 450 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 451 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 452 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 453 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 454 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 455 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 456 /* QP uses 1 as its source QP number */ 457 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 458 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 459 MLX5_IB_QP_RSS = 1 << 8, 460 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 461 MLX5_IB_QP_UNDERLAY = 1 << 10, 462 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 463 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 464 }; 465 466 struct mlx5_umr_wr { 467 struct ib_send_wr wr; 468 u64 virt_addr; 469 u64 offset; 470 struct ib_pd *pd; 471 unsigned int page_shift; 472 unsigned int xlt_size; 473 u64 length; 474 int access_flags; 475 u32 mkey; 476 }; 477 478 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 479 { 480 return container_of(wr, struct mlx5_umr_wr, wr); 481 } 482 483 struct mlx5_shared_mr_info { 484 int mr_id; 485 struct ib_umem *umem; 486 }; 487 488 enum mlx5_ib_cq_pr_flags { 489 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 490 }; 491 492 struct mlx5_ib_cq { 493 struct ib_cq ibcq; 494 struct mlx5_core_cq mcq; 495 struct mlx5_ib_cq_buf buf; 496 struct mlx5_db db; 497 498 /* serialize access to the CQ 499 */ 500 spinlock_t lock; 501 502 /* protect resize cq 503 */ 504 struct mutex resize_mutex; 505 struct mlx5_ib_cq_buf *resize_buf; 506 struct ib_umem *resize_umem; 507 int cqe_size; 508 struct list_head list_send_qp; 509 struct list_head list_recv_qp; 510 u32 create_flags; 511 struct list_head wc_list; 512 enum ib_cq_notify_flags notify_flags; 513 struct work_struct notify_work; 514 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 515 }; 516 517 struct mlx5_ib_wc { 518 struct ib_wc wc; 519 struct list_head list; 520 }; 521 522 struct mlx5_ib_srq { 523 struct ib_srq ibsrq; 524 struct mlx5_core_srq msrq; 525 struct mlx5_frag_buf buf; 526 struct mlx5_db db; 527 u64 *wrid; 528 /* protect SRQ hanlding 529 */ 530 spinlock_t lock; 531 int head; 532 int tail; 533 u16 wqe_ctr; 534 struct ib_umem *umem; 535 /* serialize arming a SRQ 536 */ 537 struct mutex mutex; 538 int wq_sig; 539 }; 540 541 struct mlx5_ib_xrcd { 542 struct ib_xrcd ibxrcd; 543 u32 xrcdn; 544 u16 uid; 545 }; 546 547 enum mlx5_ib_mtt_access_flags { 548 MLX5_IB_MTT_READ = (1 << 0), 549 MLX5_IB_MTT_WRITE = (1 << 1), 550 }; 551 552 struct mlx5_ib_dm { 553 struct ib_dm ibdm; 554 phys_addr_t dev_addr; 555 }; 556 557 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 558 559 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 560 IB_ACCESS_REMOTE_WRITE |\ 561 IB_ACCESS_REMOTE_READ |\ 562 IB_ACCESS_REMOTE_ATOMIC |\ 563 IB_ZERO_BASED) 564 565 struct mlx5_ib_mr { 566 struct ib_mr ibmr; 567 void *descs; 568 dma_addr_t desc_map; 569 int ndescs; 570 int max_descs; 571 int desc_size; 572 int access_mode; 573 struct mlx5_core_mkey mmkey; 574 struct ib_umem *umem; 575 struct mlx5_shared_mr_info *smr_info; 576 struct list_head list; 577 int order; 578 bool allocated_from_cache; 579 int npages; 580 struct mlx5_ib_dev *dev; 581 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 582 struct mlx5_core_sig_ctx *sig; 583 int live; 584 void *descs_alloc; 585 int access_flags; /* Needed for rereg MR */ 586 587 struct mlx5_ib_mr *parent; 588 atomic_t num_leaf_free; 589 wait_queue_head_t q_leaf_free; 590 }; 591 592 struct mlx5_ib_mw { 593 struct ib_mw ibmw; 594 struct mlx5_core_mkey mmkey; 595 int ndescs; 596 }; 597 598 struct mlx5_ib_umr_context { 599 struct ib_cqe cqe; 600 enum ib_wc_status status; 601 struct completion done; 602 }; 603 604 struct umr_common { 605 struct ib_pd *pd; 606 struct ib_cq *cq; 607 struct ib_qp *qp; 608 /* control access to UMR QP 609 */ 610 struct semaphore sem; 611 }; 612 613 enum { 614 MLX5_FMR_INVALID, 615 MLX5_FMR_VALID, 616 MLX5_FMR_BUSY, 617 }; 618 619 struct mlx5_cache_ent { 620 struct list_head head; 621 /* sync access to the cahce entry 622 */ 623 spinlock_t lock; 624 625 626 struct dentry *dir; 627 char name[4]; 628 u32 order; 629 u32 xlt; 630 u32 access_mode; 631 u32 page; 632 633 u32 size; 634 u32 cur; 635 u32 miss; 636 u32 limit; 637 638 struct dentry *fsize; 639 struct dentry *fcur; 640 struct dentry *fmiss; 641 struct dentry *flimit; 642 643 struct mlx5_ib_dev *dev; 644 struct work_struct work; 645 struct delayed_work dwork; 646 int pending; 647 struct completion compl; 648 }; 649 650 struct mlx5_mr_cache { 651 struct workqueue_struct *wq; 652 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 653 int stopped; 654 struct dentry *root; 655 unsigned long last_add; 656 }; 657 658 struct mlx5_ib_gsi_qp; 659 660 struct mlx5_ib_port_resources { 661 struct mlx5_ib_resources *devr; 662 struct mlx5_ib_gsi_qp *gsi; 663 struct work_struct pkey_change_work; 664 }; 665 666 struct mlx5_ib_resources { 667 struct ib_cq *c0; 668 struct ib_xrcd *x0; 669 struct ib_xrcd *x1; 670 struct ib_pd *p0; 671 struct ib_srq *s0; 672 struct ib_srq *s1; 673 struct mlx5_ib_port_resources ports[2]; 674 /* Protects changes to the port resources */ 675 struct mutex mutex; 676 }; 677 678 struct mlx5_ib_counters { 679 const char **names; 680 size_t *offsets; 681 u32 num_q_counters; 682 u32 num_cong_counters; 683 u32 num_ext_ppcnt_counters; 684 u16 set_id; 685 bool set_id_valid; 686 }; 687 688 struct mlx5_ib_multiport_info; 689 690 struct mlx5_ib_multiport { 691 struct mlx5_ib_multiport_info *mpi; 692 /* To be held when accessing the multiport info */ 693 spinlock_t mpi_lock; 694 }; 695 696 struct mlx5_ib_port { 697 struct mlx5_ib_counters cnts; 698 struct mlx5_ib_multiport mp; 699 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 700 }; 701 702 struct mlx5_roce { 703 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 704 * netdev pointer 705 */ 706 rwlock_t netdev_lock; 707 struct net_device *netdev; 708 struct notifier_block nb; 709 atomic_t tx_port_affinity; 710 enum ib_port_state last_port_state; 711 struct mlx5_ib_dev *dev; 712 u8 native_port_num; 713 }; 714 715 struct mlx5_ib_dbg_param { 716 int offset; 717 struct mlx5_ib_dev *dev; 718 struct dentry *dentry; 719 u8 port_num; 720 }; 721 722 enum mlx5_ib_dbg_cc_types { 723 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 724 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 725 MLX5_IB_DBG_CC_RP_TIME_RESET, 726 MLX5_IB_DBG_CC_RP_BYTE_RESET, 727 MLX5_IB_DBG_CC_RP_THRESHOLD, 728 MLX5_IB_DBG_CC_RP_AI_RATE, 729 MLX5_IB_DBG_CC_RP_HAI_RATE, 730 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 731 MLX5_IB_DBG_CC_RP_MIN_RATE, 732 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 733 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 734 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 735 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 736 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 737 MLX5_IB_DBG_CC_RP_GD, 738 MLX5_IB_DBG_CC_NP_CNP_DSCP, 739 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 740 MLX5_IB_DBG_CC_NP_CNP_PRIO, 741 MLX5_IB_DBG_CC_MAX, 742 }; 743 744 struct mlx5_ib_dbg_cc_params { 745 struct dentry *root; 746 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 747 }; 748 749 enum { 750 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 751 }; 752 753 struct mlx5_ib_dbg_delay_drop { 754 struct dentry *dir_debugfs; 755 struct dentry *rqs_cnt_debugfs; 756 struct dentry *events_cnt_debugfs; 757 struct dentry *timeout_debugfs; 758 }; 759 760 struct mlx5_ib_delay_drop { 761 struct mlx5_ib_dev *dev; 762 struct work_struct delay_drop_work; 763 /* serialize setting of delay drop */ 764 struct mutex lock; 765 u32 timeout; 766 bool activate; 767 atomic_t events_cnt; 768 atomic_t rqs_cnt; 769 struct mlx5_ib_dbg_delay_drop *dbg; 770 }; 771 772 enum mlx5_ib_stages { 773 MLX5_IB_STAGE_INIT, 774 MLX5_IB_STAGE_FLOW_DB, 775 MLX5_IB_STAGE_CAPS, 776 MLX5_IB_STAGE_NON_DEFAULT_CB, 777 MLX5_IB_STAGE_ROCE, 778 MLX5_IB_STAGE_SRQ, 779 MLX5_IB_STAGE_DEVICE_RESOURCES, 780 MLX5_IB_STAGE_DEVICE_NOTIFIER, 781 MLX5_IB_STAGE_ODP, 782 MLX5_IB_STAGE_COUNTERS, 783 MLX5_IB_STAGE_CONG_DEBUGFS, 784 MLX5_IB_STAGE_UAR, 785 MLX5_IB_STAGE_BFREG, 786 MLX5_IB_STAGE_PRE_IB_REG_UMR, 787 MLX5_IB_STAGE_SPECS, 788 MLX5_IB_STAGE_WHITELIST_UID, 789 MLX5_IB_STAGE_IB_REG, 790 MLX5_IB_STAGE_POST_IB_REG_UMR, 791 MLX5_IB_STAGE_DELAY_DROP, 792 MLX5_IB_STAGE_CLASS_ATTR, 793 MLX5_IB_STAGE_MAX, 794 }; 795 796 struct mlx5_ib_stage { 797 int (*init)(struct mlx5_ib_dev *dev); 798 void (*cleanup)(struct mlx5_ib_dev *dev); 799 }; 800 801 #define STAGE_CREATE(_stage, _init, _cleanup) \ 802 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 803 804 struct mlx5_ib_profile { 805 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 806 }; 807 808 struct mlx5_ib_multiport_info { 809 struct list_head list; 810 struct mlx5_ib_dev *ibdev; 811 struct mlx5_core_dev *mdev; 812 struct notifier_block mdev_events; 813 struct completion unref_comp; 814 u64 sys_image_guid; 815 u32 mdev_refcnt; 816 bool is_master; 817 bool unaffiliate; 818 }; 819 820 struct mlx5_ib_flow_action { 821 struct ib_flow_action ib_action; 822 union { 823 struct { 824 u64 ib_flags; 825 struct mlx5_accel_esp_xfrm *ctx; 826 } esp_aes_gcm; 827 struct { 828 struct mlx5_ib_dev *dev; 829 u32 sub_type; 830 u32 action_id; 831 } flow_action_raw; 832 }; 833 }; 834 835 struct mlx5_memic { 836 struct mlx5_core_dev *dev; 837 spinlock_t memic_lock; 838 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 839 }; 840 841 struct mlx5_read_counters_attr { 842 struct mlx5_fc *hw_cntrs_hndl; 843 u64 *out; 844 u32 flags; 845 }; 846 847 enum mlx5_ib_counters_type { 848 MLX5_IB_COUNTERS_FLOW, 849 }; 850 851 struct mlx5_ib_mcounters { 852 struct ib_counters ibcntrs; 853 enum mlx5_ib_counters_type type; 854 /* number of counters supported for this counters type */ 855 u32 counters_num; 856 struct mlx5_fc *hw_cntrs_hndl; 857 /* read function for this counters type */ 858 int (*read_counters)(struct ib_device *ibdev, 859 struct mlx5_read_counters_attr *read_attr); 860 /* max index set as part of create_flow */ 861 u32 cntrs_max_index; 862 /* number of counters data entries (<description,index> pair) */ 863 u32 ncounters; 864 /* counters data array for descriptions and indexes */ 865 struct mlx5_ib_flow_counters_desc *counters_data; 866 /* protects access to mcounters internal data */ 867 struct mutex mcntrs_mutex; 868 }; 869 870 static inline struct mlx5_ib_mcounters * 871 to_mcounters(struct ib_counters *ibcntrs) 872 { 873 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 874 } 875 876 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 877 bool is_egress, 878 struct mlx5_flow_act *action); 879 struct mlx5_ib_lb_state { 880 /* protect the user_td */ 881 struct mutex mutex; 882 u32 user_td; 883 int qps; 884 bool enabled; 885 }; 886 887 struct mlx5_ib_pf_eq { 888 struct mlx5_ib_dev *dev; 889 struct mlx5_eq *core; 890 struct work_struct work; 891 spinlock_t lock; /* Pagefaults spinlock */ 892 struct workqueue_struct *wq; 893 mempool_t *pool; 894 }; 895 896 struct mlx5_ib_dev { 897 struct ib_device ib_dev; 898 const struct uverbs_object_tree_def *driver_trees[7]; 899 struct mlx5_core_dev *mdev; 900 struct notifier_block mdev_events; 901 struct mlx5_roce roce[MLX5_MAX_PORTS]; 902 int num_ports; 903 /* serialize update of capability mask 904 */ 905 struct mutex cap_mask_mutex; 906 bool ib_active; 907 struct umr_common umrc; 908 /* sync used page count stats 909 */ 910 struct mlx5_ib_resources devr; 911 struct mlx5_mr_cache cache; 912 struct timer_list delay_timer; 913 /* Prevents soft lock on massive reg MRs */ 914 struct mutex slow_path_mutex; 915 int fill_delay; 916 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 917 struct ib_odp_caps odp_caps; 918 u64 odp_max_size; 919 struct mlx5_ib_pf_eq odp_pf_eq; 920 921 /* 922 * Sleepable RCU that prevents destruction of MRs while they are still 923 * being used by a page fault handler. 924 */ 925 struct srcu_struct mr_srcu; 926 u32 null_mkey; 927 #endif 928 struct mlx5_ib_flow_db *flow_db; 929 /* protect resources needed as part of reset flow */ 930 spinlock_t reset_flow_resource_lock; 931 struct list_head qp_list; 932 /* Array with num_ports elements */ 933 struct mlx5_ib_port *port; 934 struct mlx5_sq_bfreg bfreg; 935 struct mlx5_sq_bfreg fp_bfreg; 936 struct mlx5_ib_delay_drop delay_drop; 937 const struct mlx5_ib_profile *profile; 938 struct mlx5_eswitch_rep *rep; 939 int lag_active; 940 941 struct mlx5_ib_lb_state lb; 942 u8 umr_fence; 943 struct list_head ib_dev_list; 944 u64 sys_image_guid; 945 struct mlx5_memic memic; 946 u16 devx_whitelist_uid; 947 struct mlx5_srq_table srq_table; 948 }; 949 950 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 951 { 952 return container_of(mcq, struct mlx5_ib_cq, mcq); 953 } 954 955 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 956 { 957 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 958 } 959 960 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 961 { 962 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 963 } 964 965 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 966 { 967 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 968 } 969 970 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 971 { 972 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 973 } 974 975 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 976 { 977 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 978 } 979 980 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 981 { 982 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 983 } 984 985 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 986 { 987 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 988 } 989 990 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 991 { 992 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 993 } 994 995 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 996 { 997 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 998 } 999 1000 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1001 { 1002 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1003 } 1004 1005 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1006 { 1007 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1008 } 1009 1010 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1011 { 1012 return container_of(msrq, struct mlx5_ib_srq, msrq); 1013 } 1014 1015 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1016 { 1017 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1018 } 1019 1020 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1021 { 1022 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1023 } 1024 1025 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1026 { 1027 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1028 } 1029 1030 static inline struct mlx5_ib_flow_action * 1031 to_mflow_act(struct ib_flow_action *ibact) 1032 { 1033 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1034 } 1035 1036 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1037 struct mlx5_db *db); 1038 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1039 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1040 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1041 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1042 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 1043 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1044 const void *in_mad, void *response_mad); 1045 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 1046 struct ib_udata *udata); 1047 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1048 int mlx5_ib_destroy_ah(struct ib_ah *ah); 1049 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 1050 struct ib_srq_init_attr *init_attr, 1051 struct ib_udata *udata); 1052 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1053 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1054 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1055 int mlx5_ib_destroy_srq(struct ib_srq *srq); 1056 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1057 const struct ib_recv_wr **bad_wr); 1058 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1059 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1060 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1061 struct ib_qp_init_attr *init_attr, 1062 struct ib_udata *udata); 1063 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1064 int attr_mask, struct ib_udata *udata); 1065 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1066 struct ib_qp_init_attr *qp_init_attr); 1067 int mlx5_ib_destroy_qp(struct ib_qp *qp); 1068 void mlx5_ib_drain_sq(struct ib_qp *qp); 1069 void mlx5_ib_drain_rq(struct ib_qp *qp); 1070 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1071 const struct ib_send_wr **bad_wr); 1072 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1073 const struct ib_recv_wr **bad_wr); 1074 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 1075 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 1076 void *buffer, u32 length, 1077 struct mlx5_ib_qp_base *base); 1078 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 1079 const struct ib_cq_init_attr *attr, 1080 struct ib_ucontext *context, 1081 struct ib_udata *udata); 1082 int mlx5_ib_destroy_cq(struct ib_cq *cq); 1083 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1084 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1085 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1086 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1087 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1088 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1089 u64 virt_addr, int access_flags, 1090 struct ib_udata *udata); 1091 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1092 struct ib_udata *udata); 1093 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1094 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1095 int page_shift, int flags); 1096 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1097 int access_flags); 1098 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1099 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1100 u64 length, u64 virt_addr, int access_flags, 1101 struct ib_pd *pd, struct ib_udata *udata); 1102 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 1103 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 1104 enum ib_mr_type mr_type, 1105 u32 max_num_sg); 1106 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1107 unsigned int *sg_offset); 1108 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1109 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1110 const struct ib_mad_hdr *in, size_t in_mad_size, 1111 struct ib_mad_hdr *out, size_t *out_mad_size, 1112 u16 *out_mad_pkey_index); 1113 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1114 struct ib_ucontext *context, 1115 struct ib_udata *udata); 1116 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 1117 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1118 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1119 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1120 struct ib_smp *out_mad); 1121 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1122 __be64 *sys_image_guid); 1123 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1124 u16 *max_pkeys); 1125 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1126 u32 *vendor_id); 1127 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1128 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1129 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1130 u16 *pkey); 1131 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1132 union ib_gid *gid); 1133 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1134 struct ib_port_attr *props); 1135 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1136 struct ib_port_attr *props); 1137 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1138 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1139 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1140 unsigned long max_page_shift, 1141 int *count, int *shift, 1142 int *ncont, int *order); 1143 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1144 int page_shift, size_t offset, size_t num_pages, 1145 __be64 *pas, int access_flags); 1146 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1147 int page_shift, __be64 *pas, int access_flags); 1148 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1149 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1150 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1151 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1152 1153 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1154 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1155 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1156 struct ib_mr_status *mr_status); 1157 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1158 struct ib_wq_init_attr *init_attr, 1159 struct ib_udata *udata); 1160 int mlx5_ib_destroy_wq(struct ib_wq *wq); 1161 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1162 u32 wq_attr_mask, struct ib_udata *udata); 1163 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1164 struct ib_rwq_ind_table_init_attr *init_attr, 1165 struct ib_udata *udata); 1166 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1167 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); 1168 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1169 struct ib_ucontext *context, 1170 struct ib_dm_alloc_attr *attr, 1171 struct uverbs_attr_bundle *attrs); 1172 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm); 1173 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1174 struct ib_dm_mr_attr *attr, 1175 struct uverbs_attr_bundle *attrs); 1176 1177 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1178 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1179 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1180 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1181 int __init mlx5_ib_odp_init(void); 1182 void mlx5_ib_odp_cleanup(void); 1183 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start, 1184 unsigned long end); 1185 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1186 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1187 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1188 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1189 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1190 { 1191 return; 1192 } 1193 1194 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1195 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1196 static inline int mlx5_ib_odp_init(void) { return 0; } 1197 static inline void mlx5_ib_odp_cleanup(void) {} 1198 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1199 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1200 size_t nentries, struct mlx5_ib_mr *mr, 1201 int flags) {} 1202 1203 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1204 1205 /* Needed for rep profile */ 1206 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); 1207 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); 1208 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); 1209 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); 1210 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); 1211 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); 1212 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); 1213 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); 1214 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); 1215 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); 1216 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); 1217 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); 1218 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); 1219 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); 1220 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); 1221 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); 1222 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); 1223 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1224 const struct mlx5_ib_profile *profile, 1225 int stage); 1226 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1227 const struct mlx5_ib_profile *profile); 1228 1229 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1230 u8 port, struct ifla_vf_info *info); 1231 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1232 u8 port, int state); 1233 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1234 u8 port, struct ifla_vf_stats *stats); 1235 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1236 u64 guid, int type); 1237 1238 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1239 const struct ib_gid_attr *attr); 1240 1241 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1242 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1243 1244 /* GSI QP helper functions */ 1245 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1246 struct ib_qp_init_attr *init_attr); 1247 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1248 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1249 int attr_mask); 1250 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1251 int qp_attr_mask, 1252 struct ib_qp_init_attr *qp_init_attr); 1253 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1254 const struct ib_send_wr **bad_wr); 1255 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1256 const struct ib_recv_wr **bad_wr); 1257 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1258 1259 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1260 1261 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1262 int bfregn); 1263 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1265 u8 ib_port_num, 1266 u8 *native_port_num); 1267 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1268 u8 port_num); 1269 1270 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1271 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev); 1272 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1273 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); 1274 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1275 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1276 struct mlx5_flow_act *flow_act, void *cmd_in, int inlen, 1277 int dest_id, int dest_type); 1278 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1279 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root); 1280 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1281 #else 1282 static inline int 1283 mlx5_ib_devx_create(struct mlx5_ib_dev *dev) { return -EOPNOTSUPP; }; 1284 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1285 static inline const struct uverbs_object_tree_def * 1286 mlx5_ib_get_devx_tree(void) { return NULL; } 1287 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1288 int *dest_type) 1289 { 1290 return false; 1291 } 1292 static inline int 1293 mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root) 1294 { 1295 return 0; 1296 } 1297 static inline void 1298 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1299 { 1300 return; 1301 }; 1302 #endif 1303 static inline void init_query_mad(struct ib_smp *mad) 1304 { 1305 mad->base_version = 1; 1306 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1307 mad->class_version = 1; 1308 mad->method = IB_MGMT_METHOD_GET; 1309 } 1310 1311 static inline u8 convert_access(int acc) 1312 { 1313 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1314 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1315 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1316 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1317 MLX5_PERM_LOCAL_READ; 1318 } 1319 1320 static inline int is_qp1(enum ib_qp_type qp_type) 1321 { 1322 return qp_type == MLX5_IB_QPT_HW_GSI; 1323 } 1324 1325 #define MLX5_MAX_UMR_SHIFT 16 1326 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1327 1328 static inline u32 check_cq_create_flags(u32 flags) 1329 { 1330 /* 1331 * It returns non-zero value for unsupported CQ 1332 * create flags, otherwise it returns zero. 1333 */ 1334 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1335 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1336 } 1337 1338 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1339 u32 *user_index) 1340 { 1341 if (cqe_version) { 1342 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1343 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1344 return -EINVAL; 1345 *user_index = cmd_uidx; 1346 } else { 1347 *user_index = MLX5_IB_DEFAULT_UIDX; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1354 struct mlx5_ib_create_qp *ucmd, 1355 int inlen, 1356 u32 *user_index) 1357 { 1358 u8 cqe_version = ucontext->cqe_version; 1359 1360 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1361 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1362 return 0; 1363 1364 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1365 !!cqe_version)) 1366 return -EINVAL; 1367 1368 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1369 } 1370 1371 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1372 struct mlx5_ib_create_srq *ucmd, 1373 int inlen, 1374 u32 *user_index) 1375 { 1376 u8 cqe_version = ucontext->cqe_version; 1377 1378 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1379 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1380 return 0; 1381 1382 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1383 !!cqe_version)) 1384 return -EINVAL; 1385 1386 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1387 } 1388 1389 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1390 { 1391 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1392 MLX5_UARS_IN_PAGE : 1; 1393 } 1394 1395 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1396 struct mlx5_bfreg_info *bfregi) 1397 { 1398 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1399 } 1400 1401 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1402 void mlx5_ib_put_xlt_emergency_page(void); 1403 1404 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1405 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1406 bool dyn_bfreg); 1407 #endif /* MLX5_IB_H */ 1408