1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_smi.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 53 #include "srq.h" 54 55 #define mlx5_ib_dbg(_dev, format, arg...) \ 56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_err(_dev, format, arg...) \ 60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define mlx5_ib_warn(_dev, format, arg...) \ 64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 65 __LINE__, current->pid, ##arg) 66 67 #define MLX5_IB_DEFAULT_UIDX 0xffffff 68 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 69 70 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 71 72 enum { 73 MLX5_IB_MMAP_OFFSET_START = 9, 74 MLX5_IB_MMAP_OFFSET_END = 255, 75 }; 76 77 enum { 78 MLX5_IB_MMAP_CMD_SHIFT = 8, 79 MLX5_IB_MMAP_CMD_MASK = 0xff, 80 }; 81 82 enum { 83 MLX5_RES_SCAT_DATA32_CQE = 0x1, 84 MLX5_RES_SCAT_DATA64_CQE = 0x2, 85 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 86 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 87 }; 88 89 enum mlx5_ib_mad_ifc_flags { 90 MLX5_MAD_IFC_IGNORE_MKEY = 1, 91 MLX5_MAD_IFC_IGNORE_BKEY = 2, 92 MLX5_MAD_IFC_NET_VIEW = 4, 93 }; 94 95 enum { 96 MLX5_CROSS_CHANNEL_BFREG = 0, 97 }; 98 99 enum { 100 MLX5_CQE_VERSION_V0, 101 MLX5_CQE_VERSION_V1, 102 }; 103 104 enum { 105 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 106 MLX5_TM_MAX_SGE = 1, 107 }; 108 109 enum { 110 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 111 MLX5_IB_INVALID_BFREG = BIT(31), 112 }; 113 114 enum { 115 MLX5_MAX_MEMIC_PAGES = 0x100, 116 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 117 }; 118 119 enum { 120 MLX5_MEMIC_BASE_ALIGN = 6, 121 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 122 }; 123 124 enum mlx5_ib_mmap_type { 125 MLX5_IB_MMAP_TYPE_MEMIC = 1, 126 MLX5_IB_MMAP_TYPE_VAR = 2, 127 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 128 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 129 }; 130 131 struct mlx5_bfreg_info { 132 u32 *sys_pages; 133 int num_low_latency_bfregs; 134 unsigned int *count; 135 136 /* 137 * protect bfreg allocation data structs 138 */ 139 struct mutex lock; 140 u32 ver; 141 u8 lib_uar_4k : 1; 142 u8 lib_uar_dyn : 1; 143 u32 num_sys_pages; 144 u32 num_static_sys_pages; 145 u32 total_num_bfregs; 146 u32 num_dyn_bfregs; 147 }; 148 149 struct mlx5_ib_ucontext { 150 struct ib_ucontext ibucontext; 151 struct list_head db_page_list; 152 153 /* protect doorbell record alloc/free 154 */ 155 struct mutex db_page_mutex; 156 struct mlx5_bfreg_info bfregi; 157 u8 cqe_version; 158 /* Transport Domain number */ 159 u32 tdn; 160 161 u64 lib_caps; 162 u16 devx_uid; 163 /* For RoCE LAG TX affinity */ 164 atomic_t tx_port_affinity; 165 }; 166 167 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 168 { 169 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 170 } 171 172 struct mlx5_ib_pd { 173 struct ib_pd ibpd; 174 u32 pdn; 175 u16 uid; 176 }; 177 178 enum { 179 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 180 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 181 MLX5_IB_FLOW_ACTION_DECAP, 182 }; 183 184 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 185 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 186 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 187 #error "Invalid number of bypass priorities" 188 #endif 189 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 190 191 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 192 #define MLX5_IB_NUM_SNIFFER_FTS 2 193 #define MLX5_IB_NUM_EGRESS_FTS 1 194 struct mlx5_ib_flow_prio { 195 struct mlx5_flow_table *flow_table; 196 unsigned int refcount; 197 }; 198 199 struct mlx5_ib_flow_handler { 200 struct list_head list; 201 struct ib_flow ibflow; 202 struct mlx5_ib_flow_prio *prio; 203 struct mlx5_flow_handle *rule; 204 struct ib_counters *ibcounters; 205 struct mlx5_ib_dev *dev; 206 struct mlx5_ib_flow_matcher *flow_matcher; 207 }; 208 209 struct mlx5_ib_flow_matcher { 210 struct mlx5_ib_match_params matcher_mask; 211 int mask_len; 212 enum mlx5_ib_flow_type flow_type; 213 enum mlx5_flow_namespace_type ns_type; 214 u16 priority; 215 struct mlx5_core_dev *mdev; 216 atomic_t usecnt; 217 u8 match_criteria_enable; 218 }; 219 220 struct mlx5_ib_pp { 221 u16 index; 222 struct mlx5_core_dev *mdev; 223 }; 224 225 struct mlx5_ib_flow_db { 226 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 227 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 228 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 229 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 230 struct mlx5_ib_flow_prio fdb; 231 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 232 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 233 struct mlx5_flow_table *lag_demux_ft; 234 /* Protect flow steering bypass flow tables 235 * when add/del flow rules. 236 * only single add/removal of flow steering rule could be done 237 * simultaneously. 238 */ 239 struct mutex lock; 240 }; 241 242 /* Use macros here so that don't have to duplicate 243 * enum ib_send_flags and enum ib_qp_type for low-level driver 244 */ 245 246 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 247 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 248 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 249 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 250 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 251 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 252 253 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 254 /* 255 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 256 * creates the actual hardware QP. 257 */ 258 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 259 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 260 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 261 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 262 263 #define MLX5_IB_UMR_OCTOWORD 16 264 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 265 266 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 267 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 268 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 269 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 270 #define MLX5_IB_UPD_XLT_PD BIT(4) 271 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 272 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 273 274 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 275 * 276 * These flags are intended for internal use by the mlx5_ib driver, and they 277 * rely on the range reserved for that use in the ib_qp_create_flags enum. 278 */ 279 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 280 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 281 282 struct wr_list { 283 u16 opcode; 284 u16 next; 285 }; 286 287 enum mlx5_ib_rq_flags { 288 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 289 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 290 }; 291 292 struct mlx5_ib_wq { 293 struct mlx5_frag_buf_ctrl fbc; 294 u64 *wrid; 295 u32 *wr_data; 296 struct wr_list *w_list; 297 unsigned *wqe_head; 298 u16 unsig_count; 299 300 /* serialize post to the work queue 301 */ 302 spinlock_t lock; 303 int wqe_cnt; 304 int max_post; 305 int max_gs; 306 int offset; 307 int wqe_shift; 308 unsigned head; 309 unsigned tail; 310 u16 cur_post; 311 u16 last_poll; 312 void *cur_edge; 313 }; 314 315 enum mlx5_ib_wq_flags { 316 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 317 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 318 }; 319 320 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 321 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 322 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 323 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 324 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 325 326 struct mlx5_ib_rwq { 327 struct ib_wq ibwq; 328 struct mlx5_core_qp core_qp; 329 u32 rq_num_pas; 330 u32 log_rq_stride; 331 u32 log_rq_size; 332 u32 rq_page_offset; 333 u32 log_page_size; 334 u32 log_num_strides; 335 u32 two_byte_shift_en; 336 u32 single_stride_log_num_of_bytes; 337 struct ib_umem *umem; 338 size_t buf_size; 339 unsigned int page_shift; 340 struct mlx5_db db; 341 u32 user_index; 342 u32 wqe_count; 343 u32 wqe_shift; 344 int wq_sig; 345 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 346 }; 347 348 struct mlx5_ib_rwq_ind_table { 349 struct ib_rwq_ind_table ib_rwq_ind_tbl; 350 u32 rqtn; 351 u16 uid; 352 }; 353 354 struct mlx5_ib_ubuffer { 355 struct ib_umem *umem; 356 int buf_size; 357 u64 buf_addr; 358 }; 359 360 struct mlx5_ib_qp_base { 361 struct mlx5_ib_qp *container_mibqp; 362 struct mlx5_core_qp mqp; 363 struct mlx5_ib_ubuffer ubuffer; 364 }; 365 366 struct mlx5_ib_qp_trans { 367 struct mlx5_ib_qp_base base; 368 u16 xrcdn; 369 u8 alt_port; 370 u8 atomic_rd_en; 371 u8 resp_depth; 372 }; 373 374 struct mlx5_ib_rss_qp { 375 u32 tirn; 376 }; 377 378 struct mlx5_ib_rq { 379 struct mlx5_ib_qp_base base; 380 struct mlx5_ib_wq *rq; 381 struct mlx5_ib_ubuffer ubuffer; 382 struct mlx5_db *doorbell; 383 u32 tirn; 384 u8 state; 385 u32 flags; 386 }; 387 388 struct mlx5_ib_sq { 389 struct mlx5_ib_qp_base base; 390 struct mlx5_ib_wq *sq; 391 struct mlx5_ib_ubuffer ubuffer; 392 struct mlx5_db *doorbell; 393 struct mlx5_flow_handle *flow_rule; 394 u32 tisn; 395 u8 state; 396 }; 397 398 struct mlx5_ib_raw_packet_qp { 399 struct mlx5_ib_sq sq; 400 struct mlx5_ib_rq rq; 401 }; 402 403 struct mlx5_bf { 404 int buf_size; 405 unsigned long offset; 406 struct mlx5_sq_bfreg *bfreg; 407 }; 408 409 struct mlx5_ib_dct { 410 struct mlx5_core_dct mdct; 411 u32 *in; 412 }; 413 414 struct mlx5_ib_qp { 415 struct ib_qp ibqp; 416 union { 417 struct mlx5_ib_qp_trans trans_qp; 418 struct mlx5_ib_raw_packet_qp raw_packet_qp; 419 struct mlx5_ib_rss_qp rss_qp; 420 struct mlx5_ib_dct dct; 421 }; 422 struct mlx5_frag_buf buf; 423 424 struct mlx5_db db; 425 struct mlx5_ib_wq rq; 426 427 u8 sq_signal_bits; 428 u8 next_fence; 429 struct mlx5_ib_wq sq; 430 431 /* serialize qp state modifications 432 */ 433 struct mutex mutex; 434 /* cached variant of create_flags from struct ib_qp_init_attr */ 435 u32 flags; 436 u8 port; 437 u8 state; 438 int max_inline_data; 439 struct mlx5_bf bf; 440 u8 has_rq:1; 441 u8 is_rss:1; 442 443 /* only for user space QPs. For kernel 444 * we have it from the bf object 445 */ 446 int bfregn; 447 448 struct list_head qps_list; 449 struct list_head cq_recv_list; 450 struct list_head cq_send_list; 451 struct mlx5_rate_limit rl; 452 u32 underlay_qpn; 453 u32 flags_en; 454 /* 455 * IB/core doesn't store low-level QP types, so 456 * store both MLX and IBTA types in the field below. 457 * IB_QPT_DRIVER will be break to DCI/DCT subtypes. 458 */ 459 enum ib_qp_type type; 460 /* A flag to indicate if there's a new counter is configured 461 * but not take effective 462 */ 463 u32 counter_pending; 464 u16 gsi_lag_port; 465 }; 466 467 struct mlx5_ib_cq_buf { 468 struct mlx5_frag_buf_ctrl fbc; 469 struct mlx5_frag_buf frag_buf; 470 struct ib_umem *umem; 471 int cqe_size; 472 int nent; 473 }; 474 475 struct mlx5_umr_wr { 476 struct ib_send_wr wr; 477 u64 virt_addr; 478 u64 offset; 479 struct ib_pd *pd; 480 unsigned int page_shift; 481 unsigned int xlt_size; 482 u64 length; 483 int access_flags; 484 u32 mkey; 485 u8 ignore_free_state:1; 486 }; 487 488 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 489 { 490 return container_of(wr, struct mlx5_umr_wr, wr); 491 } 492 493 struct mlx5_shared_mr_info { 494 int mr_id; 495 struct ib_umem *umem; 496 }; 497 498 enum mlx5_ib_cq_pr_flags { 499 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 500 }; 501 502 struct mlx5_ib_cq { 503 struct ib_cq ibcq; 504 struct mlx5_core_cq mcq; 505 struct mlx5_ib_cq_buf buf; 506 struct mlx5_db db; 507 508 /* serialize access to the CQ 509 */ 510 spinlock_t lock; 511 512 /* protect resize cq 513 */ 514 struct mutex resize_mutex; 515 struct mlx5_ib_cq_buf *resize_buf; 516 struct ib_umem *resize_umem; 517 int cqe_size; 518 struct list_head list_send_qp; 519 struct list_head list_recv_qp; 520 u32 create_flags; 521 struct list_head wc_list; 522 enum ib_cq_notify_flags notify_flags; 523 struct work_struct notify_work; 524 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 525 }; 526 527 struct mlx5_ib_wc { 528 struct ib_wc wc; 529 struct list_head list; 530 }; 531 532 struct mlx5_ib_srq { 533 struct ib_srq ibsrq; 534 struct mlx5_core_srq msrq; 535 struct mlx5_frag_buf buf; 536 struct mlx5_db db; 537 struct mlx5_frag_buf_ctrl fbc; 538 u64 *wrid; 539 /* protect SRQ hanlding 540 */ 541 spinlock_t lock; 542 int head; 543 int tail; 544 u16 wqe_ctr; 545 struct ib_umem *umem; 546 /* serialize arming a SRQ 547 */ 548 struct mutex mutex; 549 int wq_sig; 550 }; 551 552 struct mlx5_ib_xrcd { 553 struct ib_xrcd ibxrcd; 554 u32 xrcdn; 555 }; 556 557 enum mlx5_ib_mtt_access_flags { 558 MLX5_IB_MTT_READ = (1 << 0), 559 MLX5_IB_MTT_WRITE = (1 << 1), 560 }; 561 562 struct mlx5_user_mmap_entry { 563 struct rdma_user_mmap_entry rdma_entry; 564 u8 mmap_flag; 565 u64 address; 566 u32 page_idx; 567 }; 568 569 struct mlx5_ib_dm { 570 struct ib_dm ibdm; 571 phys_addr_t dev_addr; 572 u32 type; 573 size_t size; 574 union { 575 struct { 576 u32 obj_id; 577 } icm_dm; 578 /* other dm types specific params should be added here */ 579 }; 580 struct mlx5_user_mmap_entry mentry; 581 }; 582 583 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 584 585 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 586 IB_ACCESS_REMOTE_WRITE |\ 587 IB_ACCESS_REMOTE_READ |\ 588 IB_ACCESS_REMOTE_ATOMIC |\ 589 IB_ZERO_BASED) 590 591 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 592 IB_ACCESS_REMOTE_WRITE |\ 593 IB_ACCESS_REMOTE_READ |\ 594 IB_ZERO_BASED) 595 596 #define mlx5_update_odp_stats(mr, counter_name, value) \ 597 atomic64_add(value, &((mr)->odp_stats.counter_name)) 598 599 struct mlx5_ib_mr { 600 struct ib_mr ibmr; 601 void *descs; 602 dma_addr_t desc_map; 603 int ndescs; 604 int data_length; 605 int meta_ndescs; 606 int meta_length; 607 int max_descs; 608 int desc_size; 609 int access_mode; 610 struct mlx5_core_mkey mmkey; 611 struct ib_umem *umem; 612 struct mlx5_shared_mr_info *smr_info; 613 struct list_head list; 614 unsigned int order; 615 struct mlx5_cache_ent *cache_ent; 616 int npages; 617 struct mlx5_ib_dev *dev; 618 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 619 struct mlx5_core_sig_ctx *sig; 620 void *descs_alloc; 621 int access_flags; /* Needed for rereg MR */ 622 623 struct mlx5_ib_mr *parent; 624 /* Needed for IB_MR_TYPE_INTEGRITY */ 625 struct mlx5_ib_mr *pi_mr; 626 struct mlx5_ib_mr *klm_mr; 627 struct mlx5_ib_mr *mtt_mr; 628 u64 data_iova; 629 u64 pi_iova; 630 631 /* For ODP and implicit */ 632 atomic_t num_deferred_work; 633 wait_queue_head_t q_deferred_work; 634 struct xarray implicit_children; 635 union { 636 struct rcu_head rcu; 637 struct list_head elm; 638 struct work_struct work; 639 } odp_destroy; 640 struct ib_odp_counters odp_stats; 641 bool is_odp_implicit; 642 643 struct mlx5_async_work cb_work; 644 }; 645 646 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 647 { 648 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 649 mr->umem->is_odp; 650 } 651 652 struct mlx5_ib_mw { 653 struct ib_mw ibmw; 654 struct mlx5_core_mkey mmkey; 655 int ndescs; 656 }; 657 658 struct mlx5_ib_devx_mr { 659 struct mlx5_core_mkey mmkey; 660 int ndescs; 661 }; 662 663 struct mlx5_ib_umr_context { 664 struct ib_cqe cqe; 665 enum ib_wc_status status; 666 struct completion done; 667 }; 668 669 struct umr_common { 670 struct ib_pd *pd; 671 struct ib_cq *cq; 672 struct ib_qp *qp; 673 /* control access to UMR QP 674 */ 675 struct semaphore sem; 676 }; 677 678 struct mlx5_cache_ent { 679 struct list_head head; 680 /* sync access to the cahce entry 681 */ 682 spinlock_t lock; 683 684 685 char name[4]; 686 u32 order; 687 u32 xlt; 688 u32 access_mode; 689 u32 page; 690 691 u8 disabled:1; 692 u8 fill_to_high_water:1; 693 694 /* 695 * - available_mrs is the length of list head, ie the number of MRs 696 * available for immediate allocation. 697 * - total_mrs is available_mrs plus all in use MRs that could be 698 * returned to the cache. 699 * - limit is the low water mark for available_mrs, 2* limit is the 700 * upper water mark. 701 * - pending is the number of MRs currently being created 702 */ 703 u32 total_mrs; 704 u32 available_mrs; 705 u32 limit; 706 u32 pending; 707 708 /* Statistics */ 709 u32 miss; 710 711 struct mlx5_ib_dev *dev; 712 struct work_struct work; 713 struct delayed_work dwork; 714 }; 715 716 struct mlx5_mr_cache { 717 struct workqueue_struct *wq; 718 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 719 struct dentry *root; 720 unsigned long last_add; 721 }; 722 723 struct mlx5_ib_gsi_qp; 724 725 struct mlx5_ib_port_resources { 726 struct mlx5_ib_resources *devr; 727 struct mlx5_ib_gsi_qp *gsi; 728 struct work_struct pkey_change_work; 729 }; 730 731 struct mlx5_ib_resources { 732 struct ib_cq *c0; 733 struct ib_xrcd *x0; 734 struct ib_xrcd *x1; 735 struct ib_pd *p0; 736 struct ib_srq *s0; 737 struct ib_srq *s1; 738 struct mlx5_ib_port_resources ports[2]; 739 /* Protects changes to the port resources */ 740 struct mutex mutex; 741 }; 742 743 struct mlx5_ib_counters { 744 const char **names; 745 size_t *offsets; 746 u32 num_q_counters; 747 u32 num_cong_counters; 748 u32 num_ext_ppcnt_counters; 749 u16 set_id; 750 }; 751 752 struct mlx5_ib_multiport_info; 753 754 struct mlx5_ib_multiport { 755 struct mlx5_ib_multiport_info *mpi; 756 /* To be held when accessing the multiport info */ 757 spinlock_t mpi_lock; 758 }; 759 760 struct mlx5_roce { 761 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 762 * netdev pointer 763 */ 764 rwlock_t netdev_lock; 765 struct net_device *netdev; 766 struct notifier_block nb; 767 atomic_t tx_port_affinity; 768 enum ib_port_state last_port_state; 769 struct mlx5_ib_dev *dev; 770 u8 native_port_num; 771 }; 772 773 struct mlx5_ib_port { 774 struct mlx5_ib_counters cnts; 775 struct mlx5_ib_multiport mp; 776 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 777 struct mlx5_roce roce; 778 struct mlx5_eswitch_rep *rep; 779 }; 780 781 struct mlx5_ib_dbg_param { 782 int offset; 783 struct mlx5_ib_dev *dev; 784 struct dentry *dentry; 785 u8 port_num; 786 }; 787 788 enum mlx5_ib_dbg_cc_types { 789 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 790 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 791 MLX5_IB_DBG_CC_RP_TIME_RESET, 792 MLX5_IB_DBG_CC_RP_BYTE_RESET, 793 MLX5_IB_DBG_CC_RP_THRESHOLD, 794 MLX5_IB_DBG_CC_RP_AI_RATE, 795 MLX5_IB_DBG_CC_RP_MAX_RATE, 796 MLX5_IB_DBG_CC_RP_HAI_RATE, 797 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 798 MLX5_IB_DBG_CC_RP_MIN_RATE, 799 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 800 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 801 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 802 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 803 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 804 MLX5_IB_DBG_CC_RP_GD, 805 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 806 MLX5_IB_DBG_CC_NP_CNP_DSCP, 807 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 808 MLX5_IB_DBG_CC_NP_CNP_PRIO, 809 MLX5_IB_DBG_CC_MAX, 810 }; 811 812 struct mlx5_ib_dbg_cc_params { 813 struct dentry *root; 814 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 815 }; 816 817 enum { 818 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 819 }; 820 821 struct mlx5_ib_delay_drop { 822 struct mlx5_ib_dev *dev; 823 struct work_struct delay_drop_work; 824 /* serialize setting of delay drop */ 825 struct mutex lock; 826 u32 timeout; 827 bool activate; 828 atomic_t events_cnt; 829 atomic_t rqs_cnt; 830 struct dentry *dir_debugfs; 831 }; 832 833 enum mlx5_ib_stages { 834 MLX5_IB_STAGE_INIT, 835 MLX5_IB_STAGE_FLOW_DB, 836 MLX5_IB_STAGE_CAPS, 837 MLX5_IB_STAGE_NON_DEFAULT_CB, 838 MLX5_IB_STAGE_ROCE, 839 MLX5_IB_STAGE_QP, 840 MLX5_IB_STAGE_SRQ, 841 MLX5_IB_STAGE_DEVICE_RESOURCES, 842 MLX5_IB_STAGE_DEVICE_NOTIFIER, 843 MLX5_IB_STAGE_ODP, 844 MLX5_IB_STAGE_COUNTERS, 845 MLX5_IB_STAGE_CONG_DEBUGFS, 846 MLX5_IB_STAGE_UAR, 847 MLX5_IB_STAGE_BFREG, 848 MLX5_IB_STAGE_PRE_IB_REG_UMR, 849 MLX5_IB_STAGE_WHITELIST_UID, 850 MLX5_IB_STAGE_IB_REG, 851 MLX5_IB_STAGE_POST_IB_REG_UMR, 852 MLX5_IB_STAGE_DELAY_DROP, 853 MLX5_IB_STAGE_CLASS_ATTR, 854 MLX5_IB_STAGE_MAX, 855 }; 856 857 struct mlx5_ib_stage { 858 int (*init)(struct mlx5_ib_dev *dev); 859 void (*cleanup)(struct mlx5_ib_dev *dev); 860 }; 861 862 #define STAGE_CREATE(_stage, _init, _cleanup) \ 863 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 864 865 struct mlx5_ib_profile { 866 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 867 }; 868 869 struct mlx5_ib_multiport_info { 870 struct list_head list; 871 struct mlx5_ib_dev *ibdev; 872 struct mlx5_core_dev *mdev; 873 struct notifier_block mdev_events; 874 struct completion unref_comp; 875 u64 sys_image_guid; 876 u32 mdev_refcnt; 877 bool is_master; 878 bool unaffiliate; 879 }; 880 881 struct mlx5_ib_flow_action { 882 struct ib_flow_action ib_action; 883 union { 884 struct { 885 u64 ib_flags; 886 struct mlx5_accel_esp_xfrm *ctx; 887 } esp_aes_gcm; 888 struct { 889 struct mlx5_ib_dev *dev; 890 u32 sub_type; 891 union { 892 struct mlx5_modify_hdr *modify_hdr; 893 struct mlx5_pkt_reformat *pkt_reformat; 894 }; 895 } flow_action_raw; 896 }; 897 }; 898 899 struct mlx5_dm { 900 struct mlx5_core_dev *dev; 901 /* This lock is used to protect the access to the shared 902 * allocation map when concurrent requests by different 903 * processes are handled. 904 */ 905 spinlock_t lock; 906 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 907 }; 908 909 struct mlx5_read_counters_attr { 910 struct mlx5_fc *hw_cntrs_hndl; 911 u64 *out; 912 u32 flags; 913 }; 914 915 enum mlx5_ib_counters_type { 916 MLX5_IB_COUNTERS_FLOW, 917 }; 918 919 struct mlx5_ib_mcounters { 920 struct ib_counters ibcntrs; 921 enum mlx5_ib_counters_type type; 922 /* number of counters supported for this counters type */ 923 u32 counters_num; 924 struct mlx5_fc *hw_cntrs_hndl; 925 /* read function for this counters type */ 926 int (*read_counters)(struct ib_device *ibdev, 927 struct mlx5_read_counters_attr *read_attr); 928 /* max index set as part of create_flow */ 929 u32 cntrs_max_index; 930 /* number of counters data entries (<description,index> pair) */ 931 u32 ncounters; 932 /* counters data array for descriptions and indexes */ 933 struct mlx5_ib_flow_counters_desc *counters_data; 934 /* protects access to mcounters internal data */ 935 struct mutex mcntrs_mutex; 936 }; 937 938 static inline struct mlx5_ib_mcounters * 939 to_mcounters(struct ib_counters *ibcntrs) 940 { 941 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 942 } 943 944 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 945 bool is_egress, 946 struct mlx5_flow_act *action); 947 struct mlx5_ib_lb_state { 948 /* protect the user_td */ 949 struct mutex mutex; 950 u32 user_td; 951 int qps; 952 bool enabled; 953 }; 954 955 struct mlx5_ib_pf_eq { 956 struct notifier_block irq_nb; 957 struct mlx5_ib_dev *dev; 958 struct mlx5_eq *core; 959 struct work_struct work; 960 spinlock_t lock; /* Pagefaults spinlock */ 961 struct workqueue_struct *wq; 962 mempool_t *pool; 963 }; 964 965 struct mlx5_devx_event_table { 966 struct mlx5_nb devx_nb; 967 /* serialize updating the event_xa */ 968 struct mutex event_xa_lock; 969 struct xarray event_xa; 970 }; 971 972 struct mlx5_var_table { 973 /* serialize updating the bitmap */ 974 struct mutex bitmap_lock; 975 unsigned long *bitmap; 976 u64 hw_start_addr; 977 u32 stride_size; 978 u64 num_var_hw_entries; 979 }; 980 981 struct mlx5_ib_dev { 982 struct ib_device ib_dev; 983 struct mlx5_core_dev *mdev; 984 struct notifier_block mdev_events; 985 int num_ports; 986 /* serialize update of capability mask 987 */ 988 struct mutex cap_mask_mutex; 989 u8 ib_active:1; 990 u8 is_rep:1; 991 u8 lag_active:1; 992 u8 wc_support:1; 993 u8 fill_delay; 994 struct umr_common umrc; 995 /* sync used page count stats 996 */ 997 struct mlx5_ib_resources devr; 998 999 atomic_t mkey_var; 1000 struct mlx5_mr_cache cache; 1001 struct timer_list delay_timer; 1002 /* Prevents soft lock on massive reg MRs */ 1003 struct mutex slow_path_mutex; 1004 struct ib_odp_caps odp_caps; 1005 u64 odp_max_size; 1006 struct mlx5_ib_pf_eq odp_pf_eq; 1007 1008 /* 1009 * Sleepable RCU that prevents destruction of MRs while they are still 1010 * being used by a page fault handler. 1011 */ 1012 struct srcu_struct odp_srcu; 1013 struct xarray odp_mkeys; 1014 1015 u32 null_mkey; 1016 struct mlx5_ib_flow_db *flow_db; 1017 /* protect resources needed as part of reset flow */ 1018 spinlock_t reset_flow_resource_lock; 1019 struct list_head qp_list; 1020 /* Array with num_ports elements */ 1021 struct mlx5_ib_port *port; 1022 struct mlx5_sq_bfreg bfreg; 1023 struct mlx5_sq_bfreg wc_bfreg; 1024 struct mlx5_sq_bfreg fp_bfreg; 1025 struct mlx5_ib_delay_drop delay_drop; 1026 const struct mlx5_ib_profile *profile; 1027 1028 struct mlx5_ib_lb_state lb; 1029 u8 umr_fence; 1030 struct list_head ib_dev_list; 1031 u64 sys_image_guid; 1032 struct mlx5_dm dm; 1033 u16 devx_whitelist_uid; 1034 struct mlx5_srq_table srq_table; 1035 struct mlx5_qp_table qp_table; 1036 struct mlx5_async_ctx async_ctx; 1037 struct mlx5_devx_event_table devx_event_table; 1038 struct mlx5_var_table var_table; 1039 1040 struct xarray sig_mrs; 1041 }; 1042 1043 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1044 { 1045 return container_of(mcq, struct mlx5_ib_cq, mcq); 1046 } 1047 1048 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1049 { 1050 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1051 } 1052 1053 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1054 { 1055 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1056 } 1057 1058 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1059 { 1060 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1061 udata, struct mlx5_ib_ucontext, ibucontext); 1062 1063 return to_mdev(context->ibucontext.device); 1064 } 1065 1066 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1067 { 1068 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1069 } 1070 1071 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1072 { 1073 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1074 } 1075 1076 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1077 { 1078 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1079 } 1080 1081 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 1082 { 1083 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 1084 } 1085 1086 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1087 { 1088 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1089 } 1090 1091 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1092 { 1093 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1094 } 1095 1096 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1097 { 1098 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1099 } 1100 1101 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1102 { 1103 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1104 } 1105 1106 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1107 { 1108 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1109 } 1110 1111 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1112 { 1113 return container_of(msrq, struct mlx5_ib_srq, msrq); 1114 } 1115 1116 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1117 { 1118 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1119 } 1120 1121 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1122 { 1123 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1124 } 1125 1126 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1127 { 1128 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1129 } 1130 1131 static inline struct mlx5_ib_flow_action * 1132 to_mflow_act(struct ib_flow_action *ibact) 1133 { 1134 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1135 } 1136 1137 static inline struct mlx5_user_mmap_entry * 1138 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1139 { 1140 return container_of(rdma_entry, 1141 struct mlx5_user_mmap_entry, rdma_entry); 1142 } 1143 1144 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1145 struct ib_udata *udata, unsigned long virt, 1146 struct mlx5_db *db); 1147 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1148 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1149 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1150 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1151 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1152 struct ib_udata *udata); 1153 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1154 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1155 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1156 struct ib_udata *udata); 1157 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1158 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1159 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1160 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1161 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1162 const struct ib_recv_wr **bad_wr); 1163 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1164 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1165 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1166 struct ib_qp_init_attr *init_attr, 1167 struct ib_udata *udata); 1168 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1169 int attr_mask, struct ib_udata *udata); 1170 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1171 struct ib_qp_init_attr *qp_init_attr); 1172 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1173 void mlx5_ib_drain_sq(struct ib_qp *qp); 1174 void mlx5_ib_drain_rq(struct ib_qp *qp); 1175 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1176 size_t buflen, size_t *bc); 1177 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1178 size_t buflen, size_t *bc); 1179 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1180 size_t buflen, size_t *bc); 1181 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1182 struct ib_udata *udata); 1183 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1184 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1185 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1186 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1187 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1188 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1189 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1190 u64 virt_addr, int access_flags, 1191 struct ib_udata *udata); 1192 int mlx5_ib_advise_mr(struct ib_pd *pd, 1193 enum ib_uverbs_advise_mr_advice advice, 1194 u32 flags, 1195 struct ib_sge *sg_list, 1196 u32 num_sge, 1197 struct uverbs_attr_bundle *attrs); 1198 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1199 struct ib_udata *udata); 1200 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1201 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1202 int page_shift, int flags); 1203 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1204 struct ib_udata *udata, 1205 int access_flags); 1206 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1207 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1208 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1209 u64 length, u64 virt_addr, int access_flags, 1210 struct ib_pd *pd, struct ib_udata *udata); 1211 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1212 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1213 u32 max_num_sg, struct ib_udata *udata); 1214 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1215 u32 max_num_sg, 1216 u32 max_num_meta_sg); 1217 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1218 unsigned int *sg_offset); 1219 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1220 int data_sg_nents, unsigned int *data_sg_offset, 1221 struct scatterlist *meta_sg, int meta_sg_nents, 1222 unsigned int *meta_sg_offset); 1223 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1224 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1225 const struct ib_mad *in, struct ib_mad *out, 1226 size_t *out_mad_size, u16 *out_mad_pkey_index); 1227 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1228 struct ib_udata *udata); 1229 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1230 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1231 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1232 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1233 struct ib_smp *out_mad); 1234 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1235 __be64 *sys_image_guid); 1236 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1237 u16 *max_pkeys); 1238 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1239 u32 *vendor_id); 1240 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1241 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1242 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1243 u16 *pkey); 1244 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1245 union ib_gid *gid); 1246 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1247 struct ib_port_attr *props); 1248 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1249 struct ib_port_attr *props); 1250 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1251 unsigned long max_page_shift, 1252 int *count, int *shift, 1253 int *ncont, int *order); 1254 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1255 int page_shift, size_t offset, size_t num_pages, 1256 __be64 *pas, int access_flags); 1257 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1258 int page_shift, __be64 *pas, int access_flags); 1259 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1260 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1261 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1262 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1263 1264 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1265 unsigned int entry); 1266 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1267 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1268 1269 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1270 struct ib_mr_status *mr_status); 1271 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1272 struct ib_wq_init_attr *init_attr, 1273 struct ib_udata *udata); 1274 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1275 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1276 u32 wq_attr_mask, struct ib_udata *udata); 1277 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1278 struct ib_rwq_ind_table_init_attr *init_attr, 1279 struct ib_udata *udata); 1280 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1281 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1282 struct ib_ucontext *context, 1283 struct ib_dm_alloc_attr *attr, 1284 struct uverbs_attr_bundle *attrs); 1285 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1286 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1287 struct ib_dm_mr_attr *attr, 1288 struct uverbs_attr_bundle *attrs); 1289 1290 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1291 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1292 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1293 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1294 int __init mlx5_ib_odp_init(void); 1295 void mlx5_ib_odp_cleanup(void); 1296 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1297 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1298 struct mlx5_ib_mr *mr, int flags); 1299 1300 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1301 enum ib_uverbs_advise_mr_advice advice, 1302 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1303 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1304 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1305 { 1306 return; 1307 } 1308 1309 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1310 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1311 static inline int mlx5_ib_odp_init(void) { return 0; } 1312 static inline void mlx5_ib_odp_cleanup(void) {} 1313 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1314 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1315 struct mlx5_ib_mr *mr, int flags) {} 1316 1317 static inline int 1318 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1319 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1320 struct ib_sge *sg_list, u32 num_sge) 1321 { 1322 return -EOPNOTSUPP; 1323 } 1324 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1325 1326 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1327 1328 /* Needed for rep profile */ 1329 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1330 const struct mlx5_ib_profile *profile, 1331 int stage); 1332 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1333 const struct mlx5_ib_profile *profile); 1334 1335 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1336 u8 port, struct ifla_vf_info *info); 1337 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1338 u8 port, int state); 1339 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1340 u8 port, struct ifla_vf_stats *stats); 1341 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1342 struct ifla_vf_guid *node_guid, 1343 struct ifla_vf_guid *port_guid); 1344 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1345 u64 guid, int type); 1346 1347 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1348 const struct ib_gid_attr *attr); 1349 1350 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1351 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1352 1353 /* GSI QP helper functions */ 1354 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1355 struct ib_qp_init_attr *init_attr); 1356 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1357 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1358 int attr_mask); 1359 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1360 int qp_attr_mask, 1361 struct ib_qp_init_attr *qp_init_attr); 1362 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1363 const struct ib_send_wr **bad_wr); 1364 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1365 const struct ib_recv_wr **bad_wr); 1366 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1367 1368 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1369 1370 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1371 int bfregn); 1372 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1373 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1374 u8 ib_port_num, 1375 u8 *native_port_num); 1376 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1377 u8 port_num); 1378 int mlx5_ib_fill_res_entry(struct sk_buff *msg, 1379 struct rdma_restrack_entry *res); 1380 int mlx5_ib_fill_stat_entry(struct sk_buff *msg, 1381 struct rdma_restrack_entry *res); 1382 1383 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1384 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1385 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1386 1387 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1388 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user); 1389 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1390 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev); 1391 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev); 1392 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1393 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1394 struct mlx5_flow_context *flow_context, 1395 struct mlx5_flow_act *flow_act, u32 counter_id, 1396 void *cmd_in, int inlen, int dest_id, int dest_type); 1397 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1398 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id); 1399 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1400 #else 1401 static inline int 1402 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1403 bool is_user) { return -EOPNOTSUPP; } 1404 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1405 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {} 1406 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {} 1407 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1408 int *dest_type) 1409 { 1410 return false; 1411 } 1412 static inline void 1413 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1414 { 1415 return; 1416 }; 1417 #endif 1418 static inline void init_query_mad(struct ib_smp *mad) 1419 { 1420 mad->base_version = 1; 1421 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1422 mad->class_version = 1; 1423 mad->method = IB_MGMT_METHOD_GET; 1424 } 1425 1426 static inline u8 convert_access(int acc) 1427 { 1428 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1429 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1430 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1431 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1432 MLX5_PERM_LOCAL_READ; 1433 } 1434 1435 static inline int is_qp1(enum ib_qp_type qp_type) 1436 { 1437 return qp_type == MLX5_IB_QPT_HW_GSI; 1438 } 1439 1440 #define MLX5_MAX_UMR_SHIFT 16 1441 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1442 1443 static inline u32 check_cq_create_flags(u32 flags) 1444 { 1445 /* 1446 * It returns non-zero value for unsupported CQ 1447 * create flags, otherwise it returns zero. 1448 */ 1449 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1450 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1451 } 1452 1453 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1454 u32 *user_index) 1455 { 1456 if (cqe_version) { 1457 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1458 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1459 return -EINVAL; 1460 *user_index = cmd_uidx; 1461 } else { 1462 *user_index = MLX5_IB_DEFAULT_UIDX; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1469 struct mlx5_ib_create_qp *ucmd, 1470 int inlen, 1471 u32 *user_index) 1472 { 1473 u8 cqe_version = ucontext->cqe_version; 1474 1475 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1476 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1477 return 0; 1478 1479 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1480 return -EINVAL; 1481 1482 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1483 } 1484 1485 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1486 struct mlx5_ib_create_srq *ucmd, 1487 int inlen, 1488 u32 *user_index) 1489 { 1490 u8 cqe_version = ucontext->cqe_version; 1491 1492 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1493 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1494 return 0; 1495 1496 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1497 return -EINVAL; 1498 1499 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1500 } 1501 1502 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1503 { 1504 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1505 MLX5_UARS_IN_PAGE : 1; 1506 } 1507 1508 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1509 struct mlx5_bfreg_info *bfregi) 1510 { 1511 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1512 } 1513 1514 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1515 void mlx5_ib_put_xlt_emergency_page(void); 1516 1517 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1518 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1519 bool dyn_bfreg); 1520 1521 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter); 1522 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num); 1523 1524 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev, 1525 bool do_modify_atomic, int access_flags) 1526 { 1527 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1528 return false; 1529 1530 if (do_modify_atomic && 1531 MLX5_CAP_GEN(dev->mdev, atomic) && 1532 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1533 return false; 1534 1535 if (access_flags & IB_ACCESS_RELAXED_ORDERING && 1536 (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) || 1537 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read))) 1538 return false; 1539 1540 return true; 1541 } 1542 1543 int mlx5_ib_enable_driver(struct ib_device *dev); 1544 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1545 1546 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1547 { 1548 return dev->lag_active || 1549 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1550 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1551 } 1552 #endif /* MLX5_IB_H */ 1553