1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #ifndef MLX5_IB_H
8 #define MLX5_IB_H
9
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <rdma/ib_verbs.h>
13 #include <rdma/ib_umem.h>
14 #include <rdma/ib_smi.h>
15 #include <linux/mlx5/driver.h>
16 #include <linux/mlx5/cq.h>
17 #include <linux/mlx5/fs.h>
18 #include <linux/mlx5/qp.h>
19 #include <linux/types.h>
20 #include <linux/mlx5/transobj.h>
21 #include <rdma/ib_user_verbs.h>
22 #include <rdma/mlx5-abi.h>
23 #include <rdma/uverbs_ioctl.h>
24 #include <rdma/mlx5_user_ioctl_cmds.h>
25 #include <rdma/mlx5_user_ioctl_verbs.h>
26
27 #include "srq.h"
28 #include "qp.h"
29 #include "macsec.h"
30
31 #define mlx5_ib_dbg(_dev, format, arg...) \
32 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
33 __LINE__, current->pid, ##arg)
34
35 #define mlx5_ib_err(_dev, format, arg...) \
36 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
37 __LINE__, current->pid, ##arg)
38
39 #define mlx5_ib_warn(_dev, format, arg...) \
40 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
41 __LINE__, current->pid, ##arg)
42
43 #define mlx5_ib_log(lvl, _dev, format, arg...) \
44 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \
45 __func__, __LINE__, current->pid, ##arg)
46
47 #define MLX5_IB_DEFAULT_UIDX 0xffffff
48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
49
50 static __always_inline unsigned long
__mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,unsigned int pgsz_shift)51 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,
52 unsigned int pgsz_shift)
53 {
54 unsigned int largest_pg_shift =
55 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift,
56 BITS_PER_LONG - 1);
57
58 /*
59 * Despite a command allowing it, the device does not support lower than
60 * 4k page size.
61 */
62 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift);
63 return GENMASK(largest_pg_shift, pgsz_shift);
64 }
65
66 /*
67 * For mkc users, instead of a page_offset the command has a start_iova which
68 * specifies both the page_offset and the on-the-wire IOVA
69 */
70 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \
71 ib_umem_find_best_pgsz(umem, \
72 __mlx5_log_page_size_to_bitmap( \
73 __mlx5_bit_sz(typ, log_pgsz_fld), \
74 pgsz_shift), \
75 iova)
76
77 static __always_inline unsigned long
__mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,unsigned int offset_shift)78 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,
79 unsigned int offset_shift)
80 {
81 unsigned int largest_offset_shift =
82 min_t(unsigned long, page_offset_bits - 1 + offset_shift,
83 BITS_PER_LONG - 1);
84
85 return GENMASK(largest_offset_shift, offset_shift);
86 }
87
88 /*
89 * QP/CQ/WQ/etc type commands take a page offset that satisifies:
90 * page_offset_quantized * (page_size/scale) = page_offset
91 * Which restricts allowed page sizes to ones that satisify the above.
92 */
93 unsigned long __mlx5_umem_find_best_quantized_pgoff(
94 struct ib_umem *umem, unsigned long pgsz_bitmap,
95 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
96 unsigned int *page_offset_quantized);
97 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \
98 pgsz_shift, page_offset_fld, \
99 scale, page_offset_quantized) \
100 __mlx5_umem_find_best_quantized_pgoff( \
101 umem, \
102 __mlx5_log_page_size_to_bitmap( \
103 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
104 __mlx5_bit_sz(typ, page_offset_fld), \
105 GENMASK(31, order_base_2(scale)), scale, \
106 page_offset_quantized)
107
108 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \
109 pgsz_shift, page_offset_fld, \
110 scale, page_offset_quantized) \
111 __mlx5_umem_find_best_quantized_pgoff( \
112 umem, \
113 __mlx5_log_page_size_to_bitmap( \
114 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
115 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \
116 page_offset_quantized)
117
118 static inline unsigned long
mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf * umem_dmabuf)119 mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf)
120 {
121 /*
122 * mkeys used for dmabuf are fixed at PAGE_SIZE because we must be able
123 * to hold any sgl after a move operation. Ideally the mkc page size
124 * could be changed at runtime to be optimal, but right now the driver
125 * cannot do that.
126 */
127 return ib_umem_find_best_pgsz(&umem_dmabuf->umem, PAGE_SIZE,
128 umem_dmabuf->umem.iova);
129 }
130
131 enum {
132 MLX5_IB_MMAP_OFFSET_START = 9,
133 MLX5_IB_MMAP_OFFSET_END = 255,
134 };
135
136 enum {
137 MLX5_IB_MMAP_CMD_SHIFT = 8,
138 MLX5_IB_MMAP_CMD_MASK = 0xff,
139 };
140
141 enum {
142 MLX5_RES_SCAT_DATA32_CQE = 0x1,
143 MLX5_RES_SCAT_DATA64_CQE = 0x2,
144 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
145 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
146 };
147
148 enum mlx5_ib_mad_ifc_flags {
149 MLX5_MAD_IFC_IGNORE_MKEY = 1,
150 MLX5_MAD_IFC_IGNORE_BKEY = 2,
151 MLX5_MAD_IFC_NET_VIEW = 4,
152 };
153
154 enum {
155 MLX5_CROSS_CHANNEL_BFREG = 0,
156 };
157
158 enum {
159 MLX5_CQE_VERSION_V0,
160 MLX5_CQE_VERSION_V1,
161 };
162
163 enum {
164 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
165 MLX5_TM_MAX_SGE = 1,
166 };
167
168 enum {
169 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
170 MLX5_IB_INVALID_BFREG = BIT(31),
171 };
172
173 enum {
174 MLX5_MAX_MEMIC_PAGES = 0x100,
175 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
176 };
177
178 enum {
179 MLX5_MEMIC_BASE_ALIGN = 6,
180 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
181 };
182
183 enum mlx5_ib_mmap_type {
184 MLX5_IB_MMAP_TYPE_MEMIC = 1,
185 MLX5_IB_MMAP_TYPE_VAR = 2,
186 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
187 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
188 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5,
189 };
190
191 struct mlx5_bfreg_info {
192 u32 *sys_pages;
193 int num_low_latency_bfregs;
194 unsigned int *count;
195
196 /*
197 * protect bfreg allocation data structs
198 */
199 struct mutex lock;
200 u32 ver;
201 u8 lib_uar_4k : 1;
202 u8 lib_uar_dyn : 1;
203 u32 num_sys_pages;
204 u32 num_static_sys_pages;
205 u32 total_num_bfregs;
206 u32 num_dyn_bfregs;
207 };
208
209 struct mlx5_ib_ucontext {
210 struct ib_ucontext ibucontext;
211 struct list_head db_page_list;
212
213 /* protect doorbell record alloc/free
214 */
215 struct mutex db_page_mutex;
216 struct mlx5_bfreg_info bfregi;
217 u8 cqe_version;
218 /* Transport Domain number */
219 u32 tdn;
220
221 u64 lib_caps;
222 u16 devx_uid;
223 /* For RoCE LAG TX affinity */
224 atomic_t tx_port_affinity;
225 };
226
to_mucontext(struct ib_ucontext * ibucontext)227 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
228 {
229 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
230 }
231
232 struct mlx5_ib_pd {
233 struct ib_pd ibpd;
234 u32 pdn;
235 u16 uid;
236 };
237
238 enum {
239 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
240 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
241 MLX5_IB_FLOW_ACTION_DECAP,
242 };
243
244 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
245 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
246 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
247 #error "Invalid number of bypass priorities"
248 #endif
249 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
250
251 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
252 #define MLX5_IB_NUM_SNIFFER_FTS 2
253 #define MLX5_IB_NUM_EGRESS_FTS 1
254 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS
255
256 struct mlx5_ib_anchor {
257 struct mlx5_flow_table *ft;
258 struct mlx5_flow_group *fg_goto_table;
259 struct mlx5_flow_group *fg_drop;
260 struct mlx5_flow_handle *rule_goto_table;
261 struct mlx5_flow_handle *rule_drop;
262 unsigned int rule_goto_table_ref;
263 };
264
265 struct mlx5_ib_flow_prio {
266 struct mlx5_flow_table *flow_table;
267 struct mlx5_ib_anchor anchor;
268 unsigned int refcount;
269 };
270
271 struct mlx5_ib_flow_handler {
272 struct list_head list;
273 struct ib_flow ibflow;
274 struct mlx5_ib_flow_prio *prio;
275 struct mlx5_flow_handle *rule;
276 struct ib_counters *ibcounters;
277 struct mlx5_ib_dev *dev;
278 struct mlx5_ib_flow_matcher *flow_matcher;
279 };
280
281 struct mlx5_ib_flow_matcher {
282 struct mlx5_ib_match_params matcher_mask;
283 int mask_len;
284 enum mlx5_ib_flow_type flow_type;
285 enum mlx5_flow_namespace_type ns_type;
286 u16 priority;
287 struct mlx5_core_dev *mdev;
288 atomic_t usecnt;
289 u8 match_criteria_enable;
290 };
291
292 struct mlx5_ib_steering_anchor {
293 struct mlx5_ib_flow_prio *ft_prio;
294 struct mlx5_ib_dev *dev;
295 atomic_t usecnt;
296 };
297
298 struct mlx5_ib_pp {
299 u16 index;
300 struct mlx5_core_dev *mdev;
301 };
302
303 enum mlx5_ib_optional_counter_type {
304 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS,
305 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS,
306 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS,
307
308 MLX5_IB_OPCOUNTER_MAX,
309 };
310
311 struct mlx5_ib_flow_db {
312 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
313 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
314 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
315 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
316 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS];
317 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
318 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
319 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX];
320 struct mlx5_flow_table *lag_demux_ft;
321 /* Protect flow steering bypass flow tables
322 * when add/del flow rules.
323 * only single add/removal of flow steering rule could be done
324 * simultaneously.
325 */
326 struct mutex lock;
327 };
328
329 /* Use macros here so that don't have to duplicate
330 * enum ib_qp_type for low-level driver
331 */
332
333 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
334 /*
335 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
336 * creates the actual hardware QP.
337 */
338 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
339 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
340 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
341 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
342
343 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
344 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
345 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
346 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
347 #define MLX5_IB_UPD_XLT_PD BIT(4)
348 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
349 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
350
351 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
352 *
353 * These flags are intended for internal use by the mlx5_ib driver, and they
354 * rely on the range reserved for that use in the ib_qp_create_flags enum.
355 */
356 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
357 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
358
359 struct wr_list {
360 u16 opcode;
361 u16 next;
362 };
363
364 enum mlx5_ib_rq_flags {
365 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
366 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
367 };
368
369 struct mlx5_ib_wq {
370 struct mlx5_frag_buf_ctrl fbc;
371 u64 *wrid;
372 u32 *wr_data;
373 struct wr_list *w_list;
374 unsigned *wqe_head;
375 u16 unsig_count;
376
377 /* serialize post to the work queue
378 */
379 spinlock_t lock;
380 int wqe_cnt;
381 int max_post;
382 int max_gs;
383 int offset;
384 int wqe_shift;
385 unsigned head;
386 unsigned tail;
387 u16 cur_post;
388 u16 last_poll;
389 void *cur_edge;
390 };
391
392 enum mlx5_ib_wq_flags {
393 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
394 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
395 };
396
397 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
398 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
399 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
400 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
401 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
402
403 struct mlx5_ib_rwq {
404 struct ib_wq ibwq;
405 struct mlx5_core_qp core_qp;
406 u32 rq_num_pas;
407 u32 log_rq_stride;
408 u32 log_rq_size;
409 u32 rq_page_offset;
410 u32 log_page_size;
411 u32 log_num_strides;
412 u32 two_byte_shift_en;
413 u32 single_stride_log_num_of_bytes;
414 struct ib_umem *umem;
415 size_t buf_size;
416 unsigned int page_shift;
417 struct mlx5_db db;
418 u32 user_index;
419 u32 wqe_count;
420 u32 wqe_shift;
421 int wq_sig;
422 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
423 };
424
425 struct mlx5_ib_rwq_ind_table {
426 struct ib_rwq_ind_table ib_rwq_ind_tbl;
427 u32 rqtn;
428 u16 uid;
429 };
430
431 struct mlx5_ib_ubuffer {
432 struct ib_umem *umem;
433 int buf_size;
434 u64 buf_addr;
435 };
436
437 struct mlx5_ib_qp_base {
438 struct mlx5_ib_qp *container_mibqp;
439 struct mlx5_core_qp mqp;
440 struct mlx5_ib_ubuffer ubuffer;
441 };
442
443 struct mlx5_ib_qp_trans {
444 struct mlx5_ib_qp_base base;
445 u16 xrcdn;
446 u32 alt_port;
447 u8 atomic_rd_en;
448 u8 resp_depth;
449 };
450
451 struct mlx5_ib_rss_qp {
452 u32 tirn;
453 };
454
455 struct mlx5_ib_rq {
456 struct mlx5_ib_qp_base base;
457 struct mlx5_ib_wq *rq;
458 struct mlx5_ib_ubuffer ubuffer;
459 struct mlx5_db *doorbell;
460 u32 tirn;
461 u8 state;
462 u32 flags;
463 };
464
465 struct mlx5_ib_sq {
466 struct mlx5_ib_qp_base base;
467 struct mlx5_ib_wq *sq;
468 struct mlx5_ib_ubuffer ubuffer;
469 struct mlx5_db *doorbell;
470 struct mlx5_flow_handle *flow_rule;
471 u32 tisn;
472 u8 state;
473 };
474
475 struct mlx5_ib_raw_packet_qp {
476 struct mlx5_ib_sq sq;
477 struct mlx5_ib_rq rq;
478 };
479
480 struct mlx5_bf {
481 int buf_size;
482 unsigned long offset;
483 struct mlx5_sq_bfreg *bfreg;
484 };
485
486 struct mlx5_ib_dct {
487 struct mlx5_core_dct mdct;
488 u32 *in;
489 };
490
491 struct mlx5_ib_gsi_qp {
492 struct ib_qp *rx_qp;
493 u32 port_num;
494 struct ib_qp_cap cap;
495 struct ib_cq *cq;
496 struct mlx5_ib_gsi_wr *outstanding_wrs;
497 u32 outstanding_pi, outstanding_ci;
498 int num_qps;
499 /* Protects access to the tx_qps. Post send operations synchronize
500 * with tx_qp creation in setup_qp(). Also protects the
501 * outstanding_wrs array and indices.
502 */
503 spinlock_t lock;
504 struct ib_qp **tx_qps;
505 };
506
507 struct mlx5_ib_qp {
508 struct ib_qp ibqp;
509 union {
510 struct mlx5_ib_qp_trans trans_qp;
511 struct mlx5_ib_raw_packet_qp raw_packet_qp;
512 struct mlx5_ib_rss_qp rss_qp;
513 struct mlx5_ib_dct dct;
514 struct mlx5_ib_gsi_qp gsi;
515 };
516 struct mlx5_frag_buf buf;
517
518 struct mlx5_db db;
519 struct mlx5_ib_wq rq;
520
521 u8 sq_signal_bits;
522 u8 next_fence;
523 struct mlx5_ib_wq sq;
524
525 /* serialize qp state modifications
526 */
527 struct mutex mutex;
528 /* cached variant of create_flags from struct ib_qp_init_attr */
529 u32 flags;
530 u32 port;
531 u8 state;
532 int max_inline_data;
533 struct mlx5_bf bf;
534 u8 has_rq:1;
535 u8 is_rss:1;
536
537 /* only for user space QPs. For kernel
538 * we have it from the bf object
539 */
540 int bfregn;
541
542 struct list_head qps_list;
543 struct list_head cq_recv_list;
544 struct list_head cq_send_list;
545 struct mlx5_rate_limit rl;
546 u32 underlay_qpn;
547 u32 flags_en;
548 /*
549 * IB/core doesn't store low-level QP types, so
550 * store both MLX and IBTA types in the field below.
551 */
552 enum ib_qp_type type;
553 /* A flag to indicate if there's a new counter is configured
554 * but not take effective
555 */
556 u32 counter_pending;
557 u16 gsi_lag_port;
558 };
559
560 struct mlx5_ib_cq_buf {
561 struct mlx5_frag_buf_ctrl fbc;
562 struct mlx5_frag_buf frag_buf;
563 struct ib_umem *umem;
564 int cqe_size;
565 int nent;
566 };
567
568 enum mlx5_ib_cq_pr_flags {
569 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
570 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1,
571 };
572
573 struct mlx5_ib_cq {
574 struct ib_cq ibcq;
575 struct mlx5_core_cq mcq;
576 struct mlx5_ib_cq_buf buf;
577 struct mlx5_db db;
578
579 /* serialize access to the CQ
580 */
581 spinlock_t lock;
582
583 /* protect resize cq
584 */
585 struct mutex resize_mutex;
586 struct mlx5_ib_cq_buf *resize_buf;
587 struct ib_umem *resize_umem;
588 int cqe_size;
589 struct list_head list_send_qp;
590 struct list_head list_recv_qp;
591 u32 create_flags;
592 struct list_head wc_list;
593 enum ib_cq_notify_flags notify_flags;
594 struct work_struct notify_work;
595 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
596 };
597
598 struct mlx5_ib_wc {
599 struct ib_wc wc;
600 struct list_head list;
601 };
602
603 struct mlx5_ib_srq {
604 struct ib_srq ibsrq;
605 struct mlx5_core_srq msrq;
606 struct mlx5_frag_buf buf;
607 struct mlx5_db db;
608 struct mlx5_frag_buf_ctrl fbc;
609 u64 *wrid;
610 /* protect SRQ hanlding
611 */
612 spinlock_t lock;
613 int head;
614 int tail;
615 u16 wqe_ctr;
616 struct ib_umem *umem;
617 /* serialize arming a SRQ
618 */
619 struct mutex mutex;
620 int wq_sig;
621 };
622
623 struct mlx5_ib_xrcd {
624 struct ib_xrcd ibxrcd;
625 u32 xrcdn;
626 };
627
628 enum mlx5_ib_mtt_access_flags {
629 MLX5_IB_MTT_READ = (1 << 0),
630 MLX5_IB_MTT_WRITE = (1 << 1),
631 };
632
633 struct mlx5_user_mmap_entry {
634 struct rdma_user_mmap_entry rdma_entry;
635 u8 mmap_flag;
636 u64 address;
637 u32 page_idx;
638 };
639
640 enum mlx5_mkey_type {
641 MLX5_MKEY_MR = 1,
642 MLX5_MKEY_MW,
643 MLX5_MKEY_INDIRECT_DEVX,
644 };
645
646 struct mlx5r_cache_rb_key {
647 u8 ats:1;
648 unsigned int access_mode;
649 unsigned int access_flags;
650 unsigned int ndescs;
651 };
652
653 struct mlx5_ib_mkey {
654 u32 key;
655 enum mlx5_mkey_type type;
656 unsigned int ndescs;
657 struct wait_queue_head wait;
658 refcount_t usecount;
659 /* Cacheable user Mkey must hold either a rb_key or a cache_ent. */
660 struct mlx5r_cache_rb_key rb_key;
661 struct mlx5_cache_ent *cache_ent;
662 };
663
664 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
665
666 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
667 IB_ACCESS_REMOTE_WRITE |\
668 IB_ACCESS_REMOTE_READ |\
669 IB_ACCESS_REMOTE_ATOMIC |\
670 IB_ZERO_BASED)
671
672 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
673 IB_ACCESS_REMOTE_WRITE |\
674 IB_ACCESS_REMOTE_READ |\
675 IB_ZERO_BASED)
676
677 #define mlx5_update_odp_stats(mr, counter_name, value) \
678 atomic64_add(value, &((mr)->odp_stats.counter_name))
679
680 struct mlx5_ib_mr {
681 struct ib_mr ibmr;
682 struct mlx5_ib_mkey mmkey;
683
684 struct ib_umem *umem;
685
686 union {
687 /* Used only by kernel MRs (umem == NULL) */
688 struct {
689 void *descs;
690 void *descs_alloc;
691 dma_addr_t desc_map;
692 int max_descs;
693 int desc_size;
694 int access_mode;
695
696 /* For Kernel IB_MR_TYPE_INTEGRITY */
697 struct mlx5_core_sig_ctx *sig;
698 struct mlx5_ib_mr *pi_mr;
699 struct mlx5_ib_mr *klm_mr;
700 struct mlx5_ib_mr *mtt_mr;
701 u64 data_iova;
702 u64 pi_iova;
703 int meta_ndescs;
704 int meta_length;
705 int data_length;
706 };
707
708 /* Used only by User MRs (umem != NULL) */
709 struct {
710 unsigned int page_shift;
711 /* Current access_flags */
712 int access_flags;
713
714 /* For User ODP */
715 struct mlx5_ib_mr *parent;
716 struct xarray implicit_children;
717 union {
718 struct work_struct work;
719 } odp_destroy;
720 struct ib_odp_counters odp_stats;
721 bool is_odp_implicit;
722 };
723 };
724 };
725
is_odp_mr(struct mlx5_ib_mr * mr)726 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
727 {
728 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
729 mr->umem->is_odp;
730 }
731
is_dmabuf_mr(struct mlx5_ib_mr * mr)732 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr)
733 {
734 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
735 mr->umem->is_dmabuf;
736 }
737
738 struct mlx5_ib_mw {
739 struct ib_mw ibmw;
740 struct mlx5_ib_mkey mmkey;
741 };
742
743 struct mlx5_ib_umr_context {
744 struct ib_cqe cqe;
745 enum ib_wc_status status;
746 struct completion done;
747 };
748
749 enum {
750 MLX5_UMR_STATE_UNINIT,
751 MLX5_UMR_STATE_ACTIVE,
752 MLX5_UMR_STATE_RECOVER,
753 MLX5_UMR_STATE_ERR,
754 };
755
756 struct umr_common {
757 struct ib_pd *pd;
758 struct ib_cq *cq;
759 struct ib_qp *qp;
760 /* Protects from UMR QP overflow
761 */
762 struct semaphore sem;
763 /* Protects from using UMR while the UMR is not active
764 */
765 struct mutex lock;
766 unsigned int state;
767 };
768
769 struct mlx5_cache_ent {
770 struct xarray mkeys;
771 unsigned long stored;
772 unsigned long reserved;
773
774 char name[4];
775
776 struct rb_node node;
777 struct mlx5r_cache_rb_key rb_key;
778
779 u8 is_tmp:1;
780 u8 disabled:1;
781 u8 fill_to_high_water:1;
782
783 /*
784 * - limit is the low water mark for stored mkeys, 2* limit is the
785 * upper water mark.
786 */
787 u32 in_use;
788 u32 limit;
789
790 /* Statistics */
791 u32 miss;
792
793 struct mlx5_ib_dev *dev;
794 struct delayed_work dwork;
795 };
796
797 struct mlx5r_async_create_mkey {
798 union {
799 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)];
800 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
801 };
802 struct mlx5_async_work cb_work;
803 struct mlx5_cache_ent *ent;
804 u32 mkey;
805 };
806
807 struct mlx5_mkey_cache {
808 struct workqueue_struct *wq;
809 struct rb_root rb_root;
810 struct mutex rb_lock;
811 struct dentry *fs_root;
812 unsigned long last_add;
813 struct delayed_work remove_ent_dwork;
814 };
815
816 struct mlx5_ib_port_resources {
817 struct mlx5_ib_gsi_qp *gsi;
818 struct work_struct pkey_change_work;
819 };
820
821 struct mlx5_ib_resources {
822 struct ib_cq *c0;
823 struct mutex cq_lock;
824 u32 xrcdn0;
825 u32 xrcdn1;
826 struct ib_pd *p0;
827 struct ib_srq *s0;
828 struct ib_srq *s1;
829 struct mutex srq_lock;
830 struct mlx5_ib_port_resources ports[2];
831 };
832
833 #define MAX_OPFC_RULES 2
834
835 struct mlx5_ib_op_fc {
836 struct mlx5_fc *fc;
837 struct mlx5_flow_handle *rule[MAX_OPFC_RULES];
838 };
839
840 struct mlx5_ib_counters {
841 struct rdma_stat_desc *descs;
842 size_t *offsets;
843 u32 num_q_counters;
844 u32 num_cong_counters;
845 u32 num_ext_ppcnt_counters;
846 u32 num_op_counters;
847 u16 set_id;
848 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX];
849 };
850
851 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num,
852 struct mlx5_ib_op_fc *opfc,
853 enum mlx5_ib_optional_counter_type type);
854
855 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev,
856 struct mlx5_ib_op_fc *opfc,
857 enum mlx5_ib_optional_counter_type type);
858
859 struct mlx5_ib_multiport_info;
860
861 struct mlx5_ib_multiport {
862 struct mlx5_ib_multiport_info *mpi;
863 /* To be held when accessing the multiport info */
864 spinlock_t mpi_lock;
865 };
866
867 struct mlx5_roce {
868 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
869 * netdev pointer
870 */
871 rwlock_t netdev_lock;
872 struct net_device *netdev;
873 struct notifier_block nb;
874 struct netdev_net_notifier nn;
875 struct notifier_block mdev_nb;
876 struct net_device *tracking_netdev;
877 atomic_t tx_port_affinity;
878 enum ib_port_state last_port_state;
879 struct mlx5_ib_dev *dev;
880 u32 native_port_num;
881 };
882
883 struct mlx5_ib_port {
884 struct mlx5_ib_counters cnts;
885 struct mlx5_ib_multiport mp;
886 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
887 struct mlx5_roce roce;
888 struct mlx5_eswitch_rep *rep;
889 #ifdef CONFIG_MLX5_MACSEC
890 struct mlx5_reserved_gids *reserved_gids;
891 #endif
892 };
893
894 struct mlx5_ib_dbg_param {
895 int offset;
896 struct mlx5_ib_dev *dev;
897 struct dentry *dentry;
898 u32 port_num;
899 };
900
901 enum mlx5_ib_dbg_cc_types {
902 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
903 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
904 MLX5_IB_DBG_CC_RP_TIME_RESET,
905 MLX5_IB_DBG_CC_RP_BYTE_RESET,
906 MLX5_IB_DBG_CC_RP_THRESHOLD,
907 MLX5_IB_DBG_CC_RP_AI_RATE,
908 MLX5_IB_DBG_CC_RP_MAX_RATE,
909 MLX5_IB_DBG_CC_RP_HAI_RATE,
910 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
911 MLX5_IB_DBG_CC_RP_MIN_RATE,
912 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
913 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
914 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
915 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
916 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
917 MLX5_IB_DBG_CC_RP_GD,
918 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
919 MLX5_IB_DBG_CC_NP_CNP_DSCP,
920 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
921 MLX5_IB_DBG_CC_NP_CNP_PRIO,
922 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID,
923 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP,
924 MLX5_IB_DBG_CC_MAX,
925 };
926
927 struct mlx5_ib_dbg_cc_params {
928 struct dentry *root;
929 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
930 };
931
932 enum {
933 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
934 };
935
936 struct mlx5_ib_delay_drop {
937 struct mlx5_ib_dev *dev;
938 struct work_struct delay_drop_work;
939 /* serialize setting of delay drop */
940 struct mutex lock;
941 u32 timeout;
942 bool activate;
943 atomic_t events_cnt;
944 atomic_t rqs_cnt;
945 struct dentry *dir_debugfs;
946 };
947
948 enum mlx5_ib_stages {
949 MLX5_IB_STAGE_INIT,
950 MLX5_IB_STAGE_FS,
951 MLX5_IB_STAGE_CAPS,
952 MLX5_IB_STAGE_NON_DEFAULT_CB,
953 MLX5_IB_STAGE_ROCE,
954 MLX5_IB_STAGE_QP,
955 MLX5_IB_STAGE_SRQ,
956 MLX5_IB_STAGE_DEVICE_RESOURCES,
957 MLX5_IB_STAGE_ODP,
958 MLX5_IB_STAGE_COUNTERS,
959 MLX5_IB_STAGE_CONG_DEBUGFS,
960 MLX5_IB_STAGE_UAR,
961 MLX5_IB_STAGE_BFREG,
962 MLX5_IB_STAGE_PRE_IB_REG_UMR,
963 MLX5_IB_STAGE_WHITELIST_UID,
964 MLX5_IB_STAGE_IB_REG,
965 MLX5_IB_STAGE_DEVICE_NOTIFIER,
966 MLX5_IB_STAGE_POST_IB_REG_UMR,
967 MLX5_IB_STAGE_DELAY_DROP,
968 MLX5_IB_STAGE_RESTRACK,
969 MLX5_IB_STAGE_MAX,
970 };
971
972 struct mlx5_ib_stage {
973 int (*init)(struct mlx5_ib_dev *dev);
974 void (*cleanup)(struct mlx5_ib_dev *dev);
975 };
976
977 #define STAGE_CREATE(_stage, _init, _cleanup) \
978 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
979
980 struct mlx5_ib_profile {
981 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
982 };
983
984 struct mlx5_ib_multiport_info {
985 struct list_head list;
986 struct mlx5_ib_dev *ibdev;
987 struct mlx5_core_dev *mdev;
988 struct notifier_block mdev_events;
989 struct completion unref_comp;
990 u64 sys_image_guid;
991 u32 mdev_refcnt;
992 bool is_master;
993 bool unaffiliate;
994 };
995
996 struct mlx5_ib_flow_action {
997 struct ib_flow_action ib_action;
998 union {
999 struct {
1000 u64 ib_flags;
1001 struct mlx5_accel_esp_xfrm *ctx;
1002 } esp_aes_gcm;
1003 struct {
1004 struct mlx5_ib_dev *dev;
1005 u32 sub_type;
1006 union {
1007 struct mlx5_modify_hdr *modify_hdr;
1008 struct mlx5_pkt_reformat *pkt_reformat;
1009 };
1010 } flow_action_raw;
1011 };
1012 };
1013
1014 struct mlx5_dm {
1015 struct mlx5_core_dev *dev;
1016 /* This lock is used to protect the access to the shared
1017 * allocation map when concurrent requests by different
1018 * processes are handled.
1019 */
1020 spinlock_t lock;
1021 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
1022 };
1023
1024 struct mlx5_read_counters_attr {
1025 struct mlx5_fc *hw_cntrs_hndl;
1026 u64 *out;
1027 u32 flags;
1028 };
1029
1030 enum mlx5_ib_counters_type {
1031 MLX5_IB_COUNTERS_FLOW,
1032 };
1033
1034 struct mlx5_ib_mcounters {
1035 struct ib_counters ibcntrs;
1036 enum mlx5_ib_counters_type type;
1037 /* number of counters supported for this counters type */
1038 u32 counters_num;
1039 struct mlx5_fc *hw_cntrs_hndl;
1040 /* read function for this counters type */
1041 int (*read_counters)(struct ib_device *ibdev,
1042 struct mlx5_read_counters_attr *read_attr);
1043 /* max index set as part of create_flow */
1044 u32 cntrs_max_index;
1045 /* number of counters data entries (<description,index> pair) */
1046 u32 ncounters;
1047 /* counters data array for descriptions and indexes */
1048 struct mlx5_ib_flow_counters_desc *counters_data;
1049 /* protects access to mcounters internal data */
1050 struct mutex mcntrs_mutex;
1051 };
1052
1053 static inline struct mlx5_ib_mcounters *
to_mcounters(struct ib_counters * ibcntrs)1054 to_mcounters(struct ib_counters *ibcntrs)
1055 {
1056 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
1057 }
1058
1059 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
1060 bool is_egress,
1061 struct mlx5_flow_act *action);
1062 struct mlx5_ib_lb_state {
1063 /* protect the user_td */
1064 struct mutex mutex;
1065 u32 user_td;
1066 int qps;
1067 bool enabled;
1068 };
1069
1070 struct mlx5_ib_pf_eq {
1071 struct notifier_block irq_nb;
1072 struct mlx5_ib_dev *dev;
1073 struct mlx5_eq *core;
1074 struct work_struct work;
1075 spinlock_t lock; /* Pagefaults spinlock */
1076 struct workqueue_struct *wq;
1077 mempool_t *pool;
1078 };
1079
1080 struct mlx5_devx_event_table {
1081 struct mlx5_nb devx_nb;
1082 /* serialize updating the event_xa */
1083 struct mutex event_xa_lock;
1084 struct xarray event_xa;
1085 };
1086
1087 struct mlx5_var_table {
1088 /* serialize updating the bitmap */
1089 struct mutex bitmap_lock;
1090 unsigned long *bitmap;
1091 u64 hw_start_addr;
1092 u32 stride_size;
1093 u64 num_var_hw_entries;
1094 };
1095
1096 struct mlx5_port_caps {
1097 bool has_smi;
1098 u8 ext_port_cap;
1099 };
1100
1101
1102 struct mlx5_special_mkeys {
1103 u32 dump_fill_mkey;
1104 __be32 null_mkey;
1105 __be32 terminate_scatter_list_mkey;
1106 };
1107
1108 struct mlx5_macsec {
1109 struct mutex lock; /* Protects mlx5_macsec internal contexts */
1110 struct list_head macsec_devices_list;
1111 struct notifier_block blocking_events_nb;
1112 };
1113
1114 struct mlx5_ib_dev {
1115 struct ib_device ib_dev;
1116 struct mlx5_core_dev *mdev;
1117 struct notifier_block mdev_events;
1118 int num_ports;
1119 /* serialize update of capability mask
1120 */
1121 struct mutex cap_mask_mutex;
1122 u8 ib_active:1;
1123 u8 is_rep:1;
1124 u8 lag_active:1;
1125 u8 wc_support:1;
1126 u8 fill_delay;
1127 struct umr_common umrc;
1128 /* sync used page count stats
1129 */
1130 struct mlx5_ib_resources devr;
1131
1132 atomic_t mkey_var;
1133 struct mlx5_mkey_cache cache;
1134 struct timer_list delay_timer;
1135 /* Prevents soft lock on massive reg MRs */
1136 struct mutex slow_path_mutex;
1137 struct ib_odp_caps odp_caps;
1138 u64 odp_max_size;
1139 struct mutex odp_eq_mutex;
1140 struct mlx5_ib_pf_eq odp_pf_eq;
1141
1142 struct xarray odp_mkeys;
1143
1144 struct mlx5_ib_flow_db *flow_db;
1145 /* protect resources needed as part of reset flow */
1146 spinlock_t reset_flow_resource_lock;
1147 struct list_head qp_list;
1148 /* Array with num_ports elements */
1149 struct mlx5_ib_port *port;
1150 struct mlx5_sq_bfreg bfreg;
1151 struct mlx5_sq_bfreg wc_bfreg;
1152 struct mlx5_sq_bfreg fp_bfreg;
1153 struct mlx5_ib_delay_drop delay_drop;
1154 const struct mlx5_ib_profile *profile;
1155
1156 struct mlx5_ib_lb_state lb;
1157 u8 umr_fence;
1158 struct list_head ib_dev_list;
1159 u64 sys_image_guid;
1160 struct mlx5_dm dm;
1161 u16 devx_whitelist_uid;
1162 struct mlx5_srq_table srq_table;
1163 struct mlx5_qp_table qp_table;
1164 struct mlx5_async_ctx async_ctx;
1165 struct mlx5_devx_event_table devx_event_table;
1166 struct mlx5_var_table var_table;
1167
1168 struct xarray sig_mrs;
1169 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
1170 u16 pkey_table_len;
1171 u8 lag_ports;
1172 struct mlx5_special_mkeys mkeys;
1173
1174 #ifdef CONFIG_MLX5_MACSEC
1175 struct mlx5_macsec macsec;
1176 #endif
1177 };
1178
to_mibcq(struct mlx5_core_cq * mcq)1179 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1180 {
1181 return container_of(mcq, struct mlx5_ib_cq, mcq);
1182 }
1183
to_mxrcd(struct ib_xrcd * ibxrcd)1184 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1185 {
1186 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1187 }
1188
to_mdev(struct ib_device * ibdev)1189 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1190 {
1191 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1192 }
1193
mr_to_mdev(struct mlx5_ib_mr * mr)1194 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr)
1195 {
1196 return to_mdev(mr->ibmr.device);
1197 }
1198
mlx5_udata_to_mdev(struct ib_udata * udata)1199 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1200 {
1201 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1202 udata, struct mlx5_ib_ucontext, ibucontext);
1203
1204 return to_mdev(context->ibucontext.device);
1205 }
1206
to_mcq(struct ib_cq * ibcq)1207 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1208 {
1209 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1210 }
1211
to_mibqp(struct mlx5_core_qp * mqp)1212 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1213 {
1214 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1215 }
1216
to_mibrwq(struct mlx5_core_qp * core_qp)1217 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1218 {
1219 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1220 }
1221
to_mpd(struct ib_pd * ibpd)1222 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1223 {
1224 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1225 }
1226
to_msrq(struct ib_srq * ibsrq)1227 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1228 {
1229 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1230 }
1231
to_mqp(struct ib_qp * ibqp)1232 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1233 {
1234 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1235 }
1236
to_mrwq(struct ib_wq * ibwq)1237 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1238 {
1239 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1240 }
1241
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)1242 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1243 {
1244 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1245 }
1246
to_mibsrq(struct mlx5_core_srq * msrq)1247 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1248 {
1249 return container_of(msrq, struct mlx5_ib_srq, msrq);
1250 }
1251
to_mmr(struct ib_mr * ibmr)1252 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1253 {
1254 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1255 }
1256
to_mmw(struct ib_mw * ibmw)1257 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1258 {
1259 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1260 }
1261
1262 static inline struct mlx5_ib_flow_action *
to_mflow_act(struct ib_flow_action * ibact)1263 to_mflow_act(struct ib_flow_action *ibact)
1264 {
1265 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1266 }
1267
1268 static inline struct mlx5_user_mmap_entry *
to_mmmap(struct rdma_user_mmap_entry * rdma_entry)1269 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1270 {
1271 return container_of(rdma_entry,
1272 struct mlx5_user_mmap_entry, rdma_entry);
1273 }
1274
1275 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev);
1276 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev);
1277 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1278 struct mlx5_db *db);
1279 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1280 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1281 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1282 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1283 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1284 struct ib_udata *udata);
1285 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
mlx5_ib_destroy_ah(struct ib_ah * ah,u32 flags)1286 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1287 {
1288 return 0;
1289 }
1290 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1291 struct ib_udata *udata);
1292 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1293 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1294 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1295 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1296 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1297 const struct ib_recv_wr **bad_wr);
1298 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1299 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1300 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
1301 struct ib_udata *udata);
1302 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1303 int attr_mask, struct ib_udata *udata);
1304 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1305 struct ib_qp_init_attr *qp_init_attr);
1306 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1307 void mlx5_ib_drain_sq(struct ib_qp *qp);
1308 void mlx5_ib_drain_rq(struct ib_qp *qp);
1309 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1310 size_t buflen, size_t *bc);
1311 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1312 size_t buflen, size_t *bc);
1313 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1314 size_t buflen, size_t *bc);
1315 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1316 struct ib_udata *udata);
1317 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1318 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1319 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1320 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1321 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1322 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1323 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1324 u64 virt_addr, int access_flags,
1325 struct ib_udata *udata);
1326 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
1327 u64 length, u64 virt_addr,
1328 int fd, int access_flags,
1329 struct ib_udata *udata);
1330 int mlx5_ib_advise_mr(struct ib_pd *pd,
1331 enum ib_uverbs_advise_mr_advice advice,
1332 u32 flags,
1333 struct ib_sge *sg_list,
1334 u32 num_sge,
1335 struct uverbs_attr_bundle *attrs);
1336 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1337 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1338 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1339 int access_flags);
1340 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1341 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr);
1342 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1343 u64 length, u64 virt_addr, int access_flags,
1344 struct ib_pd *pd, struct ib_udata *udata);
1345 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1346 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1347 u32 max_num_sg);
1348 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1349 u32 max_num_sg,
1350 u32 max_num_meta_sg);
1351 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1352 unsigned int *sg_offset);
1353 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1354 int data_sg_nents, unsigned int *data_sg_offset,
1355 struct scatterlist *meta_sg, int meta_sg_nents,
1356 unsigned int *meta_sg_offset);
1357 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,
1358 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1359 const struct ib_mad *in, struct ib_mad *out,
1360 size_t *out_mad_size, u16 *out_mad_pkey_index);
1361 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1362 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1363 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port);
1364 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1365 __be64 *sys_image_guid);
1366 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1367 u16 *max_pkeys);
1368 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1369 u32 *vendor_id);
1370 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1371 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1372 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index,
1373 u16 *pkey);
1374 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index,
1375 union ib_gid *gid);
1376 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port,
1377 struct ib_port_attr *props);
1378 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1379 struct ib_port_attr *props);
1380 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
1381 u64 access_flags);
1382 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1383 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1384 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev);
1385 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev);
1386 struct mlx5_cache_ent *
1387 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev,
1388 struct mlx5r_cache_rb_key rb_key,
1389 bool persistent_entry);
1390
1391 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1392 int access_flags, int access_mode,
1393 int ndescs);
1394
1395 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1396 struct ib_mr_status *mr_status);
1397 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1398 struct ib_wq_init_attr *init_attr,
1399 struct ib_udata *udata);
1400 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1401 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1402 u32 wq_attr_mask, struct ib_udata *udata);
1403 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1404 struct ib_rwq_ind_table_init_attr *init_attr,
1405 struct ib_udata *udata);
1406 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1407 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1408 struct ib_dm_mr_attr *attr,
1409 struct uverbs_attr_bundle *attrs);
1410
1411 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1412 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1413 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq);
1414 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1415 int __init mlx5_ib_odp_init(void);
1416 void mlx5_ib_odp_cleanup(void);
1417 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev);
1418 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1419 struct mlx5_ib_mr *mr, int flags);
1420
1421 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1422 enum ib_uverbs_advise_mr_advice advice,
1423 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1424 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr);
1425 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr);
1426 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1427 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5r_odp_create_eq(struct mlx5_ib_dev * dev,struct mlx5_ib_pf_eq * eq)1428 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev,
1429 struct mlx5_ib_pf_eq *eq)
1430 {
1431 return 0;
1432 }
mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev * ibdev)1433 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
mlx5_ib_odp_init(void)1434 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)1435 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_odp_init_mkey_cache(struct mlx5_ib_dev * dev)1436 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev)
1437 {
1438 return 0;
1439 }
mlx5_odp_populate_xlt(void * xlt,size_t idx,size_t nentries,struct mlx5_ib_mr * mr,int flags)1440 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1441 struct mlx5_ib_mr *mr, int flags) {}
1442
1443 static inline int
mlx5_ib_advise_mr_prefetch(struct ib_pd * pd,enum ib_uverbs_advise_mr_advice advice,u32 flags,struct ib_sge * sg_list,u32 num_sge)1444 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1445 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1446 struct ib_sge *sg_list, u32 num_sge)
1447 {
1448 return -EOPNOTSUPP;
1449 }
mlx5_ib_init_odp_mr(struct mlx5_ib_mr * mr)1450 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
1451 {
1452 return -EOPNOTSUPP;
1453 }
mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr * mr)1454 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
1455 {
1456 return -EOPNOTSUPP;
1457 }
1458 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1459
1460 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1461
1462 /* Needed for rep profile */
1463 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1464 const struct mlx5_ib_profile *profile,
1465 int stage);
1466 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
1467 const struct mlx5_ib_profile *profile);
1468
1469 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1470 u32 port, struct ifla_vf_info *info);
1471 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1472 u32 port, int state);
1473 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1474 u32 port, struct ifla_vf_stats *stats);
1475 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port,
1476 struct ifla_vf_guid *node_guid,
1477 struct ifla_vf_guid *port_guid);
1478 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port,
1479 u64 guid, int type);
1480
1481 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1482 const struct ib_gid_attr *attr);
1483
1484 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1485 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1486
1487 /* GSI QP helper functions */
1488 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1489 struct ib_qp_init_attr *attr);
1490 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1491 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1492 int attr_mask);
1493 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1494 int qp_attr_mask,
1495 struct ib_qp_init_attr *qp_init_attr);
1496 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1497 const struct ib_send_wr **bad_wr);
1498 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1499 const struct ib_recv_wr **bad_wr);
1500 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1501
1502 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1503
1504 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1505 int bfregn);
1506 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1507 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1508 u32 ib_port_num,
1509 u32 *native_port_num);
1510 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1511 u32 port_num);
1512
1513 extern const struct uapi_definition mlx5_ib_devx_defs[];
1514 extern const struct uapi_definition mlx5_ib_flow_defs[];
1515 extern const struct uapi_definition mlx5_ib_qos_defs[];
1516 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1517
is_qp1(enum ib_qp_type qp_type)1518 static inline int is_qp1(enum ib_qp_type qp_type)
1519 {
1520 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1521 }
1522
check_cq_create_flags(u32 flags)1523 static inline u32 check_cq_create_flags(u32 flags)
1524 {
1525 /*
1526 * It returns non-zero value for unsupported CQ
1527 * create flags, otherwise it returns zero.
1528 */
1529 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1530 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1531 }
1532
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1533 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1534 u32 *user_index)
1535 {
1536 if (cqe_version) {
1537 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1538 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1539 return -EINVAL;
1540 *user_index = cmd_uidx;
1541 } else {
1542 *user_index = MLX5_IB_DEFAULT_UIDX;
1543 }
1544
1545 return 0;
1546 }
1547
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1548 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1549 struct mlx5_ib_create_qp *ucmd,
1550 int inlen,
1551 u32 *user_index)
1552 {
1553 u8 cqe_version = ucontext->cqe_version;
1554
1555 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1556 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1557 return 0;
1558
1559 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1560 return -EINVAL;
1561
1562 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1563 }
1564
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1565 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1566 struct mlx5_ib_create_srq *ucmd,
1567 int inlen,
1568 u32 *user_index)
1569 {
1570 u8 cqe_version = ucontext->cqe_version;
1571
1572 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1573 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1574 return 0;
1575
1576 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1577 return -EINVAL;
1578
1579 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1580 }
1581
get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1582 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1583 {
1584 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1585 MLX5_UARS_IN_PAGE : 1;
1586 }
1587
1588 extern void *xlt_emergency_page;
1589
1590 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1591 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1592 bool dyn_bfreg);
1593
mlx5r_store_odp_mkey(struct mlx5_ib_dev * dev,struct mlx5_ib_mkey * mmkey)1594 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev,
1595 struct mlx5_ib_mkey *mmkey)
1596 {
1597 refcount_set(&mmkey->usecount, 1);
1598
1599 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key),
1600 mmkey, GFP_KERNEL));
1601 }
1602
1603 /* deref an mkey that can participate in ODP flow */
mlx5r_deref_odp_mkey(struct mlx5_ib_mkey * mmkey)1604 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey)
1605 {
1606 if (refcount_dec_and_test(&mmkey->usecount))
1607 wake_up(&mmkey->wait);
1608 }
1609
1610 /* deref an mkey that can participate in ODP flow and wait for relese */
mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey * mmkey)1611 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey)
1612 {
1613 mlx5r_deref_odp_mkey(mmkey);
1614 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0);
1615 }
1616
1617 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1618
mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev * dev)1619 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1620 {
1621 /*
1622 * If the driver is in hash mode and the port_select_flow_table_bypass cap
1623 * is supported, it means that the driver no longer needs to assign the port
1624 * affinity by default. If a user wants to set the port affinity explicitly,
1625 * the user has a dedicated API to do that, so there is no need to assign
1626 * the port affinity by default.
1627 */
1628 if (dev->lag_active &&
1629 mlx5_lag_mode_is_hash(dev->mdev) &&
1630 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass))
1631 return 0;
1632
1633 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active)
1634 return 0;
1635
1636 return dev->lag_active ||
1637 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1638 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1639 }
1640
rt_supported(int ts_cap)1641 static inline bool rt_supported(int ts_cap)
1642 {
1643 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME ||
1644 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;
1645 }
1646
1647 /*
1648 * PCI Peer to Peer is a trainwreck. If no switch is present then things
1649 * sometimes work, depending on the pci_distance_p2p logic for excluding broken
1650 * root complexes. However if a switch is present in the path, then things get
1651 * really ugly depending on how the switch is setup. This table assumes that the
1652 * root complex is strict and is validating that all req/reps are matches
1653 * perfectly - so any scenario where it sees only half the transaction is a
1654 * failure.
1655 *
1656 * CR/RR/DT ATS RO P2P
1657 * 00X X X OK
1658 * 010 X X fails (request is routed to root but root never sees comp)
1659 * 011 0 X fails (request is routed to root but root never sees comp)
1660 * 011 1 X OK
1661 * 10X X 1 OK
1662 * 101 X 0 fails (completion is routed to root but root didn't see req)
1663 * 110 X 0 SLOW
1664 * 111 0 0 SLOW
1665 * 111 1 0 fails (completion is routed to root but root didn't see req)
1666 * 111 1 1 OK
1667 *
1668 * Unfortunately we cannot reliably know if a switch is present or what the
1669 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that
1670 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows.
1671 *
1672 * For now assume if the umem is a dma_buf then it is P2P.
1673 */
mlx5_umem_needs_ats(struct mlx5_ib_dev * dev,struct ib_umem * umem,int access_flags)1674 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev,
1675 struct ib_umem *umem, int access_flags)
1676 {
1677 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf)
1678 return false;
1679 return access_flags & IB_ACCESS_RELAXED_ORDERING;
1680 }
1681
1682 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
1683 unsigned int index, const union ib_gid *gid,
1684 const struct ib_gid_attr *attr);
1685 #endif /* MLX5_IB_H */
1686