1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem_odp.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include "umr.h" 45 #include <rdma/uverbs_std_types.h> 46 #include <rdma/uverbs_ioctl.h> 47 #include <rdma/mlx5_user_ioctl_verbs.h> 48 #include <rdma/mlx5_user_ioctl_cmds.h> 49 50 #define UVERBS_MODULE_NAME mlx5_ib 51 #include <rdma/uverbs_named_ioctl.h> 52 53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 54 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 57 struct mlx5_ib_event_work { 58 struct work_struct work; 59 union { 60 struct mlx5_ib_dev *dev; 61 struct mlx5_ib_multiport_info *mpi; 62 }; 63 bool is_slave; 64 unsigned int event; 65 void *param; 66 }; 67 68 enum { 69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 70 }; 71 72 static struct workqueue_struct *mlx5_ib_event_wq; 73 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 74 static LIST_HEAD(mlx5_ib_dev_list); 75 /* 76 * This mutex should be held when accessing either of the above lists 77 */ 78 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 79 80 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 81 { 82 struct mlx5_ib_dev *dev; 83 84 mutex_lock(&mlx5_ib_multiport_mutex); 85 dev = mpi->ibdev; 86 mutex_unlock(&mlx5_ib_multiport_mutex); 87 return dev; 88 } 89 90 static enum rdma_link_layer 91 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 92 { 93 switch (port_type_cap) { 94 case MLX5_CAP_PORT_TYPE_IB: 95 return IB_LINK_LAYER_INFINIBAND; 96 case MLX5_CAP_PORT_TYPE_ETH: 97 return IB_LINK_LAYER_ETHERNET; 98 default: 99 return IB_LINK_LAYER_UNSPECIFIED; 100 } 101 } 102 103 static enum rdma_link_layer 104 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 105 { 106 struct mlx5_ib_dev *dev = to_mdev(device); 107 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 108 109 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 110 } 111 112 static int get_port_state(struct ib_device *ibdev, 113 u32 port_num, 114 enum ib_port_state *state) 115 { 116 struct ib_port_attr attr; 117 int ret; 118 119 memset(&attr, 0, sizeof(attr)); 120 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 121 if (!ret) 122 *state = attr.state; 123 return ret; 124 } 125 126 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 127 struct net_device *ndev, 128 struct net_device *upper, 129 u32 *port_num) 130 { 131 struct net_device *rep_ndev; 132 struct mlx5_ib_port *port; 133 int i; 134 135 for (i = 0; i < dev->num_ports; i++) { 136 port = &dev->port[i]; 137 if (!port->rep) 138 continue; 139 140 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 141 *port_num = i + 1; 142 return &port->roce; 143 } 144 145 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 146 continue; 147 148 read_lock(&port->roce.netdev_lock); 149 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 150 port->rep->vport); 151 if (rep_ndev == ndev) { 152 read_unlock(&port->roce.netdev_lock); 153 *port_num = i + 1; 154 return &port->roce; 155 } 156 read_unlock(&port->roce.netdev_lock); 157 } 158 159 return NULL; 160 } 161 162 static int mlx5_netdev_event(struct notifier_block *this, 163 unsigned long event, void *ptr) 164 { 165 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 166 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 167 u32 port_num = roce->native_port_num; 168 struct mlx5_core_dev *mdev; 169 struct mlx5_ib_dev *ibdev; 170 171 ibdev = roce->dev; 172 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 173 if (!mdev) 174 return NOTIFY_DONE; 175 176 switch (event) { 177 case NETDEV_REGISTER: 178 /* Should already be registered during the load */ 179 if (ibdev->is_rep) 180 break; 181 write_lock(&roce->netdev_lock); 182 if (ndev->dev.parent == mdev->device) 183 roce->netdev = ndev; 184 write_unlock(&roce->netdev_lock); 185 break; 186 187 case NETDEV_UNREGISTER: 188 /* In case of reps, ib device goes away before the netdevs */ 189 write_lock(&roce->netdev_lock); 190 if (roce->netdev == ndev) 191 roce->netdev = NULL; 192 write_unlock(&roce->netdev_lock); 193 break; 194 195 case NETDEV_CHANGE: 196 case NETDEV_UP: 197 case NETDEV_DOWN: { 198 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 199 struct net_device *upper = NULL; 200 201 if (lag_ndev) { 202 upper = netdev_master_upper_dev_get(lag_ndev); 203 dev_put(lag_ndev); 204 } 205 206 if (ibdev->is_rep) 207 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 208 if (!roce) 209 return NOTIFY_DONE; 210 if ((upper == ndev || 211 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 212 ibdev->ib_active) { 213 struct ib_event ibev = { }; 214 enum ib_port_state port_state; 215 216 if (get_port_state(&ibdev->ib_dev, port_num, 217 &port_state)) 218 goto done; 219 220 if (roce->last_port_state == port_state) 221 goto done; 222 223 roce->last_port_state = port_state; 224 ibev.device = &ibdev->ib_dev; 225 if (port_state == IB_PORT_DOWN) 226 ibev.event = IB_EVENT_PORT_ERR; 227 else if (port_state == IB_PORT_ACTIVE) 228 ibev.event = IB_EVENT_PORT_ACTIVE; 229 else 230 goto done; 231 232 ibev.element.port_num = port_num; 233 ib_dispatch_event(&ibev); 234 } 235 break; 236 } 237 238 default: 239 break; 240 } 241 done: 242 mlx5_ib_put_native_port_mdev(ibdev, port_num); 243 return NOTIFY_DONE; 244 } 245 246 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 247 u32 port_num) 248 { 249 struct mlx5_ib_dev *ibdev = to_mdev(device); 250 struct net_device *ndev; 251 struct mlx5_core_dev *mdev; 252 253 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 254 if (!mdev) 255 return NULL; 256 257 ndev = mlx5_lag_get_roce_netdev(mdev); 258 if (ndev) 259 goto out; 260 261 /* Ensure ndev does not disappear before we invoke dev_hold() 262 */ 263 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 264 ndev = ibdev->port[port_num - 1].roce.netdev; 265 if (ndev) 266 dev_hold(ndev); 267 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 268 269 out: 270 mlx5_ib_put_native_port_mdev(ibdev, port_num); 271 return ndev; 272 } 273 274 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 275 u32 ib_port_num, 276 u32 *native_port_num) 277 { 278 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 279 ib_port_num); 280 struct mlx5_core_dev *mdev = NULL; 281 struct mlx5_ib_multiport_info *mpi; 282 struct mlx5_ib_port *port; 283 284 if (!mlx5_core_mp_enabled(ibdev->mdev) || 285 ll != IB_LINK_LAYER_ETHERNET) { 286 if (native_port_num) 287 *native_port_num = ib_port_num; 288 return ibdev->mdev; 289 } 290 291 if (native_port_num) 292 *native_port_num = 1; 293 294 port = &ibdev->port[ib_port_num - 1]; 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 297 if (mpi && !mpi->unaffiliate) { 298 mdev = mpi->mdev; 299 /* If it's the master no need to refcount, it'll exist 300 * as long as the ib_dev exists. 301 */ 302 if (!mpi->is_master) 303 mpi->mdev_refcnt++; 304 } 305 spin_unlock(&port->mp.mpi_lock); 306 307 return mdev; 308 } 309 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 311 { 312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 313 port_num); 314 struct mlx5_ib_multiport_info *mpi; 315 struct mlx5_ib_port *port; 316 317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 318 return; 319 320 port = &ibdev->port[port_num - 1]; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[port_num - 1].mp.mpi; 324 if (mpi->is_master) 325 goto out; 326 327 mpi->mdev_refcnt--; 328 if (mpi->unaffiliate) 329 complete(&mpi->unref_comp); 330 out: 331 spin_unlock(&port->mp.mpi_lock); 332 } 333 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 335 u16 *active_speed, u8 *active_width) 336 { 337 switch (eth_proto_oper) { 338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_SDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 352 *active_width = IB_WIDTH_1X; 353 *active_speed = IB_SPEED_QDR; 354 break; 355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 358 *active_width = IB_WIDTH_1X; 359 *active_speed = IB_SPEED_EDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_QDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_HDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_FDR; 377 break; 378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 382 *active_width = IB_WIDTH_4X; 383 *active_speed = IB_SPEED_EDR; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 393 u8 *active_width) 394 { 395 switch (eth_proto_oper) { 396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_SDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_DDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 406 *active_width = IB_WIDTH_1X; 407 *active_speed = IB_SPEED_QDR; 408 break; 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_EDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 418 *active_width = IB_WIDTH_2X; 419 *active_speed = IB_SPEED_EDR; 420 break; 421 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 422 *active_width = IB_WIDTH_1X; 423 *active_speed = IB_SPEED_HDR; 424 break; 425 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 430 *active_width = IB_WIDTH_2X; 431 *active_speed = IB_SPEED_HDR; 432 break; 433 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 434 *active_width = IB_WIDTH_1X; 435 *active_speed = IB_SPEED_NDR; 436 break; 437 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 438 *active_width = IB_WIDTH_4X; 439 *active_speed = IB_SPEED_HDR; 440 break; 441 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 442 *active_width = IB_WIDTH_2X; 443 *active_speed = IB_SPEED_NDR; 444 break; 445 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 446 *active_width = IB_WIDTH_4X; 447 *active_speed = IB_SPEED_NDR; 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 return 0; 454 } 455 456 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 457 u8 *active_width, bool ext) 458 { 459 return ext ? 460 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 461 active_width) : 462 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 463 active_width); 464 } 465 466 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 467 struct ib_port_attr *props) 468 { 469 struct mlx5_ib_dev *dev = to_mdev(device); 470 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 471 struct mlx5_core_dev *mdev; 472 struct net_device *ndev, *upper; 473 enum ib_mtu ndev_ib_mtu; 474 bool put_mdev = true; 475 u32 eth_prot_oper; 476 u32 mdev_port_num; 477 bool ext; 478 int err; 479 480 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 481 if (!mdev) { 482 /* This means the port isn't affiliated yet. Get the 483 * info for the master port instead. 484 */ 485 put_mdev = false; 486 mdev = dev->mdev; 487 mdev_port_num = 1; 488 port_num = 1; 489 } 490 491 /* Possible bad flows are checked before filling out props so in case 492 * of an error it will still be zeroed out. 493 * Use native port in case of reps 494 */ 495 if (dev->is_rep) 496 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 497 1); 498 else 499 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 500 mdev_port_num); 501 if (err) 502 goto out; 503 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 504 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 505 506 props->active_width = IB_WIDTH_4X; 507 props->active_speed = IB_SPEED_QDR; 508 509 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 510 &props->active_width, ext); 511 512 if (!dev->is_rep && dev->mdev->roce.roce_en) { 513 u16 qkey_viol_cntr; 514 515 props->port_cap_flags |= IB_PORT_CM_SUP; 516 props->ip_gids = true; 517 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 518 roce_address_table_size); 519 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 520 props->qkey_viol_cntr = qkey_viol_cntr; 521 } 522 props->max_mtu = IB_MTU_4096; 523 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 524 props->pkey_tbl_len = 1; 525 props->state = IB_PORT_DOWN; 526 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 527 528 /* If this is a stub query for an unaffiliated port stop here */ 529 if (!put_mdev) 530 goto out; 531 532 ndev = mlx5_ib_get_netdev(device, port_num); 533 if (!ndev) 534 goto out; 535 536 if (dev->lag_active) { 537 rcu_read_lock(); 538 upper = netdev_master_upper_dev_get_rcu(ndev); 539 if (upper) { 540 dev_put(ndev); 541 ndev = upper; 542 dev_hold(ndev); 543 } 544 rcu_read_unlock(); 545 } 546 547 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 548 props->state = IB_PORT_ACTIVE; 549 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 550 } 551 552 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 553 554 dev_put(ndev); 555 556 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 557 out: 558 if (put_mdev) 559 mlx5_ib_put_native_port_mdev(dev, port_num); 560 return err; 561 } 562 563 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 564 unsigned int index, const union ib_gid *gid, 565 const struct ib_gid_attr *attr) 566 { 567 enum ib_gid_type gid_type; 568 u16 vlan_id = 0xffff; 569 u8 roce_version = 0; 570 u8 roce_l3_type = 0; 571 u8 mac[ETH_ALEN]; 572 int ret; 573 574 gid_type = attr->gid_type; 575 if (gid) { 576 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 577 if (ret) 578 return ret; 579 } 580 581 switch (gid_type) { 582 case IB_GID_TYPE_ROCE: 583 roce_version = MLX5_ROCE_VERSION_1; 584 break; 585 case IB_GID_TYPE_ROCE_UDP_ENCAP: 586 roce_version = MLX5_ROCE_VERSION_2; 587 if (gid && ipv6_addr_v4mapped((void *)gid)) 588 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 589 else 590 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 591 break; 592 593 default: 594 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 595 } 596 597 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 598 roce_l3_type, gid->raw, mac, 599 vlan_id < VLAN_CFI_MASK, vlan_id, 600 port_num); 601 } 602 603 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 604 __always_unused void **context) 605 { 606 return set_roce_addr(to_mdev(attr->device), attr->port_num, 607 attr->index, &attr->gid, attr); 608 } 609 610 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 611 __always_unused void **context) 612 { 613 return set_roce_addr(to_mdev(attr->device), attr->port_num, 614 attr->index, NULL, attr); 615 } 616 617 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 618 const struct ib_gid_attr *attr) 619 { 620 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 621 return 0; 622 623 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 624 } 625 626 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 627 { 628 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 629 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 630 return 0; 631 } 632 633 enum { 634 MLX5_VPORT_ACCESS_METHOD_MAD, 635 MLX5_VPORT_ACCESS_METHOD_HCA, 636 MLX5_VPORT_ACCESS_METHOD_NIC, 637 }; 638 639 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 640 { 641 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 642 return MLX5_VPORT_ACCESS_METHOD_MAD; 643 644 if (mlx5_ib_port_link_layer(ibdev, 1) == 645 IB_LINK_LAYER_ETHERNET) 646 return MLX5_VPORT_ACCESS_METHOD_NIC; 647 648 return MLX5_VPORT_ACCESS_METHOD_HCA; 649 } 650 651 static void get_atomic_caps(struct mlx5_ib_dev *dev, 652 u8 atomic_size_qp, 653 struct ib_device_attr *props) 654 { 655 u8 tmp; 656 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 657 u8 atomic_req_8B_endianness_mode = 658 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 659 660 /* Check if HW supports 8 bytes standard atomic operations and capable 661 * of host endianness respond 662 */ 663 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 664 if (((atomic_operations & tmp) == tmp) && 665 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 666 (atomic_req_8B_endianness_mode)) { 667 props->atomic_cap = IB_ATOMIC_HCA; 668 } else { 669 props->atomic_cap = IB_ATOMIC_NONE; 670 } 671 } 672 673 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 674 struct ib_device_attr *props) 675 { 676 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 677 678 get_atomic_caps(dev, atomic_size_qp, props); 679 } 680 681 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 682 __be64 *sys_image_guid) 683 { 684 struct mlx5_ib_dev *dev = to_mdev(ibdev); 685 struct mlx5_core_dev *mdev = dev->mdev; 686 u64 tmp; 687 int err; 688 689 switch (mlx5_get_vport_access_method(ibdev)) { 690 case MLX5_VPORT_ACCESS_METHOD_MAD: 691 return mlx5_query_mad_ifc_system_image_guid(ibdev, 692 sys_image_guid); 693 694 case MLX5_VPORT_ACCESS_METHOD_HCA: 695 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 696 break; 697 698 case MLX5_VPORT_ACCESS_METHOD_NIC: 699 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 700 break; 701 702 default: 703 return -EINVAL; 704 } 705 706 if (!err) 707 *sys_image_guid = cpu_to_be64(tmp); 708 709 return err; 710 711 } 712 713 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 714 u16 *max_pkeys) 715 { 716 struct mlx5_ib_dev *dev = to_mdev(ibdev); 717 struct mlx5_core_dev *mdev = dev->mdev; 718 719 switch (mlx5_get_vport_access_method(ibdev)) { 720 case MLX5_VPORT_ACCESS_METHOD_MAD: 721 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 722 723 case MLX5_VPORT_ACCESS_METHOD_HCA: 724 case MLX5_VPORT_ACCESS_METHOD_NIC: 725 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 726 pkey_table_size)); 727 return 0; 728 729 default: 730 return -EINVAL; 731 } 732 } 733 734 static int mlx5_query_vendor_id(struct ib_device *ibdev, 735 u32 *vendor_id) 736 { 737 struct mlx5_ib_dev *dev = to_mdev(ibdev); 738 739 switch (mlx5_get_vport_access_method(ibdev)) { 740 case MLX5_VPORT_ACCESS_METHOD_MAD: 741 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 742 743 case MLX5_VPORT_ACCESS_METHOD_HCA: 744 case MLX5_VPORT_ACCESS_METHOD_NIC: 745 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 746 747 default: 748 return -EINVAL; 749 } 750 } 751 752 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 753 __be64 *node_guid) 754 { 755 u64 tmp; 756 int err; 757 758 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 759 case MLX5_VPORT_ACCESS_METHOD_MAD: 760 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 761 762 case MLX5_VPORT_ACCESS_METHOD_HCA: 763 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 764 break; 765 766 case MLX5_VPORT_ACCESS_METHOD_NIC: 767 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 768 break; 769 770 default: 771 return -EINVAL; 772 } 773 774 if (!err) 775 *node_guid = cpu_to_be64(tmp); 776 777 return err; 778 } 779 780 struct mlx5_reg_node_desc { 781 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 782 }; 783 784 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 785 { 786 struct mlx5_reg_node_desc in; 787 788 if (mlx5_use_mad_ifc(dev)) 789 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 790 791 memset(&in, 0, sizeof(in)); 792 793 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 794 sizeof(struct mlx5_reg_node_desc), 795 MLX5_REG_NODE_DESC, 0, 0); 796 } 797 798 static int mlx5_ib_query_device(struct ib_device *ibdev, 799 struct ib_device_attr *props, 800 struct ib_udata *uhw) 801 { 802 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 803 struct mlx5_ib_dev *dev = to_mdev(ibdev); 804 struct mlx5_core_dev *mdev = dev->mdev; 805 int err = -ENOMEM; 806 int max_sq_desc; 807 int max_rq_sg; 808 int max_sq_sg; 809 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 810 bool raw_support = !mlx5_core_mp_enabled(mdev); 811 struct mlx5_ib_query_device_resp resp = {}; 812 size_t resp_len; 813 u64 max_tso; 814 815 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 816 if (uhw_outlen && uhw_outlen < resp_len) 817 return -EINVAL; 818 819 resp.response_length = resp_len; 820 821 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 822 return -EINVAL; 823 824 memset(props, 0, sizeof(*props)); 825 err = mlx5_query_system_image_guid(ibdev, 826 &props->sys_image_guid); 827 if (err) 828 return err; 829 830 props->max_pkeys = dev->pkey_table_len; 831 832 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 833 if (err) 834 return err; 835 836 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 837 (fw_rev_min(dev->mdev) << 16) | 838 fw_rev_sub(dev->mdev); 839 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 840 IB_DEVICE_PORT_ACTIVE_EVENT | 841 IB_DEVICE_SYS_IMAGE_GUID | 842 IB_DEVICE_RC_RNR_NAK_GEN; 843 844 if (MLX5_CAP_GEN(mdev, pkv)) 845 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 846 if (MLX5_CAP_GEN(mdev, qkv)) 847 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 848 if (MLX5_CAP_GEN(mdev, apm)) 849 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 850 if (MLX5_CAP_GEN(mdev, xrc)) 851 props->device_cap_flags |= IB_DEVICE_XRC; 852 if (MLX5_CAP_GEN(mdev, imaicl)) { 853 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 854 IB_DEVICE_MEM_WINDOW_TYPE_2B; 855 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 856 /* We support 'Gappy' memory registration too */ 857 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 858 } 859 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 860 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 861 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 862 if (MLX5_CAP_GEN(mdev, sho)) { 863 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 864 /* At this stage no support for signature handover */ 865 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 866 IB_PROT_T10DIF_TYPE_2 | 867 IB_PROT_T10DIF_TYPE_3; 868 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 869 IB_GUARD_T10DIF_CSUM; 870 } 871 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 872 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 873 874 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 875 if (MLX5_CAP_ETH(mdev, csum_cap)) { 876 /* Legacy bit to support old userspace libraries */ 877 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 878 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 879 } 880 881 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 882 props->raw_packet_caps |= 883 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 884 885 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 886 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 887 if (max_tso) { 888 resp.tso_caps.max_tso = 1 << max_tso; 889 resp.tso_caps.supported_qpts |= 890 1 << IB_QPT_RAW_PACKET; 891 resp.response_length += sizeof(resp.tso_caps); 892 } 893 } 894 895 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 896 resp.rss_caps.rx_hash_function = 897 MLX5_RX_HASH_FUNC_TOEPLITZ; 898 resp.rss_caps.rx_hash_fields_mask = 899 MLX5_RX_HASH_SRC_IPV4 | 900 MLX5_RX_HASH_DST_IPV4 | 901 MLX5_RX_HASH_SRC_IPV6 | 902 MLX5_RX_HASH_DST_IPV6 | 903 MLX5_RX_HASH_SRC_PORT_TCP | 904 MLX5_RX_HASH_DST_PORT_TCP | 905 MLX5_RX_HASH_SRC_PORT_UDP | 906 MLX5_RX_HASH_DST_PORT_UDP | 907 MLX5_RX_HASH_INNER; 908 resp.response_length += sizeof(resp.rss_caps); 909 } 910 } else { 911 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 912 resp.response_length += sizeof(resp.tso_caps); 913 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 914 resp.response_length += sizeof(resp.rss_caps); 915 } 916 917 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 918 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 919 props->kernel_cap_flags |= IBK_UD_TSO; 920 } 921 922 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 923 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 924 raw_support) 925 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 926 927 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 928 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 929 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 930 931 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 932 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 933 raw_support) { 934 /* Legacy bit to support old userspace libraries */ 935 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 936 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 937 } 938 939 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 940 props->max_dm_size = 941 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 942 } 943 944 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 945 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 946 947 if (MLX5_CAP_GEN(mdev, end_pad)) 948 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 949 950 props->vendor_part_id = mdev->pdev->device; 951 props->hw_ver = mdev->pdev->revision; 952 953 props->max_mr_size = ~0ull; 954 props->page_size_cap = ~(min_page_size - 1); 955 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 956 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 957 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 958 sizeof(struct mlx5_wqe_data_seg); 959 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 960 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 961 sizeof(struct mlx5_wqe_raddr_seg)) / 962 sizeof(struct mlx5_wqe_data_seg); 963 props->max_send_sge = max_sq_sg; 964 props->max_recv_sge = max_rq_sg; 965 props->max_sge_rd = MLX5_MAX_SGE_RD; 966 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 967 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 968 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 969 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 970 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 971 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 972 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 973 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 974 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 975 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 976 props->max_srq_sge = max_rq_sg - 1; 977 props->max_fast_reg_page_list_len = 978 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 979 props->max_pi_fast_reg_page_list_len = 980 props->max_fast_reg_page_list_len / 2; 981 props->max_sgl_rd = 982 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 983 get_atomic_caps_qp(dev, props); 984 props->masked_atomic_cap = IB_ATOMIC_NONE; 985 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 986 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 987 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 988 props->max_mcast_grp; 989 props->max_ah = INT_MAX; 990 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 991 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 992 993 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 994 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 995 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 996 props->odp_caps = dev->odp_caps; 997 if (!uhw) { 998 /* ODP for kernel QPs is not implemented for receive 999 * WQEs and SRQ WQEs 1000 */ 1001 props->odp_caps.per_transport_caps.rc_odp_caps &= 1002 ~(IB_ODP_SUPPORT_READ | 1003 IB_ODP_SUPPORT_SRQ_RECV); 1004 props->odp_caps.per_transport_caps.uc_odp_caps &= 1005 ~(IB_ODP_SUPPORT_READ | 1006 IB_ODP_SUPPORT_SRQ_RECV); 1007 props->odp_caps.per_transport_caps.ud_odp_caps &= 1008 ~(IB_ODP_SUPPORT_READ | 1009 IB_ODP_SUPPORT_SRQ_RECV); 1010 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1011 ~(IB_ODP_SUPPORT_READ | 1012 IB_ODP_SUPPORT_SRQ_RECV); 1013 } 1014 } 1015 1016 if (mlx5_core_is_vf(mdev)) 1017 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1018 1019 if (mlx5_ib_port_link_layer(ibdev, 1) == 1020 IB_LINK_LAYER_ETHERNET && raw_support) { 1021 props->rss_caps.max_rwq_indirection_tables = 1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1023 props->rss_caps.max_rwq_indirection_table_size = 1024 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1025 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1026 props->max_wq_type_rq = 1027 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1028 } 1029 1030 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1031 props->tm_caps.max_num_tags = 1032 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1033 props->tm_caps.max_ops = 1034 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1035 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1036 } 1037 1038 if (MLX5_CAP_GEN(mdev, tag_matching) && 1039 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1040 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1041 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1042 } 1043 1044 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1045 props->cq_caps.max_cq_moderation_count = 1046 MLX5_MAX_CQ_COUNT; 1047 props->cq_caps.max_cq_moderation_period = 1048 MLX5_MAX_CQ_PERIOD; 1049 } 1050 1051 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1052 resp.response_length += sizeof(resp.cqe_comp_caps); 1053 1054 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1055 resp.cqe_comp_caps.max_num = 1056 MLX5_CAP_GEN(dev->mdev, 1057 cqe_compression_max_num); 1058 1059 resp.cqe_comp_caps.supported_format = 1060 MLX5_IB_CQE_RES_FORMAT_HASH | 1061 MLX5_IB_CQE_RES_FORMAT_CSUM; 1062 1063 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1064 resp.cqe_comp_caps.supported_format |= 1065 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1066 } 1067 } 1068 1069 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1070 raw_support) { 1071 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1072 MLX5_CAP_GEN(mdev, qos)) { 1073 resp.packet_pacing_caps.qp_rate_limit_max = 1074 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1075 resp.packet_pacing_caps.qp_rate_limit_min = 1076 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1077 resp.packet_pacing_caps.supported_qpts |= 1078 1 << IB_QPT_RAW_PACKET; 1079 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1080 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1081 resp.packet_pacing_caps.cap_flags |= 1082 MLX5_IB_PP_SUPPORT_BURST; 1083 } 1084 resp.response_length += sizeof(resp.packet_pacing_caps); 1085 } 1086 1087 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1088 uhw_outlen) { 1089 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1090 resp.mlx5_ib_support_multi_pkt_send_wqes = 1091 MLX5_IB_ALLOW_MPW; 1092 1093 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1094 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1095 MLX5_IB_SUPPORT_EMPW; 1096 1097 resp.response_length += 1098 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1099 } 1100 1101 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1102 resp.response_length += sizeof(resp.flags); 1103 1104 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1105 resp.flags |= 1106 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1107 1108 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1109 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1110 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1111 resp.flags |= 1112 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1113 1114 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1115 } 1116 1117 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1118 resp.response_length += sizeof(resp.sw_parsing_caps); 1119 if (MLX5_CAP_ETH(mdev, swp)) { 1120 resp.sw_parsing_caps.sw_parsing_offloads |= 1121 MLX5_IB_SW_PARSING; 1122 1123 if (MLX5_CAP_ETH(mdev, swp_csum)) 1124 resp.sw_parsing_caps.sw_parsing_offloads |= 1125 MLX5_IB_SW_PARSING_CSUM; 1126 1127 if (MLX5_CAP_ETH(mdev, swp_lso)) 1128 resp.sw_parsing_caps.sw_parsing_offloads |= 1129 MLX5_IB_SW_PARSING_LSO; 1130 1131 if (resp.sw_parsing_caps.sw_parsing_offloads) 1132 resp.sw_parsing_caps.supported_qpts = 1133 BIT(IB_QPT_RAW_PACKET); 1134 } 1135 } 1136 1137 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1138 raw_support) { 1139 resp.response_length += sizeof(resp.striding_rq_caps); 1140 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1141 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1142 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1143 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1144 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1145 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1146 resp.striding_rq_caps 1147 .min_single_wqe_log_num_of_strides = 1148 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1149 else 1150 resp.striding_rq_caps 1151 .min_single_wqe_log_num_of_strides = 1152 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1153 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1154 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1155 resp.striding_rq_caps.supported_qpts = 1156 BIT(IB_QPT_RAW_PACKET); 1157 } 1158 } 1159 1160 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1161 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1162 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1163 resp.tunnel_offloads_caps |= 1164 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1165 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1166 resp.tunnel_offloads_caps |= 1167 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1168 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1169 resp.tunnel_offloads_caps |= 1170 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1171 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1172 resp.tunnel_offloads_caps |= 1173 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1174 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1175 resp.tunnel_offloads_caps |= 1176 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1177 } 1178 1179 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1180 resp.response_length += sizeof(resp.dci_streams_caps); 1181 1182 resp.dci_streams_caps.max_log_num_concurent = 1183 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1184 1185 resp.dci_streams_caps.max_log_num_errored = 1186 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1187 } 1188 1189 if (uhw_outlen) { 1190 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1191 1192 if (err) 1193 return err; 1194 } 1195 1196 return 0; 1197 } 1198 1199 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1200 u8 *ib_width) 1201 { 1202 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1203 1204 if (active_width & MLX5_PTYS_WIDTH_1X) 1205 *ib_width = IB_WIDTH_1X; 1206 else if (active_width & MLX5_PTYS_WIDTH_2X) 1207 *ib_width = IB_WIDTH_2X; 1208 else if (active_width & MLX5_PTYS_WIDTH_4X) 1209 *ib_width = IB_WIDTH_4X; 1210 else if (active_width & MLX5_PTYS_WIDTH_8X) 1211 *ib_width = IB_WIDTH_8X; 1212 else if (active_width & MLX5_PTYS_WIDTH_12X) 1213 *ib_width = IB_WIDTH_12X; 1214 else { 1215 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1216 active_width); 1217 *ib_width = IB_WIDTH_4X; 1218 } 1219 1220 return; 1221 } 1222 1223 static int mlx5_mtu_to_ib_mtu(int mtu) 1224 { 1225 switch (mtu) { 1226 case 256: return 1; 1227 case 512: return 2; 1228 case 1024: return 3; 1229 case 2048: return 4; 1230 case 4096: return 5; 1231 default: 1232 pr_warn("invalid mtu\n"); 1233 return -1; 1234 } 1235 } 1236 1237 enum ib_max_vl_num { 1238 __IB_MAX_VL_0 = 1, 1239 __IB_MAX_VL_0_1 = 2, 1240 __IB_MAX_VL_0_3 = 3, 1241 __IB_MAX_VL_0_7 = 4, 1242 __IB_MAX_VL_0_14 = 5, 1243 }; 1244 1245 enum mlx5_vl_hw_cap { 1246 MLX5_VL_HW_0 = 1, 1247 MLX5_VL_HW_0_1 = 2, 1248 MLX5_VL_HW_0_2 = 3, 1249 MLX5_VL_HW_0_3 = 4, 1250 MLX5_VL_HW_0_4 = 5, 1251 MLX5_VL_HW_0_5 = 6, 1252 MLX5_VL_HW_0_6 = 7, 1253 MLX5_VL_HW_0_7 = 8, 1254 MLX5_VL_HW_0_14 = 15 1255 }; 1256 1257 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1258 u8 *max_vl_num) 1259 { 1260 switch (vl_hw_cap) { 1261 case MLX5_VL_HW_0: 1262 *max_vl_num = __IB_MAX_VL_0; 1263 break; 1264 case MLX5_VL_HW_0_1: 1265 *max_vl_num = __IB_MAX_VL_0_1; 1266 break; 1267 case MLX5_VL_HW_0_3: 1268 *max_vl_num = __IB_MAX_VL_0_3; 1269 break; 1270 case MLX5_VL_HW_0_7: 1271 *max_vl_num = __IB_MAX_VL_0_7; 1272 break; 1273 case MLX5_VL_HW_0_14: 1274 *max_vl_num = __IB_MAX_VL_0_14; 1275 break; 1276 1277 default: 1278 return -EINVAL; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1285 struct ib_port_attr *props) 1286 { 1287 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1288 struct mlx5_core_dev *mdev = dev->mdev; 1289 struct mlx5_hca_vport_context *rep; 1290 u16 max_mtu; 1291 u16 oper_mtu; 1292 int err; 1293 u16 ib_link_width_oper; 1294 u8 vl_hw_cap; 1295 1296 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1297 if (!rep) { 1298 err = -ENOMEM; 1299 goto out; 1300 } 1301 1302 /* props being zeroed by the caller, avoid zeroing it here */ 1303 1304 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1305 if (err) 1306 goto out; 1307 1308 props->lid = rep->lid; 1309 props->lmc = rep->lmc; 1310 props->sm_lid = rep->sm_lid; 1311 props->sm_sl = rep->sm_sl; 1312 props->state = rep->vport_state; 1313 props->phys_state = rep->port_physical_state; 1314 props->port_cap_flags = rep->cap_mask1; 1315 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1316 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1317 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1318 props->bad_pkey_cntr = rep->pkey_violation_counter; 1319 props->qkey_viol_cntr = rep->qkey_violation_counter; 1320 props->subnet_timeout = rep->subnet_timeout; 1321 props->init_type_reply = rep->init_type_reply; 1322 1323 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1324 props->port_cap_flags2 = rep->cap_mask2; 1325 1326 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1327 &props->active_speed, port); 1328 if (err) 1329 goto out; 1330 1331 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1332 1333 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1334 1335 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1336 1337 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1338 1339 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1340 1341 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1342 if (err) 1343 goto out; 1344 1345 err = translate_max_vl_num(ibdev, vl_hw_cap, 1346 &props->max_vl_num); 1347 out: 1348 kfree(rep); 1349 return err; 1350 } 1351 1352 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1353 struct ib_port_attr *props) 1354 { 1355 unsigned int count; 1356 int ret; 1357 1358 switch (mlx5_get_vport_access_method(ibdev)) { 1359 case MLX5_VPORT_ACCESS_METHOD_MAD: 1360 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1361 break; 1362 1363 case MLX5_VPORT_ACCESS_METHOD_HCA: 1364 ret = mlx5_query_hca_port(ibdev, port, props); 1365 break; 1366 1367 case MLX5_VPORT_ACCESS_METHOD_NIC: 1368 ret = mlx5_query_port_roce(ibdev, port, props); 1369 break; 1370 1371 default: 1372 ret = -EINVAL; 1373 } 1374 1375 if (!ret && props) { 1376 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1377 struct mlx5_core_dev *mdev; 1378 bool put_mdev = true; 1379 1380 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1381 if (!mdev) { 1382 /* If the port isn't affiliated yet query the master. 1383 * The master and slave will have the same values. 1384 */ 1385 mdev = dev->mdev; 1386 port = 1; 1387 put_mdev = false; 1388 } 1389 count = mlx5_core_reserved_gids_count(mdev); 1390 if (put_mdev) 1391 mlx5_ib_put_native_port_mdev(dev, port); 1392 props->gid_tbl_len -= count; 1393 } 1394 return ret; 1395 } 1396 1397 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1398 struct ib_port_attr *props) 1399 { 1400 return mlx5_query_port_roce(ibdev, port, props); 1401 } 1402 1403 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1404 u16 *pkey) 1405 { 1406 /* Default special Pkey for representor device port as per the 1407 * IB specification 1.3 section 10.9.1.2. 1408 */ 1409 *pkey = 0xffff; 1410 return 0; 1411 } 1412 1413 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1414 union ib_gid *gid) 1415 { 1416 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1417 struct mlx5_core_dev *mdev = dev->mdev; 1418 1419 switch (mlx5_get_vport_access_method(ibdev)) { 1420 case MLX5_VPORT_ACCESS_METHOD_MAD: 1421 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1422 1423 case MLX5_VPORT_ACCESS_METHOD_HCA: 1424 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1425 1426 default: 1427 return -EINVAL; 1428 } 1429 1430 } 1431 1432 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1433 u16 index, u16 *pkey) 1434 { 1435 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1436 struct mlx5_core_dev *mdev; 1437 bool put_mdev = true; 1438 u32 mdev_port_num; 1439 int err; 1440 1441 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1442 if (!mdev) { 1443 /* The port isn't affiliated yet, get the PKey from the master 1444 * port. For RoCE the PKey tables will be the same. 1445 */ 1446 put_mdev = false; 1447 mdev = dev->mdev; 1448 mdev_port_num = 1; 1449 } 1450 1451 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1452 index, pkey); 1453 if (put_mdev) 1454 mlx5_ib_put_native_port_mdev(dev, port); 1455 1456 return err; 1457 } 1458 1459 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1460 u16 *pkey) 1461 { 1462 switch (mlx5_get_vport_access_method(ibdev)) { 1463 case MLX5_VPORT_ACCESS_METHOD_MAD: 1464 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1465 1466 case MLX5_VPORT_ACCESS_METHOD_HCA: 1467 case MLX5_VPORT_ACCESS_METHOD_NIC: 1468 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1469 default: 1470 return -EINVAL; 1471 } 1472 } 1473 1474 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1475 struct ib_device_modify *props) 1476 { 1477 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1478 struct mlx5_reg_node_desc in; 1479 struct mlx5_reg_node_desc out; 1480 int err; 1481 1482 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1483 return -EOPNOTSUPP; 1484 1485 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1486 return 0; 1487 1488 /* 1489 * If possible, pass node desc to FW, so it can generate 1490 * a 144 trap. If cmd fails, just ignore. 1491 */ 1492 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1493 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1494 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1495 if (err) 1496 return err; 1497 1498 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1499 1500 return err; 1501 } 1502 1503 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1504 u32 value) 1505 { 1506 struct mlx5_hca_vport_context ctx = {}; 1507 struct mlx5_core_dev *mdev; 1508 u32 mdev_port_num; 1509 int err; 1510 1511 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1512 if (!mdev) 1513 return -ENODEV; 1514 1515 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1516 if (err) 1517 goto out; 1518 1519 if (~ctx.cap_mask1_perm & mask) { 1520 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1521 mask, ctx.cap_mask1_perm); 1522 err = -EINVAL; 1523 goto out; 1524 } 1525 1526 ctx.cap_mask1 = value; 1527 ctx.cap_mask1_perm = mask; 1528 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1529 0, &ctx); 1530 1531 out: 1532 mlx5_ib_put_native_port_mdev(dev, port_num); 1533 1534 return err; 1535 } 1536 1537 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1538 struct ib_port_modify *props) 1539 { 1540 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1541 struct ib_port_attr attr; 1542 u32 tmp; 1543 int err; 1544 u32 change_mask; 1545 u32 value; 1546 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1547 IB_LINK_LAYER_INFINIBAND); 1548 1549 /* CM layer calls ib_modify_port() regardless of the link layer. For 1550 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1551 */ 1552 if (!is_ib) 1553 return 0; 1554 1555 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1556 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1557 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1558 return set_port_caps_atomic(dev, port, change_mask, value); 1559 } 1560 1561 mutex_lock(&dev->cap_mask_mutex); 1562 1563 err = ib_query_port(ibdev, port, &attr); 1564 if (err) 1565 goto out; 1566 1567 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1568 ~props->clr_port_cap_mask; 1569 1570 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1571 1572 out: 1573 mutex_unlock(&dev->cap_mask_mutex); 1574 return err; 1575 } 1576 1577 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1578 { 1579 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1580 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1581 } 1582 1583 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1584 { 1585 /* Large page with non 4k uar support might limit the dynamic size */ 1586 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1587 return MLX5_MIN_DYN_BFREGS; 1588 1589 return MLX5_MAX_DYN_BFREGS; 1590 } 1591 1592 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1593 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1594 struct mlx5_bfreg_info *bfregi) 1595 { 1596 int uars_per_sys_page; 1597 int bfregs_per_sys_page; 1598 int ref_bfregs = req->total_num_bfregs; 1599 1600 if (req->total_num_bfregs == 0) 1601 return -EINVAL; 1602 1603 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1604 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1605 1606 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1607 return -ENOMEM; 1608 1609 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1610 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1611 /* This holds the required static allocation asked by the user */ 1612 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1613 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1614 return -EINVAL; 1615 1616 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1617 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1618 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1619 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1620 1621 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1622 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1623 lib_uar_4k ? "yes" : "no", ref_bfregs, 1624 req->total_num_bfregs, bfregi->total_num_bfregs, 1625 bfregi->num_sys_pages); 1626 1627 return 0; 1628 } 1629 1630 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1631 { 1632 struct mlx5_bfreg_info *bfregi; 1633 int err; 1634 int i; 1635 1636 bfregi = &context->bfregi; 1637 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1638 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1639 context->devx_uid); 1640 if (err) 1641 goto error; 1642 1643 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1644 } 1645 1646 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1647 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1648 1649 return 0; 1650 1651 error: 1652 for (--i; i >= 0; i--) 1653 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1654 context->devx_uid)) 1655 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1656 1657 return err; 1658 } 1659 1660 static void deallocate_uars(struct mlx5_ib_dev *dev, 1661 struct mlx5_ib_ucontext *context) 1662 { 1663 struct mlx5_bfreg_info *bfregi; 1664 int i; 1665 1666 bfregi = &context->bfregi; 1667 for (i = 0; i < bfregi->num_sys_pages; i++) 1668 if (i < bfregi->num_static_sys_pages || 1669 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1670 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1671 context->devx_uid); 1672 } 1673 1674 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1675 { 1676 int err = 0; 1677 1678 mutex_lock(&dev->lb.mutex); 1679 if (td) 1680 dev->lb.user_td++; 1681 if (qp) 1682 dev->lb.qps++; 1683 1684 if (dev->lb.user_td == 2 || 1685 dev->lb.qps == 1) { 1686 if (!dev->lb.enabled) { 1687 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1688 dev->lb.enabled = true; 1689 } 1690 } 1691 1692 mutex_unlock(&dev->lb.mutex); 1693 1694 return err; 1695 } 1696 1697 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1698 { 1699 mutex_lock(&dev->lb.mutex); 1700 if (td) 1701 dev->lb.user_td--; 1702 if (qp) 1703 dev->lb.qps--; 1704 1705 if (dev->lb.user_td == 1 && 1706 dev->lb.qps == 0) { 1707 if (dev->lb.enabled) { 1708 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1709 dev->lb.enabled = false; 1710 } 1711 } 1712 1713 mutex_unlock(&dev->lb.mutex); 1714 } 1715 1716 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1717 u16 uid) 1718 { 1719 int err; 1720 1721 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1722 return 0; 1723 1724 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1725 if (err) 1726 return err; 1727 1728 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1729 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1730 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1731 return err; 1732 1733 return mlx5_ib_enable_lb(dev, true, false); 1734 } 1735 1736 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1737 u16 uid) 1738 { 1739 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1740 return; 1741 1742 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1743 1744 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1745 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1746 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1747 return; 1748 1749 mlx5_ib_disable_lb(dev, true, false); 1750 } 1751 1752 static int set_ucontext_resp(struct ib_ucontext *uctx, 1753 struct mlx5_ib_alloc_ucontext_resp *resp) 1754 { 1755 struct ib_device *ibdev = uctx->device; 1756 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1757 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1758 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1759 1760 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1761 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1762 resp->comp_mask |= 1763 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1764 } 1765 1766 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1767 if (dev->wc_support) 1768 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1769 log_bf_reg_size); 1770 resp->cache_line_size = cache_line_size(); 1771 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1772 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1773 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1774 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1775 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1776 resp->cqe_version = context->cqe_version; 1777 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1778 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1779 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1780 MLX5_CAP_GEN(dev->mdev, 1781 num_of_uars_per_page) : 1; 1782 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1783 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1784 resp->num_ports = dev->num_ports; 1785 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1786 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1787 1788 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1789 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1790 resp->eth_min_inline++; 1791 } 1792 1793 if (dev->mdev->clock_info) 1794 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1795 1796 /* 1797 * We don't want to expose information from the PCI bar that is located 1798 * after 4096 bytes, so if the arch only supports larger pages, let's 1799 * pretend we don't support reading the HCA's core clock. This is also 1800 * forced by mmap function. 1801 */ 1802 if (PAGE_SIZE <= 4096) { 1803 resp->comp_mask |= 1804 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1805 resp->hca_core_clock_offset = 1806 offsetof(struct mlx5_init_seg, 1807 internal_timer_h) % PAGE_SIZE; 1808 } 1809 1810 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1811 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1812 1813 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1814 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1815 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1816 resp->comp_mask |= 1817 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1818 1819 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1820 1821 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1822 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1823 1824 resp->comp_mask |= 1825 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1826 1827 return 0; 1828 } 1829 1830 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1831 struct ib_udata *udata) 1832 { 1833 struct ib_device *ibdev = uctx->device; 1834 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1835 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1836 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1837 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1838 struct mlx5_bfreg_info *bfregi; 1839 int ver; 1840 int err; 1841 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1842 max_cqe_version); 1843 bool lib_uar_4k; 1844 bool lib_uar_dyn; 1845 1846 if (!dev->ib_active) 1847 return -EAGAIN; 1848 1849 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1850 ver = 0; 1851 else if (udata->inlen >= min_req_v2) 1852 ver = 2; 1853 else 1854 return -EINVAL; 1855 1856 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1857 if (err) 1858 return err; 1859 1860 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1861 return -EOPNOTSUPP; 1862 1863 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1864 return -EOPNOTSUPP; 1865 1866 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1867 MLX5_NON_FP_BFREGS_PER_UAR); 1868 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1869 return -EINVAL; 1870 1871 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1872 err = mlx5_ib_devx_create(dev, true); 1873 if (err < 0) 1874 goto out_ctx; 1875 context->devx_uid = err; 1876 } 1877 1878 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1879 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1880 bfregi = &context->bfregi; 1881 1882 if (lib_uar_dyn) { 1883 bfregi->lib_uar_dyn = lib_uar_dyn; 1884 goto uar_done; 1885 } 1886 1887 /* updates req->total_num_bfregs */ 1888 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1889 if (err) 1890 goto out_devx; 1891 1892 mutex_init(&bfregi->lock); 1893 bfregi->lib_uar_4k = lib_uar_4k; 1894 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1895 GFP_KERNEL); 1896 if (!bfregi->count) { 1897 err = -ENOMEM; 1898 goto out_devx; 1899 } 1900 1901 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1902 sizeof(*bfregi->sys_pages), 1903 GFP_KERNEL); 1904 if (!bfregi->sys_pages) { 1905 err = -ENOMEM; 1906 goto out_count; 1907 } 1908 1909 err = allocate_uars(dev, context); 1910 if (err) 1911 goto out_sys_pages; 1912 1913 uar_done: 1914 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1915 context->devx_uid); 1916 if (err) 1917 goto out_uars; 1918 1919 INIT_LIST_HEAD(&context->db_page_list); 1920 mutex_init(&context->db_page_mutex); 1921 1922 context->cqe_version = min_t(__u8, 1923 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1924 req.max_cqe_version); 1925 1926 err = set_ucontext_resp(uctx, &resp); 1927 if (err) 1928 goto out_mdev; 1929 1930 resp.response_length = min(udata->outlen, sizeof(resp)); 1931 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1932 if (err) 1933 goto out_mdev; 1934 1935 bfregi->ver = ver; 1936 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1937 context->lib_caps = req.lib_caps; 1938 print_lib_caps(dev, context->lib_caps); 1939 1940 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1941 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1942 1943 atomic_set(&context->tx_port_affinity, 1944 atomic_add_return( 1945 1, &dev->port[port].roce.tx_port_affinity)); 1946 } 1947 1948 return 0; 1949 1950 out_mdev: 1951 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1952 1953 out_uars: 1954 deallocate_uars(dev, context); 1955 1956 out_sys_pages: 1957 kfree(bfregi->sys_pages); 1958 1959 out_count: 1960 kfree(bfregi->count); 1961 1962 out_devx: 1963 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1964 mlx5_ib_devx_destroy(dev, context->devx_uid); 1965 1966 out_ctx: 1967 return err; 1968 } 1969 1970 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1971 struct uverbs_attr_bundle *attrs) 1972 { 1973 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1974 int ret; 1975 1976 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1977 if (ret) 1978 return ret; 1979 1980 uctx_resp.response_length = 1981 min_t(size_t, 1982 uverbs_attr_get_len(attrs, 1983 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1984 sizeof(uctx_resp)); 1985 1986 ret = uverbs_copy_to_struct_or_zero(attrs, 1987 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1988 &uctx_resp, 1989 sizeof(uctx_resp)); 1990 return ret; 1991 } 1992 1993 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1994 { 1995 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1996 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1997 struct mlx5_bfreg_info *bfregi; 1998 1999 bfregi = &context->bfregi; 2000 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2001 2002 deallocate_uars(dev, context); 2003 kfree(bfregi->sys_pages); 2004 kfree(bfregi->count); 2005 2006 if (context->devx_uid) 2007 mlx5_ib_devx_destroy(dev, context->devx_uid); 2008 } 2009 2010 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2011 int uar_idx) 2012 { 2013 int fw_uars_per_page; 2014 2015 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2016 2017 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2018 } 2019 2020 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2021 int uar_idx) 2022 { 2023 unsigned int fw_uars_per_page; 2024 2025 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2026 MLX5_UARS_IN_PAGE : 1; 2027 2028 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2029 } 2030 2031 static int get_command(unsigned long offset) 2032 { 2033 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2034 } 2035 2036 static int get_arg(unsigned long offset) 2037 { 2038 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2039 } 2040 2041 static int get_index(unsigned long offset) 2042 { 2043 return get_arg(offset); 2044 } 2045 2046 /* Index resides in an extra byte to enable larger values than 255 */ 2047 static int get_extended_index(unsigned long offset) 2048 { 2049 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2050 } 2051 2052 2053 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2054 { 2055 } 2056 2057 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2058 { 2059 switch (cmd) { 2060 case MLX5_IB_MMAP_WC_PAGE: 2061 return "WC"; 2062 case MLX5_IB_MMAP_REGULAR_PAGE: 2063 return "best effort WC"; 2064 case MLX5_IB_MMAP_NC_PAGE: 2065 return "NC"; 2066 case MLX5_IB_MMAP_DEVICE_MEM: 2067 return "Device Memory"; 2068 default: 2069 return NULL; 2070 } 2071 } 2072 2073 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2074 struct vm_area_struct *vma, 2075 struct mlx5_ib_ucontext *context) 2076 { 2077 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2078 !(vma->vm_flags & VM_SHARED)) 2079 return -EINVAL; 2080 2081 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2082 return -EOPNOTSUPP; 2083 2084 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2085 return -EPERM; 2086 vm_flags_clear(vma, VM_MAYWRITE); 2087 2088 if (!dev->mdev->clock_info) 2089 return -EOPNOTSUPP; 2090 2091 return vm_insert_page(vma, vma->vm_start, 2092 virt_to_page(dev->mdev->clock_info)); 2093 } 2094 2095 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2096 { 2097 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2098 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2099 struct mlx5_var_table *var_table = &dev->var_table; 2100 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2101 2102 switch (mentry->mmap_flag) { 2103 case MLX5_IB_MMAP_TYPE_MEMIC: 2104 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2105 mlx5_ib_dm_mmap_free(dev, mentry); 2106 break; 2107 case MLX5_IB_MMAP_TYPE_VAR: 2108 mutex_lock(&var_table->bitmap_lock); 2109 clear_bit(mentry->page_idx, var_table->bitmap); 2110 mutex_unlock(&var_table->bitmap_lock); 2111 kfree(mentry); 2112 break; 2113 case MLX5_IB_MMAP_TYPE_UAR_WC: 2114 case MLX5_IB_MMAP_TYPE_UAR_NC: 2115 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2116 context->devx_uid); 2117 kfree(mentry); 2118 break; 2119 default: 2120 WARN_ON(true); 2121 } 2122 } 2123 2124 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2125 struct vm_area_struct *vma, 2126 struct mlx5_ib_ucontext *context) 2127 { 2128 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2129 int err; 2130 unsigned long idx; 2131 phys_addr_t pfn; 2132 pgprot_t prot; 2133 u32 bfreg_dyn_idx = 0; 2134 u32 uar_index; 2135 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2136 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2137 bfregi->num_static_sys_pages; 2138 2139 if (bfregi->lib_uar_dyn) 2140 return -EINVAL; 2141 2142 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2143 return -EINVAL; 2144 2145 if (dyn_uar) 2146 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2147 else 2148 idx = get_index(vma->vm_pgoff); 2149 2150 if (idx >= max_valid_idx) { 2151 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2152 idx, max_valid_idx); 2153 return -EINVAL; 2154 } 2155 2156 switch (cmd) { 2157 case MLX5_IB_MMAP_WC_PAGE: 2158 case MLX5_IB_MMAP_ALLOC_WC: 2159 case MLX5_IB_MMAP_REGULAR_PAGE: 2160 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2161 prot = pgprot_writecombine(vma->vm_page_prot); 2162 break; 2163 case MLX5_IB_MMAP_NC_PAGE: 2164 prot = pgprot_noncached(vma->vm_page_prot); 2165 break; 2166 default: 2167 return -EINVAL; 2168 } 2169 2170 if (dyn_uar) { 2171 int uars_per_page; 2172 2173 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2174 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2175 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2176 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2177 bfreg_dyn_idx, bfregi->total_num_bfregs); 2178 return -EINVAL; 2179 } 2180 2181 mutex_lock(&bfregi->lock); 2182 /* Fail if uar already allocated, first bfreg index of each 2183 * page holds its count. 2184 */ 2185 if (bfregi->count[bfreg_dyn_idx]) { 2186 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2187 mutex_unlock(&bfregi->lock); 2188 return -EINVAL; 2189 } 2190 2191 bfregi->count[bfreg_dyn_idx]++; 2192 mutex_unlock(&bfregi->lock); 2193 2194 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2195 context->devx_uid); 2196 if (err) { 2197 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2198 goto free_bfreg; 2199 } 2200 } else { 2201 uar_index = bfregi->sys_pages[idx]; 2202 } 2203 2204 pfn = uar_index2pfn(dev, uar_index); 2205 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2206 2207 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2208 prot, NULL); 2209 if (err) { 2210 mlx5_ib_err(dev, 2211 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2212 err, mmap_cmd2str(cmd)); 2213 goto err; 2214 } 2215 2216 if (dyn_uar) 2217 bfregi->sys_pages[idx] = uar_index; 2218 return 0; 2219 2220 err: 2221 if (!dyn_uar) 2222 return err; 2223 2224 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2225 2226 free_bfreg: 2227 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2228 2229 return err; 2230 } 2231 2232 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2233 { 2234 unsigned long idx; 2235 u8 command; 2236 2237 command = get_command(vma->vm_pgoff); 2238 idx = get_extended_index(vma->vm_pgoff); 2239 2240 return (command << 16 | idx); 2241 } 2242 2243 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2244 struct vm_area_struct *vma, 2245 struct ib_ucontext *ucontext) 2246 { 2247 struct mlx5_user_mmap_entry *mentry; 2248 struct rdma_user_mmap_entry *entry; 2249 unsigned long pgoff; 2250 pgprot_t prot; 2251 phys_addr_t pfn; 2252 int ret; 2253 2254 pgoff = mlx5_vma_to_pgoff(vma); 2255 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2256 if (!entry) 2257 return -EINVAL; 2258 2259 mentry = to_mmmap(entry); 2260 pfn = (mentry->address >> PAGE_SHIFT); 2261 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2262 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2263 prot = pgprot_noncached(vma->vm_page_prot); 2264 else 2265 prot = pgprot_writecombine(vma->vm_page_prot); 2266 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2267 entry->npages * PAGE_SIZE, 2268 prot, 2269 entry); 2270 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2271 return ret; 2272 } 2273 2274 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2275 { 2276 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2277 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2278 2279 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2280 (index & 0xFF)) << PAGE_SHIFT; 2281 } 2282 2283 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2284 { 2285 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2286 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2287 unsigned long command; 2288 phys_addr_t pfn; 2289 2290 command = get_command(vma->vm_pgoff); 2291 switch (command) { 2292 case MLX5_IB_MMAP_WC_PAGE: 2293 case MLX5_IB_MMAP_ALLOC_WC: 2294 if (!dev->wc_support) 2295 return -EPERM; 2296 fallthrough; 2297 case MLX5_IB_MMAP_NC_PAGE: 2298 case MLX5_IB_MMAP_REGULAR_PAGE: 2299 return uar_mmap(dev, command, vma, context); 2300 2301 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2302 return -ENOSYS; 2303 2304 case MLX5_IB_MMAP_CORE_CLOCK: 2305 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2306 return -EINVAL; 2307 2308 if (vma->vm_flags & VM_WRITE) 2309 return -EPERM; 2310 vm_flags_clear(vma, VM_MAYWRITE); 2311 2312 /* Don't expose to user-space information it shouldn't have */ 2313 if (PAGE_SIZE > 4096) 2314 return -EOPNOTSUPP; 2315 2316 pfn = (dev->mdev->iseg_base + 2317 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2318 PAGE_SHIFT; 2319 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2320 PAGE_SIZE, 2321 pgprot_noncached(vma->vm_page_prot), 2322 NULL); 2323 case MLX5_IB_MMAP_CLOCK_INFO: 2324 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2325 2326 default: 2327 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2328 } 2329 2330 return 0; 2331 } 2332 2333 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2334 { 2335 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2336 struct ib_device *ibdev = ibpd->device; 2337 struct mlx5_ib_alloc_pd_resp resp; 2338 int err; 2339 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2340 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2341 u16 uid = 0; 2342 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2343 udata, struct mlx5_ib_ucontext, ibucontext); 2344 2345 uid = context ? context->devx_uid : 0; 2346 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2347 MLX5_SET(alloc_pd_in, in, uid, uid); 2348 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2349 if (err) 2350 return err; 2351 2352 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2353 pd->uid = uid; 2354 if (udata) { 2355 resp.pdn = pd->pdn; 2356 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2357 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2358 return -EFAULT; 2359 } 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2366 { 2367 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2368 struct mlx5_ib_pd *mpd = to_mpd(pd); 2369 2370 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2371 } 2372 2373 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2374 { 2375 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2376 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2377 int err; 2378 u16 uid; 2379 2380 uid = ibqp->pd ? 2381 to_mpd(ibqp->pd)->uid : 0; 2382 2383 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2384 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2385 return -EOPNOTSUPP; 2386 } 2387 2388 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2389 if (err) 2390 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2391 ibqp->qp_num, gid->raw); 2392 2393 return err; 2394 } 2395 2396 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2397 { 2398 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2399 int err; 2400 u16 uid; 2401 2402 uid = ibqp->pd ? 2403 to_mpd(ibqp->pd)->uid : 0; 2404 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2405 if (err) 2406 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2407 ibqp->qp_num, gid->raw); 2408 2409 return err; 2410 } 2411 2412 static int init_node_data(struct mlx5_ib_dev *dev) 2413 { 2414 int err; 2415 2416 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2417 if (err) 2418 return err; 2419 2420 dev->mdev->rev_id = dev->mdev->pdev->revision; 2421 2422 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2423 } 2424 2425 static ssize_t fw_pages_show(struct device *device, 2426 struct device_attribute *attr, char *buf) 2427 { 2428 struct mlx5_ib_dev *dev = 2429 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2430 2431 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2432 } 2433 static DEVICE_ATTR_RO(fw_pages); 2434 2435 static ssize_t reg_pages_show(struct device *device, 2436 struct device_attribute *attr, char *buf) 2437 { 2438 struct mlx5_ib_dev *dev = 2439 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2440 2441 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2442 } 2443 static DEVICE_ATTR_RO(reg_pages); 2444 2445 static ssize_t hca_type_show(struct device *device, 2446 struct device_attribute *attr, char *buf) 2447 { 2448 struct mlx5_ib_dev *dev = 2449 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2450 2451 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2452 } 2453 static DEVICE_ATTR_RO(hca_type); 2454 2455 static ssize_t hw_rev_show(struct device *device, 2456 struct device_attribute *attr, char *buf) 2457 { 2458 struct mlx5_ib_dev *dev = 2459 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2460 2461 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2462 } 2463 static DEVICE_ATTR_RO(hw_rev); 2464 2465 static ssize_t board_id_show(struct device *device, 2466 struct device_attribute *attr, char *buf) 2467 { 2468 struct mlx5_ib_dev *dev = 2469 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2470 2471 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2472 dev->mdev->board_id); 2473 } 2474 static DEVICE_ATTR_RO(board_id); 2475 2476 static struct attribute *mlx5_class_attributes[] = { 2477 &dev_attr_hw_rev.attr, 2478 &dev_attr_hca_type.attr, 2479 &dev_attr_board_id.attr, 2480 &dev_attr_fw_pages.attr, 2481 &dev_attr_reg_pages.attr, 2482 NULL, 2483 }; 2484 2485 static const struct attribute_group mlx5_attr_group = { 2486 .attrs = mlx5_class_attributes, 2487 }; 2488 2489 static void pkey_change_handler(struct work_struct *work) 2490 { 2491 struct mlx5_ib_port_resources *ports = 2492 container_of(work, struct mlx5_ib_port_resources, 2493 pkey_change_work); 2494 2495 if (!ports->gsi) 2496 /* 2497 * We got this event before device was fully configured 2498 * and MAD registration code wasn't called/finished yet. 2499 */ 2500 return; 2501 2502 mlx5_ib_gsi_pkey_change(ports->gsi); 2503 } 2504 2505 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2506 { 2507 struct mlx5_ib_qp *mqp; 2508 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2509 struct mlx5_core_cq *mcq; 2510 struct list_head cq_armed_list; 2511 unsigned long flags_qp; 2512 unsigned long flags_cq; 2513 unsigned long flags; 2514 2515 INIT_LIST_HEAD(&cq_armed_list); 2516 2517 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2518 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2519 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2520 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2521 if (mqp->sq.tail != mqp->sq.head) { 2522 send_mcq = to_mcq(mqp->ibqp.send_cq); 2523 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2524 if (send_mcq->mcq.comp && 2525 mqp->ibqp.send_cq->comp_handler) { 2526 if (!send_mcq->mcq.reset_notify_added) { 2527 send_mcq->mcq.reset_notify_added = 1; 2528 list_add_tail(&send_mcq->mcq.reset_notify, 2529 &cq_armed_list); 2530 } 2531 } 2532 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2533 } 2534 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2535 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2536 /* no handling is needed for SRQ */ 2537 if (!mqp->ibqp.srq) { 2538 if (mqp->rq.tail != mqp->rq.head) { 2539 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2540 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2541 if (recv_mcq->mcq.comp && 2542 mqp->ibqp.recv_cq->comp_handler) { 2543 if (!recv_mcq->mcq.reset_notify_added) { 2544 recv_mcq->mcq.reset_notify_added = 1; 2545 list_add_tail(&recv_mcq->mcq.reset_notify, 2546 &cq_armed_list); 2547 } 2548 } 2549 spin_unlock_irqrestore(&recv_mcq->lock, 2550 flags_cq); 2551 } 2552 } 2553 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2554 } 2555 /*At that point all inflight post send were put to be executed as of we 2556 * lock/unlock above locks Now need to arm all involved CQs. 2557 */ 2558 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2559 mcq->comp(mcq, NULL); 2560 } 2561 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2562 } 2563 2564 static void delay_drop_handler(struct work_struct *work) 2565 { 2566 int err; 2567 struct mlx5_ib_delay_drop *delay_drop = 2568 container_of(work, struct mlx5_ib_delay_drop, 2569 delay_drop_work); 2570 2571 atomic_inc(&delay_drop->events_cnt); 2572 2573 mutex_lock(&delay_drop->lock); 2574 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2575 if (err) { 2576 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2577 delay_drop->timeout); 2578 delay_drop->activate = false; 2579 } 2580 mutex_unlock(&delay_drop->lock); 2581 } 2582 2583 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2584 struct ib_event *ibev) 2585 { 2586 u32 port = (eqe->data.port.port >> 4) & 0xf; 2587 2588 switch (eqe->sub_type) { 2589 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2590 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2591 IB_LINK_LAYER_ETHERNET) 2592 schedule_work(&ibdev->delay_drop.delay_drop_work); 2593 break; 2594 default: /* do nothing */ 2595 return; 2596 } 2597 } 2598 2599 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2600 struct ib_event *ibev) 2601 { 2602 u32 port = (eqe->data.port.port >> 4) & 0xf; 2603 2604 ibev->element.port_num = port; 2605 2606 switch (eqe->sub_type) { 2607 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2608 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2609 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2610 /* In RoCE, port up/down events are handled in 2611 * mlx5_netdev_event(). 2612 */ 2613 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2614 IB_LINK_LAYER_ETHERNET) 2615 return -EINVAL; 2616 2617 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2618 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2619 break; 2620 2621 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2622 ibev->event = IB_EVENT_LID_CHANGE; 2623 break; 2624 2625 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2626 ibev->event = IB_EVENT_PKEY_CHANGE; 2627 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2628 break; 2629 2630 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2631 ibev->event = IB_EVENT_GID_CHANGE; 2632 break; 2633 2634 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2635 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2636 break; 2637 default: 2638 return -EINVAL; 2639 } 2640 2641 return 0; 2642 } 2643 2644 static void mlx5_ib_handle_event(struct work_struct *_work) 2645 { 2646 struct mlx5_ib_event_work *work = 2647 container_of(_work, struct mlx5_ib_event_work, work); 2648 struct mlx5_ib_dev *ibdev; 2649 struct ib_event ibev; 2650 bool fatal = false; 2651 2652 if (work->is_slave) { 2653 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2654 if (!ibdev) 2655 goto out; 2656 } else { 2657 ibdev = work->dev; 2658 } 2659 2660 switch (work->event) { 2661 case MLX5_DEV_EVENT_SYS_ERROR: 2662 ibev.event = IB_EVENT_DEVICE_FATAL; 2663 mlx5_ib_handle_internal_error(ibdev); 2664 ibev.element.port_num = (u8)(unsigned long)work->param; 2665 fatal = true; 2666 break; 2667 case MLX5_EVENT_TYPE_PORT_CHANGE: 2668 if (handle_port_change(ibdev, work->param, &ibev)) 2669 goto out; 2670 break; 2671 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2672 handle_general_event(ibdev, work->param, &ibev); 2673 fallthrough; 2674 default: 2675 goto out; 2676 } 2677 2678 ibev.device = &ibdev->ib_dev; 2679 2680 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2681 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2682 goto out; 2683 } 2684 2685 if (ibdev->ib_active) 2686 ib_dispatch_event(&ibev); 2687 2688 if (fatal) 2689 ibdev->ib_active = false; 2690 out: 2691 kfree(work); 2692 } 2693 2694 static int mlx5_ib_event(struct notifier_block *nb, 2695 unsigned long event, void *param) 2696 { 2697 struct mlx5_ib_event_work *work; 2698 2699 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2700 if (!work) 2701 return NOTIFY_DONE; 2702 2703 INIT_WORK(&work->work, mlx5_ib_handle_event); 2704 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2705 work->is_slave = false; 2706 work->param = param; 2707 work->event = event; 2708 2709 queue_work(mlx5_ib_event_wq, &work->work); 2710 2711 return NOTIFY_OK; 2712 } 2713 2714 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2715 unsigned long event, void *param) 2716 { 2717 struct mlx5_ib_event_work *work; 2718 2719 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2720 if (!work) 2721 return NOTIFY_DONE; 2722 2723 INIT_WORK(&work->work, mlx5_ib_handle_event); 2724 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2725 work->is_slave = true; 2726 work->param = param; 2727 work->event = event; 2728 queue_work(mlx5_ib_event_wq, &work->work); 2729 2730 return NOTIFY_OK; 2731 } 2732 2733 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2734 { 2735 struct mlx5_hca_vport_context vport_ctx; 2736 int err; 2737 int port; 2738 2739 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2740 return 0; 2741 2742 for (port = 1; port <= dev->num_ports; port++) { 2743 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2744 dev->port_caps[port - 1].has_smi = true; 2745 continue; 2746 } 2747 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2748 &vport_ctx); 2749 if (err) { 2750 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2751 port, err); 2752 return err; 2753 } 2754 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2755 } 2756 2757 return 0; 2758 } 2759 2760 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2761 { 2762 unsigned int port; 2763 2764 rdma_for_each_port (&dev->ib_dev, port) 2765 mlx5_query_ext_port_caps(dev, port); 2766 } 2767 2768 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2769 { 2770 switch (umr_fence_cap) { 2771 case MLX5_CAP_UMR_FENCE_NONE: 2772 return MLX5_FENCE_MODE_NONE; 2773 case MLX5_CAP_UMR_FENCE_SMALL: 2774 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2775 default: 2776 return MLX5_FENCE_MODE_STRONG_ORDERING; 2777 } 2778 } 2779 2780 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2781 { 2782 struct mlx5_ib_resources *devr = &dev->devr; 2783 struct ib_srq_init_attr attr; 2784 struct ib_device *ibdev; 2785 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2786 int port; 2787 int ret = 0; 2788 2789 ibdev = &dev->ib_dev; 2790 2791 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2792 return -EOPNOTSUPP; 2793 2794 devr->p0 = ib_alloc_pd(ibdev, 0); 2795 if (IS_ERR(devr->p0)) 2796 return PTR_ERR(devr->p0); 2797 2798 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2799 if (IS_ERR(devr->c0)) { 2800 ret = PTR_ERR(devr->c0); 2801 goto error1; 2802 } 2803 2804 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2805 if (ret) 2806 goto error2; 2807 2808 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2809 if (ret) 2810 goto error3; 2811 2812 memset(&attr, 0, sizeof(attr)); 2813 attr.attr.max_sge = 1; 2814 attr.attr.max_wr = 1; 2815 attr.srq_type = IB_SRQT_XRC; 2816 attr.ext.cq = devr->c0; 2817 2818 devr->s0 = ib_create_srq(devr->p0, &attr); 2819 if (IS_ERR(devr->s0)) { 2820 ret = PTR_ERR(devr->s0); 2821 goto err_create; 2822 } 2823 2824 memset(&attr, 0, sizeof(attr)); 2825 attr.attr.max_sge = 1; 2826 attr.attr.max_wr = 1; 2827 attr.srq_type = IB_SRQT_BASIC; 2828 2829 devr->s1 = ib_create_srq(devr->p0, &attr); 2830 if (IS_ERR(devr->s1)) { 2831 ret = PTR_ERR(devr->s1); 2832 goto error6; 2833 } 2834 2835 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2836 INIT_WORK(&devr->ports[port].pkey_change_work, 2837 pkey_change_handler); 2838 2839 return 0; 2840 2841 error6: 2842 ib_destroy_srq(devr->s0); 2843 err_create: 2844 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2845 error3: 2846 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2847 error2: 2848 ib_destroy_cq(devr->c0); 2849 error1: 2850 ib_dealloc_pd(devr->p0); 2851 return ret; 2852 } 2853 2854 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2855 { 2856 struct mlx5_ib_resources *devr = &dev->devr; 2857 int port; 2858 2859 /* 2860 * Make sure no change P_Key work items are still executing. 2861 * 2862 * At this stage, the mlx5_ib_event should be unregistered 2863 * and it ensures that no new works are added. 2864 */ 2865 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2866 cancel_work_sync(&devr->ports[port].pkey_change_work); 2867 2868 ib_destroy_srq(devr->s1); 2869 ib_destroy_srq(devr->s0); 2870 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2871 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2872 ib_destroy_cq(devr->c0); 2873 ib_dealloc_pd(devr->p0); 2874 } 2875 2876 static u32 get_core_cap_flags(struct ib_device *ibdev, 2877 struct mlx5_hca_vport_context *rep) 2878 { 2879 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2880 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2881 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2882 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2883 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2884 u32 ret = 0; 2885 2886 if (rep->grh_required) 2887 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2888 2889 if (ll == IB_LINK_LAYER_INFINIBAND) 2890 return ret | RDMA_CORE_PORT_IBA_IB; 2891 2892 if (raw_support) 2893 ret |= RDMA_CORE_PORT_RAW_PACKET; 2894 2895 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2896 return ret; 2897 2898 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2899 return ret; 2900 2901 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2902 ret |= RDMA_CORE_PORT_IBA_ROCE; 2903 2904 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2905 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2906 2907 return ret; 2908 } 2909 2910 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2911 struct ib_port_immutable *immutable) 2912 { 2913 struct ib_port_attr attr; 2914 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2915 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2916 struct mlx5_hca_vport_context rep = {0}; 2917 int err; 2918 2919 err = ib_query_port(ibdev, port_num, &attr); 2920 if (err) 2921 return err; 2922 2923 if (ll == IB_LINK_LAYER_INFINIBAND) { 2924 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2925 &rep); 2926 if (err) 2927 return err; 2928 } 2929 2930 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2931 immutable->gid_tbl_len = attr.gid_tbl_len; 2932 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2933 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2934 2935 return 0; 2936 } 2937 2938 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2939 struct ib_port_immutable *immutable) 2940 { 2941 struct ib_port_attr attr; 2942 int err; 2943 2944 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2945 2946 err = ib_query_port(ibdev, port_num, &attr); 2947 if (err) 2948 return err; 2949 2950 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2951 immutable->gid_tbl_len = attr.gid_tbl_len; 2952 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2953 2954 return 0; 2955 } 2956 2957 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2958 { 2959 struct mlx5_ib_dev *dev = 2960 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2961 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2962 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2963 fw_rev_sub(dev->mdev)); 2964 } 2965 2966 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2967 { 2968 struct mlx5_core_dev *mdev = dev->mdev; 2969 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2970 MLX5_FLOW_NAMESPACE_LAG); 2971 struct mlx5_flow_table *ft; 2972 int err; 2973 2974 if (!ns || !mlx5_lag_is_active(mdev)) 2975 return 0; 2976 2977 err = mlx5_cmd_create_vport_lag(mdev); 2978 if (err) 2979 return err; 2980 2981 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 2982 if (IS_ERR(ft)) { 2983 err = PTR_ERR(ft); 2984 goto err_destroy_vport_lag; 2985 } 2986 2987 dev->flow_db->lag_demux_ft = ft; 2988 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 2989 dev->lag_active = true; 2990 return 0; 2991 2992 err_destroy_vport_lag: 2993 mlx5_cmd_destroy_vport_lag(mdev); 2994 return err; 2995 } 2996 2997 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 2998 { 2999 struct mlx5_core_dev *mdev = dev->mdev; 3000 3001 if (dev->lag_active) { 3002 dev->lag_active = false; 3003 3004 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3005 dev->flow_db->lag_demux_ft = NULL; 3006 3007 mlx5_cmd_destroy_vport_lag(mdev); 3008 } 3009 } 3010 3011 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3012 struct net_device *netdev) 3013 { 3014 int err; 3015 3016 if (roce->tracking_netdev) 3017 return; 3018 roce->tracking_netdev = netdev; 3019 roce->nb.notifier_call = mlx5_netdev_event; 3020 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3021 WARN_ON(err); 3022 } 3023 3024 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3025 { 3026 if (!roce->tracking_netdev) 3027 return; 3028 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3029 &roce->nn); 3030 roce->tracking_netdev = NULL; 3031 } 3032 3033 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3034 unsigned long event, void *data) 3035 { 3036 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3037 struct net_device *netdev = data; 3038 3039 switch (event) { 3040 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3041 if (netdev) 3042 mlx5_netdev_notifier_register(roce, netdev); 3043 else 3044 mlx5_netdev_notifier_unregister(roce); 3045 break; 3046 default: 3047 return NOTIFY_DONE; 3048 } 3049 3050 return NOTIFY_OK; 3051 } 3052 3053 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3054 { 3055 struct mlx5_roce *roce = &dev->port[port_num].roce; 3056 3057 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3058 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3059 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3060 } 3061 3062 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3063 { 3064 struct mlx5_roce *roce = &dev->port[port_num].roce; 3065 3066 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3067 mlx5_netdev_notifier_unregister(roce); 3068 } 3069 3070 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3071 { 3072 int err; 3073 3074 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3075 err = mlx5_nic_vport_enable_roce(dev->mdev); 3076 if (err) 3077 return err; 3078 } 3079 3080 err = mlx5_eth_lag_init(dev); 3081 if (err) 3082 goto err_disable_roce; 3083 3084 return 0; 3085 3086 err_disable_roce: 3087 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3088 mlx5_nic_vport_disable_roce(dev->mdev); 3089 3090 return err; 3091 } 3092 3093 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3094 { 3095 mlx5_eth_lag_cleanup(dev); 3096 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3097 mlx5_nic_vport_disable_roce(dev->mdev); 3098 } 3099 3100 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3101 enum rdma_netdev_t type, 3102 struct rdma_netdev_alloc_params *params) 3103 { 3104 if (type != RDMA_NETDEV_IPOIB) 3105 return -EOPNOTSUPP; 3106 3107 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3108 } 3109 3110 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3111 size_t count, loff_t *pos) 3112 { 3113 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3114 char lbuf[20]; 3115 int len; 3116 3117 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3118 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3119 } 3120 3121 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3122 size_t count, loff_t *pos) 3123 { 3124 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3125 u32 timeout; 3126 u32 var; 3127 3128 if (kstrtouint_from_user(buf, count, 0, &var)) 3129 return -EFAULT; 3130 3131 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3132 1000); 3133 if (timeout != var) 3134 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3135 timeout); 3136 3137 delay_drop->timeout = timeout; 3138 3139 return count; 3140 } 3141 3142 static const struct file_operations fops_delay_drop_timeout = { 3143 .owner = THIS_MODULE, 3144 .open = simple_open, 3145 .write = delay_drop_timeout_write, 3146 .read = delay_drop_timeout_read, 3147 }; 3148 3149 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3150 struct mlx5_ib_multiport_info *mpi) 3151 { 3152 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3153 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3154 int comps; 3155 int err; 3156 int i; 3157 3158 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3159 3160 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3161 3162 spin_lock(&port->mp.mpi_lock); 3163 if (!mpi->ibdev) { 3164 spin_unlock(&port->mp.mpi_lock); 3165 return; 3166 } 3167 3168 mpi->ibdev = NULL; 3169 3170 spin_unlock(&port->mp.mpi_lock); 3171 if (mpi->mdev_events.notifier_call) 3172 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3173 mpi->mdev_events.notifier_call = NULL; 3174 mlx5_mdev_netdev_untrack(ibdev, port_num); 3175 spin_lock(&port->mp.mpi_lock); 3176 3177 comps = mpi->mdev_refcnt; 3178 if (comps) { 3179 mpi->unaffiliate = true; 3180 init_completion(&mpi->unref_comp); 3181 spin_unlock(&port->mp.mpi_lock); 3182 3183 for (i = 0; i < comps; i++) 3184 wait_for_completion(&mpi->unref_comp); 3185 3186 spin_lock(&port->mp.mpi_lock); 3187 mpi->unaffiliate = false; 3188 } 3189 3190 port->mp.mpi = NULL; 3191 3192 spin_unlock(&port->mp.mpi_lock); 3193 3194 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3195 3196 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3197 /* Log an error, still needed to cleanup the pointers and add 3198 * it back to the list. 3199 */ 3200 if (err) 3201 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3202 port_num + 1); 3203 3204 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3205 } 3206 3207 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3208 struct mlx5_ib_multiport_info *mpi) 3209 { 3210 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3211 int err; 3212 3213 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3214 3215 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3216 if (ibdev->port[port_num].mp.mpi) { 3217 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3218 port_num + 1); 3219 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3220 return false; 3221 } 3222 3223 ibdev->port[port_num].mp.mpi = mpi; 3224 mpi->ibdev = ibdev; 3225 mpi->mdev_events.notifier_call = NULL; 3226 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3227 3228 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3229 if (err) 3230 goto unbind; 3231 3232 mlx5_mdev_netdev_track(ibdev, port_num); 3233 3234 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3235 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3236 3237 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3238 3239 return true; 3240 3241 unbind: 3242 mlx5_ib_unbind_slave_port(ibdev, mpi); 3243 return false; 3244 } 3245 3246 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3247 { 3248 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3249 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3250 port_num + 1); 3251 struct mlx5_ib_multiport_info *mpi; 3252 int err; 3253 u32 i; 3254 3255 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3256 return 0; 3257 3258 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3259 &dev->sys_image_guid); 3260 if (err) 3261 return err; 3262 3263 err = mlx5_nic_vport_enable_roce(dev->mdev); 3264 if (err) 3265 return err; 3266 3267 mutex_lock(&mlx5_ib_multiport_mutex); 3268 for (i = 0; i < dev->num_ports; i++) { 3269 bool bound = false; 3270 3271 /* build a stub multiport info struct for the native port. */ 3272 if (i == port_num) { 3273 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3274 if (!mpi) { 3275 mutex_unlock(&mlx5_ib_multiport_mutex); 3276 mlx5_nic_vport_disable_roce(dev->mdev); 3277 return -ENOMEM; 3278 } 3279 3280 mpi->is_master = true; 3281 mpi->mdev = dev->mdev; 3282 mpi->sys_image_guid = dev->sys_image_guid; 3283 dev->port[i].mp.mpi = mpi; 3284 mpi->ibdev = dev; 3285 mpi = NULL; 3286 continue; 3287 } 3288 3289 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3290 list) { 3291 if (dev->sys_image_guid == mpi->sys_image_guid && 3292 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3293 bound = mlx5_ib_bind_slave_port(dev, mpi); 3294 } 3295 3296 if (bound) { 3297 dev_dbg(mpi->mdev->device, 3298 "removing port from unaffiliated list.\n"); 3299 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3300 list_del(&mpi->list); 3301 break; 3302 } 3303 } 3304 if (!bound) 3305 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3306 i + 1); 3307 } 3308 3309 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3310 mutex_unlock(&mlx5_ib_multiport_mutex); 3311 return err; 3312 } 3313 3314 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3315 { 3316 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3317 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3318 port_num + 1); 3319 u32 i; 3320 3321 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3322 return; 3323 3324 mutex_lock(&mlx5_ib_multiport_mutex); 3325 for (i = 0; i < dev->num_ports; i++) { 3326 if (dev->port[i].mp.mpi) { 3327 /* Destroy the native port stub */ 3328 if (i == port_num) { 3329 kfree(dev->port[i].mp.mpi); 3330 dev->port[i].mp.mpi = NULL; 3331 } else { 3332 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3333 i + 1); 3334 list_add_tail(&dev->port[i].mp.mpi->list, 3335 &mlx5_ib_unaffiliated_port_list); 3336 mlx5_ib_unbind_slave_port(dev, 3337 dev->port[i].mp.mpi); 3338 } 3339 } 3340 } 3341 3342 mlx5_ib_dbg(dev, "removing from devlist\n"); 3343 list_del(&dev->ib_dev_list); 3344 mutex_unlock(&mlx5_ib_multiport_mutex); 3345 3346 mlx5_nic_vport_disable_roce(dev->mdev); 3347 } 3348 3349 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3350 enum rdma_remove_reason why, 3351 struct uverbs_attr_bundle *attrs) 3352 { 3353 struct mlx5_user_mmap_entry *obj = uobject->object; 3354 3355 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3356 return 0; 3357 } 3358 3359 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3360 struct mlx5_user_mmap_entry *entry, 3361 size_t length) 3362 { 3363 return rdma_user_mmap_entry_insert_range( 3364 &c->ibucontext, &entry->rdma_entry, length, 3365 (MLX5_IB_MMAP_OFFSET_START << 16), 3366 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3367 } 3368 3369 static struct mlx5_user_mmap_entry * 3370 alloc_var_entry(struct mlx5_ib_ucontext *c) 3371 { 3372 struct mlx5_user_mmap_entry *entry; 3373 struct mlx5_var_table *var_table; 3374 u32 page_idx; 3375 int err; 3376 3377 var_table = &to_mdev(c->ibucontext.device)->var_table; 3378 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3379 if (!entry) 3380 return ERR_PTR(-ENOMEM); 3381 3382 mutex_lock(&var_table->bitmap_lock); 3383 page_idx = find_first_zero_bit(var_table->bitmap, 3384 var_table->num_var_hw_entries); 3385 if (page_idx >= var_table->num_var_hw_entries) { 3386 err = -ENOSPC; 3387 mutex_unlock(&var_table->bitmap_lock); 3388 goto end; 3389 } 3390 3391 set_bit(page_idx, var_table->bitmap); 3392 mutex_unlock(&var_table->bitmap_lock); 3393 3394 entry->address = var_table->hw_start_addr + 3395 (page_idx * var_table->stride_size); 3396 entry->page_idx = page_idx; 3397 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3398 3399 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3400 var_table->stride_size); 3401 if (err) 3402 goto err_insert; 3403 3404 return entry; 3405 3406 err_insert: 3407 mutex_lock(&var_table->bitmap_lock); 3408 clear_bit(page_idx, var_table->bitmap); 3409 mutex_unlock(&var_table->bitmap_lock); 3410 end: 3411 kfree(entry); 3412 return ERR_PTR(err); 3413 } 3414 3415 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3416 struct uverbs_attr_bundle *attrs) 3417 { 3418 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3419 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3420 struct mlx5_ib_ucontext *c; 3421 struct mlx5_user_mmap_entry *entry; 3422 u64 mmap_offset; 3423 u32 length; 3424 int err; 3425 3426 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3427 if (IS_ERR(c)) 3428 return PTR_ERR(c); 3429 3430 entry = alloc_var_entry(c); 3431 if (IS_ERR(entry)) 3432 return PTR_ERR(entry); 3433 3434 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3435 length = entry->rdma_entry.npages * PAGE_SIZE; 3436 uobj->object = entry; 3437 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3438 3439 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3440 &mmap_offset, sizeof(mmap_offset)); 3441 if (err) 3442 return err; 3443 3444 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3445 &entry->page_idx, sizeof(entry->page_idx)); 3446 if (err) 3447 return err; 3448 3449 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3450 &length, sizeof(length)); 3451 return err; 3452 } 3453 3454 DECLARE_UVERBS_NAMED_METHOD( 3455 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3456 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3457 MLX5_IB_OBJECT_VAR, 3458 UVERBS_ACCESS_NEW, 3459 UA_MANDATORY), 3460 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3461 UVERBS_ATTR_TYPE(u32), 3462 UA_MANDATORY), 3463 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3464 UVERBS_ATTR_TYPE(u32), 3465 UA_MANDATORY), 3466 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3467 UVERBS_ATTR_TYPE(u64), 3468 UA_MANDATORY)); 3469 3470 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3471 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3472 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3473 MLX5_IB_OBJECT_VAR, 3474 UVERBS_ACCESS_DESTROY, 3475 UA_MANDATORY)); 3476 3477 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3478 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3479 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3480 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3481 3482 static bool var_is_supported(struct ib_device *device) 3483 { 3484 struct mlx5_ib_dev *dev = to_mdev(device); 3485 3486 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3487 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3488 } 3489 3490 static struct mlx5_user_mmap_entry * 3491 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3492 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3493 { 3494 struct mlx5_user_mmap_entry *entry; 3495 struct mlx5_ib_dev *dev; 3496 u32 uar_index; 3497 int err; 3498 3499 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3500 if (!entry) 3501 return ERR_PTR(-ENOMEM); 3502 3503 dev = to_mdev(c->ibucontext.device); 3504 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3505 if (err) 3506 goto end; 3507 3508 entry->page_idx = uar_index; 3509 entry->address = uar_index2paddress(dev, uar_index); 3510 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3511 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3512 else 3513 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3514 3515 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3516 if (err) 3517 goto err_insert; 3518 3519 return entry; 3520 3521 err_insert: 3522 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3523 end: 3524 kfree(entry); 3525 return ERR_PTR(err); 3526 } 3527 3528 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3529 struct uverbs_attr_bundle *attrs) 3530 { 3531 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3532 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3533 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3534 struct mlx5_ib_ucontext *c; 3535 struct mlx5_user_mmap_entry *entry; 3536 u64 mmap_offset; 3537 u32 length; 3538 int err; 3539 3540 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3541 if (IS_ERR(c)) 3542 return PTR_ERR(c); 3543 3544 err = uverbs_get_const(&alloc_type, attrs, 3545 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3546 if (err) 3547 return err; 3548 3549 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3550 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3551 return -EOPNOTSUPP; 3552 3553 if (!to_mdev(c->ibucontext.device)->wc_support && 3554 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3555 return -EOPNOTSUPP; 3556 3557 entry = alloc_uar_entry(c, alloc_type); 3558 if (IS_ERR(entry)) 3559 return PTR_ERR(entry); 3560 3561 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3562 length = entry->rdma_entry.npages * PAGE_SIZE; 3563 uobj->object = entry; 3564 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3565 3566 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3567 &mmap_offset, sizeof(mmap_offset)); 3568 if (err) 3569 return err; 3570 3571 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3572 &entry->page_idx, sizeof(entry->page_idx)); 3573 if (err) 3574 return err; 3575 3576 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3577 &length, sizeof(length)); 3578 return err; 3579 } 3580 3581 DECLARE_UVERBS_NAMED_METHOD( 3582 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3583 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3584 MLX5_IB_OBJECT_UAR, 3585 UVERBS_ACCESS_NEW, 3586 UA_MANDATORY), 3587 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3588 enum mlx5_ib_uapi_uar_alloc_type, 3589 UA_MANDATORY), 3590 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3591 UVERBS_ATTR_TYPE(u32), 3592 UA_MANDATORY), 3593 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3594 UVERBS_ATTR_TYPE(u32), 3595 UA_MANDATORY), 3596 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3597 UVERBS_ATTR_TYPE(u64), 3598 UA_MANDATORY)); 3599 3600 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3601 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3602 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3603 MLX5_IB_OBJECT_UAR, 3604 UVERBS_ACCESS_DESTROY, 3605 UA_MANDATORY)); 3606 3607 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3608 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3609 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3610 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3611 3612 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3613 mlx5_ib_query_context, 3614 UVERBS_OBJECT_DEVICE, 3615 UVERBS_METHOD_QUERY_CONTEXT, 3616 UVERBS_ATTR_PTR_OUT( 3617 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3618 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3619 dump_fill_mkey), 3620 UA_MANDATORY)); 3621 3622 static const struct uapi_definition mlx5_ib_defs[] = { 3623 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3624 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3625 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3626 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3627 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3628 3629 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3630 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3631 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3632 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3633 {} 3634 }; 3635 3636 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3637 { 3638 mlx5_ib_cleanup_multiport_master(dev); 3639 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3640 mutex_destroy(&dev->cap_mask_mutex); 3641 WARN_ON(!xa_empty(&dev->sig_mrs)); 3642 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3643 } 3644 3645 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3646 { 3647 struct mlx5_core_dev *mdev = dev->mdev; 3648 int err; 3649 int i; 3650 3651 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3652 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3653 dev->ib_dev.phys_port_cnt = dev->num_ports; 3654 dev->ib_dev.dev.parent = mdev->device; 3655 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3656 3657 for (i = 0; i < dev->num_ports; i++) { 3658 spin_lock_init(&dev->port[i].mp.mpi_lock); 3659 rwlock_init(&dev->port[i].roce.netdev_lock); 3660 dev->port[i].roce.dev = dev; 3661 dev->port[i].roce.native_port_num = i + 1; 3662 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3663 } 3664 3665 err = mlx5r_cmd_query_special_mkeys(dev); 3666 if (err) 3667 return err; 3668 3669 err = mlx5_ib_init_multiport_master(dev); 3670 if (err) 3671 return err; 3672 3673 err = set_has_smi_cap(dev); 3674 if (err) 3675 goto err_mp; 3676 3677 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3678 if (err) 3679 goto err_mp; 3680 3681 if (mlx5_use_mad_ifc(dev)) 3682 get_ext_port_caps(dev); 3683 3684 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3685 3686 mutex_init(&dev->cap_mask_mutex); 3687 INIT_LIST_HEAD(&dev->qp_list); 3688 spin_lock_init(&dev->reset_flow_resource_lock); 3689 xa_init(&dev->odp_mkeys); 3690 xa_init(&dev->sig_mrs); 3691 atomic_set(&dev->mkey_var, 0); 3692 3693 spin_lock_init(&dev->dm.lock); 3694 dev->dm.dev = mdev; 3695 return 0; 3696 3697 err_mp: 3698 mlx5_ib_cleanup_multiport_master(dev); 3699 return err; 3700 } 3701 3702 static int mlx5_ib_enable_driver(struct ib_device *dev) 3703 { 3704 struct mlx5_ib_dev *mdev = to_mdev(dev); 3705 int ret; 3706 3707 ret = mlx5_ib_test_wc(mdev); 3708 mlx5_ib_dbg(mdev, "Write-Combining %s", 3709 mdev->wc_support ? "supported" : "not supported"); 3710 3711 return ret; 3712 } 3713 3714 static const struct ib_device_ops mlx5_ib_dev_ops = { 3715 .owner = THIS_MODULE, 3716 .driver_id = RDMA_DRIVER_MLX5, 3717 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3718 3719 .add_gid = mlx5_ib_add_gid, 3720 .alloc_mr = mlx5_ib_alloc_mr, 3721 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3722 .alloc_pd = mlx5_ib_alloc_pd, 3723 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3724 .attach_mcast = mlx5_ib_mcg_attach, 3725 .check_mr_status = mlx5_ib_check_mr_status, 3726 .create_ah = mlx5_ib_create_ah, 3727 .create_cq = mlx5_ib_create_cq, 3728 .create_qp = mlx5_ib_create_qp, 3729 .create_srq = mlx5_ib_create_srq, 3730 .create_user_ah = mlx5_ib_create_ah, 3731 .dealloc_pd = mlx5_ib_dealloc_pd, 3732 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3733 .del_gid = mlx5_ib_del_gid, 3734 .dereg_mr = mlx5_ib_dereg_mr, 3735 .destroy_ah = mlx5_ib_destroy_ah, 3736 .destroy_cq = mlx5_ib_destroy_cq, 3737 .destroy_qp = mlx5_ib_destroy_qp, 3738 .destroy_srq = mlx5_ib_destroy_srq, 3739 .detach_mcast = mlx5_ib_mcg_detach, 3740 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3741 .drain_rq = mlx5_ib_drain_rq, 3742 .drain_sq = mlx5_ib_drain_sq, 3743 .device_group = &mlx5_attr_group, 3744 .enable_driver = mlx5_ib_enable_driver, 3745 .get_dev_fw_str = get_dev_fw_str, 3746 .get_dma_mr = mlx5_ib_get_dma_mr, 3747 .get_link_layer = mlx5_ib_port_link_layer, 3748 .map_mr_sg = mlx5_ib_map_mr_sg, 3749 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3750 .mmap = mlx5_ib_mmap, 3751 .mmap_free = mlx5_ib_mmap_free, 3752 .modify_cq = mlx5_ib_modify_cq, 3753 .modify_device = mlx5_ib_modify_device, 3754 .modify_port = mlx5_ib_modify_port, 3755 .modify_qp = mlx5_ib_modify_qp, 3756 .modify_srq = mlx5_ib_modify_srq, 3757 .poll_cq = mlx5_ib_poll_cq, 3758 .post_recv = mlx5_ib_post_recv_nodrain, 3759 .post_send = mlx5_ib_post_send_nodrain, 3760 .post_srq_recv = mlx5_ib_post_srq_recv, 3761 .process_mad = mlx5_ib_process_mad, 3762 .query_ah = mlx5_ib_query_ah, 3763 .query_device = mlx5_ib_query_device, 3764 .query_gid = mlx5_ib_query_gid, 3765 .query_pkey = mlx5_ib_query_pkey, 3766 .query_qp = mlx5_ib_query_qp, 3767 .query_srq = mlx5_ib_query_srq, 3768 .query_ucontext = mlx5_ib_query_ucontext, 3769 .reg_user_mr = mlx5_ib_reg_user_mr, 3770 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3771 .req_notify_cq = mlx5_ib_arm_cq, 3772 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3773 .resize_cq = mlx5_ib_resize_cq, 3774 3775 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3776 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3777 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3778 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3779 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3780 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3781 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3782 }; 3783 3784 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3785 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3786 }; 3787 3788 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3789 .get_vf_config = mlx5_ib_get_vf_config, 3790 .get_vf_guid = mlx5_ib_get_vf_guid, 3791 .get_vf_stats = mlx5_ib_get_vf_stats, 3792 .set_vf_guid = mlx5_ib_set_vf_guid, 3793 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3794 }; 3795 3796 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3797 .alloc_mw = mlx5_ib_alloc_mw, 3798 .dealloc_mw = mlx5_ib_dealloc_mw, 3799 3800 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3801 }; 3802 3803 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3804 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3805 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3806 3807 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3808 }; 3809 3810 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3811 { 3812 struct mlx5_core_dev *mdev = dev->mdev; 3813 struct mlx5_var_table *var_table = &dev->var_table; 3814 u8 log_doorbell_bar_size; 3815 u8 log_doorbell_stride; 3816 u64 bar_size; 3817 3818 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3819 log_doorbell_bar_size); 3820 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3821 log_doorbell_stride); 3822 var_table->hw_start_addr = dev->mdev->bar_addr + 3823 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3824 doorbell_bar_offset); 3825 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3826 var_table->stride_size = 1ULL << log_doorbell_stride; 3827 var_table->num_var_hw_entries = div_u64(bar_size, 3828 var_table->stride_size); 3829 mutex_init(&var_table->bitmap_lock); 3830 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3831 GFP_KERNEL); 3832 return (var_table->bitmap) ? 0 : -ENOMEM; 3833 } 3834 3835 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3836 { 3837 bitmap_free(dev->var_table.bitmap); 3838 } 3839 3840 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3841 { 3842 struct mlx5_core_dev *mdev = dev->mdev; 3843 int err; 3844 3845 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3846 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3847 ib_set_device_ops(&dev->ib_dev, 3848 &mlx5_ib_dev_ipoib_enhanced_ops); 3849 3850 if (mlx5_core_is_pf(mdev)) 3851 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3852 3853 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3854 3855 if (MLX5_CAP_GEN(mdev, imaicl)) 3856 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3857 3858 if (MLX5_CAP_GEN(mdev, xrc)) 3859 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3860 3861 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3862 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3863 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3864 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3865 3866 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3867 3868 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3869 dev->ib_dev.driver_def = mlx5_ib_defs; 3870 3871 err = init_node_data(dev); 3872 if (err) 3873 return err; 3874 3875 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3876 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3877 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3878 mutex_init(&dev->lb.mutex); 3879 3880 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3881 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3882 err = mlx5_ib_init_var_table(dev); 3883 if (err) 3884 return err; 3885 } 3886 3887 dev->ib_dev.use_cq_dim = true; 3888 3889 return 0; 3890 } 3891 3892 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3893 .get_port_immutable = mlx5_port_immutable, 3894 .query_port = mlx5_ib_query_port, 3895 }; 3896 3897 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3898 { 3899 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3900 return 0; 3901 } 3902 3903 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3904 .get_port_immutable = mlx5_port_rep_immutable, 3905 .query_port = mlx5_ib_rep_query_port, 3906 .query_pkey = mlx5_ib_rep_query_pkey, 3907 }; 3908 3909 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3910 { 3911 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3912 return 0; 3913 } 3914 3915 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3916 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3917 .create_wq = mlx5_ib_create_wq, 3918 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3919 .destroy_wq = mlx5_ib_destroy_wq, 3920 .get_netdev = mlx5_ib_get_netdev, 3921 .modify_wq = mlx5_ib_modify_wq, 3922 3923 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3924 ib_rwq_ind_tbl), 3925 }; 3926 3927 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3928 { 3929 struct mlx5_core_dev *mdev = dev->mdev; 3930 enum rdma_link_layer ll; 3931 int port_type_cap; 3932 u32 port_num = 0; 3933 int err; 3934 3935 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3936 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3937 3938 if (ll == IB_LINK_LAYER_ETHERNET) { 3939 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3940 3941 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3942 3943 /* Register only for native ports */ 3944 mlx5_mdev_netdev_track(dev, port_num); 3945 3946 err = mlx5_enable_eth(dev); 3947 if (err) 3948 goto cleanup; 3949 } 3950 3951 return 0; 3952 cleanup: 3953 mlx5_mdev_netdev_untrack(dev, port_num); 3954 return err; 3955 } 3956 3957 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3958 { 3959 struct mlx5_core_dev *mdev = dev->mdev; 3960 enum rdma_link_layer ll; 3961 int port_type_cap; 3962 u32 port_num; 3963 3964 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3965 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3966 3967 if (ll == IB_LINK_LAYER_ETHERNET) { 3968 mlx5_disable_eth(dev); 3969 3970 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3971 mlx5_mdev_netdev_untrack(dev, port_num); 3972 } 3973 } 3974 3975 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3976 { 3977 mlx5_ib_init_cong_debugfs(dev, 3978 mlx5_core_native_port_num(dev->mdev) - 1); 3979 return 0; 3980 } 3981 3982 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 3983 { 3984 mlx5_ib_cleanup_cong_debugfs(dev, 3985 mlx5_core_native_port_num(dev->mdev) - 1); 3986 } 3987 3988 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 3989 { 3990 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3991 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 3992 } 3993 3994 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 3995 { 3996 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3997 } 3998 3999 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4000 { 4001 int err; 4002 4003 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4004 if (err) 4005 return err; 4006 4007 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4008 if (err) 4009 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4010 4011 return err; 4012 } 4013 4014 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4015 { 4016 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4017 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4018 } 4019 4020 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4021 { 4022 const char *name; 4023 4024 if (!mlx5_lag_is_active(dev->mdev)) 4025 name = "mlx5_%d"; 4026 else 4027 name = "mlx5_bond_%d"; 4028 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4029 } 4030 4031 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4032 { 4033 mlx5_mkey_cache_cleanup(dev); 4034 mlx5r_umr_resource_cleanup(dev); 4035 } 4036 4037 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4038 { 4039 ib_unregister_device(&dev->ib_dev); 4040 } 4041 4042 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4043 { 4044 int ret; 4045 4046 ret = mlx5r_umr_resource_init(dev); 4047 if (ret) 4048 return ret; 4049 4050 ret = mlx5_mkey_cache_init(dev); 4051 if (ret) { 4052 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4053 mlx5r_umr_resource_cleanup(dev); 4054 } 4055 return ret; 4056 } 4057 4058 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4059 { 4060 struct dentry *root; 4061 4062 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4063 return 0; 4064 4065 mutex_init(&dev->delay_drop.lock); 4066 dev->delay_drop.dev = dev; 4067 dev->delay_drop.activate = false; 4068 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4069 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4070 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4071 atomic_set(&dev->delay_drop.events_cnt, 0); 4072 4073 if (!mlx5_debugfs_root) 4074 return 0; 4075 4076 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4077 dev->delay_drop.dir_debugfs = root; 4078 4079 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4080 &dev->delay_drop.events_cnt); 4081 debugfs_create_atomic_t("num_rqs", 0400, root, 4082 &dev->delay_drop.rqs_cnt); 4083 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4084 &fops_delay_drop_timeout); 4085 return 0; 4086 } 4087 4088 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4089 { 4090 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4091 return; 4092 4093 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4094 if (!dev->delay_drop.dir_debugfs) 4095 return; 4096 4097 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4098 dev->delay_drop.dir_debugfs = NULL; 4099 } 4100 4101 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4102 { 4103 dev->mdev_events.notifier_call = mlx5_ib_event; 4104 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4105 return 0; 4106 } 4107 4108 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4109 { 4110 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4111 } 4112 4113 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4114 const struct mlx5_ib_profile *profile, 4115 int stage) 4116 { 4117 dev->ib_active = false; 4118 4119 /* Number of stages to cleanup */ 4120 while (stage) { 4121 stage--; 4122 if (profile->stage[stage].cleanup) 4123 profile->stage[stage].cleanup(dev); 4124 } 4125 4126 kfree(dev->port); 4127 ib_dealloc_device(&dev->ib_dev); 4128 } 4129 4130 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4131 const struct mlx5_ib_profile *profile) 4132 { 4133 int err; 4134 int i; 4135 4136 dev->profile = profile; 4137 4138 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4139 if (profile->stage[i].init) { 4140 err = profile->stage[i].init(dev); 4141 if (err) 4142 goto err_out; 4143 } 4144 } 4145 4146 dev->ib_active = true; 4147 return 0; 4148 4149 err_out: 4150 /* Clean up stages which were initialized */ 4151 while (i) { 4152 i--; 4153 if (profile->stage[i].cleanup) 4154 profile->stage[i].cleanup(dev); 4155 } 4156 return -ENOMEM; 4157 } 4158 4159 static const struct mlx5_ib_profile pf_profile = { 4160 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4161 mlx5_ib_stage_init_init, 4162 mlx5_ib_stage_init_cleanup), 4163 STAGE_CREATE(MLX5_IB_STAGE_FS, 4164 mlx5_ib_fs_init, 4165 mlx5_ib_fs_cleanup), 4166 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4167 mlx5_ib_stage_caps_init, 4168 mlx5_ib_stage_caps_cleanup), 4169 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4170 mlx5_ib_stage_non_default_cb, 4171 NULL), 4172 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4173 mlx5_ib_roce_init, 4174 mlx5_ib_roce_cleanup), 4175 STAGE_CREATE(MLX5_IB_STAGE_QP, 4176 mlx5_init_qp_table, 4177 mlx5_cleanup_qp_table), 4178 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4179 mlx5_init_srq_table, 4180 mlx5_cleanup_srq_table), 4181 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4182 mlx5_ib_dev_res_init, 4183 mlx5_ib_dev_res_cleanup), 4184 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4185 mlx5_ib_stage_dev_notifier_init, 4186 mlx5_ib_stage_dev_notifier_cleanup), 4187 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4188 mlx5_ib_odp_init_one, 4189 mlx5_ib_odp_cleanup_one), 4190 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4191 mlx5_ib_counters_init, 4192 mlx5_ib_counters_cleanup), 4193 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4194 mlx5_ib_stage_cong_debugfs_init, 4195 mlx5_ib_stage_cong_debugfs_cleanup), 4196 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4197 mlx5_ib_stage_uar_init, 4198 mlx5_ib_stage_uar_cleanup), 4199 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4200 mlx5_ib_stage_bfrag_init, 4201 mlx5_ib_stage_bfrag_cleanup), 4202 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4203 NULL, 4204 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4205 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4206 mlx5_ib_devx_init, 4207 mlx5_ib_devx_cleanup), 4208 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4209 mlx5_ib_stage_ib_reg_init, 4210 mlx5_ib_stage_ib_reg_cleanup), 4211 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4212 mlx5_ib_stage_post_ib_reg_umr_init, 4213 NULL), 4214 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4215 mlx5_ib_stage_delay_drop_init, 4216 mlx5_ib_stage_delay_drop_cleanup), 4217 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4218 mlx5_ib_restrack_init, 4219 NULL), 4220 }; 4221 4222 const struct mlx5_ib_profile raw_eth_profile = { 4223 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4224 mlx5_ib_stage_init_init, 4225 mlx5_ib_stage_init_cleanup), 4226 STAGE_CREATE(MLX5_IB_STAGE_FS, 4227 mlx5_ib_fs_init, 4228 mlx5_ib_fs_cleanup), 4229 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4230 mlx5_ib_stage_caps_init, 4231 mlx5_ib_stage_caps_cleanup), 4232 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4233 mlx5_ib_stage_raw_eth_non_default_cb, 4234 NULL), 4235 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4236 mlx5_ib_roce_init, 4237 mlx5_ib_roce_cleanup), 4238 STAGE_CREATE(MLX5_IB_STAGE_QP, 4239 mlx5_init_qp_table, 4240 mlx5_cleanup_qp_table), 4241 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4242 mlx5_init_srq_table, 4243 mlx5_cleanup_srq_table), 4244 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4245 mlx5_ib_dev_res_init, 4246 mlx5_ib_dev_res_cleanup), 4247 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4248 mlx5_ib_stage_dev_notifier_init, 4249 mlx5_ib_stage_dev_notifier_cleanup), 4250 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4251 mlx5_ib_counters_init, 4252 mlx5_ib_counters_cleanup), 4253 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4254 mlx5_ib_stage_cong_debugfs_init, 4255 mlx5_ib_stage_cong_debugfs_cleanup), 4256 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4257 mlx5_ib_stage_uar_init, 4258 mlx5_ib_stage_uar_cleanup), 4259 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4260 mlx5_ib_stage_bfrag_init, 4261 mlx5_ib_stage_bfrag_cleanup), 4262 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4263 NULL, 4264 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4265 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4266 mlx5_ib_devx_init, 4267 mlx5_ib_devx_cleanup), 4268 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4269 mlx5_ib_stage_ib_reg_init, 4270 mlx5_ib_stage_ib_reg_cleanup), 4271 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4272 mlx5_ib_stage_post_ib_reg_umr_init, 4273 NULL), 4274 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4275 mlx5_ib_restrack_init, 4276 NULL), 4277 }; 4278 4279 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4280 const struct auxiliary_device_id *id) 4281 { 4282 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4283 struct mlx5_core_dev *mdev = idev->mdev; 4284 struct mlx5_ib_multiport_info *mpi; 4285 struct mlx5_ib_dev *dev; 4286 bool bound = false; 4287 int err; 4288 4289 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4290 if (!mpi) 4291 return -ENOMEM; 4292 4293 mpi->mdev = mdev; 4294 err = mlx5_query_nic_vport_system_image_guid(mdev, 4295 &mpi->sys_image_guid); 4296 if (err) { 4297 kfree(mpi); 4298 return err; 4299 } 4300 4301 mutex_lock(&mlx5_ib_multiport_mutex); 4302 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4303 if (dev->sys_image_guid == mpi->sys_image_guid) 4304 bound = mlx5_ib_bind_slave_port(dev, mpi); 4305 4306 if (bound) { 4307 rdma_roce_rescan_device(&dev->ib_dev); 4308 mpi->ibdev->ib_active = true; 4309 break; 4310 } 4311 } 4312 4313 if (!bound) { 4314 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4315 dev_dbg(mdev->device, 4316 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4317 } 4318 mutex_unlock(&mlx5_ib_multiport_mutex); 4319 4320 auxiliary_set_drvdata(adev, mpi); 4321 return 0; 4322 } 4323 4324 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4325 { 4326 struct mlx5_ib_multiport_info *mpi; 4327 4328 mpi = auxiliary_get_drvdata(adev); 4329 mutex_lock(&mlx5_ib_multiport_mutex); 4330 if (mpi->ibdev) 4331 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4332 else 4333 list_del(&mpi->list); 4334 mutex_unlock(&mlx5_ib_multiport_mutex); 4335 kfree(mpi); 4336 } 4337 4338 static int mlx5r_probe(struct auxiliary_device *adev, 4339 const struct auxiliary_device_id *id) 4340 { 4341 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4342 struct mlx5_core_dev *mdev = idev->mdev; 4343 const struct mlx5_ib_profile *profile; 4344 int port_type_cap, num_ports, ret; 4345 enum rdma_link_layer ll; 4346 struct mlx5_ib_dev *dev; 4347 4348 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4349 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4350 4351 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4352 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4353 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4354 if (!dev) 4355 return -ENOMEM; 4356 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4357 GFP_KERNEL); 4358 if (!dev->port) { 4359 ib_dealloc_device(&dev->ib_dev); 4360 return -ENOMEM; 4361 } 4362 4363 dev->mdev = mdev; 4364 dev->num_ports = num_ports; 4365 4366 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4367 profile = &raw_eth_profile; 4368 else 4369 profile = &pf_profile; 4370 4371 ret = __mlx5_ib_add(dev, profile); 4372 if (ret) { 4373 kfree(dev->port); 4374 ib_dealloc_device(&dev->ib_dev); 4375 return ret; 4376 } 4377 4378 auxiliary_set_drvdata(adev, dev); 4379 return 0; 4380 } 4381 4382 static void mlx5r_remove(struct auxiliary_device *adev) 4383 { 4384 struct mlx5_ib_dev *dev; 4385 4386 dev = auxiliary_get_drvdata(adev); 4387 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4388 } 4389 4390 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4391 { .name = MLX5_ADEV_NAME ".multiport", }, 4392 {}, 4393 }; 4394 4395 static const struct auxiliary_device_id mlx5r_id_table[] = { 4396 { .name = MLX5_ADEV_NAME ".rdma", }, 4397 {}, 4398 }; 4399 4400 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4401 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4402 4403 static struct auxiliary_driver mlx5r_mp_driver = { 4404 .name = "multiport", 4405 .probe = mlx5r_mp_probe, 4406 .remove = mlx5r_mp_remove, 4407 .id_table = mlx5r_mp_id_table, 4408 }; 4409 4410 static struct auxiliary_driver mlx5r_driver = { 4411 .name = "rdma", 4412 .probe = mlx5r_probe, 4413 .remove = mlx5r_remove, 4414 .id_table = mlx5r_id_table, 4415 }; 4416 4417 static int __init mlx5_ib_init(void) 4418 { 4419 int ret; 4420 4421 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4422 if (!xlt_emergency_page) 4423 return -ENOMEM; 4424 4425 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4426 if (!mlx5_ib_event_wq) { 4427 free_page((unsigned long)xlt_emergency_page); 4428 return -ENOMEM; 4429 } 4430 4431 ret = mlx5_ib_qp_event_init(); 4432 if (ret) 4433 goto qp_event_err; 4434 4435 mlx5_ib_odp_init(); 4436 ret = mlx5r_rep_init(); 4437 if (ret) 4438 goto rep_err; 4439 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4440 if (ret) 4441 goto mp_err; 4442 ret = auxiliary_driver_register(&mlx5r_driver); 4443 if (ret) 4444 goto drv_err; 4445 return 0; 4446 4447 drv_err: 4448 auxiliary_driver_unregister(&mlx5r_mp_driver); 4449 mp_err: 4450 mlx5r_rep_cleanup(); 4451 rep_err: 4452 mlx5_ib_qp_event_cleanup(); 4453 qp_event_err: 4454 destroy_workqueue(mlx5_ib_event_wq); 4455 free_page((unsigned long)xlt_emergency_page); 4456 return ret; 4457 } 4458 4459 static void __exit mlx5_ib_cleanup(void) 4460 { 4461 auxiliary_driver_unregister(&mlx5r_driver); 4462 auxiliary_driver_unregister(&mlx5r_mp_driver); 4463 mlx5r_rep_cleanup(); 4464 4465 mlx5_ib_qp_event_cleanup(); 4466 destroy_workqueue(mlx5_ib_event_wq); 4467 free_page((unsigned long)xlt_emergency_page); 4468 } 4469 4470 module_init(mlx5_ib_init); 4471 module_exit(mlx5_ib_cleanup); 4472