1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/delay.h> 45 #include <rdma/ib_user_verbs.h> 46 #include <rdma/ib_addr.h> 47 #include <rdma/ib_cache.h> 48 #include <linux/mlx5/port.h> 49 #include <linux/mlx5/vport.h> 50 #include <linux/list.h> 51 #include <rdma/ib_smi.h> 52 #include <rdma/ib_umem.h> 53 #include <linux/in.h> 54 #include <linux/etherdevice.h> 55 #include <linux/mlx5/fs.h> 56 #include "mlx5_ib.h" 57 58 #define DRIVER_NAME "mlx5_ib" 59 #define DRIVER_VERSION "2.2-1" 60 #define DRIVER_RELDATE "Feb 2014" 61 62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 64 MODULE_LICENSE("Dual BSD/GPL"); 65 MODULE_VERSION(DRIVER_VERSION); 66 67 static int deprecated_prof_sel = 2; 68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 switch (event) { 109 case NETDEV_REGISTER: 110 case NETDEV_UNREGISTER: 111 write_lock(&ibdev->roce.netdev_lock); 112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 114 NULL : ndev; 115 write_unlock(&ibdev->roce.netdev_lock); 116 break; 117 118 case NETDEV_UP: 119 case NETDEV_DOWN: { 120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 121 struct net_device *upper = NULL; 122 123 if (lag_ndev) { 124 upper = netdev_master_upper_dev_get(lag_ndev); 125 dev_put(lag_ndev); 126 } 127 128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 129 && ibdev->ib_active) { 130 struct ib_event ibev = { }; 131 132 ibev.device = &ibdev->ib_dev; 133 ibev.event = (event == NETDEV_UP) ? 134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 135 ibev.element.port_num = 1; 136 ib_dispatch_event(&ibev); 137 } 138 break; 139 } 140 141 default: 142 break; 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 149 u8 port_num) 150 { 151 struct mlx5_ib_dev *ibdev = to_mdev(device); 152 struct net_device *ndev; 153 154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 155 if (ndev) 156 return ndev; 157 158 /* Ensure ndev does not disappear before we invoke dev_hold() 159 */ 160 read_lock(&ibdev->roce.netdev_lock); 161 ndev = ibdev->roce.netdev; 162 if (ndev) 163 dev_hold(ndev); 164 read_unlock(&ibdev->roce.netdev_lock); 165 166 return ndev; 167 } 168 169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 170 struct ib_port_attr *props) 171 { 172 struct mlx5_ib_dev *dev = to_mdev(device); 173 struct net_device *ndev, *upper; 174 enum ib_mtu ndev_ib_mtu; 175 u16 qkey_viol_cntr; 176 177 memset(props, 0, sizeof(*props)); 178 179 props->port_cap_flags |= IB_PORT_CM_SUP; 180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 181 182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 183 roce_address_table_size); 184 props->max_mtu = IB_MTU_4096; 185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 186 props->pkey_tbl_len = 1; 187 props->state = IB_PORT_DOWN; 188 props->phys_state = 3; 189 190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 191 props->qkey_viol_cntr = qkey_viol_cntr; 192 193 ndev = mlx5_ib_get_netdev(device, port_num); 194 if (!ndev) 195 return 0; 196 197 if (mlx5_lag_is_active(dev->mdev)) { 198 rcu_read_lock(); 199 upper = netdev_master_upper_dev_get_rcu(ndev); 200 if (upper) { 201 dev_put(ndev); 202 ndev = upper; 203 dev_hold(ndev); 204 } 205 rcu_read_unlock(); 206 } 207 208 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 209 props->state = IB_PORT_ACTIVE; 210 props->phys_state = 5; 211 } 212 213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 214 215 dev_put(ndev); 216 217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 218 219 props->active_width = IB_WIDTH_4X; /* TODO */ 220 props->active_speed = IB_SPEED_QDR; /* TODO */ 221 222 return 0; 223 } 224 225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 226 const struct ib_gid_attr *attr, 227 void *mlx5_addr) 228 { 229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 231 source_l3_address); 232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 233 source_mac_47_32); 234 235 if (!gid) 236 return; 237 238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 239 240 if (is_vlan_dev(attr->ndev)) { 241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 243 } 244 245 switch (attr->gid_type) { 246 case IB_GID_TYPE_IB: 247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 248 break; 249 case IB_GID_TYPE_ROCE_UDP_ENCAP: 250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 251 break; 252 253 default: 254 WARN_ON(true); 255 } 256 257 if (attr->gid_type != IB_GID_TYPE_IB) { 258 if (ipv6_addr_v4mapped((void *)gid)) 259 MLX5_SET_RA(mlx5_addr, roce_l3_type, 260 MLX5_ROCE_L3_TYPE_IPV4); 261 else 262 MLX5_SET_RA(mlx5_addr, roce_l3_type, 263 MLX5_ROCE_L3_TYPE_IPV6); 264 } 265 266 if ((attr->gid_type == IB_GID_TYPE_IB) || 267 !ipv6_addr_v4mapped((void *)gid)) 268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 269 else 270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 271 } 272 273 static int set_roce_addr(struct ib_device *device, u8 port_num, 274 unsigned int index, 275 const union ib_gid *gid, 276 const struct ib_gid_attr *attr) 277 { 278 struct mlx5_ib_dev *dev = to_mdev(device); 279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 283 284 if (ll != IB_LINK_LAYER_ETHERNET) 285 return -EINVAL; 286 287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 288 289 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 292 } 293 294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 295 unsigned int index, const union ib_gid *gid, 296 const struct ib_gid_attr *attr, 297 __always_unused void **context) 298 { 299 return set_roce_addr(device, port_num, index, gid, attr); 300 } 301 302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 303 unsigned int index, __always_unused void **context) 304 { 305 return set_roce_addr(device, port_num, index, NULL, NULL); 306 } 307 308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 309 int index) 310 { 311 struct ib_gid_attr attr; 312 union ib_gid gid; 313 314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 315 return 0; 316 317 if (!attr.ndev) 318 return 0; 319 320 dev_put(attr.ndev); 321 322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 323 return 0; 324 325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 326 } 327 328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 329 { 330 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 331 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 332 return 0; 333 } 334 335 enum { 336 MLX5_VPORT_ACCESS_METHOD_MAD, 337 MLX5_VPORT_ACCESS_METHOD_HCA, 338 MLX5_VPORT_ACCESS_METHOD_NIC, 339 }; 340 341 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 342 { 343 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 344 return MLX5_VPORT_ACCESS_METHOD_MAD; 345 346 if (mlx5_ib_port_link_layer(ibdev, 1) == 347 IB_LINK_LAYER_ETHERNET) 348 return MLX5_VPORT_ACCESS_METHOD_NIC; 349 350 return MLX5_VPORT_ACCESS_METHOD_HCA; 351 } 352 353 static void get_atomic_caps(struct mlx5_ib_dev *dev, 354 struct ib_device_attr *props) 355 { 356 u8 tmp; 357 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 358 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 359 u8 atomic_req_8B_endianness_mode = 360 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 361 362 /* Check if HW supports 8 bytes standard atomic operations and capable 363 * of host endianness respond 364 */ 365 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 366 if (((atomic_operations & tmp) == tmp) && 367 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 368 (atomic_req_8B_endianness_mode)) { 369 props->atomic_cap = IB_ATOMIC_HCA; 370 } else { 371 props->atomic_cap = IB_ATOMIC_NONE; 372 } 373 } 374 375 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 376 __be64 *sys_image_guid) 377 { 378 struct mlx5_ib_dev *dev = to_mdev(ibdev); 379 struct mlx5_core_dev *mdev = dev->mdev; 380 u64 tmp; 381 int err; 382 383 switch (mlx5_get_vport_access_method(ibdev)) { 384 case MLX5_VPORT_ACCESS_METHOD_MAD: 385 return mlx5_query_mad_ifc_system_image_guid(ibdev, 386 sys_image_guid); 387 388 case MLX5_VPORT_ACCESS_METHOD_HCA: 389 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 390 break; 391 392 case MLX5_VPORT_ACCESS_METHOD_NIC: 393 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 394 break; 395 396 default: 397 return -EINVAL; 398 } 399 400 if (!err) 401 *sys_image_guid = cpu_to_be64(tmp); 402 403 return err; 404 405 } 406 407 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 408 u16 *max_pkeys) 409 { 410 struct mlx5_ib_dev *dev = to_mdev(ibdev); 411 struct mlx5_core_dev *mdev = dev->mdev; 412 413 switch (mlx5_get_vport_access_method(ibdev)) { 414 case MLX5_VPORT_ACCESS_METHOD_MAD: 415 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 416 417 case MLX5_VPORT_ACCESS_METHOD_HCA: 418 case MLX5_VPORT_ACCESS_METHOD_NIC: 419 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 420 pkey_table_size)); 421 return 0; 422 423 default: 424 return -EINVAL; 425 } 426 } 427 428 static int mlx5_query_vendor_id(struct ib_device *ibdev, 429 u32 *vendor_id) 430 { 431 struct mlx5_ib_dev *dev = to_mdev(ibdev); 432 433 switch (mlx5_get_vport_access_method(ibdev)) { 434 case MLX5_VPORT_ACCESS_METHOD_MAD: 435 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 436 437 case MLX5_VPORT_ACCESS_METHOD_HCA: 438 case MLX5_VPORT_ACCESS_METHOD_NIC: 439 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 440 441 default: 442 return -EINVAL; 443 } 444 } 445 446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 447 __be64 *node_guid) 448 { 449 u64 tmp; 450 int err; 451 452 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 453 case MLX5_VPORT_ACCESS_METHOD_MAD: 454 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 455 456 case MLX5_VPORT_ACCESS_METHOD_HCA: 457 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 458 break; 459 460 case MLX5_VPORT_ACCESS_METHOD_NIC: 461 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 462 break; 463 464 default: 465 return -EINVAL; 466 } 467 468 if (!err) 469 *node_guid = cpu_to_be64(tmp); 470 471 return err; 472 } 473 474 struct mlx5_reg_node_desc { 475 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 476 }; 477 478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 479 { 480 struct mlx5_reg_node_desc in; 481 482 if (mlx5_use_mad_ifc(dev)) 483 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 484 485 memset(&in, 0, sizeof(in)); 486 487 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 488 sizeof(struct mlx5_reg_node_desc), 489 MLX5_REG_NODE_DESC, 0, 0); 490 } 491 492 static int mlx5_ib_query_device(struct ib_device *ibdev, 493 struct ib_device_attr *props, 494 struct ib_udata *uhw) 495 { 496 struct mlx5_ib_dev *dev = to_mdev(ibdev); 497 struct mlx5_core_dev *mdev = dev->mdev; 498 int err = -ENOMEM; 499 int max_sq_desc; 500 int max_rq_sg; 501 int max_sq_sg; 502 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 503 struct mlx5_ib_query_device_resp resp = {}; 504 size_t resp_len; 505 u64 max_tso; 506 507 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 508 if (uhw->outlen && uhw->outlen < resp_len) 509 return -EINVAL; 510 else 511 resp.response_length = resp_len; 512 513 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 514 return -EINVAL; 515 516 memset(props, 0, sizeof(*props)); 517 err = mlx5_query_system_image_guid(ibdev, 518 &props->sys_image_guid); 519 if (err) 520 return err; 521 522 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 523 if (err) 524 return err; 525 526 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 527 if (err) 528 return err; 529 530 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 531 (fw_rev_min(dev->mdev) << 16) | 532 fw_rev_sub(dev->mdev); 533 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 534 IB_DEVICE_PORT_ACTIVE_EVENT | 535 IB_DEVICE_SYS_IMAGE_GUID | 536 IB_DEVICE_RC_RNR_NAK_GEN; 537 538 if (MLX5_CAP_GEN(mdev, pkv)) 539 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 540 if (MLX5_CAP_GEN(mdev, qkv)) 541 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 542 if (MLX5_CAP_GEN(mdev, apm)) 543 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 544 if (MLX5_CAP_GEN(mdev, xrc)) 545 props->device_cap_flags |= IB_DEVICE_XRC; 546 if (MLX5_CAP_GEN(mdev, imaicl)) { 547 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 548 IB_DEVICE_MEM_WINDOW_TYPE_2B; 549 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 550 /* We support 'Gappy' memory registration too */ 551 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 552 } 553 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 554 if (MLX5_CAP_GEN(mdev, sho)) { 555 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 556 /* At this stage no support for signature handover */ 557 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 558 IB_PROT_T10DIF_TYPE_2 | 559 IB_PROT_T10DIF_TYPE_3; 560 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 561 IB_GUARD_T10DIF_CSUM; 562 } 563 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 564 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 565 566 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 567 if (MLX5_CAP_ETH(mdev, csum_cap)) 568 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 569 570 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 571 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 572 if (max_tso) { 573 resp.tso_caps.max_tso = 1 << max_tso; 574 resp.tso_caps.supported_qpts |= 575 1 << IB_QPT_RAW_PACKET; 576 resp.response_length += sizeof(resp.tso_caps); 577 } 578 } 579 580 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 581 resp.rss_caps.rx_hash_function = 582 MLX5_RX_HASH_FUNC_TOEPLITZ; 583 resp.rss_caps.rx_hash_fields_mask = 584 MLX5_RX_HASH_SRC_IPV4 | 585 MLX5_RX_HASH_DST_IPV4 | 586 MLX5_RX_HASH_SRC_IPV6 | 587 MLX5_RX_HASH_DST_IPV6 | 588 MLX5_RX_HASH_SRC_PORT_TCP | 589 MLX5_RX_HASH_DST_PORT_TCP | 590 MLX5_RX_HASH_SRC_PORT_UDP | 591 MLX5_RX_HASH_DST_PORT_UDP; 592 resp.response_length += sizeof(resp.rss_caps); 593 } 594 } else { 595 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 596 resp.response_length += sizeof(resp.tso_caps); 597 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 598 resp.response_length += sizeof(resp.rss_caps); 599 } 600 601 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 602 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 603 props->device_cap_flags |= IB_DEVICE_UD_TSO; 604 } 605 606 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 607 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 608 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 609 610 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 611 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 612 613 props->vendor_part_id = mdev->pdev->device; 614 props->hw_ver = mdev->pdev->revision; 615 616 props->max_mr_size = ~0ull; 617 props->page_size_cap = ~(min_page_size - 1); 618 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 619 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 620 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 621 sizeof(struct mlx5_wqe_data_seg); 622 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 623 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 624 sizeof(struct mlx5_wqe_raddr_seg)) / 625 sizeof(struct mlx5_wqe_data_seg); 626 props->max_sge = min(max_rq_sg, max_sq_sg); 627 props->max_sge_rd = MLX5_MAX_SGE_RD; 628 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 629 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 630 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 631 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 632 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 633 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 634 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 635 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 636 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 637 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 638 props->max_srq_sge = max_rq_sg - 1; 639 props->max_fast_reg_page_list_len = 640 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 641 get_atomic_caps(dev, props); 642 props->masked_atomic_cap = IB_ATOMIC_NONE; 643 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 644 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 645 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 646 props->max_mcast_grp; 647 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 648 props->max_ah = INT_MAX; 649 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 650 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 651 652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 653 if (MLX5_CAP_GEN(mdev, pg)) 654 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 655 props->odp_caps = dev->odp_caps; 656 #endif 657 658 if (MLX5_CAP_GEN(mdev, cd)) 659 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 660 661 if (!mlx5_core_is_pf(mdev)) 662 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 663 664 if (mlx5_ib_port_link_layer(ibdev, 1) == 665 IB_LINK_LAYER_ETHERNET) { 666 props->rss_caps.max_rwq_indirection_tables = 667 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 668 props->rss_caps.max_rwq_indirection_table_size = 669 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 670 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 671 props->max_wq_type_rq = 672 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 673 } 674 675 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 676 resp.cqe_comp_caps.max_num = 677 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 678 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 679 resp.cqe_comp_caps.supported_format = 680 MLX5_IB_CQE_RES_FORMAT_HASH | 681 MLX5_IB_CQE_RES_FORMAT_CSUM; 682 resp.response_length += sizeof(resp.cqe_comp_caps); 683 } 684 685 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 686 if (MLX5_CAP_QOS(mdev, packet_pacing) && 687 MLX5_CAP_GEN(mdev, qos)) { 688 resp.packet_pacing_caps.qp_rate_limit_max = 689 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 690 resp.packet_pacing_caps.qp_rate_limit_min = 691 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 692 resp.packet_pacing_caps.supported_qpts |= 693 1 << IB_QPT_RAW_PACKET; 694 } 695 resp.response_length += sizeof(resp.packet_pacing_caps); 696 } 697 698 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 699 uhw->outlen)) { 700 resp.mlx5_ib_support_multi_pkt_send_wqes = 701 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 702 resp.response_length += 703 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 704 } 705 706 if (field_avail(typeof(resp), reserved, uhw->outlen)) 707 resp.response_length += sizeof(resp.reserved); 708 709 if (uhw->outlen) { 710 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 711 712 if (err) 713 return err; 714 } 715 716 return 0; 717 } 718 719 enum mlx5_ib_width { 720 MLX5_IB_WIDTH_1X = 1 << 0, 721 MLX5_IB_WIDTH_2X = 1 << 1, 722 MLX5_IB_WIDTH_4X = 1 << 2, 723 MLX5_IB_WIDTH_8X = 1 << 3, 724 MLX5_IB_WIDTH_12X = 1 << 4 725 }; 726 727 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 728 u8 *ib_width) 729 { 730 struct mlx5_ib_dev *dev = to_mdev(ibdev); 731 int err = 0; 732 733 if (active_width & MLX5_IB_WIDTH_1X) { 734 *ib_width = IB_WIDTH_1X; 735 } else if (active_width & MLX5_IB_WIDTH_2X) { 736 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 737 (int)active_width); 738 err = -EINVAL; 739 } else if (active_width & MLX5_IB_WIDTH_4X) { 740 *ib_width = IB_WIDTH_4X; 741 } else if (active_width & MLX5_IB_WIDTH_8X) { 742 *ib_width = IB_WIDTH_8X; 743 } else if (active_width & MLX5_IB_WIDTH_12X) { 744 *ib_width = IB_WIDTH_12X; 745 } else { 746 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 747 (int)active_width); 748 err = -EINVAL; 749 } 750 751 return err; 752 } 753 754 static int mlx5_mtu_to_ib_mtu(int mtu) 755 { 756 switch (mtu) { 757 case 256: return 1; 758 case 512: return 2; 759 case 1024: return 3; 760 case 2048: return 4; 761 case 4096: return 5; 762 default: 763 pr_warn("invalid mtu\n"); 764 return -1; 765 } 766 } 767 768 enum ib_max_vl_num { 769 __IB_MAX_VL_0 = 1, 770 __IB_MAX_VL_0_1 = 2, 771 __IB_MAX_VL_0_3 = 3, 772 __IB_MAX_VL_0_7 = 4, 773 __IB_MAX_VL_0_14 = 5, 774 }; 775 776 enum mlx5_vl_hw_cap { 777 MLX5_VL_HW_0 = 1, 778 MLX5_VL_HW_0_1 = 2, 779 MLX5_VL_HW_0_2 = 3, 780 MLX5_VL_HW_0_3 = 4, 781 MLX5_VL_HW_0_4 = 5, 782 MLX5_VL_HW_0_5 = 6, 783 MLX5_VL_HW_0_6 = 7, 784 MLX5_VL_HW_0_7 = 8, 785 MLX5_VL_HW_0_14 = 15 786 }; 787 788 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 789 u8 *max_vl_num) 790 { 791 switch (vl_hw_cap) { 792 case MLX5_VL_HW_0: 793 *max_vl_num = __IB_MAX_VL_0; 794 break; 795 case MLX5_VL_HW_0_1: 796 *max_vl_num = __IB_MAX_VL_0_1; 797 break; 798 case MLX5_VL_HW_0_3: 799 *max_vl_num = __IB_MAX_VL_0_3; 800 break; 801 case MLX5_VL_HW_0_7: 802 *max_vl_num = __IB_MAX_VL_0_7; 803 break; 804 case MLX5_VL_HW_0_14: 805 *max_vl_num = __IB_MAX_VL_0_14; 806 break; 807 808 default: 809 return -EINVAL; 810 } 811 812 return 0; 813 } 814 815 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 816 struct ib_port_attr *props) 817 { 818 struct mlx5_ib_dev *dev = to_mdev(ibdev); 819 struct mlx5_core_dev *mdev = dev->mdev; 820 struct mlx5_hca_vport_context *rep; 821 u16 max_mtu; 822 u16 oper_mtu; 823 int err; 824 u8 ib_link_width_oper; 825 u8 vl_hw_cap; 826 827 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 828 if (!rep) { 829 err = -ENOMEM; 830 goto out; 831 } 832 833 memset(props, 0, sizeof(*props)); 834 835 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 836 if (err) 837 goto out; 838 839 props->lid = rep->lid; 840 props->lmc = rep->lmc; 841 props->sm_lid = rep->sm_lid; 842 props->sm_sl = rep->sm_sl; 843 props->state = rep->vport_state; 844 props->phys_state = rep->port_physical_state; 845 props->port_cap_flags = rep->cap_mask1; 846 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 847 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 848 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 849 props->bad_pkey_cntr = rep->pkey_violation_counter; 850 props->qkey_viol_cntr = rep->qkey_violation_counter; 851 props->subnet_timeout = rep->subnet_timeout; 852 props->init_type_reply = rep->init_type_reply; 853 props->grh_required = rep->grh_required; 854 855 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 856 if (err) 857 goto out; 858 859 err = translate_active_width(ibdev, ib_link_width_oper, 860 &props->active_width); 861 if (err) 862 goto out; 863 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 864 if (err) 865 goto out; 866 867 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 868 869 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 870 871 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 872 873 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 874 875 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 876 if (err) 877 goto out; 878 879 err = translate_max_vl_num(ibdev, vl_hw_cap, 880 &props->max_vl_num); 881 out: 882 kfree(rep); 883 return err; 884 } 885 886 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 887 struct ib_port_attr *props) 888 { 889 switch (mlx5_get_vport_access_method(ibdev)) { 890 case MLX5_VPORT_ACCESS_METHOD_MAD: 891 return mlx5_query_mad_ifc_port(ibdev, port, props); 892 893 case MLX5_VPORT_ACCESS_METHOD_HCA: 894 return mlx5_query_hca_port(ibdev, port, props); 895 896 case MLX5_VPORT_ACCESS_METHOD_NIC: 897 return mlx5_query_port_roce(ibdev, port, props); 898 899 default: 900 return -EINVAL; 901 } 902 } 903 904 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 905 union ib_gid *gid) 906 { 907 struct mlx5_ib_dev *dev = to_mdev(ibdev); 908 struct mlx5_core_dev *mdev = dev->mdev; 909 910 switch (mlx5_get_vport_access_method(ibdev)) { 911 case MLX5_VPORT_ACCESS_METHOD_MAD: 912 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 913 914 case MLX5_VPORT_ACCESS_METHOD_HCA: 915 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 916 917 default: 918 return -EINVAL; 919 } 920 921 } 922 923 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 924 u16 *pkey) 925 { 926 struct mlx5_ib_dev *dev = to_mdev(ibdev); 927 struct mlx5_core_dev *mdev = dev->mdev; 928 929 switch (mlx5_get_vport_access_method(ibdev)) { 930 case MLX5_VPORT_ACCESS_METHOD_MAD: 931 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 932 933 case MLX5_VPORT_ACCESS_METHOD_HCA: 934 case MLX5_VPORT_ACCESS_METHOD_NIC: 935 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 936 pkey); 937 default: 938 return -EINVAL; 939 } 940 } 941 942 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 943 struct ib_device_modify *props) 944 { 945 struct mlx5_ib_dev *dev = to_mdev(ibdev); 946 struct mlx5_reg_node_desc in; 947 struct mlx5_reg_node_desc out; 948 int err; 949 950 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 951 return -EOPNOTSUPP; 952 953 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 954 return 0; 955 956 /* 957 * If possible, pass node desc to FW, so it can generate 958 * a 144 trap. If cmd fails, just ignore. 959 */ 960 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 961 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 962 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 963 if (err) 964 return err; 965 966 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 967 968 return err; 969 } 970 971 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 972 struct ib_port_modify *props) 973 { 974 struct mlx5_ib_dev *dev = to_mdev(ibdev); 975 struct ib_port_attr attr; 976 u32 tmp; 977 int err; 978 979 mutex_lock(&dev->cap_mask_mutex); 980 981 err = mlx5_ib_query_port(ibdev, port, &attr); 982 if (err) 983 goto out; 984 985 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 986 ~props->clr_port_cap_mask; 987 988 err = mlx5_set_port_caps(dev->mdev, port, tmp); 989 990 out: 991 mutex_unlock(&dev->cap_mask_mutex); 992 return err; 993 } 994 995 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 996 struct ib_udata *udata) 997 { 998 struct mlx5_ib_dev *dev = to_mdev(ibdev); 999 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1000 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1001 struct mlx5_ib_ucontext *context; 1002 struct mlx5_uuar_info *uuari; 1003 struct mlx5_uar *uars; 1004 int gross_uuars; 1005 int num_uars; 1006 int ver; 1007 int uuarn; 1008 int err; 1009 int i; 1010 size_t reqlen; 1011 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1012 max_cqe_version); 1013 1014 if (!dev->ib_active) 1015 return ERR_PTR(-EAGAIN); 1016 1017 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1018 return ERR_PTR(-EINVAL); 1019 1020 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1021 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1022 ver = 0; 1023 else if (reqlen >= min_req_v2) 1024 ver = 2; 1025 else 1026 return ERR_PTR(-EINVAL); 1027 1028 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1029 if (err) 1030 return ERR_PTR(err); 1031 1032 if (req.flags) 1033 return ERR_PTR(-EINVAL); 1034 1035 if (req.total_num_uuars > MLX5_MAX_UUARS) 1036 return ERR_PTR(-ENOMEM); 1037 1038 if (req.total_num_uuars == 0) 1039 return ERR_PTR(-EINVAL); 1040 1041 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1042 return ERR_PTR(-EOPNOTSUPP); 1043 1044 if (reqlen > sizeof(req) && 1045 !ib_is_udata_cleared(udata, sizeof(req), 1046 reqlen - sizeof(req))) 1047 return ERR_PTR(-EOPNOTSUPP); 1048 1049 req.total_num_uuars = ALIGN(req.total_num_uuars, 1050 MLX5_NON_FP_BF_REGS_PER_PAGE); 1051 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1052 return ERR_PTR(-EINVAL); 1053 1054 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1055 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1056 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1057 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1058 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1059 resp.cache_line_size = cache_line_size(); 1060 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1061 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1062 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1063 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1064 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1065 resp.cqe_version = min_t(__u8, 1066 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1067 req.max_cqe_version); 1068 resp.response_length = min(offsetof(typeof(resp), response_length) + 1069 sizeof(resp.response_length), udata->outlen); 1070 1071 context = kzalloc(sizeof(*context), GFP_KERNEL); 1072 if (!context) 1073 return ERR_PTR(-ENOMEM); 1074 1075 uuari = &context->uuari; 1076 mutex_init(&uuari->lock); 1077 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1078 if (!uars) { 1079 err = -ENOMEM; 1080 goto out_ctx; 1081 } 1082 1083 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1084 sizeof(*uuari->bitmap), 1085 GFP_KERNEL); 1086 if (!uuari->bitmap) { 1087 err = -ENOMEM; 1088 goto out_uar_ctx; 1089 } 1090 /* 1091 * clear all fast path uuars 1092 */ 1093 for (i = 0; i < gross_uuars; i++) { 1094 uuarn = i & 3; 1095 if (uuarn == 2 || uuarn == 3) 1096 set_bit(i, uuari->bitmap); 1097 } 1098 1099 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1100 if (!uuari->count) { 1101 err = -ENOMEM; 1102 goto out_bitmap; 1103 } 1104 1105 for (i = 0; i < num_uars; i++) { 1106 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1107 if (err) 1108 goto out_count; 1109 } 1110 1111 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1112 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1113 #endif 1114 1115 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1116 if (!context->upd_xlt_page) { 1117 err = -ENOMEM; 1118 goto out_uars; 1119 } 1120 mutex_init(&context->upd_xlt_page_mutex); 1121 1122 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1123 err = mlx5_core_alloc_transport_domain(dev->mdev, 1124 &context->tdn); 1125 if (err) 1126 goto out_page; 1127 } 1128 1129 INIT_LIST_HEAD(&context->vma_private_list); 1130 INIT_LIST_HEAD(&context->db_page_list); 1131 mutex_init(&context->db_page_mutex); 1132 1133 resp.tot_uuars = req.total_num_uuars; 1134 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1135 1136 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1137 resp.response_length += sizeof(resp.cqe_version); 1138 1139 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1140 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1141 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1142 resp.response_length += sizeof(resp.cmds_supp_uhw); 1143 } 1144 1145 /* 1146 * We don't want to expose information from the PCI bar that is located 1147 * after 4096 bytes, so if the arch only supports larger pages, let's 1148 * pretend we don't support reading the HCA's core clock. This is also 1149 * forced by mmap function. 1150 */ 1151 if (PAGE_SIZE <= 4096 && 1152 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1153 resp.comp_mask |= 1154 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1155 resp.hca_core_clock_offset = 1156 offsetof(struct mlx5_init_seg, internal_timer_h) % 1157 PAGE_SIZE; 1158 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1159 sizeof(resp.reserved2); 1160 } 1161 1162 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1163 if (err) 1164 goto out_td; 1165 1166 uuari->ver = ver; 1167 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1168 uuari->uars = uars; 1169 uuari->num_uars = num_uars; 1170 context->cqe_version = resp.cqe_version; 1171 1172 return &context->ibucontext; 1173 1174 out_td: 1175 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1176 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1177 1178 out_page: 1179 free_page(context->upd_xlt_page); 1180 1181 out_uars: 1182 for (i--; i >= 0; i--) 1183 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1184 out_count: 1185 kfree(uuari->count); 1186 1187 out_bitmap: 1188 kfree(uuari->bitmap); 1189 1190 out_uar_ctx: 1191 kfree(uars); 1192 1193 out_ctx: 1194 kfree(context); 1195 return ERR_PTR(err); 1196 } 1197 1198 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1199 { 1200 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1201 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1202 struct mlx5_uuar_info *uuari = &context->uuari; 1203 int i; 1204 1205 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1206 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1207 1208 free_page(context->upd_xlt_page); 1209 1210 for (i = 0; i < uuari->num_uars; i++) { 1211 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1212 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1213 } 1214 1215 kfree(uuari->count); 1216 kfree(uuari->bitmap); 1217 kfree(uuari->uars); 1218 kfree(context); 1219 1220 return 0; 1221 } 1222 1223 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1224 { 1225 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1226 } 1227 1228 static int get_command(unsigned long offset) 1229 { 1230 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1231 } 1232 1233 static int get_arg(unsigned long offset) 1234 { 1235 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1236 } 1237 1238 static int get_index(unsigned long offset) 1239 { 1240 return get_arg(offset); 1241 } 1242 1243 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1244 { 1245 /* vma_open is called when a new VMA is created on top of our VMA. This 1246 * is done through either mremap flow or split_vma (usually due to 1247 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1248 * as this VMA is strongly hardware related. Therefore we set the 1249 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1250 * calling us again and trying to do incorrect actions. We assume that 1251 * the original VMA size is exactly a single page, and therefore all 1252 * "splitting" operation will not happen to it. 1253 */ 1254 area->vm_ops = NULL; 1255 } 1256 1257 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1258 { 1259 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1260 1261 /* It's guaranteed that all VMAs opened on a FD are closed before the 1262 * file itself is closed, therefore no sync is needed with the regular 1263 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1264 * However need a sync with accessing the vma as part of 1265 * mlx5_ib_disassociate_ucontext. 1266 * The close operation is usually called under mm->mmap_sem except when 1267 * process is exiting. 1268 * The exiting case is handled explicitly as part of 1269 * mlx5_ib_disassociate_ucontext. 1270 */ 1271 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1272 1273 /* setting the vma context pointer to null in the mlx5_ib driver's 1274 * private data, to protect a race condition in 1275 * mlx5_ib_disassociate_ucontext(). 1276 */ 1277 mlx5_ib_vma_priv_data->vma = NULL; 1278 list_del(&mlx5_ib_vma_priv_data->list); 1279 kfree(mlx5_ib_vma_priv_data); 1280 } 1281 1282 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1283 .open = mlx5_ib_vma_open, 1284 .close = mlx5_ib_vma_close 1285 }; 1286 1287 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1288 struct mlx5_ib_ucontext *ctx) 1289 { 1290 struct mlx5_ib_vma_private_data *vma_prv; 1291 struct list_head *vma_head = &ctx->vma_private_list; 1292 1293 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1294 if (!vma_prv) 1295 return -ENOMEM; 1296 1297 vma_prv->vma = vma; 1298 vma->vm_private_data = vma_prv; 1299 vma->vm_ops = &mlx5_ib_vm_ops; 1300 1301 list_add(&vma_prv->list, vma_head); 1302 1303 return 0; 1304 } 1305 1306 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1307 { 1308 int ret; 1309 struct vm_area_struct *vma; 1310 struct mlx5_ib_vma_private_data *vma_private, *n; 1311 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1312 struct task_struct *owning_process = NULL; 1313 struct mm_struct *owning_mm = NULL; 1314 1315 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1316 if (!owning_process) 1317 return; 1318 1319 owning_mm = get_task_mm(owning_process); 1320 if (!owning_mm) { 1321 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1322 while (1) { 1323 put_task_struct(owning_process); 1324 usleep_range(1000, 2000); 1325 owning_process = get_pid_task(ibcontext->tgid, 1326 PIDTYPE_PID); 1327 if (!owning_process || 1328 owning_process->state == TASK_DEAD) { 1329 pr_info("disassociate ucontext done, task was terminated\n"); 1330 /* in case task was dead need to release the 1331 * task struct. 1332 */ 1333 if (owning_process) 1334 put_task_struct(owning_process); 1335 return; 1336 } 1337 } 1338 } 1339 1340 /* need to protect from a race on closing the vma as part of 1341 * mlx5_ib_vma_close. 1342 */ 1343 down_read(&owning_mm->mmap_sem); 1344 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1345 list) { 1346 vma = vma_private->vma; 1347 ret = zap_vma_ptes(vma, vma->vm_start, 1348 PAGE_SIZE); 1349 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1350 /* context going to be destroyed, should 1351 * not access ops any more. 1352 */ 1353 vma->vm_ops = NULL; 1354 list_del(&vma_private->list); 1355 kfree(vma_private); 1356 } 1357 up_read(&owning_mm->mmap_sem); 1358 mmput(owning_mm); 1359 put_task_struct(owning_process); 1360 } 1361 1362 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1363 { 1364 switch (cmd) { 1365 case MLX5_IB_MMAP_WC_PAGE: 1366 return "WC"; 1367 case MLX5_IB_MMAP_REGULAR_PAGE: 1368 return "best effort WC"; 1369 case MLX5_IB_MMAP_NC_PAGE: 1370 return "NC"; 1371 default: 1372 return NULL; 1373 } 1374 } 1375 1376 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1377 struct vm_area_struct *vma, 1378 struct mlx5_ib_ucontext *context) 1379 { 1380 struct mlx5_uuar_info *uuari = &context->uuari; 1381 int err; 1382 unsigned long idx; 1383 phys_addr_t pfn, pa; 1384 pgprot_t prot; 1385 1386 switch (cmd) { 1387 case MLX5_IB_MMAP_WC_PAGE: 1388 /* Some architectures don't support WC memory */ 1389 #if defined(CONFIG_X86) 1390 if (!pat_enabled()) 1391 return -EPERM; 1392 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1393 return -EPERM; 1394 #endif 1395 /* fall through */ 1396 case MLX5_IB_MMAP_REGULAR_PAGE: 1397 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1398 prot = pgprot_writecombine(vma->vm_page_prot); 1399 break; 1400 case MLX5_IB_MMAP_NC_PAGE: 1401 prot = pgprot_noncached(vma->vm_page_prot); 1402 break; 1403 default: 1404 return -EINVAL; 1405 } 1406 1407 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1408 return -EINVAL; 1409 1410 idx = get_index(vma->vm_pgoff); 1411 if (idx >= uuari->num_uars) 1412 return -EINVAL; 1413 1414 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1415 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1416 1417 vma->vm_page_prot = prot; 1418 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1419 PAGE_SIZE, vma->vm_page_prot); 1420 if (err) { 1421 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1422 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1423 return -EAGAIN; 1424 } 1425 1426 pa = pfn << PAGE_SHIFT; 1427 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1428 vma->vm_start, &pa); 1429 1430 return mlx5_ib_set_vma_data(vma, context); 1431 } 1432 1433 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1434 { 1435 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1436 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1437 unsigned long command; 1438 phys_addr_t pfn; 1439 1440 command = get_command(vma->vm_pgoff); 1441 switch (command) { 1442 case MLX5_IB_MMAP_WC_PAGE: 1443 case MLX5_IB_MMAP_NC_PAGE: 1444 case MLX5_IB_MMAP_REGULAR_PAGE: 1445 return uar_mmap(dev, command, vma, context); 1446 1447 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1448 return -ENOSYS; 1449 1450 case MLX5_IB_MMAP_CORE_CLOCK: 1451 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1452 return -EINVAL; 1453 1454 if (vma->vm_flags & VM_WRITE) 1455 return -EPERM; 1456 1457 /* Don't expose to user-space information it shouldn't have */ 1458 if (PAGE_SIZE > 4096) 1459 return -EOPNOTSUPP; 1460 1461 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1462 pfn = (dev->mdev->iseg_base + 1463 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1464 PAGE_SHIFT; 1465 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1466 PAGE_SIZE, vma->vm_page_prot)) 1467 return -EAGAIN; 1468 1469 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1470 vma->vm_start, 1471 (unsigned long long)pfn << PAGE_SHIFT); 1472 break; 1473 1474 default: 1475 return -EINVAL; 1476 } 1477 1478 return 0; 1479 } 1480 1481 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1482 struct ib_ucontext *context, 1483 struct ib_udata *udata) 1484 { 1485 struct mlx5_ib_alloc_pd_resp resp; 1486 struct mlx5_ib_pd *pd; 1487 int err; 1488 1489 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1490 if (!pd) 1491 return ERR_PTR(-ENOMEM); 1492 1493 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1494 if (err) { 1495 kfree(pd); 1496 return ERR_PTR(err); 1497 } 1498 1499 if (context) { 1500 resp.pdn = pd->pdn; 1501 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1502 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1503 kfree(pd); 1504 return ERR_PTR(-EFAULT); 1505 } 1506 } 1507 1508 return &pd->ibpd; 1509 } 1510 1511 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1512 { 1513 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1514 struct mlx5_ib_pd *mpd = to_mpd(pd); 1515 1516 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1517 kfree(mpd); 1518 1519 return 0; 1520 } 1521 1522 enum { 1523 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1524 MATCH_CRITERIA_ENABLE_MISC_BIT, 1525 MATCH_CRITERIA_ENABLE_INNER_BIT 1526 }; 1527 1528 #define HEADER_IS_ZERO(match_criteria, headers) \ 1529 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1530 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1531 1532 static u8 get_match_criteria_enable(u32 *match_criteria) 1533 { 1534 u8 match_criteria_enable; 1535 1536 match_criteria_enable = 1537 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1538 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1539 match_criteria_enable |= 1540 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1541 MATCH_CRITERIA_ENABLE_MISC_BIT; 1542 match_criteria_enable |= 1543 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1544 MATCH_CRITERIA_ENABLE_INNER_BIT; 1545 1546 return match_criteria_enable; 1547 } 1548 1549 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1550 { 1551 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1552 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1553 } 1554 1555 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1556 bool inner) 1557 { 1558 if (inner) { 1559 MLX5_SET(fte_match_set_misc, 1560 misc_c, inner_ipv6_flow_label, mask); 1561 MLX5_SET(fte_match_set_misc, 1562 misc_v, inner_ipv6_flow_label, val); 1563 } else { 1564 MLX5_SET(fte_match_set_misc, 1565 misc_c, outer_ipv6_flow_label, mask); 1566 MLX5_SET(fte_match_set_misc, 1567 misc_v, outer_ipv6_flow_label, val); 1568 } 1569 } 1570 1571 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1572 { 1573 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1574 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1575 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1576 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1577 } 1578 1579 #define LAST_ETH_FIELD vlan_tag 1580 #define LAST_IB_FIELD sl 1581 #define LAST_IPV4_FIELD tos 1582 #define LAST_IPV6_FIELD traffic_class 1583 #define LAST_TCP_UDP_FIELD src_port 1584 #define LAST_TUNNEL_FIELD tunnel_id 1585 1586 /* Field is the last supported field */ 1587 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1588 memchr_inv((void *)&filter.field +\ 1589 sizeof(filter.field), 0,\ 1590 sizeof(filter) -\ 1591 offsetof(typeof(filter), field) -\ 1592 sizeof(filter.field)) 1593 1594 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1595 const union ib_flow_spec *ib_spec) 1596 { 1597 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1598 misc_parameters); 1599 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1600 misc_parameters); 1601 void *headers_c; 1602 void *headers_v; 1603 1604 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1605 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1606 inner_headers); 1607 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1608 inner_headers); 1609 } else { 1610 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1611 outer_headers); 1612 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1613 outer_headers); 1614 } 1615 1616 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1617 case IB_FLOW_SPEC_ETH: 1618 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1619 return -ENOTSUPP; 1620 1621 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1622 dmac_47_16), 1623 ib_spec->eth.mask.dst_mac); 1624 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1625 dmac_47_16), 1626 ib_spec->eth.val.dst_mac); 1627 1628 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1629 smac_47_16), 1630 ib_spec->eth.mask.src_mac); 1631 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1632 smac_47_16), 1633 ib_spec->eth.val.src_mac); 1634 1635 if (ib_spec->eth.mask.vlan_tag) { 1636 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1637 vlan_tag, 1); 1638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1639 vlan_tag, 1); 1640 1641 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1642 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1643 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1644 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1645 1646 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1647 first_cfi, 1648 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1649 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1650 first_cfi, 1651 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1652 1653 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1654 first_prio, 1655 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1657 first_prio, 1658 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1659 } 1660 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1661 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1663 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1664 break; 1665 case IB_FLOW_SPEC_IPV4: 1666 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1667 return -ENOTSUPP; 1668 1669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1670 ethertype, 0xffff); 1671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1672 ethertype, ETH_P_IP); 1673 1674 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1675 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1676 &ib_spec->ipv4.mask.src_ip, 1677 sizeof(ib_spec->ipv4.mask.src_ip)); 1678 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1679 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1680 &ib_spec->ipv4.val.src_ip, 1681 sizeof(ib_spec->ipv4.val.src_ip)); 1682 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1683 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1684 &ib_spec->ipv4.mask.dst_ip, 1685 sizeof(ib_spec->ipv4.mask.dst_ip)); 1686 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1687 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1688 &ib_spec->ipv4.val.dst_ip, 1689 sizeof(ib_spec->ipv4.val.dst_ip)); 1690 1691 set_tos(headers_c, headers_v, 1692 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1693 1694 set_proto(headers_c, headers_v, 1695 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1696 break; 1697 case IB_FLOW_SPEC_IPV6: 1698 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1699 return -ENOTSUPP; 1700 1701 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1702 ethertype, 0xffff); 1703 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1704 ethertype, ETH_P_IPV6); 1705 1706 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1707 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1708 &ib_spec->ipv6.mask.src_ip, 1709 sizeof(ib_spec->ipv6.mask.src_ip)); 1710 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1711 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1712 &ib_spec->ipv6.val.src_ip, 1713 sizeof(ib_spec->ipv6.val.src_ip)); 1714 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1715 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1716 &ib_spec->ipv6.mask.dst_ip, 1717 sizeof(ib_spec->ipv6.mask.dst_ip)); 1718 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1719 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1720 &ib_spec->ipv6.val.dst_ip, 1721 sizeof(ib_spec->ipv6.val.dst_ip)); 1722 1723 set_tos(headers_c, headers_v, 1724 ib_spec->ipv6.mask.traffic_class, 1725 ib_spec->ipv6.val.traffic_class); 1726 1727 set_proto(headers_c, headers_v, 1728 ib_spec->ipv6.mask.next_hdr, 1729 ib_spec->ipv6.val.next_hdr); 1730 1731 set_flow_label(misc_params_c, misc_params_v, 1732 ntohl(ib_spec->ipv6.mask.flow_label), 1733 ntohl(ib_spec->ipv6.val.flow_label), 1734 ib_spec->type & IB_FLOW_SPEC_INNER); 1735 1736 break; 1737 case IB_FLOW_SPEC_TCP: 1738 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1739 LAST_TCP_UDP_FIELD)) 1740 return -ENOTSUPP; 1741 1742 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1743 0xff); 1744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1745 IPPROTO_TCP); 1746 1747 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 1748 ntohs(ib_spec->tcp_udp.mask.src_port)); 1749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 1750 ntohs(ib_spec->tcp_udp.val.src_port)); 1751 1752 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 1753 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1754 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 1755 ntohs(ib_spec->tcp_udp.val.dst_port)); 1756 break; 1757 case IB_FLOW_SPEC_UDP: 1758 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1759 LAST_TCP_UDP_FIELD)) 1760 return -ENOTSUPP; 1761 1762 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1763 0xff); 1764 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1765 IPPROTO_UDP); 1766 1767 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 1768 ntohs(ib_spec->tcp_udp.mask.src_port)); 1769 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 1770 ntohs(ib_spec->tcp_udp.val.src_port)); 1771 1772 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 1773 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1774 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 1775 ntohs(ib_spec->tcp_udp.val.dst_port)); 1776 break; 1777 case IB_FLOW_SPEC_VXLAN_TUNNEL: 1778 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 1779 LAST_TUNNEL_FIELD)) 1780 return -ENOTSUPP; 1781 1782 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 1783 ntohl(ib_spec->tunnel.mask.tunnel_id)); 1784 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 1785 ntohl(ib_spec->tunnel.val.tunnel_id)); 1786 break; 1787 default: 1788 return -EINVAL; 1789 } 1790 1791 return 0; 1792 } 1793 1794 /* If a flow could catch both multicast and unicast packets, 1795 * it won't fall into the multicast flow steering table and this rule 1796 * could steal other multicast packets. 1797 */ 1798 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1799 { 1800 struct ib_flow_spec_eth *eth_spec; 1801 1802 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1803 ib_attr->size < sizeof(struct ib_flow_attr) + 1804 sizeof(struct ib_flow_spec_eth) || 1805 ib_attr->num_of_specs < 1) 1806 return false; 1807 1808 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1809 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1810 eth_spec->size != sizeof(*eth_spec)) 1811 return false; 1812 1813 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1814 is_multicast_ether_addr(eth_spec->val.dst_mac); 1815 } 1816 1817 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1818 { 1819 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1820 bool has_ipv4_spec = false; 1821 bool eth_type_ipv4 = true; 1822 unsigned int spec_index; 1823 1824 /* Validate that ethertype is correct */ 1825 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1826 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1827 ib_spec->eth.mask.ether_type) { 1828 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1829 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1830 eth_type_ipv4 = false; 1831 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1832 has_ipv4_spec = true; 1833 } 1834 ib_spec = (void *)ib_spec + ib_spec->size; 1835 } 1836 return !has_ipv4_spec || eth_type_ipv4; 1837 } 1838 1839 static void put_flow_table(struct mlx5_ib_dev *dev, 1840 struct mlx5_ib_flow_prio *prio, bool ft_added) 1841 { 1842 prio->refcount -= !!ft_added; 1843 if (!prio->refcount) { 1844 mlx5_destroy_flow_table(prio->flow_table); 1845 prio->flow_table = NULL; 1846 } 1847 } 1848 1849 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1850 { 1851 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1852 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1853 struct mlx5_ib_flow_handler, 1854 ibflow); 1855 struct mlx5_ib_flow_handler *iter, *tmp; 1856 1857 mutex_lock(&dev->flow_db.lock); 1858 1859 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1860 mlx5_del_flow_rules(iter->rule); 1861 put_flow_table(dev, iter->prio, true); 1862 list_del(&iter->list); 1863 kfree(iter); 1864 } 1865 1866 mlx5_del_flow_rules(handler->rule); 1867 put_flow_table(dev, handler->prio, true); 1868 mutex_unlock(&dev->flow_db.lock); 1869 1870 kfree(handler); 1871 1872 return 0; 1873 } 1874 1875 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1876 { 1877 priority *= 2; 1878 if (!dont_trap) 1879 priority++; 1880 return priority; 1881 } 1882 1883 enum flow_table_type { 1884 MLX5_IB_FT_RX, 1885 MLX5_IB_FT_TX 1886 }; 1887 1888 #define MLX5_FS_MAX_TYPES 10 1889 #define MLX5_FS_MAX_ENTRIES 32000UL 1890 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1891 struct ib_flow_attr *flow_attr, 1892 enum flow_table_type ft_type) 1893 { 1894 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1895 struct mlx5_flow_namespace *ns = NULL; 1896 struct mlx5_ib_flow_prio *prio; 1897 struct mlx5_flow_table *ft; 1898 int num_entries; 1899 int num_groups; 1900 int priority; 1901 int err = 0; 1902 1903 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1904 if (flow_is_multicast_only(flow_attr) && 1905 !dont_trap) 1906 priority = MLX5_IB_FLOW_MCAST_PRIO; 1907 else 1908 priority = ib_prio_to_core_prio(flow_attr->priority, 1909 dont_trap); 1910 ns = mlx5_get_flow_namespace(dev->mdev, 1911 MLX5_FLOW_NAMESPACE_BYPASS); 1912 num_entries = MLX5_FS_MAX_ENTRIES; 1913 num_groups = MLX5_FS_MAX_TYPES; 1914 prio = &dev->flow_db.prios[priority]; 1915 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1916 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1917 ns = mlx5_get_flow_namespace(dev->mdev, 1918 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1919 build_leftovers_ft_param(&priority, 1920 &num_entries, 1921 &num_groups); 1922 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1923 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1924 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1925 allow_sniffer_and_nic_rx_shared_tir)) 1926 return ERR_PTR(-ENOTSUPP); 1927 1928 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 1929 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 1930 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 1931 1932 prio = &dev->flow_db.sniffer[ft_type]; 1933 priority = 0; 1934 num_entries = 1; 1935 num_groups = 1; 1936 } 1937 1938 if (!ns) 1939 return ERR_PTR(-ENOTSUPP); 1940 1941 ft = prio->flow_table; 1942 if (!ft) { 1943 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1944 num_entries, 1945 num_groups, 1946 0, 0); 1947 1948 if (!IS_ERR(ft)) { 1949 prio->refcount = 0; 1950 prio->flow_table = ft; 1951 } else { 1952 err = PTR_ERR(ft); 1953 } 1954 } 1955 1956 return err ? ERR_PTR(err) : prio; 1957 } 1958 1959 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1960 struct mlx5_ib_flow_prio *ft_prio, 1961 const struct ib_flow_attr *flow_attr, 1962 struct mlx5_flow_destination *dst) 1963 { 1964 struct mlx5_flow_table *ft = ft_prio->flow_table; 1965 struct mlx5_ib_flow_handler *handler; 1966 struct mlx5_flow_act flow_act = {0}; 1967 struct mlx5_flow_spec *spec; 1968 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 1969 unsigned int spec_index; 1970 int err = 0; 1971 1972 if (!is_valid_attr(flow_attr)) 1973 return ERR_PTR(-EINVAL); 1974 1975 spec = mlx5_vzalloc(sizeof(*spec)); 1976 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1977 if (!handler || !spec) { 1978 err = -ENOMEM; 1979 goto free; 1980 } 1981 1982 INIT_LIST_HEAD(&handler->list); 1983 1984 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1985 err = parse_flow_attr(spec->match_criteria, 1986 spec->match_value, ib_flow); 1987 if (err < 0) 1988 goto free; 1989 1990 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1991 } 1992 1993 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 1994 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1995 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1996 flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 1997 handler->rule = mlx5_add_flow_rules(ft, spec, 1998 &flow_act, 1999 dst, 1); 2000 2001 if (IS_ERR(handler->rule)) { 2002 err = PTR_ERR(handler->rule); 2003 goto free; 2004 } 2005 2006 ft_prio->refcount++; 2007 handler->prio = ft_prio; 2008 2009 ft_prio->flow_table = ft; 2010 free: 2011 if (err) 2012 kfree(handler); 2013 kvfree(spec); 2014 return err ? ERR_PTR(err) : handler; 2015 } 2016 2017 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2018 struct mlx5_ib_flow_prio *ft_prio, 2019 struct ib_flow_attr *flow_attr, 2020 struct mlx5_flow_destination *dst) 2021 { 2022 struct mlx5_ib_flow_handler *handler_dst = NULL; 2023 struct mlx5_ib_flow_handler *handler = NULL; 2024 2025 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2026 if (!IS_ERR(handler)) { 2027 handler_dst = create_flow_rule(dev, ft_prio, 2028 flow_attr, dst); 2029 if (IS_ERR(handler_dst)) { 2030 mlx5_del_flow_rules(handler->rule); 2031 ft_prio->refcount--; 2032 kfree(handler); 2033 handler = handler_dst; 2034 } else { 2035 list_add(&handler_dst->list, &handler->list); 2036 } 2037 } 2038 2039 return handler; 2040 } 2041 enum { 2042 LEFTOVERS_MC, 2043 LEFTOVERS_UC, 2044 }; 2045 2046 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2047 struct mlx5_ib_flow_prio *ft_prio, 2048 struct ib_flow_attr *flow_attr, 2049 struct mlx5_flow_destination *dst) 2050 { 2051 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2052 struct mlx5_ib_flow_handler *handler = NULL; 2053 2054 static struct { 2055 struct ib_flow_attr flow_attr; 2056 struct ib_flow_spec_eth eth_flow; 2057 } leftovers_specs[] = { 2058 [LEFTOVERS_MC] = { 2059 .flow_attr = { 2060 .num_of_specs = 1, 2061 .size = sizeof(leftovers_specs[0]) 2062 }, 2063 .eth_flow = { 2064 .type = IB_FLOW_SPEC_ETH, 2065 .size = sizeof(struct ib_flow_spec_eth), 2066 .mask = {.dst_mac = {0x1} }, 2067 .val = {.dst_mac = {0x1} } 2068 } 2069 }, 2070 [LEFTOVERS_UC] = { 2071 .flow_attr = { 2072 .num_of_specs = 1, 2073 .size = sizeof(leftovers_specs[0]) 2074 }, 2075 .eth_flow = { 2076 .type = IB_FLOW_SPEC_ETH, 2077 .size = sizeof(struct ib_flow_spec_eth), 2078 .mask = {.dst_mac = {0x1} }, 2079 .val = {.dst_mac = {} } 2080 } 2081 } 2082 }; 2083 2084 handler = create_flow_rule(dev, ft_prio, 2085 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2086 dst); 2087 if (!IS_ERR(handler) && 2088 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2089 handler_ucast = create_flow_rule(dev, ft_prio, 2090 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2091 dst); 2092 if (IS_ERR(handler_ucast)) { 2093 mlx5_del_flow_rules(handler->rule); 2094 ft_prio->refcount--; 2095 kfree(handler); 2096 handler = handler_ucast; 2097 } else { 2098 list_add(&handler_ucast->list, &handler->list); 2099 } 2100 } 2101 2102 return handler; 2103 } 2104 2105 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2106 struct mlx5_ib_flow_prio *ft_rx, 2107 struct mlx5_ib_flow_prio *ft_tx, 2108 struct mlx5_flow_destination *dst) 2109 { 2110 struct mlx5_ib_flow_handler *handler_rx; 2111 struct mlx5_ib_flow_handler *handler_tx; 2112 int err; 2113 static const struct ib_flow_attr flow_attr = { 2114 .num_of_specs = 0, 2115 .size = sizeof(flow_attr) 2116 }; 2117 2118 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2119 if (IS_ERR(handler_rx)) { 2120 err = PTR_ERR(handler_rx); 2121 goto err; 2122 } 2123 2124 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2125 if (IS_ERR(handler_tx)) { 2126 err = PTR_ERR(handler_tx); 2127 goto err_tx; 2128 } 2129 2130 list_add(&handler_tx->list, &handler_rx->list); 2131 2132 return handler_rx; 2133 2134 err_tx: 2135 mlx5_del_flow_rules(handler_rx->rule); 2136 ft_rx->refcount--; 2137 kfree(handler_rx); 2138 err: 2139 return ERR_PTR(err); 2140 } 2141 2142 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2143 struct ib_flow_attr *flow_attr, 2144 int domain) 2145 { 2146 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2147 struct mlx5_ib_qp *mqp = to_mqp(qp); 2148 struct mlx5_ib_flow_handler *handler = NULL; 2149 struct mlx5_flow_destination *dst = NULL; 2150 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2151 struct mlx5_ib_flow_prio *ft_prio; 2152 int err; 2153 2154 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2155 return ERR_PTR(-ENOSPC); 2156 2157 if (domain != IB_FLOW_DOMAIN_USER || 2158 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2159 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2160 return ERR_PTR(-EINVAL); 2161 2162 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2163 if (!dst) 2164 return ERR_PTR(-ENOMEM); 2165 2166 mutex_lock(&dev->flow_db.lock); 2167 2168 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2169 if (IS_ERR(ft_prio)) { 2170 err = PTR_ERR(ft_prio); 2171 goto unlock; 2172 } 2173 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2174 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2175 if (IS_ERR(ft_prio_tx)) { 2176 err = PTR_ERR(ft_prio_tx); 2177 ft_prio_tx = NULL; 2178 goto destroy_ft; 2179 } 2180 } 2181 2182 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2183 if (mqp->flags & MLX5_IB_QP_RSS) 2184 dst->tir_num = mqp->rss_qp.tirn; 2185 else 2186 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2187 2188 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2189 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2190 handler = create_dont_trap_rule(dev, ft_prio, 2191 flow_attr, dst); 2192 } else { 2193 handler = create_flow_rule(dev, ft_prio, flow_attr, 2194 dst); 2195 } 2196 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2197 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2198 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2199 dst); 2200 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2201 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2202 } else { 2203 err = -EINVAL; 2204 goto destroy_ft; 2205 } 2206 2207 if (IS_ERR(handler)) { 2208 err = PTR_ERR(handler); 2209 handler = NULL; 2210 goto destroy_ft; 2211 } 2212 2213 mutex_unlock(&dev->flow_db.lock); 2214 kfree(dst); 2215 2216 return &handler->ibflow; 2217 2218 destroy_ft: 2219 put_flow_table(dev, ft_prio, false); 2220 if (ft_prio_tx) 2221 put_flow_table(dev, ft_prio_tx, false); 2222 unlock: 2223 mutex_unlock(&dev->flow_db.lock); 2224 kfree(dst); 2225 kfree(handler); 2226 return ERR_PTR(err); 2227 } 2228 2229 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2230 { 2231 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2232 int err; 2233 2234 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2235 if (err) 2236 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2237 ibqp->qp_num, gid->raw); 2238 2239 return err; 2240 } 2241 2242 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2243 { 2244 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2245 int err; 2246 2247 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2248 if (err) 2249 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2250 ibqp->qp_num, gid->raw); 2251 2252 return err; 2253 } 2254 2255 static int init_node_data(struct mlx5_ib_dev *dev) 2256 { 2257 int err; 2258 2259 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2260 if (err) 2261 return err; 2262 2263 dev->mdev->rev_id = dev->mdev->pdev->revision; 2264 2265 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2266 } 2267 2268 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2269 char *buf) 2270 { 2271 struct mlx5_ib_dev *dev = 2272 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2273 2274 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2275 } 2276 2277 static ssize_t show_reg_pages(struct device *device, 2278 struct device_attribute *attr, char *buf) 2279 { 2280 struct mlx5_ib_dev *dev = 2281 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2282 2283 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2284 } 2285 2286 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2287 char *buf) 2288 { 2289 struct mlx5_ib_dev *dev = 2290 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2291 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2292 } 2293 2294 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2295 char *buf) 2296 { 2297 struct mlx5_ib_dev *dev = 2298 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2299 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2300 } 2301 2302 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2303 char *buf) 2304 { 2305 struct mlx5_ib_dev *dev = 2306 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2307 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2308 dev->mdev->board_id); 2309 } 2310 2311 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2312 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2313 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2314 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2315 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2316 2317 static struct device_attribute *mlx5_class_attributes[] = { 2318 &dev_attr_hw_rev, 2319 &dev_attr_hca_type, 2320 &dev_attr_board_id, 2321 &dev_attr_fw_pages, 2322 &dev_attr_reg_pages, 2323 }; 2324 2325 static void pkey_change_handler(struct work_struct *work) 2326 { 2327 struct mlx5_ib_port_resources *ports = 2328 container_of(work, struct mlx5_ib_port_resources, 2329 pkey_change_work); 2330 2331 mutex_lock(&ports->devr->mutex); 2332 mlx5_ib_gsi_pkey_change(ports->gsi); 2333 mutex_unlock(&ports->devr->mutex); 2334 } 2335 2336 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2337 { 2338 struct mlx5_ib_qp *mqp; 2339 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2340 struct mlx5_core_cq *mcq; 2341 struct list_head cq_armed_list; 2342 unsigned long flags_qp; 2343 unsigned long flags_cq; 2344 unsigned long flags; 2345 2346 INIT_LIST_HEAD(&cq_armed_list); 2347 2348 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2349 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2350 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2351 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2352 if (mqp->sq.tail != mqp->sq.head) { 2353 send_mcq = to_mcq(mqp->ibqp.send_cq); 2354 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2355 if (send_mcq->mcq.comp && 2356 mqp->ibqp.send_cq->comp_handler) { 2357 if (!send_mcq->mcq.reset_notify_added) { 2358 send_mcq->mcq.reset_notify_added = 1; 2359 list_add_tail(&send_mcq->mcq.reset_notify, 2360 &cq_armed_list); 2361 } 2362 } 2363 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2364 } 2365 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2366 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2367 /* no handling is needed for SRQ */ 2368 if (!mqp->ibqp.srq) { 2369 if (mqp->rq.tail != mqp->rq.head) { 2370 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2371 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2372 if (recv_mcq->mcq.comp && 2373 mqp->ibqp.recv_cq->comp_handler) { 2374 if (!recv_mcq->mcq.reset_notify_added) { 2375 recv_mcq->mcq.reset_notify_added = 1; 2376 list_add_tail(&recv_mcq->mcq.reset_notify, 2377 &cq_armed_list); 2378 } 2379 } 2380 spin_unlock_irqrestore(&recv_mcq->lock, 2381 flags_cq); 2382 } 2383 } 2384 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2385 } 2386 /*At that point all inflight post send were put to be executed as of we 2387 * lock/unlock above locks Now need to arm all involved CQs. 2388 */ 2389 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2390 mcq->comp(mcq); 2391 } 2392 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2393 } 2394 2395 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2396 enum mlx5_dev_event event, unsigned long param) 2397 { 2398 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2399 struct ib_event ibev; 2400 bool fatal = false; 2401 u8 port = 0; 2402 2403 switch (event) { 2404 case MLX5_DEV_EVENT_SYS_ERROR: 2405 ibev.event = IB_EVENT_DEVICE_FATAL; 2406 mlx5_ib_handle_internal_error(ibdev); 2407 fatal = true; 2408 break; 2409 2410 case MLX5_DEV_EVENT_PORT_UP: 2411 case MLX5_DEV_EVENT_PORT_DOWN: 2412 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2413 port = (u8)param; 2414 2415 /* In RoCE, port up/down events are handled in 2416 * mlx5_netdev_event(). 2417 */ 2418 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2419 IB_LINK_LAYER_ETHERNET) 2420 return; 2421 2422 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2423 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2424 break; 2425 2426 case MLX5_DEV_EVENT_LID_CHANGE: 2427 ibev.event = IB_EVENT_LID_CHANGE; 2428 port = (u8)param; 2429 break; 2430 2431 case MLX5_DEV_EVENT_PKEY_CHANGE: 2432 ibev.event = IB_EVENT_PKEY_CHANGE; 2433 port = (u8)param; 2434 2435 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2436 break; 2437 2438 case MLX5_DEV_EVENT_GUID_CHANGE: 2439 ibev.event = IB_EVENT_GID_CHANGE; 2440 port = (u8)param; 2441 break; 2442 2443 case MLX5_DEV_EVENT_CLIENT_REREG: 2444 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2445 port = (u8)param; 2446 break; 2447 default: 2448 return; 2449 } 2450 2451 ibev.device = &ibdev->ib_dev; 2452 ibev.element.port_num = port; 2453 2454 if (port < 1 || port > ibdev->num_ports) { 2455 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2456 return; 2457 } 2458 2459 if (ibdev->ib_active) 2460 ib_dispatch_event(&ibev); 2461 2462 if (fatal) 2463 ibdev->ib_active = false; 2464 } 2465 2466 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2467 { 2468 int port; 2469 2470 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2471 mlx5_query_ext_port_caps(dev, port); 2472 } 2473 2474 static int get_port_caps(struct mlx5_ib_dev *dev) 2475 { 2476 struct ib_device_attr *dprops = NULL; 2477 struct ib_port_attr *pprops = NULL; 2478 int err = -ENOMEM; 2479 int port; 2480 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2481 2482 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2483 if (!pprops) 2484 goto out; 2485 2486 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2487 if (!dprops) 2488 goto out; 2489 2490 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2491 if (err) { 2492 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2493 goto out; 2494 } 2495 2496 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2497 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2498 if (err) { 2499 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2500 port, err); 2501 break; 2502 } 2503 dev->mdev->port_caps[port - 1].pkey_table_len = 2504 dprops->max_pkeys; 2505 dev->mdev->port_caps[port - 1].gid_table_len = 2506 pprops->gid_tbl_len; 2507 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2508 dprops->max_pkeys, pprops->gid_tbl_len); 2509 } 2510 2511 out: 2512 kfree(pprops); 2513 kfree(dprops); 2514 2515 return err; 2516 } 2517 2518 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2519 { 2520 int err; 2521 2522 err = mlx5_mr_cache_cleanup(dev); 2523 if (err) 2524 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2525 2526 mlx5_ib_destroy_qp(dev->umrc.qp); 2527 ib_free_cq(dev->umrc.cq); 2528 ib_dealloc_pd(dev->umrc.pd); 2529 } 2530 2531 enum { 2532 MAX_UMR_WR = 128, 2533 }; 2534 2535 static int create_umr_res(struct mlx5_ib_dev *dev) 2536 { 2537 struct ib_qp_init_attr *init_attr = NULL; 2538 struct ib_qp_attr *attr = NULL; 2539 struct ib_pd *pd; 2540 struct ib_cq *cq; 2541 struct ib_qp *qp; 2542 int ret; 2543 2544 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2545 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2546 if (!attr || !init_attr) { 2547 ret = -ENOMEM; 2548 goto error_0; 2549 } 2550 2551 pd = ib_alloc_pd(&dev->ib_dev, 0); 2552 if (IS_ERR(pd)) { 2553 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2554 ret = PTR_ERR(pd); 2555 goto error_0; 2556 } 2557 2558 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2559 if (IS_ERR(cq)) { 2560 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2561 ret = PTR_ERR(cq); 2562 goto error_2; 2563 } 2564 2565 init_attr->send_cq = cq; 2566 init_attr->recv_cq = cq; 2567 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2568 init_attr->cap.max_send_wr = MAX_UMR_WR; 2569 init_attr->cap.max_send_sge = 1; 2570 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2571 init_attr->port_num = 1; 2572 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2573 if (IS_ERR(qp)) { 2574 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2575 ret = PTR_ERR(qp); 2576 goto error_3; 2577 } 2578 qp->device = &dev->ib_dev; 2579 qp->real_qp = qp; 2580 qp->uobject = NULL; 2581 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2582 2583 attr->qp_state = IB_QPS_INIT; 2584 attr->port_num = 1; 2585 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2586 IB_QP_PORT, NULL); 2587 if (ret) { 2588 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2589 goto error_4; 2590 } 2591 2592 memset(attr, 0, sizeof(*attr)); 2593 attr->qp_state = IB_QPS_RTR; 2594 attr->path_mtu = IB_MTU_256; 2595 2596 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2597 if (ret) { 2598 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2599 goto error_4; 2600 } 2601 2602 memset(attr, 0, sizeof(*attr)); 2603 attr->qp_state = IB_QPS_RTS; 2604 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2605 if (ret) { 2606 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2607 goto error_4; 2608 } 2609 2610 dev->umrc.qp = qp; 2611 dev->umrc.cq = cq; 2612 dev->umrc.pd = pd; 2613 2614 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2615 ret = mlx5_mr_cache_init(dev); 2616 if (ret) { 2617 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2618 goto error_4; 2619 } 2620 2621 kfree(attr); 2622 kfree(init_attr); 2623 2624 return 0; 2625 2626 error_4: 2627 mlx5_ib_destroy_qp(qp); 2628 2629 error_3: 2630 ib_free_cq(cq); 2631 2632 error_2: 2633 ib_dealloc_pd(pd); 2634 2635 error_0: 2636 kfree(attr); 2637 kfree(init_attr); 2638 return ret; 2639 } 2640 2641 static int create_dev_resources(struct mlx5_ib_resources *devr) 2642 { 2643 struct ib_srq_init_attr attr; 2644 struct mlx5_ib_dev *dev; 2645 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2646 int port; 2647 int ret = 0; 2648 2649 dev = container_of(devr, struct mlx5_ib_dev, devr); 2650 2651 mutex_init(&devr->mutex); 2652 2653 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2654 if (IS_ERR(devr->p0)) { 2655 ret = PTR_ERR(devr->p0); 2656 goto error0; 2657 } 2658 devr->p0->device = &dev->ib_dev; 2659 devr->p0->uobject = NULL; 2660 atomic_set(&devr->p0->usecnt, 0); 2661 2662 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2663 if (IS_ERR(devr->c0)) { 2664 ret = PTR_ERR(devr->c0); 2665 goto error1; 2666 } 2667 devr->c0->device = &dev->ib_dev; 2668 devr->c0->uobject = NULL; 2669 devr->c0->comp_handler = NULL; 2670 devr->c0->event_handler = NULL; 2671 devr->c0->cq_context = NULL; 2672 atomic_set(&devr->c0->usecnt, 0); 2673 2674 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2675 if (IS_ERR(devr->x0)) { 2676 ret = PTR_ERR(devr->x0); 2677 goto error2; 2678 } 2679 devr->x0->device = &dev->ib_dev; 2680 devr->x0->inode = NULL; 2681 atomic_set(&devr->x0->usecnt, 0); 2682 mutex_init(&devr->x0->tgt_qp_mutex); 2683 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2684 2685 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2686 if (IS_ERR(devr->x1)) { 2687 ret = PTR_ERR(devr->x1); 2688 goto error3; 2689 } 2690 devr->x1->device = &dev->ib_dev; 2691 devr->x1->inode = NULL; 2692 atomic_set(&devr->x1->usecnt, 0); 2693 mutex_init(&devr->x1->tgt_qp_mutex); 2694 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2695 2696 memset(&attr, 0, sizeof(attr)); 2697 attr.attr.max_sge = 1; 2698 attr.attr.max_wr = 1; 2699 attr.srq_type = IB_SRQT_XRC; 2700 attr.ext.xrc.cq = devr->c0; 2701 attr.ext.xrc.xrcd = devr->x0; 2702 2703 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2704 if (IS_ERR(devr->s0)) { 2705 ret = PTR_ERR(devr->s0); 2706 goto error4; 2707 } 2708 devr->s0->device = &dev->ib_dev; 2709 devr->s0->pd = devr->p0; 2710 devr->s0->uobject = NULL; 2711 devr->s0->event_handler = NULL; 2712 devr->s0->srq_context = NULL; 2713 devr->s0->srq_type = IB_SRQT_XRC; 2714 devr->s0->ext.xrc.xrcd = devr->x0; 2715 devr->s0->ext.xrc.cq = devr->c0; 2716 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2717 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2718 atomic_inc(&devr->p0->usecnt); 2719 atomic_set(&devr->s0->usecnt, 0); 2720 2721 memset(&attr, 0, sizeof(attr)); 2722 attr.attr.max_sge = 1; 2723 attr.attr.max_wr = 1; 2724 attr.srq_type = IB_SRQT_BASIC; 2725 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2726 if (IS_ERR(devr->s1)) { 2727 ret = PTR_ERR(devr->s1); 2728 goto error5; 2729 } 2730 devr->s1->device = &dev->ib_dev; 2731 devr->s1->pd = devr->p0; 2732 devr->s1->uobject = NULL; 2733 devr->s1->event_handler = NULL; 2734 devr->s1->srq_context = NULL; 2735 devr->s1->srq_type = IB_SRQT_BASIC; 2736 devr->s1->ext.xrc.cq = devr->c0; 2737 atomic_inc(&devr->p0->usecnt); 2738 atomic_set(&devr->s0->usecnt, 0); 2739 2740 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2741 INIT_WORK(&devr->ports[port].pkey_change_work, 2742 pkey_change_handler); 2743 devr->ports[port].devr = devr; 2744 } 2745 2746 return 0; 2747 2748 error5: 2749 mlx5_ib_destroy_srq(devr->s0); 2750 error4: 2751 mlx5_ib_dealloc_xrcd(devr->x1); 2752 error3: 2753 mlx5_ib_dealloc_xrcd(devr->x0); 2754 error2: 2755 mlx5_ib_destroy_cq(devr->c0); 2756 error1: 2757 mlx5_ib_dealloc_pd(devr->p0); 2758 error0: 2759 return ret; 2760 } 2761 2762 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2763 { 2764 struct mlx5_ib_dev *dev = 2765 container_of(devr, struct mlx5_ib_dev, devr); 2766 int port; 2767 2768 mlx5_ib_destroy_srq(devr->s1); 2769 mlx5_ib_destroy_srq(devr->s0); 2770 mlx5_ib_dealloc_xrcd(devr->x0); 2771 mlx5_ib_dealloc_xrcd(devr->x1); 2772 mlx5_ib_destroy_cq(devr->c0); 2773 mlx5_ib_dealloc_pd(devr->p0); 2774 2775 /* Make sure no change P_Key work items are still executing */ 2776 for (port = 0; port < dev->num_ports; ++port) 2777 cancel_work_sync(&devr->ports[port].pkey_change_work); 2778 } 2779 2780 static u32 get_core_cap_flags(struct ib_device *ibdev) 2781 { 2782 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2783 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2784 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2785 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2786 u32 ret = 0; 2787 2788 if (ll == IB_LINK_LAYER_INFINIBAND) 2789 return RDMA_CORE_PORT_IBA_IB; 2790 2791 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2792 return 0; 2793 2794 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2795 return 0; 2796 2797 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2798 ret |= RDMA_CORE_PORT_IBA_ROCE; 2799 2800 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2801 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2802 2803 return ret; 2804 } 2805 2806 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2807 struct ib_port_immutable *immutable) 2808 { 2809 struct ib_port_attr attr; 2810 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2811 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2812 int err; 2813 2814 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2815 if (err) 2816 return err; 2817 2818 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2819 immutable->gid_tbl_len = attr.gid_tbl_len; 2820 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2821 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 2822 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2823 2824 return 0; 2825 } 2826 2827 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2828 size_t str_len) 2829 { 2830 struct mlx5_ib_dev *dev = 2831 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2832 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2833 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2834 } 2835 2836 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2837 { 2838 struct mlx5_core_dev *mdev = dev->mdev; 2839 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2840 MLX5_FLOW_NAMESPACE_LAG); 2841 struct mlx5_flow_table *ft; 2842 int err; 2843 2844 if (!ns || !mlx5_lag_is_active(mdev)) 2845 return 0; 2846 2847 err = mlx5_cmd_create_vport_lag(mdev); 2848 if (err) 2849 return err; 2850 2851 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 2852 if (IS_ERR(ft)) { 2853 err = PTR_ERR(ft); 2854 goto err_destroy_vport_lag; 2855 } 2856 2857 dev->flow_db.lag_demux_ft = ft; 2858 return 0; 2859 2860 err_destroy_vport_lag: 2861 mlx5_cmd_destroy_vport_lag(mdev); 2862 return err; 2863 } 2864 2865 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 2866 { 2867 struct mlx5_core_dev *mdev = dev->mdev; 2868 2869 if (dev->flow_db.lag_demux_ft) { 2870 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 2871 dev->flow_db.lag_demux_ft = NULL; 2872 2873 mlx5_cmd_destroy_vport_lag(mdev); 2874 } 2875 } 2876 2877 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 2878 { 2879 int err; 2880 2881 dev->roce.nb.notifier_call = mlx5_netdev_event; 2882 err = register_netdevice_notifier(&dev->roce.nb); 2883 if (err) { 2884 dev->roce.nb.notifier_call = NULL; 2885 return err; 2886 } 2887 2888 return 0; 2889 } 2890 2891 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 2892 { 2893 if (dev->roce.nb.notifier_call) { 2894 unregister_netdevice_notifier(&dev->roce.nb); 2895 dev->roce.nb.notifier_call = NULL; 2896 } 2897 } 2898 2899 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 2900 { 2901 int err; 2902 2903 err = mlx5_add_netdev_notifier(dev); 2904 if (err) 2905 return err; 2906 2907 if (MLX5_CAP_GEN(dev->mdev, roce)) { 2908 err = mlx5_nic_vport_enable_roce(dev->mdev); 2909 if (err) 2910 goto err_unregister_netdevice_notifier; 2911 } 2912 2913 err = mlx5_eth_lag_init(dev); 2914 if (err) 2915 goto err_disable_roce; 2916 2917 return 0; 2918 2919 err_disable_roce: 2920 if (MLX5_CAP_GEN(dev->mdev, roce)) 2921 mlx5_nic_vport_disable_roce(dev->mdev); 2922 2923 err_unregister_netdevice_notifier: 2924 mlx5_remove_netdev_notifier(dev); 2925 return err; 2926 } 2927 2928 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 2929 { 2930 mlx5_eth_lag_cleanup(dev); 2931 if (MLX5_CAP_GEN(dev->mdev, roce)) 2932 mlx5_nic_vport_disable_roce(dev->mdev); 2933 } 2934 2935 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2936 { 2937 unsigned int i; 2938 2939 for (i = 0; i < dev->num_ports; i++) 2940 mlx5_core_dealloc_q_counter(dev->mdev, 2941 dev->port[i].q_cnt_id); 2942 } 2943 2944 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2945 { 2946 int i; 2947 int ret; 2948 2949 for (i = 0; i < dev->num_ports; i++) { 2950 ret = mlx5_core_alloc_q_counter(dev->mdev, 2951 &dev->port[i].q_cnt_id); 2952 if (ret) { 2953 mlx5_ib_warn(dev, 2954 "couldn't allocate queue counter for port %d, err %d\n", 2955 i + 1, ret); 2956 goto dealloc_counters; 2957 } 2958 } 2959 2960 return 0; 2961 2962 dealloc_counters: 2963 while (--i >= 0) 2964 mlx5_core_dealloc_q_counter(dev->mdev, 2965 dev->port[i].q_cnt_id); 2966 2967 return ret; 2968 } 2969 2970 static const char * const names[] = { 2971 "rx_write_requests", 2972 "rx_read_requests", 2973 "rx_atomic_requests", 2974 "out_of_buffer", 2975 "out_of_sequence", 2976 "duplicate_request", 2977 "rnr_nak_retry_err", 2978 "packet_seq_err", 2979 "implied_nak_seq_err", 2980 "local_ack_timeout_err", 2981 }; 2982 2983 static const size_t stats_offsets[] = { 2984 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 2985 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 2986 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 2987 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 2988 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 2989 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 2990 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 2991 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 2992 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 2993 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 2994 }; 2995 2996 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 2997 u8 port_num) 2998 { 2999 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3000 3001 /* We support only per port stats */ 3002 if (port_num == 0) 3003 return NULL; 3004 3005 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3006 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3007 } 3008 3009 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3010 struct rdma_hw_stats *stats, 3011 u8 port, int index) 3012 { 3013 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3014 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3015 void *out; 3016 __be32 val; 3017 int ret; 3018 int i; 3019 3020 if (!port || !stats) 3021 return -ENOSYS; 3022 3023 out = mlx5_vzalloc(outlen); 3024 if (!out) 3025 return -ENOMEM; 3026 3027 ret = mlx5_core_query_q_counter(dev->mdev, 3028 dev->port[port - 1].q_cnt_id, 0, 3029 out, outlen); 3030 if (ret) 3031 goto free; 3032 3033 for (i = 0; i < ARRAY_SIZE(names); i++) { 3034 val = *(__be32 *)(out + stats_offsets[i]); 3035 stats->value[i] = (u64)be32_to_cpu(val); 3036 } 3037 free: 3038 kvfree(out); 3039 return ARRAY_SIZE(names); 3040 } 3041 3042 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3043 { 3044 struct mlx5_ib_dev *dev; 3045 enum rdma_link_layer ll; 3046 int port_type_cap; 3047 const char *name; 3048 int err; 3049 int i; 3050 3051 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3052 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3053 3054 printk_once(KERN_INFO "%s", mlx5_version); 3055 3056 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3057 if (!dev) 3058 return NULL; 3059 3060 dev->mdev = mdev; 3061 3062 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3063 GFP_KERNEL); 3064 if (!dev->port) 3065 goto err_dealloc; 3066 3067 rwlock_init(&dev->roce.netdev_lock); 3068 err = get_port_caps(dev); 3069 if (err) 3070 goto err_free_port; 3071 3072 if (mlx5_use_mad_ifc(dev)) 3073 get_ext_port_caps(dev); 3074 3075 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3076 3077 if (!mlx5_lag_is_active(mdev)) 3078 name = "mlx5_%d"; 3079 else 3080 name = "mlx5_bond_%d"; 3081 3082 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3083 dev->ib_dev.owner = THIS_MODULE; 3084 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3085 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3086 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3087 dev->ib_dev.phys_port_cnt = dev->num_ports; 3088 dev->ib_dev.num_comp_vectors = 3089 dev->mdev->priv.eq_table.num_comp_vectors; 3090 dev->ib_dev.dma_device = &mdev->pdev->dev; 3091 3092 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3093 dev->ib_dev.uverbs_cmd_mask = 3094 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3095 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3096 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3097 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3098 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3099 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3100 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3101 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3102 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3103 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3104 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3105 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3106 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3107 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3108 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3109 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3110 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3111 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3112 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3113 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3114 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3115 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3116 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3117 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3118 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3119 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3120 dev->ib_dev.uverbs_ex_cmd_mask = 3121 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3122 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3123 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3124 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3125 3126 dev->ib_dev.query_device = mlx5_ib_query_device; 3127 dev->ib_dev.query_port = mlx5_ib_query_port; 3128 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3129 if (ll == IB_LINK_LAYER_ETHERNET) 3130 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3131 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3132 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3133 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3134 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3135 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3136 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3137 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3138 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3139 dev->ib_dev.mmap = mlx5_ib_mmap; 3140 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3141 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3142 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3143 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3144 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3145 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3146 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3147 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3148 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3149 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3150 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3151 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3152 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3153 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3154 dev->ib_dev.post_send = mlx5_ib_post_send; 3155 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3156 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3157 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3158 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3159 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3160 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3161 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3162 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3163 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3164 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3165 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3166 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3167 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3168 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3169 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3170 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3171 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3172 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3173 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3174 if (mlx5_core_is_pf(mdev)) { 3175 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3176 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3177 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3178 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3179 } 3180 3181 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3182 3183 mlx5_ib_internal_fill_odp_caps(dev); 3184 3185 if (MLX5_CAP_GEN(mdev, imaicl)) { 3186 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3187 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3188 dev->ib_dev.uverbs_cmd_mask |= 3189 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3190 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3191 } 3192 3193 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3194 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3195 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3196 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3197 } 3198 3199 if (MLX5_CAP_GEN(mdev, xrc)) { 3200 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3201 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3202 dev->ib_dev.uverbs_cmd_mask |= 3203 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3204 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3205 } 3206 3207 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3208 IB_LINK_LAYER_ETHERNET) { 3209 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3210 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3211 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3212 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3213 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3214 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3215 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3216 dev->ib_dev.uverbs_ex_cmd_mask |= 3217 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3218 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3219 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3220 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3221 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3222 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3223 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3224 } 3225 err = init_node_data(dev); 3226 if (err) 3227 goto err_free_port; 3228 3229 mutex_init(&dev->flow_db.lock); 3230 mutex_init(&dev->cap_mask_mutex); 3231 INIT_LIST_HEAD(&dev->qp_list); 3232 spin_lock_init(&dev->reset_flow_resource_lock); 3233 3234 if (ll == IB_LINK_LAYER_ETHERNET) { 3235 err = mlx5_enable_eth(dev); 3236 if (err) 3237 goto err_free_port; 3238 } 3239 3240 err = create_dev_resources(&dev->devr); 3241 if (err) 3242 goto err_disable_eth; 3243 3244 err = mlx5_ib_odp_init_one(dev); 3245 if (err) 3246 goto err_rsrc; 3247 3248 err = mlx5_ib_alloc_q_counters(dev); 3249 if (err) 3250 goto err_odp; 3251 3252 err = ib_register_device(&dev->ib_dev, NULL); 3253 if (err) 3254 goto err_q_cnt; 3255 3256 err = create_umr_res(dev); 3257 if (err) 3258 goto err_dev; 3259 3260 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3261 err = device_create_file(&dev->ib_dev.dev, 3262 mlx5_class_attributes[i]); 3263 if (err) 3264 goto err_umrc; 3265 } 3266 3267 dev->ib_active = true; 3268 3269 return dev; 3270 3271 err_umrc: 3272 destroy_umrc_res(dev); 3273 3274 err_dev: 3275 ib_unregister_device(&dev->ib_dev); 3276 3277 err_q_cnt: 3278 mlx5_ib_dealloc_q_counters(dev); 3279 3280 err_odp: 3281 mlx5_ib_odp_remove_one(dev); 3282 3283 err_rsrc: 3284 destroy_dev_resources(&dev->devr); 3285 3286 err_disable_eth: 3287 if (ll == IB_LINK_LAYER_ETHERNET) { 3288 mlx5_disable_eth(dev); 3289 mlx5_remove_netdev_notifier(dev); 3290 } 3291 3292 err_free_port: 3293 kfree(dev->port); 3294 3295 err_dealloc: 3296 ib_dealloc_device((struct ib_device *)dev); 3297 3298 return NULL; 3299 } 3300 3301 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3302 { 3303 struct mlx5_ib_dev *dev = context; 3304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3305 3306 mlx5_remove_netdev_notifier(dev); 3307 ib_unregister_device(&dev->ib_dev); 3308 mlx5_ib_dealloc_q_counters(dev); 3309 destroy_umrc_res(dev); 3310 mlx5_ib_odp_remove_one(dev); 3311 destroy_dev_resources(&dev->devr); 3312 if (ll == IB_LINK_LAYER_ETHERNET) 3313 mlx5_disable_eth(dev); 3314 kfree(dev->port); 3315 ib_dealloc_device(&dev->ib_dev); 3316 } 3317 3318 static struct mlx5_interface mlx5_ib_interface = { 3319 .add = mlx5_ib_add, 3320 .remove = mlx5_ib_remove, 3321 .event = mlx5_ib_event, 3322 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3323 .pfault = mlx5_ib_pfault, 3324 #endif 3325 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3326 }; 3327 3328 static int __init mlx5_ib_init(void) 3329 { 3330 int err; 3331 3332 if (deprecated_prof_sel != 2) 3333 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 3334 3335 err = mlx5_register_interface(&mlx5_ib_interface); 3336 3337 return err; 3338 } 3339 3340 static void __exit mlx5_ib_cleanup(void) 3341 { 3342 mlx5_unregister_interface(&mlx5_ib_interface); 3343 } 3344 3345 module_init(mlx5_ib_init); 3346 module_exit(mlx5_ib_cleanup); 3347