1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/mlx5/driver.h> 28 #include <linux/list.h> 29 #include <rdma/ib_smi.h> 30 #include <rdma/ib_umem_odp.h> 31 #include <rdma/lag.h> 32 #include <linux/in.h> 33 #include <linux/etherdevice.h> 34 #include "mlx5_ib.h" 35 #include "ib_rep.h" 36 #include "cmd.h" 37 #include "devx.h" 38 #include "dm.h" 39 #include "fs.h" 40 #include "srq.h" 41 #include "qp.h" 42 #include "wr.h" 43 #include "restrack.h" 44 #include "counters.h" 45 #include "umr.h" 46 #include <rdma/uverbs_std_types.h> 47 #include <rdma/uverbs_ioctl.h> 48 #include <rdma/mlx5_user_ioctl_verbs.h> 49 #include <rdma/mlx5_user_ioctl_cmds.h> 50 #include "macsec.h" 51 52 #define UVERBS_MODULE_NAME mlx5_ib 53 #include <rdma/uverbs_named_ioctl.h> 54 55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 56 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 57 MODULE_LICENSE("Dual BSD/GPL"); 58 59 struct mlx5_ib_event_work { 60 struct work_struct work; 61 union { 62 struct mlx5_ib_dev *dev; 63 struct mlx5_ib_multiport_info *mpi; 64 }; 65 bool is_slave; 66 unsigned int event; 67 void *param; 68 }; 69 70 enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72 }; 73 74 static struct workqueue_struct *mlx5_ib_event_wq; 75 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 76 static LIST_HEAD(mlx5_ib_dev_list); 77 /* 78 * This mutex should be held when accessing either of the above lists 79 */ 80 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 81 82 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 83 { 84 struct mlx5_ib_dev *dev; 85 86 mutex_lock(&mlx5_ib_multiport_mutex); 87 dev = mpi->ibdev; 88 mutex_unlock(&mlx5_ib_multiport_mutex); 89 return dev; 90 } 91 92 static enum rdma_link_layer 93 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 94 { 95 switch (port_type_cap) { 96 case MLX5_CAP_PORT_TYPE_IB: 97 return IB_LINK_LAYER_INFINIBAND; 98 case MLX5_CAP_PORT_TYPE_ETH: 99 return IB_LINK_LAYER_ETHERNET; 100 default: 101 return IB_LINK_LAYER_UNSPECIFIED; 102 } 103 } 104 105 static enum rdma_link_layer 106 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 107 { 108 struct mlx5_ib_dev *dev = to_mdev(device); 109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 110 111 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 112 } 113 114 static int get_port_state(struct ib_device *ibdev, 115 u32 port_num, 116 enum ib_port_state *state) 117 { 118 struct ib_port_attr attr; 119 int ret; 120 121 memset(&attr, 0, sizeof(attr)); 122 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 123 if (!ret) 124 *state = attr.state; 125 return ret; 126 } 127 128 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 129 struct net_device *ndev, 130 struct net_device *upper, 131 u32 *port_num) 132 { 133 struct net_device *rep_ndev; 134 struct mlx5_ib_port *port; 135 int i; 136 137 for (i = 0; i < dev->num_ports; i++) { 138 port = &dev->port[i]; 139 if (!port->rep) 140 continue; 141 142 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 143 *port_num = i + 1; 144 return &port->roce; 145 } 146 147 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 148 continue; 149 150 read_lock(&port->roce.netdev_lock); 151 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 152 port->rep->vport); 153 if (rep_ndev == ndev) { 154 read_unlock(&port->roce.netdev_lock); 155 *port_num = i + 1; 156 return &port->roce; 157 } 158 read_unlock(&port->roce.netdev_lock); 159 } 160 161 return NULL; 162 } 163 164 static int mlx5_netdev_event(struct notifier_block *this, 165 unsigned long event, void *ptr) 166 { 167 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 168 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 169 u32 port_num = roce->native_port_num; 170 struct mlx5_core_dev *mdev; 171 struct mlx5_ib_dev *ibdev; 172 173 ibdev = roce->dev; 174 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 175 if (!mdev) 176 return NOTIFY_DONE; 177 178 switch (event) { 179 case NETDEV_REGISTER: 180 /* Should already be registered during the load */ 181 if (ibdev->is_rep) 182 break; 183 write_lock(&roce->netdev_lock); 184 if (ndev->dev.parent == mdev->device) 185 roce->netdev = ndev; 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_UNREGISTER: 190 /* In case of reps, ib device goes away before the netdevs */ 191 write_lock(&roce->netdev_lock); 192 if (roce->netdev == ndev) 193 roce->netdev = NULL; 194 write_unlock(&roce->netdev_lock); 195 break; 196 197 case NETDEV_CHANGE: 198 case NETDEV_UP: 199 case NETDEV_DOWN: { 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 201 struct net_device *upper = NULL; 202 203 if (lag_ndev) { 204 upper = netdev_master_upper_dev_get(lag_ndev); 205 dev_put(lag_ndev); 206 } 207 208 if (ibdev->is_rep) 209 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 210 if (!roce) 211 return NOTIFY_DONE; 212 if ((upper == ndev || 213 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 214 ibdev->ib_active) { 215 struct ib_event ibev = { }; 216 enum ib_port_state port_state; 217 218 if (get_port_state(&ibdev->ib_dev, port_num, 219 &port_state)) 220 goto done; 221 222 if (roce->last_port_state == port_state) 223 goto done; 224 225 roce->last_port_state = port_state; 226 ibev.device = &ibdev->ib_dev; 227 if (port_state == IB_PORT_DOWN) 228 ibev.event = IB_EVENT_PORT_ERR; 229 else if (port_state == IB_PORT_ACTIVE) 230 ibev.event = IB_EVENT_PORT_ACTIVE; 231 else 232 goto done; 233 234 ibev.element.port_num = port_num; 235 ib_dispatch_event(&ibev); 236 } 237 break; 238 } 239 240 default: 241 break; 242 } 243 done: 244 mlx5_ib_put_native_port_mdev(ibdev, port_num); 245 return NOTIFY_DONE; 246 } 247 248 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 249 u32 port_num) 250 { 251 struct mlx5_ib_dev *ibdev = to_mdev(device); 252 struct net_device *ndev; 253 struct mlx5_core_dev *mdev; 254 255 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 256 if (!mdev) 257 return NULL; 258 259 ndev = mlx5_lag_get_roce_netdev(mdev); 260 if (ndev) 261 goto out; 262 263 /* Ensure ndev does not disappear before we invoke dev_hold() 264 */ 265 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 266 ndev = ibdev->port[port_num - 1].roce.netdev; 267 if (ndev) 268 dev_hold(ndev); 269 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 270 271 out: 272 mlx5_ib_put_native_port_mdev(ibdev, port_num); 273 return ndev; 274 } 275 276 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 277 u32 ib_port_num, 278 u32 *native_port_num) 279 { 280 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 281 ib_port_num); 282 struct mlx5_core_dev *mdev = NULL; 283 struct mlx5_ib_multiport_info *mpi; 284 struct mlx5_ib_port *port; 285 286 if (!mlx5_core_mp_enabled(ibdev->mdev) || 287 ll != IB_LINK_LAYER_ETHERNET) { 288 if (native_port_num) 289 *native_port_num = ib_port_num; 290 return ibdev->mdev; 291 } 292 293 if (native_port_num) 294 *native_port_num = 1; 295 296 port = &ibdev->port[ib_port_num - 1]; 297 spin_lock(&port->mp.mpi_lock); 298 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 299 if (mpi && !mpi->unaffiliate) { 300 mdev = mpi->mdev; 301 /* If it's the master no need to refcount, it'll exist 302 * as long as the ib_dev exists. 303 */ 304 if (!mpi->is_master) 305 mpi->mdev_refcnt++; 306 } 307 spin_unlock(&port->mp.mpi_lock); 308 309 return mdev; 310 } 311 312 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 313 { 314 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 315 port_num); 316 struct mlx5_ib_multiport_info *mpi; 317 struct mlx5_ib_port *port; 318 319 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 320 return; 321 322 port = &ibdev->port[port_num - 1]; 323 324 spin_lock(&port->mp.mpi_lock); 325 mpi = ibdev->port[port_num - 1].mp.mpi; 326 if (mpi->is_master) 327 goto out; 328 329 mpi->mdev_refcnt--; 330 if (mpi->unaffiliate) 331 complete(&mpi->unref_comp); 332 out: 333 spin_unlock(&port->mp.mpi_lock); 334 } 335 336 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 337 u16 *active_speed, u8 *active_width) 338 { 339 switch (eth_proto_oper) { 340 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 342 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 343 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_SDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 352 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 353 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 354 *active_width = IB_WIDTH_1X; 355 *active_speed = IB_SPEED_QDR; 356 break; 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 358 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 359 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 360 *active_width = IB_WIDTH_1X; 361 *active_speed = IB_SPEED_EDR; 362 break; 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 365 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 366 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_QDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 371 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 372 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 373 *active_width = IB_WIDTH_1X; 374 *active_speed = IB_SPEED_HDR; 375 break; 376 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 377 *active_width = IB_WIDTH_4X; 378 *active_speed = IB_SPEED_FDR; 379 break; 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 382 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 383 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 384 *active_width = IB_WIDTH_4X; 385 *active_speed = IB_SPEED_EDR; 386 break; 387 default: 388 return -EINVAL; 389 } 390 391 return 0; 392 } 393 394 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 395 u8 *active_width) 396 { 397 switch (eth_proto_oper) { 398 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 399 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 400 *active_width = IB_WIDTH_1X; 401 *active_speed = IB_SPEED_SDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_DDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 408 *active_width = IB_WIDTH_1X; 409 *active_speed = IB_SPEED_QDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 412 *active_width = IB_WIDTH_4X; 413 *active_speed = IB_SPEED_QDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 416 *active_width = IB_WIDTH_1X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_EDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_HDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_EDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_HDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 436 *active_width = IB_WIDTH_1X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 440 *active_width = IB_WIDTH_4X; 441 *active_speed = IB_SPEED_HDR; 442 break; 443 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 444 *active_width = IB_WIDTH_2X; 445 *active_speed = IB_SPEED_NDR; 446 break; 447 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 448 *active_width = IB_WIDTH_8X; 449 *active_speed = IB_SPEED_HDR; 450 break; 451 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 452 *active_width = IB_WIDTH_4X; 453 *active_speed = IB_SPEED_NDR; 454 break; 455 default: 456 return -EINVAL; 457 } 458 459 return 0; 460 } 461 462 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 463 u8 *active_width, bool ext) 464 { 465 return ext ? 466 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 467 active_width) : 468 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 469 active_width); 470 } 471 472 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 473 struct ib_port_attr *props) 474 { 475 struct mlx5_ib_dev *dev = to_mdev(device); 476 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 477 struct mlx5_core_dev *mdev; 478 struct net_device *ndev, *upper; 479 enum ib_mtu ndev_ib_mtu; 480 bool put_mdev = true; 481 u32 eth_prot_oper; 482 u32 mdev_port_num; 483 bool ext; 484 int err; 485 486 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 487 if (!mdev) { 488 /* This means the port isn't affiliated yet. Get the 489 * info for the master port instead. 490 */ 491 put_mdev = false; 492 mdev = dev->mdev; 493 mdev_port_num = 1; 494 port_num = 1; 495 } 496 497 /* Possible bad flows are checked before filling out props so in case 498 * of an error it will still be zeroed out. 499 * Use native port in case of reps 500 */ 501 if (dev->is_rep) 502 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 503 1); 504 else 505 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 506 mdev_port_num); 507 if (err) 508 goto out; 509 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 510 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 511 512 props->active_width = IB_WIDTH_4X; 513 props->active_speed = IB_SPEED_QDR; 514 515 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 516 &props->active_width, ext); 517 518 if (!dev->is_rep && dev->mdev->roce.roce_en) { 519 u16 qkey_viol_cntr; 520 521 props->port_cap_flags |= IB_PORT_CM_SUP; 522 props->ip_gids = true; 523 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 524 roce_address_table_size); 525 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 526 props->qkey_viol_cntr = qkey_viol_cntr; 527 } 528 props->max_mtu = IB_MTU_4096; 529 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 530 props->pkey_tbl_len = 1; 531 props->state = IB_PORT_DOWN; 532 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 533 534 /* If this is a stub query for an unaffiliated port stop here */ 535 if (!put_mdev) 536 goto out; 537 538 ndev = mlx5_ib_get_netdev(device, port_num); 539 if (!ndev) 540 goto out; 541 542 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 543 rcu_read_lock(); 544 upper = netdev_master_upper_dev_get_rcu(ndev); 545 if (upper) { 546 dev_put(ndev); 547 ndev = upper; 548 dev_hold(ndev); 549 } 550 rcu_read_unlock(); 551 } 552 553 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 554 props->state = IB_PORT_ACTIVE; 555 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 556 } 557 558 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 559 560 dev_put(ndev); 561 562 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 563 out: 564 if (put_mdev) 565 mlx5_ib_put_native_port_mdev(dev, port_num); 566 return err; 567 } 568 569 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 570 unsigned int index, const union ib_gid *gid, 571 const struct ib_gid_attr *attr) 572 { 573 enum ib_gid_type gid_type; 574 u16 vlan_id = 0xffff; 575 u8 roce_version = 0; 576 u8 roce_l3_type = 0; 577 u8 mac[ETH_ALEN]; 578 int ret; 579 580 gid_type = attr->gid_type; 581 if (gid) { 582 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 583 if (ret) 584 return ret; 585 } 586 587 switch (gid_type) { 588 case IB_GID_TYPE_ROCE: 589 roce_version = MLX5_ROCE_VERSION_1; 590 break; 591 case IB_GID_TYPE_ROCE_UDP_ENCAP: 592 roce_version = MLX5_ROCE_VERSION_2; 593 if (gid && ipv6_addr_v4mapped((void *)gid)) 594 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 595 else 596 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 597 break; 598 599 default: 600 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 601 } 602 603 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 604 roce_l3_type, gid->raw, mac, 605 vlan_id < VLAN_CFI_MASK, vlan_id, 606 port_num); 607 } 608 609 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 610 __always_unused void **context) 611 { 612 int ret; 613 614 ret = mlx5r_add_gid_macsec_operations(attr); 615 if (ret) 616 return ret; 617 618 return set_roce_addr(to_mdev(attr->device), attr->port_num, 619 attr->index, &attr->gid, attr); 620 } 621 622 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 623 __always_unused void **context) 624 { 625 int ret; 626 627 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 628 attr->index, NULL, attr); 629 if (ret) 630 return ret; 631 632 mlx5r_del_gid_macsec_operations(attr); 633 return 0; 634 } 635 636 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 637 const struct ib_gid_attr *attr) 638 { 639 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 640 return 0; 641 642 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 643 } 644 645 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 646 { 647 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 648 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 649 return 0; 650 } 651 652 enum { 653 MLX5_VPORT_ACCESS_METHOD_MAD, 654 MLX5_VPORT_ACCESS_METHOD_HCA, 655 MLX5_VPORT_ACCESS_METHOD_NIC, 656 }; 657 658 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 659 { 660 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 661 return MLX5_VPORT_ACCESS_METHOD_MAD; 662 663 if (mlx5_ib_port_link_layer(ibdev, 1) == 664 IB_LINK_LAYER_ETHERNET) 665 return MLX5_VPORT_ACCESS_METHOD_NIC; 666 667 return MLX5_VPORT_ACCESS_METHOD_HCA; 668 } 669 670 static void get_atomic_caps(struct mlx5_ib_dev *dev, 671 u8 atomic_size_qp, 672 struct ib_device_attr *props) 673 { 674 u8 tmp; 675 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 676 u8 atomic_req_8B_endianness_mode = 677 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 678 679 /* Check if HW supports 8 bytes standard atomic operations and capable 680 * of host endianness respond 681 */ 682 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 683 if (((atomic_operations & tmp) == tmp) && 684 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 685 (atomic_req_8B_endianness_mode)) { 686 props->atomic_cap = IB_ATOMIC_HCA; 687 } else { 688 props->atomic_cap = IB_ATOMIC_NONE; 689 } 690 } 691 692 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 693 struct ib_device_attr *props) 694 { 695 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 696 697 get_atomic_caps(dev, atomic_size_qp, props); 698 } 699 700 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 701 __be64 *sys_image_guid) 702 { 703 struct mlx5_ib_dev *dev = to_mdev(ibdev); 704 struct mlx5_core_dev *mdev = dev->mdev; 705 u64 tmp; 706 int err; 707 708 switch (mlx5_get_vport_access_method(ibdev)) { 709 case MLX5_VPORT_ACCESS_METHOD_MAD: 710 return mlx5_query_mad_ifc_system_image_guid(ibdev, 711 sys_image_guid); 712 713 case MLX5_VPORT_ACCESS_METHOD_HCA: 714 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 715 break; 716 717 case MLX5_VPORT_ACCESS_METHOD_NIC: 718 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 719 break; 720 721 default: 722 return -EINVAL; 723 } 724 725 if (!err) 726 *sys_image_guid = cpu_to_be64(tmp); 727 728 return err; 729 730 } 731 732 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 733 u16 *max_pkeys) 734 { 735 struct mlx5_ib_dev *dev = to_mdev(ibdev); 736 struct mlx5_core_dev *mdev = dev->mdev; 737 738 switch (mlx5_get_vport_access_method(ibdev)) { 739 case MLX5_VPORT_ACCESS_METHOD_MAD: 740 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 741 742 case MLX5_VPORT_ACCESS_METHOD_HCA: 743 case MLX5_VPORT_ACCESS_METHOD_NIC: 744 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 745 pkey_table_size)); 746 return 0; 747 748 default: 749 return -EINVAL; 750 } 751 } 752 753 static int mlx5_query_vendor_id(struct ib_device *ibdev, 754 u32 *vendor_id) 755 { 756 struct mlx5_ib_dev *dev = to_mdev(ibdev); 757 758 switch (mlx5_get_vport_access_method(ibdev)) { 759 case MLX5_VPORT_ACCESS_METHOD_MAD: 760 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 761 762 case MLX5_VPORT_ACCESS_METHOD_HCA: 763 case MLX5_VPORT_ACCESS_METHOD_NIC: 764 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 765 766 default: 767 return -EINVAL; 768 } 769 } 770 771 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 772 __be64 *node_guid) 773 { 774 u64 tmp; 775 int err; 776 777 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 778 case MLX5_VPORT_ACCESS_METHOD_MAD: 779 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 780 781 case MLX5_VPORT_ACCESS_METHOD_HCA: 782 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 783 break; 784 785 case MLX5_VPORT_ACCESS_METHOD_NIC: 786 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 787 break; 788 789 default: 790 return -EINVAL; 791 } 792 793 if (!err) 794 *node_guid = cpu_to_be64(tmp); 795 796 return err; 797 } 798 799 struct mlx5_reg_node_desc { 800 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 801 }; 802 803 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 804 { 805 struct mlx5_reg_node_desc in; 806 807 if (mlx5_use_mad_ifc(dev)) 808 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 809 810 memset(&in, 0, sizeof(in)); 811 812 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 813 sizeof(struct mlx5_reg_node_desc), 814 MLX5_REG_NODE_DESC, 0, 0); 815 } 816 817 static int mlx5_ib_query_device(struct ib_device *ibdev, 818 struct ib_device_attr *props, 819 struct ib_udata *uhw) 820 { 821 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 822 struct mlx5_ib_dev *dev = to_mdev(ibdev); 823 struct mlx5_core_dev *mdev = dev->mdev; 824 int err = -ENOMEM; 825 int max_sq_desc; 826 int max_rq_sg; 827 int max_sq_sg; 828 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 829 bool raw_support = !mlx5_core_mp_enabled(mdev); 830 struct mlx5_ib_query_device_resp resp = {}; 831 size_t resp_len; 832 u64 max_tso; 833 834 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 835 if (uhw_outlen && uhw_outlen < resp_len) 836 return -EINVAL; 837 838 resp.response_length = resp_len; 839 840 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 841 return -EINVAL; 842 843 memset(props, 0, sizeof(*props)); 844 err = mlx5_query_system_image_guid(ibdev, 845 &props->sys_image_guid); 846 if (err) 847 return err; 848 849 props->max_pkeys = dev->pkey_table_len; 850 851 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 852 if (err) 853 return err; 854 855 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 856 (fw_rev_min(dev->mdev) << 16) | 857 fw_rev_sub(dev->mdev); 858 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 859 IB_DEVICE_PORT_ACTIVE_EVENT | 860 IB_DEVICE_SYS_IMAGE_GUID | 861 IB_DEVICE_RC_RNR_NAK_GEN; 862 863 if (MLX5_CAP_GEN(mdev, pkv)) 864 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 865 if (MLX5_CAP_GEN(mdev, qkv)) 866 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 867 if (MLX5_CAP_GEN(mdev, apm)) 868 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 869 if (MLX5_CAP_GEN(mdev, xrc)) 870 props->device_cap_flags |= IB_DEVICE_XRC; 871 if (MLX5_CAP_GEN(mdev, imaicl)) { 872 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 873 IB_DEVICE_MEM_WINDOW_TYPE_2B; 874 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 875 /* We support 'Gappy' memory registration too */ 876 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 877 } 878 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 879 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 880 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 881 if (MLX5_CAP_GEN(mdev, sho)) { 882 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 883 /* At this stage no support for signature handover */ 884 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 885 IB_PROT_T10DIF_TYPE_2 | 886 IB_PROT_T10DIF_TYPE_3; 887 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 888 IB_GUARD_T10DIF_CSUM; 889 } 890 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 891 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 892 893 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 894 if (MLX5_CAP_ETH(mdev, csum_cap)) { 895 /* Legacy bit to support old userspace libraries */ 896 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 897 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 898 } 899 900 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 901 props->raw_packet_caps |= 902 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 903 904 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 905 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 906 if (max_tso) { 907 resp.tso_caps.max_tso = 1 << max_tso; 908 resp.tso_caps.supported_qpts |= 909 1 << IB_QPT_RAW_PACKET; 910 resp.response_length += sizeof(resp.tso_caps); 911 } 912 } 913 914 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 915 resp.rss_caps.rx_hash_function = 916 MLX5_RX_HASH_FUNC_TOEPLITZ; 917 resp.rss_caps.rx_hash_fields_mask = 918 MLX5_RX_HASH_SRC_IPV4 | 919 MLX5_RX_HASH_DST_IPV4 | 920 MLX5_RX_HASH_SRC_IPV6 | 921 MLX5_RX_HASH_DST_IPV6 | 922 MLX5_RX_HASH_SRC_PORT_TCP | 923 MLX5_RX_HASH_DST_PORT_TCP | 924 MLX5_RX_HASH_SRC_PORT_UDP | 925 MLX5_RX_HASH_DST_PORT_UDP | 926 MLX5_RX_HASH_INNER; 927 resp.response_length += sizeof(resp.rss_caps); 928 } 929 } else { 930 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 931 resp.response_length += sizeof(resp.tso_caps); 932 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 933 resp.response_length += sizeof(resp.rss_caps); 934 } 935 936 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 937 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 938 props->kernel_cap_flags |= IBK_UD_TSO; 939 } 940 941 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 942 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 943 raw_support) 944 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 945 946 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 947 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 948 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 949 950 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 951 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 952 raw_support) { 953 /* Legacy bit to support old userspace libraries */ 954 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 955 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 956 } 957 958 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 959 props->max_dm_size = 960 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 961 } 962 963 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 964 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 965 966 if (MLX5_CAP_GEN(mdev, end_pad)) 967 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 968 969 props->vendor_part_id = mdev->pdev->device; 970 props->hw_ver = mdev->pdev->revision; 971 972 props->max_mr_size = ~0ull; 973 props->page_size_cap = ~(min_page_size - 1); 974 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 975 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 976 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 977 sizeof(struct mlx5_wqe_data_seg); 978 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 979 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 980 sizeof(struct mlx5_wqe_raddr_seg)) / 981 sizeof(struct mlx5_wqe_data_seg); 982 props->max_send_sge = max_sq_sg; 983 props->max_recv_sge = max_rq_sg; 984 props->max_sge_rd = MLX5_MAX_SGE_RD; 985 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 986 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 987 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 988 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 989 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 990 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 991 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 992 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 993 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 994 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 995 props->max_srq_sge = max_rq_sg - 1; 996 props->max_fast_reg_page_list_len = 997 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 998 props->max_pi_fast_reg_page_list_len = 999 props->max_fast_reg_page_list_len / 2; 1000 props->max_sgl_rd = 1001 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1002 get_atomic_caps_qp(dev, props); 1003 props->masked_atomic_cap = IB_ATOMIC_NONE; 1004 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1005 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1006 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1007 props->max_mcast_grp; 1008 props->max_ah = INT_MAX; 1009 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1010 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1011 1012 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1013 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1014 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1015 props->odp_caps = dev->odp_caps; 1016 if (!uhw) { 1017 /* ODP for kernel QPs is not implemented for receive 1018 * WQEs and SRQ WQEs 1019 */ 1020 props->odp_caps.per_transport_caps.rc_odp_caps &= 1021 ~(IB_ODP_SUPPORT_READ | 1022 IB_ODP_SUPPORT_SRQ_RECV); 1023 props->odp_caps.per_transport_caps.uc_odp_caps &= 1024 ~(IB_ODP_SUPPORT_READ | 1025 IB_ODP_SUPPORT_SRQ_RECV); 1026 props->odp_caps.per_transport_caps.ud_odp_caps &= 1027 ~(IB_ODP_SUPPORT_READ | 1028 IB_ODP_SUPPORT_SRQ_RECV); 1029 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1030 ~(IB_ODP_SUPPORT_READ | 1031 IB_ODP_SUPPORT_SRQ_RECV); 1032 } 1033 } 1034 1035 if (mlx5_core_is_vf(mdev)) 1036 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1037 1038 if (mlx5_ib_port_link_layer(ibdev, 1) == 1039 IB_LINK_LAYER_ETHERNET && raw_support) { 1040 props->rss_caps.max_rwq_indirection_tables = 1041 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1042 props->rss_caps.max_rwq_indirection_table_size = 1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1044 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1045 props->max_wq_type_rq = 1046 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1047 } 1048 1049 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1050 props->tm_caps.max_num_tags = 1051 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1052 props->tm_caps.max_ops = 1053 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1054 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1055 } 1056 1057 if (MLX5_CAP_GEN(mdev, tag_matching) && 1058 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1059 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1060 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1061 } 1062 1063 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1064 props->cq_caps.max_cq_moderation_count = 1065 MLX5_MAX_CQ_COUNT; 1066 props->cq_caps.max_cq_moderation_period = 1067 MLX5_MAX_CQ_PERIOD; 1068 } 1069 1070 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1071 resp.response_length += sizeof(resp.cqe_comp_caps); 1072 1073 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1074 resp.cqe_comp_caps.max_num = 1075 MLX5_CAP_GEN(dev->mdev, 1076 cqe_compression_max_num); 1077 1078 resp.cqe_comp_caps.supported_format = 1079 MLX5_IB_CQE_RES_FORMAT_HASH | 1080 MLX5_IB_CQE_RES_FORMAT_CSUM; 1081 1082 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1083 resp.cqe_comp_caps.supported_format |= 1084 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1085 } 1086 } 1087 1088 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1089 raw_support) { 1090 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1091 MLX5_CAP_GEN(mdev, qos)) { 1092 resp.packet_pacing_caps.qp_rate_limit_max = 1093 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1094 resp.packet_pacing_caps.qp_rate_limit_min = 1095 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1096 resp.packet_pacing_caps.supported_qpts |= 1097 1 << IB_QPT_RAW_PACKET; 1098 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1099 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1100 resp.packet_pacing_caps.cap_flags |= 1101 MLX5_IB_PP_SUPPORT_BURST; 1102 } 1103 resp.response_length += sizeof(resp.packet_pacing_caps); 1104 } 1105 1106 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1107 uhw_outlen) { 1108 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1109 resp.mlx5_ib_support_multi_pkt_send_wqes = 1110 MLX5_IB_ALLOW_MPW; 1111 1112 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1113 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1114 MLX5_IB_SUPPORT_EMPW; 1115 1116 resp.response_length += 1117 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1118 } 1119 1120 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1121 resp.response_length += sizeof(resp.flags); 1122 1123 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1124 resp.flags |= 1125 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1126 1127 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1128 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1129 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1130 resp.flags |= 1131 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1132 1133 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1134 } 1135 1136 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1137 resp.response_length += sizeof(resp.sw_parsing_caps); 1138 if (MLX5_CAP_ETH(mdev, swp)) { 1139 resp.sw_parsing_caps.sw_parsing_offloads |= 1140 MLX5_IB_SW_PARSING; 1141 1142 if (MLX5_CAP_ETH(mdev, swp_csum)) 1143 resp.sw_parsing_caps.sw_parsing_offloads |= 1144 MLX5_IB_SW_PARSING_CSUM; 1145 1146 if (MLX5_CAP_ETH(mdev, swp_lso)) 1147 resp.sw_parsing_caps.sw_parsing_offloads |= 1148 MLX5_IB_SW_PARSING_LSO; 1149 1150 if (resp.sw_parsing_caps.sw_parsing_offloads) 1151 resp.sw_parsing_caps.supported_qpts = 1152 BIT(IB_QPT_RAW_PACKET); 1153 } 1154 } 1155 1156 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1157 raw_support) { 1158 resp.response_length += sizeof(resp.striding_rq_caps); 1159 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1164 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1165 resp.striding_rq_caps 1166 .min_single_wqe_log_num_of_strides = 1167 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1168 else 1169 resp.striding_rq_caps 1170 .min_single_wqe_log_num_of_strides = 1171 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1172 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1173 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1174 resp.striding_rq_caps.supported_qpts = 1175 BIT(IB_QPT_RAW_PACKET); 1176 } 1177 } 1178 1179 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1180 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1181 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1182 resp.tunnel_offloads_caps |= 1183 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1184 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1185 resp.tunnel_offloads_caps |= 1186 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1187 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1188 resp.tunnel_offloads_caps |= 1189 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1190 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1191 resp.tunnel_offloads_caps |= 1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1193 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1194 resp.tunnel_offloads_caps |= 1195 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1196 } 1197 1198 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1199 resp.response_length += sizeof(resp.dci_streams_caps); 1200 1201 resp.dci_streams_caps.max_log_num_concurent = 1202 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1203 1204 resp.dci_streams_caps.max_log_num_errored = 1205 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1206 } 1207 1208 if (uhw_outlen) { 1209 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1210 1211 if (err) 1212 return err; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1219 u8 *ib_width) 1220 { 1221 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1222 1223 if (active_width & MLX5_PTYS_WIDTH_1X) 1224 *ib_width = IB_WIDTH_1X; 1225 else if (active_width & MLX5_PTYS_WIDTH_2X) 1226 *ib_width = IB_WIDTH_2X; 1227 else if (active_width & MLX5_PTYS_WIDTH_4X) 1228 *ib_width = IB_WIDTH_4X; 1229 else if (active_width & MLX5_PTYS_WIDTH_8X) 1230 *ib_width = IB_WIDTH_8X; 1231 else if (active_width & MLX5_PTYS_WIDTH_12X) 1232 *ib_width = IB_WIDTH_12X; 1233 else { 1234 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1235 active_width); 1236 *ib_width = IB_WIDTH_4X; 1237 } 1238 1239 return; 1240 } 1241 1242 static int mlx5_mtu_to_ib_mtu(int mtu) 1243 { 1244 switch (mtu) { 1245 case 256: return 1; 1246 case 512: return 2; 1247 case 1024: return 3; 1248 case 2048: return 4; 1249 case 4096: return 5; 1250 default: 1251 pr_warn("invalid mtu\n"); 1252 return -1; 1253 } 1254 } 1255 1256 enum ib_max_vl_num { 1257 __IB_MAX_VL_0 = 1, 1258 __IB_MAX_VL_0_1 = 2, 1259 __IB_MAX_VL_0_3 = 3, 1260 __IB_MAX_VL_0_7 = 4, 1261 __IB_MAX_VL_0_14 = 5, 1262 }; 1263 1264 enum mlx5_vl_hw_cap { 1265 MLX5_VL_HW_0 = 1, 1266 MLX5_VL_HW_0_1 = 2, 1267 MLX5_VL_HW_0_2 = 3, 1268 MLX5_VL_HW_0_3 = 4, 1269 MLX5_VL_HW_0_4 = 5, 1270 MLX5_VL_HW_0_5 = 6, 1271 MLX5_VL_HW_0_6 = 7, 1272 MLX5_VL_HW_0_7 = 8, 1273 MLX5_VL_HW_0_14 = 15 1274 }; 1275 1276 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1277 u8 *max_vl_num) 1278 { 1279 switch (vl_hw_cap) { 1280 case MLX5_VL_HW_0: 1281 *max_vl_num = __IB_MAX_VL_0; 1282 break; 1283 case MLX5_VL_HW_0_1: 1284 *max_vl_num = __IB_MAX_VL_0_1; 1285 break; 1286 case MLX5_VL_HW_0_3: 1287 *max_vl_num = __IB_MAX_VL_0_3; 1288 break; 1289 case MLX5_VL_HW_0_7: 1290 *max_vl_num = __IB_MAX_VL_0_7; 1291 break; 1292 case MLX5_VL_HW_0_14: 1293 *max_vl_num = __IB_MAX_VL_0_14; 1294 break; 1295 1296 default: 1297 return -EINVAL; 1298 } 1299 1300 return 0; 1301 } 1302 1303 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1304 struct ib_port_attr *props) 1305 { 1306 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1307 struct mlx5_core_dev *mdev = dev->mdev; 1308 struct mlx5_hca_vport_context *rep; 1309 u16 max_mtu; 1310 u16 oper_mtu; 1311 int err; 1312 u16 ib_link_width_oper; 1313 u8 vl_hw_cap; 1314 1315 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1316 if (!rep) { 1317 err = -ENOMEM; 1318 goto out; 1319 } 1320 1321 /* props being zeroed by the caller, avoid zeroing it here */ 1322 1323 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1324 if (err) 1325 goto out; 1326 1327 props->lid = rep->lid; 1328 props->lmc = rep->lmc; 1329 props->sm_lid = rep->sm_lid; 1330 props->sm_sl = rep->sm_sl; 1331 props->state = rep->vport_state; 1332 props->phys_state = rep->port_physical_state; 1333 props->port_cap_flags = rep->cap_mask1; 1334 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1335 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1336 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1337 props->bad_pkey_cntr = rep->pkey_violation_counter; 1338 props->qkey_viol_cntr = rep->qkey_violation_counter; 1339 props->subnet_timeout = rep->subnet_timeout; 1340 props->init_type_reply = rep->init_type_reply; 1341 1342 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1343 props->port_cap_flags2 = rep->cap_mask2; 1344 1345 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1346 &props->active_speed, port); 1347 if (err) 1348 goto out; 1349 1350 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1351 1352 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1353 1354 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1355 1356 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1357 1358 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1359 1360 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1361 if (err) 1362 goto out; 1363 1364 err = translate_max_vl_num(ibdev, vl_hw_cap, 1365 &props->max_vl_num); 1366 out: 1367 kfree(rep); 1368 return err; 1369 } 1370 1371 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1372 struct ib_port_attr *props) 1373 { 1374 unsigned int count; 1375 int ret; 1376 1377 switch (mlx5_get_vport_access_method(ibdev)) { 1378 case MLX5_VPORT_ACCESS_METHOD_MAD: 1379 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1380 break; 1381 1382 case MLX5_VPORT_ACCESS_METHOD_HCA: 1383 ret = mlx5_query_hca_port(ibdev, port, props); 1384 break; 1385 1386 case MLX5_VPORT_ACCESS_METHOD_NIC: 1387 ret = mlx5_query_port_roce(ibdev, port, props); 1388 break; 1389 1390 default: 1391 ret = -EINVAL; 1392 } 1393 1394 if (!ret && props) { 1395 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1396 struct mlx5_core_dev *mdev; 1397 bool put_mdev = true; 1398 1399 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1400 if (!mdev) { 1401 /* If the port isn't affiliated yet query the master. 1402 * The master and slave will have the same values. 1403 */ 1404 mdev = dev->mdev; 1405 port = 1; 1406 put_mdev = false; 1407 } 1408 count = mlx5_core_reserved_gids_count(mdev); 1409 if (put_mdev) 1410 mlx5_ib_put_native_port_mdev(dev, port); 1411 props->gid_tbl_len -= count; 1412 } 1413 return ret; 1414 } 1415 1416 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1417 struct ib_port_attr *props) 1418 { 1419 return mlx5_query_port_roce(ibdev, port, props); 1420 } 1421 1422 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1423 u16 *pkey) 1424 { 1425 /* Default special Pkey for representor device port as per the 1426 * IB specification 1.3 section 10.9.1.2. 1427 */ 1428 *pkey = 0xffff; 1429 return 0; 1430 } 1431 1432 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1433 union ib_gid *gid) 1434 { 1435 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1436 struct mlx5_core_dev *mdev = dev->mdev; 1437 1438 switch (mlx5_get_vport_access_method(ibdev)) { 1439 case MLX5_VPORT_ACCESS_METHOD_MAD: 1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1441 1442 case MLX5_VPORT_ACCESS_METHOD_HCA: 1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1444 1445 default: 1446 return -EINVAL; 1447 } 1448 1449 } 1450 1451 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1452 u16 index, u16 *pkey) 1453 { 1454 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1455 struct mlx5_core_dev *mdev; 1456 bool put_mdev = true; 1457 u32 mdev_port_num; 1458 int err; 1459 1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1461 if (!mdev) { 1462 /* The port isn't affiliated yet, get the PKey from the master 1463 * port. For RoCE the PKey tables will be the same. 1464 */ 1465 put_mdev = false; 1466 mdev = dev->mdev; 1467 mdev_port_num = 1; 1468 } 1469 1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1471 index, pkey); 1472 if (put_mdev) 1473 mlx5_ib_put_native_port_mdev(dev, port); 1474 1475 return err; 1476 } 1477 1478 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1479 u16 *pkey) 1480 { 1481 switch (mlx5_get_vport_access_method(ibdev)) { 1482 case MLX5_VPORT_ACCESS_METHOD_MAD: 1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1484 1485 case MLX5_VPORT_ACCESS_METHOD_HCA: 1486 case MLX5_VPORT_ACCESS_METHOD_NIC: 1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1488 default: 1489 return -EINVAL; 1490 } 1491 } 1492 1493 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1494 struct ib_device_modify *props) 1495 { 1496 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1497 struct mlx5_reg_node_desc in; 1498 struct mlx5_reg_node_desc out; 1499 int err; 1500 1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1502 return -EOPNOTSUPP; 1503 1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1505 return 0; 1506 1507 /* 1508 * If possible, pass node desc to FW, so it can generate 1509 * a 144 trap. If cmd fails, just ignore. 1510 */ 1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1514 if (err) 1515 return err; 1516 1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1518 1519 return err; 1520 } 1521 1522 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1523 u32 value) 1524 { 1525 struct mlx5_hca_vport_context ctx = {}; 1526 struct mlx5_core_dev *mdev; 1527 u32 mdev_port_num; 1528 int err; 1529 1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1531 if (!mdev) 1532 return -ENODEV; 1533 1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1535 if (err) 1536 goto out; 1537 1538 if (~ctx.cap_mask1_perm & mask) { 1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1540 mask, ctx.cap_mask1_perm); 1541 err = -EINVAL; 1542 goto out; 1543 } 1544 1545 ctx.cap_mask1 = value; 1546 ctx.cap_mask1_perm = mask; 1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1548 0, &ctx); 1549 1550 out: 1551 mlx5_ib_put_native_port_mdev(dev, port_num); 1552 1553 return err; 1554 } 1555 1556 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1557 struct ib_port_modify *props) 1558 { 1559 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1560 struct ib_port_attr attr; 1561 u32 tmp; 1562 int err; 1563 u32 change_mask; 1564 u32 value; 1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1566 IB_LINK_LAYER_INFINIBAND); 1567 1568 /* CM layer calls ib_modify_port() regardless of the link layer. For 1569 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1570 */ 1571 if (!is_ib) 1572 return 0; 1573 1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1577 return set_port_caps_atomic(dev, port, change_mask, value); 1578 } 1579 1580 mutex_lock(&dev->cap_mask_mutex); 1581 1582 err = ib_query_port(ibdev, port, &attr); 1583 if (err) 1584 goto out; 1585 1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1587 ~props->clr_port_cap_mask; 1588 1589 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1590 1591 out: 1592 mutex_unlock(&dev->cap_mask_mutex); 1593 return err; 1594 } 1595 1596 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1597 { 1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1600 } 1601 1602 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1603 { 1604 /* Large page with non 4k uar support might limit the dynamic size */ 1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1606 return MLX5_MIN_DYN_BFREGS; 1607 1608 return MLX5_MAX_DYN_BFREGS; 1609 } 1610 1611 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1612 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1613 struct mlx5_bfreg_info *bfregi) 1614 { 1615 int uars_per_sys_page; 1616 int bfregs_per_sys_page; 1617 int ref_bfregs = req->total_num_bfregs; 1618 1619 if (req->total_num_bfregs == 0) 1620 return -EINVAL; 1621 1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1624 1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1626 return -ENOMEM; 1627 1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1630 /* This holds the required static allocation asked by the user */ 1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1633 return -EINVAL; 1634 1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1639 1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1642 lib_uar_4k ? "yes" : "no", ref_bfregs, 1643 req->total_num_bfregs, bfregi->total_num_bfregs, 1644 bfregi->num_sys_pages); 1645 1646 return 0; 1647 } 1648 1649 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1650 { 1651 struct mlx5_bfreg_info *bfregi; 1652 int err; 1653 int i; 1654 1655 bfregi = &context->bfregi; 1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1657 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1658 context->devx_uid); 1659 if (err) 1660 goto error; 1661 1662 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1663 } 1664 1665 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1666 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1667 1668 return 0; 1669 1670 error: 1671 for (--i; i >= 0; i--) 1672 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1673 context->devx_uid)) 1674 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1675 1676 return err; 1677 } 1678 1679 static void deallocate_uars(struct mlx5_ib_dev *dev, 1680 struct mlx5_ib_ucontext *context) 1681 { 1682 struct mlx5_bfreg_info *bfregi; 1683 int i; 1684 1685 bfregi = &context->bfregi; 1686 for (i = 0; i < bfregi->num_sys_pages; i++) 1687 if (i < bfregi->num_static_sys_pages || 1688 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1689 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1690 context->devx_uid); 1691 } 1692 1693 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1694 { 1695 int err = 0; 1696 1697 mutex_lock(&dev->lb.mutex); 1698 if (td) 1699 dev->lb.user_td++; 1700 if (qp) 1701 dev->lb.qps++; 1702 1703 if (dev->lb.user_td == 2 || 1704 dev->lb.qps == 1) { 1705 if (!dev->lb.enabled) { 1706 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1707 dev->lb.enabled = true; 1708 } 1709 } 1710 1711 mutex_unlock(&dev->lb.mutex); 1712 1713 return err; 1714 } 1715 1716 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1717 { 1718 mutex_lock(&dev->lb.mutex); 1719 if (td) 1720 dev->lb.user_td--; 1721 if (qp) 1722 dev->lb.qps--; 1723 1724 if (dev->lb.user_td == 1 && 1725 dev->lb.qps == 0) { 1726 if (dev->lb.enabled) { 1727 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1728 dev->lb.enabled = false; 1729 } 1730 } 1731 1732 mutex_unlock(&dev->lb.mutex); 1733 } 1734 1735 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1736 u16 uid) 1737 { 1738 int err; 1739 1740 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1741 return 0; 1742 1743 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1744 if (err) 1745 return err; 1746 1747 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1748 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1749 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1750 return err; 1751 1752 return mlx5_ib_enable_lb(dev, true, false); 1753 } 1754 1755 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1756 u16 uid) 1757 { 1758 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1759 return; 1760 1761 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1762 1763 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1764 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1765 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1766 return; 1767 1768 mlx5_ib_disable_lb(dev, true, false); 1769 } 1770 1771 static int set_ucontext_resp(struct ib_ucontext *uctx, 1772 struct mlx5_ib_alloc_ucontext_resp *resp) 1773 { 1774 struct ib_device *ibdev = uctx->device; 1775 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1776 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1777 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1778 1779 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1780 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1781 resp->comp_mask |= 1782 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1783 } 1784 1785 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1786 if (dev->wc_support) 1787 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1788 log_bf_reg_size); 1789 resp->cache_line_size = cache_line_size(); 1790 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1791 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1792 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1793 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1794 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1795 resp->cqe_version = context->cqe_version; 1796 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1797 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1798 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1799 MLX5_CAP_GEN(dev->mdev, 1800 num_of_uars_per_page) : 1; 1801 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1802 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1803 resp->num_ports = dev->num_ports; 1804 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1805 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1806 1807 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1808 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1809 resp->eth_min_inline++; 1810 } 1811 1812 if (dev->mdev->clock_info) 1813 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1814 1815 /* 1816 * We don't want to expose information from the PCI bar that is located 1817 * after 4096 bytes, so if the arch only supports larger pages, let's 1818 * pretend we don't support reading the HCA's core clock. This is also 1819 * forced by mmap function. 1820 */ 1821 if (PAGE_SIZE <= 4096) { 1822 resp->comp_mask |= 1823 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1824 resp->hca_core_clock_offset = 1825 offsetof(struct mlx5_init_seg, 1826 internal_timer_h) % PAGE_SIZE; 1827 } 1828 1829 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1830 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1831 1832 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1833 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1834 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1835 resp->comp_mask |= 1836 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1837 1838 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1839 1840 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1841 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1842 1843 resp->comp_mask |= 1844 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1845 1846 return 0; 1847 } 1848 1849 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1850 struct ib_udata *udata) 1851 { 1852 struct ib_device *ibdev = uctx->device; 1853 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1854 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1855 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1856 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1857 struct mlx5_bfreg_info *bfregi; 1858 int ver; 1859 int err; 1860 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1861 max_cqe_version); 1862 bool lib_uar_4k; 1863 bool lib_uar_dyn; 1864 1865 if (!dev->ib_active) 1866 return -EAGAIN; 1867 1868 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1869 ver = 0; 1870 else if (udata->inlen >= min_req_v2) 1871 ver = 2; 1872 else 1873 return -EINVAL; 1874 1875 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1876 if (err) 1877 return err; 1878 1879 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1880 return -EOPNOTSUPP; 1881 1882 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1883 return -EOPNOTSUPP; 1884 1885 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1886 MLX5_NON_FP_BFREGS_PER_UAR); 1887 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1888 return -EINVAL; 1889 1890 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1891 err = mlx5_ib_devx_create(dev, true); 1892 if (err < 0) 1893 goto out_ctx; 1894 context->devx_uid = err; 1895 } 1896 1897 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1898 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1899 bfregi = &context->bfregi; 1900 1901 if (lib_uar_dyn) { 1902 bfregi->lib_uar_dyn = lib_uar_dyn; 1903 goto uar_done; 1904 } 1905 1906 /* updates req->total_num_bfregs */ 1907 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1908 if (err) 1909 goto out_devx; 1910 1911 mutex_init(&bfregi->lock); 1912 bfregi->lib_uar_4k = lib_uar_4k; 1913 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1914 GFP_KERNEL); 1915 if (!bfregi->count) { 1916 err = -ENOMEM; 1917 goto out_devx; 1918 } 1919 1920 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1921 sizeof(*bfregi->sys_pages), 1922 GFP_KERNEL); 1923 if (!bfregi->sys_pages) { 1924 err = -ENOMEM; 1925 goto out_count; 1926 } 1927 1928 err = allocate_uars(dev, context); 1929 if (err) 1930 goto out_sys_pages; 1931 1932 uar_done: 1933 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1934 context->devx_uid); 1935 if (err) 1936 goto out_uars; 1937 1938 INIT_LIST_HEAD(&context->db_page_list); 1939 mutex_init(&context->db_page_mutex); 1940 1941 context->cqe_version = min_t(__u8, 1942 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1943 req.max_cqe_version); 1944 1945 err = set_ucontext_resp(uctx, &resp); 1946 if (err) 1947 goto out_mdev; 1948 1949 resp.response_length = min(udata->outlen, sizeof(resp)); 1950 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1951 if (err) 1952 goto out_mdev; 1953 1954 bfregi->ver = ver; 1955 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1956 context->lib_caps = req.lib_caps; 1957 print_lib_caps(dev, context->lib_caps); 1958 1959 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1960 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1961 1962 atomic_set(&context->tx_port_affinity, 1963 atomic_add_return( 1964 1, &dev->port[port].roce.tx_port_affinity)); 1965 } 1966 1967 return 0; 1968 1969 out_mdev: 1970 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1971 1972 out_uars: 1973 deallocate_uars(dev, context); 1974 1975 out_sys_pages: 1976 kfree(bfregi->sys_pages); 1977 1978 out_count: 1979 kfree(bfregi->count); 1980 1981 out_devx: 1982 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1983 mlx5_ib_devx_destroy(dev, context->devx_uid); 1984 1985 out_ctx: 1986 return err; 1987 } 1988 1989 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1990 struct uverbs_attr_bundle *attrs) 1991 { 1992 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1993 int ret; 1994 1995 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1996 if (ret) 1997 return ret; 1998 1999 uctx_resp.response_length = 2000 min_t(size_t, 2001 uverbs_attr_get_len(attrs, 2002 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2003 sizeof(uctx_resp)); 2004 2005 ret = uverbs_copy_to_struct_or_zero(attrs, 2006 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2007 &uctx_resp, 2008 sizeof(uctx_resp)); 2009 return ret; 2010 } 2011 2012 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2013 { 2014 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2015 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2016 struct mlx5_bfreg_info *bfregi; 2017 2018 bfregi = &context->bfregi; 2019 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2020 2021 deallocate_uars(dev, context); 2022 kfree(bfregi->sys_pages); 2023 kfree(bfregi->count); 2024 2025 if (context->devx_uid) 2026 mlx5_ib_devx_destroy(dev, context->devx_uid); 2027 } 2028 2029 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2030 int uar_idx) 2031 { 2032 int fw_uars_per_page; 2033 2034 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2035 2036 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2037 } 2038 2039 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2040 int uar_idx) 2041 { 2042 unsigned int fw_uars_per_page; 2043 2044 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2045 MLX5_UARS_IN_PAGE : 1; 2046 2047 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2048 } 2049 2050 static int get_command(unsigned long offset) 2051 { 2052 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2053 } 2054 2055 static int get_arg(unsigned long offset) 2056 { 2057 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2058 } 2059 2060 static int get_index(unsigned long offset) 2061 { 2062 return get_arg(offset); 2063 } 2064 2065 /* Index resides in an extra byte to enable larger values than 255 */ 2066 static int get_extended_index(unsigned long offset) 2067 { 2068 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2069 } 2070 2071 2072 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2073 { 2074 } 2075 2076 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2077 { 2078 switch (cmd) { 2079 case MLX5_IB_MMAP_WC_PAGE: 2080 return "WC"; 2081 case MLX5_IB_MMAP_REGULAR_PAGE: 2082 return "best effort WC"; 2083 case MLX5_IB_MMAP_NC_PAGE: 2084 return "NC"; 2085 case MLX5_IB_MMAP_DEVICE_MEM: 2086 return "Device Memory"; 2087 default: 2088 return "Unknown"; 2089 } 2090 } 2091 2092 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2093 struct vm_area_struct *vma, 2094 struct mlx5_ib_ucontext *context) 2095 { 2096 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2097 !(vma->vm_flags & VM_SHARED)) 2098 return -EINVAL; 2099 2100 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2101 return -EOPNOTSUPP; 2102 2103 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2104 return -EPERM; 2105 vm_flags_clear(vma, VM_MAYWRITE); 2106 2107 if (!dev->mdev->clock_info) 2108 return -EOPNOTSUPP; 2109 2110 return vm_insert_page(vma, vma->vm_start, 2111 virt_to_page(dev->mdev->clock_info)); 2112 } 2113 2114 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2115 { 2116 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2117 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2118 struct mlx5_var_table *var_table = &dev->var_table; 2119 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2120 2121 switch (mentry->mmap_flag) { 2122 case MLX5_IB_MMAP_TYPE_MEMIC: 2123 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2124 mlx5_ib_dm_mmap_free(dev, mentry); 2125 break; 2126 case MLX5_IB_MMAP_TYPE_VAR: 2127 mutex_lock(&var_table->bitmap_lock); 2128 clear_bit(mentry->page_idx, var_table->bitmap); 2129 mutex_unlock(&var_table->bitmap_lock); 2130 kfree(mentry); 2131 break; 2132 case MLX5_IB_MMAP_TYPE_UAR_WC: 2133 case MLX5_IB_MMAP_TYPE_UAR_NC: 2134 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2135 context->devx_uid); 2136 kfree(mentry); 2137 break; 2138 default: 2139 WARN_ON(true); 2140 } 2141 } 2142 2143 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2144 struct vm_area_struct *vma, 2145 struct mlx5_ib_ucontext *context) 2146 { 2147 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2148 int err; 2149 unsigned long idx; 2150 phys_addr_t pfn; 2151 pgprot_t prot; 2152 u32 bfreg_dyn_idx = 0; 2153 u32 uar_index; 2154 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2155 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2156 bfregi->num_static_sys_pages; 2157 2158 if (bfregi->lib_uar_dyn) 2159 return -EINVAL; 2160 2161 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2162 return -EINVAL; 2163 2164 if (dyn_uar) 2165 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2166 else 2167 idx = get_index(vma->vm_pgoff); 2168 2169 if (idx >= max_valid_idx) { 2170 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2171 idx, max_valid_idx); 2172 return -EINVAL; 2173 } 2174 2175 switch (cmd) { 2176 case MLX5_IB_MMAP_WC_PAGE: 2177 case MLX5_IB_MMAP_ALLOC_WC: 2178 case MLX5_IB_MMAP_REGULAR_PAGE: 2179 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2180 prot = pgprot_writecombine(vma->vm_page_prot); 2181 break; 2182 case MLX5_IB_MMAP_NC_PAGE: 2183 prot = pgprot_noncached(vma->vm_page_prot); 2184 break; 2185 default: 2186 return -EINVAL; 2187 } 2188 2189 if (dyn_uar) { 2190 int uars_per_page; 2191 2192 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2193 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2194 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2195 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2196 bfreg_dyn_idx, bfregi->total_num_bfregs); 2197 return -EINVAL; 2198 } 2199 2200 mutex_lock(&bfregi->lock); 2201 /* Fail if uar already allocated, first bfreg index of each 2202 * page holds its count. 2203 */ 2204 if (bfregi->count[bfreg_dyn_idx]) { 2205 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2206 mutex_unlock(&bfregi->lock); 2207 return -EINVAL; 2208 } 2209 2210 bfregi->count[bfreg_dyn_idx]++; 2211 mutex_unlock(&bfregi->lock); 2212 2213 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2214 context->devx_uid); 2215 if (err) { 2216 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2217 goto free_bfreg; 2218 } 2219 } else { 2220 uar_index = bfregi->sys_pages[idx]; 2221 } 2222 2223 pfn = uar_index2pfn(dev, uar_index); 2224 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2225 2226 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2227 prot, NULL); 2228 if (err) { 2229 mlx5_ib_err(dev, 2230 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2231 err, mmap_cmd2str(cmd)); 2232 goto err; 2233 } 2234 2235 if (dyn_uar) 2236 bfregi->sys_pages[idx] = uar_index; 2237 return 0; 2238 2239 err: 2240 if (!dyn_uar) 2241 return err; 2242 2243 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2244 2245 free_bfreg: 2246 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2247 2248 return err; 2249 } 2250 2251 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2252 { 2253 unsigned long idx; 2254 u8 command; 2255 2256 command = get_command(vma->vm_pgoff); 2257 idx = get_extended_index(vma->vm_pgoff); 2258 2259 return (command << 16 | idx); 2260 } 2261 2262 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2263 struct vm_area_struct *vma, 2264 struct ib_ucontext *ucontext) 2265 { 2266 struct mlx5_user_mmap_entry *mentry; 2267 struct rdma_user_mmap_entry *entry; 2268 unsigned long pgoff; 2269 pgprot_t prot; 2270 phys_addr_t pfn; 2271 int ret; 2272 2273 pgoff = mlx5_vma_to_pgoff(vma); 2274 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2275 if (!entry) 2276 return -EINVAL; 2277 2278 mentry = to_mmmap(entry); 2279 pfn = (mentry->address >> PAGE_SHIFT); 2280 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2281 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2282 prot = pgprot_noncached(vma->vm_page_prot); 2283 else 2284 prot = pgprot_writecombine(vma->vm_page_prot); 2285 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2286 entry->npages * PAGE_SIZE, 2287 prot, 2288 entry); 2289 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2290 return ret; 2291 } 2292 2293 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2294 { 2295 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2296 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2297 2298 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2299 (index & 0xFF)) << PAGE_SHIFT; 2300 } 2301 2302 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2303 { 2304 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2305 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2306 unsigned long command; 2307 phys_addr_t pfn; 2308 2309 command = get_command(vma->vm_pgoff); 2310 switch (command) { 2311 case MLX5_IB_MMAP_WC_PAGE: 2312 case MLX5_IB_MMAP_ALLOC_WC: 2313 if (!dev->wc_support) 2314 return -EPERM; 2315 fallthrough; 2316 case MLX5_IB_MMAP_NC_PAGE: 2317 case MLX5_IB_MMAP_REGULAR_PAGE: 2318 return uar_mmap(dev, command, vma, context); 2319 2320 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2321 return -ENOSYS; 2322 2323 case MLX5_IB_MMAP_CORE_CLOCK: 2324 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2325 return -EINVAL; 2326 2327 if (vma->vm_flags & VM_WRITE) 2328 return -EPERM; 2329 vm_flags_clear(vma, VM_MAYWRITE); 2330 2331 /* Don't expose to user-space information it shouldn't have */ 2332 if (PAGE_SIZE > 4096) 2333 return -EOPNOTSUPP; 2334 2335 pfn = (dev->mdev->iseg_base + 2336 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2337 PAGE_SHIFT; 2338 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2339 PAGE_SIZE, 2340 pgprot_noncached(vma->vm_page_prot), 2341 NULL); 2342 case MLX5_IB_MMAP_CLOCK_INFO: 2343 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2344 2345 default: 2346 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2347 } 2348 2349 return 0; 2350 } 2351 2352 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2353 { 2354 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2355 struct ib_device *ibdev = ibpd->device; 2356 struct mlx5_ib_alloc_pd_resp resp; 2357 int err; 2358 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2359 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2360 u16 uid = 0; 2361 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2362 udata, struct mlx5_ib_ucontext, ibucontext); 2363 2364 uid = context ? context->devx_uid : 0; 2365 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2366 MLX5_SET(alloc_pd_in, in, uid, uid); 2367 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2368 if (err) 2369 return err; 2370 2371 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2372 pd->uid = uid; 2373 if (udata) { 2374 resp.pdn = pd->pdn; 2375 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2376 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2377 return -EFAULT; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2385 { 2386 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2387 struct mlx5_ib_pd *mpd = to_mpd(pd); 2388 2389 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2390 } 2391 2392 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2393 { 2394 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2395 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2396 int err; 2397 u16 uid; 2398 2399 uid = ibqp->pd ? 2400 to_mpd(ibqp->pd)->uid : 0; 2401 2402 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2403 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2404 return -EOPNOTSUPP; 2405 } 2406 2407 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2408 if (err) 2409 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2410 ibqp->qp_num, gid->raw); 2411 2412 return err; 2413 } 2414 2415 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2416 { 2417 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2418 int err; 2419 u16 uid; 2420 2421 uid = ibqp->pd ? 2422 to_mpd(ibqp->pd)->uid : 0; 2423 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2424 if (err) 2425 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2426 ibqp->qp_num, gid->raw); 2427 2428 return err; 2429 } 2430 2431 static int init_node_data(struct mlx5_ib_dev *dev) 2432 { 2433 int err; 2434 2435 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2436 if (err) 2437 return err; 2438 2439 dev->mdev->rev_id = dev->mdev->pdev->revision; 2440 2441 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2442 } 2443 2444 static ssize_t fw_pages_show(struct device *device, 2445 struct device_attribute *attr, char *buf) 2446 { 2447 struct mlx5_ib_dev *dev = 2448 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2449 2450 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2451 } 2452 static DEVICE_ATTR_RO(fw_pages); 2453 2454 static ssize_t reg_pages_show(struct device *device, 2455 struct device_attribute *attr, char *buf) 2456 { 2457 struct mlx5_ib_dev *dev = 2458 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2459 2460 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2461 } 2462 static DEVICE_ATTR_RO(reg_pages); 2463 2464 static ssize_t hca_type_show(struct device *device, 2465 struct device_attribute *attr, char *buf) 2466 { 2467 struct mlx5_ib_dev *dev = 2468 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2469 2470 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2471 } 2472 static DEVICE_ATTR_RO(hca_type); 2473 2474 static ssize_t hw_rev_show(struct device *device, 2475 struct device_attribute *attr, char *buf) 2476 { 2477 struct mlx5_ib_dev *dev = 2478 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2479 2480 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2481 } 2482 static DEVICE_ATTR_RO(hw_rev); 2483 2484 static ssize_t board_id_show(struct device *device, 2485 struct device_attribute *attr, char *buf) 2486 { 2487 struct mlx5_ib_dev *dev = 2488 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2489 2490 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2491 dev->mdev->board_id); 2492 } 2493 static DEVICE_ATTR_RO(board_id); 2494 2495 static struct attribute *mlx5_class_attributes[] = { 2496 &dev_attr_hw_rev.attr, 2497 &dev_attr_hca_type.attr, 2498 &dev_attr_board_id.attr, 2499 &dev_attr_fw_pages.attr, 2500 &dev_attr_reg_pages.attr, 2501 NULL, 2502 }; 2503 2504 static const struct attribute_group mlx5_attr_group = { 2505 .attrs = mlx5_class_attributes, 2506 }; 2507 2508 static void pkey_change_handler(struct work_struct *work) 2509 { 2510 struct mlx5_ib_port_resources *ports = 2511 container_of(work, struct mlx5_ib_port_resources, 2512 pkey_change_work); 2513 2514 if (!ports->gsi) 2515 /* 2516 * We got this event before device was fully configured 2517 * and MAD registration code wasn't called/finished yet. 2518 */ 2519 return; 2520 2521 mlx5_ib_gsi_pkey_change(ports->gsi); 2522 } 2523 2524 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2525 { 2526 struct mlx5_ib_qp *mqp; 2527 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2528 struct mlx5_core_cq *mcq; 2529 struct list_head cq_armed_list; 2530 unsigned long flags_qp; 2531 unsigned long flags_cq; 2532 unsigned long flags; 2533 2534 INIT_LIST_HEAD(&cq_armed_list); 2535 2536 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2537 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2538 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2539 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2540 if (mqp->sq.tail != mqp->sq.head) { 2541 send_mcq = to_mcq(mqp->ibqp.send_cq); 2542 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2543 if (send_mcq->mcq.comp && 2544 mqp->ibqp.send_cq->comp_handler) { 2545 if (!send_mcq->mcq.reset_notify_added) { 2546 send_mcq->mcq.reset_notify_added = 1; 2547 list_add_tail(&send_mcq->mcq.reset_notify, 2548 &cq_armed_list); 2549 } 2550 } 2551 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2552 } 2553 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2554 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2555 /* no handling is needed for SRQ */ 2556 if (!mqp->ibqp.srq) { 2557 if (mqp->rq.tail != mqp->rq.head) { 2558 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2559 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2560 if (recv_mcq->mcq.comp && 2561 mqp->ibqp.recv_cq->comp_handler) { 2562 if (!recv_mcq->mcq.reset_notify_added) { 2563 recv_mcq->mcq.reset_notify_added = 1; 2564 list_add_tail(&recv_mcq->mcq.reset_notify, 2565 &cq_armed_list); 2566 } 2567 } 2568 spin_unlock_irqrestore(&recv_mcq->lock, 2569 flags_cq); 2570 } 2571 } 2572 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2573 } 2574 /*At that point all inflight post send were put to be executed as of we 2575 * lock/unlock above locks Now need to arm all involved CQs. 2576 */ 2577 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2578 mcq->comp(mcq, NULL); 2579 } 2580 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2581 } 2582 2583 static void delay_drop_handler(struct work_struct *work) 2584 { 2585 int err; 2586 struct mlx5_ib_delay_drop *delay_drop = 2587 container_of(work, struct mlx5_ib_delay_drop, 2588 delay_drop_work); 2589 2590 atomic_inc(&delay_drop->events_cnt); 2591 2592 mutex_lock(&delay_drop->lock); 2593 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2594 if (err) { 2595 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2596 delay_drop->timeout); 2597 delay_drop->activate = false; 2598 } 2599 mutex_unlock(&delay_drop->lock); 2600 } 2601 2602 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2603 struct ib_event *ibev) 2604 { 2605 u32 port = (eqe->data.port.port >> 4) & 0xf; 2606 2607 switch (eqe->sub_type) { 2608 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2609 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2610 IB_LINK_LAYER_ETHERNET) 2611 schedule_work(&ibdev->delay_drop.delay_drop_work); 2612 break; 2613 default: /* do nothing */ 2614 return; 2615 } 2616 } 2617 2618 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2619 struct ib_event *ibev) 2620 { 2621 u32 port = (eqe->data.port.port >> 4) & 0xf; 2622 2623 ibev->element.port_num = port; 2624 2625 switch (eqe->sub_type) { 2626 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2627 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2628 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2629 /* In RoCE, port up/down events are handled in 2630 * mlx5_netdev_event(). 2631 */ 2632 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2633 IB_LINK_LAYER_ETHERNET) 2634 return -EINVAL; 2635 2636 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2637 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2638 break; 2639 2640 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2641 ibev->event = IB_EVENT_LID_CHANGE; 2642 break; 2643 2644 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2645 ibev->event = IB_EVENT_PKEY_CHANGE; 2646 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2647 break; 2648 2649 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2650 ibev->event = IB_EVENT_GID_CHANGE; 2651 break; 2652 2653 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2654 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2655 break; 2656 default: 2657 return -EINVAL; 2658 } 2659 2660 return 0; 2661 } 2662 2663 static void mlx5_ib_handle_event(struct work_struct *_work) 2664 { 2665 struct mlx5_ib_event_work *work = 2666 container_of(_work, struct mlx5_ib_event_work, work); 2667 struct mlx5_ib_dev *ibdev; 2668 struct ib_event ibev; 2669 bool fatal = false; 2670 2671 if (work->is_slave) { 2672 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2673 if (!ibdev) 2674 goto out; 2675 } else { 2676 ibdev = work->dev; 2677 } 2678 2679 switch (work->event) { 2680 case MLX5_DEV_EVENT_SYS_ERROR: 2681 ibev.event = IB_EVENT_DEVICE_FATAL; 2682 mlx5_ib_handle_internal_error(ibdev); 2683 ibev.element.port_num = (u8)(unsigned long)work->param; 2684 fatal = true; 2685 break; 2686 case MLX5_EVENT_TYPE_PORT_CHANGE: 2687 if (handle_port_change(ibdev, work->param, &ibev)) 2688 goto out; 2689 break; 2690 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2691 handle_general_event(ibdev, work->param, &ibev); 2692 fallthrough; 2693 default: 2694 goto out; 2695 } 2696 2697 ibev.device = &ibdev->ib_dev; 2698 2699 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2700 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2701 goto out; 2702 } 2703 2704 if (ibdev->ib_active) 2705 ib_dispatch_event(&ibev); 2706 2707 if (fatal) 2708 ibdev->ib_active = false; 2709 out: 2710 kfree(work); 2711 } 2712 2713 static int mlx5_ib_event(struct notifier_block *nb, 2714 unsigned long event, void *param) 2715 { 2716 struct mlx5_ib_event_work *work; 2717 2718 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2719 if (!work) 2720 return NOTIFY_DONE; 2721 2722 INIT_WORK(&work->work, mlx5_ib_handle_event); 2723 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2724 work->is_slave = false; 2725 work->param = param; 2726 work->event = event; 2727 2728 queue_work(mlx5_ib_event_wq, &work->work); 2729 2730 return NOTIFY_OK; 2731 } 2732 2733 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2734 unsigned long event, void *param) 2735 { 2736 struct mlx5_ib_event_work *work; 2737 2738 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2739 if (!work) 2740 return NOTIFY_DONE; 2741 2742 INIT_WORK(&work->work, mlx5_ib_handle_event); 2743 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2744 work->is_slave = true; 2745 work->param = param; 2746 work->event = event; 2747 queue_work(mlx5_ib_event_wq, &work->work); 2748 2749 return NOTIFY_OK; 2750 } 2751 2752 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2753 { 2754 struct mlx5_hca_vport_context vport_ctx; 2755 int err; 2756 int port; 2757 2758 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2759 return 0; 2760 2761 for (port = 1; port <= dev->num_ports; port++) { 2762 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2763 dev->port_caps[port - 1].has_smi = true; 2764 continue; 2765 } 2766 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2767 &vport_ctx); 2768 if (err) { 2769 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2770 port, err); 2771 return err; 2772 } 2773 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2780 { 2781 unsigned int port; 2782 2783 rdma_for_each_port (&dev->ib_dev, port) 2784 mlx5_query_ext_port_caps(dev, port); 2785 } 2786 2787 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2788 { 2789 switch (umr_fence_cap) { 2790 case MLX5_CAP_UMR_FENCE_NONE: 2791 return MLX5_FENCE_MODE_NONE; 2792 case MLX5_CAP_UMR_FENCE_SMALL: 2793 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2794 default: 2795 return MLX5_FENCE_MODE_STRONG_ORDERING; 2796 } 2797 } 2798 2799 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 2800 { 2801 struct mlx5_ib_resources *devr = &dev->devr; 2802 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2803 struct ib_device *ibdev; 2804 struct ib_pd *pd; 2805 struct ib_cq *cq; 2806 int ret = 0; 2807 2808 2809 /* 2810 * devr->c0 is set once, never changed until device unload. 2811 * Avoid taking the mutex if initialization is already done. 2812 */ 2813 if (devr->c0) 2814 return 0; 2815 2816 mutex_lock(&devr->cq_lock); 2817 if (devr->c0) 2818 goto unlock; 2819 2820 ibdev = &dev->ib_dev; 2821 pd = ib_alloc_pd(ibdev, 0); 2822 if (IS_ERR(pd)) { 2823 ret = PTR_ERR(pd); 2824 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret); 2825 goto unlock; 2826 } 2827 2828 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2829 if (IS_ERR(cq)) { 2830 ret = PTR_ERR(cq); 2831 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret); 2832 ib_dealloc_pd(pd); 2833 goto unlock; 2834 } 2835 2836 devr->p0 = pd; 2837 devr->c0 = cq; 2838 2839 unlock: 2840 mutex_unlock(&devr->cq_lock); 2841 return ret; 2842 } 2843 2844 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 2845 { 2846 struct mlx5_ib_resources *devr = &dev->devr; 2847 struct ib_srq_init_attr attr; 2848 struct ib_srq *s0, *s1; 2849 int ret = 0; 2850 2851 /* 2852 * devr->s1 is set once, never changed until device unload. 2853 * Avoid taking the mutex if initialization is already done. 2854 */ 2855 if (devr->s1) 2856 return 0; 2857 2858 mutex_lock(&devr->srq_lock); 2859 if (devr->s1) 2860 goto unlock; 2861 2862 ret = mlx5_ib_dev_res_cq_init(dev); 2863 if (ret) 2864 goto unlock; 2865 2866 memset(&attr, 0, sizeof(attr)); 2867 attr.attr.max_sge = 1; 2868 attr.attr.max_wr = 1; 2869 attr.srq_type = IB_SRQT_XRC; 2870 attr.ext.cq = devr->c0; 2871 2872 s0 = ib_create_srq(devr->p0, &attr); 2873 if (IS_ERR(s0)) { 2874 ret = PTR_ERR(s0); 2875 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret); 2876 goto unlock; 2877 } 2878 2879 memset(&attr, 0, sizeof(attr)); 2880 attr.attr.max_sge = 1; 2881 attr.attr.max_wr = 1; 2882 attr.srq_type = IB_SRQT_BASIC; 2883 2884 s1 = ib_create_srq(devr->p0, &attr); 2885 if (IS_ERR(s1)) { 2886 ret = PTR_ERR(s1); 2887 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret); 2888 ib_destroy_srq(s0); 2889 } 2890 2891 devr->s0 = s0; 2892 devr->s1 = s1; 2893 2894 unlock: 2895 mutex_unlock(&devr->srq_lock); 2896 return ret; 2897 } 2898 2899 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2900 { 2901 struct mlx5_ib_resources *devr = &dev->devr; 2902 int ret; 2903 2904 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2905 return -EOPNOTSUPP; 2906 2907 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2908 if (ret) 2909 return ret; 2910 2911 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2912 if (ret) { 2913 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2914 return ret; 2915 } 2916 2917 mutex_init(&devr->cq_lock); 2918 mutex_init(&devr->srq_lock); 2919 2920 return 0; 2921 } 2922 2923 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2924 { 2925 struct mlx5_ib_resources *devr = &dev->devr; 2926 2927 /* After s0/s1 init, they are not unset during the device lifetime. */ 2928 if (devr->s1) { 2929 ib_destroy_srq(devr->s1); 2930 ib_destroy_srq(devr->s0); 2931 } 2932 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2933 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2934 /* After p0/c0 init, they are not unset during the device lifetime. */ 2935 if (devr->c0) { 2936 ib_destroy_cq(devr->c0); 2937 ib_dealloc_pd(devr->p0); 2938 } 2939 mutex_destroy(&devr->cq_lock); 2940 mutex_destroy(&devr->srq_lock); 2941 } 2942 2943 static u32 get_core_cap_flags(struct ib_device *ibdev, 2944 struct mlx5_hca_vport_context *rep) 2945 { 2946 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2947 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2948 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2949 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2950 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2951 u32 ret = 0; 2952 2953 if (rep->grh_required) 2954 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2955 2956 if (ll == IB_LINK_LAYER_INFINIBAND) 2957 return ret | RDMA_CORE_PORT_IBA_IB; 2958 2959 if (raw_support) 2960 ret |= RDMA_CORE_PORT_RAW_PACKET; 2961 2962 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2963 return ret; 2964 2965 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2966 return ret; 2967 2968 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2969 ret |= RDMA_CORE_PORT_IBA_ROCE; 2970 2971 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2972 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2973 2974 return ret; 2975 } 2976 2977 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2978 struct ib_port_immutable *immutable) 2979 { 2980 struct ib_port_attr attr; 2981 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2982 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2983 struct mlx5_hca_vport_context rep = {0}; 2984 int err; 2985 2986 err = ib_query_port(ibdev, port_num, &attr); 2987 if (err) 2988 return err; 2989 2990 if (ll == IB_LINK_LAYER_INFINIBAND) { 2991 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2992 &rep); 2993 if (err) 2994 return err; 2995 } 2996 2997 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2998 immutable->gid_tbl_len = attr.gid_tbl_len; 2999 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3000 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3001 3002 return 0; 3003 } 3004 3005 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3006 struct ib_port_immutable *immutable) 3007 { 3008 struct ib_port_attr attr; 3009 int err; 3010 3011 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3012 3013 err = ib_query_port(ibdev, port_num, &attr); 3014 if (err) 3015 return err; 3016 3017 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3018 immutable->gid_tbl_len = attr.gid_tbl_len; 3019 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3020 3021 return 0; 3022 } 3023 3024 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3025 { 3026 struct mlx5_ib_dev *dev = 3027 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3028 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3029 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3030 fw_rev_sub(dev->mdev)); 3031 } 3032 3033 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3034 { 3035 struct mlx5_core_dev *mdev = dev->mdev; 3036 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3037 MLX5_FLOW_NAMESPACE_LAG); 3038 struct mlx5_flow_table *ft; 3039 int err; 3040 3041 if (!ns || !mlx5_lag_is_active(mdev)) 3042 return 0; 3043 3044 err = mlx5_cmd_create_vport_lag(mdev); 3045 if (err) 3046 return err; 3047 3048 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3049 if (IS_ERR(ft)) { 3050 err = PTR_ERR(ft); 3051 goto err_destroy_vport_lag; 3052 } 3053 3054 dev->flow_db->lag_demux_ft = ft; 3055 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3056 dev->lag_active = true; 3057 return 0; 3058 3059 err_destroy_vport_lag: 3060 mlx5_cmd_destroy_vport_lag(mdev); 3061 return err; 3062 } 3063 3064 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3065 { 3066 struct mlx5_core_dev *mdev = dev->mdev; 3067 3068 if (dev->lag_active) { 3069 dev->lag_active = false; 3070 3071 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3072 dev->flow_db->lag_demux_ft = NULL; 3073 3074 mlx5_cmd_destroy_vport_lag(mdev); 3075 } 3076 } 3077 3078 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3079 struct net_device *netdev) 3080 { 3081 int err; 3082 3083 if (roce->tracking_netdev) 3084 return; 3085 roce->tracking_netdev = netdev; 3086 roce->nb.notifier_call = mlx5_netdev_event; 3087 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3088 WARN_ON(err); 3089 } 3090 3091 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3092 { 3093 if (!roce->tracking_netdev) 3094 return; 3095 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3096 &roce->nn); 3097 roce->tracking_netdev = NULL; 3098 } 3099 3100 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3101 unsigned long event, void *data) 3102 { 3103 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3104 struct net_device *netdev = data; 3105 3106 switch (event) { 3107 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3108 if (netdev) 3109 mlx5_netdev_notifier_register(roce, netdev); 3110 else 3111 mlx5_netdev_notifier_unregister(roce); 3112 break; 3113 default: 3114 return NOTIFY_DONE; 3115 } 3116 3117 return NOTIFY_OK; 3118 } 3119 3120 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3121 { 3122 struct mlx5_roce *roce = &dev->port[port_num].roce; 3123 3124 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3125 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3126 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3127 } 3128 3129 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3130 { 3131 struct mlx5_roce *roce = &dev->port[port_num].roce; 3132 3133 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3134 mlx5_netdev_notifier_unregister(roce); 3135 } 3136 3137 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3138 { 3139 int err; 3140 3141 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3142 err = mlx5_nic_vport_enable_roce(dev->mdev); 3143 if (err) 3144 return err; 3145 } 3146 3147 err = mlx5_eth_lag_init(dev); 3148 if (err) 3149 goto err_disable_roce; 3150 3151 return 0; 3152 3153 err_disable_roce: 3154 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3155 mlx5_nic_vport_disable_roce(dev->mdev); 3156 3157 return err; 3158 } 3159 3160 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3161 { 3162 mlx5_eth_lag_cleanup(dev); 3163 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3164 mlx5_nic_vport_disable_roce(dev->mdev); 3165 } 3166 3167 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3168 enum rdma_netdev_t type, 3169 struct rdma_netdev_alloc_params *params) 3170 { 3171 if (type != RDMA_NETDEV_IPOIB) 3172 return -EOPNOTSUPP; 3173 3174 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3175 } 3176 3177 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3178 size_t count, loff_t *pos) 3179 { 3180 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3181 char lbuf[20]; 3182 int len; 3183 3184 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3185 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3186 } 3187 3188 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3189 size_t count, loff_t *pos) 3190 { 3191 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3192 u32 timeout; 3193 u32 var; 3194 3195 if (kstrtouint_from_user(buf, count, 0, &var)) 3196 return -EFAULT; 3197 3198 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3199 1000); 3200 if (timeout != var) 3201 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3202 timeout); 3203 3204 delay_drop->timeout = timeout; 3205 3206 return count; 3207 } 3208 3209 static const struct file_operations fops_delay_drop_timeout = { 3210 .owner = THIS_MODULE, 3211 .open = simple_open, 3212 .write = delay_drop_timeout_write, 3213 .read = delay_drop_timeout_read, 3214 }; 3215 3216 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3217 struct mlx5_ib_multiport_info *mpi) 3218 { 3219 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3220 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3221 int comps; 3222 int err; 3223 int i; 3224 3225 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3226 3227 mlx5_core_mp_event_replay(ibdev->mdev, 3228 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3229 NULL); 3230 mlx5_core_mp_event_replay(mpi->mdev, 3231 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3232 NULL); 3233 3234 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3235 3236 spin_lock(&port->mp.mpi_lock); 3237 if (!mpi->ibdev) { 3238 spin_unlock(&port->mp.mpi_lock); 3239 return; 3240 } 3241 3242 mpi->ibdev = NULL; 3243 3244 spin_unlock(&port->mp.mpi_lock); 3245 if (mpi->mdev_events.notifier_call) 3246 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3247 mpi->mdev_events.notifier_call = NULL; 3248 mlx5_mdev_netdev_untrack(ibdev, port_num); 3249 spin_lock(&port->mp.mpi_lock); 3250 3251 comps = mpi->mdev_refcnt; 3252 if (comps) { 3253 mpi->unaffiliate = true; 3254 init_completion(&mpi->unref_comp); 3255 spin_unlock(&port->mp.mpi_lock); 3256 3257 for (i = 0; i < comps; i++) 3258 wait_for_completion(&mpi->unref_comp); 3259 3260 spin_lock(&port->mp.mpi_lock); 3261 mpi->unaffiliate = false; 3262 } 3263 3264 port->mp.mpi = NULL; 3265 3266 spin_unlock(&port->mp.mpi_lock); 3267 3268 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3269 3270 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3271 /* Log an error, still needed to cleanup the pointers and add 3272 * it back to the list. 3273 */ 3274 if (err) 3275 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3276 port_num + 1); 3277 3278 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3279 } 3280 3281 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3282 struct mlx5_ib_multiport_info *mpi) 3283 { 3284 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3285 u64 key; 3286 int err; 3287 3288 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3289 3290 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3291 if (ibdev->port[port_num].mp.mpi) { 3292 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3293 port_num + 1); 3294 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3295 return false; 3296 } 3297 3298 ibdev->port[port_num].mp.mpi = mpi; 3299 mpi->ibdev = ibdev; 3300 mpi->mdev_events.notifier_call = NULL; 3301 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3302 3303 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3304 if (err) 3305 goto unbind; 3306 3307 mlx5_mdev_netdev_track(ibdev, port_num); 3308 3309 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3310 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3311 3312 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3313 3314 key = mpi->mdev->priv.adev_idx; 3315 mlx5_core_mp_event_replay(mpi->mdev, 3316 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3317 &key); 3318 mlx5_core_mp_event_replay(ibdev->mdev, 3319 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3320 &key); 3321 3322 return true; 3323 3324 unbind: 3325 mlx5_ib_unbind_slave_port(ibdev, mpi); 3326 return false; 3327 } 3328 3329 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3330 { 3331 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3332 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3333 port_num + 1); 3334 struct mlx5_ib_multiport_info *mpi; 3335 int err; 3336 u32 i; 3337 3338 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3339 return 0; 3340 3341 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3342 &dev->sys_image_guid); 3343 if (err) 3344 return err; 3345 3346 err = mlx5_nic_vport_enable_roce(dev->mdev); 3347 if (err) 3348 return err; 3349 3350 mutex_lock(&mlx5_ib_multiport_mutex); 3351 for (i = 0; i < dev->num_ports; i++) { 3352 bool bound = false; 3353 3354 /* build a stub multiport info struct for the native port. */ 3355 if (i == port_num) { 3356 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3357 if (!mpi) { 3358 mutex_unlock(&mlx5_ib_multiport_mutex); 3359 mlx5_nic_vport_disable_roce(dev->mdev); 3360 return -ENOMEM; 3361 } 3362 3363 mpi->is_master = true; 3364 mpi->mdev = dev->mdev; 3365 mpi->sys_image_guid = dev->sys_image_guid; 3366 dev->port[i].mp.mpi = mpi; 3367 mpi->ibdev = dev; 3368 mpi = NULL; 3369 continue; 3370 } 3371 3372 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3373 list) { 3374 if (dev->sys_image_guid == mpi->sys_image_guid && 3375 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3376 bound = mlx5_ib_bind_slave_port(dev, mpi); 3377 } 3378 3379 if (bound) { 3380 dev_dbg(mpi->mdev->device, 3381 "removing port from unaffiliated list.\n"); 3382 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3383 list_del(&mpi->list); 3384 break; 3385 } 3386 } 3387 if (!bound) 3388 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3389 i + 1); 3390 } 3391 3392 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3393 mutex_unlock(&mlx5_ib_multiport_mutex); 3394 return err; 3395 } 3396 3397 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3398 { 3399 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3400 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3401 port_num + 1); 3402 u32 i; 3403 3404 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3405 return; 3406 3407 mutex_lock(&mlx5_ib_multiport_mutex); 3408 for (i = 0; i < dev->num_ports; i++) { 3409 if (dev->port[i].mp.mpi) { 3410 /* Destroy the native port stub */ 3411 if (i == port_num) { 3412 kfree(dev->port[i].mp.mpi); 3413 dev->port[i].mp.mpi = NULL; 3414 } else { 3415 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3416 i + 1); 3417 list_add_tail(&dev->port[i].mp.mpi->list, 3418 &mlx5_ib_unaffiliated_port_list); 3419 mlx5_ib_unbind_slave_port(dev, 3420 dev->port[i].mp.mpi); 3421 } 3422 } 3423 } 3424 3425 mlx5_ib_dbg(dev, "removing from devlist\n"); 3426 list_del(&dev->ib_dev_list); 3427 mutex_unlock(&mlx5_ib_multiport_mutex); 3428 3429 mlx5_nic_vport_disable_roce(dev->mdev); 3430 } 3431 3432 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3433 enum rdma_remove_reason why, 3434 struct uverbs_attr_bundle *attrs) 3435 { 3436 struct mlx5_user_mmap_entry *obj = uobject->object; 3437 3438 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3439 return 0; 3440 } 3441 3442 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3443 struct mlx5_user_mmap_entry *entry, 3444 size_t length) 3445 { 3446 return rdma_user_mmap_entry_insert_range( 3447 &c->ibucontext, &entry->rdma_entry, length, 3448 (MLX5_IB_MMAP_OFFSET_START << 16), 3449 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3450 } 3451 3452 static struct mlx5_user_mmap_entry * 3453 alloc_var_entry(struct mlx5_ib_ucontext *c) 3454 { 3455 struct mlx5_user_mmap_entry *entry; 3456 struct mlx5_var_table *var_table; 3457 u32 page_idx; 3458 int err; 3459 3460 var_table = &to_mdev(c->ibucontext.device)->var_table; 3461 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3462 if (!entry) 3463 return ERR_PTR(-ENOMEM); 3464 3465 mutex_lock(&var_table->bitmap_lock); 3466 page_idx = find_first_zero_bit(var_table->bitmap, 3467 var_table->num_var_hw_entries); 3468 if (page_idx >= var_table->num_var_hw_entries) { 3469 err = -ENOSPC; 3470 mutex_unlock(&var_table->bitmap_lock); 3471 goto end; 3472 } 3473 3474 set_bit(page_idx, var_table->bitmap); 3475 mutex_unlock(&var_table->bitmap_lock); 3476 3477 entry->address = var_table->hw_start_addr + 3478 (page_idx * var_table->stride_size); 3479 entry->page_idx = page_idx; 3480 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3481 3482 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3483 var_table->stride_size); 3484 if (err) 3485 goto err_insert; 3486 3487 return entry; 3488 3489 err_insert: 3490 mutex_lock(&var_table->bitmap_lock); 3491 clear_bit(page_idx, var_table->bitmap); 3492 mutex_unlock(&var_table->bitmap_lock); 3493 end: 3494 kfree(entry); 3495 return ERR_PTR(err); 3496 } 3497 3498 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3499 struct uverbs_attr_bundle *attrs) 3500 { 3501 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3502 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3503 struct mlx5_ib_ucontext *c; 3504 struct mlx5_user_mmap_entry *entry; 3505 u64 mmap_offset; 3506 u32 length; 3507 int err; 3508 3509 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3510 if (IS_ERR(c)) 3511 return PTR_ERR(c); 3512 3513 entry = alloc_var_entry(c); 3514 if (IS_ERR(entry)) 3515 return PTR_ERR(entry); 3516 3517 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3518 length = entry->rdma_entry.npages * PAGE_SIZE; 3519 uobj->object = entry; 3520 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3521 3522 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3523 &mmap_offset, sizeof(mmap_offset)); 3524 if (err) 3525 return err; 3526 3527 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3528 &entry->page_idx, sizeof(entry->page_idx)); 3529 if (err) 3530 return err; 3531 3532 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3533 &length, sizeof(length)); 3534 return err; 3535 } 3536 3537 DECLARE_UVERBS_NAMED_METHOD( 3538 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3539 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3540 MLX5_IB_OBJECT_VAR, 3541 UVERBS_ACCESS_NEW, 3542 UA_MANDATORY), 3543 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3544 UVERBS_ATTR_TYPE(u32), 3545 UA_MANDATORY), 3546 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3547 UVERBS_ATTR_TYPE(u32), 3548 UA_MANDATORY), 3549 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3550 UVERBS_ATTR_TYPE(u64), 3551 UA_MANDATORY)); 3552 3553 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3554 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3555 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3556 MLX5_IB_OBJECT_VAR, 3557 UVERBS_ACCESS_DESTROY, 3558 UA_MANDATORY)); 3559 3560 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3561 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3562 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3563 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3564 3565 static bool var_is_supported(struct ib_device *device) 3566 { 3567 struct mlx5_ib_dev *dev = to_mdev(device); 3568 3569 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3570 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3571 } 3572 3573 static struct mlx5_user_mmap_entry * 3574 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3575 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3576 { 3577 struct mlx5_user_mmap_entry *entry; 3578 struct mlx5_ib_dev *dev; 3579 u32 uar_index; 3580 int err; 3581 3582 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3583 if (!entry) 3584 return ERR_PTR(-ENOMEM); 3585 3586 dev = to_mdev(c->ibucontext.device); 3587 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3588 if (err) 3589 goto end; 3590 3591 entry->page_idx = uar_index; 3592 entry->address = uar_index2paddress(dev, uar_index); 3593 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3594 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3595 else 3596 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3597 3598 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3599 if (err) 3600 goto err_insert; 3601 3602 return entry; 3603 3604 err_insert: 3605 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3606 end: 3607 kfree(entry); 3608 return ERR_PTR(err); 3609 } 3610 3611 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3612 struct uverbs_attr_bundle *attrs) 3613 { 3614 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3615 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3616 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3617 struct mlx5_ib_ucontext *c; 3618 struct mlx5_user_mmap_entry *entry; 3619 u64 mmap_offset; 3620 u32 length; 3621 int err; 3622 3623 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3624 if (IS_ERR(c)) 3625 return PTR_ERR(c); 3626 3627 err = uverbs_get_const(&alloc_type, attrs, 3628 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3629 if (err) 3630 return err; 3631 3632 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3633 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3634 return -EOPNOTSUPP; 3635 3636 if (!to_mdev(c->ibucontext.device)->wc_support && 3637 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3638 return -EOPNOTSUPP; 3639 3640 entry = alloc_uar_entry(c, alloc_type); 3641 if (IS_ERR(entry)) 3642 return PTR_ERR(entry); 3643 3644 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3645 length = entry->rdma_entry.npages * PAGE_SIZE; 3646 uobj->object = entry; 3647 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3648 3649 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3650 &mmap_offset, sizeof(mmap_offset)); 3651 if (err) 3652 return err; 3653 3654 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3655 &entry->page_idx, sizeof(entry->page_idx)); 3656 if (err) 3657 return err; 3658 3659 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3660 &length, sizeof(length)); 3661 return err; 3662 } 3663 3664 DECLARE_UVERBS_NAMED_METHOD( 3665 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3666 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3667 MLX5_IB_OBJECT_UAR, 3668 UVERBS_ACCESS_NEW, 3669 UA_MANDATORY), 3670 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3671 enum mlx5_ib_uapi_uar_alloc_type, 3672 UA_MANDATORY), 3673 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3674 UVERBS_ATTR_TYPE(u32), 3675 UA_MANDATORY), 3676 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3677 UVERBS_ATTR_TYPE(u32), 3678 UA_MANDATORY), 3679 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3680 UVERBS_ATTR_TYPE(u64), 3681 UA_MANDATORY)); 3682 3683 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3684 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3685 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3686 MLX5_IB_OBJECT_UAR, 3687 UVERBS_ACCESS_DESTROY, 3688 UA_MANDATORY)); 3689 3690 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3691 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3692 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3693 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3694 3695 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3696 mlx5_ib_query_context, 3697 UVERBS_OBJECT_DEVICE, 3698 UVERBS_METHOD_QUERY_CONTEXT, 3699 UVERBS_ATTR_PTR_OUT( 3700 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3701 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3702 dump_fill_mkey), 3703 UA_MANDATORY)); 3704 3705 static const struct uapi_definition mlx5_ib_defs[] = { 3706 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3707 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3708 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3709 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3710 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3711 3712 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3713 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3714 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3715 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3716 {} 3717 }; 3718 3719 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3720 { 3721 mlx5_ib_cleanup_multiport_master(dev); 3722 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3723 mutex_destroy(&dev->cap_mask_mutex); 3724 WARN_ON(!xa_empty(&dev->sig_mrs)); 3725 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3726 mlx5r_macsec_dealloc_gids(dev); 3727 } 3728 3729 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3730 { 3731 struct mlx5_core_dev *mdev = dev->mdev; 3732 int err, i; 3733 3734 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3735 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3736 dev->ib_dev.phys_port_cnt = dev->num_ports; 3737 dev->ib_dev.dev.parent = mdev->device; 3738 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3739 3740 for (i = 0; i < dev->num_ports; i++) { 3741 spin_lock_init(&dev->port[i].mp.mpi_lock); 3742 rwlock_init(&dev->port[i].roce.netdev_lock); 3743 dev->port[i].roce.dev = dev; 3744 dev->port[i].roce.native_port_num = i + 1; 3745 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3746 } 3747 3748 err = mlx5r_cmd_query_special_mkeys(dev); 3749 if (err) 3750 return err; 3751 3752 err = mlx5r_macsec_init_gids_and_devlist(dev); 3753 if (err) 3754 return err; 3755 3756 err = mlx5_ib_init_multiport_master(dev); 3757 if (err) 3758 goto err; 3759 3760 err = set_has_smi_cap(dev); 3761 if (err) 3762 goto err_mp; 3763 3764 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3765 if (err) 3766 goto err_mp; 3767 3768 if (mlx5_use_mad_ifc(dev)) 3769 get_ext_port_caps(dev); 3770 3771 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 3772 3773 mutex_init(&dev->cap_mask_mutex); 3774 INIT_LIST_HEAD(&dev->qp_list); 3775 spin_lock_init(&dev->reset_flow_resource_lock); 3776 xa_init(&dev->odp_mkeys); 3777 xa_init(&dev->sig_mrs); 3778 atomic_set(&dev->mkey_var, 0); 3779 3780 spin_lock_init(&dev->dm.lock); 3781 dev->dm.dev = mdev; 3782 return 0; 3783 err_mp: 3784 mlx5_ib_cleanup_multiport_master(dev); 3785 err: 3786 mlx5r_macsec_dealloc_gids(dev); 3787 return err; 3788 } 3789 3790 static int mlx5_ib_enable_driver(struct ib_device *dev) 3791 { 3792 struct mlx5_ib_dev *mdev = to_mdev(dev); 3793 int ret; 3794 3795 ret = mlx5_ib_test_wc(mdev); 3796 mlx5_ib_dbg(mdev, "Write-Combining %s", 3797 mdev->wc_support ? "supported" : "not supported"); 3798 3799 return ret; 3800 } 3801 3802 static const struct ib_device_ops mlx5_ib_dev_ops = { 3803 .owner = THIS_MODULE, 3804 .driver_id = RDMA_DRIVER_MLX5, 3805 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3806 3807 .add_gid = mlx5_ib_add_gid, 3808 .alloc_mr = mlx5_ib_alloc_mr, 3809 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3810 .alloc_pd = mlx5_ib_alloc_pd, 3811 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3812 .attach_mcast = mlx5_ib_mcg_attach, 3813 .check_mr_status = mlx5_ib_check_mr_status, 3814 .create_ah = mlx5_ib_create_ah, 3815 .create_cq = mlx5_ib_create_cq, 3816 .create_qp = mlx5_ib_create_qp, 3817 .create_srq = mlx5_ib_create_srq, 3818 .create_user_ah = mlx5_ib_create_ah, 3819 .dealloc_pd = mlx5_ib_dealloc_pd, 3820 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3821 .del_gid = mlx5_ib_del_gid, 3822 .dereg_mr = mlx5_ib_dereg_mr, 3823 .destroy_ah = mlx5_ib_destroy_ah, 3824 .destroy_cq = mlx5_ib_destroy_cq, 3825 .destroy_qp = mlx5_ib_destroy_qp, 3826 .destroy_srq = mlx5_ib_destroy_srq, 3827 .detach_mcast = mlx5_ib_mcg_detach, 3828 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3829 .drain_rq = mlx5_ib_drain_rq, 3830 .drain_sq = mlx5_ib_drain_sq, 3831 .device_group = &mlx5_attr_group, 3832 .enable_driver = mlx5_ib_enable_driver, 3833 .get_dev_fw_str = get_dev_fw_str, 3834 .get_dma_mr = mlx5_ib_get_dma_mr, 3835 .get_link_layer = mlx5_ib_port_link_layer, 3836 .map_mr_sg = mlx5_ib_map_mr_sg, 3837 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3838 .mmap = mlx5_ib_mmap, 3839 .mmap_free = mlx5_ib_mmap_free, 3840 .modify_cq = mlx5_ib_modify_cq, 3841 .modify_device = mlx5_ib_modify_device, 3842 .modify_port = mlx5_ib_modify_port, 3843 .modify_qp = mlx5_ib_modify_qp, 3844 .modify_srq = mlx5_ib_modify_srq, 3845 .poll_cq = mlx5_ib_poll_cq, 3846 .post_recv = mlx5_ib_post_recv_nodrain, 3847 .post_send = mlx5_ib_post_send_nodrain, 3848 .post_srq_recv = mlx5_ib_post_srq_recv, 3849 .process_mad = mlx5_ib_process_mad, 3850 .query_ah = mlx5_ib_query_ah, 3851 .query_device = mlx5_ib_query_device, 3852 .query_gid = mlx5_ib_query_gid, 3853 .query_pkey = mlx5_ib_query_pkey, 3854 .query_qp = mlx5_ib_query_qp, 3855 .query_srq = mlx5_ib_query_srq, 3856 .query_ucontext = mlx5_ib_query_ucontext, 3857 .reg_user_mr = mlx5_ib_reg_user_mr, 3858 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3859 .req_notify_cq = mlx5_ib_arm_cq, 3860 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3861 .resize_cq = mlx5_ib_resize_cq, 3862 3863 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3864 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3865 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3866 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3867 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3868 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3869 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3870 }; 3871 3872 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3873 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3874 }; 3875 3876 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3877 .get_vf_config = mlx5_ib_get_vf_config, 3878 .get_vf_guid = mlx5_ib_get_vf_guid, 3879 .get_vf_stats = mlx5_ib_get_vf_stats, 3880 .set_vf_guid = mlx5_ib_set_vf_guid, 3881 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3882 }; 3883 3884 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3885 .alloc_mw = mlx5_ib_alloc_mw, 3886 .dealloc_mw = mlx5_ib_dealloc_mw, 3887 3888 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3889 }; 3890 3891 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3892 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3893 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3894 3895 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3896 }; 3897 3898 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3899 { 3900 struct mlx5_core_dev *mdev = dev->mdev; 3901 struct mlx5_var_table *var_table = &dev->var_table; 3902 u8 log_doorbell_bar_size; 3903 u8 log_doorbell_stride; 3904 u64 bar_size; 3905 3906 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3907 log_doorbell_bar_size); 3908 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3909 log_doorbell_stride); 3910 var_table->hw_start_addr = dev->mdev->bar_addr + 3911 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3912 doorbell_bar_offset); 3913 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3914 var_table->stride_size = 1ULL << log_doorbell_stride; 3915 var_table->num_var_hw_entries = div_u64(bar_size, 3916 var_table->stride_size); 3917 mutex_init(&var_table->bitmap_lock); 3918 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3919 GFP_KERNEL); 3920 return (var_table->bitmap) ? 0 : -ENOMEM; 3921 } 3922 3923 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3924 { 3925 bitmap_free(dev->var_table.bitmap); 3926 } 3927 3928 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3929 { 3930 struct mlx5_core_dev *mdev = dev->mdev; 3931 int err; 3932 3933 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3934 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3935 ib_set_device_ops(&dev->ib_dev, 3936 &mlx5_ib_dev_ipoib_enhanced_ops); 3937 3938 if (mlx5_core_is_pf(mdev)) 3939 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3940 3941 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3942 3943 if (MLX5_CAP_GEN(mdev, imaicl)) 3944 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3945 3946 if (MLX5_CAP_GEN(mdev, xrc)) 3947 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3948 3949 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3950 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3951 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3952 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3953 3954 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3955 3956 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3957 dev->ib_dev.driver_def = mlx5_ib_defs; 3958 3959 err = init_node_data(dev); 3960 if (err) 3961 return err; 3962 3963 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3964 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3965 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3966 mutex_init(&dev->lb.mutex); 3967 3968 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3969 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3970 err = mlx5_ib_init_var_table(dev); 3971 if (err) 3972 return err; 3973 } 3974 3975 dev->ib_dev.use_cq_dim = true; 3976 3977 return 0; 3978 } 3979 3980 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3981 .get_port_immutable = mlx5_port_immutable, 3982 .query_port = mlx5_ib_query_port, 3983 }; 3984 3985 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3986 { 3987 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3988 return 0; 3989 } 3990 3991 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3992 .get_port_immutable = mlx5_port_rep_immutable, 3993 .query_port = mlx5_ib_rep_query_port, 3994 .query_pkey = mlx5_ib_rep_query_pkey, 3995 }; 3996 3997 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3998 { 3999 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4000 return 0; 4001 } 4002 4003 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4004 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4005 .create_wq = mlx5_ib_create_wq, 4006 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4007 .destroy_wq = mlx5_ib_destroy_wq, 4008 .get_netdev = mlx5_ib_get_netdev, 4009 .modify_wq = mlx5_ib_modify_wq, 4010 4011 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4012 ib_rwq_ind_tbl), 4013 }; 4014 4015 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4016 { 4017 struct mlx5_core_dev *mdev = dev->mdev; 4018 enum rdma_link_layer ll; 4019 int port_type_cap; 4020 u32 port_num = 0; 4021 int err; 4022 4023 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4024 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4025 4026 if (ll == IB_LINK_LAYER_ETHERNET) { 4027 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4028 4029 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4030 4031 /* Register only for native ports */ 4032 mlx5_mdev_netdev_track(dev, port_num); 4033 4034 err = mlx5_enable_eth(dev); 4035 if (err) 4036 goto cleanup; 4037 } 4038 4039 return 0; 4040 cleanup: 4041 mlx5_mdev_netdev_untrack(dev, port_num); 4042 return err; 4043 } 4044 4045 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4046 { 4047 struct mlx5_core_dev *mdev = dev->mdev; 4048 enum rdma_link_layer ll; 4049 int port_type_cap; 4050 u32 port_num; 4051 4052 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4053 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4054 4055 if (ll == IB_LINK_LAYER_ETHERNET) { 4056 mlx5_disable_eth(dev); 4057 4058 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4059 mlx5_mdev_netdev_untrack(dev, port_num); 4060 } 4061 } 4062 4063 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4064 { 4065 mlx5_ib_init_cong_debugfs(dev, 4066 mlx5_core_native_port_num(dev->mdev) - 1); 4067 return 0; 4068 } 4069 4070 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4071 { 4072 mlx5_ib_cleanup_cong_debugfs(dev, 4073 mlx5_core_native_port_num(dev->mdev) - 1); 4074 } 4075 4076 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4077 { 4078 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4079 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4080 } 4081 4082 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4083 { 4084 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4085 } 4086 4087 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4088 { 4089 int err; 4090 4091 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4092 if (err) 4093 return err; 4094 4095 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4096 if (err) 4097 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4098 4099 return err; 4100 } 4101 4102 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4103 { 4104 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4105 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4106 } 4107 4108 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4109 { 4110 const char *name; 4111 4112 if (!mlx5_lag_is_active(dev->mdev)) 4113 name = "mlx5_%d"; 4114 else 4115 name = "mlx5_bond_%d"; 4116 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4117 } 4118 4119 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4120 { 4121 mlx5_mkey_cache_cleanup(dev); 4122 mlx5r_umr_resource_cleanup(dev); 4123 } 4124 4125 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4126 { 4127 ib_unregister_device(&dev->ib_dev); 4128 } 4129 4130 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4131 { 4132 int ret; 4133 4134 ret = mlx5r_umr_resource_init(dev); 4135 if (ret) 4136 return ret; 4137 4138 ret = mlx5_mkey_cache_init(dev); 4139 if (ret) 4140 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4141 return ret; 4142 } 4143 4144 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4145 { 4146 struct dentry *root; 4147 4148 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4149 return 0; 4150 4151 mutex_init(&dev->delay_drop.lock); 4152 dev->delay_drop.dev = dev; 4153 dev->delay_drop.activate = false; 4154 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4155 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4156 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4157 atomic_set(&dev->delay_drop.events_cnt, 0); 4158 4159 if (!mlx5_debugfs_root) 4160 return 0; 4161 4162 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4163 dev->delay_drop.dir_debugfs = root; 4164 4165 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4166 &dev->delay_drop.events_cnt); 4167 debugfs_create_atomic_t("num_rqs", 0400, root, 4168 &dev->delay_drop.rqs_cnt); 4169 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4170 &fops_delay_drop_timeout); 4171 return 0; 4172 } 4173 4174 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4175 { 4176 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4177 return; 4178 4179 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4180 if (!dev->delay_drop.dir_debugfs) 4181 return; 4182 4183 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4184 dev->delay_drop.dir_debugfs = NULL; 4185 } 4186 4187 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4188 { 4189 struct mlx5_ib_resources *devr = &dev->devr; 4190 int port; 4191 4192 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4193 INIT_WORK(&devr->ports[port].pkey_change_work, 4194 pkey_change_handler); 4195 4196 dev->mdev_events.notifier_call = mlx5_ib_event; 4197 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4198 4199 mlx5r_macsec_event_register(dev); 4200 4201 return 0; 4202 } 4203 4204 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4205 { 4206 struct mlx5_ib_resources *devr = &dev->devr; 4207 int port; 4208 4209 mlx5r_macsec_event_unregister(dev); 4210 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4211 4212 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4213 cancel_work_sync(&devr->ports[port].pkey_change_work); 4214 } 4215 4216 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4217 const struct mlx5_ib_profile *profile, 4218 int stage) 4219 { 4220 dev->ib_active = false; 4221 4222 /* Number of stages to cleanup */ 4223 while (stage) { 4224 stage--; 4225 if (profile->stage[stage].cleanup) 4226 profile->stage[stage].cleanup(dev); 4227 } 4228 4229 kfree(dev->port); 4230 ib_dealloc_device(&dev->ib_dev); 4231 } 4232 4233 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4234 const struct mlx5_ib_profile *profile) 4235 { 4236 int err; 4237 int i; 4238 4239 dev->profile = profile; 4240 4241 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4242 if (profile->stage[i].init) { 4243 err = profile->stage[i].init(dev); 4244 if (err) 4245 goto err_out; 4246 } 4247 } 4248 4249 dev->ib_active = true; 4250 return 0; 4251 4252 err_out: 4253 /* Clean up stages which were initialized */ 4254 while (i) { 4255 i--; 4256 if (profile->stage[i].cleanup) 4257 profile->stage[i].cleanup(dev); 4258 } 4259 return -ENOMEM; 4260 } 4261 4262 static const struct mlx5_ib_profile pf_profile = { 4263 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4264 mlx5_ib_stage_init_init, 4265 mlx5_ib_stage_init_cleanup), 4266 STAGE_CREATE(MLX5_IB_STAGE_FS, 4267 mlx5_ib_fs_init, 4268 mlx5_ib_fs_cleanup), 4269 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4270 mlx5_ib_stage_caps_init, 4271 mlx5_ib_stage_caps_cleanup), 4272 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4273 mlx5_ib_stage_non_default_cb, 4274 NULL), 4275 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4276 mlx5_ib_roce_init, 4277 mlx5_ib_roce_cleanup), 4278 STAGE_CREATE(MLX5_IB_STAGE_QP, 4279 mlx5_init_qp_table, 4280 mlx5_cleanup_qp_table), 4281 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4282 mlx5_init_srq_table, 4283 mlx5_cleanup_srq_table), 4284 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4285 mlx5_ib_dev_res_init, 4286 mlx5_ib_dev_res_cleanup), 4287 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4288 mlx5_ib_odp_init_one, 4289 mlx5_ib_odp_cleanup_one), 4290 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4291 mlx5_ib_counters_init, 4292 mlx5_ib_counters_cleanup), 4293 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4294 mlx5_ib_stage_cong_debugfs_init, 4295 mlx5_ib_stage_cong_debugfs_cleanup), 4296 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4297 mlx5_ib_stage_uar_init, 4298 mlx5_ib_stage_uar_cleanup), 4299 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4300 mlx5_ib_stage_bfrag_init, 4301 mlx5_ib_stage_bfrag_cleanup), 4302 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4303 NULL, 4304 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4305 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4306 mlx5_ib_devx_init, 4307 mlx5_ib_devx_cleanup), 4308 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4309 mlx5_ib_stage_ib_reg_init, 4310 mlx5_ib_stage_ib_reg_cleanup), 4311 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4312 mlx5_ib_stage_dev_notifier_init, 4313 mlx5_ib_stage_dev_notifier_cleanup), 4314 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4315 mlx5_ib_stage_post_ib_reg_umr_init, 4316 NULL), 4317 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4318 mlx5_ib_stage_delay_drop_init, 4319 mlx5_ib_stage_delay_drop_cleanup), 4320 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4321 mlx5_ib_restrack_init, 4322 NULL), 4323 }; 4324 4325 const struct mlx5_ib_profile raw_eth_profile = { 4326 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4327 mlx5_ib_stage_init_init, 4328 mlx5_ib_stage_init_cleanup), 4329 STAGE_CREATE(MLX5_IB_STAGE_FS, 4330 mlx5_ib_fs_init, 4331 mlx5_ib_fs_cleanup), 4332 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4333 mlx5_ib_stage_caps_init, 4334 mlx5_ib_stage_caps_cleanup), 4335 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4336 mlx5_ib_stage_raw_eth_non_default_cb, 4337 NULL), 4338 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4339 mlx5_ib_roce_init, 4340 mlx5_ib_roce_cleanup), 4341 STAGE_CREATE(MLX5_IB_STAGE_QP, 4342 mlx5_init_qp_table, 4343 mlx5_cleanup_qp_table), 4344 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4345 mlx5_init_srq_table, 4346 mlx5_cleanup_srq_table), 4347 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4348 mlx5_ib_dev_res_init, 4349 mlx5_ib_dev_res_cleanup), 4350 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4351 mlx5_ib_counters_init, 4352 mlx5_ib_counters_cleanup), 4353 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4354 mlx5_ib_stage_cong_debugfs_init, 4355 mlx5_ib_stage_cong_debugfs_cleanup), 4356 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4357 mlx5_ib_stage_uar_init, 4358 mlx5_ib_stage_uar_cleanup), 4359 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4360 mlx5_ib_stage_bfrag_init, 4361 mlx5_ib_stage_bfrag_cleanup), 4362 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4363 NULL, 4364 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4365 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4366 mlx5_ib_devx_init, 4367 mlx5_ib_devx_cleanup), 4368 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4369 mlx5_ib_stage_ib_reg_init, 4370 mlx5_ib_stage_ib_reg_cleanup), 4371 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4372 mlx5_ib_stage_dev_notifier_init, 4373 mlx5_ib_stage_dev_notifier_cleanup), 4374 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4375 mlx5_ib_stage_post_ib_reg_umr_init, 4376 NULL), 4377 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4378 mlx5_ib_stage_delay_drop_init, 4379 mlx5_ib_stage_delay_drop_cleanup), 4380 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4381 mlx5_ib_restrack_init, 4382 NULL), 4383 }; 4384 4385 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4386 const struct auxiliary_device_id *id) 4387 { 4388 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4389 struct mlx5_core_dev *mdev = idev->mdev; 4390 struct mlx5_ib_multiport_info *mpi; 4391 struct mlx5_ib_dev *dev; 4392 bool bound = false; 4393 int err; 4394 4395 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4396 if (!mpi) 4397 return -ENOMEM; 4398 4399 mpi->mdev = mdev; 4400 err = mlx5_query_nic_vport_system_image_guid(mdev, 4401 &mpi->sys_image_guid); 4402 if (err) { 4403 kfree(mpi); 4404 return err; 4405 } 4406 4407 mutex_lock(&mlx5_ib_multiport_mutex); 4408 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4409 if (dev->sys_image_guid == mpi->sys_image_guid) 4410 bound = mlx5_ib_bind_slave_port(dev, mpi); 4411 4412 if (bound) { 4413 rdma_roce_rescan_device(&dev->ib_dev); 4414 mpi->ibdev->ib_active = true; 4415 break; 4416 } 4417 } 4418 4419 if (!bound) { 4420 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4421 dev_dbg(mdev->device, 4422 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4423 } 4424 mutex_unlock(&mlx5_ib_multiport_mutex); 4425 4426 auxiliary_set_drvdata(adev, mpi); 4427 return 0; 4428 } 4429 4430 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4431 { 4432 struct mlx5_ib_multiport_info *mpi; 4433 4434 mpi = auxiliary_get_drvdata(adev); 4435 mutex_lock(&mlx5_ib_multiport_mutex); 4436 if (mpi->ibdev) 4437 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4438 else 4439 list_del(&mpi->list); 4440 mutex_unlock(&mlx5_ib_multiport_mutex); 4441 kfree(mpi); 4442 } 4443 4444 static int mlx5r_probe(struct auxiliary_device *adev, 4445 const struct auxiliary_device_id *id) 4446 { 4447 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4448 struct mlx5_core_dev *mdev = idev->mdev; 4449 const struct mlx5_ib_profile *profile; 4450 int port_type_cap, num_ports, ret; 4451 enum rdma_link_layer ll; 4452 struct mlx5_ib_dev *dev; 4453 4454 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4455 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4456 4457 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4458 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4459 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4460 if (!dev) 4461 return -ENOMEM; 4462 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4463 GFP_KERNEL); 4464 if (!dev->port) { 4465 ib_dealloc_device(&dev->ib_dev); 4466 return -ENOMEM; 4467 } 4468 4469 dev->mdev = mdev; 4470 dev->num_ports = num_ports; 4471 4472 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4473 profile = &raw_eth_profile; 4474 else 4475 profile = &pf_profile; 4476 4477 ret = __mlx5_ib_add(dev, profile); 4478 if (ret) { 4479 kfree(dev->port); 4480 ib_dealloc_device(&dev->ib_dev); 4481 return ret; 4482 } 4483 4484 auxiliary_set_drvdata(adev, dev); 4485 return 0; 4486 } 4487 4488 static void mlx5r_remove(struct auxiliary_device *adev) 4489 { 4490 struct mlx5_ib_dev *dev; 4491 4492 dev = auxiliary_get_drvdata(adev); 4493 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4494 } 4495 4496 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4497 { .name = MLX5_ADEV_NAME ".multiport", }, 4498 {}, 4499 }; 4500 4501 static const struct auxiliary_device_id mlx5r_id_table[] = { 4502 { .name = MLX5_ADEV_NAME ".rdma", }, 4503 {}, 4504 }; 4505 4506 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4507 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4508 4509 static struct auxiliary_driver mlx5r_mp_driver = { 4510 .name = "multiport", 4511 .probe = mlx5r_mp_probe, 4512 .remove = mlx5r_mp_remove, 4513 .id_table = mlx5r_mp_id_table, 4514 }; 4515 4516 static struct auxiliary_driver mlx5r_driver = { 4517 .name = "rdma", 4518 .probe = mlx5r_probe, 4519 .remove = mlx5r_remove, 4520 .id_table = mlx5r_id_table, 4521 }; 4522 4523 static int __init mlx5_ib_init(void) 4524 { 4525 int ret; 4526 4527 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4528 if (!xlt_emergency_page) 4529 return -ENOMEM; 4530 4531 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4532 if (!mlx5_ib_event_wq) { 4533 free_page((unsigned long)xlt_emergency_page); 4534 return -ENOMEM; 4535 } 4536 4537 ret = mlx5_ib_qp_event_init(); 4538 if (ret) 4539 goto qp_event_err; 4540 4541 mlx5_ib_odp_init(); 4542 ret = mlx5r_rep_init(); 4543 if (ret) 4544 goto rep_err; 4545 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4546 if (ret) 4547 goto mp_err; 4548 ret = auxiliary_driver_register(&mlx5r_driver); 4549 if (ret) 4550 goto drv_err; 4551 return 0; 4552 4553 drv_err: 4554 auxiliary_driver_unregister(&mlx5r_mp_driver); 4555 mp_err: 4556 mlx5r_rep_cleanup(); 4557 rep_err: 4558 mlx5_ib_qp_event_cleanup(); 4559 qp_event_err: 4560 destroy_workqueue(mlx5_ib_event_wq); 4561 free_page((unsigned long)xlt_emergency_page); 4562 return ret; 4563 } 4564 4565 static void __exit mlx5_ib_cleanup(void) 4566 { 4567 auxiliary_driver_unregister(&mlx5r_driver); 4568 auxiliary_driver_unregister(&mlx5r_mp_driver); 4569 mlx5r_rep_cleanup(); 4570 4571 mlx5_ib_qp_event_cleanup(); 4572 destroy_workqueue(mlx5_ib_event_wq); 4573 free_page((unsigned long)xlt_emergency_page); 4574 } 4575 4576 module_init(mlx5_ib_init); 4577 module_exit(mlx5_ib_cleanup); 4578