1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/sched/mm.h> 45 #include <linux/sched/task.h> 46 #include <linux/delay.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_cache.h> 50 #include <linux/mlx5/port.h> 51 #include <linux/mlx5/vport.h> 52 #include <linux/list.h> 53 #include <rdma/ib_smi.h> 54 #include <rdma/ib_umem.h> 55 #include <linux/in.h> 56 #include <linux/etherdevice.h> 57 #include <linux/mlx5/fs.h> 58 #include <linux/mlx5/vport.h> 59 #include "mlx5_ib.h" 60 #include "cmd.h" 61 62 #define DRIVER_NAME "mlx5_ib" 63 #define DRIVER_VERSION "5.0-0" 64 65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 67 MODULE_LICENSE("Dual BSD/GPL"); 68 MODULE_VERSION(DRIVER_VERSION); 69 70 static char mlx5_version[] = 71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 72 DRIVER_VERSION "\n"; 73 74 enum { 75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 76 }; 77 78 static enum rdma_link_layer 79 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 80 { 81 switch (port_type_cap) { 82 case MLX5_CAP_PORT_TYPE_IB: 83 return IB_LINK_LAYER_INFINIBAND; 84 case MLX5_CAP_PORT_TYPE_ETH: 85 return IB_LINK_LAYER_ETHERNET; 86 default: 87 return IB_LINK_LAYER_UNSPECIFIED; 88 } 89 } 90 91 static enum rdma_link_layer 92 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 93 { 94 struct mlx5_ib_dev *dev = to_mdev(device); 95 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 96 97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 98 } 99 100 static int mlx5_netdev_event(struct notifier_block *this, 101 unsigned long event, void *ptr) 102 { 103 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 104 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 105 roce.nb); 106 107 switch (event) { 108 case NETDEV_REGISTER: 109 case NETDEV_UNREGISTER: 110 write_lock(&ibdev->roce.netdev_lock); 111 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 112 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 113 NULL : ndev; 114 write_unlock(&ibdev->roce.netdev_lock); 115 break; 116 117 case NETDEV_UP: 118 case NETDEV_DOWN: { 119 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 120 struct net_device *upper = NULL; 121 122 if (lag_ndev) { 123 upper = netdev_master_upper_dev_get(lag_ndev); 124 dev_put(lag_ndev); 125 } 126 127 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 128 && ibdev->ib_active) { 129 struct ib_event ibev = { }; 130 131 ibev.device = &ibdev->ib_dev; 132 ibev.event = (event == NETDEV_UP) ? 133 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 134 ibev.element.port_num = 1; 135 ib_dispatch_event(&ibev); 136 } 137 break; 138 } 139 140 default: 141 break; 142 } 143 144 return NOTIFY_DONE; 145 } 146 147 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 148 u8 port_num) 149 { 150 struct mlx5_ib_dev *ibdev = to_mdev(device); 151 struct net_device *ndev; 152 153 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 154 if (ndev) 155 return ndev; 156 157 /* Ensure ndev does not disappear before we invoke dev_hold() 158 */ 159 read_lock(&ibdev->roce.netdev_lock); 160 ndev = ibdev->roce.netdev; 161 if (ndev) 162 dev_hold(ndev); 163 read_unlock(&ibdev->roce.netdev_lock); 164 165 return ndev; 166 } 167 168 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 169 u8 *active_width) 170 { 171 switch (eth_proto_oper) { 172 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 174 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 175 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 176 *active_width = IB_WIDTH_1X; 177 *active_speed = IB_SPEED_SDR; 178 break; 179 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 184 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 185 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 186 *active_width = IB_WIDTH_1X; 187 *active_speed = IB_SPEED_QDR; 188 break; 189 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 190 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 191 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 192 *active_width = IB_WIDTH_1X; 193 *active_speed = IB_SPEED_EDR; 194 break; 195 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 197 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 198 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 199 *active_width = IB_WIDTH_4X; 200 *active_speed = IB_SPEED_QDR; 201 break; 202 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 203 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 204 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_HDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 209 *active_width = IB_WIDTH_4X; 210 *active_speed = IB_SPEED_FDR; 211 break; 212 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 214 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 215 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 216 *active_width = IB_WIDTH_4X; 217 *active_speed = IB_SPEED_EDR; 218 break; 219 default: 220 return -EINVAL; 221 } 222 223 return 0; 224 } 225 226 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 227 struct ib_port_attr *props) 228 { 229 struct mlx5_ib_dev *dev = to_mdev(device); 230 struct mlx5_core_dev *mdev = dev->mdev; 231 struct net_device *ndev, *upper; 232 enum ib_mtu ndev_ib_mtu; 233 u16 qkey_viol_cntr; 234 u32 eth_prot_oper; 235 int err; 236 237 /* Possible bad flows are checked before filling out props so in case 238 * of an error it will still be zeroed out. 239 */ 240 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 241 if (err) 242 return err; 243 244 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 245 &props->active_width); 246 247 props->port_cap_flags |= IB_PORT_CM_SUP; 248 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 249 250 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 251 roce_address_table_size); 252 props->max_mtu = IB_MTU_4096; 253 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 254 props->pkey_tbl_len = 1; 255 props->state = IB_PORT_DOWN; 256 props->phys_state = 3; 257 258 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 259 props->qkey_viol_cntr = qkey_viol_cntr; 260 261 ndev = mlx5_ib_get_netdev(device, port_num); 262 if (!ndev) 263 return 0; 264 265 if (mlx5_lag_is_active(dev->mdev)) { 266 rcu_read_lock(); 267 upper = netdev_master_upper_dev_get_rcu(ndev); 268 if (upper) { 269 dev_put(ndev); 270 ndev = upper; 271 dev_hold(ndev); 272 } 273 rcu_read_unlock(); 274 } 275 276 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 277 props->state = IB_PORT_ACTIVE; 278 props->phys_state = 5; 279 } 280 281 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 282 283 dev_put(ndev); 284 285 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 286 return 0; 287 } 288 289 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 290 unsigned int index, const union ib_gid *gid, 291 const struct ib_gid_attr *attr) 292 { 293 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 294 u8 roce_version = 0; 295 u8 roce_l3_type = 0; 296 bool vlan = false; 297 u8 mac[ETH_ALEN]; 298 u16 vlan_id = 0; 299 300 if (gid) { 301 gid_type = attr->gid_type; 302 ether_addr_copy(mac, attr->ndev->dev_addr); 303 304 if (is_vlan_dev(attr->ndev)) { 305 vlan = true; 306 vlan_id = vlan_dev_vlan_id(attr->ndev); 307 } 308 } 309 310 switch (gid_type) { 311 case IB_GID_TYPE_IB: 312 roce_version = MLX5_ROCE_VERSION_1; 313 break; 314 case IB_GID_TYPE_ROCE_UDP_ENCAP: 315 roce_version = MLX5_ROCE_VERSION_2; 316 if (ipv6_addr_v4mapped((void *)gid)) 317 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 318 else 319 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 320 break; 321 322 default: 323 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 324 } 325 326 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 327 roce_l3_type, gid->raw, mac, vlan, 328 vlan_id); 329 } 330 331 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 332 unsigned int index, const union ib_gid *gid, 333 const struct ib_gid_attr *attr, 334 __always_unused void **context) 335 { 336 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 337 } 338 339 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 340 unsigned int index, __always_unused void **context) 341 { 342 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 343 } 344 345 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 346 int index) 347 { 348 struct ib_gid_attr attr; 349 union ib_gid gid; 350 351 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 352 return 0; 353 354 if (!attr.ndev) 355 return 0; 356 357 dev_put(attr.ndev); 358 359 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 360 return 0; 361 362 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 363 } 364 365 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 366 int index, enum ib_gid_type *gid_type) 367 { 368 struct ib_gid_attr attr; 369 union ib_gid gid; 370 int ret; 371 372 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 373 if (ret) 374 return ret; 375 376 if (!attr.ndev) 377 return -ENODEV; 378 379 dev_put(attr.ndev); 380 381 *gid_type = attr.gid_type; 382 383 return 0; 384 } 385 386 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 387 { 388 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 389 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 390 return 0; 391 } 392 393 enum { 394 MLX5_VPORT_ACCESS_METHOD_MAD, 395 MLX5_VPORT_ACCESS_METHOD_HCA, 396 MLX5_VPORT_ACCESS_METHOD_NIC, 397 }; 398 399 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 400 { 401 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 402 return MLX5_VPORT_ACCESS_METHOD_MAD; 403 404 if (mlx5_ib_port_link_layer(ibdev, 1) == 405 IB_LINK_LAYER_ETHERNET) 406 return MLX5_VPORT_ACCESS_METHOD_NIC; 407 408 return MLX5_VPORT_ACCESS_METHOD_HCA; 409 } 410 411 static void get_atomic_caps(struct mlx5_ib_dev *dev, 412 struct ib_device_attr *props) 413 { 414 u8 tmp; 415 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 416 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 417 u8 atomic_req_8B_endianness_mode = 418 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 419 420 /* Check if HW supports 8 bytes standard atomic operations and capable 421 * of host endianness respond 422 */ 423 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 424 if (((atomic_operations & tmp) == tmp) && 425 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 426 (atomic_req_8B_endianness_mode)) { 427 props->atomic_cap = IB_ATOMIC_HCA; 428 } else { 429 props->atomic_cap = IB_ATOMIC_NONE; 430 } 431 } 432 433 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 434 __be64 *sys_image_guid) 435 { 436 struct mlx5_ib_dev *dev = to_mdev(ibdev); 437 struct mlx5_core_dev *mdev = dev->mdev; 438 u64 tmp; 439 int err; 440 441 switch (mlx5_get_vport_access_method(ibdev)) { 442 case MLX5_VPORT_ACCESS_METHOD_MAD: 443 return mlx5_query_mad_ifc_system_image_guid(ibdev, 444 sys_image_guid); 445 446 case MLX5_VPORT_ACCESS_METHOD_HCA: 447 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 448 break; 449 450 case MLX5_VPORT_ACCESS_METHOD_NIC: 451 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 452 break; 453 454 default: 455 return -EINVAL; 456 } 457 458 if (!err) 459 *sys_image_guid = cpu_to_be64(tmp); 460 461 return err; 462 463 } 464 465 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 466 u16 *max_pkeys) 467 { 468 struct mlx5_ib_dev *dev = to_mdev(ibdev); 469 struct mlx5_core_dev *mdev = dev->mdev; 470 471 switch (mlx5_get_vport_access_method(ibdev)) { 472 case MLX5_VPORT_ACCESS_METHOD_MAD: 473 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 case MLX5_VPORT_ACCESS_METHOD_NIC: 477 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 478 pkey_table_size)); 479 return 0; 480 481 default: 482 return -EINVAL; 483 } 484 } 485 486 static int mlx5_query_vendor_id(struct ib_device *ibdev, 487 u32 *vendor_id) 488 { 489 struct mlx5_ib_dev *dev = to_mdev(ibdev); 490 491 switch (mlx5_get_vport_access_method(ibdev)) { 492 case MLX5_VPORT_ACCESS_METHOD_MAD: 493 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 494 495 case MLX5_VPORT_ACCESS_METHOD_HCA: 496 case MLX5_VPORT_ACCESS_METHOD_NIC: 497 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 498 499 default: 500 return -EINVAL; 501 } 502 } 503 504 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 505 __be64 *node_guid) 506 { 507 u64 tmp; 508 int err; 509 510 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 511 case MLX5_VPORT_ACCESS_METHOD_MAD: 512 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 513 514 case MLX5_VPORT_ACCESS_METHOD_HCA: 515 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 516 break; 517 518 case MLX5_VPORT_ACCESS_METHOD_NIC: 519 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 520 break; 521 522 default: 523 return -EINVAL; 524 } 525 526 if (!err) 527 *node_guid = cpu_to_be64(tmp); 528 529 return err; 530 } 531 532 struct mlx5_reg_node_desc { 533 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 534 }; 535 536 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 537 { 538 struct mlx5_reg_node_desc in; 539 540 if (mlx5_use_mad_ifc(dev)) 541 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 542 543 memset(&in, 0, sizeof(in)); 544 545 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 546 sizeof(struct mlx5_reg_node_desc), 547 MLX5_REG_NODE_DESC, 0, 0); 548 } 549 550 static int mlx5_ib_query_device(struct ib_device *ibdev, 551 struct ib_device_attr *props, 552 struct ib_udata *uhw) 553 { 554 struct mlx5_ib_dev *dev = to_mdev(ibdev); 555 struct mlx5_core_dev *mdev = dev->mdev; 556 int err = -ENOMEM; 557 int max_sq_desc; 558 int max_rq_sg; 559 int max_sq_sg; 560 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 561 struct mlx5_ib_query_device_resp resp = {}; 562 size_t resp_len; 563 u64 max_tso; 564 565 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 566 if (uhw->outlen && uhw->outlen < resp_len) 567 return -EINVAL; 568 else 569 resp.response_length = resp_len; 570 571 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 572 return -EINVAL; 573 574 memset(props, 0, sizeof(*props)); 575 err = mlx5_query_system_image_guid(ibdev, 576 &props->sys_image_guid); 577 if (err) 578 return err; 579 580 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 581 if (err) 582 return err; 583 584 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 585 if (err) 586 return err; 587 588 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 589 (fw_rev_min(dev->mdev) << 16) | 590 fw_rev_sub(dev->mdev); 591 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 592 IB_DEVICE_PORT_ACTIVE_EVENT | 593 IB_DEVICE_SYS_IMAGE_GUID | 594 IB_DEVICE_RC_RNR_NAK_GEN; 595 596 if (MLX5_CAP_GEN(mdev, pkv)) 597 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 598 if (MLX5_CAP_GEN(mdev, qkv)) 599 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 600 if (MLX5_CAP_GEN(mdev, apm)) 601 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 602 if (MLX5_CAP_GEN(mdev, xrc)) 603 props->device_cap_flags |= IB_DEVICE_XRC; 604 if (MLX5_CAP_GEN(mdev, imaicl)) { 605 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 606 IB_DEVICE_MEM_WINDOW_TYPE_2B; 607 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 608 /* We support 'Gappy' memory registration too */ 609 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 610 } 611 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 612 if (MLX5_CAP_GEN(mdev, sho)) { 613 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 614 /* At this stage no support for signature handover */ 615 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 616 IB_PROT_T10DIF_TYPE_2 | 617 IB_PROT_T10DIF_TYPE_3; 618 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 619 IB_GUARD_T10DIF_CSUM; 620 } 621 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 622 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 623 624 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 625 if (MLX5_CAP_ETH(mdev, csum_cap)) { 626 /* Legacy bit to support old userspace libraries */ 627 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 628 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 629 } 630 631 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 632 props->raw_packet_caps |= 633 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 634 635 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 636 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 637 if (max_tso) { 638 resp.tso_caps.max_tso = 1 << max_tso; 639 resp.tso_caps.supported_qpts |= 640 1 << IB_QPT_RAW_PACKET; 641 resp.response_length += sizeof(resp.tso_caps); 642 } 643 } 644 645 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 646 resp.rss_caps.rx_hash_function = 647 MLX5_RX_HASH_FUNC_TOEPLITZ; 648 resp.rss_caps.rx_hash_fields_mask = 649 MLX5_RX_HASH_SRC_IPV4 | 650 MLX5_RX_HASH_DST_IPV4 | 651 MLX5_RX_HASH_SRC_IPV6 | 652 MLX5_RX_HASH_DST_IPV6 | 653 MLX5_RX_HASH_SRC_PORT_TCP | 654 MLX5_RX_HASH_DST_PORT_TCP | 655 MLX5_RX_HASH_SRC_PORT_UDP | 656 MLX5_RX_HASH_DST_PORT_UDP; 657 resp.response_length += sizeof(resp.rss_caps); 658 } 659 } else { 660 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 661 resp.response_length += sizeof(resp.tso_caps); 662 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 663 resp.response_length += sizeof(resp.rss_caps); 664 } 665 666 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 667 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 668 props->device_cap_flags |= IB_DEVICE_UD_TSO; 669 } 670 671 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 672 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 673 /* Legacy bit to support old userspace libraries */ 674 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 675 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 676 } 677 678 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 679 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 680 681 props->vendor_part_id = mdev->pdev->device; 682 props->hw_ver = mdev->pdev->revision; 683 684 props->max_mr_size = ~0ull; 685 props->page_size_cap = ~(min_page_size - 1); 686 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 687 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 688 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 689 sizeof(struct mlx5_wqe_data_seg); 690 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 691 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 692 sizeof(struct mlx5_wqe_raddr_seg)) / 693 sizeof(struct mlx5_wqe_data_seg); 694 props->max_sge = min(max_rq_sg, max_sq_sg); 695 props->max_sge_rd = MLX5_MAX_SGE_RD; 696 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 697 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 698 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 699 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 700 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 701 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 702 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 703 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 704 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 705 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 706 props->max_srq_sge = max_rq_sg - 1; 707 props->max_fast_reg_page_list_len = 708 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 709 get_atomic_caps(dev, props); 710 props->masked_atomic_cap = IB_ATOMIC_NONE; 711 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 712 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 713 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 714 props->max_mcast_grp; 715 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 716 props->max_ah = INT_MAX; 717 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 718 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 719 720 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 721 if (MLX5_CAP_GEN(mdev, pg)) 722 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 723 props->odp_caps = dev->odp_caps; 724 #endif 725 726 if (MLX5_CAP_GEN(mdev, cd)) 727 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 728 729 if (!mlx5_core_is_pf(mdev)) 730 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 731 732 if (mlx5_ib_port_link_layer(ibdev, 1) == 733 IB_LINK_LAYER_ETHERNET) { 734 props->rss_caps.max_rwq_indirection_tables = 735 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 736 props->rss_caps.max_rwq_indirection_table_size = 737 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 738 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 739 props->max_wq_type_rq = 740 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 741 } 742 743 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 744 resp.cqe_comp_caps.max_num = 745 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 746 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 747 resp.cqe_comp_caps.supported_format = 748 MLX5_IB_CQE_RES_FORMAT_HASH | 749 MLX5_IB_CQE_RES_FORMAT_CSUM; 750 resp.response_length += sizeof(resp.cqe_comp_caps); 751 } 752 753 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 754 if (MLX5_CAP_QOS(mdev, packet_pacing) && 755 MLX5_CAP_GEN(mdev, qos)) { 756 resp.packet_pacing_caps.qp_rate_limit_max = 757 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 758 resp.packet_pacing_caps.qp_rate_limit_min = 759 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 760 resp.packet_pacing_caps.supported_qpts |= 761 1 << IB_QPT_RAW_PACKET; 762 } 763 resp.response_length += sizeof(resp.packet_pacing_caps); 764 } 765 766 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 767 uhw->outlen)) { 768 resp.mlx5_ib_support_multi_pkt_send_wqes = 769 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 770 resp.response_length += 771 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 772 } 773 774 if (field_avail(typeof(resp), reserved, uhw->outlen)) 775 resp.response_length += sizeof(resp.reserved); 776 777 if (uhw->outlen) { 778 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 779 780 if (err) 781 return err; 782 } 783 784 return 0; 785 } 786 787 enum mlx5_ib_width { 788 MLX5_IB_WIDTH_1X = 1 << 0, 789 MLX5_IB_WIDTH_2X = 1 << 1, 790 MLX5_IB_WIDTH_4X = 1 << 2, 791 MLX5_IB_WIDTH_8X = 1 << 3, 792 MLX5_IB_WIDTH_12X = 1 << 4 793 }; 794 795 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 796 u8 *ib_width) 797 { 798 struct mlx5_ib_dev *dev = to_mdev(ibdev); 799 int err = 0; 800 801 if (active_width & MLX5_IB_WIDTH_1X) { 802 *ib_width = IB_WIDTH_1X; 803 } else if (active_width & MLX5_IB_WIDTH_2X) { 804 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 805 (int)active_width); 806 err = -EINVAL; 807 } else if (active_width & MLX5_IB_WIDTH_4X) { 808 *ib_width = IB_WIDTH_4X; 809 } else if (active_width & MLX5_IB_WIDTH_8X) { 810 *ib_width = IB_WIDTH_8X; 811 } else if (active_width & MLX5_IB_WIDTH_12X) { 812 *ib_width = IB_WIDTH_12X; 813 } else { 814 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 815 (int)active_width); 816 err = -EINVAL; 817 } 818 819 return err; 820 } 821 822 static int mlx5_mtu_to_ib_mtu(int mtu) 823 { 824 switch (mtu) { 825 case 256: return 1; 826 case 512: return 2; 827 case 1024: return 3; 828 case 2048: return 4; 829 case 4096: return 5; 830 default: 831 pr_warn("invalid mtu\n"); 832 return -1; 833 } 834 } 835 836 enum ib_max_vl_num { 837 __IB_MAX_VL_0 = 1, 838 __IB_MAX_VL_0_1 = 2, 839 __IB_MAX_VL_0_3 = 3, 840 __IB_MAX_VL_0_7 = 4, 841 __IB_MAX_VL_0_14 = 5, 842 }; 843 844 enum mlx5_vl_hw_cap { 845 MLX5_VL_HW_0 = 1, 846 MLX5_VL_HW_0_1 = 2, 847 MLX5_VL_HW_0_2 = 3, 848 MLX5_VL_HW_0_3 = 4, 849 MLX5_VL_HW_0_4 = 5, 850 MLX5_VL_HW_0_5 = 6, 851 MLX5_VL_HW_0_6 = 7, 852 MLX5_VL_HW_0_7 = 8, 853 MLX5_VL_HW_0_14 = 15 854 }; 855 856 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 857 u8 *max_vl_num) 858 { 859 switch (vl_hw_cap) { 860 case MLX5_VL_HW_0: 861 *max_vl_num = __IB_MAX_VL_0; 862 break; 863 case MLX5_VL_HW_0_1: 864 *max_vl_num = __IB_MAX_VL_0_1; 865 break; 866 case MLX5_VL_HW_0_3: 867 *max_vl_num = __IB_MAX_VL_0_3; 868 break; 869 case MLX5_VL_HW_0_7: 870 *max_vl_num = __IB_MAX_VL_0_7; 871 break; 872 case MLX5_VL_HW_0_14: 873 *max_vl_num = __IB_MAX_VL_0_14; 874 break; 875 876 default: 877 return -EINVAL; 878 } 879 880 return 0; 881 } 882 883 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 884 struct ib_port_attr *props) 885 { 886 struct mlx5_ib_dev *dev = to_mdev(ibdev); 887 struct mlx5_core_dev *mdev = dev->mdev; 888 struct mlx5_hca_vport_context *rep; 889 u16 max_mtu; 890 u16 oper_mtu; 891 int err; 892 u8 ib_link_width_oper; 893 u8 vl_hw_cap; 894 895 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 896 if (!rep) { 897 err = -ENOMEM; 898 goto out; 899 } 900 901 /* props being zeroed by the caller, avoid zeroing it here */ 902 903 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 904 if (err) 905 goto out; 906 907 props->lid = rep->lid; 908 props->lmc = rep->lmc; 909 props->sm_lid = rep->sm_lid; 910 props->sm_sl = rep->sm_sl; 911 props->state = rep->vport_state; 912 props->phys_state = rep->port_physical_state; 913 props->port_cap_flags = rep->cap_mask1; 914 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 915 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 916 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 917 props->bad_pkey_cntr = rep->pkey_violation_counter; 918 props->qkey_viol_cntr = rep->qkey_violation_counter; 919 props->subnet_timeout = rep->subnet_timeout; 920 props->init_type_reply = rep->init_type_reply; 921 props->grh_required = rep->grh_required; 922 923 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 924 if (err) 925 goto out; 926 927 err = translate_active_width(ibdev, ib_link_width_oper, 928 &props->active_width); 929 if (err) 930 goto out; 931 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 932 if (err) 933 goto out; 934 935 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 936 937 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 938 939 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 940 941 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 942 943 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 944 if (err) 945 goto out; 946 947 err = translate_max_vl_num(ibdev, vl_hw_cap, 948 &props->max_vl_num); 949 out: 950 kfree(rep); 951 return err; 952 } 953 954 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 955 struct ib_port_attr *props) 956 { 957 unsigned int count; 958 int ret; 959 960 switch (mlx5_get_vport_access_method(ibdev)) { 961 case MLX5_VPORT_ACCESS_METHOD_MAD: 962 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 963 break; 964 965 case MLX5_VPORT_ACCESS_METHOD_HCA: 966 ret = mlx5_query_hca_port(ibdev, port, props); 967 break; 968 969 case MLX5_VPORT_ACCESS_METHOD_NIC: 970 ret = mlx5_query_port_roce(ibdev, port, props); 971 break; 972 973 default: 974 ret = -EINVAL; 975 } 976 977 if (!ret && props) { 978 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 979 props->gid_tbl_len -= count; 980 } 981 return ret; 982 } 983 984 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 985 union ib_gid *gid) 986 { 987 struct mlx5_ib_dev *dev = to_mdev(ibdev); 988 struct mlx5_core_dev *mdev = dev->mdev; 989 990 switch (mlx5_get_vport_access_method(ibdev)) { 991 case MLX5_VPORT_ACCESS_METHOD_MAD: 992 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 993 994 case MLX5_VPORT_ACCESS_METHOD_HCA: 995 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 996 997 default: 998 return -EINVAL; 999 } 1000 1001 } 1002 1003 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1004 u16 *pkey) 1005 { 1006 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1007 struct mlx5_core_dev *mdev = dev->mdev; 1008 1009 switch (mlx5_get_vport_access_method(ibdev)) { 1010 case MLX5_VPORT_ACCESS_METHOD_MAD: 1011 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1012 1013 case MLX5_VPORT_ACCESS_METHOD_HCA: 1014 case MLX5_VPORT_ACCESS_METHOD_NIC: 1015 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1016 pkey); 1017 default: 1018 return -EINVAL; 1019 } 1020 } 1021 1022 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1023 struct ib_device_modify *props) 1024 { 1025 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1026 struct mlx5_reg_node_desc in; 1027 struct mlx5_reg_node_desc out; 1028 int err; 1029 1030 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1031 return -EOPNOTSUPP; 1032 1033 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1034 return 0; 1035 1036 /* 1037 * If possible, pass node desc to FW, so it can generate 1038 * a 144 trap. If cmd fails, just ignore. 1039 */ 1040 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1041 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1042 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1043 if (err) 1044 return err; 1045 1046 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1047 1048 return err; 1049 } 1050 1051 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1052 u32 value) 1053 { 1054 struct mlx5_hca_vport_context ctx = {}; 1055 int err; 1056 1057 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1058 port_num, 0, &ctx); 1059 if (err) 1060 return err; 1061 1062 if (~ctx.cap_mask1_perm & mask) { 1063 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1064 mask, ctx.cap_mask1_perm); 1065 return -EINVAL; 1066 } 1067 1068 ctx.cap_mask1 = value; 1069 ctx.cap_mask1_perm = mask; 1070 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1071 port_num, 0, &ctx); 1072 1073 return err; 1074 } 1075 1076 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1077 struct ib_port_modify *props) 1078 { 1079 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1080 struct ib_port_attr attr; 1081 u32 tmp; 1082 int err; 1083 u32 change_mask; 1084 u32 value; 1085 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1086 IB_LINK_LAYER_INFINIBAND); 1087 1088 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1089 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1090 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1091 return set_port_caps_atomic(dev, port, change_mask, value); 1092 } 1093 1094 mutex_lock(&dev->cap_mask_mutex); 1095 1096 err = ib_query_port(ibdev, port, &attr); 1097 if (err) 1098 goto out; 1099 1100 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1101 ~props->clr_port_cap_mask; 1102 1103 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1104 1105 out: 1106 mutex_unlock(&dev->cap_mask_mutex); 1107 return err; 1108 } 1109 1110 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1111 { 1112 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1113 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1114 } 1115 1116 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1117 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1118 u32 *num_sys_pages) 1119 { 1120 int uars_per_sys_page; 1121 int bfregs_per_sys_page; 1122 int ref_bfregs = req->total_num_bfregs; 1123 1124 if (req->total_num_bfregs == 0) 1125 return -EINVAL; 1126 1127 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1128 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1129 1130 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1131 return -ENOMEM; 1132 1133 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1134 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1135 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1136 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1137 1138 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1139 return -EINVAL; 1140 1141 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n", 1142 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1143 lib_uar_4k ? "yes" : "no", ref_bfregs, 1144 req->total_num_bfregs, *num_sys_pages); 1145 1146 return 0; 1147 } 1148 1149 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1150 { 1151 struct mlx5_bfreg_info *bfregi; 1152 int err; 1153 int i; 1154 1155 bfregi = &context->bfregi; 1156 for (i = 0; i < bfregi->num_sys_pages; i++) { 1157 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1158 if (err) 1159 goto error; 1160 1161 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1162 } 1163 return 0; 1164 1165 error: 1166 for (--i; i >= 0; i--) 1167 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1168 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1169 1170 return err; 1171 } 1172 1173 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1174 { 1175 struct mlx5_bfreg_info *bfregi; 1176 int err; 1177 int i; 1178 1179 bfregi = &context->bfregi; 1180 for (i = 0; i < bfregi->num_sys_pages; i++) { 1181 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1182 if (err) { 1183 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1184 return err; 1185 } 1186 } 1187 return 0; 1188 } 1189 1190 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1191 struct ib_udata *udata) 1192 { 1193 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1194 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1195 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1196 struct mlx5_ib_ucontext *context; 1197 struct mlx5_bfreg_info *bfregi; 1198 int ver; 1199 int err; 1200 size_t reqlen; 1201 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1202 max_cqe_version); 1203 bool lib_uar_4k; 1204 1205 if (!dev->ib_active) 1206 return ERR_PTR(-EAGAIN); 1207 1208 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1209 return ERR_PTR(-EINVAL); 1210 1211 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1212 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1213 ver = 0; 1214 else if (reqlen >= min_req_v2) 1215 ver = 2; 1216 else 1217 return ERR_PTR(-EINVAL); 1218 1219 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1220 if (err) 1221 return ERR_PTR(err); 1222 1223 if (req.flags) 1224 return ERR_PTR(-EINVAL); 1225 1226 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1227 return ERR_PTR(-EOPNOTSUPP); 1228 1229 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1230 MLX5_NON_FP_BFREGS_PER_UAR); 1231 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1232 return ERR_PTR(-EINVAL); 1233 1234 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1235 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1236 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1237 resp.cache_line_size = cache_line_size(); 1238 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1239 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1240 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1241 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1242 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1243 resp.cqe_version = min_t(__u8, 1244 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1245 req.max_cqe_version); 1246 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1247 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1248 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1249 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1250 resp.response_length = min(offsetof(typeof(resp), response_length) + 1251 sizeof(resp.response_length), udata->outlen); 1252 1253 context = kzalloc(sizeof(*context), GFP_KERNEL); 1254 if (!context) 1255 return ERR_PTR(-ENOMEM); 1256 1257 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1258 bfregi = &context->bfregi; 1259 1260 /* updates req->total_num_bfregs */ 1261 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1262 if (err) 1263 goto out_ctx; 1264 1265 mutex_init(&bfregi->lock); 1266 bfregi->lib_uar_4k = lib_uar_4k; 1267 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1268 GFP_KERNEL); 1269 if (!bfregi->count) { 1270 err = -ENOMEM; 1271 goto out_ctx; 1272 } 1273 1274 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1275 sizeof(*bfregi->sys_pages), 1276 GFP_KERNEL); 1277 if (!bfregi->sys_pages) { 1278 err = -ENOMEM; 1279 goto out_count; 1280 } 1281 1282 err = allocate_uars(dev, context); 1283 if (err) 1284 goto out_sys_pages; 1285 1286 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1287 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1288 #endif 1289 1290 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1291 if (!context->upd_xlt_page) { 1292 err = -ENOMEM; 1293 goto out_uars; 1294 } 1295 mutex_init(&context->upd_xlt_page_mutex); 1296 1297 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1298 err = mlx5_core_alloc_transport_domain(dev->mdev, 1299 &context->tdn); 1300 if (err) 1301 goto out_page; 1302 } 1303 1304 INIT_LIST_HEAD(&context->vma_private_list); 1305 INIT_LIST_HEAD(&context->db_page_list); 1306 mutex_init(&context->db_page_mutex); 1307 1308 resp.tot_bfregs = req.total_num_bfregs; 1309 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1310 1311 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1312 resp.response_length += sizeof(resp.cqe_version); 1313 1314 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1315 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1316 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1317 resp.response_length += sizeof(resp.cmds_supp_uhw); 1318 } 1319 1320 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1321 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1322 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1323 resp.eth_min_inline++; 1324 } 1325 resp.response_length += sizeof(resp.eth_min_inline); 1326 } 1327 1328 /* 1329 * We don't want to expose information from the PCI bar that is located 1330 * after 4096 bytes, so if the arch only supports larger pages, let's 1331 * pretend we don't support reading the HCA's core clock. This is also 1332 * forced by mmap function. 1333 */ 1334 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1335 if (PAGE_SIZE <= 4096) { 1336 resp.comp_mask |= 1337 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1338 resp.hca_core_clock_offset = 1339 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1340 } 1341 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1342 sizeof(resp.reserved2); 1343 } 1344 1345 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1346 resp.response_length += sizeof(resp.log_uar_size); 1347 1348 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1349 resp.response_length += sizeof(resp.num_uars_per_page); 1350 1351 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1352 if (err) 1353 goto out_td; 1354 1355 bfregi->ver = ver; 1356 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1357 context->cqe_version = resp.cqe_version; 1358 context->lib_caps = req.lib_caps; 1359 print_lib_caps(dev, context->lib_caps); 1360 1361 return &context->ibucontext; 1362 1363 out_td: 1364 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1365 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1366 1367 out_page: 1368 free_page(context->upd_xlt_page); 1369 1370 out_uars: 1371 deallocate_uars(dev, context); 1372 1373 out_sys_pages: 1374 kfree(bfregi->sys_pages); 1375 1376 out_count: 1377 kfree(bfregi->count); 1378 1379 out_ctx: 1380 kfree(context); 1381 1382 return ERR_PTR(err); 1383 } 1384 1385 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1386 { 1387 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1388 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1389 struct mlx5_bfreg_info *bfregi; 1390 1391 bfregi = &context->bfregi; 1392 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1393 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1394 1395 free_page(context->upd_xlt_page); 1396 deallocate_uars(dev, context); 1397 kfree(bfregi->sys_pages); 1398 kfree(bfregi->count); 1399 kfree(context); 1400 1401 return 0; 1402 } 1403 1404 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1405 struct mlx5_bfreg_info *bfregi, 1406 int idx) 1407 { 1408 int fw_uars_per_page; 1409 1410 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1411 1412 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1413 bfregi->sys_pages[idx] / fw_uars_per_page; 1414 } 1415 1416 static int get_command(unsigned long offset) 1417 { 1418 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1419 } 1420 1421 static int get_arg(unsigned long offset) 1422 { 1423 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1424 } 1425 1426 static int get_index(unsigned long offset) 1427 { 1428 return get_arg(offset); 1429 } 1430 1431 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1432 { 1433 /* vma_open is called when a new VMA is created on top of our VMA. This 1434 * is done through either mremap flow or split_vma (usually due to 1435 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1436 * as this VMA is strongly hardware related. Therefore we set the 1437 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1438 * calling us again and trying to do incorrect actions. We assume that 1439 * the original VMA size is exactly a single page, and therefore all 1440 * "splitting" operation will not happen to it. 1441 */ 1442 area->vm_ops = NULL; 1443 } 1444 1445 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1446 { 1447 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1448 1449 /* It's guaranteed that all VMAs opened on a FD are closed before the 1450 * file itself is closed, therefore no sync is needed with the regular 1451 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1452 * However need a sync with accessing the vma as part of 1453 * mlx5_ib_disassociate_ucontext. 1454 * The close operation is usually called under mm->mmap_sem except when 1455 * process is exiting. 1456 * The exiting case is handled explicitly as part of 1457 * mlx5_ib_disassociate_ucontext. 1458 */ 1459 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1460 1461 /* setting the vma context pointer to null in the mlx5_ib driver's 1462 * private data, to protect a race condition in 1463 * mlx5_ib_disassociate_ucontext(). 1464 */ 1465 mlx5_ib_vma_priv_data->vma = NULL; 1466 list_del(&mlx5_ib_vma_priv_data->list); 1467 kfree(mlx5_ib_vma_priv_data); 1468 } 1469 1470 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1471 .open = mlx5_ib_vma_open, 1472 .close = mlx5_ib_vma_close 1473 }; 1474 1475 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1476 struct mlx5_ib_ucontext *ctx) 1477 { 1478 struct mlx5_ib_vma_private_data *vma_prv; 1479 struct list_head *vma_head = &ctx->vma_private_list; 1480 1481 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1482 if (!vma_prv) 1483 return -ENOMEM; 1484 1485 vma_prv->vma = vma; 1486 vma->vm_private_data = vma_prv; 1487 vma->vm_ops = &mlx5_ib_vm_ops; 1488 1489 list_add(&vma_prv->list, vma_head); 1490 1491 return 0; 1492 } 1493 1494 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1495 { 1496 int ret; 1497 struct vm_area_struct *vma; 1498 struct mlx5_ib_vma_private_data *vma_private, *n; 1499 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1500 struct task_struct *owning_process = NULL; 1501 struct mm_struct *owning_mm = NULL; 1502 1503 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1504 if (!owning_process) 1505 return; 1506 1507 owning_mm = get_task_mm(owning_process); 1508 if (!owning_mm) { 1509 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1510 while (1) { 1511 put_task_struct(owning_process); 1512 usleep_range(1000, 2000); 1513 owning_process = get_pid_task(ibcontext->tgid, 1514 PIDTYPE_PID); 1515 if (!owning_process || 1516 owning_process->state == TASK_DEAD) { 1517 pr_info("disassociate ucontext done, task was terminated\n"); 1518 /* in case task was dead need to release the 1519 * task struct. 1520 */ 1521 if (owning_process) 1522 put_task_struct(owning_process); 1523 return; 1524 } 1525 } 1526 } 1527 1528 /* need to protect from a race on closing the vma as part of 1529 * mlx5_ib_vma_close. 1530 */ 1531 down_write(&owning_mm->mmap_sem); 1532 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1533 list) { 1534 vma = vma_private->vma; 1535 ret = zap_vma_ptes(vma, vma->vm_start, 1536 PAGE_SIZE); 1537 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1538 /* context going to be destroyed, should 1539 * not access ops any more. 1540 */ 1541 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1542 vma->vm_ops = NULL; 1543 list_del(&vma_private->list); 1544 kfree(vma_private); 1545 } 1546 up_write(&owning_mm->mmap_sem); 1547 mmput(owning_mm); 1548 put_task_struct(owning_process); 1549 } 1550 1551 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1552 { 1553 switch (cmd) { 1554 case MLX5_IB_MMAP_WC_PAGE: 1555 return "WC"; 1556 case MLX5_IB_MMAP_REGULAR_PAGE: 1557 return "best effort WC"; 1558 case MLX5_IB_MMAP_NC_PAGE: 1559 return "NC"; 1560 default: 1561 return NULL; 1562 } 1563 } 1564 1565 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1566 struct vm_area_struct *vma, 1567 struct mlx5_ib_ucontext *context) 1568 { 1569 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1570 int err; 1571 unsigned long idx; 1572 phys_addr_t pfn, pa; 1573 pgprot_t prot; 1574 int uars_per_page; 1575 1576 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1577 return -EINVAL; 1578 1579 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1580 idx = get_index(vma->vm_pgoff); 1581 if (idx % uars_per_page || 1582 idx * uars_per_page >= bfregi->num_sys_pages) { 1583 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1584 return -EINVAL; 1585 } 1586 1587 switch (cmd) { 1588 case MLX5_IB_MMAP_WC_PAGE: 1589 /* Some architectures don't support WC memory */ 1590 #if defined(CONFIG_X86) 1591 if (!pat_enabled()) 1592 return -EPERM; 1593 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1594 return -EPERM; 1595 #endif 1596 /* fall through */ 1597 case MLX5_IB_MMAP_REGULAR_PAGE: 1598 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1599 prot = pgprot_writecombine(vma->vm_page_prot); 1600 break; 1601 case MLX5_IB_MMAP_NC_PAGE: 1602 prot = pgprot_noncached(vma->vm_page_prot); 1603 break; 1604 default: 1605 return -EINVAL; 1606 } 1607 1608 pfn = uar_index2pfn(dev, bfregi, idx); 1609 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1610 1611 vma->vm_page_prot = prot; 1612 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1613 PAGE_SIZE, vma->vm_page_prot); 1614 if (err) { 1615 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1616 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1617 return -EAGAIN; 1618 } 1619 1620 pa = pfn << PAGE_SHIFT; 1621 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1622 vma->vm_start, &pa); 1623 1624 return mlx5_ib_set_vma_data(vma, context); 1625 } 1626 1627 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1628 { 1629 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1630 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1631 unsigned long command; 1632 phys_addr_t pfn; 1633 1634 command = get_command(vma->vm_pgoff); 1635 switch (command) { 1636 case MLX5_IB_MMAP_WC_PAGE: 1637 case MLX5_IB_MMAP_NC_PAGE: 1638 case MLX5_IB_MMAP_REGULAR_PAGE: 1639 return uar_mmap(dev, command, vma, context); 1640 1641 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1642 return -ENOSYS; 1643 1644 case MLX5_IB_MMAP_CORE_CLOCK: 1645 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1646 return -EINVAL; 1647 1648 if (vma->vm_flags & VM_WRITE) 1649 return -EPERM; 1650 1651 /* Don't expose to user-space information it shouldn't have */ 1652 if (PAGE_SIZE > 4096) 1653 return -EOPNOTSUPP; 1654 1655 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1656 pfn = (dev->mdev->iseg_base + 1657 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1658 PAGE_SHIFT; 1659 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1660 PAGE_SIZE, vma->vm_page_prot)) 1661 return -EAGAIN; 1662 1663 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1664 vma->vm_start, 1665 (unsigned long long)pfn << PAGE_SHIFT); 1666 break; 1667 1668 default: 1669 return -EINVAL; 1670 } 1671 1672 return 0; 1673 } 1674 1675 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1676 struct ib_ucontext *context, 1677 struct ib_udata *udata) 1678 { 1679 struct mlx5_ib_alloc_pd_resp resp; 1680 struct mlx5_ib_pd *pd; 1681 int err; 1682 1683 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1684 if (!pd) 1685 return ERR_PTR(-ENOMEM); 1686 1687 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1688 if (err) { 1689 kfree(pd); 1690 return ERR_PTR(err); 1691 } 1692 1693 if (context) { 1694 resp.pdn = pd->pdn; 1695 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1696 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1697 kfree(pd); 1698 return ERR_PTR(-EFAULT); 1699 } 1700 } 1701 1702 return &pd->ibpd; 1703 } 1704 1705 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1706 { 1707 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1708 struct mlx5_ib_pd *mpd = to_mpd(pd); 1709 1710 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1711 kfree(mpd); 1712 1713 return 0; 1714 } 1715 1716 enum { 1717 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1718 MATCH_CRITERIA_ENABLE_MISC_BIT, 1719 MATCH_CRITERIA_ENABLE_INNER_BIT 1720 }; 1721 1722 #define HEADER_IS_ZERO(match_criteria, headers) \ 1723 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1724 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1725 1726 static u8 get_match_criteria_enable(u32 *match_criteria) 1727 { 1728 u8 match_criteria_enable; 1729 1730 match_criteria_enable = 1731 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1732 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1733 match_criteria_enable |= 1734 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1735 MATCH_CRITERIA_ENABLE_MISC_BIT; 1736 match_criteria_enable |= 1737 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1738 MATCH_CRITERIA_ENABLE_INNER_BIT; 1739 1740 return match_criteria_enable; 1741 } 1742 1743 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1744 { 1745 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1746 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1747 } 1748 1749 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1750 bool inner) 1751 { 1752 if (inner) { 1753 MLX5_SET(fte_match_set_misc, 1754 misc_c, inner_ipv6_flow_label, mask); 1755 MLX5_SET(fte_match_set_misc, 1756 misc_v, inner_ipv6_flow_label, val); 1757 } else { 1758 MLX5_SET(fte_match_set_misc, 1759 misc_c, outer_ipv6_flow_label, mask); 1760 MLX5_SET(fte_match_set_misc, 1761 misc_v, outer_ipv6_flow_label, val); 1762 } 1763 } 1764 1765 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1766 { 1767 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1768 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1769 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1770 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1771 } 1772 1773 #define LAST_ETH_FIELD vlan_tag 1774 #define LAST_IB_FIELD sl 1775 #define LAST_IPV4_FIELD tos 1776 #define LAST_IPV6_FIELD traffic_class 1777 #define LAST_TCP_UDP_FIELD src_port 1778 #define LAST_TUNNEL_FIELD tunnel_id 1779 #define LAST_FLOW_TAG_FIELD tag_id 1780 #define LAST_DROP_FIELD size 1781 1782 /* Field is the last supported field */ 1783 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1784 memchr_inv((void *)&filter.field +\ 1785 sizeof(filter.field), 0,\ 1786 sizeof(filter) -\ 1787 offsetof(typeof(filter), field) -\ 1788 sizeof(filter.field)) 1789 1790 #define IPV4_VERSION 4 1791 #define IPV6_VERSION 6 1792 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1793 u32 *match_v, const union ib_flow_spec *ib_spec, 1794 u32 *tag_id, bool *is_drop) 1795 { 1796 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1797 misc_parameters); 1798 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1799 misc_parameters); 1800 void *headers_c; 1801 void *headers_v; 1802 int match_ipv; 1803 1804 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1805 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1806 inner_headers); 1807 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1808 inner_headers); 1809 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1810 ft_field_support.inner_ip_version); 1811 } else { 1812 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1813 outer_headers); 1814 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1815 outer_headers); 1816 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1817 ft_field_support.outer_ip_version); 1818 } 1819 1820 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1821 case IB_FLOW_SPEC_ETH: 1822 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1823 return -EOPNOTSUPP; 1824 1825 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1826 dmac_47_16), 1827 ib_spec->eth.mask.dst_mac); 1828 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1829 dmac_47_16), 1830 ib_spec->eth.val.dst_mac); 1831 1832 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1833 smac_47_16), 1834 ib_spec->eth.mask.src_mac); 1835 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1836 smac_47_16), 1837 ib_spec->eth.val.src_mac); 1838 1839 if (ib_spec->eth.mask.vlan_tag) { 1840 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1841 cvlan_tag, 1); 1842 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1843 cvlan_tag, 1); 1844 1845 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1846 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1847 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1848 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1849 1850 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1851 first_cfi, 1852 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1853 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1854 first_cfi, 1855 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1856 1857 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1858 first_prio, 1859 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1860 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1861 first_prio, 1862 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1863 } 1864 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1865 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1867 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1868 break; 1869 case IB_FLOW_SPEC_IPV4: 1870 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1871 return -EOPNOTSUPP; 1872 1873 if (match_ipv) { 1874 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1875 ip_version, 0xf); 1876 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1877 ip_version, IPV4_VERSION); 1878 } else { 1879 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1880 ethertype, 0xffff); 1881 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1882 ethertype, ETH_P_IP); 1883 } 1884 1885 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1886 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1887 &ib_spec->ipv4.mask.src_ip, 1888 sizeof(ib_spec->ipv4.mask.src_ip)); 1889 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1890 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1891 &ib_spec->ipv4.val.src_ip, 1892 sizeof(ib_spec->ipv4.val.src_ip)); 1893 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1894 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1895 &ib_spec->ipv4.mask.dst_ip, 1896 sizeof(ib_spec->ipv4.mask.dst_ip)); 1897 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1898 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1899 &ib_spec->ipv4.val.dst_ip, 1900 sizeof(ib_spec->ipv4.val.dst_ip)); 1901 1902 set_tos(headers_c, headers_v, 1903 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1904 1905 set_proto(headers_c, headers_v, 1906 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1907 break; 1908 case IB_FLOW_SPEC_IPV6: 1909 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1910 return -EOPNOTSUPP; 1911 1912 if (match_ipv) { 1913 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1914 ip_version, 0xf); 1915 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1916 ip_version, IPV6_VERSION); 1917 } else { 1918 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1919 ethertype, 0xffff); 1920 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1921 ethertype, ETH_P_IPV6); 1922 } 1923 1924 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1925 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1926 &ib_spec->ipv6.mask.src_ip, 1927 sizeof(ib_spec->ipv6.mask.src_ip)); 1928 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1929 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1930 &ib_spec->ipv6.val.src_ip, 1931 sizeof(ib_spec->ipv6.val.src_ip)); 1932 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1933 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1934 &ib_spec->ipv6.mask.dst_ip, 1935 sizeof(ib_spec->ipv6.mask.dst_ip)); 1936 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1937 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1938 &ib_spec->ipv6.val.dst_ip, 1939 sizeof(ib_spec->ipv6.val.dst_ip)); 1940 1941 set_tos(headers_c, headers_v, 1942 ib_spec->ipv6.mask.traffic_class, 1943 ib_spec->ipv6.val.traffic_class); 1944 1945 set_proto(headers_c, headers_v, 1946 ib_spec->ipv6.mask.next_hdr, 1947 ib_spec->ipv6.val.next_hdr); 1948 1949 set_flow_label(misc_params_c, misc_params_v, 1950 ntohl(ib_spec->ipv6.mask.flow_label), 1951 ntohl(ib_spec->ipv6.val.flow_label), 1952 ib_spec->type & IB_FLOW_SPEC_INNER); 1953 1954 break; 1955 case IB_FLOW_SPEC_TCP: 1956 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1957 LAST_TCP_UDP_FIELD)) 1958 return -EOPNOTSUPP; 1959 1960 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1961 0xff); 1962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1963 IPPROTO_TCP); 1964 1965 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 1966 ntohs(ib_spec->tcp_udp.mask.src_port)); 1967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 1968 ntohs(ib_spec->tcp_udp.val.src_port)); 1969 1970 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 1971 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1972 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 1973 ntohs(ib_spec->tcp_udp.val.dst_port)); 1974 break; 1975 case IB_FLOW_SPEC_UDP: 1976 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1977 LAST_TCP_UDP_FIELD)) 1978 return -EOPNOTSUPP; 1979 1980 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1981 0xff); 1982 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1983 IPPROTO_UDP); 1984 1985 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 1986 ntohs(ib_spec->tcp_udp.mask.src_port)); 1987 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 1988 ntohs(ib_spec->tcp_udp.val.src_port)); 1989 1990 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 1991 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1992 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 1993 ntohs(ib_spec->tcp_udp.val.dst_port)); 1994 break; 1995 case IB_FLOW_SPEC_VXLAN_TUNNEL: 1996 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 1997 LAST_TUNNEL_FIELD)) 1998 return -EOPNOTSUPP; 1999 2000 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2001 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2002 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2003 ntohl(ib_spec->tunnel.val.tunnel_id)); 2004 break; 2005 case IB_FLOW_SPEC_ACTION_TAG: 2006 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2007 LAST_FLOW_TAG_FIELD)) 2008 return -EOPNOTSUPP; 2009 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2010 return -EINVAL; 2011 2012 *tag_id = ib_spec->flow_tag.tag_id; 2013 break; 2014 case IB_FLOW_SPEC_ACTION_DROP: 2015 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2016 LAST_DROP_FIELD)) 2017 return -EOPNOTSUPP; 2018 *is_drop = true; 2019 break; 2020 default: 2021 return -EINVAL; 2022 } 2023 2024 return 0; 2025 } 2026 2027 /* If a flow could catch both multicast and unicast packets, 2028 * it won't fall into the multicast flow steering table and this rule 2029 * could steal other multicast packets. 2030 */ 2031 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 2032 { 2033 struct ib_flow_spec_eth *eth_spec; 2034 2035 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2036 ib_attr->size < sizeof(struct ib_flow_attr) + 2037 sizeof(struct ib_flow_spec_eth) || 2038 ib_attr->num_of_specs < 1) 2039 return false; 2040 2041 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 2042 if (eth_spec->type != IB_FLOW_SPEC_ETH || 2043 eth_spec->size != sizeof(*eth_spec)) 2044 return false; 2045 2046 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2047 is_multicast_ether_addr(eth_spec->val.dst_mac); 2048 } 2049 2050 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2051 const struct ib_flow_attr *flow_attr, 2052 bool check_inner) 2053 { 2054 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2055 int match_ipv = check_inner ? 2056 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2057 ft_field_support.inner_ip_version) : 2058 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2059 ft_field_support.outer_ip_version); 2060 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2061 bool ipv4_spec_valid, ipv6_spec_valid; 2062 unsigned int ip_spec_type = 0; 2063 bool has_ethertype = false; 2064 unsigned int spec_index; 2065 bool mask_valid = true; 2066 u16 eth_type = 0; 2067 bool type_valid; 2068 2069 /* Validate that ethertype is correct */ 2070 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2071 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2072 ib_spec->eth.mask.ether_type) { 2073 mask_valid = (ib_spec->eth.mask.ether_type == 2074 htons(0xffff)); 2075 has_ethertype = true; 2076 eth_type = ntohs(ib_spec->eth.val.ether_type); 2077 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2078 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2079 ip_spec_type = ib_spec->type; 2080 } 2081 ib_spec = (void *)ib_spec + ib_spec->size; 2082 } 2083 2084 type_valid = (!has_ethertype) || (!ip_spec_type); 2085 if (!type_valid && mask_valid) { 2086 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2087 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2088 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2089 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2090 2091 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2092 (((eth_type == ETH_P_MPLS_UC) || 2093 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2094 } 2095 2096 return type_valid; 2097 } 2098 2099 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2100 const struct ib_flow_attr *flow_attr) 2101 { 2102 return is_valid_ethertype(mdev, flow_attr, false) && 2103 is_valid_ethertype(mdev, flow_attr, true); 2104 } 2105 2106 static void put_flow_table(struct mlx5_ib_dev *dev, 2107 struct mlx5_ib_flow_prio *prio, bool ft_added) 2108 { 2109 prio->refcount -= !!ft_added; 2110 if (!prio->refcount) { 2111 mlx5_destroy_flow_table(prio->flow_table); 2112 prio->flow_table = NULL; 2113 } 2114 } 2115 2116 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2117 { 2118 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2119 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2120 struct mlx5_ib_flow_handler, 2121 ibflow); 2122 struct mlx5_ib_flow_handler *iter, *tmp; 2123 2124 mutex_lock(&dev->flow_db.lock); 2125 2126 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2127 mlx5_del_flow_rules(iter->rule); 2128 put_flow_table(dev, iter->prio, true); 2129 list_del(&iter->list); 2130 kfree(iter); 2131 } 2132 2133 mlx5_del_flow_rules(handler->rule); 2134 put_flow_table(dev, handler->prio, true); 2135 mutex_unlock(&dev->flow_db.lock); 2136 2137 kfree(handler); 2138 2139 return 0; 2140 } 2141 2142 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2143 { 2144 priority *= 2; 2145 if (!dont_trap) 2146 priority++; 2147 return priority; 2148 } 2149 2150 enum flow_table_type { 2151 MLX5_IB_FT_RX, 2152 MLX5_IB_FT_TX 2153 }; 2154 2155 #define MLX5_FS_MAX_TYPES 6 2156 #define MLX5_FS_MAX_ENTRIES BIT(16) 2157 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2158 struct ib_flow_attr *flow_attr, 2159 enum flow_table_type ft_type) 2160 { 2161 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2162 struct mlx5_flow_namespace *ns = NULL; 2163 struct mlx5_ib_flow_prio *prio; 2164 struct mlx5_flow_table *ft; 2165 int max_table_size; 2166 int num_entries; 2167 int num_groups; 2168 int priority; 2169 int err = 0; 2170 2171 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2172 log_max_ft_size)); 2173 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2174 if (flow_is_multicast_only(flow_attr) && 2175 !dont_trap) 2176 priority = MLX5_IB_FLOW_MCAST_PRIO; 2177 else 2178 priority = ib_prio_to_core_prio(flow_attr->priority, 2179 dont_trap); 2180 ns = mlx5_get_flow_namespace(dev->mdev, 2181 MLX5_FLOW_NAMESPACE_BYPASS); 2182 num_entries = MLX5_FS_MAX_ENTRIES; 2183 num_groups = MLX5_FS_MAX_TYPES; 2184 prio = &dev->flow_db.prios[priority]; 2185 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2186 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2187 ns = mlx5_get_flow_namespace(dev->mdev, 2188 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2189 build_leftovers_ft_param(&priority, 2190 &num_entries, 2191 &num_groups); 2192 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2193 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2194 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2195 allow_sniffer_and_nic_rx_shared_tir)) 2196 return ERR_PTR(-ENOTSUPP); 2197 2198 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2199 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2200 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2201 2202 prio = &dev->flow_db.sniffer[ft_type]; 2203 priority = 0; 2204 num_entries = 1; 2205 num_groups = 1; 2206 } 2207 2208 if (!ns) 2209 return ERR_PTR(-ENOTSUPP); 2210 2211 if (num_entries > max_table_size) 2212 return ERR_PTR(-ENOMEM); 2213 2214 ft = prio->flow_table; 2215 if (!ft) { 2216 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2217 num_entries, 2218 num_groups, 2219 0, 0); 2220 2221 if (!IS_ERR(ft)) { 2222 prio->refcount = 0; 2223 prio->flow_table = ft; 2224 } else { 2225 err = PTR_ERR(ft); 2226 } 2227 } 2228 2229 return err ? ERR_PTR(err) : prio; 2230 } 2231 2232 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2233 struct mlx5_ib_flow_prio *ft_prio, 2234 const struct ib_flow_attr *flow_attr, 2235 struct mlx5_flow_destination *dst) 2236 { 2237 struct mlx5_flow_table *ft = ft_prio->flow_table; 2238 struct mlx5_ib_flow_handler *handler; 2239 struct mlx5_flow_act flow_act = {0}; 2240 struct mlx5_flow_spec *spec; 2241 struct mlx5_flow_destination *rule_dst = dst; 2242 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2243 unsigned int spec_index; 2244 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2245 bool is_drop = false; 2246 int err = 0; 2247 int dest_num = 1; 2248 2249 if (!is_valid_attr(dev->mdev, flow_attr)) 2250 return ERR_PTR(-EINVAL); 2251 2252 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2253 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2254 if (!handler || !spec) { 2255 err = -ENOMEM; 2256 goto free; 2257 } 2258 2259 INIT_LIST_HEAD(&handler->list); 2260 2261 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2262 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2263 spec->match_value, 2264 ib_flow, &flow_tag, &is_drop); 2265 if (err < 0) 2266 goto free; 2267 2268 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2269 } 2270 2271 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2272 if (is_drop) { 2273 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2274 rule_dst = NULL; 2275 dest_num = 0; 2276 } else { 2277 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2278 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2279 } 2280 2281 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2282 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2283 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2284 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2285 flow_tag, flow_attr->type); 2286 err = -EINVAL; 2287 goto free; 2288 } 2289 flow_act.flow_tag = flow_tag; 2290 handler->rule = mlx5_add_flow_rules(ft, spec, 2291 &flow_act, 2292 rule_dst, dest_num); 2293 2294 if (IS_ERR(handler->rule)) { 2295 err = PTR_ERR(handler->rule); 2296 goto free; 2297 } 2298 2299 ft_prio->refcount++; 2300 handler->prio = ft_prio; 2301 2302 ft_prio->flow_table = ft; 2303 free: 2304 if (err) 2305 kfree(handler); 2306 kvfree(spec); 2307 return err ? ERR_PTR(err) : handler; 2308 } 2309 2310 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2311 struct mlx5_ib_flow_prio *ft_prio, 2312 struct ib_flow_attr *flow_attr, 2313 struct mlx5_flow_destination *dst) 2314 { 2315 struct mlx5_ib_flow_handler *handler_dst = NULL; 2316 struct mlx5_ib_flow_handler *handler = NULL; 2317 2318 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2319 if (!IS_ERR(handler)) { 2320 handler_dst = create_flow_rule(dev, ft_prio, 2321 flow_attr, dst); 2322 if (IS_ERR(handler_dst)) { 2323 mlx5_del_flow_rules(handler->rule); 2324 ft_prio->refcount--; 2325 kfree(handler); 2326 handler = handler_dst; 2327 } else { 2328 list_add(&handler_dst->list, &handler->list); 2329 } 2330 } 2331 2332 return handler; 2333 } 2334 enum { 2335 LEFTOVERS_MC, 2336 LEFTOVERS_UC, 2337 }; 2338 2339 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2340 struct mlx5_ib_flow_prio *ft_prio, 2341 struct ib_flow_attr *flow_attr, 2342 struct mlx5_flow_destination *dst) 2343 { 2344 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2345 struct mlx5_ib_flow_handler *handler = NULL; 2346 2347 static struct { 2348 struct ib_flow_attr flow_attr; 2349 struct ib_flow_spec_eth eth_flow; 2350 } leftovers_specs[] = { 2351 [LEFTOVERS_MC] = { 2352 .flow_attr = { 2353 .num_of_specs = 1, 2354 .size = sizeof(leftovers_specs[0]) 2355 }, 2356 .eth_flow = { 2357 .type = IB_FLOW_SPEC_ETH, 2358 .size = sizeof(struct ib_flow_spec_eth), 2359 .mask = {.dst_mac = {0x1} }, 2360 .val = {.dst_mac = {0x1} } 2361 } 2362 }, 2363 [LEFTOVERS_UC] = { 2364 .flow_attr = { 2365 .num_of_specs = 1, 2366 .size = sizeof(leftovers_specs[0]) 2367 }, 2368 .eth_flow = { 2369 .type = IB_FLOW_SPEC_ETH, 2370 .size = sizeof(struct ib_flow_spec_eth), 2371 .mask = {.dst_mac = {0x1} }, 2372 .val = {.dst_mac = {} } 2373 } 2374 } 2375 }; 2376 2377 handler = create_flow_rule(dev, ft_prio, 2378 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2379 dst); 2380 if (!IS_ERR(handler) && 2381 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2382 handler_ucast = create_flow_rule(dev, ft_prio, 2383 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2384 dst); 2385 if (IS_ERR(handler_ucast)) { 2386 mlx5_del_flow_rules(handler->rule); 2387 ft_prio->refcount--; 2388 kfree(handler); 2389 handler = handler_ucast; 2390 } else { 2391 list_add(&handler_ucast->list, &handler->list); 2392 } 2393 } 2394 2395 return handler; 2396 } 2397 2398 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2399 struct mlx5_ib_flow_prio *ft_rx, 2400 struct mlx5_ib_flow_prio *ft_tx, 2401 struct mlx5_flow_destination *dst) 2402 { 2403 struct mlx5_ib_flow_handler *handler_rx; 2404 struct mlx5_ib_flow_handler *handler_tx; 2405 int err; 2406 static const struct ib_flow_attr flow_attr = { 2407 .num_of_specs = 0, 2408 .size = sizeof(flow_attr) 2409 }; 2410 2411 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2412 if (IS_ERR(handler_rx)) { 2413 err = PTR_ERR(handler_rx); 2414 goto err; 2415 } 2416 2417 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2418 if (IS_ERR(handler_tx)) { 2419 err = PTR_ERR(handler_tx); 2420 goto err_tx; 2421 } 2422 2423 list_add(&handler_tx->list, &handler_rx->list); 2424 2425 return handler_rx; 2426 2427 err_tx: 2428 mlx5_del_flow_rules(handler_rx->rule); 2429 ft_rx->refcount--; 2430 kfree(handler_rx); 2431 err: 2432 return ERR_PTR(err); 2433 } 2434 2435 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2436 struct ib_flow_attr *flow_attr, 2437 int domain) 2438 { 2439 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2440 struct mlx5_ib_qp *mqp = to_mqp(qp); 2441 struct mlx5_ib_flow_handler *handler = NULL; 2442 struct mlx5_flow_destination *dst = NULL; 2443 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2444 struct mlx5_ib_flow_prio *ft_prio; 2445 int err; 2446 2447 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2448 return ERR_PTR(-ENOMEM); 2449 2450 if (domain != IB_FLOW_DOMAIN_USER || 2451 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2452 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2453 return ERR_PTR(-EINVAL); 2454 2455 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2456 if (!dst) 2457 return ERR_PTR(-ENOMEM); 2458 2459 mutex_lock(&dev->flow_db.lock); 2460 2461 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2462 if (IS_ERR(ft_prio)) { 2463 err = PTR_ERR(ft_prio); 2464 goto unlock; 2465 } 2466 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2467 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2468 if (IS_ERR(ft_prio_tx)) { 2469 err = PTR_ERR(ft_prio_tx); 2470 ft_prio_tx = NULL; 2471 goto destroy_ft; 2472 } 2473 } 2474 2475 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2476 if (mqp->flags & MLX5_IB_QP_RSS) 2477 dst->tir_num = mqp->rss_qp.tirn; 2478 else 2479 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2480 2481 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2482 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2483 handler = create_dont_trap_rule(dev, ft_prio, 2484 flow_attr, dst); 2485 } else { 2486 handler = create_flow_rule(dev, ft_prio, flow_attr, 2487 dst); 2488 } 2489 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2490 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2491 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2492 dst); 2493 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2494 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2495 } else { 2496 err = -EINVAL; 2497 goto destroy_ft; 2498 } 2499 2500 if (IS_ERR(handler)) { 2501 err = PTR_ERR(handler); 2502 handler = NULL; 2503 goto destroy_ft; 2504 } 2505 2506 mutex_unlock(&dev->flow_db.lock); 2507 kfree(dst); 2508 2509 return &handler->ibflow; 2510 2511 destroy_ft: 2512 put_flow_table(dev, ft_prio, false); 2513 if (ft_prio_tx) 2514 put_flow_table(dev, ft_prio_tx, false); 2515 unlock: 2516 mutex_unlock(&dev->flow_db.lock); 2517 kfree(dst); 2518 kfree(handler); 2519 return ERR_PTR(err); 2520 } 2521 2522 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2523 { 2524 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2525 int err; 2526 2527 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2528 if (err) 2529 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2530 ibqp->qp_num, gid->raw); 2531 2532 return err; 2533 } 2534 2535 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2536 { 2537 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2538 int err; 2539 2540 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2541 if (err) 2542 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2543 ibqp->qp_num, gid->raw); 2544 2545 return err; 2546 } 2547 2548 static int init_node_data(struct mlx5_ib_dev *dev) 2549 { 2550 int err; 2551 2552 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2553 if (err) 2554 return err; 2555 2556 dev->mdev->rev_id = dev->mdev->pdev->revision; 2557 2558 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2559 } 2560 2561 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2562 char *buf) 2563 { 2564 struct mlx5_ib_dev *dev = 2565 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2566 2567 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2568 } 2569 2570 static ssize_t show_reg_pages(struct device *device, 2571 struct device_attribute *attr, char *buf) 2572 { 2573 struct mlx5_ib_dev *dev = 2574 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2575 2576 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2577 } 2578 2579 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2580 char *buf) 2581 { 2582 struct mlx5_ib_dev *dev = 2583 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2584 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2585 } 2586 2587 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2588 char *buf) 2589 { 2590 struct mlx5_ib_dev *dev = 2591 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2592 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2593 } 2594 2595 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2596 char *buf) 2597 { 2598 struct mlx5_ib_dev *dev = 2599 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2600 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2601 dev->mdev->board_id); 2602 } 2603 2604 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2605 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2606 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2607 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2608 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2609 2610 static struct device_attribute *mlx5_class_attributes[] = { 2611 &dev_attr_hw_rev, 2612 &dev_attr_hca_type, 2613 &dev_attr_board_id, 2614 &dev_attr_fw_pages, 2615 &dev_attr_reg_pages, 2616 }; 2617 2618 static void pkey_change_handler(struct work_struct *work) 2619 { 2620 struct mlx5_ib_port_resources *ports = 2621 container_of(work, struct mlx5_ib_port_resources, 2622 pkey_change_work); 2623 2624 mutex_lock(&ports->devr->mutex); 2625 mlx5_ib_gsi_pkey_change(ports->gsi); 2626 mutex_unlock(&ports->devr->mutex); 2627 } 2628 2629 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2630 { 2631 struct mlx5_ib_qp *mqp; 2632 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2633 struct mlx5_core_cq *mcq; 2634 struct list_head cq_armed_list; 2635 unsigned long flags_qp; 2636 unsigned long flags_cq; 2637 unsigned long flags; 2638 2639 INIT_LIST_HEAD(&cq_armed_list); 2640 2641 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2642 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2643 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2644 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2645 if (mqp->sq.tail != mqp->sq.head) { 2646 send_mcq = to_mcq(mqp->ibqp.send_cq); 2647 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2648 if (send_mcq->mcq.comp && 2649 mqp->ibqp.send_cq->comp_handler) { 2650 if (!send_mcq->mcq.reset_notify_added) { 2651 send_mcq->mcq.reset_notify_added = 1; 2652 list_add_tail(&send_mcq->mcq.reset_notify, 2653 &cq_armed_list); 2654 } 2655 } 2656 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2657 } 2658 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2659 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2660 /* no handling is needed for SRQ */ 2661 if (!mqp->ibqp.srq) { 2662 if (mqp->rq.tail != mqp->rq.head) { 2663 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2664 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2665 if (recv_mcq->mcq.comp && 2666 mqp->ibqp.recv_cq->comp_handler) { 2667 if (!recv_mcq->mcq.reset_notify_added) { 2668 recv_mcq->mcq.reset_notify_added = 1; 2669 list_add_tail(&recv_mcq->mcq.reset_notify, 2670 &cq_armed_list); 2671 } 2672 } 2673 spin_unlock_irqrestore(&recv_mcq->lock, 2674 flags_cq); 2675 } 2676 } 2677 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2678 } 2679 /*At that point all inflight post send were put to be executed as of we 2680 * lock/unlock above locks Now need to arm all involved CQs. 2681 */ 2682 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2683 mcq->comp(mcq); 2684 } 2685 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2686 } 2687 2688 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2689 enum mlx5_dev_event event, unsigned long param) 2690 { 2691 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2692 struct ib_event ibev; 2693 bool fatal = false; 2694 u8 port = 0; 2695 2696 switch (event) { 2697 case MLX5_DEV_EVENT_SYS_ERROR: 2698 ibev.event = IB_EVENT_DEVICE_FATAL; 2699 mlx5_ib_handle_internal_error(ibdev); 2700 fatal = true; 2701 break; 2702 2703 case MLX5_DEV_EVENT_PORT_UP: 2704 case MLX5_DEV_EVENT_PORT_DOWN: 2705 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2706 port = (u8)param; 2707 2708 /* In RoCE, port up/down events are handled in 2709 * mlx5_netdev_event(). 2710 */ 2711 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2712 IB_LINK_LAYER_ETHERNET) 2713 return; 2714 2715 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2716 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2717 break; 2718 2719 case MLX5_DEV_EVENT_LID_CHANGE: 2720 ibev.event = IB_EVENT_LID_CHANGE; 2721 port = (u8)param; 2722 break; 2723 2724 case MLX5_DEV_EVENT_PKEY_CHANGE: 2725 ibev.event = IB_EVENT_PKEY_CHANGE; 2726 port = (u8)param; 2727 2728 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2729 break; 2730 2731 case MLX5_DEV_EVENT_GUID_CHANGE: 2732 ibev.event = IB_EVENT_GID_CHANGE; 2733 port = (u8)param; 2734 break; 2735 2736 case MLX5_DEV_EVENT_CLIENT_REREG: 2737 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2738 port = (u8)param; 2739 break; 2740 default: 2741 return; 2742 } 2743 2744 ibev.device = &ibdev->ib_dev; 2745 ibev.element.port_num = port; 2746 2747 if (port < 1 || port > ibdev->num_ports) { 2748 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2749 return; 2750 } 2751 2752 if (ibdev->ib_active) 2753 ib_dispatch_event(&ibev); 2754 2755 if (fatal) 2756 ibdev->ib_active = false; 2757 } 2758 2759 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2760 { 2761 struct mlx5_hca_vport_context vport_ctx; 2762 int err; 2763 int port; 2764 2765 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2766 dev->mdev->port_caps[port - 1].has_smi = false; 2767 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2768 MLX5_CAP_PORT_TYPE_IB) { 2769 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2770 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2771 port, 0, 2772 &vport_ctx); 2773 if (err) { 2774 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2775 port, err); 2776 return err; 2777 } 2778 dev->mdev->port_caps[port - 1].has_smi = 2779 vport_ctx.has_smi; 2780 } else { 2781 dev->mdev->port_caps[port - 1].has_smi = true; 2782 } 2783 } 2784 } 2785 return 0; 2786 } 2787 2788 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2789 { 2790 int port; 2791 2792 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2793 mlx5_query_ext_port_caps(dev, port); 2794 } 2795 2796 static int get_port_caps(struct mlx5_ib_dev *dev) 2797 { 2798 struct ib_device_attr *dprops = NULL; 2799 struct ib_port_attr *pprops = NULL; 2800 int err = -ENOMEM; 2801 int port; 2802 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2803 2804 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2805 if (!pprops) 2806 goto out; 2807 2808 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2809 if (!dprops) 2810 goto out; 2811 2812 err = set_has_smi_cap(dev); 2813 if (err) 2814 goto out; 2815 2816 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2817 if (err) { 2818 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2819 goto out; 2820 } 2821 2822 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2823 memset(pprops, 0, sizeof(*pprops)); 2824 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2825 if (err) { 2826 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2827 port, err); 2828 break; 2829 } 2830 dev->mdev->port_caps[port - 1].pkey_table_len = 2831 dprops->max_pkeys; 2832 dev->mdev->port_caps[port - 1].gid_table_len = 2833 pprops->gid_tbl_len; 2834 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2835 dprops->max_pkeys, pprops->gid_tbl_len); 2836 } 2837 2838 out: 2839 kfree(pprops); 2840 kfree(dprops); 2841 2842 return err; 2843 } 2844 2845 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2846 { 2847 int err; 2848 2849 err = mlx5_mr_cache_cleanup(dev); 2850 if (err) 2851 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2852 2853 mlx5_ib_destroy_qp(dev->umrc.qp); 2854 ib_free_cq(dev->umrc.cq); 2855 ib_dealloc_pd(dev->umrc.pd); 2856 } 2857 2858 enum { 2859 MAX_UMR_WR = 128, 2860 }; 2861 2862 static int create_umr_res(struct mlx5_ib_dev *dev) 2863 { 2864 struct ib_qp_init_attr *init_attr = NULL; 2865 struct ib_qp_attr *attr = NULL; 2866 struct ib_pd *pd; 2867 struct ib_cq *cq; 2868 struct ib_qp *qp; 2869 int ret; 2870 2871 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2872 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2873 if (!attr || !init_attr) { 2874 ret = -ENOMEM; 2875 goto error_0; 2876 } 2877 2878 pd = ib_alloc_pd(&dev->ib_dev, 0); 2879 if (IS_ERR(pd)) { 2880 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2881 ret = PTR_ERR(pd); 2882 goto error_0; 2883 } 2884 2885 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2886 if (IS_ERR(cq)) { 2887 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2888 ret = PTR_ERR(cq); 2889 goto error_2; 2890 } 2891 2892 init_attr->send_cq = cq; 2893 init_attr->recv_cq = cq; 2894 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2895 init_attr->cap.max_send_wr = MAX_UMR_WR; 2896 init_attr->cap.max_send_sge = 1; 2897 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2898 init_attr->port_num = 1; 2899 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2900 if (IS_ERR(qp)) { 2901 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2902 ret = PTR_ERR(qp); 2903 goto error_3; 2904 } 2905 qp->device = &dev->ib_dev; 2906 qp->real_qp = qp; 2907 qp->uobject = NULL; 2908 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2909 2910 attr->qp_state = IB_QPS_INIT; 2911 attr->port_num = 1; 2912 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2913 IB_QP_PORT, NULL); 2914 if (ret) { 2915 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2916 goto error_4; 2917 } 2918 2919 memset(attr, 0, sizeof(*attr)); 2920 attr->qp_state = IB_QPS_RTR; 2921 attr->path_mtu = IB_MTU_256; 2922 2923 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2924 if (ret) { 2925 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2926 goto error_4; 2927 } 2928 2929 memset(attr, 0, sizeof(*attr)); 2930 attr->qp_state = IB_QPS_RTS; 2931 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2932 if (ret) { 2933 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2934 goto error_4; 2935 } 2936 2937 dev->umrc.qp = qp; 2938 dev->umrc.cq = cq; 2939 dev->umrc.pd = pd; 2940 2941 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2942 ret = mlx5_mr_cache_init(dev); 2943 if (ret) { 2944 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2945 goto error_4; 2946 } 2947 2948 kfree(attr); 2949 kfree(init_attr); 2950 2951 return 0; 2952 2953 error_4: 2954 mlx5_ib_destroy_qp(qp); 2955 2956 error_3: 2957 ib_free_cq(cq); 2958 2959 error_2: 2960 ib_dealloc_pd(pd); 2961 2962 error_0: 2963 kfree(attr); 2964 kfree(init_attr); 2965 return ret; 2966 } 2967 2968 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2969 { 2970 switch (umr_fence_cap) { 2971 case MLX5_CAP_UMR_FENCE_NONE: 2972 return MLX5_FENCE_MODE_NONE; 2973 case MLX5_CAP_UMR_FENCE_SMALL: 2974 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2975 default: 2976 return MLX5_FENCE_MODE_STRONG_ORDERING; 2977 } 2978 } 2979 2980 static int create_dev_resources(struct mlx5_ib_resources *devr) 2981 { 2982 struct ib_srq_init_attr attr; 2983 struct mlx5_ib_dev *dev; 2984 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2985 int port; 2986 int ret = 0; 2987 2988 dev = container_of(devr, struct mlx5_ib_dev, devr); 2989 2990 mutex_init(&devr->mutex); 2991 2992 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2993 if (IS_ERR(devr->p0)) { 2994 ret = PTR_ERR(devr->p0); 2995 goto error0; 2996 } 2997 devr->p0->device = &dev->ib_dev; 2998 devr->p0->uobject = NULL; 2999 atomic_set(&devr->p0->usecnt, 0); 3000 3001 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3002 if (IS_ERR(devr->c0)) { 3003 ret = PTR_ERR(devr->c0); 3004 goto error1; 3005 } 3006 devr->c0->device = &dev->ib_dev; 3007 devr->c0->uobject = NULL; 3008 devr->c0->comp_handler = NULL; 3009 devr->c0->event_handler = NULL; 3010 devr->c0->cq_context = NULL; 3011 atomic_set(&devr->c0->usecnt, 0); 3012 3013 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3014 if (IS_ERR(devr->x0)) { 3015 ret = PTR_ERR(devr->x0); 3016 goto error2; 3017 } 3018 devr->x0->device = &dev->ib_dev; 3019 devr->x0->inode = NULL; 3020 atomic_set(&devr->x0->usecnt, 0); 3021 mutex_init(&devr->x0->tgt_qp_mutex); 3022 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3023 3024 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3025 if (IS_ERR(devr->x1)) { 3026 ret = PTR_ERR(devr->x1); 3027 goto error3; 3028 } 3029 devr->x1->device = &dev->ib_dev; 3030 devr->x1->inode = NULL; 3031 atomic_set(&devr->x1->usecnt, 0); 3032 mutex_init(&devr->x1->tgt_qp_mutex); 3033 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3034 3035 memset(&attr, 0, sizeof(attr)); 3036 attr.attr.max_sge = 1; 3037 attr.attr.max_wr = 1; 3038 attr.srq_type = IB_SRQT_XRC; 3039 attr.ext.xrc.cq = devr->c0; 3040 attr.ext.xrc.xrcd = devr->x0; 3041 3042 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3043 if (IS_ERR(devr->s0)) { 3044 ret = PTR_ERR(devr->s0); 3045 goto error4; 3046 } 3047 devr->s0->device = &dev->ib_dev; 3048 devr->s0->pd = devr->p0; 3049 devr->s0->uobject = NULL; 3050 devr->s0->event_handler = NULL; 3051 devr->s0->srq_context = NULL; 3052 devr->s0->srq_type = IB_SRQT_XRC; 3053 devr->s0->ext.xrc.xrcd = devr->x0; 3054 devr->s0->ext.xrc.cq = devr->c0; 3055 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3056 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 3057 atomic_inc(&devr->p0->usecnt); 3058 atomic_set(&devr->s0->usecnt, 0); 3059 3060 memset(&attr, 0, sizeof(attr)); 3061 attr.attr.max_sge = 1; 3062 attr.attr.max_wr = 1; 3063 attr.srq_type = IB_SRQT_BASIC; 3064 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3065 if (IS_ERR(devr->s1)) { 3066 ret = PTR_ERR(devr->s1); 3067 goto error5; 3068 } 3069 devr->s1->device = &dev->ib_dev; 3070 devr->s1->pd = devr->p0; 3071 devr->s1->uobject = NULL; 3072 devr->s1->event_handler = NULL; 3073 devr->s1->srq_context = NULL; 3074 devr->s1->srq_type = IB_SRQT_BASIC; 3075 devr->s1->ext.xrc.cq = devr->c0; 3076 atomic_inc(&devr->p0->usecnt); 3077 atomic_set(&devr->s0->usecnt, 0); 3078 3079 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3080 INIT_WORK(&devr->ports[port].pkey_change_work, 3081 pkey_change_handler); 3082 devr->ports[port].devr = devr; 3083 } 3084 3085 return 0; 3086 3087 error5: 3088 mlx5_ib_destroy_srq(devr->s0); 3089 error4: 3090 mlx5_ib_dealloc_xrcd(devr->x1); 3091 error3: 3092 mlx5_ib_dealloc_xrcd(devr->x0); 3093 error2: 3094 mlx5_ib_destroy_cq(devr->c0); 3095 error1: 3096 mlx5_ib_dealloc_pd(devr->p0); 3097 error0: 3098 return ret; 3099 } 3100 3101 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3102 { 3103 struct mlx5_ib_dev *dev = 3104 container_of(devr, struct mlx5_ib_dev, devr); 3105 int port; 3106 3107 mlx5_ib_destroy_srq(devr->s1); 3108 mlx5_ib_destroy_srq(devr->s0); 3109 mlx5_ib_dealloc_xrcd(devr->x0); 3110 mlx5_ib_dealloc_xrcd(devr->x1); 3111 mlx5_ib_destroy_cq(devr->c0); 3112 mlx5_ib_dealloc_pd(devr->p0); 3113 3114 /* Make sure no change P_Key work items are still executing */ 3115 for (port = 0; port < dev->num_ports; ++port) 3116 cancel_work_sync(&devr->ports[port].pkey_change_work); 3117 } 3118 3119 static u32 get_core_cap_flags(struct ib_device *ibdev) 3120 { 3121 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3122 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3123 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3124 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3125 u32 ret = 0; 3126 3127 if (ll == IB_LINK_LAYER_INFINIBAND) 3128 return RDMA_CORE_PORT_IBA_IB; 3129 3130 ret = RDMA_CORE_PORT_RAW_PACKET; 3131 3132 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3133 return ret; 3134 3135 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3136 return ret; 3137 3138 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3139 ret |= RDMA_CORE_PORT_IBA_ROCE; 3140 3141 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3142 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3143 3144 return ret; 3145 } 3146 3147 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3148 struct ib_port_immutable *immutable) 3149 { 3150 struct ib_port_attr attr; 3151 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3152 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3153 int err; 3154 3155 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3156 3157 err = ib_query_port(ibdev, port_num, &attr); 3158 if (err) 3159 return err; 3160 3161 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3162 immutable->gid_tbl_len = attr.gid_tbl_len; 3163 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3164 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3165 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3166 3167 return 0; 3168 } 3169 3170 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3171 size_t str_len) 3172 { 3173 struct mlx5_ib_dev *dev = 3174 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3175 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3176 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3177 } 3178 3179 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3180 { 3181 struct mlx5_core_dev *mdev = dev->mdev; 3182 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3183 MLX5_FLOW_NAMESPACE_LAG); 3184 struct mlx5_flow_table *ft; 3185 int err; 3186 3187 if (!ns || !mlx5_lag_is_active(mdev)) 3188 return 0; 3189 3190 err = mlx5_cmd_create_vport_lag(mdev); 3191 if (err) 3192 return err; 3193 3194 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3195 if (IS_ERR(ft)) { 3196 err = PTR_ERR(ft); 3197 goto err_destroy_vport_lag; 3198 } 3199 3200 dev->flow_db.lag_demux_ft = ft; 3201 return 0; 3202 3203 err_destroy_vport_lag: 3204 mlx5_cmd_destroy_vport_lag(mdev); 3205 return err; 3206 } 3207 3208 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3209 { 3210 struct mlx5_core_dev *mdev = dev->mdev; 3211 3212 if (dev->flow_db.lag_demux_ft) { 3213 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3214 dev->flow_db.lag_demux_ft = NULL; 3215 3216 mlx5_cmd_destroy_vport_lag(mdev); 3217 } 3218 } 3219 3220 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3221 { 3222 int err; 3223 3224 dev->roce.nb.notifier_call = mlx5_netdev_event; 3225 err = register_netdevice_notifier(&dev->roce.nb); 3226 if (err) { 3227 dev->roce.nb.notifier_call = NULL; 3228 return err; 3229 } 3230 3231 return 0; 3232 } 3233 3234 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3235 { 3236 if (dev->roce.nb.notifier_call) { 3237 unregister_netdevice_notifier(&dev->roce.nb); 3238 dev->roce.nb.notifier_call = NULL; 3239 } 3240 } 3241 3242 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3243 { 3244 int err; 3245 3246 err = mlx5_add_netdev_notifier(dev); 3247 if (err) 3248 return err; 3249 3250 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3251 err = mlx5_nic_vport_enable_roce(dev->mdev); 3252 if (err) 3253 goto err_unregister_netdevice_notifier; 3254 } 3255 3256 err = mlx5_eth_lag_init(dev); 3257 if (err) 3258 goto err_disable_roce; 3259 3260 return 0; 3261 3262 err_disable_roce: 3263 if (MLX5_CAP_GEN(dev->mdev, roce)) 3264 mlx5_nic_vport_disable_roce(dev->mdev); 3265 3266 err_unregister_netdevice_notifier: 3267 mlx5_remove_netdev_notifier(dev); 3268 return err; 3269 } 3270 3271 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3272 { 3273 mlx5_eth_lag_cleanup(dev); 3274 if (MLX5_CAP_GEN(dev->mdev, roce)) 3275 mlx5_nic_vport_disable_roce(dev->mdev); 3276 } 3277 3278 struct mlx5_ib_counter { 3279 const char *name; 3280 size_t offset; 3281 }; 3282 3283 #define INIT_Q_COUNTER(_name) \ 3284 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3285 3286 static const struct mlx5_ib_counter basic_q_cnts[] = { 3287 INIT_Q_COUNTER(rx_write_requests), 3288 INIT_Q_COUNTER(rx_read_requests), 3289 INIT_Q_COUNTER(rx_atomic_requests), 3290 INIT_Q_COUNTER(out_of_buffer), 3291 }; 3292 3293 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3294 INIT_Q_COUNTER(out_of_sequence), 3295 }; 3296 3297 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3298 INIT_Q_COUNTER(duplicate_request), 3299 INIT_Q_COUNTER(rnr_nak_retry_err), 3300 INIT_Q_COUNTER(packet_seq_err), 3301 INIT_Q_COUNTER(implied_nak_seq_err), 3302 INIT_Q_COUNTER(local_ack_timeout_err), 3303 }; 3304 3305 #define INIT_CONG_COUNTER(_name) \ 3306 { .name = #_name, .offset = \ 3307 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3308 3309 static const struct mlx5_ib_counter cong_cnts[] = { 3310 INIT_CONG_COUNTER(rp_cnp_ignored), 3311 INIT_CONG_COUNTER(rp_cnp_handled), 3312 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3313 INIT_CONG_COUNTER(np_cnp_sent), 3314 }; 3315 3316 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3317 { 3318 unsigned int i; 3319 3320 for (i = 0; i < dev->num_ports; i++) { 3321 mlx5_core_dealloc_q_counter(dev->mdev, 3322 dev->port[i].cnts.set_id); 3323 kfree(dev->port[i].cnts.names); 3324 kfree(dev->port[i].cnts.offsets); 3325 } 3326 } 3327 3328 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3329 struct mlx5_ib_counters *cnts) 3330 { 3331 u32 num_counters; 3332 3333 num_counters = ARRAY_SIZE(basic_q_cnts); 3334 3335 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3336 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3337 3338 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3339 num_counters += ARRAY_SIZE(retrans_q_cnts); 3340 cnts->num_q_counters = num_counters; 3341 3342 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3343 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3344 num_counters += ARRAY_SIZE(cong_cnts); 3345 } 3346 3347 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3348 if (!cnts->names) 3349 return -ENOMEM; 3350 3351 cnts->offsets = kcalloc(num_counters, 3352 sizeof(cnts->offsets), GFP_KERNEL); 3353 if (!cnts->offsets) 3354 goto err_names; 3355 3356 return 0; 3357 3358 err_names: 3359 kfree(cnts->names); 3360 return -ENOMEM; 3361 } 3362 3363 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3364 const char **names, 3365 size_t *offsets) 3366 { 3367 int i; 3368 int j = 0; 3369 3370 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3371 names[j] = basic_q_cnts[i].name; 3372 offsets[j] = basic_q_cnts[i].offset; 3373 } 3374 3375 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3376 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3377 names[j] = out_of_seq_q_cnts[i].name; 3378 offsets[j] = out_of_seq_q_cnts[i].offset; 3379 } 3380 } 3381 3382 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3383 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3384 names[j] = retrans_q_cnts[i].name; 3385 offsets[j] = retrans_q_cnts[i].offset; 3386 } 3387 } 3388 3389 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3390 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3391 names[j] = cong_cnts[i].name; 3392 offsets[j] = cong_cnts[i].offset; 3393 } 3394 } 3395 } 3396 3397 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3398 { 3399 int i; 3400 int ret; 3401 3402 for (i = 0; i < dev->num_ports; i++) { 3403 struct mlx5_ib_port *port = &dev->port[i]; 3404 3405 ret = mlx5_core_alloc_q_counter(dev->mdev, 3406 &port->cnts.set_id); 3407 if (ret) { 3408 mlx5_ib_warn(dev, 3409 "couldn't allocate queue counter for port %d, err %d\n", 3410 i + 1, ret); 3411 goto dealloc_counters; 3412 } 3413 3414 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3415 if (ret) 3416 goto dealloc_counters; 3417 3418 mlx5_ib_fill_counters(dev, port->cnts.names, 3419 port->cnts.offsets); 3420 } 3421 3422 return 0; 3423 3424 dealloc_counters: 3425 while (--i >= 0) 3426 mlx5_core_dealloc_q_counter(dev->mdev, 3427 dev->port[i].cnts.set_id); 3428 3429 return ret; 3430 } 3431 3432 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3433 u8 port_num) 3434 { 3435 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3436 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3437 3438 /* We support only per port stats */ 3439 if (port_num == 0) 3440 return NULL; 3441 3442 return rdma_alloc_hw_stats_struct(port->cnts.names, 3443 port->cnts.num_q_counters + 3444 port->cnts.num_cong_counters, 3445 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3446 } 3447 3448 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3449 struct mlx5_ib_port *port, 3450 struct rdma_hw_stats *stats) 3451 { 3452 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3453 void *out; 3454 __be32 val; 3455 int ret, i; 3456 3457 out = kvzalloc(outlen, GFP_KERNEL); 3458 if (!out) 3459 return -ENOMEM; 3460 3461 ret = mlx5_core_query_q_counter(dev->mdev, 3462 port->cnts.set_id, 0, 3463 out, outlen); 3464 if (ret) 3465 goto free; 3466 3467 for (i = 0; i < port->cnts.num_q_counters; i++) { 3468 val = *(__be32 *)(out + port->cnts.offsets[i]); 3469 stats->value[i] = (u64)be32_to_cpu(val); 3470 } 3471 3472 free: 3473 kvfree(out); 3474 return ret; 3475 } 3476 3477 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3478 struct mlx5_ib_port *port, 3479 struct rdma_hw_stats *stats) 3480 { 3481 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3482 void *out; 3483 int ret, i; 3484 int offset = port->cnts.num_q_counters; 3485 3486 out = kvzalloc(outlen, GFP_KERNEL); 3487 if (!out) 3488 return -ENOMEM; 3489 3490 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3491 if (ret) 3492 goto free; 3493 3494 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3495 stats->value[i + offset] = 3496 be64_to_cpup((__be64 *)(out + 3497 port->cnts.offsets[i + offset])); 3498 } 3499 3500 free: 3501 kvfree(out); 3502 return ret; 3503 } 3504 3505 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3506 struct rdma_hw_stats *stats, 3507 u8 port_num, int index) 3508 { 3509 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3510 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3511 int ret, num_counters; 3512 3513 if (!stats) 3514 return -EINVAL; 3515 3516 ret = mlx5_ib_query_q_counters(dev, port, stats); 3517 if (ret) 3518 return ret; 3519 num_counters = port->cnts.num_q_counters; 3520 3521 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3522 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3523 if (ret) 3524 return ret; 3525 num_counters += port->cnts.num_cong_counters; 3526 } 3527 3528 return num_counters; 3529 } 3530 3531 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3532 { 3533 return mlx5_rdma_netdev_free(netdev); 3534 } 3535 3536 static struct net_device* 3537 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3538 u8 port_num, 3539 enum rdma_netdev_t type, 3540 const char *name, 3541 unsigned char name_assign_type, 3542 void (*setup)(struct net_device *)) 3543 { 3544 struct net_device *netdev; 3545 struct rdma_netdev *rn; 3546 3547 if (type != RDMA_NETDEV_IPOIB) 3548 return ERR_PTR(-EOPNOTSUPP); 3549 3550 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3551 name, setup); 3552 if (likely(!IS_ERR_OR_NULL(netdev))) { 3553 rn = netdev_priv(netdev); 3554 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3555 } 3556 return netdev; 3557 } 3558 3559 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3560 { 3561 struct mlx5_ib_dev *dev; 3562 enum rdma_link_layer ll; 3563 int port_type_cap; 3564 const char *name; 3565 int err; 3566 int i; 3567 3568 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3569 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3570 3571 printk_once(KERN_INFO "%s", mlx5_version); 3572 3573 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3574 if (!dev) 3575 return NULL; 3576 3577 dev->mdev = mdev; 3578 3579 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3580 GFP_KERNEL); 3581 if (!dev->port) 3582 goto err_dealloc; 3583 3584 rwlock_init(&dev->roce.netdev_lock); 3585 err = get_port_caps(dev); 3586 if (err) 3587 goto err_free_port; 3588 3589 if (mlx5_use_mad_ifc(dev)) 3590 get_ext_port_caps(dev); 3591 3592 if (!mlx5_lag_is_active(mdev)) 3593 name = "mlx5_%d"; 3594 else 3595 name = "mlx5_bond_%d"; 3596 3597 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3598 dev->ib_dev.owner = THIS_MODULE; 3599 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3600 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3601 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3602 dev->ib_dev.phys_port_cnt = dev->num_ports; 3603 dev->ib_dev.num_comp_vectors = 3604 dev->mdev->priv.eq_table.num_comp_vectors; 3605 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3606 3607 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3608 dev->ib_dev.uverbs_cmd_mask = 3609 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3610 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3611 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3612 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3613 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3614 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3615 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3616 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3617 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3618 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3619 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3620 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3621 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3622 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3623 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3624 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3625 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3626 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3627 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3628 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3629 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3630 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3631 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3632 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3633 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3634 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3635 dev->ib_dev.uverbs_ex_cmd_mask = 3636 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3637 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3638 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3639 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3640 3641 dev->ib_dev.query_device = mlx5_ib_query_device; 3642 dev->ib_dev.query_port = mlx5_ib_query_port; 3643 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3644 if (ll == IB_LINK_LAYER_ETHERNET) 3645 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3646 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3647 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3648 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3649 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3650 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3651 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3652 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3653 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3654 dev->ib_dev.mmap = mlx5_ib_mmap; 3655 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3656 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3657 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3658 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3659 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3660 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3661 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3662 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3663 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3664 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3665 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3666 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3667 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3668 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3669 dev->ib_dev.post_send = mlx5_ib_post_send; 3670 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3671 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3672 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3673 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3674 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3675 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3676 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3677 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3678 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3679 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3680 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3681 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3682 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3683 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3684 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3685 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3686 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3687 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3688 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3689 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 3690 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 3691 3692 if (mlx5_core_is_pf(mdev)) { 3693 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3694 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3695 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3696 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3697 } 3698 3699 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3700 3701 mlx5_ib_internal_fill_odp_caps(dev); 3702 3703 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3704 3705 if (MLX5_CAP_GEN(mdev, imaicl)) { 3706 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3707 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3708 dev->ib_dev.uverbs_cmd_mask |= 3709 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3710 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3711 } 3712 3713 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3714 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3715 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3716 } 3717 3718 if (MLX5_CAP_GEN(mdev, xrc)) { 3719 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3720 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3721 dev->ib_dev.uverbs_cmd_mask |= 3722 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3723 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3724 } 3725 3726 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3727 IB_LINK_LAYER_ETHERNET) { 3728 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3729 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3730 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3731 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3732 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3733 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3734 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3735 dev->ib_dev.uverbs_ex_cmd_mask |= 3736 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3737 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3738 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3739 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3740 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3741 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3742 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3743 } 3744 err = init_node_data(dev); 3745 if (err) 3746 goto err_free_port; 3747 3748 mutex_init(&dev->flow_db.lock); 3749 mutex_init(&dev->cap_mask_mutex); 3750 INIT_LIST_HEAD(&dev->qp_list); 3751 spin_lock_init(&dev->reset_flow_resource_lock); 3752 3753 if (ll == IB_LINK_LAYER_ETHERNET) { 3754 err = mlx5_enable_eth(dev); 3755 if (err) 3756 goto err_free_port; 3757 } 3758 3759 err = create_dev_resources(&dev->devr); 3760 if (err) 3761 goto err_disable_eth; 3762 3763 err = mlx5_ib_odp_init_one(dev); 3764 if (err) 3765 goto err_rsrc; 3766 3767 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3768 err = mlx5_ib_alloc_counters(dev); 3769 if (err) 3770 goto err_odp; 3771 } 3772 3773 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3774 if (!dev->mdev->priv.uar) 3775 goto err_cnt; 3776 3777 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3778 if (err) 3779 goto err_uar_page; 3780 3781 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3782 if (err) 3783 goto err_bfreg; 3784 3785 err = ib_register_device(&dev->ib_dev, NULL); 3786 if (err) 3787 goto err_fp_bfreg; 3788 3789 err = create_umr_res(dev); 3790 if (err) 3791 goto err_dev; 3792 3793 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3794 err = device_create_file(&dev->ib_dev.dev, 3795 mlx5_class_attributes[i]); 3796 if (err) 3797 goto err_umrc; 3798 } 3799 3800 dev->ib_active = true; 3801 3802 return dev; 3803 3804 err_umrc: 3805 destroy_umrc_res(dev); 3806 3807 err_dev: 3808 ib_unregister_device(&dev->ib_dev); 3809 3810 err_fp_bfreg: 3811 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3812 3813 err_bfreg: 3814 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3815 3816 err_uar_page: 3817 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3818 3819 err_cnt: 3820 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3821 mlx5_ib_dealloc_counters(dev); 3822 3823 err_odp: 3824 mlx5_ib_odp_remove_one(dev); 3825 3826 err_rsrc: 3827 destroy_dev_resources(&dev->devr); 3828 3829 err_disable_eth: 3830 if (ll == IB_LINK_LAYER_ETHERNET) { 3831 mlx5_disable_eth(dev); 3832 mlx5_remove_netdev_notifier(dev); 3833 } 3834 3835 err_free_port: 3836 kfree(dev->port); 3837 3838 err_dealloc: 3839 ib_dealloc_device((struct ib_device *)dev); 3840 3841 return NULL; 3842 } 3843 3844 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3845 { 3846 struct mlx5_ib_dev *dev = context; 3847 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3848 3849 mlx5_remove_netdev_notifier(dev); 3850 ib_unregister_device(&dev->ib_dev); 3851 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3852 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3853 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 3854 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3855 mlx5_ib_dealloc_counters(dev); 3856 destroy_umrc_res(dev); 3857 mlx5_ib_odp_remove_one(dev); 3858 destroy_dev_resources(&dev->devr); 3859 if (ll == IB_LINK_LAYER_ETHERNET) 3860 mlx5_disable_eth(dev); 3861 kfree(dev->port); 3862 ib_dealloc_device(&dev->ib_dev); 3863 } 3864 3865 static struct mlx5_interface mlx5_ib_interface = { 3866 .add = mlx5_ib_add, 3867 .remove = mlx5_ib_remove, 3868 .event = mlx5_ib_event, 3869 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3870 .pfault = mlx5_ib_pfault, 3871 #endif 3872 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3873 }; 3874 3875 static int __init mlx5_ib_init(void) 3876 { 3877 int err; 3878 3879 mlx5_ib_odp_init(); 3880 3881 err = mlx5_register_interface(&mlx5_ib_interface); 3882 3883 return err; 3884 } 3885 3886 static void __exit mlx5_ib_cleanup(void) 3887 { 3888 mlx5_unregister_interface(&mlx5_ib_interface); 3889 } 3890 3891 module_init(mlx5_ib_init); 3892 module_exit(mlx5_ib_cleanup); 3893