1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <linux/in.h> 57 #include <linux/etherdevice.h> 58 #include <linux/mlx5/fs.h> 59 #include <linux/mlx5/vport.h> 60 #include "mlx5_ib.h" 61 #include "cmd.h" 62 #include <linux/mlx5/vport.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int get_port_state(struct ib_device *ibdev, 102 u8 port_num, 103 enum ib_port_state *state) 104 { 105 struct ib_port_attr attr; 106 int ret; 107 108 memset(&attr, 0, sizeof(attr)); 109 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 110 if (!ret) 111 *state = attr.state; 112 return ret; 113 } 114 115 static int mlx5_netdev_event(struct notifier_block *this, 116 unsigned long event, void *ptr) 117 { 118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 120 roce.nb); 121 122 switch (event) { 123 case NETDEV_REGISTER: 124 case NETDEV_UNREGISTER: 125 write_lock(&ibdev->roce.netdev_lock); 126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 128 NULL : ndev; 129 write_unlock(&ibdev->roce.netdev_lock); 130 break; 131 132 case NETDEV_CHANGE: 133 case NETDEV_UP: 134 case NETDEV_DOWN: { 135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 136 struct net_device *upper = NULL; 137 138 if (lag_ndev) { 139 upper = netdev_master_upper_dev_get(lag_ndev); 140 dev_put(lag_ndev); 141 } 142 143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 144 && ibdev->ib_active) { 145 struct ib_event ibev = { }; 146 enum ib_port_state port_state; 147 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state)) 149 return NOTIFY_DONE; 150 151 if (ibdev->roce.last_port_state == port_state) 152 return NOTIFY_DONE; 153 154 ibdev->roce.last_port_state = port_state; 155 ibev.device = &ibdev->ib_dev; 156 if (port_state == IB_PORT_DOWN) 157 ibev.event = IB_EVENT_PORT_ERR; 158 else if (port_state == IB_PORT_ACTIVE) 159 ibev.event = IB_EVENT_PORT_ACTIVE; 160 else 161 return NOTIFY_DONE; 162 163 ibev.element.port_num = 1; 164 ib_dispatch_event(&ibev); 165 } 166 break; 167 } 168 169 default: 170 break; 171 } 172 173 return NOTIFY_DONE; 174 } 175 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 177 u8 port_num) 178 { 179 struct mlx5_ib_dev *ibdev = to_mdev(device); 180 struct net_device *ndev; 181 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 183 if (ndev) 184 return ndev; 185 186 /* Ensure ndev does not disappear before we invoke dev_hold() 187 */ 188 read_lock(&ibdev->roce.netdev_lock); 189 ndev = ibdev->roce.netdev; 190 if (ndev) 191 dev_hold(ndev); 192 read_unlock(&ibdev->roce.netdev_lock); 193 194 return ndev; 195 } 196 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 198 u8 *active_width) 199 { 200 switch (eth_proto_oper) { 201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_SDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 215 *active_width = IB_WIDTH_1X; 216 *active_speed = IB_SPEED_QDR; 217 break; 218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 221 *active_width = IB_WIDTH_1X; 222 *active_speed = IB_SPEED_EDR; 223 break; 224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 228 *active_width = IB_WIDTH_4X; 229 *active_speed = IB_SPEED_QDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 234 *active_width = IB_WIDTH_1X; 235 *active_speed = IB_SPEED_HDR; 236 break; 237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 238 *active_width = IB_WIDTH_4X; 239 *active_speed = IB_SPEED_FDR; 240 break; 241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 256 struct ib_port_attr *props) 257 { 258 struct mlx5_ib_dev *dev = to_mdev(device); 259 struct mlx5_core_dev *mdev = dev->mdev; 260 struct net_device *ndev, *upper; 261 enum ib_mtu ndev_ib_mtu; 262 u16 qkey_viol_cntr; 263 u32 eth_prot_oper; 264 int err; 265 266 /* Possible bad flows are checked before filling out props so in case 267 * of an error it will still be zeroed out. 268 */ 269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 270 if (err) 271 return err; 272 273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 274 &props->active_width); 275 276 props->port_cap_flags |= IB_PORT_CM_SUP; 277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 278 279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 280 roce_address_table_size); 281 props->max_mtu = IB_MTU_4096; 282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 283 props->pkey_tbl_len = 1; 284 props->state = IB_PORT_DOWN; 285 props->phys_state = 3; 286 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 288 props->qkey_viol_cntr = qkey_viol_cntr; 289 290 ndev = mlx5_ib_get_netdev(device, port_num); 291 if (!ndev) 292 return 0; 293 294 if (mlx5_lag_is_active(dev->mdev)) { 295 rcu_read_lock(); 296 upper = netdev_master_upper_dev_get_rcu(ndev); 297 if (upper) { 298 dev_put(ndev); 299 ndev = upper; 300 dev_hold(ndev); 301 } 302 rcu_read_unlock(); 303 } 304 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 306 props->state = IB_PORT_ACTIVE; 307 props->phys_state = 5; 308 } 309 310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 311 312 dev_put(ndev); 313 314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 315 return 0; 316 } 317 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 319 unsigned int index, const union ib_gid *gid, 320 const struct ib_gid_attr *attr) 321 { 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 323 u8 roce_version = 0; 324 u8 roce_l3_type = 0; 325 bool vlan = false; 326 u8 mac[ETH_ALEN]; 327 u16 vlan_id = 0; 328 329 if (gid) { 330 gid_type = attr->gid_type; 331 ether_addr_copy(mac, attr->ndev->dev_addr); 332 333 if (is_vlan_dev(attr->ndev)) { 334 vlan = true; 335 vlan_id = vlan_dev_vlan_id(attr->ndev); 336 } 337 } 338 339 switch (gid_type) { 340 case IB_GID_TYPE_IB: 341 roce_version = MLX5_ROCE_VERSION_1; 342 break; 343 case IB_GID_TYPE_ROCE_UDP_ENCAP: 344 roce_version = MLX5_ROCE_VERSION_2; 345 if (ipv6_addr_v4mapped((void *)gid)) 346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 347 else 348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 349 break; 350 351 default: 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 353 } 354 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 356 roce_l3_type, gid->raw, mac, vlan, 357 vlan_id); 358 } 359 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 361 unsigned int index, const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 __always_unused void **context) 364 { 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 366 } 367 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 369 unsigned int index, __always_unused void **context) 370 { 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 372 } 373 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 375 int index) 376 { 377 struct ib_gid_attr attr; 378 union ib_gid gid; 379 380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 381 return 0; 382 383 if (!attr.ndev) 384 return 0; 385 386 dev_put(attr.ndev); 387 388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 389 return 0; 390 391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 392 } 393 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 395 int index, enum ib_gid_type *gid_type) 396 { 397 struct ib_gid_attr attr; 398 union ib_gid gid; 399 int ret; 400 401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (!attr.ndev) 406 return -ENODEV; 407 408 dev_put(attr.ndev); 409 410 *gid_type = attr.gid_type; 411 412 return 0; 413 } 414 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 416 { 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 418 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 419 return 0; 420 } 421 422 enum { 423 MLX5_VPORT_ACCESS_METHOD_MAD, 424 MLX5_VPORT_ACCESS_METHOD_HCA, 425 MLX5_VPORT_ACCESS_METHOD_NIC, 426 }; 427 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 429 { 430 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 431 return MLX5_VPORT_ACCESS_METHOD_MAD; 432 433 if (mlx5_ib_port_link_layer(ibdev, 1) == 434 IB_LINK_LAYER_ETHERNET) 435 return MLX5_VPORT_ACCESS_METHOD_NIC; 436 437 return MLX5_VPORT_ACCESS_METHOD_HCA; 438 } 439 440 static void get_atomic_caps(struct mlx5_ib_dev *dev, 441 struct ib_device_attr *props) 442 { 443 u8 tmp; 444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 446 u8 atomic_req_8B_endianness_mode = 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 448 449 /* Check if HW supports 8 bytes standard atomic operations and capable 450 * of host endianness respond 451 */ 452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 453 if (((atomic_operations & tmp) == tmp) && 454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 455 (atomic_req_8B_endianness_mode)) { 456 props->atomic_cap = IB_ATOMIC_HCA; 457 } else { 458 props->atomic_cap = IB_ATOMIC_NONE; 459 } 460 } 461 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 463 __be64 *sys_image_guid) 464 { 465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 466 struct mlx5_core_dev *mdev = dev->mdev; 467 u64 tmp; 468 int err; 469 470 switch (mlx5_get_vport_access_method(ibdev)) { 471 case MLX5_VPORT_ACCESS_METHOD_MAD: 472 return mlx5_query_mad_ifc_system_image_guid(ibdev, 473 sys_image_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *sys_image_guid = cpu_to_be64(tmp); 489 490 return err; 491 492 } 493 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 495 u16 *max_pkeys) 496 { 497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 498 struct mlx5_core_dev *mdev = dev->mdev; 499 500 switch (mlx5_get_vport_access_method(ibdev)) { 501 case MLX5_VPORT_ACCESS_METHOD_MAD: 502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 503 504 case MLX5_VPORT_ACCESS_METHOD_HCA: 505 case MLX5_VPORT_ACCESS_METHOD_NIC: 506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 507 pkey_table_size)); 508 return 0; 509 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int mlx5_query_vendor_id(struct ib_device *ibdev, 516 u32 *vendor_id) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 520 switch (mlx5_get_vport_access_method(ibdev)) { 521 case MLX5_VPORT_ACCESS_METHOD_MAD: 522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 527 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 534 __be64 *node_guid) 535 { 536 u64 tmp; 537 int err; 538 539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 540 case MLX5_VPORT_ACCESS_METHOD_MAD: 541 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 542 543 case MLX5_VPORT_ACCESS_METHOD_HCA: 544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 case MLX5_VPORT_ACCESS_METHOD_NIC: 548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 if (!err) 556 *node_guid = cpu_to_be64(tmp); 557 558 return err; 559 } 560 561 struct mlx5_reg_node_desc { 562 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 563 }; 564 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 566 { 567 struct mlx5_reg_node_desc in; 568 569 if (mlx5_use_mad_ifc(dev)) 570 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 571 572 memset(&in, 0, sizeof(in)); 573 574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 575 sizeof(struct mlx5_reg_node_desc), 576 MLX5_REG_NODE_DESC, 0, 0); 577 } 578 579 static int mlx5_ib_query_device(struct ib_device *ibdev, 580 struct ib_device_attr *props, 581 struct ib_udata *uhw) 582 { 583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 584 struct mlx5_core_dev *mdev = dev->mdev; 585 int err = -ENOMEM; 586 int max_sq_desc; 587 int max_rq_sg; 588 int max_sq_sg; 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 590 struct mlx5_ib_query_device_resp resp = {}; 591 size_t resp_len; 592 u64 max_tso; 593 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 595 if (uhw->outlen && uhw->outlen < resp_len) 596 return -EINVAL; 597 else 598 resp.response_length = resp_len; 599 600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 601 return -EINVAL; 602 603 memset(props, 0, sizeof(*props)); 604 err = mlx5_query_system_image_guid(ibdev, 605 &props->sys_image_guid); 606 if (err) 607 return err; 608 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 610 if (err) 611 return err; 612 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 614 if (err) 615 return err; 616 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 618 (fw_rev_min(dev->mdev) << 16) | 619 fw_rev_sub(dev->mdev); 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 621 IB_DEVICE_PORT_ACTIVE_EVENT | 622 IB_DEVICE_SYS_IMAGE_GUID | 623 IB_DEVICE_RC_RNR_NAK_GEN; 624 625 if (MLX5_CAP_GEN(mdev, pkv)) 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 627 if (MLX5_CAP_GEN(mdev, qkv)) 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 629 if (MLX5_CAP_GEN(mdev, apm)) 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 631 if (MLX5_CAP_GEN(mdev, xrc)) 632 props->device_cap_flags |= IB_DEVICE_XRC; 633 if (MLX5_CAP_GEN(mdev, imaicl)) { 634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 635 IB_DEVICE_MEM_WINDOW_TYPE_2B; 636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 637 /* We support 'Gappy' memory registration too */ 638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 639 } 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 641 if (MLX5_CAP_GEN(mdev, sho)) { 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 643 /* At this stage no support for signature handover */ 644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 645 IB_PROT_T10DIF_TYPE_2 | 646 IB_PROT_T10DIF_TYPE_3; 647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 648 IB_GUARD_T10DIF_CSUM; 649 } 650 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 652 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 654 if (MLX5_CAP_ETH(mdev, csum_cap)) { 655 /* Legacy bit to support old userspace libraries */ 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 658 } 659 660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 661 props->raw_packet_caps |= 662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 663 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 666 if (max_tso) { 667 resp.tso_caps.max_tso = 1 << max_tso; 668 resp.tso_caps.supported_qpts |= 669 1 << IB_QPT_RAW_PACKET; 670 resp.response_length += sizeof(resp.tso_caps); 671 } 672 } 673 674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 675 resp.rss_caps.rx_hash_function = 676 MLX5_RX_HASH_FUNC_TOEPLITZ; 677 resp.rss_caps.rx_hash_fields_mask = 678 MLX5_RX_HASH_SRC_IPV4 | 679 MLX5_RX_HASH_DST_IPV4 | 680 MLX5_RX_HASH_SRC_IPV6 | 681 MLX5_RX_HASH_DST_IPV6 | 682 MLX5_RX_HASH_SRC_PORT_TCP | 683 MLX5_RX_HASH_DST_PORT_TCP | 684 MLX5_RX_HASH_SRC_PORT_UDP | 685 MLX5_RX_HASH_DST_PORT_UDP; 686 resp.response_length += sizeof(resp.rss_caps); 687 } 688 } else { 689 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 690 resp.response_length += sizeof(resp.tso_caps); 691 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 692 resp.response_length += sizeof(resp.rss_caps); 693 } 694 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 697 props->device_cap_flags |= IB_DEVICE_UD_TSO; 698 } 699 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 701 MLX5_CAP_GEN(dev->mdev, general_notification_event)) 702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 703 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 707 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 710 /* Legacy bit to support old userspace libraries */ 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 713 } 714 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 717 718 if (MLX5_CAP_GEN(mdev, end_pad)) 719 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 720 721 props->vendor_part_id = mdev->pdev->device; 722 props->hw_ver = mdev->pdev->revision; 723 724 props->max_mr_size = ~0ull; 725 props->page_size_cap = ~(min_page_size - 1); 726 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 727 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 728 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 729 sizeof(struct mlx5_wqe_data_seg); 730 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 731 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 732 sizeof(struct mlx5_wqe_raddr_seg)) / 733 sizeof(struct mlx5_wqe_data_seg); 734 props->max_sge = min(max_rq_sg, max_sq_sg); 735 props->max_sge_rd = MLX5_MAX_SGE_RD; 736 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 737 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 738 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 739 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 740 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 741 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 742 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 743 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 744 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 745 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 746 props->max_srq_sge = max_rq_sg - 1; 747 props->max_fast_reg_page_list_len = 748 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 749 get_atomic_caps(dev, props); 750 props->masked_atomic_cap = IB_ATOMIC_NONE; 751 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 752 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 753 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 754 props->max_mcast_grp; 755 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 756 props->max_ah = INT_MAX; 757 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 758 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 759 760 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 761 if (MLX5_CAP_GEN(mdev, pg)) 762 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 763 props->odp_caps = dev->odp_caps; 764 #endif 765 766 if (MLX5_CAP_GEN(mdev, cd)) 767 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 768 769 if (!mlx5_core_is_pf(mdev)) 770 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 771 772 if (mlx5_ib_port_link_layer(ibdev, 1) == 773 IB_LINK_LAYER_ETHERNET) { 774 props->rss_caps.max_rwq_indirection_tables = 775 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 776 props->rss_caps.max_rwq_indirection_table_size = 777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 778 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 779 props->max_wq_type_rq = 780 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 781 } 782 783 if (MLX5_CAP_GEN(mdev, tag_matching)) { 784 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 785 props->tm_caps.max_num_tags = 786 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 787 props->tm_caps.flags = IB_TM_CAP_RC; 788 props->tm_caps.max_ops = 789 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 790 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 791 } 792 793 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 794 props->cq_caps.max_cq_moderation_count = 795 MLX5_MAX_CQ_COUNT; 796 props->cq_caps.max_cq_moderation_period = 797 MLX5_MAX_CQ_PERIOD; 798 } 799 800 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 801 resp.cqe_comp_caps.max_num = 802 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 803 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 804 resp.cqe_comp_caps.supported_format = 805 MLX5_IB_CQE_RES_FORMAT_HASH | 806 MLX5_IB_CQE_RES_FORMAT_CSUM; 807 resp.response_length += sizeof(resp.cqe_comp_caps); 808 } 809 810 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 811 if (MLX5_CAP_QOS(mdev, packet_pacing) && 812 MLX5_CAP_GEN(mdev, qos)) { 813 resp.packet_pacing_caps.qp_rate_limit_max = 814 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 815 resp.packet_pacing_caps.qp_rate_limit_min = 816 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 817 resp.packet_pacing_caps.supported_qpts |= 818 1 << IB_QPT_RAW_PACKET; 819 } 820 resp.response_length += sizeof(resp.packet_pacing_caps); 821 } 822 823 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 824 uhw->outlen)) { 825 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 826 resp.mlx5_ib_support_multi_pkt_send_wqes = 827 MLX5_IB_ALLOW_MPW; 828 829 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 830 resp.mlx5_ib_support_multi_pkt_send_wqes |= 831 MLX5_IB_SUPPORT_EMPW; 832 833 resp.response_length += 834 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 835 } 836 837 if (field_avail(typeof(resp), flags, uhw->outlen)) { 838 resp.response_length += sizeof(resp.flags); 839 840 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 841 resp.flags |= 842 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 843 844 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 845 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 846 } 847 848 if (field_avail(typeof(resp), sw_parsing_caps, 849 uhw->outlen)) { 850 resp.response_length += sizeof(resp.sw_parsing_caps); 851 if (MLX5_CAP_ETH(mdev, swp)) { 852 resp.sw_parsing_caps.sw_parsing_offloads |= 853 MLX5_IB_SW_PARSING; 854 855 if (MLX5_CAP_ETH(mdev, swp_csum)) 856 resp.sw_parsing_caps.sw_parsing_offloads |= 857 MLX5_IB_SW_PARSING_CSUM; 858 859 if (MLX5_CAP_ETH(mdev, swp_lso)) 860 resp.sw_parsing_caps.sw_parsing_offloads |= 861 MLX5_IB_SW_PARSING_LSO; 862 863 if (resp.sw_parsing_caps.sw_parsing_offloads) 864 resp.sw_parsing_caps.supported_qpts = 865 BIT(IB_QPT_RAW_PACKET); 866 } 867 } 868 869 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) { 870 resp.response_length += sizeof(resp.striding_rq_caps); 871 if (MLX5_CAP_GEN(mdev, striding_rq)) { 872 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 873 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 874 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 875 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 876 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 877 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 878 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 879 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 880 resp.striding_rq_caps.supported_qpts = 881 BIT(IB_QPT_RAW_PACKET); 882 } 883 } 884 885 if (field_avail(typeof(resp), tunnel_offloads_caps, 886 uhw->outlen)) { 887 resp.response_length += sizeof(resp.tunnel_offloads_caps); 888 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 889 resp.tunnel_offloads_caps |= 890 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 891 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 892 resp.tunnel_offloads_caps |= 893 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 894 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 895 resp.tunnel_offloads_caps |= 896 MLX5_IB_TUNNELED_OFFLOADS_GRE; 897 } 898 899 if (uhw->outlen) { 900 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 901 902 if (err) 903 return err; 904 } 905 906 return 0; 907 } 908 909 enum mlx5_ib_width { 910 MLX5_IB_WIDTH_1X = 1 << 0, 911 MLX5_IB_WIDTH_2X = 1 << 1, 912 MLX5_IB_WIDTH_4X = 1 << 2, 913 MLX5_IB_WIDTH_8X = 1 << 3, 914 MLX5_IB_WIDTH_12X = 1 << 4 915 }; 916 917 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 918 u8 *ib_width) 919 { 920 struct mlx5_ib_dev *dev = to_mdev(ibdev); 921 int err = 0; 922 923 if (active_width & MLX5_IB_WIDTH_1X) { 924 *ib_width = IB_WIDTH_1X; 925 } else if (active_width & MLX5_IB_WIDTH_2X) { 926 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 927 (int)active_width); 928 err = -EINVAL; 929 } else if (active_width & MLX5_IB_WIDTH_4X) { 930 *ib_width = IB_WIDTH_4X; 931 } else if (active_width & MLX5_IB_WIDTH_8X) { 932 *ib_width = IB_WIDTH_8X; 933 } else if (active_width & MLX5_IB_WIDTH_12X) { 934 *ib_width = IB_WIDTH_12X; 935 } else { 936 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 937 (int)active_width); 938 err = -EINVAL; 939 } 940 941 return err; 942 } 943 944 static int mlx5_mtu_to_ib_mtu(int mtu) 945 { 946 switch (mtu) { 947 case 256: return 1; 948 case 512: return 2; 949 case 1024: return 3; 950 case 2048: return 4; 951 case 4096: return 5; 952 default: 953 pr_warn("invalid mtu\n"); 954 return -1; 955 } 956 } 957 958 enum ib_max_vl_num { 959 __IB_MAX_VL_0 = 1, 960 __IB_MAX_VL_0_1 = 2, 961 __IB_MAX_VL_0_3 = 3, 962 __IB_MAX_VL_0_7 = 4, 963 __IB_MAX_VL_0_14 = 5, 964 }; 965 966 enum mlx5_vl_hw_cap { 967 MLX5_VL_HW_0 = 1, 968 MLX5_VL_HW_0_1 = 2, 969 MLX5_VL_HW_0_2 = 3, 970 MLX5_VL_HW_0_3 = 4, 971 MLX5_VL_HW_0_4 = 5, 972 MLX5_VL_HW_0_5 = 6, 973 MLX5_VL_HW_0_6 = 7, 974 MLX5_VL_HW_0_7 = 8, 975 MLX5_VL_HW_0_14 = 15 976 }; 977 978 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 979 u8 *max_vl_num) 980 { 981 switch (vl_hw_cap) { 982 case MLX5_VL_HW_0: 983 *max_vl_num = __IB_MAX_VL_0; 984 break; 985 case MLX5_VL_HW_0_1: 986 *max_vl_num = __IB_MAX_VL_0_1; 987 break; 988 case MLX5_VL_HW_0_3: 989 *max_vl_num = __IB_MAX_VL_0_3; 990 break; 991 case MLX5_VL_HW_0_7: 992 *max_vl_num = __IB_MAX_VL_0_7; 993 break; 994 case MLX5_VL_HW_0_14: 995 *max_vl_num = __IB_MAX_VL_0_14; 996 break; 997 998 default: 999 return -EINVAL; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1006 struct ib_port_attr *props) 1007 { 1008 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1009 struct mlx5_core_dev *mdev = dev->mdev; 1010 struct mlx5_hca_vport_context *rep; 1011 u16 max_mtu; 1012 u16 oper_mtu; 1013 int err; 1014 u8 ib_link_width_oper; 1015 u8 vl_hw_cap; 1016 1017 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1018 if (!rep) { 1019 err = -ENOMEM; 1020 goto out; 1021 } 1022 1023 /* props being zeroed by the caller, avoid zeroing it here */ 1024 1025 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1026 if (err) 1027 goto out; 1028 1029 props->lid = rep->lid; 1030 props->lmc = rep->lmc; 1031 props->sm_lid = rep->sm_lid; 1032 props->sm_sl = rep->sm_sl; 1033 props->state = rep->vport_state; 1034 props->phys_state = rep->port_physical_state; 1035 props->port_cap_flags = rep->cap_mask1; 1036 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1037 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1038 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1039 props->bad_pkey_cntr = rep->pkey_violation_counter; 1040 props->qkey_viol_cntr = rep->qkey_violation_counter; 1041 props->subnet_timeout = rep->subnet_timeout; 1042 props->init_type_reply = rep->init_type_reply; 1043 props->grh_required = rep->grh_required; 1044 1045 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1046 if (err) 1047 goto out; 1048 1049 err = translate_active_width(ibdev, ib_link_width_oper, 1050 &props->active_width); 1051 if (err) 1052 goto out; 1053 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1054 if (err) 1055 goto out; 1056 1057 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1058 1059 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1060 1061 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1062 1063 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1064 1065 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1066 if (err) 1067 goto out; 1068 1069 err = translate_max_vl_num(ibdev, vl_hw_cap, 1070 &props->max_vl_num); 1071 out: 1072 kfree(rep); 1073 return err; 1074 } 1075 1076 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1077 struct ib_port_attr *props) 1078 { 1079 unsigned int count; 1080 int ret; 1081 1082 switch (mlx5_get_vport_access_method(ibdev)) { 1083 case MLX5_VPORT_ACCESS_METHOD_MAD: 1084 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1085 break; 1086 1087 case MLX5_VPORT_ACCESS_METHOD_HCA: 1088 ret = mlx5_query_hca_port(ibdev, port, props); 1089 break; 1090 1091 case MLX5_VPORT_ACCESS_METHOD_NIC: 1092 ret = mlx5_query_port_roce(ibdev, port, props); 1093 break; 1094 1095 default: 1096 ret = -EINVAL; 1097 } 1098 1099 if (!ret && props) { 1100 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 1101 props->gid_tbl_len -= count; 1102 } 1103 return ret; 1104 } 1105 1106 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1107 union ib_gid *gid) 1108 { 1109 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1110 struct mlx5_core_dev *mdev = dev->mdev; 1111 1112 switch (mlx5_get_vport_access_method(ibdev)) { 1113 case MLX5_VPORT_ACCESS_METHOD_MAD: 1114 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1115 1116 case MLX5_VPORT_ACCESS_METHOD_HCA: 1117 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1118 1119 default: 1120 return -EINVAL; 1121 } 1122 1123 } 1124 1125 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1126 u16 *pkey) 1127 { 1128 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1129 struct mlx5_core_dev *mdev = dev->mdev; 1130 1131 switch (mlx5_get_vport_access_method(ibdev)) { 1132 case MLX5_VPORT_ACCESS_METHOD_MAD: 1133 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1134 1135 case MLX5_VPORT_ACCESS_METHOD_HCA: 1136 case MLX5_VPORT_ACCESS_METHOD_NIC: 1137 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1138 pkey); 1139 default: 1140 return -EINVAL; 1141 } 1142 } 1143 1144 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1145 struct ib_device_modify *props) 1146 { 1147 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1148 struct mlx5_reg_node_desc in; 1149 struct mlx5_reg_node_desc out; 1150 int err; 1151 1152 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1153 return -EOPNOTSUPP; 1154 1155 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1156 return 0; 1157 1158 /* 1159 * If possible, pass node desc to FW, so it can generate 1160 * a 144 trap. If cmd fails, just ignore. 1161 */ 1162 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1163 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1164 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1165 if (err) 1166 return err; 1167 1168 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1169 1170 return err; 1171 } 1172 1173 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1174 u32 value) 1175 { 1176 struct mlx5_hca_vport_context ctx = {}; 1177 int err; 1178 1179 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1180 port_num, 0, &ctx); 1181 if (err) 1182 return err; 1183 1184 if (~ctx.cap_mask1_perm & mask) { 1185 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1186 mask, ctx.cap_mask1_perm); 1187 return -EINVAL; 1188 } 1189 1190 ctx.cap_mask1 = value; 1191 ctx.cap_mask1_perm = mask; 1192 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1193 port_num, 0, &ctx); 1194 1195 return err; 1196 } 1197 1198 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1199 struct ib_port_modify *props) 1200 { 1201 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1202 struct ib_port_attr attr; 1203 u32 tmp; 1204 int err; 1205 u32 change_mask; 1206 u32 value; 1207 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1208 IB_LINK_LAYER_INFINIBAND); 1209 1210 /* CM layer calls ib_modify_port() regardless of the link layer. For 1211 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1212 */ 1213 if (!is_ib) 1214 return 0; 1215 1216 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1217 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1218 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1219 return set_port_caps_atomic(dev, port, change_mask, value); 1220 } 1221 1222 mutex_lock(&dev->cap_mask_mutex); 1223 1224 err = ib_query_port(ibdev, port, &attr); 1225 if (err) 1226 goto out; 1227 1228 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1229 ~props->clr_port_cap_mask; 1230 1231 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1232 1233 out: 1234 mutex_unlock(&dev->cap_mask_mutex); 1235 return err; 1236 } 1237 1238 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1239 { 1240 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1241 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1242 } 1243 1244 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1245 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1246 u32 *num_sys_pages) 1247 { 1248 int uars_per_sys_page; 1249 int bfregs_per_sys_page; 1250 int ref_bfregs = req->total_num_bfregs; 1251 1252 if (req->total_num_bfregs == 0) 1253 return -EINVAL; 1254 1255 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1256 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1257 1258 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1259 return -ENOMEM; 1260 1261 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1262 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1263 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1264 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1265 1266 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1267 return -EINVAL; 1268 1269 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", 1270 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1271 lib_uar_4k ? "yes" : "no", ref_bfregs, 1272 req->total_num_bfregs, *num_sys_pages); 1273 1274 return 0; 1275 } 1276 1277 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1278 { 1279 struct mlx5_bfreg_info *bfregi; 1280 int err; 1281 int i; 1282 1283 bfregi = &context->bfregi; 1284 for (i = 0; i < bfregi->num_sys_pages; i++) { 1285 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1286 if (err) 1287 goto error; 1288 1289 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1290 } 1291 return 0; 1292 1293 error: 1294 for (--i; i >= 0; i--) 1295 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1296 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1297 1298 return err; 1299 } 1300 1301 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1302 { 1303 struct mlx5_bfreg_info *bfregi; 1304 int err; 1305 int i; 1306 1307 bfregi = &context->bfregi; 1308 for (i = 0; i < bfregi->num_sys_pages; i++) { 1309 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1310 if (err) { 1311 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1312 return err; 1313 } 1314 } 1315 return 0; 1316 } 1317 1318 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1319 { 1320 int err; 1321 1322 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1323 if (err) 1324 return err; 1325 1326 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1327 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1328 return err; 1329 1330 mutex_lock(&dev->lb_mutex); 1331 dev->user_td++; 1332 1333 if (dev->user_td == 2) 1334 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1335 1336 mutex_unlock(&dev->lb_mutex); 1337 return err; 1338 } 1339 1340 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1341 { 1342 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1343 1344 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1345 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1346 return; 1347 1348 mutex_lock(&dev->lb_mutex); 1349 dev->user_td--; 1350 1351 if (dev->user_td < 2) 1352 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1353 1354 mutex_unlock(&dev->lb_mutex); 1355 } 1356 1357 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1358 struct ib_udata *udata) 1359 { 1360 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1361 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1362 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1363 struct mlx5_ib_ucontext *context; 1364 struct mlx5_bfreg_info *bfregi; 1365 int ver; 1366 int err; 1367 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1368 max_cqe_version); 1369 bool lib_uar_4k; 1370 1371 if (!dev->ib_active) 1372 return ERR_PTR(-EAGAIN); 1373 1374 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1375 ver = 0; 1376 else if (udata->inlen >= min_req_v2) 1377 ver = 2; 1378 else 1379 return ERR_PTR(-EINVAL); 1380 1381 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1382 if (err) 1383 return ERR_PTR(err); 1384 1385 if (req.flags) 1386 return ERR_PTR(-EINVAL); 1387 1388 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1389 return ERR_PTR(-EOPNOTSUPP); 1390 1391 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1392 MLX5_NON_FP_BFREGS_PER_UAR); 1393 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1394 return ERR_PTR(-EINVAL); 1395 1396 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1397 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1398 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1399 resp.cache_line_size = cache_line_size(); 1400 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1401 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1402 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1403 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1404 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1405 resp.cqe_version = min_t(__u8, 1406 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1407 req.max_cqe_version); 1408 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1409 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1410 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1411 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1412 resp.response_length = min(offsetof(typeof(resp), response_length) + 1413 sizeof(resp.response_length), udata->outlen); 1414 1415 context = kzalloc(sizeof(*context), GFP_KERNEL); 1416 if (!context) 1417 return ERR_PTR(-ENOMEM); 1418 1419 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1420 bfregi = &context->bfregi; 1421 1422 /* updates req->total_num_bfregs */ 1423 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1424 if (err) 1425 goto out_ctx; 1426 1427 mutex_init(&bfregi->lock); 1428 bfregi->lib_uar_4k = lib_uar_4k; 1429 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1430 GFP_KERNEL); 1431 if (!bfregi->count) { 1432 err = -ENOMEM; 1433 goto out_ctx; 1434 } 1435 1436 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1437 sizeof(*bfregi->sys_pages), 1438 GFP_KERNEL); 1439 if (!bfregi->sys_pages) { 1440 err = -ENOMEM; 1441 goto out_count; 1442 } 1443 1444 err = allocate_uars(dev, context); 1445 if (err) 1446 goto out_sys_pages; 1447 1448 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1449 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1450 #endif 1451 1452 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1453 if (!context->upd_xlt_page) { 1454 err = -ENOMEM; 1455 goto out_uars; 1456 } 1457 mutex_init(&context->upd_xlt_page_mutex); 1458 1459 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1460 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1461 if (err) 1462 goto out_page; 1463 } 1464 1465 INIT_LIST_HEAD(&context->vma_private_list); 1466 mutex_init(&context->vma_private_list_mutex); 1467 INIT_LIST_HEAD(&context->db_page_list); 1468 mutex_init(&context->db_page_mutex); 1469 1470 resp.tot_bfregs = req.total_num_bfregs; 1471 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1472 1473 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1474 resp.response_length += sizeof(resp.cqe_version); 1475 1476 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1477 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1478 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1479 resp.response_length += sizeof(resp.cmds_supp_uhw); 1480 } 1481 1482 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1483 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1484 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1485 resp.eth_min_inline++; 1486 } 1487 resp.response_length += sizeof(resp.eth_min_inline); 1488 } 1489 1490 /* 1491 * We don't want to expose information from the PCI bar that is located 1492 * after 4096 bytes, so if the arch only supports larger pages, let's 1493 * pretend we don't support reading the HCA's core clock. This is also 1494 * forced by mmap function. 1495 */ 1496 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1497 if (PAGE_SIZE <= 4096) { 1498 resp.comp_mask |= 1499 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1500 resp.hca_core_clock_offset = 1501 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1502 } 1503 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1504 sizeof(resp.reserved2); 1505 } 1506 1507 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1508 resp.response_length += sizeof(resp.log_uar_size); 1509 1510 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1511 resp.response_length += sizeof(resp.num_uars_per_page); 1512 1513 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1514 if (err) 1515 goto out_td; 1516 1517 bfregi->ver = ver; 1518 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1519 context->cqe_version = resp.cqe_version; 1520 context->lib_caps = req.lib_caps; 1521 print_lib_caps(dev, context->lib_caps); 1522 1523 return &context->ibucontext; 1524 1525 out_td: 1526 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1527 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1528 1529 out_page: 1530 free_page(context->upd_xlt_page); 1531 1532 out_uars: 1533 deallocate_uars(dev, context); 1534 1535 out_sys_pages: 1536 kfree(bfregi->sys_pages); 1537 1538 out_count: 1539 kfree(bfregi->count); 1540 1541 out_ctx: 1542 kfree(context); 1543 1544 return ERR_PTR(err); 1545 } 1546 1547 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1548 { 1549 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1550 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1551 struct mlx5_bfreg_info *bfregi; 1552 1553 bfregi = &context->bfregi; 1554 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1555 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1556 1557 free_page(context->upd_xlt_page); 1558 deallocate_uars(dev, context); 1559 kfree(bfregi->sys_pages); 1560 kfree(bfregi->count); 1561 kfree(context); 1562 1563 return 0; 1564 } 1565 1566 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1567 struct mlx5_bfreg_info *bfregi, 1568 int idx) 1569 { 1570 int fw_uars_per_page; 1571 1572 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1573 1574 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1575 bfregi->sys_pages[idx] / fw_uars_per_page; 1576 } 1577 1578 static int get_command(unsigned long offset) 1579 { 1580 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1581 } 1582 1583 static int get_arg(unsigned long offset) 1584 { 1585 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1586 } 1587 1588 static int get_index(unsigned long offset) 1589 { 1590 return get_arg(offset); 1591 } 1592 1593 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1594 { 1595 /* vma_open is called when a new VMA is created on top of our VMA. This 1596 * is done through either mremap flow or split_vma (usually due to 1597 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1598 * as this VMA is strongly hardware related. Therefore we set the 1599 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1600 * calling us again and trying to do incorrect actions. We assume that 1601 * the original VMA size is exactly a single page, and therefore all 1602 * "splitting" operation will not happen to it. 1603 */ 1604 area->vm_ops = NULL; 1605 } 1606 1607 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1608 { 1609 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1610 1611 /* It's guaranteed that all VMAs opened on a FD are closed before the 1612 * file itself is closed, therefore no sync is needed with the regular 1613 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1614 * However need a sync with accessing the vma as part of 1615 * mlx5_ib_disassociate_ucontext. 1616 * The close operation is usually called under mm->mmap_sem except when 1617 * process is exiting. 1618 * The exiting case is handled explicitly as part of 1619 * mlx5_ib_disassociate_ucontext. 1620 */ 1621 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1622 1623 /* setting the vma context pointer to null in the mlx5_ib driver's 1624 * private data, to protect a race condition in 1625 * mlx5_ib_disassociate_ucontext(). 1626 */ 1627 mlx5_ib_vma_priv_data->vma = NULL; 1628 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1629 list_del(&mlx5_ib_vma_priv_data->list); 1630 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1631 kfree(mlx5_ib_vma_priv_data); 1632 } 1633 1634 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1635 .open = mlx5_ib_vma_open, 1636 .close = mlx5_ib_vma_close 1637 }; 1638 1639 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1640 struct mlx5_ib_ucontext *ctx) 1641 { 1642 struct mlx5_ib_vma_private_data *vma_prv; 1643 struct list_head *vma_head = &ctx->vma_private_list; 1644 1645 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1646 if (!vma_prv) 1647 return -ENOMEM; 1648 1649 vma_prv->vma = vma; 1650 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1651 vma->vm_private_data = vma_prv; 1652 vma->vm_ops = &mlx5_ib_vm_ops; 1653 1654 mutex_lock(&ctx->vma_private_list_mutex); 1655 list_add(&vma_prv->list, vma_head); 1656 mutex_unlock(&ctx->vma_private_list_mutex); 1657 1658 return 0; 1659 } 1660 1661 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1662 { 1663 int ret; 1664 struct vm_area_struct *vma; 1665 struct mlx5_ib_vma_private_data *vma_private, *n; 1666 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1667 struct task_struct *owning_process = NULL; 1668 struct mm_struct *owning_mm = NULL; 1669 1670 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1671 if (!owning_process) 1672 return; 1673 1674 owning_mm = get_task_mm(owning_process); 1675 if (!owning_mm) { 1676 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1677 while (1) { 1678 put_task_struct(owning_process); 1679 usleep_range(1000, 2000); 1680 owning_process = get_pid_task(ibcontext->tgid, 1681 PIDTYPE_PID); 1682 if (!owning_process || 1683 owning_process->state == TASK_DEAD) { 1684 pr_info("disassociate ucontext done, task was terminated\n"); 1685 /* in case task was dead need to release the 1686 * task struct. 1687 */ 1688 if (owning_process) 1689 put_task_struct(owning_process); 1690 return; 1691 } 1692 } 1693 } 1694 1695 /* need to protect from a race on closing the vma as part of 1696 * mlx5_ib_vma_close. 1697 */ 1698 down_write(&owning_mm->mmap_sem); 1699 mutex_lock(&context->vma_private_list_mutex); 1700 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1701 list) { 1702 vma = vma_private->vma; 1703 ret = zap_vma_ptes(vma, vma->vm_start, 1704 PAGE_SIZE); 1705 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1706 /* context going to be destroyed, should 1707 * not access ops any more. 1708 */ 1709 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1710 vma->vm_ops = NULL; 1711 list_del(&vma_private->list); 1712 kfree(vma_private); 1713 } 1714 mutex_unlock(&context->vma_private_list_mutex); 1715 up_write(&owning_mm->mmap_sem); 1716 mmput(owning_mm); 1717 put_task_struct(owning_process); 1718 } 1719 1720 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1721 { 1722 switch (cmd) { 1723 case MLX5_IB_MMAP_WC_PAGE: 1724 return "WC"; 1725 case MLX5_IB_MMAP_REGULAR_PAGE: 1726 return "best effort WC"; 1727 case MLX5_IB_MMAP_NC_PAGE: 1728 return "NC"; 1729 default: 1730 return NULL; 1731 } 1732 } 1733 1734 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1735 struct vm_area_struct *vma, 1736 struct mlx5_ib_ucontext *context) 1737 { 1738 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1739 int err; 1740 unsigned long idx; 1741 phys_addr_t pfn, pa; 1742 pgprot_t prot; 1743 int uars_per_page; 1744 1745 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1746 return -EINVAL; 1747 1748 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1749 idx = get_index(vma->vm_pgoff); 1750 if (idx % uars_per_page || 1751 idx * uars_per_page >= bfregi->num_sys_pages) { 1752 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1753 return -EINVAL; 1754 } 1755 1756 switch (cmd) { 1757 case MLX5_IB_MMAP_WC_PAGE: 1758 /* Some architectures don't support WC memory */ 1759 #if defined(CONFIG_X86) 1760 if (!pat_enabled()) 1761 return -EPERM; 1762 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1763 return -EPERM; 1764 #endif 1765 /* fall through */ 1766 case MLX5_IB_MMAP_REGULAR_PAGE: 1767 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1768 prot = pgprot_writecombine(vma->vm_page_prot); 1769 break; 1770 case MLX5_IB_MMAP_NC_PAGE: 1771 prot = pgprot_noncached(vma->vm_page_prot); 1772 break; 1773 default: 1774 return -EINVAL; 1775 } 1776 1777 pfn = uar_index2pfn(dev, bfregi, idx); 1778 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1779 1780 vma->vm_page_prot = prot; 1781 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1782 PAGE_SIZE, vma->vm_page_prot); 1783 if (err) { 1784 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1785 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1786 return -EAGAIN; 1787 } 1788 1789 pa = pfn << PAGE_SHIFT; 1790 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1791 vma->vm_start, &pa); 1792 1793 return mlx5_ib_set_vma_data(vma, context); 1794 } 1795 1796 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1797 { 1798 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1799 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1800 unsigned long command; 1801 phys_addr_t pfn; 1802 1803 command = get_command(vma->vm_pgoff); 1804 switch (command) { 1805 case MLX5_IB_MMAP_WC_PAGE: 1806 case MLX5_IB_MMAP_NC_PAGE: 1807 case MLX5_IB_MMAP_REGULAR_PAGE: 1808 return uar_mmap(dev, command, vma, context); 1809 1810 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1811 return -ENOSYS; 1812 1813 case MLX5_IB_MMAP_CORE_CLOCK: 1814 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1815 return -EINVAL; 1816 1817 if (vma->vm_flags & VM_WRITE) 1818 return -EPERM; 1819 1820 /* Don't expose to user-space information it shouldn't have */ 1821 if (PAGE_SIZE > 4096) 1822 return -EOPNOTSUPP; 1823 1824 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1825 pfn = (dev->mdev->iseg_base + 1826 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1827 PAGE_SHIFT; 1828 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1829 PAGE_SIZE, vma->vm_page_prot)) 1830 return -EAGAIN; 1831 1832 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1833 vma->vm_start, 1834 (unsigned long long)pfn << PAGE_SHIFT); 1835 break; 1836 1837 default: 1838 return -EINVAL; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1845 struct ib_ucontext *context, 1846 struct ib_udata *udata) 1847 { 1848 struct mlx5_ib_alloc_pd_resp resp; 1849 struct mlx5_ib_pd *pd; 1850 int err; 1851 1852 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1853 if (!pd) 1854 return ERR_PTR(-ENOMEM); 1855 1856 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1857 if (err) { 1858 kfree(pd); 1859 return ERR_PTR(err); 1860 } 1861 1862 if (context) { 1863 resp.pdn = pd->pdn; 1864 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1865 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1866 kfree(pd); 1867 return ERR_PTR(-EFAULT); 1868 } 1869 } 1870 1871 return &pd->ibpd; 1872 } 1873 1874 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1875 { 1876 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1877 struct mlx5_ib_pd *mpd = to_mpd(pd); 1878 1879 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1880 kfree(mpd); 1881 1882 return 0; 1883 } 1884 1885 enum { 1886 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1887 MATCH_CRITERIA_ENABLE_MISC_BIT, 1888 MATCH_CRITERIA_ENABLE_INNER_BIT 1889 }; 1890 1891 #define HEADER_IS_ZERO(match_criteria, headers) \ 1892 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1893 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1894 1895 static u8 get_match_criteria_enable(u32 *match_criteria) 1896 { 1897 u8 match_criteria_enable; 1898 1899 match_criteria_enable = 1900 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1901 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1902 match_criteria_enable |= 1903 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1904 MATCH_CRITERIA_ENABLE_MISC_BIT; 1905 match_criteria_enable |= 1906 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1907 MATCH_CRITERIA_ENABLE_INNER_BIT; 1908 1909 return match_criteria_enable; 1910 } 1911 1912 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1913 { 1914 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1915 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1916 } 1917 1918 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1919 bool inner) 1920 { 1921 if (inner) { 1922 MLX5_SET(fte_match_set_misc, 1923 misc_c, inner_ipv6_flow_label, mask); 1924 MLX5_SET(fte_match_set_misc, 1925 misc_v, inner_ipv6_flow_label, val); 1926 } else { 1927 MLX5_SET(fte_match_set_misc, 1928 misc_c, outer_ipv6_flow_label, mask); 1929 MLX5_SET(fte_match_set_misc, 1930 misc_v, outer_ipv6_flow_label, val); 1931 } 1932 } 1933 1934 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1935 { 1936 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1937 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1938 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1939 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1940 } 1941 1942 #define LAST_ETH_FIELD vlan_tag 1943 #define LAST_IB_FIELD sl 1944 #define LAST_IPV4_FIELD tos 1945 #define LAST_IPV6_FIELD traffic_class 1946 #define LAST_TCP_UDP_FIELD src_port 1947 #define LAST_TUNNEL_FIELD tunnel_id 1948 #define LAST_FLOW_TAG_FIELD tag_id 1949 #define LAST_DROP_FIELD size 1950 1951 /* Field is the last supported field */ 1952 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1953 memchr_inv((void *)&filter.field +\ 1954 sizeof(filter.field), 0,\ 1955 sizeof(filter) -\ 1956 offsetof(typeof(filter), field) -\ 1957 sizeof(filter.field)) 1958 1959 #define IPV4_VERSION 4 1960 #define IPV6_VERSION 6 1961 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1962 u32 *match_v, const union ib_flow_spec *ib_spec, 1963 u32 *tag_id, bool *is_drop) 1964 { 1965 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1966 misc_parameters); 1967 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1968 misc_parameters); 1969 void *headers_c; 1970 void *headers_v; 1971 int match_ipv; 1972 1973 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1974 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1975 inner_headers); 1976 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1977 inner_headers); 1978 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1979 ft_field_support.inner_ip_version); 1980 } else { 1981 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1982 outer_headers); 1983 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1984 outer_headers); 1985 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1986 ft_field_support.outer_ip_version); 1987 } 1988 1989 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1990 case IB_FLOW_SPEC_ETH: 1991 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1992 return -EOPNOTSUPP; 1993 1994 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1995 dmac_47_16), 1996 ib_spec->eth.mask.dst_mac); 1997 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1998 dmac_47_16), 1999 ib_spec->eth.val.dst_mac); 2000 2001 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2002 smac_47_16), 2003 ib_spec->eth.mask.src_mac); 2004 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2005 smac_47_16), 2006 ib_spec->eth.val.src_mac); 2007 2008 if (ib_spec->eth.mask.vlan_tag) { 2009 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2010 cvlan_tag, 1); 2011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2012 cvlan_tag, 1); 2013 2014 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2015 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2016 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2017 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2018 2019 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2020 first_cfi, 2021 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2022 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2023 first_cfi, 2024 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2025 2026 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2027 first_prio, 2028 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2029 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2030 first_prio, 2031 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2032 } 2033 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2034 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2035 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2036 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2037 break; 2038 case IB_FLOW_SPEC_IPV4: 2039 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2040 return -EOPNOTSUPP; 2041 2042 if (match_ipv) { 2043 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2044 ip_version, 0xf); 2045 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2046 ip_version, IPV4_VERSION); 2047 } else { 2048 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2049 ethertype, 0xffff); 2050 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2051 ethertype, ETH_P_IP); 2052 } 2053 2054 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2055 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2056 &ib_spec->ipv4.mask.src_ip, 2057 sizeof(ib_spec->ipv4.mask.src_ip)); 2058 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2059 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2060 &ib_spec->ipv4.val.src_ip, 2061 sizeof(ib_spec->ipv4.val.src_ip)); 2062 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2063 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2064 &ib_spec->ipv4.mask.dst_ip, 2065 sizeof(ib_spec->ipv4.mask.dst_ip)); 2066 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2067 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2068 &ib_spec->ipv4.val.dst_ip, 2069 sizeof(ib_spec->ipv4.val.dst_ip)); 2070 2071 set_tos(headers_c, headers_v, 2072 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2073 2074 set_proto(headers_c, headers_v, 2075 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2076 break; 2077 case IB_FLOW_SPEC_IPV6: 2078 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2079 return -EOPNOTSUPP; 2080 2081 if (match_ipv) { 2082 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2083 ip_version, 0xf); 2084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2085 ip_version, IPV6_VERSION); 2086 } else { 2087 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2088 ethertype, 0xffff); 2089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2090 ethertype, ETH_P_IPV6); 2091 } 2092 2093 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2094 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2095 &ib_spec->ipv6.mask.src_ip, 2096 sizeof(ib_spec->ipv6.mask.src_ip)); 2097 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2098 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2099 &ib_spec->ipv6.val.src_ip, 2100 sizeof(ib_spec->ipv6.val.src_ip)); 2101 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2102 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2103 &ib_spec->ipv6.mask.dst_ip, 2104 sizeof(ib_spec->ipv6.mask.dst_ip)); 2105 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2106 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2107 &ib_spec->ipv6.val.dst_ip, 2108 sizeof(ib_spec->ipv6.val.dst_ip)); 2109 2110 set_tos(headers_c, headers_v, 2111 ib_spec->ipv6.mask.traffic_class, 2112 ib_spec->ipv6.val.traffic_class); 2113 2114 set_proto(headers_c, headers_v, 2115 ib_spec->ipv6.mask.next_hdr, 2116 ib_spec->ipv6.val.next_hdr); 2117 2118 set_flow_label(misc_params_c, misc_params_v, 2119 ntohl(ib_spec->ipv6.mask.flow_label), 2120 ntohl(ib_spec->ipv6.val.flow_label), 2121 ib_spec->type & IB_FLOW_SPEC_INNER); 2122 2123 break; 2124 case IB_FLOW_SPEC_TCP: 2125 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2126 LAST_TCP_UDP_FIELD)) 2127 return -EOPNOTSUPP; 2128 2129 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2130 0xff); 2131 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2132 IPPROTO_TCP); 2133 2134 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2135 ntohs(ib_spec->tcp_udp.mask.src_port)); 2136 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2137 ntohs(ib_spec->tcp_udp.val.src_port)); 2138 2139 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2140 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2141 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2142 ntohs(ib_spec->tcp_udp.val.dst_port)); 2143 break; 2144 case IB_FLOW_SPEC_UDP: 2145 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2146 LAST_TCP_UDP_FIELD)) 2147 return -EOPNOTSUPP; 2148 2149 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2150 0xff); 2151 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2152 IPPROTO_UDP); 2153 2154 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2155 ntohs(ib_spec->tcp_udp.mask.src_port)); 2156 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2157 ntohs(ib_spec->tcp_udp.val.src_port)); 2158 2159 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2160 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2161 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2162 ntohs(ib_spec->tcp_udp.val.dst_port)); 2163 break; 2164 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2165 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2166 LAST_TUNNEL_FIELD)) 2167 return -EOPNOTSUPP; 2168 2169 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2170 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2171 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2172 ntohl(ib_spec->tunnel.val.tunnel_id)); 2173 break; 2174 case IB_FLOW_SPEC_ACTION_TAG: 2175 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2176 LAST_FLOW_TAG_FIELD)) 2177 return -EOPNOTSUPP; 2178 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2179 return -EINVAL; 2180 2181 *tag_id = ib_spec->flow_tag.tag_id; 2182 break; 2183 case IB_FLOW_SPEC_ACTION_DROP: 2184 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2185 LAST_DROP_FIELD)) 2186 return -EOPNOTSUPP; 2187 *is_drop = true; 2188 break; 2189 default: 2190 return -EINVAL; 2191 } 2192 2193 return 0; 2194 } 2195 2196 /* If a flow could catch both multicast and unicast packets, 2197 * it won't fall into the multicast flow steering table and this rule 2198 * could steal other multicast packets. 2199 */ 2200 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2201 { 2202 union ib_flow_spec *flow_spec; 2203 2204 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2205 ib_attr->num_of_specs < 1) 2206 return false; 2207 2208 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2209 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2210 struct ib_flow_spec_ipv4 *ipv4_spec; 2211 2212 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2213 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2214 return true; 2215 2216 return false; 2217 } 2218 2219 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2220 struct ib_flow_spec_eth *eth_spec; 2221 2222 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2223 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2224 is_multicast_ether_addr(eth_spec->val.dst_mac); 2225 } 2226 2227 return false; 2228 } 2229 2230 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2231 const struct ib_flow_attr *flow_attr, 2232 bool check_inner) 2233 { 2234 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2235 int match_ipv = check_inner ? 2236 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2237 ft_field_support.inner_ip_version) : 2238 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2239 ft_field_support.outer_ip_version); 2240 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2241 bool ipv4_spec_valid, ipv6_spec_valid; 2242 unsigned int ip_spec_type = 0; 2243 bool has_ethertype = false; 2244 unsigned int spec_index; 2245 bool mask_valid = true; 2246 u16 eth_type = 0; 2247 bool type_valid; 2248 2249 /* Validate that ethertype is correct */ 2250 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2251 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2252 ib_spec->eth.mask.ether_type) { 2253 mask_valid = (ib_spec->eth.mask.ether_type == 2254 htons(0xffff)); 2255 has_ethertype = true; 2256 eth_type = ntohs(ib_spec->eth.val.ether_type); 2257 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2258 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2259 ip_spec_type = ib_spec->type; 2260 } 2261 ib_spec = (void *)ib_spec + ib_spec->size; 2262 } 2263 2264 type_valid = (!has_ethertype) || (!ip_spec_type); 2265 if (!type_valid && mask_valid) { 2266 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2267 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2268 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2269 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2270 2271 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2272 (((eth_type == ETH_P_MPLS_UC) || 2273 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2274 } 2275 2276 return type_valid; 2277 } 2278 2279 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2280 const struct ib_flow_attr *flow_attr) 2281 { 2282 return is_valid_ethertype(mdev, flow_attr, false) && 2283 is_valid_ethertype(mdev, flow_attr, true); 2284 } 2285 2286 static void put_flow_table(struct mlx5_ib_dev *dev, 2287 struct mlx5_ib_flow_prio *prio, bool ft_added) 2288 { 2289 prio->refcount -= !!ft_added; 2290 if (!prio->refcount) { 2291 mlx5_destroy_flow_table(prio->flow_table); 2292 prio->flow_table = NULL; 2293 } 2294 } 2295 2296 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2297 { 2298 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2299 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2300 struct mlx5_ib_flow_handler, 2301 ibflow); 2302 struct mlx5_ib_flow_handler *iter, *tmp; 2303 2304 mutex_lock(&dev->flow_db.lock); 2305 2306 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2307 mlx5_del_flow_rules(iter->rule); 2308 put_flow_table(dev, iter->prio, true); 2309 list_del(&iter->list); 2310 kfree(iter); 2311 } 2312 2313 mlx5_del_flow_rules(handler->rule); 2314 put_flow_table(dev, handler->prio, true); 2315 mutex_unlock(&dev->flow_db.lock); 2316 2317 kfree(handler); 2318 2319 return 0; 2320 } 2321 2322 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2323 { 2324 priority *= 2; 2325 if (!dont_trap) 2326 priority++; 2327 return priority; 2328 } 2329 2330 enum flow_table_type { 2331 MLX5_IB_FT_RX, 2332 MLX5_IB_FT_TX 2333 }; 2334 2335 #define MLX5_FS_MAX_TYPES 6 2336 #define MLX5_FS_MAX_ENTRIES BIT(16) 2337 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2338 struct ib_flow_attr *flow_attr, 2339 enum flow_table_type ft_type) 2340 { 2341 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2342 struct mlx5_flow_namespace *ns = NULL; 2343 struct mlx5_ib_flow_prio *prio; 2344 struct mlx5_flow_table *ft; 2345 int max_table_size; 2346 int num_entries; 2347 int num_groups; 2348 int priority; 2349 int err = 0; 2350 2351 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2352 log_max_ft_size)); 2353 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2354 if (flow_is_multicast_only(flow_attr) && 2355 !dont_trap) 2356 priority = MLX5_IB_FLOW_MCAST_PRIO; 2357 else 2358 priority = ib_prio_to_core_prio(flow_attr->priority, 2359 dont_trap); 2360 ns = mlx5_get_flow_namespace(dev->mdev, 2361 MLX5_FLOW_NAMESPACE_BYPASS); 2362 num_entries = MLX5_FS_MAX_ENTRIES; 2363 num_groups = MLX5_FS_MAX_TYPES; 2364 prio = &dev->flow_db.prios[priority]; 2365 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2366 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2367 ns = mlx5_get_flow_namespace(dev->mdev, 2368 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2369 build_leftovers_ft_param(&priority, 2370 &num_entries, 2371 &num_groups); 2372 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2373 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2374 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2375 allow_sniffer_and_nic_rx_shared_tir)) 2376 return ERR_PTR(-ENOTSUPP); 2377 2378 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2379 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2380 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2381 2382 prio = &dev->flow_db.sniffer[ft_type]; 2383 priority = 0; 2384 num_entries = 1; 2385 num_groups = 1; 2386 } 2387 2388 if (!ns) 2389 return ERR_PTR(-ENOTSUPP); 2390 2391 if (num_entries > max_table_size) 2392 return ERR_PTR(-ENOMEM); 2393 2394 ft = prio->flow_table; 2395 if (!ft) { 2396 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2397 num_entries, 2398 num_groups, 2399 0, 0); 2400 2401 if (!IS_ERR(ft)) { 2402 prio->refcount = 0; 2403 prio->flow_table = ft; 2404 } else { 2405 err = PTR_ERR(ft); 2406 } 2407 } 2408 2409 return err ? ERR_PTR(err) : prio; 2410 } 2411 2412 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2413 struct mlx5_flow_spec *spec, 2414 u32 underlay_qpn) 2415 { 2416 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2417 spec->match_criteria, 2418 misc_parameters); 2419 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2420 misc_parameters); 2421 2422 if (underlay_qpn && 2423 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2424 ft_field_support.bth_dst_qp)) { 2425 MLX5_SET(fte_match_set_misc, 2426 misc_params_v, bth_dst_qp, underlay_qpn); 2427 MLX5_SET(fte_match_set_misc, 2428 misc_params_c, bth_dst_qp, 0xffffff); 2429 } 2430 } 2431 2432 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2433 struct mlx5_ib_flow_prio *ft_prio, 2434 const struct ib_flow_attr *flow_attr, 2435 struct mlx5_flow_destination *dst, 2436 u32 underlay_qpn) 2437 { 2438 struct mlx5_flow_table *ft = ft_prio->flow_table; 2439 struct mlx5_ib_flow_handler *handler; 2440 struct mlx5_flow_act flow_act = {0}; 2441 struct mlx5_flow_spec *spec; 2442 struct mlx5_flow_destination *rule_dst = dst; 2443 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2444 unsigned int spec_index; 2445 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2446 bool is_drop = false; 2447 int err = 0; 2448 int dest_num = 1; 2449 2450 if (!is_valid_attr(dev->mdev, flow_attr)) 2451 return ERR_PTR(-EINVAL); 2452 2453 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2454 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2455 if (!handler || !spec) { 2456 err = -ENOMEM; 2457 goto free; 2458 } 2459 2460 INIT_LIST_HEAD(&handler->list); 2461 2462 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2463 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2464 spec->match_value, 2465 ib_flow, &flow_tag, &is_drop); 2466 if (err < 0) 2467 goto free; 2468 2469 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2470 } 2471 2472 if (!flow_is_multicast_only(flow_attr)) 2473 set_underlay_qp(dev, spec, underlay_qpn); 2474 2475 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2476 if (is_drop) { 2477 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2478 rule_dst = NULL; 2479 dest_num = 0; 2480 } else { 2481 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2482 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2483 } 2484 2485 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2486 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2487 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2488 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2489 flow_tag, flow_attr->type); 2490 err = -EINVAL; 2491 goto free; 2492 } 2493 flow_act.flow_tag = flow_tag; 2494 handler->rule = mlx5_add_flow_rules(ft, spec, 2495 &flow_act, 2496 rule_dst, dest_num); 2497 2498 if (IS_ERR(handler->rule)) { 2499 err = PTR_ERR(handler->rule); 2500 goto free; 2501 } 2502 2503 ft_prio->refcount++; 2504 handler->prio = ft_prio; 2505 2506 ft_prio->flow_table = ft; 2507 free: 2508 if (err) 2509 kfree(handler); 2510 kvfree(spec); 2511 return err ? ERR_PTR(err) : handler; 2512 } 2513 2514 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2515 struct mlx5_ib_flow_prio *ft_prio, 2516 const struct ib_flow_attr *flow_attr, 2517 struct mlx5_flow_destination *dst) 2518 { 2519 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2520 } 2521 2522 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2523 struct mlx5_ib_flow_prio *ft_prio, 2524 struct ib_flow_attr *flow_attr, 2525 struct mlx5_flow_destination *dst) 2526 { 2527 struct mlx5_ib_flow_handler *handler_dst = NULL; 2528 struct mlx5_ib_flow_handler *handler = NULL; 2529 2530 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2531 if (!IS_ERR(handler)) { 2532 handler_dst = create_flow_rule(dev, ft_prio, 2533 flow_attr, dst); 2534 if (IS_ERR(handler_dst)) { 2535 mlx5_del_flow_rules(handler->rule); 2536 ft_prio->refcount--; 2537 kfree(handler); 2538 handler = handler_dst; 2539 } else { 2540 list_add(&handler_dst->list, &handler->list); 2541 } 2542 } 2543 2544 return handler; 2545 } 2546 enum { 2547 LEFTOVERS_MC, 2548 LEFTOVERS_UC, 2549 }; 2550 2551 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2552 struct mlx5_ib_flow_prio *ft_prio, 2553 struct ib_flow_attr *flow_attr, 2554 struct mlx5_flow_destination *dst) 2555 { 2556 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2557 struct mlx5_ib_flow_handler *handler = NULL; 2558 2559 static struct { 2560 struct ib_flow_attr flow_attr; 2561 struct ib_flow_spec_eth eth_flow; 2562 } leftovers_specs[] = { 2563 [LEFTOVERS_MC] = { 2564 .flow_attr = { 2565 .num_of_specs = 1, 2566 .size = sizeof(leftovers_specs[0]) 2567 }, 2568 .eth_flow = { 2569 .type = IB_FLOW_SPEC_ETH, 2570 .size = sizeof(struct ib_flow_spec_eth), 2571 .mask = {.dst_mac = {0x1} }, 2572 .val = {.dst_mac = {0x1} } 2573 } 2574 }, 2575 [LEFTOVERS_UC] = { 2576 .flow_attr = { 2577 .num_of_specs = 1, 2578 .size = sizeof(leftovers_specs[0]) 2579 }, 2580 .eth_flow = { 2581 .type = IB_FLOW_SPEC_ETH, 2582 .size = sizeof(struct ib_flow_spec_eth), 2583 .mask = {.dst_mac = {0x1} }, 2584 .val = {.dst_mac = {} } 2585 } 2586 } 2587 }; 2588 2589 handler = create_flow_rule(dev, ft_prio, 2590 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2591 dst); 2592 if (!IS_ERR(handler) && 2593 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2594 handler_ucast = create_flow_rule(dev, ft_prio, 2595 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2596 dst); 2597 if (IS_ERR(handler_ucast)) { 2598 mlx5_del_flow_rules(handler->rule); 2599 ft_prio->refcount--; 2600 kfree(handler); 2601 handler = handler_ucast; 2602 } else { 2603 list_add(&handler_ucast->list, &handler->list); 2604 } 2605 } 2606 2607 return handler; 2608 } 2609 2610 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2611 struct mlx5_ib_flow_prio *ft_rx, 2612 struct mlx5_ib_flow_prio *ft_tx, 2613 struct mlx5_flow_destination *dst) 2614 { 2615 struct mlx5_ib_flow_handler *handler_rx; 2616 struct mlx5_ib_flow_handler *handler_tx; 2617 int err; 2618 static const struct ib_flow_attr flow_attr = { 2619 .num_of_specs = 0, 2620 .size = sizeof(flow_attr) 2621 }; 2622 2623 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2624 if (IS_ERR(handler_rx)) { 2625 err = PTR_ERR(handler_rx); 2626 goto err; 2627 } 2628 2629 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2630 if (IS_ERR(handler_tx)) { 2631 err = PTR_ERR(handler_tx); 2632 goto err_tx; 2633 } 2634 2635 list_add(&handler_tx->list, &handler_rx->list); 2636 2637 return handler_rx; 2638 2639 err_tx: 2640 mlx5_del_flow_rules(handler_rx->rule); 2641 ft_rx->refcount--; 2642 kfree(handler_rx); 2643 err: 2644 return ERR_PTR(err); 2645 } 2646 2647 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2648 struct ib_flow_attr *flow_attr, 2649 int domain) 2650 { 2651 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2652 struct mlx5_ib_qp *mqp = to_mqp(qp); 2653 struct mlx5_ib_flow_handler *handler = NULL; 2654 struct mlx5_flow_destination *dst = NULL; 2655 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2656 struct mlx5_ib_flow_prio *ft_prio; 2657 int err; 2658 int underlay_qpn; 2659 2660 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2661 return ERR_PTR(-ENOMEM); 2662 2663 if (domain != IB_FLOW_DOMAIN_USER || 2664 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2665 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2666 return ERR_PTR(-EINVAL); 2667 2668 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2669 if (!dst) 2670 return ERR_PTR(-ENOMEM); 2671 2672 mutex_lock(&dev->flow_db.lock); 2673 2674 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2675 if (IS_ERR(ft_prio)) { 2676 err = PTR_ERR(ft_prio); 2677 goto unlock; 2678 } 2679 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2680 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2681 if (IS_ERR(ft_prio_tx)) { 2682 err = PTR_ERR(ft_prio_tx); 2683 ft_prio_tx = NULL; 2684 goto destroy_ft; 2685 } 2686 } 2687 2688 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2689 if (mqp->flags & MLX5_IB_QP_RSS) 2690 dst->tir_num = mqp->rss_qp.tirn; 2691 else 2692 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2693 2694 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2695 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2696 handler = create_dont_trap_rule(dev, ft_prio, 2697 flow_attr, dst); 2698 } else { 2699 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 2700 mqp->underlay_qpn : 0; 2701 handler = _create_flow_rule(dev, ft_prio, flow_attr, 2702 dst, underlay_qpn); 2703 } 2704 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2705 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2706 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2707 dst); 2708 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2709 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2710 } else { 2711 err = -EINVAL; 2712 goto destroy_ft; 2713 } 2714 2715 if (IS_ERR(handler)) { 2716 err = PTR_ERR(handler); 2717 handler = NULL; 2718 goto destroy_ft; 2719 } 2720 2721 mutex_unlock(&dev->flow_db.lock); 2722 kfree(dst); 2723 2724 return &handler->ibflow; 2725 2726 destroy_ft: 2727 put_flow_table(dev, ft_prio, false); 2728 if (ft_prio_tx) 2729 put_flow_table(dev, ft_prio_tx, false); 2730 unlock: 2731 mutex_unlock(&dev->flow_db.lock); 2732 kfree(dst); 2733 kfree(handler); 2734 return ERR_PTR(err); 2735 } 2736 2737 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2738 { 2739 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2740 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2741 int err; 2742 2743 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 2744 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2745 return -EOPNOTSUPP; 2746 } 2747 2748 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2749 if (err) 2750 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2751 ibqp->qp_num, gid->raw); 2752 2753 return err; 2754 } 2755 2756 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2757 { 2758 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2759 int err; 2760 2761 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2762 if (err) 2763 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2764 ibqp->qp_num, gid->raw); 2765 2766 return err; 2767 } 2768 2769 static int init_node_data(struct mlx5_ib_dev *dev) 2770 { 2771 int err; 2772 2773 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2774 if (err) 2775 return err; 2776 2777 dev->mdev->rev_id = dev->mdev->pdev->revision; 2778 2779 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2780 } 2781 2782 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2783 char *buf) 2784 { 2785 struct mlx5_ib_dev *dev = 2786 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2787 2788 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2789 } 2790 2791 static ssize_t show_reg_pages(struct device *device, 2792 struct device_attribute *attr, char *buf) 2793 { 2794 struct mlx5_ib_dev *dev = 2795 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2796 2797 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2798 } 2799 2800 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2801 char *buf) 2802 { 2803 struct mlx5_ib_dev *dev = 2804 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2805 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2806 } 2807 2808 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2809 char *buf) 2810 { 2811 struct mlx5_ib_dev *dev = 2812 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2813 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2814 } 2815 2816 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2817 char *buf) 2818 { 2819 struct mlx5_ib_dev *dev = 2820 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2821 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2822 dev->mdev->board_id); 2823 } 2824 2825 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2826 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2827 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2828 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2829 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2830 2831 static struct device_attribute *mlx5_class_attributes[] = { 2832 &dev_attr_hw_rev, 2833 &dev_attr_hca_type, 2834 &dev_attr_board_id, 2835 &dev_attr_fw_pages, 2836 &dev_attr_reg_pages, 2837 }; 2838 2839 static void pkey_change_handler(struct work_struct *work) 2840 { 2841 struct mlx5_ib_port_resources *ports = 2842 container_of(work, struct mlx5_ib_port_resources, 2843 pkey_change_work); 2844 2845 mutex_lock(&ports->devr->mutex); 2846 mlx5_ib_gsi_pkey_change(ports->gsi); 2847 mutex_unlock(&ports->devr->mutex); 2848 } 2849 2850 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2851 { 2852 struct mlx5_ib_qp *mqp; 2853 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2854 struct mlx5_core_cq *mcq; 2855 struct list_head cq_armed_list; 2856 unsigned long flags_qp; 2857 unsigned long flags_cq; 2858 unsigned long flags; 2859 2860 INIT_LIST_HEAD(&cq_armed_list); 2861 2862 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2863 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2864 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2865 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2866 if (mqp->sq.tail != mqp->sq.head) { 2867 send_mcq = to_mcq(mqp->ibqp.send_cq); 2868 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2869 if (send_mcq->mcq.comp && 2870 mqp->ibqp.send_cq->comp_handler) { 2871 if (!send_mcq->mcq.reset_notify_added) { 2872 send_mcq->mcq.reset_notify_added = 1; 2873 list_add_tail(&send_mcq->mcq.reset_notify, 2874 &cq_armed_list); 2875 } 2876 } 2877 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2878 } 2879 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2880 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2881 /* no handling is needed for SRQ */ 2882 if (!mqp->ibqp.srq) { 2883 if (mqp->rq.tail != mqp->rq.head) { 2884 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2885 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2886 if (recv_mcq->mcq.comp && 2887 mqp->ibqp.recv_cq->comp_handler) { 2888 if (!recv_mcq->mcq.reset_notify_added) { 2889 recv_mcq->mcq.reset_notify_added = 1; 2890 list_add_tail(&recv_mcq->mcq.reset_notify, 2891 &cq_armed_list); 2892 } 2893 } 2894 spin_unlock_irqrestore(&recv_mcq->lock, 2895 flags_cq); 2896 } 2897 } 2898 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2899 } 2900 /*At that point all inflight post send were put to be executed as of we 2901 * lock/unlock above locks Now need to arm all involved CQs. 2902 */ 2903 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2904 mcq->comp(mcq); 2905 } 2906 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2907 } 2908 2909 static void delay_drop_handler(struct work_struct *work) 2910 { 2911 int err; 2912 struct mlx5_ib_delay_drop *delay_drop = 2913 container_of(work, struct mlx5_ib_delay_drop, 2914 delay_drop_work); 2915 2916 atomic_inc(&delay_drop->events_cnt); 2917 2918 mutex_lock(&delay_drop->lock); 2919 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 2920 delay_drop->timeout); 2921 if (err) { 2922 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2923 delay_drop->timeout); 2924 delay_drop->activate = false; 2925 } 2926 mutex_unlock(&delay_drop->lock); 2927 } 2928 2929 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2930 enum mlx5_dev_event event, unsigned long param) 2931 { 2932 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2933 struct ib_event ibev; 2934 bool fatal = false; 2935 u8 port = 0; 2936 2937 switch (event) { 2938 case MLX5_DEV_EVENT_SYS_ERROR: 2939 ibev.event = IB_EVENT_DEVICE_FATAL; 2940 mlx5_ib_handle_internal_error(ibdev); 2941 fatal = true; 2942 break; 2943 2944 case MLX5_DEV_EVENT_PORT_UP: 2945 case MLX5_DEV_EVENT_PORT_DOWN: 2946 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2947 port = (u8)param; 2948 2949 /* In RoCE, port up/down events are handled in 2950 * mlx5_netdev_event(). 2951 */ 2952 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2953 IB_LINK_LAYER_ETHERNET) 2954 return; 2955 2956 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2957 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2958 break; 2959 2960 case MLX5_DEV_EVENT_LID_CHANGE: 2961 ibev.event = IB_EVENT_LID_CHANGE; 2962 port = (u8)param; 2963 break; 2964 2965 case MLX5_DEV_EVENT_PKEY_CHANGE: 2966 ibev.event = IB_EVENT_PKEY_CHANGE; 2967 port = (u8)param; 2968 2969 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2970 break; 2971 2972 case MLX5_DEV_EVENT_GUID_CHANGE: 2973 ibev.event = IB_EVENT_GID_CHANGE; 2974 port = (u8)param; 2975 break; 2976 2977 case MLX5_DEV_EVENT_CLIENT_REREG: 2978 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2979 port = (u8)param; 2980 break; 2981 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 2982 schedule_work(&ibdev->delay_drop.delay_drop_work); 2983 goto out; 2984 default: 2985 goto out; 2986 } 2987 2988 ibev.device = &ibdev->ib_dev; 2989 ibev.element.port_num = port; 2990 2991 if (port < 1 || port > ibdev->num_ports) { 2992 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2993 goto out; 2994 } 2995 2996 if (ibdev->ib_active) 2997 ib_dispatch_event(&ibev); 2998 2999 if (fatal) 3000 ibdev->ib_active = false; 3001 3002 out: 3003 return; 3004 } 3005 3006 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3007 { 3008 struct mlx5_hca_vport_context vport_ctx; 3009 int err; 3010 int port; 3011 3012 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 3013 dev->mdev->port_caps[port - 1].has_smi = false; 3014 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3015 MLX5_CAP_PORT_TYPE_IB) { 3016 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3017 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3018 port, 0, 3019 &vport_ctx); 3020 if (err) { 3021 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3022 port, err); 3023 return err; 3024 } 3025 dev->mdev->port_caps[port - 1].has_smi = 3026 vport_ctx.has_smi; 3027 } else { 3028 dev->mdev->port_caps[port - 1].has_smi = true; 3029 } 3030 } 3031 } 3032 return 0; 3033 } 3034 3035 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3036 { 3037 int port; 3038 3039 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 3040 mlx5_query_ext_port_caps(dev, port); 3041 } 3042 3043 static int get_port_caps(struct mlx5_ib_dev *dev) 3044 { 3045 struct ib_device_attr *dprops = NULL; 3046 struct ib_port_attr *pprops = NULL; 3047 int err = -ENOMEM; 3048 int port; 3049 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3050 3051 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3052 if (!pprops) 3053 goto out; 3054 3055 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3056 if (!dprops) 3057 goto out; 3058 3059 err = set_has_smi_cap(dev); 3060 if (err) 3061 goto out; 3062 3063 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3064 if (err) { 3065 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3066 goto out; 3067 } 3068 3069 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 3070 memset(pprops, 0, sizeof(*pprops)); 3071 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3072 if (err) { 3073 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3074 port, err); 3075 break; 3076 } 3077 dev->mdev->port_caps[port - 1].pkey_table_len = 3078 dprops->max_pkeys; 3079 dev->mdev->port_caps[port - 1].gid_table_len = 3080 pprops->gid_tbl_len; 3081 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 3082 dprops->max_pkeys, pprops->gid_tbl_len); 3083 } 3084 3085 out: 3086 kfree(pprops); 3087 kfree(dprops); 3088 3089 return err; 3090 } 3091 3092 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3093 { 3094 int err; 3095 3096 err = mlx5_mr_cache_cleanup(dev); 3097 if (err) 3098 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3099 3100 mlx5_ib_destroy_qp(dev->umrc.qp); 3101 ib_free_cq(dev->umrc.cq); 3102 ib_dealloc_pd(dev->umrc.pd); 3103 } 3104 3105 enum { 3106 MAX_UMR_WR = 128, 3107 }; 3108 3109 static int create_umr_res(struct mlx5_ib_dev *dev) 3110 { 3111 struct ib_qp_init_attr *init_attr = NULL; 3112 struct ib_qp_attr *attr = NULL; 3113 struct ib_pd *pd; 3114 struct ib_cq *cq; 3115 struct ib_qp *qp; 3116 int ret; 3117 3118 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3119 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3120 if (!attr || !init_attr) { 3121 ret = -ENOMEM; 3122 goto error_0; 3123 } 3124 3125 pd = ib_alloc_pd(&dev->ib_dev, 0); 3126 if (IS_ERR(pd)) { 3127 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3128 ret = PTR_ERR(pd); 3129 goto error_0; 3130 } 3131 3132 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3133 if (IS_ERR(cq)) { 3134 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3135 ret = PTR_ERR(cq); 3136 goto error_2; 3137 } 3138 3139 init_attr->send_cq = cq; 3140 init_attr->recv_cq = cq; 3141 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3142 init_attr->cap.max_send_wr = MAX_UMR_WR; 3143 init_attr->cap.max_send_sge = 1; 3144 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3145 init_attr->port_num = 1; 3146 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3147 if (IS_ERR(qp)) { 3148 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3149 ret = PTR_ERR(qp); 3150 goto error_3; 3151 } 3152 qp->device = &dev->ib_dev; 3153 qp->real_qp = qp; 3154 qp->uobject = NULL; 3155 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3156 qp->send_cq = init_attr->send_cq; 3157 qp->recv_cq = init_attr->recv_cq; 3158 3159 attr->qp_state = IB_QPS_INIT; 3160 attr->port_num = 1; 3161 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3162 IB_QP_PORT, NULL); 3163 if (ret) { 3164 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3165 goto error_4; 3166 } 3167 3168 memset(attr, 0, sizeof(*attr)); 3169 attr->qp_state = IB_QPS_RTR; 3170 attr->path_mtu = IB_MTU_256; 3171 3172 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3173 if (ret) { 3174 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3175 goto error_4; 3176 } 3177 3178 memset(attr, 0, sizeof(*attr)); 3179 attr->qp_state = IB_QPS_RTS; 3180 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3181 if (ret) { 3182 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3183 goto error_4; 3184 } 3185 3186 dev->umrc.qp = qp; 3187 dev->umrc.cq = cq; 3188 dev->umrc.pd = pd; 3189 3190 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3191 ret = mlx5_mr_cache_init(dev); 3192 if (ret) { 3193 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3194 goto error_4; 3195 } 3196 3197 kfree(attr); 3198 kfree(init_attr); 3199 3200 return 0; 3201 3202 error_4: 3203 mlx5_ib_destroy_qp(qp); 3204 3205 error_3: 3206 ib_free_cq(cq); 3207 3208 error_2: 3209 ib_dealloc_pd(pd); 3210 3211 error_0: 3212 kfree(attr); 3213 kfree(init_attr); 3214 return ret; 3215 } 3216 3217 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3218 { 3219 switch (umr_fence_cap) { 3220 case MLX5_CAP_UMR_FENCE_NONE: 3221 return MLX5_FENCE_MODE_NONE; 3222 case MLX5_CAP_UMR_FENCE_SMALL: 3223 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3224 default: 3225 return MLX5_FENCE_MODE_STRONG_ORDERING; 3226 } 3227 } 3228 3229 static int create_dev_resources(struct mlx5_ib_resources *devr) 3230 { 3231 struct ib_srq_init_attr attr; 3232 struct mlx5_ib_dev *dev; 3233 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3234 int port; 3235 int ret = 0; 3236 3237 dev = container_of(devr, struct mlx5_ib_dev, devr); 3238 3239 mutex_init(&devr->mutex); 3240 3241 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3242 if (IS_ERR(devr->p0)) { 3243 ret = PTR_ERR(devr->p0); 3244 goto error0; 3245 } 3246 devr->p0->device = &dev->ib_dev; 3247 devr->p0->uobject = NULL; 3248 atomic_set(&devr->p0->usecnt, 0); 3249 3250 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3251 if (IS_ERR(devr->c0)) { 3252 ret = PTR_ERR(devr->c0); 3253 goto error1; 3254 } 3255 devr->c0->device = &dev->ib_dev; 3256 devr->c0->uobject = NULL; 3257 devr->c0->comp_handler = NULL; 3258 devr->c0->event_handler = NULL; 3259 devr->c0->cq_context = NULL; 3260 atomic_set(&devr->c0->usecnt, 0); 3261 3262 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3263 if (IS_ERR(devr->x0)) { 3264 ret = PTR_ERR(devr->x0); 3265 goto error2; 3266 } 3267 devr->x0->device = &dev->ib_dev; 3268 devr->x0->inode = NULL; 3269 atomic_set(&devr->x0->usecnt, 0); 3270 mutex_init(&devr->x0->tgt_qp_mutex); 3271 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3272 3273 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3274 if (IS_ERR(devr->x1)) { 3275 ret = PTR_ERR(devr->x1); 3276 goto error3; 3277 } 3278 devr->x1->device = &dev->ib_dev; 3279 devr->x1->inode = NULL; 3280 atomic_set(&devr->x1->usecnt, 0); 3281 mutex_init(&devr->x1->tgt_qp_mutex); 3282 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3283 3284 memset(&attr, 0, sizeof(attr)); 3285 attr.attr.max_sge = 1; 3286 attr.attr.max_wr = 1; 3287 attr.srq_type = IB_SRQT_XRC; 3288 attr.ext.cq = devr->c0; 3289 attr.ext.xrc.xrcd = devr->x0; 3290 3291 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3292 if (IS_ERR(devr->s0)) { 3293 ret = PTR_ERR(devr->s0); 3294 goto error4; 3295 } 3296 devr->s0->device = &dev->ib_dev; 3297 devr->s0->pd = devr->p0; 3298 devr->s0->uobject = NULL; 3299 devr->s0->event_handler = NULL; 3300 devr->s0->srq_context = NULL; 3301 devr->s0->srq_type = IB_SRQT_XRC; 3302 devr->s0->ext.xrc.xrcd = devr->x0; 3303 devr->s0->ext.cq = devr->c0; 3304 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3305 atomic_inc(&devr->s0->ext.cq->usecnt); 3306 atomic_inc(&devr->p0->usecnt); 3307 atomic_set(&devr->s0->usecnt, 0); 3308 3309 memset(&attr, 0, sizeof(attr)); 3310 attr.attr.max_sge = 1; 3311 attr.attr.max_wr = 1; 3312 attr.srq_type = IB_SRQT_BASIC; 3313 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3314 if (IS_ERR(devr->s1)) { 3315 ret = PTR_ERR(devr->s1); 3316 goto error5; 3317 } 3318 devr->s1->device = &dev->ib_dev; 3319 devr->s1->pd = devr->p0; 3320 devr->s1->uobject = NULL; 3321 devr->s1->event_handler = NULL; 3322 devr->s1->srq_context = NULL; 3323 devr->s1->srq_type = IB_SRQT_BASIC; 3324 devr->s1->ext.cq = devr->c0; 3325 atomic_inc(&devr->p0->usecnt); 3326 atomic_set(&devr->s1->usecnt, 0); 3327 3328 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3329 INIT_WORK(&devr->ports[port].pkey_change_work, 3330 pkey_change_handler); 3331 devr->ports[port].devr = devr; 3332 } 3333 3334 return 0; 3335 3336 error5: 3337 mlx5_ib_destroy_srq(devr->s0); 3338 error4: 3339 mlx5_ib_dealloc_xrcd(devr->x1); 3340 error3: 3341 mlx5_ib_dealloc_xrcd(devr->x0); 3342 error2: 3343 mlx5_ib_destroy_cq(devr->c0); 3344 error1: 3345 mlx5_ib_dealloc_pd(devr->p0); 3346 error0: 3347 return ret; 3348 } 3349 3350 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3351 { 3352 struct mlx5_ib_dev *dev = 3353 container_of(devr, struct mlx5_ib_dev, devr); 3354 int port; 3355 3356 mlx5_ib_destroy_srq(devr->s1); 3357 mlx5_ib_destroy_srq(devr->s0); 3358 mlx5_ib_dealloc_xrcd(devr->x0); 3359 mlx5_ib_dealloc_xrcd(devr->x1); 3360 mlx5_ib_destroy_cq(devr->c0); 3361 mlx5_ib_dealloc_pd(devr->p0); 3362 3363 /* Make sure no change P_Key work items are still executing */ 3364 for (port = 0; port < dev->num_ports; ++port) 3365 cancel_work_sync(&devr->ports[port].pkey_change_work); 3366 } 3367 3368 static u32 get_core_cap_flags(struct ib_device *ibdev) 3369 { 3370 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3371 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3372 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3373 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3374 u32 ret = 0; 3375 3376 if (ll == IB_LINK_LAYER_INFINIBAND) 3377 return RDMA_CORE_PORT_IBA_IB; 3378 3379 ret = RDMA_CORE_PORT_RAW_PACKET; 3380 3381 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3382 return ret; 3383 3384 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3385 return ret; 3386 3387 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3388 ret |= RDMA_CORE_PORT_IBA_ROCE; 3389 3390 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3391 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3392 3393 return ret; 3394 } 3395 3396 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3397 struct ib_port_immutable *immutable) 3398 { 3399 struct ib_port_attr attr; 3400 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3401 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3402 int err; 3403 3404 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3405 3406 err = ib_query_port(ibdev, port_num, &attr); 3407 if (err) 3408 return err; 3409 3410 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3411 immutable->gid_tbl_len = attr.gid_tbl_len; 3412 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3413 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3414 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3415 3416 return 0; 3417 } 3418 3419 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3420 { 3421 struct mlx5_ib_dev *dev = 3422 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3423 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3424 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3425 fw_rev_sub(dev->mdev)); 3426 } 3427 3428 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3429 { 3430 struct mlx5_core_dev *mdev = dev->mdev; 3431 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3432 MLX5_FLOW_NAMESPACE_LAG); 3433 struct mlx5_flow_table *ft; 3434 int err; 3435 3436 if (!ns || !mlx5_lag_is_active(mdev)) 3437 return 0; 3438 3439 err = mlx5_cmd_create_vport_lag(mdev); 3440 if (err) 3441 return err; 3442 3443 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3444 if (IS_ERR(ft)) { 3445 err = PTR_ERR(ft); 3446 goto err_destroy_vport_lag; 3447 } 3448 3449 dev->flow_db.lag_demux_ft = ft; 3450 return 0; 3451 3452 err_destroy_vport_lag: 3453 mlx5_cmd_destroy_vport_lag(mdev); 3454 return err; 3455 } 3456 3457 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3458 { 3459 struct mlx5_core_dev *mdev = dev->mdev; 3460 3461 if (dev->flow_db.lag_demux_ft) { 3462 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3463 dev->flow_db.lag_demux_ft = NULL; 3464 3465 mlx5_cmd_destroy_vport_lag(mdev); 3466 } 3467 } 3468 3469 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3470 { 3471 int err; 3472 3473 dev->roce.nb.notifier_call = mlx5_netdev_event; 3474 err = register_netdevice_notifier(&dev->roce.nb); 3475 if (err) { 3476 dev->roce.nb.notifier_call = NULL; 3477 return err; 3478 } 3479 3480 return 0; 3481 } 3482 3483 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3484 { 3485 if (dev->roce.nb.notifier_call) { 3486 unregister_netdevice_notifier(&dev->roce.nb); 3487 dev->roce.nb.notifier_call = NULL; 3488 } 3489 } 3490 3491 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3492 { 3493 int err; 3494 3495 err = mlx5_add_netdev_notifier(dev); 3496 if (err) 3497 return err; 3498 3499 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3500 err = mlx5_nic_vport_enable_roce(dev->mdev); 3501 if (err) 3502 goto err_unregister_netdevice_notifier; 3503 } 3504 3505 err = mlx5_eth_lag_init(dev); 3506 if (err) 3507 goto err_disable_roce; 3508 3509 return 0; 3510 3511 err_disable_roce: 3512 if (MLX5_CAP_GEN(dev->mdev, roce)) 3513 mlx5_nic_vport_disable_roce(dev->mdev); 3514 3515 err_unregister_netdevice_notifier: 3516 mlx5_remove_netdev_notifier(dev); 3517 return err; 3518 } 3519 3520 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3521 { 3522 mlx5_eth_lag_cleanup(dev); 3523 if (MLX5_CAP_GEN(dev->mdev, roce)) 3524 mlx5_nic_vport_disable_roce(dev->mdev); 3525 } 3526 3527 struct mlx5_ib_counter { 3528 const char *name; 3529 size_t offset; 3530 }; 3531 3532 #define INIT_Q_COUNTER(_name) \ 3533 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3534 3535 static const struct mlx5_ib_counter basic_q_cnts[] = { 3536 INIT_Q_COUNTER(rx_write_requests), 3537 INIT_Q_COUNTER(rx_read_requests), 3538 INIT_Q_COUNTER(rx_atomic_requests), 3539 INIT_Q_COUNTER(out_of_buffer), 3540 }; 3541 3542 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3543 INIT_Q_COUNTER(out_of_sequence), 3544 }; 3545 3546 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3547 INIT_Q_COUNTER(duplicate_request), 3548 INIT_Q_COUNTER(rnr_nak_retry_err), 3549 INIT_Q_COUNTER(packet_seq_err), 3550 INIT_Q_COUNTER(implied_nak_seq_err), 3551 INIT_Q_COUNTER(local_ack_timeout_err), 3552 }; 3553 3554 #define INIT_CONG_COUNTER(_name) \ 3555 { .name = #_name, .offset = \ 3556 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3557 3558 static const struct mlx5_ib_counter cong_cnts[] = { 3559 INIT_CONG_COUNTER(rp_cnp_ignored), 3560 INIT_CONG_COUNTER(rp_cnp_handled), 3561 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3562 INIT_CONG_COUNTER(np_cnp_sent), 3563 }; 3564 3565 static const struct mlx5_ib_counter extended_err_cnts[] = { 3566 INIT_Q_COUNTER(resp_local_length_error), 3567 INIT_Q_COUNTER(resp_cqe_error), 3568 INIT_Q_COUNTER(req_cqe_error), 3569 INIT_Q_COUNTER(req_remote_invalid_request), 3570 INIT_Q_COUNTER(req_remote_access_errors), 3571 INIT_Q_COUNTER(resp_remote_access_errors), 3572 INIT_Q_COUNTER(resp_cqe_flush_error), 3573 INIT_Q_COUNTER(req_cqe_flush_error), 3574 }; 3575 3576 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3577 { 3578 unsigned int i; 3579 3580 for (i = 0; i < dev->num_ports; i++) { 3581 mlx5_core_dealloc_q_counter(dev->mdev, 3582 dev->port[i].cnts.set_id); 3583 kfree(dev->port[i].cnts.names); 3584 kfree(dev->port[i].cnts.offsets); 3585 } 3586 } 3587 3588 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3589 struct mlx5_ib_counters *cnts) 3590 { 3591 u32 num_counters; 3592 3593 num_counters = ARRAY_SIZE(basic_q_cnts); 3594 3595 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3596 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3597 3598 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3599 num_counters += ARRAY_SIZE(retrans_q_cnts); 3600 3601 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3602 num_counters += ARRAY_SIZE(extended_err_cnts); 3603 3604 cnts->num_q_counters = num_counters; 3605 3606 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3607 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3608 num_counters += ARRAY_SIZE(cong_cnts); 3609 } 3610 3611 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3612 if (!cnts->names) 3613 return -ENOMEM; 3614 3615 cnts->offsets = kcalloc(num_counters, 3616 sizeof(cnts->offsets), GFP_KERNEL); 3617 if (!cnts->offsets) 3618 goto err_names; 3619 3620 return 0; 3621 3622 err_names: 3623 kfree(cnts->names); 3624 return -ENOMEM; 3625 } 3626 3627 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3628 const char **names, 3629 size_t *offsets) 3630 { 3631 int i; 3632 int j = 0; 3633 3634 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3635 names[j] = basic_q_cnts[i].name; 3636 offsets[j] = basic_q_cnts[i].offset; 3637 } 3638 3639 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3640 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3641 names[j] = out_of_seq_q_cnts[i].name; 3642 offsets[j] = out_of_seq_q_cnts[i].offset; 3643 } 3644 } 3645 3646 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3647 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3648 names[j] = retrans_q_cnts[i].name; 3649 offsets[j] = retrans_q_cnts[i].offset; 3650 } 3651 } 3652 3653 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 3654 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 3655 names[j] = extended_err_cnts[i].name; 3656 offsets[j] = extended_err_cnts[i].offset; 3657 } 3658 } 3659 3660 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3661 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3662 names[j] = cong_cnts[i].name; 3663 offsets[j] = cong_cnts[i].offset; 3664 } 3665 } 3666 } 3667 3668 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3669 { 3670 int i; 3671 int ret; 3672 3673 for (i = 0; i < dev->num_ports; i++) { 3674 struct mlx5_ib_port *port = &dev->port[i]; 3675 3676 ret = mlx5_core_alloc_q_counter(dev->mdev, 3677 &port->cnts.set_id); 3678 if (ret) { 3679 mlx5_ib_warn(dev, 3680 "couldn't allocate queue counter for port %d, err %d\n", 3681 i + 1, ret); 3682 goto dealloc_counters; 3683 } 3684 3685 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3686 if (ret) 3687 goto dealloc_counters; 3688 3689 mlx5_ib_fill_counters(dev, port->cnts.names, 3690 port->cnts.offsets); 3691 } 3692 3693 return 0; 3694 3695 dealloc_counters: 3696 while (--i >= 0) 3697 mlx5_core_dealloc_q_counter(dev->mdev, 3698 dev->port[i].cnts.set_id); 3699 3700 return ret; 3701 } 3702 3703 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3704 u8 port_num) 3705 { 3706 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3707 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3708 3709 /* We support only per port stats */ 3710 if (port_num == 0) 3711 return NULL; 3712 3713 return rdma_alloc_hw_stats_struct(port->cnts.names, 3714 port->cnts.num_q_counters + 3715 port->cnts.num_cong_counters, 3716 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3717 } 3718 3719 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3720 struct mlx5_ib_port *port, 3721 struct rdma_hw_stats *stats) 3722 { 3723 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3724 void *out; 3725 __be32 val; 3726 int ret, i; 3727 3728 out = kvzalloc(outlen, GFP_KERNEL); 3729 if (!out) 3730 return -ENOMEM; 3731 3732 ret = mlx5_core_query_q_counter(dev->mdev, 3733 port->cnts.set_id, 0, 3734 out, outlen); 3735 if (ret) 3736 goto free; 3737 3738 for (i = 0; i < port->cnts.num_q_counters; i++) { 3739 val = *(__be32 *)(out + port->cnts.offsets[i]); 3740 stats->value[i] = (u64)be32_to_cpu(val); 3741 } 3742 3743 free: 3744 kvfree(out); 3745 return ret; 3746 } 3747 3748 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3749 struct rdma_hw_stats *stats, 3750 u8 port_num, int index) 3751 { 3752 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3753 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3754 int ret, num_counters; 3755 3756 if (!stats) 3757 return -EINVAL; 3758 3759 ret = mlx5_ib_query_q_counters(dev, port, stats); 3760 if (ret) 3761 return ret; 3762 num_counters = port->cnts.num_q_counters; 3763 3764 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3765 ret = mlx5_lag_query_cong_counters(dev->mdev, 3766 stats->value + 3767 port->cnts.num_q_counters, 3768 port->cnts.num_cong_counters, 3769 port->cnts.offsets + 3770 port->cnts.num_q_counters); 3771 if (ret) 3772 return ret; 3773 num_counters += port->cnts.num_cong_counters; 3774 } 3775 3776 return num_counters; 3777 } 3778 3779 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3780 { 3781 return mlx5_rdma_netdev_free(netdev); 3782 } 3783 3784 static struct net_device* 3785 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3786 u8 port_num, 3787 enum rdma_netdev_t type, 3788 const char *name, 3789 unsigned char name_assign_type, 3790 void (*setup)(struct net_device *)) 3791 { 3792 struct net_device *netdev; 3793 struct rdma_netdev *rn; 3794 3795 if (type != RDMA_NETDEV_IPOIB) 3796 return ERR_PTR(-EOPNOTSUPP); 3797 3798 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3799 name, setup); 3800 if (likely(!IS_ERR_OR_NULL(netdev))) { 3801 rn = netdev_priv(netdev); 3802 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3803 } 3804 return netdev; 3805 } 3806 3807 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3808 { 3809 if (!dev->delay_drop.dbg) 3810 return; 3811 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 3812 kfree(dev->delay_drop.dbg); 3813 dev->delay_drop.dbg = NULL; 3814 } 3815 3816 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3817 { 3818 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3819 return; 3820 3821 cancel_work_sync(&dev->delay_drop.delay_drop_work); 3822 delay_drop_debugfs_cleanup(dev); 3823 } 3824 3825 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3826 size_t count, loff_t *pos) 3827 { 3828 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3829 char lbuf[20]; 3830 int len; 3831 3832 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3833 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3834 } 3835 3836 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3837 size_t count, loff_t *pos) 3838 { 3839 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3840 u32 timeout; 3841 u32 var; 3842 3843 if (kstrtouint_from_user(buf, count, 0, &var)) 3844 return -EFAULT; 3845 3846 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3847 1000); 3848 if (timeout != var) 3849 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3850 timeout); 3851 3852 delay_drop->timeout = timeout; 3853 3854 return count; 3855 } 3856 3857 static const struct file_operations fops_delay_drop_timeout = { 3858 .owner = THIS_MODULE, 3859 .open = simple_open, 3860 .write = delay_drop_timeout_write, 3861 .read = delay_drop_timeout_read, 3862 }; 3863 3864 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3865 { 3866 struct mlx5_ib_dbg_delay_drop *dbg; 3867 3868 if (!mlx5_debugfs_root) 3869 return 0; 3870 3871 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 3872 if (!dbg) 3873 return -ENOMEM; 3874 3875 dev->delay_drop.dbg = dbg; 3876 3877 dbg->dir_debugfs = 3878 debugfs_create_dir("delay_drop", 3879 dev->mdev->priv.dbg_root); 3880 if (!dbg->dir_debugfs) 3881 goto out_debugfs; 3882 3883 dbg->events_cnt_debugfs = 3884 debugfs_create_atomic_t("num_timeout_events", 0400, 3885 dbg->dir_debugfs, 3886 &dev->delay_drop.events_cnt); 3887 if (!dbg->events_cnt_debugfs) 3888 goto out_debugfs; 3889 3890 dbg->rqs_cnt_debugfs = 3891 debugfs_create_atomic_t("num_rqs", 0400, 3892 dbg->dir_debugfs, 3893 &dev->delay_drop.rqs_cnt); 3894 if (!dbg->rqs_cnt_debugfs) 3895 goto out_debugfs; 3896 3897 dbg->timeout_debugfs = 3898 debugfs_create_file("timeout", 0600, 3899 dbg->dir_debugfs, 3900 &dev->delay_drop, 3901 &fops_delay_drop_timeout); 3902 if (!dbg->timeout_debugfs) 3903 goto out_debugfs; 3904 3905 return 0; 3906 3907 out_debugfs: 3908 delay_drop_debugfs_cleanup(dev); 3909 return -ENOMEM; 3910 } 3911 3912 static void init_delay_drop(struct mlx5_ib_dev *dev) 3913 { 3914 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3915 return; 3916 3917 mutex_init(&dev->delay_drop.lock); 3918 dev->delay_drop.dev = dev; 3919 dev->delay_drop.activate = false; 3920 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3921 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3922 atomic_set(&dev->delay_drop.rqs_cnt, 0); 3923 atomic_set(&dev->delay_drop.events_cnt, 0); 3924 3925 if (delay_drop_debugfs_init(dev)) 3926 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 3927 } 3928 3929 static const struct cpumask * 3930 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 3931 { 3932 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3933 3934 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 3935 } 3936 3937 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3938 { 3939 struct mlx5_ib_dev *dev; 3940 enum rdma_link_layer ll; 3941 int port_type_cap; 3942 const char *name; 3943 int err; 3944 int i; 3945 3946 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3947 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3948 3949 printk_once(KERN_INFO "%s", mlx5_version); 3950 3951 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3952 if (!dev) 3953 return NULL; 3954 3955 dev->mdev = mdev; 3956 3957 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3958 GFP_KERNEL); 3959 if (!dev->port) 3960 goto err_dealloc; 3961 3962 rwlock_init(&dev->roce.netdev_lock); 3963 err = get_port_caps(dev); 3964 if (err) 3965 goto err_free_port; 3966 3967 if (mlx5_use_mad_ifc(dev)) 3968 get_ext_port_caps(dev); 3969 3970 if (!mlx5_lag_is_active(mdev)) 3971 name = "mlx5_%d"; 3972 else 3973 name = "mlx5_bond_%d"; 3974 3975 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3976 dev->ib_dev.owner = THIS_MODULE; 3977 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3978 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3979 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3980 dev->ib_dev.phys_port_cnt = dev->num_ports; 3981 dev->ib_dev.num_comp_vectors = 3982 dev->mdev->priv.eq_table.num_comp_vectors; 3983 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3984 3985 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3986 dev->ib_dev.uverbs_cmd_mask = 3987 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3988 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3989 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3990 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3991 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3992 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3993 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3994 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3995 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3996 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3997 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3998 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3999 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4000 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4001 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4002 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4003 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4004 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4005 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4006 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4007 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4008 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4009 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4010 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4011 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4012 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4013 dev->ib_dev.uverbs_ex_cmd_mask = 4014 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4015 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4016 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4017 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 4018 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 4019 4020 dev->ib_dev.query_device = mlx5_ib_query_device; 4021 dev->ib_dev.query_port = mlx5_ib_query_port; 4022 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 4023 if (ll == IB_LINK_LAYER_ETHERNET) 4024 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 4025 dev->ib_dev.query_gid = mlx5_ib_query_gid; 4026 dev->ib_dev.add_gid = mlx5_ib_add_gid; 4027 dev->ib_dev.del_gid = mlx5_ib_del_gid; 4028 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 4029 dev->ib_dev.modify_device = mlx5_ib_modify_device; 4030 dev->ib_dev.modify_port = mlx5_ib_modify_port; 4031 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 4032 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 4033 dev->ib_dev.mmap = mlx5_ib_mmap; 4034 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 4035 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 4036 dev->ib_dev.create_ah = mlx5_ib_create_ah; 4037 dev->ib_dev.query_ah = mlx5_ib_query_ah; 4038 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 4039 dev->ib_dev.create_srq = mlx5_ib_create_srq; 4040 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 4041 dev->ib_dev.query_srq = mlx5_ib_query_srq; 4042 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 4043 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 4044 dev->ib_dev.create_qp = mlx5_ib_create_qp; 4045 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 4046 dev->ib_dev.query_qp = mlx5_ib_query_qp; 4047 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 4048 dev->ib_dev.post_send = mlx5_ib_post_send; 4049 dev->ib_dev.post_recv = mlx5_ib_post_recv; 4050 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4051 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4052 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4053 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4054 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4055 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4056 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4057 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4058 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4059 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4060 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4061 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4062 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4063 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4064 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4065 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4066 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4067 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4068 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4069 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4070 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4071 4072 if (mlx5_core_is_pf(mdev)) { 4073 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4074 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4075 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4076 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4077 } 4078 4079 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4080 4081 mlx5_ib_internal_fill_odp_caps(dev); 4082 4083 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4084 4085 if (MLX5_CAP_GEN(mdev, imaicl)) { 4086 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4087 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4088 dev->ib_dev.uverbs_cmd_mask |= 4089 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4090 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4091 } 4092 4093 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4094 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4095 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4096 } 4097 4098 if (MLX5_CAP_GEN(mdev, xrc)) { 4099 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4100 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4101 dev->ib_dev.uverbs_cmd_mask |= 4102 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4103 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4104 } 4105 4106 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4107 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4108 dev->ib_dev.uverbs_ex_cmd_mask |= 4109 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4110 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4111 4112 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 4113 IB_LINK_LAYER_ETHERNET) { 4114 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4115 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4116 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4117 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4118 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4119 dev->ib_dev.uverbs_ex_cmd_mask |= 4120 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4121 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4122 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4123 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4124 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4125 } 4126 err = init_node_data(dev); 4127 if (err) 4128 goto err_free_port; 4129 4130 mutex_init(&dev->flow_db.lock); 4131 mutex_init(&dev->cap_mask_mutex); 4132 INIT_LIST_HEAD(&dev->qp_list); 4133 spin_lock_init(&dev->reset_flow_resource_lock); 4134 4135 if (ll == IB_LINK_LAYER_ETHERNET) { 4136 err = mlx5_enable_eth(dev); 4137 if (err) 4138 goto err_free_port; 4139 dev->roce.last_port_state = IB_PORT_DOWN; 4140 } 4141 4142 err = create_dev_resources(&dev->devr); 4143 if (err) 4144 goto err_disable_eth; 4145 4146 err = mlx5_ib_odp_init_one(dev); 4147 if (err) 4148 goto err_rsrc; 4149 4150 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4151 err = mlx5_ib_alloc_counters(dev); 4152 if (err) 4153 goto err_odp; 4154 } 4155 4156 err = mlx5_ib_init_cong_debugfs(dev); 4157 if (err) 4158 goto err_cnt; 4159 4160 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4161 if (!dev->mdev->priv.uar) 4162 goto err_cong; 4163 4164 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4165 if (err) 4166 goto err_uar_page; 4167 4168 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4169 if (err) 4170 goto err_bfreg; 4171 4172 err = ib_register_device(&dev->ib_dev, NULL); 4173 if (err) 4174 goto err_fp_bfreg; 4175 4176 err = create_umr_res(dev); 4177 if (err) 4178 goto err_dev; 4179 4180 init_delay_drop(dev); 4181 4182 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4183 err = device_create_file(&dev->ib_dev.dev, 4184 mlx5_class_attributes[i]); 4185 if (err) 4186 goto err_delay_drop; 4187 } 4188 4189 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4190 MLX5_CAP_GEN(mdev, disable_local_lb)) 4191 mutex_init(&dev->lb_mutex); 4192 4193 dev->ib_active = true; 4194 4195 return dev; 4196 4197 err_delay_drop: 4198 cancel_delay_drop(dev); 4199 destroy_umrc_res(dev); 4200 4201 err_dev: 4202 ib_unregister_device(&dev->ib_dev); 4203 4204 err_fp_bfreg: 4205 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4206 4207 err_bfreg: 4208 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4209 4210 err_uar_page: 4211 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4212 4213 err_cong: 4214 mlx5_ib_cleanup_cong_debugfs(dev); 4215 err_cnt: 4216 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4217 mlx5_ib_dealloc_counters(dev); 4218 4219 err_odp: 4220 mlx5_ib_odp_remove_one(dev); 4221 4222 err_rsrc: 4223 destroy_dev_resources(&dev->devr); 4224 4225 err_disable_eth: 4226 if (ll == IB_LINK_LAYER_ETHERNET) { 4227 mlx5_disable_eth(dev); 4228 mlx5_remove_netdev_notifier(dev); 4229 } 4230 4231 err_free_port: 4232 kfree(dev->port); 4233 4234 err_dealloc: 4235 ib_dealloc_device((struct ib_device *)dev); 4236 4237 return NULL; 4238 } 4239 4240 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4241 { 4242 struct mlx5_ib_dev *dev = context; 4243 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 4244 4245 cancel_delay_drop(dev); 4246 mlx5_remove_netdev_notifier(dev); 4247 ib_unregister_device(&dev->ib_dev); 4248 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4249 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4250 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 4251 mlx5_ib_cleanup_cong_debugfs(dev); 4252 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4253 mlx5_ib_dealloc_counters(dev); 4254 destroy_umrc_res(dev); 4255 mlx5_ib_odp_remove_one(dev); 4256 destroy_dev_resources(&dev->devr); 4257 if (ll == IB_LINK_LAYER_ETHERNET) 4258 mlx5_disable_eth(dev); 4259 kfree(dev->port); 4260 ib_dealloc_device(&dev->ib_dev); 4261 } 4262 4263 static struct mlx5_interface mlx5_ib_interface = { 4264 .add = mlx5_ib_add, 4265 .remove = mlx5_ib_remove, 4266 .event = mlx5_ib_event, 4267 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4268 .pfault = mlx5_ib_pfault, 4269 #endif 4270 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4271 }; 4272 4273 static int __init mlx5_ib_init(void) 4274 { 4275 int err; 4276 4277 mlx5_ib_odp_init(); 4278 4279 err = mlx5_register_interface(&mlx5_ib_interface); 4280 4281 return err; 4282 } 4283 4284 static void __exit mlx5_ib_cleanup(void) 4285 { 4286 mlx5_unregister_interface(&mlx5_ib_interface); 4287 } 4288 4289 module_init(mlx5_ib_init); 4290 module_exit(mlx5_ib_cleanup); 4291