1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/sched.h> 42 #include <rdma/ib_user_verbs.h> 43 #include <rdma/ib_addr.h> 44 #include <rdma/ib_cache.h> 45 #include <linux/mlx5/vport.h> 46 #include <rdma/ib_smi.h> 47 #include <rdma/ib_umem.h> 48 #include <linux/in.h> 49 #include <linux/etherdevice.h> 50 #include <linux/mlx5/fs.h> 51 #include "user.h" 52 #include "mlx5_ib.h" 53 54 #define DRIVER_NAME "mlx5_ib" 55 #define DRIVER_VERSION "2.2-1" 56 #define DRIVER_RELDATE "Feb 2014" 57 58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 59 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 MODULE_VERSION(DRIVER_VERSION); 62 63 static int deprecated_prof_sel = 2; 64 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 65 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 66 67 static char mlx5_version[] = 68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 70 71 enum { 72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 73 }; 74 75 static enum rdma_link_layer 76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 77 { 78 switch (port_type_cap) { 79 case MLX5_CAP_PORT_TYPE_IB: 80 return IB_LINK_LAYER_INFINIBAND; 81 case MLX5_CAP_PORT_TYPE_ETH: 82 return IB_LINK_LAYER_ETHERNET; 83 default: 84 return IB_LINK_LAYER_UNSPECIFIED; 85 } 86 } 87 88 static enum rdma_link_layer 89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 90 { 91 struct mlx5_ib_dev *dev = to_mdev(device); 92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 93 94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 95 } 96 97 static int mlx5_netdev_event(struct notifier_block *this, 98 unsigned long event, void *ptr) 99 { 100 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 101 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 102 roce.nb); 103 104 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 105 return NOTIFY_DONE; 106 107 write_lock(&ibdev->roce.netdev_lock); 108 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 109 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 110 write_unlock(&ibdev->roce.netdev_lock); 111 112 return NOTIFY_DONE; 113 } 114 115 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 116 u8 port_num) 117 { 118 struct mlx5_ib_dev *ibdev = to_mdev(device); 119 struct net_device *ndev; 120 121 /* Ensure ndev does not disappear before we invoke dev_hold() 122 */ 123 read_lock(&ibdev->roce.netdev_lock); 124 ndev = ibdev->roce.netdev; 125 if (ndev) 126 dev_hold(ndev); 127 read_unlock(&ibdev->roce.netdev_lock); 128 129 return ndev; 130 } 131 132 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 133 struct ib_port_attr *props) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 struct net_device *ndev; 137 enum ib_mtu ndev_ib_mtu; 138 u16 qkey_viol_cntr; 139 140 memset(props, 0, sizeof(*props)); 141 142 props->port_cap_flags |= IB_PORT_CM_SUP; 143 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 144 145 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 146 roce_address_table_size); 147 props->max_mtu = IB_MTU_4096; 148 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 149 props->pkey_tbl_len = 1; 150 props->state = IB_PORT_DOWN; 151 props->phys_state = 3; 152 153 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 154 props->qkey_viol_cntr = qkey_viol_cntr; 155 156 ndev = mlx5_ib_get_netdev(device, port_num); 157 if (!ndev) 158 return 0; 159 160 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 161 props->state = IB_PORT_ACTIVE; 162 props->phys_state = 5; 163 } 164 165 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 166 167 dev_put(ndev); 168 169 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 170 171 props->active_width = IB_WIDTH_4X; /* TODO */ 172 props->active_speed = IB_SPEED_QDR; /* TODO */ 173 174 return 0; 175 } 176 177 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 178 const struct ib_gid_attr *attr, 179 void *mlx5_addr) 180 { 181 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 182 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 183 source_l3_address); 184 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 185 source_mac_47_32); 186 187 if (!gid) 188 return; 189 190 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 191 192 if (is_vlan_dev(attr->ndev)) { 193 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 194 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 195 } 196 197 switch (attr->gid_type) { 198 case IB_GID_TYPE_IB: 199 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 200 break; 201 case IB_GID_TYPE_ROCE_UDP_ENCAP: 202 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 203 break; 204 205 default: 206 WARN_ON(true); 207 } 208 209 if (attr->gid_type != IB_GID_TYPE_IB) { 210 if (ipv6_addr_v4mapped((void *)gid)) 211 MLX5_SET_RA(mlx5_addr, roce_l3_type, 212 MLX5_ROCE_L3_TYPE_IPV4); 213 else 214 MLX5_SET_RA(mlx5_addr, roce_l3_type, 215 MLX5_ROCE_L3_TYPE_IPV6); 216 } 217 218 if ((attr->gid_type == IB_GID_TYPE_IB) || 219 !ipv6_addr_v4mapped((void *)gid)) 220 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 221 else 222 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 223 } 224 225 static int set_roce_addr(struct ib_device *device, u8 port_num, 226 unsigned int index, 227 const union ib_gid *gid, 228 const struct ib_gid_attr *attr) 229 { 230 struct mlx5_ib_dev *dev = to_mdev(device); 231 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; 232 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; 233 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 234 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 235 236 if (ll != IB_LINK_LAYER_ETHERNET) 237 return -EINVAL; 238 239 memset(in, 0, sizeof(in)); 240 241 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 242 243 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 244 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 245 246 memset(out, 0, sizeof(out)); 247 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 248 } 249 250 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 251 unsigned int index, const union ib_gid *gid, 252 const struct ib_gid_attr *attr, 253 __always_unused void **context) 254 { 255 return set_roce_addr(device, port_num, index, gid, attr); 256 } 257 258 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 259 unsigned int index, __always_unused void **context) 260 { 261 return set_roce_addr(device, port_num, index, NULL, NULL); 262 } 263 264 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 265 int index) 266 { 267 struct ib_gid_attr attr; 268 union ib_gid gid; 269 270 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 271 return 0; 272 273 if (!attr.ndev) 274 return 0; 275 276 dev_put(attr.ndev); 277 278 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 279 return 0; 280 281 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 282 } 283 284 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 285 { 286 return !dev->mdev->issi; 287 } 288 289 enum { 290 MLX5_VPORT_ACCESS_METHOD_MAD, 291 MLX5_VPORT_ACCESS_METHOD_HCA, 292 MLX5_VPORT_ACCESS_METHOD_NIC, 293 }; 294 295 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 296 { 297 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 298 return MLX5_VPORT_ACCESS_METHOD_MAD; 299 300 if (mlx5_ib_port_link_layer(ibdev, 1) == 301 IB_LINK_LAYER_ETHERNET) 302 return MLX5_VPORT_ACCESS_METHOD_NIC; 303 304 return MLX5_VPORT_ACCESS_METHOD_HCA; 305 } 306 307 static void get_atomic_caps(struct mlx5_ib_dev *dev, 308 struct ib_device_attr *props) 309 { 310 u8 tmp; 311 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 312 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 313 u8 atomic_req_8B_endianness_mode = 314 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 315 316 /* Check if HW supports 8 bytes standard atomic operations and capable 317 * of host endianness respond 318 */ 319 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 320 if (((atomic_operations & tmp) == tmp) && 321 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 322 (atomic_req_8B_endianness_mode)) { 323 props->atomic_cap = IB_ATOMIC_HCA; 324 } else { 325 props->atomic_cap = IB_ATOMIC_NONE; 326 } 327 } 328 329 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 330 __be64 *sys_image_guid) 331 { 332 struct mlx5_ib_dev *dev = to_mdev(ibdev); 333 struct mlx5_core_dev *mdev = dev->mdev; 334 u64 tmp; 335 int err; 336 337 switch (mlx5_get_vport_access_method(ibdev)) { 338 case MLX5_VPORT_ACCESS_METHOD_MAD: 339 return mlx5_query_mad_ifc_system_image_guid(ibdev, 340 sys_image_guid); 341 342 case MLX5_VPORT_ACCESS_METHOD_HCA: 343 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 344 break; 345 346 case MLX5_VPORT_ACCESS_METHOD_NIC: 347 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 348 break; 349 350 default: 351 return -EINVAL; 352 } 353 354 if (!err) 355 *sys_image_guid = cpu_to_be64(tmp); 356 357 return err; 358 359 } 360 361 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 362 u16 *max_pkeys) 363 { 364 struct mlx5_ib_dev *dev = to_mdev(ibdev); 365 struct mlx5_core_dev *mdev = dev->mdev; 366 367 switch (mlx5_get_vport_access_method(ibdev)) { 368 case MLX5_VPORT_ACCESS_METHOD_MAD: 369 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 370 371 case MLX5_VPORT_ACCESS_METHOD_HCA: 372 case MLX5_VPORT_ACCESS_METHOD_NIC: 373 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 374 pkey_table_size)); 375 return 0; 376 377 default: 378 return -EINVAL; 379 } 380 } 381 382 static int mlx5_query_vendor_id(struct ib_device *ibdev, 383 u32 *vendor_id) 384 { 385 struct mlx5_ib_dev *dev = to_mdev(ibdev); 386 387 switch (mlx5_get_vport_access_method(ibdev)) { 388 case MLX5_VPORT_ACCESS_METHOD_MAD: 389 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 390 391 case MLX5_VPORT_ACCESS_METHOD_HCA: 392 case MLX5_VPORT_ACCESS_METHOD_NIC: 393 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 394 395 default: 396 return -EINVAL; 397 } 398 } 399 400 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 401 __be64 *node_guid) 402 { 403 u64 tmp; 404 int err; 405 406 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 407 case MLX5_VPORT_ACCESS_METHOD_MAD: 408 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 409 410 case MLX5_VPORT_ACCESS_METHOD_HCA: 411 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 412 break; 413 414 case MLX5_VPORT_ACCESS_METHOD_NIC: 415 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 416 break; 417 418 default: 419 return -EINVAL; 420 } 421 422 if (!err) 423 *node_guid = cpu_to_be64(tmp); 424 425 return err; 426 } 427 428 struct mlx5_reg_node_desc { 429 u8 desc[64]; 430 }; 431 432 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 433 { 434 struct mlx5_reg_node_desc in; 435 436 if (mlx5_use_mad_ifc(dev)) 437 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 438 439 memset(&in, 0, sizeof(in)); 440 441 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 442 sizeof(struct mlx5_reg_node_desc), 443 MLX5_REG_NODE_DESC, 0, 0); 444 } 445 446 static int mlx5_ib_query_device(struct ib_device *ibdev, 447 struct ib_device_attr *props, 448 struct ib_udata *uhw) 449 { 450 struct mlx5_ib_dev *dev = to_mdev(ibdev); 451 struct mlx5_core_dev *mdev = dev->mdev; 452 int err = -ENOMEM; 453 int max_rq_sg; 454 int max_sq_sg; 455 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 456 457 if (uhw->inlen || uhw->outlen) 458 return -EINVAL; 459 460 memset(props, 0, sizeof(*props)); 461 err = mlx5_query_system_image_guid(ibdev, 462 &props->sys_image_guid); 463 if (err) 464 return err; 465 466 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 467 if (err) 468 return err; 469 470 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 471 if (err) 472 return err; 473 474 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 475 (fw_rev_min(dev->mdev) << 16) | 476 fw_rev_sub(dev->mdev); 477 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 478 IB_DEVICE_PORT_ACTIVE_EVENT | 479 IB_DEVICE_SYS_IMAGE_GUID | 480 IB_DEVICE_RC_RNR_NAK_GEN; 481 482 if (MLX5_CAP_GEN(mdev, pkv)) 483 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 484 if (MLX5_CAP_GEN(mdev, qkv)) 485 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 486 if (MLX5_CAP_GEN(mdev, apm)) 487 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 488 if (MLX5_CAP_GEN(mdev, xrc)) 489 props->device_cap_flags |= IB_DEVICE_XRC; 490 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 491 if (MLX5_CAP_GEN(mdev, sho)) { 492 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 493 /* At this stage no support for signature handover */ 494 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 495 IB_PROT_T10DIF_TYPE_2 | 496 IB_PROT_T10DIF_TYPE_3; 497 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 498 IB_GUARD_T10DIF_CSUM; 499 } 500 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 501 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 502 503 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 504 (MLX5_CAP_ETH(dev->mdev, csum_cap))) 505 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 506 507 props->vendor_part_id = mdev->pdev->device; 508 props->hw_ver = mdev->pdev->revision; 509 510 props->max_mr_size = ~0ull; 511 props->page_size_cap = ~(min_page_size - 1); 512 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 513 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 514 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 515 sizeof(struct mlx5_wqe_data_seg); 516 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 517 sizeof(struct mlx5_wqe_ctrl_seg)) / 518 sizeof(struct mlx5_wqe_data_seg); 519 props->max_sge = min(max_rq_sg, max_sq_sg); 520 props->max_sge_rd = props->max_sge; 521 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 522 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 523 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 524 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 525 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 526 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 527 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 528 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 529 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 530 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 531 props->max_srq_sge = max_rq_sg - 1; 532 props->max_fast_reg_page_list_len = (unsigned int)-1; 533 get_atomic_caps(dev, props); 534 props->masked_atomic_cap = IB_ATOMIC_NONE; 535 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 536 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 537 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 538 props->max_mcast_grp; 539 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 540 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 541 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 542 543 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 544 if (MLX5_CAP_GEN(mdev, pg)) 545 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 546 props->odp_caps = dev->odp_caps; 547 #endif 548 549 if (MLX5_CAP_GEN(mdev, cd)) 550 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 551 552 return 0; 553 } 554 555 enum mlx5_ib_width { 556 MLX5_IB_WIDTH_1X = 1 << 0, 557 MLX5_IB_WIDTH_2X = 1 << 1, 558 MLX5_IB_WIDTH_4X = 1 << 2, 559 MLX5_IB_WIDTH_8X = 1 << 3, 560 MLX5_IB_WIDTH_12X = 1 << 4 561 }; 562 563 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 564 u8 *ib_width) 565 { 566 struct mlx5_ib_dev *dev = to_mdev(ibdev); 567 int err = 0; 568 569 if (active_width & MLX5_IB_WIDTH_1X) { 570 *ib_width = IB_WIDTH_1X; 571 } else if (active_width & MLX5_IB_WIDTH_2X) { 572 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 573 (int)active_width); 574 err = -EINVAL; 575 } else if (active_width & MLX5_IB_WIDTH_4X) { 576 *ib_width = IB_WIDTH_4X; 577 } else if (active_width & MLX5_IB_WIDTH_8X) { 578 *ib_width = IB_WIDTH_8X; 579 } else if (active_width & MLX5_IB_WIDTH_12X) { 580 *ib_width = IB_WIDTH_12X; 581 } else { 582 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 583 (int)active_width); 584 err = -EINVAL; 585 } 586 587 return err; 588 } 589 590 static int mlx5_mtu_to_ib_mtu(int mtu) 591 { 592 switch (mtu) { 593 case 256: return 1; 594 case 512: return 2; 595 case 1024: return 3; 596 case 2048: return 4; 597 case 4096: return 5; 598 default: 599 pr_warn("invalid mtu\n"); 600 return -1; 601 } 602 } 603 604 enum ib_max_vl_num { 605 __IB_MAX_VL_0 = 1, 606 __IB_MAX_VL_0_1 = 2, 607 __IB_MAX_VL_0_3 = 3, 608 __IB_MAX_VL_0_7 = 4, 609 __IB_MAX_VL_0_14 = 5, 610 }; 611 612 enum mlx5_vl_hw_cap { 613 MLX5_VL_HW_0 = 1, 614 MLX5_VL_HW_0_1 = 2, 615 MLX5_VL_HW_0_2 = 3, 616 MLX5_VL_HW_0_3 = 4, 617 MLX5_VL_HW_0_4 = 5, 618 MLX5_VL_HW_0_5 = 6, 619 MLX5_VL_HW_0_6 = 7, 620 MLX5_VL_HW_0_7 = 8, 621 MLX5_VL_HW_0_14 = 15 622 }; 623 624 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 625 u8 *max_vl_num) 626 { 627 switch (vl_hw_cap) { 628 case MLX5_VL_HW_0: 629 *max_vl_num = __IB_MAX_VL_0; 630 break; 631 case MLX5_VL_HW_0_1: 632 *max_vl_num = __IB_MAX_VL_0_1; 633 break; 634 case MLX5_VL_HW_0_3: 635 *max_vl_num = __IB_MAX_VL_0_3; 636 break; 637 case MLX5_VL_HW_0_7: 638 *max_vl_num = __IB_MAX_VL_0_7; 639 break; 640 case MLX5_VL_HW_0_14: 641 *max_vl_num = __IB_MAX_VL_0_14; 642 break; 643 644 default: 645 return -EINVAL; 646 } 647 648 return 0; 649 } 650 651 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 652 struct ib_port_attr *props) 653 { 654 struct mlx5_ib_dev *dev = to_mdev(ibdev); 655 struct mlx5_core_dev *mdev = dev->mdev; 656 struct mlx5_hca_vport_context *rep; 657 int max_mtu; 658 int oper_mtu; 659 int err; 660 u8 ib_link_width_oper; 661 u8 vl_hw_cap; 662 663 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 664 if (!rep) { 665 err = -ENOMEM; 666 goto out; 667 } 668 669 memset(props, 0, sizeof(*props)); 670 671 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 672 if (err) 673 goto out; 674 675 props->lid = rep->lid; 676 props->lmc = rep->lmc; 677 props->sm_lid = rep->sm_lid; 678 props->sm_sl = rep->sm_sl; 679 props->state = rep->vport_state; 680 props->phys_state = rep->port_physical_state; 681 props->port_cap_flags = rep->cap_mask1; 682 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 683 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 684 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 685 props->bad_pkey_cntr = rep->pkey_violation_counter; 686 props->qkey_viol_cntr = rep->qkey_violation_counter; 687 props->subnet_timeout = rep->subnet_timeout; 688 props->init_type_reply = rep->init_type_reply; 689 690 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 691 if (err) 692 goto out; 693 694 err = translate_active_width(ibdev, ib_link_width_oper, 695 &props->active_width); 696 if (err) 697 goto out; 698 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, 699 port); 700 if (err) 701 goto out; 702 703 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 704 705 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 706 707 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 708 709 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 710 711 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 712 if (err) 713 goto out; 714 715 err = translate_max_vl_num(ibdev, vl_hw_cap, 716 &props->max_vl_num); 717 out: 718 kfree(rep); 719 return err; 720 } 721 722 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 723 struct ib_port_attr *props) 724 { 725 switch (mlx5_get_vport_access_method(ibdev)) { 726 case MLX5_VPORT_ACCESS_METHOD_MAD: 727 return mlx5_query_mad_ifc_port(ibdev, port, props); 728 729 case MLX5_VPORT_ACCESS_METHOD_HCA: 730 return mlx5_query_hca_port(ibdev, port, props); 731 732 case MLX5_VPORT_ACCESS_METHOD_NIC: 733 return mlx5_query_port_roce(ibdev, port, props); 734 735 default: 736 return -EINVAL; 737 } 738 } 739 740 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 741 union ib_gid *gid) 742 { 743 struct mlx5_ib_dev *dev = to_mdev(ibdev); 744 struct mlx5_core_dev *mdev = dev->mdev; 745 746 switch (mlx5_get_vport_access_method(ibdev)) { 747 case MLX5_VPORT_ACCESS_METHOD_MAD: 748 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 749 750 case MLX5_VPORT_ACCESS_METHOD_HCA: 751 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 752 753 default: 754 return -EINVAL; 755 } 756 757 } 758 759 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 760 u16 *pkey) 761 { 762 struct mlx5_ib_dev *dev = to_mdev(ibdev); 763 struct mlx5_core_dev *mdev = dev->mdev; 764 765 switch (mlx5_get_vport_access_method(ibdev)) { 766 case MLX5_VPORT_ACCESS_METHOD_MAD: 767 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 768 769 case MLX5_VPORT_ACCESS_METHOD_HCA: 770 case MLX5_VPORT_ACCESS_METHOD_NIC: 771 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 772 pkey); 773 default: 774 return -EINVAL; 775 } 776 } 777 778 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 779 struct ib_device_modify *props) 780 { 781 struct mlx5_ib_dev *dev = to_mdev(ibdev); 782 struct mlx5_reg_node_desc in; 783 struct mlx5_reg_node_desc out; 784 int err; 785 786 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 787 return -EOPNOTSUPP; 788 789 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 790 return 0; 791 792 /* 793 * If possible, pass node desc to FW, so it can generate 794 * a 144 trap. If cmd fails, just ignore. 795 */ 796 memcpy(&in, props->node_desc, 64); 797 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 798 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 799 if (err) 800 return err; 801 802 memcpy(ibdev->node_desc, props->node_desc, 64); 803 804 return err; 805 } 806 807 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 808 struct ib_port_modify *props) 809 { 810 struct mlx5_ib_dev *dev = to_mdev(ibdev); 811 struct ib_port_attr attr; 812 u32 tmp; 813 int err; 814 815 mutex_lock(&dev->cap_mask_mutex); 816 817 err = mlx5_ib_query_port(ibdev, port, &attr); 818 if (err) 819 goto out; 820 821 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 822 ~props->clr_port_cap_mask; 823 824 err = mlx5_set_port_caps(dev->mdev, port, tmp); 825 826 out: 827 mutex_unlock(&dev->cap_mask_mutex); 828 return err; 829 } 830 831 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 832 struct ib_udata *udata) 833 { 834 struct mlx5_ib_dev *dev = to_mdev(ibdev); 835 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 836 struct mlx5_ib_alloc_ucontext_resp resp = {}; 837 struct mlx5_ib_ucontext *context; 838 struct mlx5_uuar_info *uuari; 839 struct mlx5_uar *uars; 840 int gross_uuars; 841 int num_uars; 842 int ver; 843 int uuarn; 844 int err; 845 int i; 846 size_t reqlen; 847 848 if (!dev->ib_active) 849 return ERR_PTR(-EAGAIN); 850 851 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 852 return ERR_PTR(-EINVAL); 853 854 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 855 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 856 ver = 0; 857 else if (reqlen >= sizeof(struct mlx5_ib_alloc_ucontext_req_v2)) 858 ver = 2; 859 else 860 return ERR_PTR(-EINVAL); 861 862 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 863 if (err) 864 return ERR_PTR(err); 865 866 if (req.flags) 867 return ERR_PTR(-EINVAL); 868 869 if (req.total_num_uuars > MLX5_MAX_UUARS) 870 return ERR_PTR(-ENOMEM); 871 872 if (req.total_num_uuars == 0) 873 return ERR_PTR(-EINVAL); 874 875 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 876 return ERR_PTR(-EOPNOTSUPP); 877 878 if (reqlen > sizeof(req) && 879 !ib_is_udata_cleared(udata, sizeof(req), 880 reqlen - sizeof(req))) 881 return ERR_PTR(-EOPNOTSUPP); 882 883 req.total_num_uuars = ALIGN(req.total_num_uuars, 884 MLX5_NON_FP_BF_REGS_PER_PAGE); 885 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 886 return ERR_PTR(-EINVAL); 887 888 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 889 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 890 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 891 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 892 resp.cache_line_size = L1_CACHE_BYTES; 893 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 894 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 895 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 896 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 897 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 898 resp.cqe_version = min_t(__u8, 899 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 900 req.max_cqe_version); 901 resp.response_length = min(offsetof(typeof(resp), response_length) + 902 sizeof(resp.response_length), udata->outlen); 903 904 context = kzalloc(sizeof(*context), GFP_KERNEL); 905 if (!context) 906 return ERR_PTR(-ENOMEM); 907 908 uuari = &context->uuari; 909 mutex_init(&uuari->lock); 910 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 911 if (!uars) { 912 err = -ENOMEM; 913 goto out_ctx; 914 } 915 916 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 917 sizeof(*uuari->bitmap), 918 GFP_KERNEL); 919 if (!uuari->bitmap) { 920 err = -ENOMEM; 921 goto out_uar_ctx; 922 } 923 /* 924 * clear all fast path uuars 925 */ 926 for (i = 0; i < gross_uuars; i++) { 927 uuarn = i & 3; 928 if (uuarn == 2 || uuarn == 3) 929 set_bit(i, uuari->bitmap); 930 } 931 932 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 933 if (!uuari->count) { 934 err = -ENOMEM; 935 goto out_bitmap; 936 } 937 938 for (i = 0; i < num_uars; i++) { 939 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 940 if (err) 941 goto out_count; 942 } 943 944 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 945 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 946 #endif 947 948 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 949 err = mlx5_core_alloc_transport_domain(dev->mdev, 950 &context->tdn); 951 if (err) 952 goto out_uars; 953 } 954 955 INIT_LIST_HEAD(&context->db_page_list); 956 mutex_init(&context->db_page_mutex); 957 958 resp.tot_uuars = req.total_num_uuars; 959 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 960 961 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 962 resp.response_length += sizeof(resp.cqe_version); 963 964 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 965 resp.comp_mask |= 966 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 967 resp.hca_core_clock_offset = 968 offsetof(struct mlx5_init_seg, internal_timer_h) % 969 PAGE_SIZE; 970 resp.response_length += sizeof(resp.hca_core_clock_offset) + 971 sizeof(resp.reserved2) + 972 sizeof(resp.reserved3); 973 } 974 975 err = ib_copy_to_udata(udata, &resp, resp.response_length); 976 if (err) 977 goto out_td; 978 979 uuari->ver = ver; 980 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 981 uuari->uars = uars; 982 uuari->num_uars = num_uars; 983 context->cqe_version = resp.cqe_version; 984 985 return &context->ibucontext; 986 987 out_td: 988 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 989 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 990 991 out_uars: 992 for (i--; i >= 0; i--) 993 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 994 out_count: 995 kfree(uuari->count); 996 997 out_bitmap: 998 kfree(uuari->bitmap); 999 1000 out_uar_ctx: 1001 kfree(uars); 1002 1003 out_ctx: 1004 kfree(context); 1005 return ERR_PTR(err); 1006 } 1007 1008 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1009 { 1010 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1011 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1012 struct mlx5_uuar_info *uuari = &context->uuari; 1013 int i; 1014 1015 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1016 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1017 1018 for (i = 0; i < uuari->num_uars; i++) { 1019 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1020 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1021 } 1022 1023 kfree(uuari->count); 1024 kfree(uuari->bitmap); 1025 kfree(uuari->uars); 1026 kfree(context); 1027 1028 return 0; 1029 } 1030 1031 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1032 { 1033 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1034 } 1035 1036 static int get_command(unsigned long offset) 1037 { 1038 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1039 } 1040 1041 static int get_arg(unsigned long offset) 1042 { 1043 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1044 } 1045 1046 static int get_index(unsigned long offset) 1047 { 1048 return get_arg(offset); 1049 } 1050 1051 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1052 { 1053 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1054 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1055 struct mlx5_uuar_info *uuari = &context->uuari; 1056 unsigned long command; 1057 unsigned long idx; 1058 phys_addr_t pfn; 1059 1060 command = get_command(vma->vm_pgoff); 1061 switch (command) { 1062 case MLX5_IB_MMAP_REGULAR_PAGE: 1063 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1064 return -EINVAL; 1065 1066 idx = get_index(vma->vm_pgoff); 1067 if (idx >= uuari->num_uars) 1068 return -EINVAL; 1069 1070 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1071 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx, 1072 (unsigned long long)pfn); 1073 1074 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1075 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1076 PAGE_SIZE, vma->vm_page_prot)) 1077 return -EAGAIN; 1078 1079 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n", 1080 vma->vm_start, 1081 (unsigned long long)pfn << PAGE_SHIFT); 1082 break; 1083 1084 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1085 return -ENOSYS; 1086 1087 case MLX5_IB_MMAP_CORE_CLOCK: 1088 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1089 return -EINVAL; 1090 1091 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 1092 return -EPERM; 1093 1094 /* Don't expose to user-space information it shouldn't have */ 1095 if (PAGE_SIZE > 4096) 1096 return -EOPNOTSUPP; 1097 1098 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1099 pfn = (dev->mdev->iseg_base + 1100 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1101 PAGE_SHIFT; 1102 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1103 PAGE_SIZE, vma->vm_page_prot)) 1104 return -EAGAIN; 1105 1106 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1107 vma->vm_start, 1108 (unsigned long long)pfn << PAGE_SHIFT); 1109 break; 1110 1111 default: 1112 return -EINVAL; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1119 struct ib_ucontext *context, 1120 struct ib_udata *udata) 1121 { 1122 struct mlx5_ib_alloc_pd_resp resp; 1123 struct mlx5_ib_pd *pd; 1124 int err; 1125 1126 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1127 if (!pd) 1128 return ERR_PTR(-ENOMEM); 1129 1130 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1131 if (err) { 1132 kfree(pd); 1133 return ERR_PTR(err); 1134 } 1135 1136 if (context) { 1137 resp.pdn = pd->pdn; 1138 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1139 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1140 kfree(pd); 1141 return ERR_PTR(-EFAULT); 1142 } 1143 } 1144 1145 return &pd->ibpd; 1146 } 1147 1148 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1149 { 1150 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1151 struct mlx5_ib_pd *mpd = to_mpd(pd); 1152 1153 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1154 kfree(mpd); 1155 1156 return 0; 1157 } 1158 1159 static bool outer_header_zero(u32 *match_criteria) 1160 { 1161 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1162 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1163 outer_headers); 1164 1165 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1166 outer_headers_c + 1, 1167 size - 1); 1168 } 1169 1170 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1171 union ib_flow_spec *ib_spec) 1172 { 1173 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1174 outer_headers); 1175 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1176 outer_headers); 1177 switch (ib_spec->type) { 1178 case IB_FLOW_SPEC_ETH: 1179 if (ib_spec->size != sizeof(ib_spec->eth)) 1180 return -EINVAL; 1181 1182 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1183 dmac_47_16), 1184 ib_spec->eth.mask.dst_mac); 1185 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1186 dmac_47_16), 1187 ib_spec->eth.val.dst_mac); 1188 1189 if (ib_spec->eth.mask.vlan_tag) { 1190 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1191 vlan_tag, 1); 1192 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1193 vlan_tag, 1); 1194 1195 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1196 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1197 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1198 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1199 1200 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1201 first_cfi, 1202 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1203 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1204 first_cfi, 1205 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1206 1207 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1208 first_prio, 1209 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1210 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1211 first_prio, 1212 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1213 } 1214 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1215 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1216 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1217 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1218 break; 1219 case IB_FLOW_SPEC_IPV4: 1220 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1221 return -EINVAL; 1222 1223 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1224 ethertype, 0xffff); 1225 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1226 ethertype, ETH_P_IP); 1227 1228 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1229 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1230 &ib_spec->ipv4.mask.src_ip, 1231 sizeof(ib_spec->ipv4.mask.src_ip)); 1232 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1233 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1234 &ib_spec->ipv4.val.src_ip, 1235 sizeof(ib_spec->ipv4.val.src_ip)); 1236 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1237 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1238 &ib_spec->ipv4.mask.dst_ip, 1239 sizeof(ib_spec->ipv4.mask.dst_ip)); 1240 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1241 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1242 &ib_spec->ipv4.val.dst_ip, 1243 sizeof(ib_spec->ipv4.val.dst_ip)); 1244 break; 1245 case IB_FLOW_SPEC_TCP: 1246 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1247 return -EINVAL; 1248 1249 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1250 0xff); 1251 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1252 IPPROTO_TCP); 1253 1254 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1255 ntohs(ib_spec->tcp_udp.mask.src_port)); 1256 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1257 ntohs(ib_spec->tcp_udp.val.src_port)); 1258 1259 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1260 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1261 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1262 ntohs(ib_spec->tcp_udp.val.dst_port)); 1263 break; 1264 case IB_FLOW_SPEC_UDP: 1265 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1266 return -EINVAL; 1267 1268 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1269 0xff); 1270 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1271 IPPROTO_UDP); 1272 1273 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1274 ntohs(ib_spec->tcp_udp.mask.src_port)); 1275 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1276 ntohs(ib_spec->tcp_udp.val.src_port)); 1277 1278 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1279 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1280 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1281 ntohs(ib_spec->tcp_udp.val.dst_port)); 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 return 0; 1288 } 1289 1290 /* If a flow could catch both multicast and unicast packets, 1291 * it won't fall into the multicast flow steering table and this rule 1292 * could steal other multicast packets. 1293 */ 1294 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1295 { 1296 struct ib_flow_spec_eth *eth_spec; 1297 1298 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1299 ib_attr->size < sizeof(struct ib_flow_attr) + 1300 sizeof(struct ib_flow_spec_eth) || 1301 ib_attr->num_of_specs < 1) 1302 return false; 1303 1304 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1305 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1306 eth_spec->size != sizeof(*eth_spec)) 1307 return false; 1308 1309 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1310 is_multicast_ether_addr(eth_spec->val.dst_mac); 1311 } 1312 1313 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1314 { 1315 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1316 bool has_ipv4_spec = false; 1317 bool eth_type_ipv4 = true; 1318 unsigned int spec_index; 1319 1320 /* Validate that ethertype is correct */ 1321 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1322 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1323 ib_spec->eth.mask.ether_type) { 1324 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1325 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1326 eth_type_ipv4 = false; 1327 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1328 has_ipv4_spec = true; 1329 } 1330 ib_spec = (void *)ib_spec + ib_spec->size; 1331 } 1332 return !has_ipv4_spec || eth_type_ipv4; 1333 } 1334 1335 static void put_flow_table(struct mlx5_ib_dev *dev, 1336 struct mlx5_ib_flow_prio *prio, bool ft_added) 1337 { 1338 prio->refcount -= !!ft_added; 1339 if (!prio->refcount) { 1340 mlx5_destroy_flow_table(prio->flow_table); 1341 prio->flow_table = NULL; 1342 } 1343 } 1344 1345 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1346 { 1347 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1348 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1349 struct mlx5_ib_flow_handler, 1350 ibflow); 1351 struct mlx5_ib_flow_handler *iter, *tmp; 1352 1353 mutex_lock(&dev->flow_db.lock); 1354 1355 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1356 mlx5_del_flow_rule(iter->rule); 1357 list_del(&iter->list); 1358 kfree(iter); 1359 } 1360 1361 mlx5_del_flow_rule(handler->rule); 1362 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1363 mutex_unlock(&dev->flow_db.lock); 1364 1365 kfree(handler); 1366 1367 return 0; 1368 } 1369 1370 #define MLX5_FS_MAX_TYPES 10 1371 #define MLX5_FS_MAX_ENTRIES 32000UL 1372 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1373 struct ib_flow_attr *flow_attr) 1374 { 1375 struct mlx5_flow_namespace *ns = NULL; 1376 struct mlx5_ib_flow_prio *prio; 1377 struct mlx5_flow_table *ft; 1378 int num_entries; 1379 int num_groups; 1380 int priority; 1381 int err = 0; 1382 1383 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1384 if (flow_is_multicast_only(flow_attr)) 1385 priority = MLX5_IB_FLOW_MCAST_PRIO; 1386 else 1387 priority = flow_attr->priority; 1388 ns = mlx5_get_flow_namespace(dev->mdev, 1389 MLX5_FLOW_NAMESPACE_BYPASS); 1390 num_entries = MLX5_FS_MAX_ENTRIES; 1391 num_groups = MLX5_FS_MAX_TYPES; 1392 prio = &dev->flow_db.prios[priority]; 1393 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1394 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1395 ns = mlx5_get_flow_namespace(dev->mdev, 1396 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1397 build_leftovers_ft_param(&priority, 1398 &num_entries, 1399 &num_groups); 1400 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1401 } 1402 1403 if (!ns) 1404 return ERR_PTR(-ENOTSUPP); 1405 1406 ft = prio->flow_table; 1407 if (!ft) { 1408 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1409 num_entries, 1410 num_groups); 1411 1412 if (!IS_ERR(ft)) { 1413 prio->refcount = 0; 1414 prio->flow_table = ft; 1415 } else { 1416 err = PTR_ERR(ft); 1417 } 1418 } 1419 1420 return err ? ERR_PTR(err) : prio; 1421 } 1422 1423 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1424 struct mlx5_ib_flow_prio *ft_prio, 1425 struct ib_flow_attr *flow_attr, 1426 struct mlx5_flow_destination *dst) 1427 { 1428 struct mlx5_flow_table *ft = ft_prio->flow_table; 1429 struct mlx5_ib_flow_handler *handler; 1430 void *ib_flow = flow_attr + 1; 1431 u8 match_criteria_enable = 0; 1432 unsigned int spec_index; 1433 u32 *match_c; 1434 u32 *match_v; 1435 int err = 0; 1436 1437 if (!is_valid_attr(flow_attr)) 1438 return ERR_PTR(-EINVAL); 1439 1440 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1441 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1442 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1443 if (!handler || !match_c || !match_v) { 1444 err = -ENOMEM; 1445 goto free; 1446 } 1447 1448 INIT_LIST_HEAD(&handler->list); 1449 1450 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1451 err = parse_flow_attr(match_c, match_v, ib_flow); 1452 if (err < 0) 1453 goto free; 1454 1455 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1456 } 1457 1458 /* Outer header support only */ 1459 match_criteria_enable = (!outer_header_zero(match_c)) << 0; 1460 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, 1461 match_c, match_v, 1462 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, 1463 MLX5_FS_DEFAULT_FLOW_TAG, 1464 dst); 1465 1466 if (IS_ERR(handler->rule)) { 1467 err = PTR_ERR(handler->rule); 1468 goto free; 1469 } 1470 1471 handler->prio = ft_prio - dev->flow_db.prios; 1472 1473 ft_prio->flow_table = ft; 1474 free: 1475 if (err) 1476 kfree(handler); 1477 kfree(match_c); 1478 kfree(match_v); 1479 return err ? ERR_PTR(err) : handler; 1480 } 1481 1482 enum { 1483 LEFTOVERS_MC, 1484 LEFTOVERS_UC, 1485 }; 1486 1487 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1488 struct mlx5_ib_flow_prio *ft_prio, 1489 struct ib_flow_attr *flow_attr, 1490 struct mlx5_flow_destination *dst) 1491 { 1492 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1493 struct mlx5_ib_flow_handler *handler = NULL; 1494 1495 static struct { 1496 struct ib_flow_attr flow_attr; 1497 struct ib_flow_spec_eth eth_flow; 1498 } leftovers_specs[] = { 1499 [LEFTOVERS_MC] = { 1500 .flow_attr = { 1501 .num_of_specs = 1, 1502 .size = sizeof(leftovers_specs[0]) 1503 }, 1504 .eth_flow = { 1505 .type = IB_FLOW_SPEC_ETH, 1506 .size = sizeof(struct ib_flow_spec_eth), 1507 .mask = {.dst_mac = {0x1} }, 1508 .val = {.dst_mac = {0x1} } 1509 } 1510 }, 1511 [LEFTOVERS_UC] = { 1512 .flow_attr = { 1513 .num_of_specs = 1, 1514 .size = sizeof(leftovers_specs[0]) 1515 }, 1516 .eth_flow = { 1517 .type = IB_FLOW_SPEC_ETH, 1518 .size = sizeof(struct ib_flow_spec_eth), 1519 .mask = {.dst_mac = {0x1} }, 1520 .val = {.dst_mac = {} } 1521 } 1522 } 1523 }; 1524 1525 handler = create_flow_rule(dev, ft_prio, 1526 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1527 dst); 1528 if (!IS_ERR(handler) && 1529 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1530 handler_ucast = create_flow_rule(dev, ft_prio, 1531 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1532 dst); 1533 if (IS_ERR(handler_ucast)) { 1534 kfree(handler); 1535 handler = handler_ucast; 1536 } else { 1537 list_add(&handler_ucast->list, &handler->list); 1538 } 1539 } 1540 1541 return handler; 1542 } 1543 1544 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1545 struct ib_flow_attr *flow_attr, 1546 int domain) 1547 { 1548 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1549 struct mlx5_ib_flow_handler *handler = NULL; 1550 struct mlx5_flow_destination *dst = NULL; 1551 struct mlx5_ib_flow_prio *ft_prio; 1552 int err; 1553 1554 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1555 return ERR_PTR(-ENOSPC); 1556 1557 if (domain != IB_FLOW_DOMAIN_USER || 1558 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1559 flow_attr->flags) 1560 return ERR_PTR(-EINVAL); 1561 1562 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1563 if (!dst) 1564 return ERR_PTR(-ENOMEM); 1565 1566 mutex_lock(&dev->flow_db.lock); 1567 1568 ft_prio = get_flow_table(dev, flow_attr); 1569 if (IS_ERR(ft_prio)) { 1570 err = PTR_ERR(ft_prio); 1571 goto unlock; 1572 } 1573 1574 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1575 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; 1576 1577 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1578 handler = create_flow_rule(dev, ft_prio, flow_attr, 1579 dst); 1580 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1581 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1582 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1583 dst); 1584 } else { 1585 err = -EINVAL; 1586 goto destroy_ft; 1587 } 1588 1589 if (IS_ERR(handler)) { 1590 err = PTR_ERR(handler); 1591 handler = NULL; 1592 goto destroy_ft; 1593 } 1594 1595 ft_prio->refcount++; 1596 mutex_unlock(&dev->flow_db.lock); 1597 kfree(dst); 1598 1599 return &handler->ibflow; 1600 1601 destroy_ft: 1602 put_flow_table(dev, ft_prio, false); 1603 unlock: 1604 mutex_unlock(&dev->flow_db.lock); 1605 kfree(dst); 1606 kfree(handler); 1607 return ERR_PTR(err); 1608 } 1609 1610 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1611 { 1612 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1613 int err; 1614 1615 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1616 if (err) 1617 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1618 ibqp->qp_num, gid->raw); 1619 1620 return err; 1621 } 1622 1623 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1624 { 1625 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1626 int err; 1627 1628 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1629 if (err) 1630 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1631 ibqp->qp_num, gid->raw); 1632 1633 return err; 1634 } 1635 1636 static int init_node_data(struct mlx5_ib_dev *dev) 1637 { 1638 int err; 1639 1640 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1641 if (err) 1642 return err; 1643 1644 dev->mdev->rev_id = dev->mdev->pdev->revision; 1645 1646 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1647 } 1648 1649 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1650 char *buf) 1651 { 1652 struct mlx5_ib_dev *dev = 1653 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1654 1655 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1656 } 1657 1658 static ssize_t show_reg_pages(struct device *device, 1659 struct device_attribute *attr, char *buf) 1660 { 1661 struct mlx5_ib_dev *dev = 1662 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1663 1664 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1665 } 1666 1667 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1668 char *buf) 1669 { 1670 struct mlx5_ib_dev *dev = 1671 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1672 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1673 } 1674 1675 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr, 1676 char *buf) 1677 { 1678 struct mlx5_ib_dev *dev = 1679 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1680 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev), 1681 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 1682 } 1683 1684 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1685 char *buf) 1686 { 1687 struct mlx5_ib_dev *dev = 1688 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1689 return sprintf(buf, "%x\n", dev->mdev->rev_id); 1690 } 1691 1692 static ssize_t show_board(struct device *device, struct device_attribute *attr, 1693 char *buf) 1694 { 1695 struct mlx5_ib_dev *dev = 1696 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1697 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 1698 dev->mdev->board_id); 1699 } 1700 1701 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 1702 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 1703 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 1704 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 1705 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 1706 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 1707 1708 static struct device_attribute *mlx5_class_attributes[] = { 1709 &dev_attr_hw_rev, 1710 &dev_attr_fw_ver, 1711 &dev_attr_hca_type, 1712 &dev_attr_board_id, 1713 &dev_attr_fw_pages, 1714 &dev_attr_reg_pages, 1715 }; 1716 1717 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 1718 enum mlx5_dev_event event, unsigned long param) 1719 { 1720 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 1721 struct ib_event ibev; 1722 1723 u8 port = 0; 1724 1725 switch (event) { 1726 case MLX5_DEV_EVENT_SYS_ERROR: 1727 ibdev->ib_active = false; 1728 ibev.event = IB_EVENT_DEVICE_FATAL; 1729 break; 1730 1731 case MLX5_DEV_EVENT_PORT_UP: 1732 ibev.event = IB_EVENT_PORT_ACTIVE; 1733 port = (u8)param; 1734 break; 1735 1736 case MLX5_DEV_EVENT_PORT_DOWN: 1737 ibev.event = IB_EVENT_PORT_ERR; 1738 port = (u8)param; 1739 break; 1740 1741 case MLX5_DEV_EVENT_PORT_INITIALIZED: 1742 /* not used by ULPs */ 1743 return; 1744 1745 case MLX5_DEV_EVENT_LID_CHANGE: 1746 ibev.event = IB_EVENT_LID_CHANGE; 1747 port = (u8)param; 1748 break; 1749 1750 case MLX5_DEV_EVENT_PKEY_CHANGE: 1751 ibev.event = IB_EVENT_PKEY_CHANGE; 1752 port = (u8)param; 1753 break; 1754 1755 case MLX5_DEV_EVENT_GUID_CHANGE: 1756 ibev.event = IB_EVENT_GID_CHANGE; 1757 port = (u8)param; 1758 break; 1759 1760 case MLX5_DEV_EVENT_CLIENT_REREG: 1761 ibev.event = IB_EVENT_CLIENT_REREGISTER; 1762 port = (u8)param; 1763 break; 1764 } 1765 1766 ibev.device = &ibdev->ib_dev; 1767 ibev.element.port_num = port; 1768 1769 if (port < 1 || port > ibdev->num_ports) { 1770 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 1771 return; 1772 } 1773 1774 if (ibdev->ib_active) 1775 ib_dispatch_event(&ibev); 1776 } 1777 1778 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 1779 { 1780 int port; 1781 1782 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 1783 mlx5_query_ext_port_caps(dev, port); 1784 } 1785 1786 static int get_port_caps(struct mlx5_ib_dev *dev) 1787 { 1788 struct ib_device_attr *dprops = NULL; 1789 struct ib_port_attr *pprops = NULL; 1790 int err = -ENOMEM; 1791 int port; 1792 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 1793 1794 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 1795 if (!pprops) 1796 goto out; 1797 1798 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 1799 if (!dprops) 1800 goto out; 1801 1802 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 1803 if (err) { 1804 mlx5_ib_warn(dev, "query_device failed %d\n", err); 1805 goto out; 1806 } 1807 1808 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 1809 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 1810 if (err) { 1811 mlx5_ib_warn(dev, "query_port %d failed %d\n", 1812 port, err); 1813 break; 1814 } 1815 dev->mdev->port_caps[port - 1].pkey_table_len = 1816 dprops->max_pkeys; 1817 dev->mdev->port_caps[port - 1].gid_table_len = 1818 pprops->gid_tbl_len; 1819 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 1820 dprops->max_pkeys, pprops->gid_tbl_len); 1821 } 1822 1823 out: 1824 kfree(pprops); 1825 kfree(dprops); 1826 1827 return err; 1828 } 1829 1830 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 1831 { 1832 int err; 1833 1834 err = mlx5_mr_cache_cleanup(dev); 1835 if (err) 1836 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 1837 1838 mlx5_ib_destroy_qp(dev->umrc.qp); 1839 ib_destroy_cq(dev->umrc.cq); 1840 ib_dealloc_pd(dev->umrc.pd); 1841 } 1842 1843 enum { 1844 MAX_UMR_WR = 128, 1845 }; 1846 1847 static int create_umr_res(struct mlx5_ib_dev *dev) 1848 { 1849 struct ib_qp_init_attr *init_attr = NULL; 1850 struct ib_qp_attr *attr = NULL; 1851 struct ib_pd *pd; 1852 struct ib_cq *cq; 1853 struct ib_qp *qp; 1854 struct ib_cq_init_attr cq_attr = {}; 1855 int ret; 1856 1857 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 1858 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 1859 if (!attr || !init_attr) { 1860 ret = -ENOMEM; 1861 goto error_0; 1862 } 1863 1864 pd = ib_alloc_pd(&dev->ib_dev); 1865 if (IS_ERR(pd)) { 1866 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 1867 ret = PTR_ERR(pd); 1868 goto error_0; 1869 } 1870 1871 cq_attr.cqe = 128; 1872 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 1873 &cq_attr); 1874 if (IS_ERR(cq)) { 1875 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 1876 ret = PTR_ERR(cq); 1877 goto error_2; 1878 } 1879 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP); 1880 1881 init_attr->send_cq = cq; 1882 init_attr->recv_cq = cq; 1883 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 1884 init_attr->cap.max_send_wr = MAX_UMR_WR; 1885 init_attr->cap.max_send_sge = 1; 1886 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 1887 init_attr->port_num = 1; 1888 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 1889 if (IS_ERR(qp)) { 1890 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 1891 ret = PTR_ERR(qp); 1892 goto error_3; 1893 } 1894 qp->device = &dev->ib_dev; 1895 qp->real_qp = qp; 1896 qp->uobject = NULL; 1897 qp->qp_type = MLX5_IB_QPT_REG_UMR; 1898 1899 attr->qp_state = IB_QPS_INIT; 1900 attr->port_num = 1; 1901 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 1902 IB_QP_PORT, NULL); 1903 if (ret) { 1904 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 1905 goto error_4; 1906 } 1907 1908 memset(attr, 0, sizeof(*attr)); 1909 attr->qp_state = IB_QPS_RTR; 1910 attr->path_mtu = IB_MTU_256; 1911 1912 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 1913 if (ret) { 1914 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 1915 goto error_4; 1916 } 1917 1918 memset(attr, 0, sizeof(*attr)); 1919 attr->qp_state = IB_QPS_RTS; 1920 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 1921 if (ret) { 1922 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 1923 goto error_4; 1924 } 1925 1926 dev->umrc.qp = qp; 1927 dev->umrc.cq = cq; 1928 dev->umrc.pd = pd; 1929 1930 sema_init(&dev->umrc.sem, MAX_UMR_WR); 1931 ret = mlx5_mr_cache_init(dev); 1932 if (ret) { 1933 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 1934 goto error_4; 1935 } 1936 1937 kfree(attr); 1938 kfree(init_attr); 1939 1940 return 0; 1941 1942 error_4: 1943 mlx5_ib_destroy_qp(qp); 1944 1945 error_3: 1946 ib_destroy_cq(cq); 1947 1948 error_2: 1949 ib_dealloc_pd(pd); 1950 1951 error_0: 1952 kfree(attr); 1953 kfree(init_attr); 1954 return ret; 1955 } 1956 1957 static int create_dev_resources(struct mlx5_ib_resources *devr) 1958 { 1959 struct ib_srq_init_attr attr; 1960 struct mlx5_ib_dev *dev; 1961 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 1962 int ret = 0; 1963 1964 dev = container_of(devr, struct mlx5_ib_dev, devr); 1965 1966 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 1967 if (IS_ERR(devr->p0)) { 1968 ret = PTR_ERR(devr->p0); 1969 goto error0; 1970 } 1971 devr->p0->device = &dev->ib_dev; 1972 devr->p0->uobject = NULL; 1973 atomic_set(&devr->p0->usecnt, 0); 1974 1975 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 1976 if (IS_ERR(devr->c0)) { 1977 ret = PTR_ERR(devr->c0); 1978 goto error1; 1979 } 1980 devr->c0->device = &dev->ib_dev; 1981 devr->c0->uobject = NULL; 1982 devr->c0->comp_handler = NULL; 1983 devr->c0->event_handler = NULL; 1984 devr->c0->cq_context = NULL; 1985 atomic_set(&devr->c0->usecnt, 0); 1986 1987 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 1988 if (IS_ERR(devr->x0)) { 1989 ret = PTR_ERR(devr->x0); 1990 goto error2; 1991 } 1992 devr->x0->device = &dev->ib_dev; 1993 devr->x0->inode = NULL; 1994 atomic_set(&devr->x0->usecnt, 0); 1995 mutex_init(&devr->x0->tgt_qp_mutex); 1996 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 1997 1998 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 1999 if (IS_ERR(devr->x1)) { 2000 ret = PTR_ERR(devr->x1); 2001 goto error3; 2002 } 2003 devr->x1->device = &dev->ib_dev; 2004 devr->x1->inode = NULL; 2005 atomic_set(&devr->x1->usecnt, 0); 2006 mutex_init(&devr->x1->tgt_qp_mutex); 2007 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2008 2009 memset(&attr, 0, sizeof(attr)); 2010 attr.attr.max_sge = 1; 2011 attr.attr.max_wr = 1; 2012 attr.srq_type = IB_SRQT_XRC; 2013 attr.ext.xrc.cq = devr->c0; 2014 attr.ext.xrc.xrcd = devr->x0; 2015 2016 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2017 if (IS_ERR(devr->s0)) { 2018 ret = PTR_ERR(devr->s0); 2019 goto error4; 2020 } 2021 devr->s0->device = &dev->ib_dev; 2022 devr->s0->pd = devr->p0; 2023 devr->s0->uobject = NULL; 2024 devr->s0->event_handler = NULL; 2025 devr->s0->srq_context = NULL; 2026 devr->s0->srq_type = IB_SRQT_XRC; 2027 devr->s0->ext.xrc.xrcd = devr->x0; 2028 devr->s0->ext.xrc.cq = devr->c0; 2029 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2030 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2031 atomic_inc(&devr->p0->usecnt); 2032 atomic_set(&devr->s0->usecnt, 0); 2033 2034 memset(&attr, 0, sizeof(attr)); 2035 attr.attr.max_sge = 1; 2036 attr.attr.max_wr = 1; 2037 attr.srq_type = IB_SRQT_BASIC; 2038 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2039 if (IS_ERR(devr->s1)) { 2040 ret = PTR_ERR(devr->s1); 2041 goto error5; 2042 } 2043 devr->s1->device = &dev->ib_dev; 2044 devr->s1->pd = devr->p0; 2045 devr->s1->uobject = NULL; 2046 devr->s1->event_handler = NULL; 2047 devr->s1->srq_context = NULL; 2048 devr->s1->srq_type = IB_SRQT_BASIC; 2049 devr->s1->ext.xrc.cq = devr->c0; 2050 atomic_inc(&devr->p0->usecnt); 2051 atomic_set(&devr->s0->usecnt, 0); 2052 2053 return 0; 2054 2055 error5: 2056 mlx5_ib_destroy_srq(devr->s0); 2057 error4: 2058 mlx5_ib_dealloc_xrcd(devr->x1); 2059 error3: 2060 mlx5_ib_dealloc_xrcd(devr->x0); 2061 error2: 2062 mlx5_ib_destroy_cq(devr->c0); 2063 error1: 2064 mlx5_ib_dealloc_pd(devr->p0); 2065 error0: 2066 return ret; 2067 } 2068 2069 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2070 { 2071 mlx5_ib_destroy_srq(devr->s1); 2072 mlx5_ib_destroy_srq(devr->s0); 2073 mlx5_ib_dealloc_xrcd(devr->x0); 2074 mlx5_ib_dealloc_xrcd(devr->x1); 2075 mlx5_ib_destroy_cq(devr->c0); 2076 mlx5_ib_dealloc_pd(devr->p0); 2077 } 2078 2079 static u32 get_core_cap_flags(struct ib_device *ibdev) 2080 { 2081 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2082 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2083 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2084 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2085 u32 ret = 0; 2086 2087 if (ll == IB_LINK_LAYER_INFINIBAND) 2088 return RDMA_CORE_PORT_IBA_IB; 2089 2090 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2091 return 0; 2092 2093 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2094 return 0; 2095 2096 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2097 ret |= RDMA_CORE_PORT_IBA_ROCE; 2098 2099 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2100 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2101 2102 return ret; 2103 } 2104 2105 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2106 struct ib_port_immutable *immutable) 2107 { 2108 struct ib_port_attr attr; 2109 int err; 2110 2111 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2112 if (err) 2113 return err; 2114 2115 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2116 immutable->gid_tbl_len = attr.gid_tbl_len; 2117 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2118 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2119 2120 return 0; 2121 } 2122 2123 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2124 { 2125 int err; 2126 2127 dev->roce.nb.notifier_call = mlx5_netdev_event; 2128 err = register_netdevice_notifier(&dev->roce.nb); 2129 if (err) 2130 return err; 2131 2132 err = mlx5_nic_vport_enable_roce(dev->mdev); 2133 if (err) 2134 goto err_unregister_netdevice_notifier; 2135 2136 return 0; 2137 2138 err_unregister_netdevice_notifier: 2139 unregister_netdevice_notifier(&dev->roce.nb); 2140 return err; 2141 } 2142 2143 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2144 { 2145 mlx5_nic_vport_disable_roce(dev->mdev); 2146 unregister_netdevice_notifier(&dev->roce.nb); 2147 } 2148 2149 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2150 { 2151 struct mlx5_ib_dev *dev; 2152 enum rdma_link_layer ll; 2153 int port_type_cap; 2154 int err; 2155 int i; 2156 2157 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2158 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2159 2160 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2161 return NULL; 2162 2163 printk_once(KERN_INFO "%s", mlx5_version); 2164 2165 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2166 if (!dev) 2167 return NULL; 2168 2169 dev->mdev = mdev; 2170 2171 rwlock_init(&dev->roce.netdev_lock); 2172 err = get_port_caps(dev); 2173 if (err) 2174 goto err_dealloc; 2175 2176 if (mlx5_use_mad_ifc(dev)) 2177 get_ext_port_caps(dev); 2178 2179 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2180 2181 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2182 dev->ib_dev.owner = THIS_MODULE; 2183 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2184 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2185 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2186 dev->ib_dev.phys_port_cnt = dev->num_ports; 2187 dev->ib_dev.num_comp_vectors = 2188 dev->mdev->priv.eq_table.num_comp_vectors; 2189 dev->ib_dev.dma_device = &mdev->pdev->dev; 2190 2191 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2192 dev->ib_dev.uverbs_cmd_mask = 2193 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2194 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2195 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2196 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2197 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2198 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2199 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2200 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2201 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2202 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2203 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2204 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2205 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2206 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2207 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2208 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2209 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2210 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2211 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2212 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2213 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2214 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2215 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2216 dev->ib_dev.uverbs_ex_cmd_mask = 2217 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE); 2218 2219 dev->ib_dev.query_device = mlx5_ib_query_device; 2220 dev->ib_dev.query_port = mlx5_ib_query_port; 2221 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2222 if (ll == IB_LINK_LAYER_ETHERNET) 2223 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2224 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2225 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2226 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2227 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2228 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2229 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2230 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2231 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2232 dev->ib_dev.mmap = mlx5_ib_mmap; 2233 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2234 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2235 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2236 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2237 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2238 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2239 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2240 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2241 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2242 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2243 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2244 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2245 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2246 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2247 dev->ib_dev.post_send = mlx5_ib_post_send; 2248 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2249 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2250 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2251 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2252 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2253 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2254 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2255 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2256 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2257 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2258 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2259 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2260 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2261 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2262 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2263 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2264 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2265 2266 mlx5_ib_internal_fill_odp_caps(dev); 2267 2268 if (MLX5_CAP_GEN(mdev, xrc)) { 2269 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2270 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2271 dev->ib_dev.uverbs_cmd_mask |= 2272 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2273 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2274 } 2275 2276 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2277 IB_LINK_LAYER_ETHERNET) { 2278 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2279 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2280 dev->ib_dev.uverbs_ex_cmd_mask |= 2281 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2282 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2283 } 2284 err = init_node_data(dev); 2285 if (err) 2286 goto err_dealloc; 2287 2288 mutex_init(&dev->flow_db.lock); 2289 mutex_init(&dev->cap_mask_mutex); 2290 2291 if (ll == IB_LINK_LAYER_ETHERNET) { 2292 err = mlx5_enable_roce(dev); 2293 if (err) 2294 goto err_dealloc; 2295 } 2296 2297 err = create_dev_resources(&dev->devr); 2298 if (err) 2299 goto err_disable_roce; 2300 2301 err = mlx5_ib_odp_init_one(dev); 2302 if (err) 2303 goto err_rsrc; 2304 2305 err = ib_register_device(&dev->ib_dev, NULL); 2306 if (err) 2307 goto err_odp; 2308 2309 err = create_umr_res(dev); 2310 if (err) 2311 goto err_dev; 2312 2313 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2314 err = device_create_file(&dev->ib_dev.dev, 2315 mlx5_class_attributes[i]); 2316 if (err) 2317 goto err_umrc; 2318 } 2319 2320 dev->ib_active = true; 2321 2322 return dev; 2323 2324 err_umrc: 2325 destroy_umrc_res(dev); 2326 2327 err_dev: 2328 ib_unregister_device(&dev->ib_dev); 2329 2330 err_odp: 2331 mlx5_ib_odp_remove_one(dev); 2332 2333 err_rsrc: 2334 destroy_dev_resources(&dev->devr); 2335 2336 err_disable_roce: 2337 if (ll == IB_LINK_LAYER_ETHERNET) 2338 mlx5_disable_roce(dev); 2339 2340 err_dealloc: 2341 ib_dealloc_device((struct ib_device *)dev); 2342 2343 return NULL; 2344 } 2345 2346 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2347 { 2348 struct mlx5_ib_dev *dev = context; 2349 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2350 2351 ib_unregister_device(&dev->ib_dev); 2352 destroy_umrc_res(dev); 2353 mlx5_ib_odp_remove_one(dev); 2354 destroy_dev_resources(&dev->devr); 2355 if (ll == IB_LINK_LAYER_ETHERNET) 2356 mlx5_disable_roce(dev); 2357 ib_dealloc_device(&dev->ib_dev); 2358 } 2359 2360 static struct mlx5_interface mlx5_ib_interface = { 2361 .add = mlx5_ib_add, 2362 .remove = mlx5_ib_remove, 2363 .event = mlx5_ib_event, 2364 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2365 }; 2366 2367 static int __init mlx5_ib_init(void) 2368 { 2369 int err; 2370 2371 if (deprecated_prof_sel != 2) 2372 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2373 2374 err = mlx5_ib_odp_init(); 2375 if (err) 2376 return err; 2377 2378 err = mlx5_register_interface(&mlx5_ib_interface); 2379 if (err) 2380 goto clean_odp; 2381 2382 return err; 2383 2384 clean_odp: 2385 mlx5_ib_odp_cleanup(); 2386 return err; 2387 } 2388 2389 static void __exit mlx5_ib_cleanup(void) 2390 { 2391 mlx5_unregister_interface(&mlx5_ib_interface); 2392 mlx5_ib_odp_cleanup(); 2393 } 2394 2395 module_init(mlx5_ib_init); 2396 module_exit(mlx5_ib_cleanup); 2397