1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem_odp.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include "umr.h" 45 #include <rdma/uverbs_std_types.h> 46 #include <rdma/uverbs_ioctl.h> 47 #include <rdma/mlx5_user_ioctl_verbs.h> 48 #include <rdma/mlx5_user_ioctl_cmds.h> 49 50 #define UVERBS_MODULE_NAME mlx5_ib 51 #include <rdma/uverbs_named_ioctl.h> 52 53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 54 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 57 struct mlx5_ib_event_work { 58 struct work_struct work; 59 union { 60 struct mlx5_ib_dev *dev; 61 struct mlx5_ib_multiport_info *mpi; 62 }; 63 bool is_slave; 64 unsigned int event; 65 void *param; 66 }; 67 68 enum { 69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 70 }; 71 72 static struct workqueue_struct *mlx5_ib_event_wq; 73 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 74 static LIST_HEAD(mlx5_ib_dev_list); 75 /* 76 * This mutex should be held when accessing either of the above lists 77 */ 78 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 79 80 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 81 { 82 struct mlx5_ib_dev *dev; 83 84 mutex_lock(&mlx5_ib_multiport_mutex); 85 dev = mpi->ibdev; 86 mutex_unlock(&mlx5_ib_multiport_mutex); 87 return dev; 88 } 89 90 static enum rdma_link_layer 91 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 92 { 93 switch (port_type_cap) { 94 case MLX5_CAP_PORT_TYPE_IB: 95 return IB_LINK_LAYER_INFINIBAND; 96 case MLX5_CAP_PORT_TYPE_ETH: 97 return IB_LINK_LAYER_ETHERNET; 98 default: 99 return IB_LINK_LAYER_UNSPECIFIED; 100 } 101 } 102 103 static enum rdma_link_layer 104 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 105 { 106 struct mlx5_ib_dev *dev = to_mdev(device); 107 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 108 109 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 110 } 111 112 static int get_port_state(struct ib_device *ibdev, 113 u32 port_num, 114 enum ib_port_state *state) 115 { 116 struct ib_port_attr attr; 117 int ret; 118 119 memset(&attr, 0, sizeof(attr)); 120 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 121 if (!ret) 122 *state = attr.state; 123 return ret; 124 } 125 126 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 127 struct net_device *ndev, 128 struct net_device *upper, 129 u32 *port_num) 130 { 131 struct net_device *rep_ndev; 132 struct mlx5_ib_port *port; 133 int i; 134 135 for (i = 0; i < dev->num_ports; i++) { 136 port = &dev->port[i]; 137 if (!port->rep) 138 continue; 139 140 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 141 *port_num = i + 1; 142 return &port->roce; 143 } 144 145 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 146 continue; 147 148 read_lock(&port->roce.netdev_lock); 149 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 150 port->rep->vport); 151 if (rep_ndev == ndev) { 152 read_unlock(&port->roce.netdev_lock); 153 *port_num = i + 1; 154 return &port->roce; 155 } 156 read_unlock(&port->roce.netdev_lock); 157 } 158 159 return NULL; 160 } 161 162 static int mlx5_netdev_event(struct notifier_block *this, 163 unsigned long event, void *ptr) 164 { 165 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 166 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 167 u32 port_num = roce->native_port_num; 168 struct mlx5_core_dev *mdev; 169 struct mlx5_ib_dev *ibdev; 170 171 ibdev = roce->dev; 172 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 173 if (!mdev) 174 return NOTIFY_DONE; 175 176 switch (event) { 177 case NETDEV_REGISTER: 178 /* Should already be registered during the load */ 179 if (ibdev->is_rep) 180 break; 181 write_lock(&roce->netdev_lock); 182 if (ndev->dev.parent == mdev->device) 183 roce->netdev = ndev; 184 write_unlock(&roce->netdev_lock); 185 break; 186 187 case NETDEV_UNREGISTER: 188 /* In case of reps, ib device goes away before the netdevs */ 189 write_lock(&roce->netdev_lock); 190 if (roce->netdev == ndev) 191 roce->netdev = NULL; 192 write_unlock(&roce->netdev_lock); 193 break; 194 195 case NETDEV_CHANGE: 196 case NETDEV_UP: 197 case NETDEV_DOWN: { 198 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 199 struct net_device *upper = NULL; 200 201 if (lag_ndev) { 202 upper = netdev_master_upper_dev_get(lag_ndev); 203 dev_put(lag_ndev); 204 } 205 206 if (ibdev->is_rep) 207 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 208 if (!roce) 209 return NOTIFY_DONE; 210 if ((upper == ndev || 211 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 212 ibdev->ib_active) { 213 struct ib_event ibev = { }; 214 enum ib_port_state port_state; 215 216 if (get_port_state(&ibdev->ib_dev, port_num, 217 &port_state)) 218 goto done; 219 220 if (roce->last_port_state == port_state) 221 goto done; 222 223 roce->last_port_state = port_state; 224 ibev.device = &ibdev->ib_dev; 225 if (port_state == IB_PORT_DOWN) 226 ibev.event = IB_EVENT_PORT_ERR; 227 else if (port_state == IB_PORT_ACTIVE) 228 ibev.event = IB_EVENT_PORT_ACTIVE; 229 else 230 goto done; 231 232 ibev.element.port_num = port_num; 233 ib_dispatch_event(&ibev); 234 } 235 break; 236 } 237 238 default: 239 break; 240 } 241 done: 242 mlx5_ib_put_native_port_mdev(ibdev, port_num); 243 return NOTIFY_DONE; 244 } 245 246 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 247 u32 port_num) 248 { 249 struct mlx5_ib_dev *ibdev = to_mdev(device); 250 struct net_device *ndev; 251 struct mlx5_core_dev *mdev; 252 253 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 254 if (!mdev) 255 return NULL; 256 257 ndev = mlx5_lag_get_roce_netdev(mdev); 258 if (ndev) 259 goto out; 260 261 /* Ensure ndev does not disappear before we invoke dev_hold() 262 */ 263 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 264 ndev = ibdev->port[port_num - 1].roce.netdev; 265 if (ndev) 266 dev_hold(ndev); 267 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 268 269 out: 270 mlx5_ib_put_native_port_mdev(ibdev, port_num); 271 return ndev; 272 } 273 274 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 275 u32 ib_port_num, 276 u32 *native_port_num) 277 { 278 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 279 ib_port_num); 280 struct mlx5_core_dev *mdev = NULL; 281 struct mlx5_ib_multiport_info *mpi; 282 struct mlx5_ib_port *port; 283 284 if (!mlx5_core_mp_enabled(ibdev->mdev) || 285 ll != IB_LINK_LAYER_ETHERNET) { 286 if (native_port_num) 287 *native_port_num = ib_port_num; 288 return ibdev->mdev; 289 } 290 291 if (native_port_num) 292 *native_port_num = 1; 293 294 port = &ibdev->port[ib_port_num - 1]; 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 297 if (mpi && !mpi->unaffiliate) { 298 mdev = mpi->mdev; 299 /* If it's the master no need to refcount, it'll exist 300 * as long as the ib_dev exists. 301 */ 302 if (!mpi->is_master) 303 mpi->mdev_refcnt++; 304 } 305 spin_unlock(&port->mp.mpi_lock); 306 307 return mdev; 308 } 309 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 311 { 312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 313 port_num); 314 struct mlx5_ib_multiport_info *mpi; 315 struct mlx5_ib_port *port; 316 317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 318 return; 319 320 port = &ibdev->port[port_num - 1]; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[port_num - 1].mp.mpi; 324 if (mpi->is_master) 325 goto out; 326 327 mpi->mdev_refcnt--; 328 if (mpi->unaffiliate) 329 complete(&mpi->unref_comp); 330 out: 331 spin_unlock(&port->mp.mpi_lock); 332 } 333 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 335 u16 *active_speed, u8 *active_width) 336 { 337 switch (eth_proto_oper) { 338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_SDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 352 *active_width = IB_WIDTH_1X; 353 *active_speed = IB_SPEED_QDR; 354 break; 355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 358 *active_width = IB_WIDTH_1X; 359 *active_speed = IB_SPEED_EDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_QDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_HDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_FDR; 377 break; 378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 382 *active_width = IB_WIDTH_4X; 383 *active_speed = IB_SPEED_EDR; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 393 u8 *active_width) 394 { 395 switch (eth_proto_oper) { 396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_SDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_DDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 406 *active_width = IB_WIDTH_1X; 407 *active_speed = IB_SPEED_QDR; 408 break; 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_EDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 418 *active_width = IB_WIDTH_2X; 419 *active_speed = IB_SPEED_EDR; 420 break; 421 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 422 *active_width = IB_WIDTH_1X; 423 *active_speed = IB_SPEED_HDR; 424 break; 425 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 426 *active_width = IB_WIDTH_4X; 427 *active_speed = IB_SPEED_EDR; 428 break; 429 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 430 *active_width = IB_WIDTH_2X; 431 *active_speed = IB_SPEED_HDR; 432 break; 433 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 434 *active_width = IB_WIDTH_1X; 435 *active_speed = IB_SPEED_NDR; 436 break; 437 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 438 *active_width = IB_WIDTH_4X; 439 *active_speed = IB_SPEED_HDR; 440 break; 441 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 442 *active_width = IB_WIDTH_2X; 443 *active_speed = IB_SPEED_NDR; 444 break; 445 case MLX5E_PROT_MASK(MLX5E_400GAUI_8): 446 *active_width = IB_WIDTH_8X; 447 *active_speed = IB_SPEED_HDR; 448 break; 449 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 450 *active_width = IB_WIDTH_4X; 451 *active_speed = IB_SPEED_NDR; 452 break; 453 default: 454 return -EINVAL; 455 } 456 457 return 0; 458 } 459 460 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 461 u8 *active_width, bool ext) 462 { 463 return ext ? 464 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 465 active_width) : 466 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 467 active_width); 468 } 469 470 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 471 struct ib_port_attr *props) 472 { 473 struct mlx5_ib_dev *dev = to_mdev(device); 474 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 475 struct mlx5_core_dev *mdev; 476 struct net_device *ndev, *upper; 477 enum ib_mtu ndev_ib_mtu; 478 bool put_mdev = true; 479 u32 eth_prot_oper; 480 u32 mdev_port_num; 481 bool ext; 482 int err; 483 484 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 485 if (!mdev) { 486 /* This means the port isn't affiliated yet. Get the 487 * info for the master port instead. 488 */ 489 put_mdev = false; 490 mdev = dev->mdev; 491 mdev_port_num = 1; 492 port_num = 1; 493 } 494 495 /* Possible bad flows are checked before filling out props so in case 496 * of an error it will still be zeroed out. 497 * Use native port in case of reps 498 */ 499 if (dev->is_rep) 500 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 501 1); 502 else 503 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 504 mdev_port_num); 505 if (err) 506 goto out; 507 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 508 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 509 510 props->active_width = IB_WIDTH_4X; 511 props->active_speed = IB_SPEED_QDR; 512 513 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 514 &props->active_width, ext); 515 516 if (!dev->is_rep && dev->mdev->roce.roce_en) { 517 u16 qkey_viol_cntr; 518 519 props->port_cap_flags |= IB_PORT_CM_SUP; 520 props->ip_gids = true; 521 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 522 roce_address_table_size); 523 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 524 props->qkey_viol_cntr = qkey_viol_cntr; 525 } 526 props->max_mtu = IB_MTU_4096; 527 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 528 props->pkey_tbl_len = 1; 529 props->state = IB_PORT_DOWN; 530 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 531 532 /* If this is a stub query for an unaffiliated port stop here */ 533 if (!put_mdev) 534 goto out; 535 536 ndev = mlx5_ib_get_netdev(device, port_num); 537 if (!ndev) 538 goto out; 539 540 if (dev->lag_active) { 541 rcu_read_lock(); 542 upper = netdev_master_upper_dev_get_rcu(ndev); 543 if (upper) { 544 dev_put(ndev); 545 ndev = upper; 546 dev_hold(ndev); 547 } 548 rcu_read_unlock(); 549 } 550 551 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 552 props->state = IB_PORT_ACTIVE; 553 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 554 } 555 556 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 557 558 dev_put(ndev); 559 560 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 561 out: 562 if (put_mdev) 563 mlx5_ib_put_native_port_mdev(dev, port_num); 564 return err; 565 } 566 567 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 568 unsigned int index, const union ib_gid *gid, 569 const struct ib_gid_attr *attr) 570 { 571 enum ib_gid_type gid_type; 572 u16 vlan_id = 0xffff; 573 u8 roce_version = 0; 574 u8 roce_l3_type = 0; 575 u8 mac[ETH_ALEN]; 576 int ret; 577 578 gid_type = attr->gid_type; 579 if (gid) { 580 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 581 if (ret) 582 return ret; 583 } 584 585 switch (gid_type) { 586 case IB_GID_TYPE_ROCE: 587 roce_version = MLX5_ROCE_VERSION_1; 588 break; 589 case IB_GID_TYPE_ROCE_UDP_ENCAP: 590 roce_version = MLX5_ROCE_VERSION_2; 591 if (gid && ipv6_addr_v4mapped((void *)gid)) 592 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 593 else 594 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 595 break; 596 597 default: 598 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 599 } 600 601 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 602 roce_l3_type, gid->raw, mac, 603 vlan_id < VLAN_CFI_MASK, vlan_id, 604 port_num); 605 } 606 607 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 608 __always_unused void **context) 609 { 610 return set_roce_addr(to_mdev(attr->device), attr->port_num, 611 attr->index, &attr->gid, attr); 612 } 613 614 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 615 __always_unused void **context) 616 { 617 return set_roce_addr(to_mdev(attr->device), attr->port_num, 618 attr->index, NULL, attr); 619 } 620 621 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 622 const struct ib_gid_attr *attr) 623 { 624 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 625 return 0; 626 627 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 628 } 629 630 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 631 { 632 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 633 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 634 return 0; 635 } 636 637 enum { 638 MLX5_VPORT_ACCESS_METHOD_MAD, 639 MLX5_VPORT_ACCESS_METHOD_HCA, 640 MLX5_VPORT_ACCESS_METHOD_NIC, 641 }; 642 643 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 644 { 645 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 646 return MLX5_VPORT_ACCESS_METHOD_MAD; 647 648 if (mlx5_ib_port_link_layer(ibdev, 1) == 649 IB_LINK_LAYER_ETHERNET) 650 return MLX5_VPORT_ACCESS_METHOD_NIC; 651 652 return MLX5_VPORT_ACCESS_METHOD_HCA; 653 } 654 655 static void get_atomic_caps(struct mlx5_ib_dev *dev, 656 u8 atomic_size_qp, 657 struct ib_device_attr *props) 658 { 659 u8 tmp; 660 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 661 u8 atomic_req_8B_endianness_mode = 662 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 663 664 /* Check if HW supports 8 bytes standard atomic operations and capable 665 * of host endianness respond 666 */ 667 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 668 if (((atomic_operations & tmp) == tmp) && 669 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 670 (atomic_req_8B_endianness_mode)) { 671 props->atomic_cap = IB_ATOMIC_HCA; 672 } else { 673 props->atomic_cap = IB_ATOMIC_NONE; 674 } 675 } 676 677 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 678 struct ib_device_attr *props) 679 { 680 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 681 682 get_atomic_caps(dev, atomic_size_qp, props); 683 } 684 685 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 686 __be64 *sys_image_guid) 687 { 688 struct mlx5_ib_dev *dev = to_mdev(ibdev); 689 struct mlx5_core_dev *mdev = dev->mdev; 690 u64 tmp; 691 int err; 692 693 switch (mlx5_get_vport_access_method(ibdev)) { 694 case MLX5_VPORT_ACCESS_METHOD_MAD: 695 return mlx5_query_mad_ifc_system_image_guid(ibdev, 696 sys_image_guid); 697 698 case MLX5_VPORT_ACCESS_METHOD_HCA: 699 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 700 break; 701 702 case MLX5_VPORT_ACCESS_METHOD_NIC: 703 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 704 break; 705 706 default: 707 return -EINVAL; 708 } 709 710 if (!err) 711 *sys_image_guid = cpu_to_be64(tmp); 712 713 return err; 714 715 } 716 717 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 718 u16 *max_pkeys) 719 { 720 struct mlx5_ib_dev *dev = to_mdev(ibdev); 721 struct mlx5_core_dev *mdev = dev->mdev; 722 723 switch (mlx5_get_vport_access_method(ibdev)) { 724 case MLX5_VPORT_ACCESS_METHOD_MAD: 725 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 726 727 case MLX5_VPORT_ACCESS_METHOD_HCA: 728 case MLX5_VPORT_ACCESS_METHOD_NIC: 729 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 730 pkey_table_size)); 731 return 0; 732 733 default: 734 return -EINVAL; 735 } 736 } 737 738 static int mlx5_query_vendor_id(struct ib_device *ibdev, 739 u32 *vendor_id) 740 { 741 struct mlx5_ib_dev *dev = to_mdev(ibdev); 742 743 switch (mlx5_get_vport_access_method(ibdev)) { 744 case MLX5_VPORT_ACCESS_METHOD_MAD: 745 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 746 747 case MLX5_VPORT_ACCESS_METHOD_HCA: 748 case MLX5_VPORT_ACCESS_METHOD_NIC: 749 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 750 751 default: 752 return -EINVAL; 753 } 754 } 755 756 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 757 __be64 *node_guid) 758 { 759 u64 tmp; 760 int err; 761 762 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 763 case MLX5_VPORT_ACCESS_METHOD_MAD: 764 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 765 766 case MLX5_VPORT_ACCESS_METHOD_HCA: 767 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 768 break; 769 770 case MLX5_VPORT_ACCESS_METHOD_NIC: 771 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 772 break; 773 774 default: 775 return -EINVAL; 776 } 777 778 if (!err) 779 *node_guid = cpu_to_be64(tmp); 780 781 return err; 782 } 783 784 struct mlx5_reg_node_desc { 785 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 786 }; 787 788 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 789 { 790 struct mlx5_reg_node_desc in; 791 792 if (mlx5_use_mad_ifc(dev)) 793 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 794 795 memset(&in, 0, sizeof(in)); 796 797 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 798 sizeof(struct mlx5_reg_node_desc), 799 MLX5_REG_NODE_DESC, 0, 0); 800 } 801 802 static int mlx5_ib_query_device(struct ib_device *ibdev, 803 struct ib_device_attr *props, 804 struct ib_udata *uhw) 805 { 806 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 807 struct mlx5_ib_dev *dev = to_mdev(ibdev); 808 struct mlx5_core_dev *mdev = dev->mdev; 809 int err = -ENOMEM; 810 int max_sq_desc; 811 int max_rq_sg; 812 int max_sq_sg; 813 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 814 bool raw_support = !mlx5_core_mp_enabled(mdev); 815 struct mlx5_ib_query_device_resp resp = {}; 816 size_t resp_len; 817 u64 max_tso; 818 819 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 820 if (uhw_outlen && uhw_outlen < resp_len) 821 return -EINVAL; 822 823 resp.response_length = resp_len; 824 825 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 826 return -EINVAL; 827 828 memset(props, 0, sizeof(*props)); 829 err = mlx5_query_system_image_guid(ibdev, 830 &props->sys_image_guid); 831 if (err) 832 return err; 833 834 props->max_pkeys = dev->pkey_table_len; 835 836 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 837 if (err) 838 return err; 839 840 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 841 (fw_rev_min(dev->mdev) << 16) | 842 fw_rev_sub(dev->mdev); 843 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 844 IB_DEVICE_PORT_ACTIVE_EVENT | 845 IB_DEVICE_SYS_IMAGE_GUID | 846 IB_DEVICE_RC_RNR_NAK_GEN; 847 848 if (MLX5_CAP_GEN(mdev, pkv)) 849 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 850 if (MLX5_CAP_GEN(mdev, qkv)) 851 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 852 if (MLX5_CAP_GEN(mdev, apm)) 853 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 854 if (MLX5_CAP_GEN(mdev, xrc)) 855 props->device_cap_flags |= IB_DEVICE_XRC; 856 if (MLX5_CAP_GEN(mdev, imaicl)) { 857 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 858 IB_DEVICE_MEM_WINDOW_TYPE_2B; 859 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 860 /* We support 'Gappy' memory registration too */ 861 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 862 } 863 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 864 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 865 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 866 if (MLX5_CAP_GEN(mdev, sho)) { 867 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 868 /* At this stage no support for signature handover */ 869 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 870 IB_PROT_T10DIF_TYPE_2 | 871 IB_PROT_T10DIF_TYPE_3; 872 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 873 IB_GUARD_T10DIF_CSUM; 874 } 875 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 876 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 877 878 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 879 if (MLX5_CAP_ETH(mdev, csum_cap)) { 880 /* Legacy bit to support old userspace libraries */ 881 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 882 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 883 } 884 885 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 886 props->raw_packet_caps |= 887 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 888 889 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 890 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 891 if (max_tso) { 892 resp.tso_caps.max_tso = 1 << max_tso; 893 resp.tso_caps.supported_qpts |= 894 1 << IB_QPT_RAW_PACKET; 895 resp.response_length += sizeof(resp.tso_caps); 896 } 897 } 898 899 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 900 resp.rss_caps.rx_hash_function = 901 MLX5_RX_HASH_FUNC_TOEPLITZ; 902 resp.rss_caps.rx_hash_fields_mask = 903 MLX5_RX_HASH_SRC_IPV4 | 904 MLX5_RX_HASH_DST_IPV4 | 905 MLX5_RX_HASH_SRC_IPV6 | 906 MLX5_RX_HASH_DST_IPV6 | 907 MLX5_RX_HASH_SRC_PORT_TCP | 908 MLX5_RX_HASH_DST_PORT_TCP | 909 MLX5_RX_HASH_SRC_PORT_UDP | 910 MLX5_RX_HASH_DST_PORT_UDP | 911 MLX5_RX_HASH_INNER; 912 resp.response_length += sizeof(resp.rss_caps); 913 } 914 } else { 915 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 916 resp.response_length += sizeof(resp.tso_caps); 917 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 918 resp.response_length += sizeof(resp.rss_caps); 919 } 920 921 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 922 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 923 props->kernel_cap_flags |= IBK_UD_TSO; 924 } 925 926 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 927 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 928 raw_support) 929 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 930 931 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 932 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 933 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 934 935 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 936 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 937 raw_support) { 938 /* Legacy bit to support old userspace libraries */ 939 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 940 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 941 } 942 943 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 944 props->max_dm_size = 945 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 946 } 947 948 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 949 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 950 951 if (MLX5_CAP_GEN(mdev, end_pad)) 952 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 953 954 props->vendor_part_id = mdev->pdev->device; 955 props->hw_ver = mdev->pdev->revision; 956 957 props->max_mr_size = ~0ull; 958 props->page_size_cap = ~(min_page_size - 1); 959 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 960 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 961 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 962 sizeof(struct mlx5_wqe_data_seg); 963 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 964 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 965 sizeof(struct mlx5_wqe_raddr_seg)) / 966 sizeof(struct mlx5_wqe_data_seg); 967 props->max_send_sge = max_sq_sg; 968 props->max_recv_sge = max_rq_sg; 969 props->max_sge_rd = MLX5_MAX_SGE_RD; 970 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 971 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 972 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 973 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 974 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 975 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 976 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 977 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 978 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 979 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 980 props->max_srq_sge = max_rq_sg - 1; 981 props->max_fast_reg_page_list_len = 982 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 983 props->max_pi_fast_reg_page_list_len = 984 props->max_fast_reg_page_list_len / 2; 985 props->max_sgl_rd = 986 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 987 get_atomic_caps_qp(dev, props); 988 props->masked_atomic_cap = IB_ATOMIC_NONE; 989 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 990 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 991 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 992 props->max_mcast_grp; 993 props->max_ah = INT_MAX; 994 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 995 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 996 997 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 998 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 999 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1000 props->odp_caps = dev->odp_caps; 1001 if (!uhw) { 1002 /* ODP for kernel QPs is not implemented for receive 1003 * WQEs and SRQ WQEs 1004 */ 1005 props->odp_caps.per_transport_caps.rc_odp_caps &= 1006 ~(IB_ODP_SUPPORT_READ | 1007 IB_ODP_SUPPORT_SRQ_RECV); 1008 props->odp_caps.per_transport_caps.uc_odp_caps &= 1009 ~(IB_ODP_SUPPORT_READ | 1010 IB_ODP_SUPPORT_SRQ_RECV); 1011 props->odp_caps.per_transport_caps.ud_odp_caps &= 1012 ~(IB_ODP_SUPPORT_READ | 1013 IB_ODP_SUPPORT_SRQ_RECV); 1014 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1015 ~(IB_ODP_SUPPORT_READ | 1016 IB_ODP_SUPPORT_SRQ_RECV); 1017 } 1018 } 1019 1020 if (mlx5_core_is_vf(mdev)) 1021 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1022 1023 if (mlx5_ib_port_link_layer(ibdev, 1) == 1024 IB_LINK_LAYER_ETHERNET && raw_support) { 1025 props->rss_caps.max_rwq_indirection_tables = 1026 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1027 props->rss_caps.max_rwq_indirection_table_size = 1028 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1029 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1030 props->max_wq_type_rq = 1031 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1032 } 1033 1034 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1035 props->tm_caps.max_num_tags = 1036 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1037 props->tm_caps.max_ops = 1038 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1039 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1040 } 1041 1042 if (MLX5_CAP_GEN(mdev, tag_matching) && 1043 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1044 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1045 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1046 } 1047 1048 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1049 props->cq_caps.max_cq_moderation_count = 1050 MLX5_MAX_CQ_COUNT; 1051 props->cq_caps.max_cq_moderation_period = 1052 MLX5_MAX_CQ_PERIOD; 1053 } 1054 1055 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1056 resp.response_length += sizeof(resp.cqe_comp_caps); 1057 1058 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1059 resp.cqe_comp_caps.max_num = 1060 MLX5_CAP_GEN(dev->mdev, 1061 cqe_compression_max_num); 1062 1063 resp.cqe_comp_caps.supported_format = 1064 MLX5_IB_CQE_RES_FORMAT_HASH | 1065 MLX5_IB_CQE_RES_FORMAT_CSUM; 1066 1067 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1068 resp.cqe_comp_caps.supported_format |= 1069 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1070 } 1071 } 1072 1073 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1074 raw_support) { 1075 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1076 MLX5_CAP_GEN(mdev, qos)) { 1077 resp.packet_pacing_caps.qp_rate_limit_max = 1078 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1079 resp.packet_pacing_caps.qp_rate_limit_min = 1080 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1081 resp.packet_pacing_caps.supported_qpts |= 1082 1 << IB_QPT_RAW_PACKET; 1083 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1084 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1085 resp.packet_pacing_caps.cap_flags |= 1086 MLX5_IB_PP_SUPPORT_BURST; 1087 } 1088 resp.response_length += sizeof(resp.packet_pacing_caps); 1089 } 1090 1091 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1092 uhw_outlen) { 1093 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1094 resp.mlx5_ib_support_multi_pkt_send_wqes = 1095 MLX5_IB_ALLOW_MPW; 1096 1097 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1098 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1099 MLX5_IB_SUPPORT_EMPW; 1100 1101 resp.response_length += 1102 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1103 } 1104 1105 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1106 resp.response_length += sizeof(resp.flags); 1107 1108 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1109 resp.flags |= 1110 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1111 1112 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1113 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1114 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1115 resp.flags |= 1116 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1117 1118 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1119 } 1120 1121 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1122 resp.response_length += sizeof(resp.sw_parsing_caps); 1123 if (MLX5_CAP_ETH(mdev, swp)) { 1124 resp.sw_parsing_caps.sw_parsing_offloads |= 1125 MLX5_IB_SW_PARSING; 1126 1127 if (MLX5_CAP_ETH(mdev, swp_csum)) 1128 resp.sw_parsing_caps.sw_parsing_offloads |= 1129 MLX5_IB_SW_PARSING_CSUM; 1130 1131 if (MLX5_CAP_ETH(mdev, swp_lso)) 1132 resp.sw_parsing_caps.sw_parsing_offloads |= 1133 MLX5_IB_SW_PARSING_LSO; 1134 1135 if (resp.sw_parsing_caps.sw_parsing_offloads) 1136 resp.sw_parsing_caps.supported_qpts = 1137 BIT(IB_QPT_RAW_PACKET); 1138 } 1139 } 1140 1141 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1142 raw_support) { 1143 resp.response_length += sizeof(resp.striding_rq_caps); 1144 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1145 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1146 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1147 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1148 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1149 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1150 resp.striding_rq_caps 1151 .min_single_wqe_log_num_of_strides = 1152 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1153 else 1154 resp.striding_rq_caps 1155 .min_single_wqe_log_num_of_strides = 1156 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1157 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1158 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1159 resp.striding_rq_caps.supported_qpts = 1160 BIT(IB_QPT_RAW_PACKET); 1161 } 1162 } 1163 1164 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1165 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1167 resp.tunnel_offloads_caps |= 1168 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1170 resp.tunnel_offloads_caps |= 1171 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1173 resp.tunnel_offloads_caps |= 1174 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1176 resp.tunnel_offloads_caps |= 1177 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1178 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1179 resp.tunnel_offloads_caps |= 1180 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1181 } 1182 1183 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1184 resp.response_length += sizeof(resp.dci_streams_caps); 1185 1186 resp.dci_streams_caps.max_log_num_concurent = 1187 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1188 1189 resp.dci_streams_caps.max_log_num_errored = 1190 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1191 } 1192 1193 if (uhw_outlen) { 1194 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1195 1196 if (err) 1197 return err; 1198 } 1199 1200 return 0; 1201 } 1202 1203 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1204 u8 *ib_width) 1205 { 1206 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1207 1208 if (active_width & MLX5_PTYS_WIDTH_1X) 1209 *ib_width = IB_WIDTH_1X; 1210 else if (active_width & MLX5_PTYS_WIDTH_2X) 1211 *ib_width = IB_WIDTH_2X; 1212 else if (active_width & MLX5_PTYS_WIDTH_4X) 1213 *ib_width = IB_WIDTH_4X; 1214 else if (active_width & MLX5_PTYS_WIDTH_8X) 1215 *ib_width = IB_WIDTH_8X; 1216 else if (active_width & MLX5_PTYS_WIDTH_12X) 1217 *ib_width = IB_WIDTH_12X; 1218 else { 1219 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1220 active_width); 1221 *ib_width = IB_WIDTH_4X; 1222 } 1223 1224 return; 1225 } 1226 1227 static int mlx5_mtu_to_ib_mtu(int mtu) 1228 { 1229 switch (mtu) { 1230 case 256: return 1; 1231 case 512: return 2; 1232 case 1024: return 3; 1233 case 2048: return 4; 1234 case 4096: return 5; 1235 default: 1236 pr_warn("invalid mtu\n"); 1237 return -1; 1238 } 1239 } 1240 1241 enum ib_max_vl_num { 1242 __IB_MAX_VL_0 = 1, 1243 __IB_MAX_VL_0_1 = 2, 1244 __IB_MAX_VL_0_3 = 3, 1245 __IB_MAX_VL_0_7 = 4, 1246 __IB_MAX_VL_0_14 = 5, 1247 }; 1248 1249 enum mlx5_vl_hw_cap { 1250 MLX5_VL_HW_0 = 1, 1251 MLX5_VL_HW_0_1 = 2, 1252 MLX5_VL_HW_0_2 = 3, 1253 MLX5_VL_HW_0_3 = 4, 1254 MLX5_VL_HW_0_4 = 5, 1255 MLX5_VL_HW_0_5 = 6, 1256 MLX5_VL_HW_0_6 = 7, 1257 MLX5_VL_HW_0_7 = 8, 1258 MLX5_VL_HW_0_14 = 15 1259 }; 1260 1261 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1262 u8 *max_vl_num) 1263 { 1264 switch (vl_hw_cap) { 1265 case MLX5_VL_HW_0: 1266 *max_vl_num = __IB_MAX_VL_0; 1267 break; 1268 case MLX5_VL_HW_0_1: 1269 *max_vl_num = __IB_MAX_VL_0_1; 1270 break; 1271 case MLX5_VL_HW_0_3: 1272 *max_vl_num = __IB_MAX_VL_0_3; 1273 break; 1274 case MLX5_VL_HW_0_7: 1275 *max_vl_num = __IB_MAX_VL_0_7; 1276 break; 1277 case MLX5_VL_HW_0_14: 1278 *max_vl_num = __IB_MAX_VL_0_14; 1279 break; 1280 1281 default: 1282 return -EINVAL; 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1289 struct ib_port_attr *props) 1290 { 1291 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1292 struct mlx5_core_dev *mdev = dev->mdev; 1293 struct mlx5_hca_vport_context *rep; 1294 u16 max_mtu; 1295 u16 oper_mtu; 1296 int err; 1297 u16 ib_link_width_oper; 1298 u8 vl_hw_cap; 1299 1300 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1301 if (!rep) { 1302 err = -ENOMEM; 1303 goto out; 1304 } 1305 1306 /* props being zeroed by the caller, avoid zeroing it here */ 1307 1308 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1309 if (err) 1310 goto out; 1311 1312 props->lid = rep->lid; 1313 props->lmc = rep->lmc; 1314 props->sm_lid = rep->sm_lid; 1315 props->sm_sl = rep->sm_sl; 1316 props->state = rep->vport_state; 1317 props->phys_state = rep->port_physical_state; 1318 props->port_cap_flags = rep->cap_mask1; 1319 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1320 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1321 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1322 props->bad_pkey_cntr = rep->pkey_violation_counter; 1323 props->qkey_viol_cntr = rep->qkey_violation_counter; 1324 props->subnet_timeout = rep->subnet_timeout; 1325 props->init_type_reply = rep->init_type_reply; 1326 1327 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1328 props->port_cap_flags2 = rep->cap_mask2; 1329 1330 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1331 &props->active_speed, port); 1332 if (err) 1333 goto out; 1334 1335 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1336 1337 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1338 1339 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1340 1341 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1342 1343 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1344 1345 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1346 if (err) 1347 goto out; 1348 1349 err = translate_max_vl_num(ibdev, vl_hw_cap, 1350 &props->max_vl_num); 1351 out: 1352 kfree(rep); 1353 return err; 1354 } 1355 1356 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1357 struct ib_port_attr *props) 1358 { 1359 unsigned int count; 1360 int ret; 1361 1362 switch (mlx5_get_vport_access_method(ibdev)) { 1363 case MLX5_VPORT_ACCESS_METHOD_MAD: 1364 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1365 break; 1366 1367 case MLX5_VPORT_ACCESS_METHOD_HCA: 1368 ret = mlx5_query_hca_port(ibdev, port, props); 1369 break; 1370 1371 case MLX5_VPORT_ACCESS_METHOD_NIC: 1372 ret = mlx5_query_port_roce(ibdev, port, props); 1373 break; 1374 1375 default: 1376 ret = -EINVAL; 1377 } 1378 1379 if (!ret && props) { 1380 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1381 struct mlx5_core_dev *mdev; 1382 bool put_mdev = true; 1383 1384 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1385 if (!mdev) { 1386 /* If the port isn't affiliated yet query the master. 1387 * The master and slave will have the same values. 1388 */ 1389 mdev = dev->mdev; 1390 port = 1; 1391 put_mdev = false; 1392 } 1393 count = mlx5_core_reserved_gids_count(mdev); 1394 if (put_mdev) 1395 mlx5_ib_put_native_port_mdev(dev, port); 1396 props->gid_tbl_len -= count; 1397 } 1398 return ret; 1399 } 1400 1401 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1402 struct ib_port_attr *props) 1403 { 1404 return mlx5_query_port_roce(ibdev, port, props); 1405 } 1406 1407 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1408 u16 *pkey) 1409 { 1410 /* Default special Pkey for representor device port as per the 1411 * IB specification 1.3 section 10.9.1.2. 1412 */ 1413 *pkey = 0xffff; 1414 return 0; 1415 } 1416 1417 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1418 union ib_gid *gid) 1419 { 1420 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1421 struct mlx5_core_dev *mdev = dev->mdev; 1422 1423 switch (mlx5_get_vport_access_method(ibdev)) { 1424 case MLX5_VPORT_ACCESS_METHOD_MAD: 1425 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1426 1427 case MLX5_VPORT_ACCESS_METHOD_HCA: 1428 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1429 1430 default: 1431 return -EINVAL; 1432 } 1433 1434 } 1435 1436 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1437 u16 index, u16 *pkey) 1438 { 1439 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1440 struct mlx5_core_dev *mdev; 1441 bool put_mdev = true; 1442 u32 mdev_port_num; 1443 int err; 1444 1445 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1446 if (!mdev) { 1447 /* The port isn't affiliated yet, get the PKey from the master 1448 * port. For RoCE the PKey tables will be the same. 1449 */ 1450 put_mdev = false; 1451 mdev = dev->mdev; 1452 mdev_port_num = 1; 1453 } 1454 1455 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1456 index, pkey); 1457 if (put_mdev) 1458 mlx5_ib_put_native_port_mdev(dev, port); 1459 1460 return err; 1461 } 1462 1463 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1464 u16 *pkey) 1465 { 1466 switch (mlx5_get_vport_access_method(ibdev)) { 1467 case MLX5_VPORT_ACCESS_METHOD_MAD: 1468 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1469 1470 case MLX5_VPORT_ACCESS_METHOD_HCA: 1471 case MLX5_VPORT_ACCESS_METHOD_NIC: 1472 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1473 default: 1474 return -EINVAL; 1475 } 1476 } 1477 1478 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1479 struct ib_device_modify *props) 1480 { 1481 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1482 struct mlx5_reg_node_desc in; 1483 struct mlx5_reg_node_desc out; 1484 int err; 1485 1486 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1487 return -EOPNOTSUPP; 1488 1489 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1490 return 0; 1491 1492 /* 1493 * If possible, pass node desc to FW, so it can generate 1494 * a 144 trap. If cmd fails, just ignore. 1495 */ 1496 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1497 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1498 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1499 if (err) 1500 return err; 1501 1502 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1503 1504 return err; 1505 } 1506 1507 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1508 u32 value) 1509 { 1510 struct mlx5_hca_vport_context ctx = {}; 1511 struct mlx5_core_dev *mdev; 1512 u32 mdev_port_num; 1513 int err; 1514 1515 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1516 if (!mdev) 1517 return -ENODEV; 1518 1519 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1520 if (err) 1521 goto out; 1522 1523 if (~ctx.cap_mask1_perm & mask) { 1524 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1525 mask, ctx.cap_mask1_perm); 1526 err = -EINVAL; 1527 goto out; 1528 } 1529 1530 ctx.cap_mask1 = value; 1531 ctx.cap_mask1_perm = mask; 1532 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1533 0, &ctx); 1534 1535 out: 1536 mlx5_ib_put_native_port_mdev(dev, port_num); 1537 1538 return err; 1539 } 1540 1541 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1542 struct ib_port_modify *props) 1543 { 1544 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1545 struct ib_port_attr attr; 1546 u32 tmp; 1547 int err; 1548 u32 change_mask; 1549 u32 value; 1550 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1551 IB_LINK_LAYER_INFINIBAND); 1552 1553 /* CM layer calls ib_modify_port() regardless of the link layer. For 1554 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1555 */ 1556 if (!is_ib) 1557 return 0; 1558 1559 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1560 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1561 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1562 return set_port_caps_atomic(dev, port, change_mask, value); 1563 } 1564 1565 mutex_lock(&dev->cap_mask_mutex); 1566 1567 err = ib_query_port(ibdev, port, &attr); 1568 if (err) 1569 goto out; 1570 1571 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1572 ~props->clr_port_cap_mask; 1573 1574 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1575 1576 out: 1577 mutex_unlock(&dev->cap_mask_mutex); 1578 return err; 1579 } 1580 1581 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1582 { 1583 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1584 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1585 } 1586 1587 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1588 { 1589 /* Large page with non 4k uar support might limit the dynamic size */ 1590 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1591 return MLX5_MIN_DYN_BFREGS; 1592 1593 return MLX5_MAX_DYN_BFREGS; 1594 } 1595 1596 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1597 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1598 struct mlx5_bfreg_info *bfregi) 1599 { 1600 int uars_per_sys_page; 1601 int bfregs_per_sys_page; 1602 int ref_bfregs = req->total_num_bfregs; 1603 1604 if (req->total_num_bfregs == 0) 1605 return -EINVAL; 1606 1607 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1608 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1609 1610 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1611 return -ENOMEM; 1612 1613 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1614 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1615 /* This holds the required static allocation asked by the user */ 1616 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1617 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1618 return -EINVAL; 1619 1620 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1621 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1622 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1623 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1624 1625 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1626 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1627 lib_uar_4k ? "yes" : "no", ref_bfregs, 1628 req->total_num_bfregs, bfregi->total_num_bfregs, 1629 bfregi->num_sys_pages); 1630 1631 return 0; 1632 } 1633 1634 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1635 { 1636 struct mlx5_bfreg_info *bfregi; 1637 int err; 1638 int i; 1639 1640 bfregi = &context->bfregi; 1641 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1642 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1643 context->devx_uid); 1644 if (err) 1645 goto error; 1646 1647 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1648 } 1649 1650 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1651 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1652 1653 return 0; 1654 1655 error: 1656 for (--i; i >= 0; i--) 1657 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1658 context->devx_uid)) 1659 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1660 1661 return err; 1662 } 1663 1664 static void deallocate_uars(struct mlx5_ib_dev *dev, 1665 struct mlx5_ib_ucontext *context) 1666 { 1667 struct mlx5_bfreg_info *bfregi; 1668 int i; 1669 1670 bfregi = &context->bfregi; 1671 for (i = 0; i < bfregi->num_sys_pages; i++) 1672 if (i < bfregi->num_static_sys_pages || 1673 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1674 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1675 context->devx_uid); 1676 } 1677 1678 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1679 { 1680 int err = 0; 1681 1682 mutex_lock(&dev->lb.mutex); 1683 if (td) 1684 dev->lb.user_td++; 1685 if (qp) 1686 dev->lb.qps++; 1687 1688 if (dev->lb.user_td == 2 || 1689 dev->lb.qps == 1) { 1690 if (!dev->lb.enabled) { 1691 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1692 dev->lb.enabled = true; 1693 } 1694 } 1695 1696 mutex_unlock(&dev->lb.mutex); 1697 1698 return err; 1699 } 1700 1701 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1702 { 1703 mutex_lock(&dev->lb.mutex); 1704 if (td) 1705 dev->lb.user_td--; 1706 if (qp) 1707 dev->lb.qps--; 1708 1709 if (dev->lb.user_td == 1 && 1710 dev->lb.qps == 0) { 1711 if (dev->lb.enabled) { 1712 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1713 dev->lb.enabled = false; 1714 } 1715 } 1716 1717 mutex_unlock(&dev->lb.mutex); 1718 } 1719 1720 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1721 u16 uid) 1722 { 1723 int err; 1724 1725 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1726 return 0; 1727 1728 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1729 if (err) 1730 return err; 1731 1732 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1733 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1734 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1735 return err; 1736 1737 return mlx5_ib_enable_lb(dev, true, false); 1738 } 1739 1740 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1741 u16 uid) 1742 { 1743 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1744 return; 1745 1746 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1747 1748 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1749 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1750 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1751 return; 1752 1753 mlx5_ib_disable_lb(dev, true, false); 1754 } 1755 1756 static int set_ucontext_resp(struct ib_ucontext *uctx, 1757 struct mlx5_ib_alloc_ucontext_resp *resp) 1758 { 1759 struct ib_device *ibdev = uctx->device; 1760 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1761 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1762 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1763 1764 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1765 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1766 resp->comp_mask |= 1767 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1768 } 1769 1770 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1771 if (dev->wc_support) 1772 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1773 log_bf_reg_size); 1774 resp->cache_line_size = cache_line_size(); 1775 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1776 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1777 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1778 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1779 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1780 resp->cqe_version = context->cqe_version; 1781 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1782 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1783 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1784 MLX5_CAP_GEN(dev->mdev, 1785 num_of_uars_per_page) : 1; 1786 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1787 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1788 resp->num_ports = dev->num_ports; 1789 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1790 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1791 1792 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1793 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1794 resp->eth_min_inline++; 1795 } 1796 1797 if (dev->mdev->clock_info) 1798 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1799 1800 /* 1801 * We don't want to expose information from the PCI bar that is located 1802 * after 4096 bytes, so if the arch only supports larger pages, let's 1803 * pretend we don't support reading the HCA's core clock. This is also 1804 * forced by mmap function. 1805 */ 1806 if (PAGE_SIZE <= 4096) { 1807 resp->comp_mask |= 1808 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1809 resp->hca_core_clock_offset = 1810 offsetof(struct mlx5_init_seg, 1811 internal_timer_h) % PAGE_SIZE; 1812 } 1813 1814 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1815 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1816 1817 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1818 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1819 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1820 resp->comp_mask |= 1821 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1822 1823 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1824 1825 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1826 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1827 1828 resp->comp_mask |= 1829 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1830 1831 return 0; 1832 } 1833 1834 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1835 struct ib_udata *udata) 1836 { 1837 struct ib_device *ibdev = uctx->device; 1838 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1839 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1840 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1841 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1842 struct mlx5_bfreg_info *bfregi; 1843 int ver; 1844 int err; 1845 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1846 max_cqe_version); 1847 bool lib_uar_4k; 1848 bool lib_uar_dyn; 1849 1850 if (!dev->ib_active) 1851 return -EAGAIN; 1852 1853 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1854 ver = 0; 1855 else if (udata->inlen >= min_req_v2) 1856 ver = 2; 1857 else 1858 return -EINVAL; 1859 1860 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1861 if (err) 1862 return err; 1863 1864 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1865 return -EOPNOTSUPP; 1866 1867 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1868 return -EOPNOTSUPP; 1869 1870 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1871 MLX5_NON_FP_BFREGS_PER_UAR); 1872 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1873 return -EINVAL; 1874 1875 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1876 err = mlx5_ib_devx_create(dev, true); 1877 if (err < 0) 1878 goto out_ctx; 1879 context->devx_uid = err; 1880 } 1881 1882 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1883 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1884 bfregi = &context->bfregi; 1885 1886 if (lib_uar_dyn) { 1887 bfregi->lib_uar_dyn = lib_uar_dyn; 1888 goto uar_done; 1889 } 1890 1891 /* updates req->total_num_bfregs */ 1892 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1893 if (err) 1894 goto out_devx; 1895 1896 mutex_init(&bfregi->lock); 1897 bfregi->lib_uar_4k = lib_uar_4k; 1898 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1899 GFP_KERNEL); 1900 if (!bfregi->count) { 1901 err = -ENOMEM; 1902 goto out_devx; 1903 } 1904 1905 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1906 sizeof(*bfregi->sys_pages), 1907 GFP_KERNEL); 1908 if (!bfregi->sys_pages) { 1909 err = -ENOMEM; 1910 goto out_count; 1911 } 1912 1913 err = allocate_uars(dev, context); 1914 if (err) 1915 goto out_sys_pages; 1916 1917 uar_done: 1918 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1919 context->devx_uid); 1920 if (err) 1921 goto out_uars; 1922 1923 INIT_LIST_HEAD(&context->db_page_list); 1924 mutex_init(&context->db_page_mutex); 1925 1926 context->cqe_version = min_t(__u8, 1927 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1928 req.max_cqe_version); 1929 1930 err = set_ucontext_resp(uctx, &resp); 1931 if (err) 1932 goto out_mdev; 1933 1934 resp.response_length = min(udata->outlen, sizeof(resp)); 1935 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1936 if (err) 1937 goto out_mdev; 1938 1939 bfregi->ver = ver; 1940 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1941 context->lib_caps = req.lib_caps; 1942 print_lib_caps(dev, context->lib_caps); 1943 1944 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1945 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1946 1947 atomic_set(&context->tx_port_affinity, 1948 atomic_add_return( 1949 1, &dev->port[port].roce.tx_port_affinity)); 1950 } 1951 1952 return 0; 1953 1954 out_mdev: 1955 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1956 1957 out_uars: 1958 deallocate_uars(dev, context); 1959 1960 out_sys_pages: 1961 kfree(bfregi->sys_pages); 1962 1963 out_count: 1964 kfree(bfregi->count); 1965 1966 out_devx: 1967 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1968 mlx5_ib_devx_destroy(dev, context->devx_uid); 1969 1970 out_ctx: 1971 return err; 1972 } 1973 1974 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1975 struct uverbs_attr_bundle *attrs) 1976 { 1977 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1978 int ret; 1979 1980 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1981 if (ret) 1982 return ret; 1983 1984 uctx_resp.response_length = 1985 min_t(size_t, 1986 uverbs_attr_get_len(attrs, 1987 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1988 sizeof(uctx_resp)); 1989 1990 ret = uverbs_copy_to_struct_or_zero(attrs, 1991 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1992 &uctx_resp, 1993 sizeof(uctx_resp)); 1994 return ret; 1995 } 1996 1997 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1998 { 1999 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2000 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2001 struct mlx5_bfreg_info *bfregi; 2002 2003 bfregi = &context->bfregi; 2004 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2005 2006 deallocate_uars(dev, context); 2007 kfree(bfregi->sys_pages); 2008 kfree(bfregi->count); 2009 2010 if (context->devx_uid) 2011 mlx5_ib_devx_destroy(dev, context->devx_uid); 2012 } 2013 2014 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2015 int uar_idx) 2016 { 2017 int fw_uars_per_page; 2018 2019 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2020 2021 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2022 } 2023 2024 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2025 int uar_idx) 2026 { 2027 unsigned int fw_uars_per_page; 2028 2029 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2030 MLX5_UARS_IN_PAGE : 1; 2031 2032 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2033 } 2034 2035 static int get_command(unsigned long offset) 2036 { 2037 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2038 } 2039 2040 static int get_arg(unsigned long offset) 2041 { 2042 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2043 } 2044 2045 static int get_index(unsigned long offset) 2046 { 2047 return get_arg(offset); 2048 } 2049 2050 /* Index resides in an extra byte to enable larger values than 255 */ 2051 static int get_extended_index(unsigned long offset) 2052 { 2053 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2054 } 2055 2056 2057 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2058 { 2059 } 2060 2061 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2062 { 2063 switch (cmd) { 2064 case MLX5_IB_MMAP_WC_PAGE: 2065 return "WC"; 2066 case MLX5_IB_MMAP_REGULAR_PAGE: 2067 return "best effort WC"; 2068 case MLX5_IB_MMAP_NC_PAGE: 2069 return "NC"; 2070 case MLX5_IB_MMAP_DEVICE_MEM: 2071 return "Device Memory"; 2072 default: 2073 return NULL; 2074 } 2075 } 2076 2077 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2078 struct vm_area_struct *vma, 2079 struct mlx5_ib_ucontext *context) 2080 { 2081 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2082 !(vma->vm_flags & VM_SHARED)) 2083 return -EINVAL; 2084 2085 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2086 return -EOPNOTSUPP; 2087 2088 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2089 return -EPERM; 2090 vm_flags_clear(vma, VM_MAYWRITE); 2091 2092 if (!dev->mdev->clock_info) 2093 return -EOPNOTSUPP; 2094 2095 return vm_insert_page(vma, vma->vm_start, 2096 virt_to_page(dev->mdev->clock_info)); 2097 } 2098 2099 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2100 { 2101 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2102 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2103 struct mlx5_var_table *var_table = &dev->var_table; 2104 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2105 2106 switch (mentry->mmap_flag) { 2107 case MLX5_IB_MMAP_TYPE_MEMIC: 2108 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2109 mlx5_ib_dm_mmap_free(dev, mentry); 2110 break; 2111 case MLX5_IB_MMAP_TYPE_VAR: 2112 mutex_lock(&var_table->bitmap_lock); 2113 clear_bit(mentry->page_idx, var_table->bitmap); 2114 mutex_unlock(&var_table->bitmap_lock); 2115 kfree(mentry); 2116 break; 2117 case MLX5_IB_MMAP_TYPE_UAR_WC: 2118 case MLX5_IB_MMAP_TYPE_UAR_NC: 2119 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2120 context->devx_uid); 2121 kfree(mentry); 2122 break; 2123 default: 2124 WARN_ON(true); 2125 } 2126 } 2127 2128 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2129 struct vm_area_struct *vma, 2130 struct mlx5_ib_ucontext *context) 2131 { 2132 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2133 int err; 2134 unsigned long idx; 2135 phys_addr_t pfn; 2136 pgprot_t prot; 2137 u32 bfreg_dyn_idx = 0; 2138 u32 uar_index; 2139 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2140 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2141 bfregi->num_static_sys_pages; 2142 2143 if (bfregi->lib_uar_dyn) 2144 return -EINVAL; 2145 2146 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2147 return -EINVAL; 2148 2149 if (dyn_uar) 2150 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2151 else 2152 idx = get_index(vma->vm_pgoff); 2153 2154 if (idx >= max_valid_idx) { 2155 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2156 idx, max_valid_idx); 2157 return -EINVAL; 2158 } 2159 2160 switch (cmd) { 2161 case MLX5_IB_MMAP_WC_PAGE: 2162 case MLX5_IB_MMAP_ALLOC_WC: 2163 case MLX5_IB_MMAP_REGULAR_PAGE: 2164 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2165 prot = pgprot_writecombine(vma->vm_page_prot); 2166 break; 2167 case MLX5_IB_MMAP_NC_PAGE: 2168 prot = pgprot_noncached(vma->vm_page_prot); 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 if (dyn_uar) { 2175 int uars_per_page; 2176 2177 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2178 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2179 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2180 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2181 bfreg_dyn_idx, bfregi->total_num_bfregs); 2182 return -EINVAL; 2183 } 2184 2185 mutex_lock(&bfregi->lock); 2186 /* Fail if uar already allocated, first bfreg index of each 2187 * page holds its count. 2188 */ 2189 if (bfregi->count[bfreg_dyn_idx]) { 2190 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2191 mutex_unlock(&bfregi->lock); 2192 return -EINVAL; 2193 } 2194 2195 bfregi->count[bfreg_dyn_idx]++; 2196 mutex_unlock(&bfregi->lock); 2197 2198 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2199 context->devx_uid); 2200 if (err) { 2201 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2202 goto free_bfreg; 2203 } 2204 } else { 2205 uar_index = bfregi->sys_pages[idx]; 2206 } 2207 2208 pfn = uar_index2pfn(dev, uar_index); 2209 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2210 2211 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2212 prot, NULL); 2213 if (err) { 2214 mlx5_ib_err(dev, 2215 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2216 err, mmap_cmd2str(cmd)); 2217 goto err; 2218 } 2219 2220 if (dyn_uar) 2221 bfregi->sys_pages[idx] = uar_index; 2222 return 0; 2223 2224 err: 2225 if (!dyn_uar) 2226 return err; 2227 2228 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2229 2230 free_bfreg: 2231 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2232 2233 return err; 2234 } 2235 2236 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2237 { 2238 unsigned long idx; 2239 u8 command; 2240 2241 command = get_command(vma->vm_pgoff); 2242 idx = get_extended_index(vma->vm_pgoff); 2243 2244 return (command << 16 | idx); 2245 } 2246 2247 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2248 struct vm_area_struct *vma, 2249 struct ib_ucontext *ucontext) 2250 { 2251 struct mlx5_user_mmap_entry *mentry; 2252 struct rdma_user_mmap_entry *entry; 2253 unsigned long pgoff; 2254 pgprot_t prot; 2255 phys_addr_t pfn; 2256 int ret; 2257 2258 pgoff = mlx5_vma_to_pgoff(vma); 2259 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2260 if (!entry) 2261 return -EINVAL; 2262 2263 mentry = to_mmmap(entry); 2264 pfn = (mentry->address >> PAGE_SHIFT); 2265 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2266 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2267 prot = pgprot_noncached(vma->vm_page_prot); 2268 else 2269 prot = pgprot_writecombine(vma->vm_page_prot); 2270 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2271 entry->npages * PAGE_SIZE, 2272 prot, 2273 entry); 2274 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2275 return ret; 2276 } 2277 2278 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2279 { 2280 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2281 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2282 2283 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2284 (index & 0xFF)) << PAGE_SHIFT; 2285 } 2286 2287 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2288 { 2289 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2290 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2291 unsigned long command; 2292 phys_addr_t pfn; 2293 2294 command = get_command(vma->vm_pgoff); 2295 switch (command) { 2296 case MLX5_IB_MMAP_WC_PAGE: 2297 case MLX5_IB_MMAP_ALLOC_WC: 2298 if (!dev->wc_support) 2299 return -EPERM; 2300 fallthrough; 2301 case MLX5_IB_MMAP_NC_PAGE: 2302 case MLX5_IB_MMAP_REGULAR_PAGE: 2303 return uar_mmap(dev, command, vma, context); 2304 2305 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2306 return -ENOSYS; 2307 2308 case MLX5_IB_MMAP_CORE_CLOCK: 2309 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2310 return -EINVAL; 2311 2312 if (vma->vm_flags & VM_WRITE) 2313 return -EPERM; 2314 vm_flags_clear(vma, VM_MAYWRITE); 2315 2316 /* Don't expose to user-space information it shouldn't have */ 2317 if (PAGE_SIZE > 4096) 2318 return -EOPNOTSUPP; 2319 2320 pfn = (dev->mdev->iseg_base + 2321 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2322 PAGE_SHIFT; 2323 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2324 PAGE_SIZE, 2325 pgprot_noncached(vma->vm_page_prot), 2326 NULL); 2327 case MLX5_IB_MMAP_CLOCK_INFO: 2328 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2329 2330 default: 2331 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2332 } 2333 2334 return 0; 2335 } 2336 2337 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2338 { 2339 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2340 struct ib_device *ibdev = ibpd->device; 2341 struct mlx5_ib_alloc_pd_resp resp; 2342 int err; 2343 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2344 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2345 u16 uid = 0; 2346 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2347 udata, struct mlx5_ib_ucontext, ibucontext); 2348 2349 uid = context ? context->devx_uid : 0; 2350 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2351 MLX5_SET(alloc_pd_in, in, uid, uid); 2352 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2353 if (err) 2354 return err; 2355 2356 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2357 pd->uid = uid; 2358 if (udata) { 2359 resp.pdn = pd->pdn; 2360 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2361 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2362 return -EFAULT; 2363 } 2364 } 2365 2366 return 0; 2367 } 2368 2369 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2370 { 2371 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2372 struct mlx5_ib_pd *mpd = to_mpd(pd); 2373 2374 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2375 } 2376 2377 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2378 { 2379 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2380 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2381 int err; 2382 u16 uid; 2383 2384 uid = ibqp->pd ? 2385 to_mpd(ibqp->pd)->uid : 0; 2386 2387 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2388 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2389 return -EOPNOTSUPP; 2390 } 2391 2392 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2393 if (err) 2394 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2395 ibqp->qp_num, gid->raw); 2396 2397 return err; 2398 } 2399 2400 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2401 { 2402 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2403 int err; 2404 u16 uid; 2405 2406 uid = ibqp->pd ? 2407 to_mpd(ibqp->pd)->uid : 0; 2408 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2409 if (err) 2410 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2411 ibqp->qp_num, gid->raw); 2412 2413 return err; 2414 } 2415 2416 static int init_node_data(struct mlx5_ib_dev *dev) 2417 { 2418 int err; 2419 2420 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2421 if (err) 2422 return err; 2423 2424 dev->mdev->rev_id = dev->mdev->pdev->revision; 2425 2426 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2427 } 2428 2429 static ssize_t fw_pages_show(struct device *device, 2430 struct device_attribute *attr, char *buf) 2431 { 2432 struct mlx5_ib_dev *dev = 2433 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2434 2435 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2436 } 2437 static DEVICE_ATTR_RO(fw_pages); 2438 2439 static ssize_t reg_pages_show(struct device *device, 2440 struct device_attribute *attr, char *buf) 2441 { 2442 struct mlx5_ib_dev *dev = 2443 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2444 2445 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2446 } 2447 static DEVICE_ATTR_RO(reg_pages); 2448 2449 static ssize_t hca_type_show(struct device *device, 2450 struct device_attribute *attr, char *buf) 2451 { 2452 struct mlx5_ib_dev *dev = 2453 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2454 2455 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2456 } 2457 static DEVICE_ATTR_RO(hca_type); 2458 2459 static ssize_t hw_rev_show(struct device *device, 2460 struct device_attribute *attr, char *buf) 2461 { 2462 struct mlx5_ib_dev *dev = 2463 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2464 2465 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2466 } 2467 static DEVICE_ATTR_RO(hw_rev); 2468 2469 static ssize_t board_id_show(struct device *device, 2470 struct device_attribute *attr, char *buf) 2471 { 2472 struct mlx5_ib_dev *dev = 2473 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2474 2475 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2476 dev->mdev->board_id); 2477 } 2478 static DEVICE_ATTR_RO(board_id); 2479 2480 static struct attribute *mlx5_class_attributes[] = { 2481 &dev_attr_hw_rev.attr, 2482 &dev_attr_hca_type.attr, 2483 &dev_attr_board_id.attr, 2484 &dev_attr_fw_pages.attr, 2485 &dev_attr_reg_pages.attr, 2486 NULL, 2487 }; 2488 2489 static const struct attribute_group mlx5_attr_group = { 2490 .attrs = mlx5_class_attributes, 2491 }; 2492 2493 static void pkey_change_handler(struct work_struct *work) 2494 { 2495 struct mlx5_ib_port_resources *ports = 2496 container_of(work, struct mlx5_ib_port_resources, 2497 pkey_change_work); 2498 2499 if (!ports->gsi) 2500 /* 2501 * We got this event before device was fully configured 2502 * and MAD registration code wasn't called/finished yet. 2503 */ 2504 return; 2505 2506 mlx5_ib_gsi_pkey_change(ports->gsi); 2507 } 2508 2509 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2510 { 2511 struct mlx5_ib_qp *mqp; 2512 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2513 struct mlx5_core_cq *mcq; 2514 struct list_head cq_armed_list; 2515 unsigned long flags_qp; 2516 unsigned long flags_cq; 2517 unsigned long flags; 2518 2519 INIT_LIST_HEAD(&cq_armed_list); 2520 2521 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2522 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2523 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2524 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2525 if (mqp->sq.tail != mqp->sq.head) { 2526 send_mcq = to_mcq(mqp->ibqp.send_cq); 2527 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2528 if (send_mcq->mcq.comp && 2529 mqp->ibqp.send_cq->comp_handler) { 2530 if (!send_mcq->mcq.reset_notify_added) { 2531 send_mcq->mcq.reset_notify_added = 1; 2532 list_add_tail(&send_mcq->mcq.reset_notify, 2533 &cq_armed_list); 2534 } 2535 } 2536 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2537 } 2538 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2539 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2540 /* no handling is needed for SRQ */ 2541 if (!mqp->ibqp.srq) { 2542 if (mqp->rq.tail != mqp->rq.head) { 2543 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2544 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2545 if (recv_mcq->mcq.comp && 2546 mqp->ibqp.recv_cq->comp_handler) { 2547 if (!recv_mcq->mcq.reset_notify_added) { 2548 recv_mcq->mcq.reset_notify_added = 1; 2549 list_add_tail(&recv_mcq->mcq.reset_notify, 2550 &cq_armed_list); 2551 } 2552 } 2553 spin_unlock_irqrestore(&recv_mcq->lock, 2554 flags_cq); 2555 } 2556 } 2557 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2558 } 2559 /*At that point all inflight post send were put to be executed as of we 2560 * lock/unlock above locks Now need to arm all involved CQs. 2561 */ 2562 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2563 mcq->comp(mcq, NULL); 2564 } 2565 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2566 } 2567 2568 static void delay_drop_handler(struct work_struct *work) 2569 { 2570 int err; 2571 struct mlx5_ib_delay_drop *delay_drop = 2572 container_of(work, struct mlx5_ib_delay_drop, 2573 delay_drop_work); 2574 2575 atomic_inc(&delay_drop->events_cnt); 2576 2577 mutex_lock(&delay_drop->lock); 2578 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2579 if (err) { 2580 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2581 delay_drop->timeout); 2582 delay_drop->activate = false; 2583 } 2584 mutex_unlock(&delay_drop->lock); 2585 } 2586 2587 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2588 struct ib_event *ibev) 2589 { 2590 u32 port = (eqe->data.port.port >> 4) & 0xf; 2591 2592 switch (eqe->sub_type) { 2593 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2594 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2595 IB_LINK_LAYER_ETHERNET) 2596 schedule_work(&ibdev->delay_drop.delay_drop_work); 2597 break; 2598 default: /* do nothing */ 2599 return; 2600 } 2601 } 2602 2603 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2604 struct ib_event *ibev) 2605 { 2606 u32 port = (eqe->data.port.port >> 4) & 0xf; 2607 2608 ibev->element.port_num = port; 2609 2610 switch (eqe->sub_type) { 2611 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2612 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2613 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2614 /* In RoCE, port up/down events are handled in 2615 * mlx5_netdev_event(). 2616 */ 2617 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2618 IB_LINK_LAYER_ETHERNET) 2619 return -EINVAL; 2620 2621 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2622 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2623 break; 2624 2625 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2626 ibev->event = IB_EVENT_LID_CHANGE; 2627 break; 2628 2629 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2630 ibev->event = IB_EVENT_PKEY_CHANGE; 2631 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2632 break; 2633 2634 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2635 ibev->event = IB_EVENT_GID_CHANGE; 2636 break; 2637 2638 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2639 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2640 break; 2641 default: 2642 return -EINVAL; 2643 } 2644 2645 return 0; 2646 } 2647 2648 static void mlx5_ib_handle_event(struct work_struct *_work) 2649 { 2650 struct mlx5_ib_event_work *work = 2651 container_of(_work, struct mlx5_ib_event_work, work); 2652 struct mlx5_ib_dev *ibdev; 2653 struct ib_event ibev; 2654 bool fatal = false; 2655 2656 if (work->is_slave) { 2657 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2658 if (!ibdev) 2659 goto out; 2660 } else { 2661 ibdev = work->dev; 2662 } 2663 2664 switch (work->event) { 2665 case MLX5_DEV_EVENT_SYS_ERROR: 2666 ibev.event = IB_EVENT_DEVICE_FATAL; 2667 mlx5_ib_handle_internal_error(ibdev); 2668 ibev.element.port_num = (u8)(unsigned long)work->param; 2669 fatal = true; 2670 break; 2671 case MLX5_EVENT_TYPE_PORT_CHANGE: 2672 if (handle_port_change(ibdev, work->param, &ibev)) 2673 goto out; 2674 break; 2675 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2676 handle_general_event(ibdev, work->param, &ibev); 2677 fallthrough; 2678 default: 2679 goto out; 2680 } 2681 2682 ibev.device = &ibdev->ib_dev; 2683 2684 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2685 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2686 goto out; 2687 } 2688 2689 if (ibdev->ib_active) 2690 ib_dispatch_event(&ibev); 2691 2692 if (fatal) 2693 ibdev->ib_active = false; 2694 out: 2695 kfree(work); 2696 } 2697 2698 static int mlx5_ib_event(struct notifier_block *nb, 2699 unsigned long event, void *param) 2700 { 2701 struct mlx5_ib_event_work *work; 2702 2703 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2704 if (!work) 2705 return NOTIFY_DONE; 2706 2707 INIT_WORK(&work->work, mlx5_ib_handle_event); 2708 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2709 work->is_slave = false; 2710 work->param = param; 2711 work->event = event; 2712 2713 queue_work(mlx5_ib_event_wq, &work->work); 2714 2715 return NOTIFY_OK; 2716 } 2717 2718 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2719 unsigned long event, void *param) 2720 { 2721 struct mlx5_ib_event_work *work; 2722 2723 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2724 if (!work) 2725 return NOTIFY_DONE; 2726 2727 INIT_WORK(&work->work, mlx5_ib_handle_event); 2728 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2729 work->is_slave = true; 2730 work->param = param; 2731 work->event = event; 2732 queue_work(mlx5_ib_event_wq, &work->work); 2733 2734 return NOTIFY_OK; 2735 } 2736 2737 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2738 { 2739 struct mlx5_hca_vport_context vport_ctx; 2740 int err; 2741 int port; 2742 2743 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2744 return 0; 2745 2746 for (port = 1; port <= dev->num_ports; port++) { 2747 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2748 dev->port_caps[port - 1].has_smi = true; 2749 continue; 2750 } 2751 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2752 &vport_ctx); 2753 if (err) { 2754 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2755 port, err); 2756 return err; 2757 } 2758 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2759 } 2760 2761 return 0; 2762 } 2763 2764 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2765 { 2766 unsigned int port; 2767 2768 rdma_for_each_port (&dev->ib_dev, port) 2769 mlx5_query_ext_port_caps(dev, port); 2770 } 2771 2772 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2773 { 2774 switch (umr_fence_cap) { 2775 case MLX5_CAP_UMR_FENCE_NONE: 2776 return MLX5_FENCE_MODE_NONE; 2777 case MLX5_CAP_UMR_FENCE_SMALL: 2778 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2779 default: 2780 return MLX5_FENCE_MODE_STRONG_ORDERING; 2781 } 2782 } 2783 2784 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2785 { 2786 struct mlx5_ib_resources *devr = &dev->devr; 2787 struct ib_srq_init_attr attr; 2788 struct ib_device *ibdev; 2789 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2790 int port; 2791 int ret = 0; 2792 2793 ibdev = &dev->ib_dev; 2794 2795 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2796 return -EOPNOTSUPP; 2797 2798 devr->p0 = ib_alloc_pd(ibdev, 0); 2799 if (IS_ERR(devr->p0)) 2800 return PTR_ERR(devr->p0); 2801 2802 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2803 if (IS_ERR(devr->c0)) { 2804 ret = PTR_ERR(devr->c0); 2805 goto error1; 2806 } 2807 2808 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2809 if (ret) 2810 goto error2; 2811 2812 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2813 if (ret) 2814 goto error3; 2815 2816 memset(&attr, 0, sizeof(attr)); 2817 attr.attr.max_sge = 1; 2818 attr.attr.max_wr = 1; 2819 attr.srq_type = IB_SRQT_XRC; 2820 attr.ext.cq = devr->c0; 2821 2822 devr->s0 = ib_create_srq(devr->p0, &attr); 2823 if (IS_ERR(devr->s0)) { 2824 ret = PTR_ERR(devr->s0); 2825 goto err_create; 2826 } 2827 2828 memset(&attr, 0, sizeof(attr)); 2829 attr.attr.max_sge = 1; 2830 attr.attr.max_wr = 1; 2831 attr.srq_type = IB_SRQT_BASIC; 2832 2833 devr->s1 = ib_create_srq(devr->p0, &attr); 2834 if (IS_ERR(devr->s1)) { 2835 ret = PTR_ERR(devr->s1); 2836 goto error6; 2837 } 2838 2839 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2840 INIT_WORK(&devr->ports[port].pkey_change_work, 2841 pkey_change_handler); 2842 2843 return 0; 2844 2845 error6: 2846 ib_destroy_srq(devr->s0); 2847 err_create: 2848 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2849 error3: 2850 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2851 error2: 2852 ib_destroy_cq(devr->c0); 2853 error1: 2854 ib_dealloc_pd(devr->p0); 2855 return ret; 2856 } 2857 2858 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2859 { 2860 struct mlx5_ib_resources *devr = &dev->devr; 2861 int port; 2862 2863 /* 2864 * Make sure no change P_Key work items are still executing. 2865 * 2866 * At this stage, the mlx5_ib_event should be unregistered 2867 * and it ensures that no new works are added. 2868 */ 2869 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2870 cancel_work_sync(&devr->ports[port].pkey_change_work); 2871 2872 ib_destroy_srq(devr->s1); 2873 ib_destroy_srq(devr->s0); 2874 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2875 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2876 ib_destroy_cq(devr->c0); 2877 ib_dealloc_pd(devr->p0); 2878 } 2879 2880 static u32 get_core_cap_flags(struct ib_device *ibdev, 2881 struct mlx5_hca_vport_context *rep) 2882 { 2883 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2884 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2885 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2886 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2887 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2888 u32 ret = 0; 2889 2890 if (rep->grh_required) 2891 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2892 2893 if (ll == IB_LINK_LAYER_INFINIBAND) 2894 return ret | RDMA_CORE_PORT_IBA_IB; 2895 2896 if (raw_support) 2897 ret |= RDMA_CORE_PORT_RAW_PACKET; 2898 2899 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2900 return ret; 2901 2902 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2903 return ret; 2904 2905 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2906 ret |= RDMA_CORE_PORT_IBA_ROCE; 2907 2908 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2909 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2910 2911 return ret; 2912 } 2913 2914 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2915 struct ib_port_immutable *immutable) 2916 { 2917 struct ib_port_attr attr; 2918 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2919 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2920 struct mlx5_hca_vport_context rep = {0}; 2921 int err; 2922 2923 err = ib_query_port(ibdev, port_num, &attr); 2924 if (err) 2925 return err; 2926 2927 if (ll == IB_LINK_LAYER_INFINIBAND) { 2928 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2929 &rep); 2930 if (err) 2931 return err; 2932 } 2933 2934 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2935 immutable->gid_tbl_len = attr.gid_tbl_len; 2936 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2937 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2938 2939 return 0; 2940 } 2941 2942 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2943 struct ib_port_immutable *immutable) 2944 { 2945 struct ib_port_attr attr; 2946 int err; 2947 2948 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2949 2950 err = ib_query_port(ibdev, port_num, &attr); 2951 if (err) 2952 return err; 2953 2954 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2955 immutable->gid_tbl_len = attr.gid_tbl_len; 2956 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2957 2958 return 0; 2959 } 2960 2961 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2962 { 2963 struct mlx5_ib_dev *dev = 2964 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2965 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2966 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2967 fw_rev_sub(dev->mdev)); 2968 } 2969 2970 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2971 { 2972 struct mlx5_core_dev *mdev = dev->mdev; 2973 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2974 MLX5_FLOW_NAMESPACE_LAG); 2975 struct mlx5_flow_table *ft; 2976 int err; 2977 2978 if (!ns || !mlx5_lag_is_active(mdev)) 2979 return 0; 2980 2981 err = mlx5_cmd_create_vport_lag(mdev); 2982 if (err) 2983 return err; 2984 2985 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 2986 if (IS_ERR(ft)) { 2987 err = PTR_ERR(ft); 2988 goto err_destroy_vport_lag; 2989 } 2990 2991 dev->flow_db->lag_demux_ft = ft; 2992 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 2993 dev->lag_active = true; 2994 return 0; 2995 2996 err_destroy_vport_lag: 2997 mlx5_cmd_destroy_vport_lag(mdev); 2998 return err; 2999 } 3000 3001 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3002 { 3003 struct mlx5_core_dev *mdev = dev->mdev; 3004 3005 if (dev->lag_active) { 3006 dev->lag_active = false; 3007 3008 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3009 dev->flow_db->lag_demux_ft = NULL; 3010 3011 mlx5_cmd_destroy_vport_lag(mdev); 3012 } 3013 } 3014 3015 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3016 struct net_device *netdev) 3017 { 3018 int err; 3019 3020 if (roce->tracking_netdev) 3021 return; 3022 roce->tracking_netdev = netdev; 3023 roce->nb.notifier_call = mlx5_netdev_event; 3024 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3025 WARN_ON(err); 3026 } 3027 3028 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3029 { 3030 if (!roce->tracking_netdev) 3031 return; 3032 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3033 &roce->nn); 3034 roce->tracking_netdev = NULL; 3035 } 3036 3037 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3038 unsigned long event, void *data) 3039 { 3040 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3041 struct net_device *netdev = data; 3042 3043 switch (event) { 3044 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3045 if (netdev) 3046 mlx5_netdev_notifier_register(roce, netdev); 3047 else 3048 mlx5_netdev_notifier_unregister(roce); 3049 break; 3050 default: 3051 return NOTIFY_DONE; 3052 } 3053 3054 return NOTIFY_OK; 3055 } 3056 3057 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3058 { 3059 struct mlx5_roce *roce = &dev->port[port_num].roce; 3060 3061 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3062 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3063 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3064 } 3065 3066 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3067 { 3068 struct mlx5_roce *roce = &dev->port[port_num].roce; 3069 3070 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3071 mlx5_netdev_notifier_unregister(roce); 3072 } 3073 3074 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3075 { 3076 int err; 3077 3078 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3079 err = mlx5_nic_vport_enable_roce(dev->mdev); 3080 if (err) 3081 return err; 3082 } 3083 3084 err = mlx5_eth_lag_init(dev); 3085 if (err) 3086 goto err_disable_roce; 3087 3088 return 0; 3089 3090 err_disable_roce: 3091 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3092 mlx5_nic_vport_disable_roce(dev->mdev); 3093 3094 return err; 3095 } 3096 3097 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3098 { 3099 mlx5_eth_lag_cleanup(dev); 3100 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3101 mlx5_nic_vport_disable_roce(dev->mdev); 3102 } 3103 3104 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3105 enum rdma_netdev_t type, 3106 struct rdma_netdev_alloc_params *params) 3107 { 3108 if (type != RDMA_NETDEV_IPOIB) 3109 return -EOPNOTSUPP; 3110 3111 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3112 } 3113 3114 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3115 size_t count, loff_t *pos) 3116 { 3117 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3118 char lbuf[20]; 3119 int len; 3120 3121 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3122 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3123 } 3124 3125 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3126 size_t count, loff_t *pos) 3127 { 3128 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3129 u32 timeout; 3130 u32 var; 3131 3132 if (kstrtouint_from_user(buf, count, 0, &var)) 3133 return -EFAULT; 3134 3135 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3136 1000); 3137 if (timeout != var) 3138 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3139 timeout); 3140 3141 delay_drop->timeout = timeout; 3142 3143 return count; 3144 } 3145 3146 static const struct file_operations fops_delay_drop_timeout = { 3147 .owner = THIS_MODULE, 3148 .open = simple_open, 3149 .write = delay_drop_timeout_write, 3150 .read = delay_drop_timeout_read, 3151 }; 3152 3153 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3154 struct mlx5_ib_multiport_info *mpi) 3155 { 3156 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3157 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3158 int comps; 3159 int err; 3160 int i; 3161 3162 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3163 3164 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3165 3166 spin_lock(&port->mp.mpi_lock); 3167 if (!mpi->ibdev) { 3168 spin_unlock(&port->mp.mpi_lock); 3169 return; 3170 } 3171 3172 mpi->ibdev = NULL; 3173 3174 spin_unlock(&port->mp.mpi_lock); 3175 if (mpi->mdev_events.notifier_call) 3176 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3177 mpi->mdev_events.notifier_call = NULL; 3178 mlx5_mdev_netdev_untrack(ibdev, port_num); 3179 spin_lock(&port->mp.mpi_lock); 3180 3181 comps = mpi->mdev_refcnt; 3182 if (comps) { 3183 mpi->unaffiliate = true; 3184 init_completion(&mpi->unref_comp); 3185 spin_unlock(&port->mp.mpi_lock); 3186 3187 for (i = 0; i < comps; i++) 3188 wait_for_completion(&mpi->unref_comp); 3189 3190 spin_lock(&port->mp.mpi_lock); 3191 mpi->unaffiliate = false; 3192 } 3193 3194 port->mp.mpi = NULL; 3195 3196 spin_unlock(&port->mp.mpi_lock); 3197 3198 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3199 3200 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3201 /* Log an error, still needed to cleanup the pointers and add 3202 * it back to the list. 3203 */ 3204 if (err) 3205 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3206 port_num + 1); 3207 3208 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3209 } 3210 3211 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3212 struct mlx5_ib_multiport_info *mpi) 3213 { 3214 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3215 int err; 3216 3217 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3218 3219 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3220 if (ibdev->port[port_num].mp.mpi) { 3221 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3222 port_num + 1); 3223 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3224 return false; 3225 } 3226 3227 ibdev->port[port_num].mp.mpi = mpi; 3228 mpi->ibdev = ibdev; 3229 mpi->mdev_events.notifier_call = NULL; 3230 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3231 3232 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3233 if (err) 3234 goto unbind; 3235 3236 mlx5_mdev_netdev_track(ibdev, port_num); 3237 3238 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3239 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3240 3241 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3242 3243 return true; 3244 3245 unbind: 3246 mlx5_ib_unbind_slave_port(ibdev, mpi); 3247 return false; 3248 } 3249 3250 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3251 { 3252 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3253 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3254 port_num + 1); 3255 struct mlx5_ib_multiport_info *mpi; 3256 int err; 3257 u32 i; 3258 3259 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3260 return 0; 3261 3262 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3263 &dev->sys_image_guid); 3264 if (err) 3265 return err; 3266 3267 err = mlx5_nic_vport_enable_roce(dev->mdev); 3268 if (err) 3269 return err; 3270 3271 mutex_lock(&mlx5_ib_multiport_mutex); 3272 for (i = 0; i < dev->num_ports; i++) { 3273 bool bound = false; 3274 3275 /* build a stub multiport info struct for the native port. */ 3276 if (i == port_num) { 3277 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3278 if (!mpi) { 3279 mutex_unlock(&mlx5_ib_multiport_mutex); 3280 mlx5_nic_vport_disable_roce(dev->mdev); 3281 return -ENOMEM; 3282 } 3283 3284 mpi->is_master = true; 3285 mpi->mdev = dev->mdev; 3286 mpi->sys_image_guid = dev->sys_image_guid; 3287 dev->port[i].mp.mpi = mpi; 3288 mpi->ibdev = dev; 3289 mpi = NULL; 3290 continue; 3291 } 3292 3293 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3294 list) { 3295 if (dev->sys_image_guid == mpi->sys_image_guid && 3296 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3297 bound = mlx5_ib_bind_slave_port(dev, mpi); 3298 } 3299 3300 if (bound) { 3301 dev_dbg(mpi->mdev->device, 3302 "removing port from unaffiliated list.\n"); 3303 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3304 list_del(&mpi->list); 3305 break; 3306 } 3307 } 3308 if (!bound) 3309 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3310 i + 1); 3311 } 3312 3313 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3314 mutex_unlock(&mlx5_ib_multiport_mutex); 3315 return err; 3316 } 3317 3318 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3319 { 3320 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3321 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3322 port_num + 1); 3323 u32 i; 3324 3325 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3326 return; 3327 3328 mutex_lock(&mlx5_ib_multiport_mutex); 3329 for (i = 0; i < dev->num_ports; i++) { 3330 if (dev->port[i].mp.mpi) { 3331 /* Destroy the native port stub */ 3332 if (i == port_num) { 3333 kfree(dev->port[i].mp.mpi); 3334 dev->port[i].mp.mpi = NULL; 3335 } else { 3336 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3337 i + 1); 3338 list_add_tail(&dev->port[i].mp.mpi->list, 3339 &mlx5_ib_unaffiliated_port_list); 3340 mlx5_ib_unbind_slave_port(dev, 3341 dev->port[i].mp.mpi); 3342 } 3343 } 3344 } 3345 3346 mlx5_ib_dbg(dev, "removing from devlist\n"); 3347 list_del(&dev->ib_dev_list); 3348 mutex_unlock(&mlx5_ib_multiport_mutex); 3349 3350 mlx5_nic_vport_disable_roce(dev->mdev); 3351 } 3352 3353 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3354 enum rdma_remove_reason why, 3355 struct uverbs_attr_bundle *attrs) 3356 { 3357 struct mlx5_user_mmap_entry *obj = uobject->object; 3358 3359 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3360 return 0; 3361 } 3362 3363 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3364 struct mlx5_user_mmap_entry *entry, 3365 size_t length) 3366 { 3367 return rdma_user_mmap_entry_insert_range( 3368 &c->ibucontext, &entry->rdma_entry, length, 3369 (MLX5_IB_MMAP_OFFSET_START << 16), 3370 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3371 } 3372 3373 static struct mlx5_user_mmap_entry * 3374 alloc_var_entry(struct mlx5_ib_ucontext *c) 3375 { 3376 struct mlx5_user_mmap_entry *entry; 3377 struct mlx5_var_table *var_table; 3378 u32 page_idx; 3379 int err; 3380 3381 var_table = &to_mdev(c->ibucontext.device)->var_table; 3382 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3383 if (!entry) 3384 return ERR_PTR(-ENOMEM); 3385 3386 mutex_lock(&var_table->bitmap_lock); 3387 page_idx = find_first_zero_bit(var_table->bitmap, 3388 var_table->num_var_hw_entries); 3389 if (page_idx >= var_table->num_var_hw_entries) { 3390 err = -ENOSPC; 3391 mutex_unlock(&var_table->bitmap_lock); 3392 goto end; 3393 } 3394 3395 set_bit(page_idx, var_table->bitmap); 3396 mutex_unlock(&var_table->bitmap_lock); 3397 3398 entry->address = var_table->hw_start_addr + 3399 (page_idx * var_table->stride_size); 3400 entry->page_idx = page_idx; 3401 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3402 3403 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3404 var_table->stride_size); 3405 if (err) 3406 goto err_insert; 3407 3408 return entry; 3409 3410 err_insert: 3411 mutex_lock(&var_table->bitmap_lock); 3412 clear_bit(page_idx, var_table->bitmap); 3413 mutex_unlock(&var_table->bitmap_lock); 3414 end: 3415 kfree(entry); 3416 return ERR_PTR(err); 3417 } 3418 3419 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3420 struct uverbs_attr_bundle *attrs) 3421 { 3422 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3423 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3424 struct mlx5_ib_ucontext *c; 3425 struct mlx5_user_mmap_entry *entry; 3426 u64 mmap_offset; 3427 u32 length; 3428 int err; 3429 3430 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3431 if (IS_ERR(c)) 3432 return PTR_ERR(c); 3433 3434 entry = alloc_var_entry(c); 3435 if (IS_ERR(entry)) 3436 return PTR_ERR(entry); 3437 3438 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3439 length = entry->rdma_entry.npages * PAGE_SIZE; 3440 uobj->object = entry; 3441 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3442 3443 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3444 &mmap_offset, sizeof(mmap_offset)); 3445 if (err) 3446 return err; 3447 3448 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3449 &entry->page_idx, sizeof(entry->page_idx)); 3450 if (err) 3451 return err; 3452 3453 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3454 &length, sizeof(length)); 3455 return err; 3456 } 3457 3458 DECLARE_UVERBS_NAMED_METHOD( 3459 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3460 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3461 MLX5_IB_OBJECT_VAR, 3462 UVERBS_ACCESS_NEW, 3463 UA_MANDATORY), 3464 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3465 UVERBS_ATTR_TYPE(u32), 3466 UA_MANDATORY), 3467 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3468 UVERBS_ATTR_TYPE(u32), 3469 UA_MANDATORY), 3470 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3471 UVERBS_ATTR_TYPE(u64), 3472 UA_MANDATORY)); 3473 3474 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3475 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3476 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3477 MLX5_IB_OBJECT_VAR, 3478 UVERBS_ACCESS_DESTROY, 3479 UA_MANDATORY)); 3480 3481 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3482 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3483 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3484 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3485 3486 static bool var_is_supported(struct ib_device *device) 3487 { 3488 struct mlx5_ib_dev *dev = to_mdev(device); 3489 3490 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3491 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3492 } 3493 3494 static struct mlx5_user_mmap_entry * 3495 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3496 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3497 { 3498 struct mlx5_user_mmap_entry *entry; 3499 struct mlx5_ib_dev *dev; 3500 u32 uar_index; 3501 int err; 3502 3503 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3504 if (!entry) 3505 return ERR_PTR(-ENOMEM); 3506 3507 dev = to_mdev(c->ibucontext.device); 3508 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3509 if (err) 3510 goto end; 3511 3512 entry->page_idx = uar_index; 3513 entry->address = uar_index2paddress(dev, uar_index); 3514 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3515 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3516 else 3517 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3518 3519 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3520 if (err) 3521 goto err_insert; 3522 3523 return entry; 3524 3525 err_insert: 3526 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3527 end: 3528 kfree(entry); 3529 return ERR_PTR(err); 3530 } 3531 3532 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3533 struct uverbs_attr_bundle *attrs) 3534 { 3535 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3536 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3537 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3538 struct mlx5_ib_ucontext *c; 3539 struct mlx5_user_mmap_entry *entry; 3540 u64 mmap_offset; 3541 u32 length; 3542 int err; 3543 3544 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3545 if (IS_ERR(c)) 3546 return PTR_ERR(c); 3547 3548 err = uverbs_get_const(&alloc_type, attrs, 3549 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3550 if (err) 3551 return err; 3552 3553 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3554 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3555 return -EOPNOTSUPP; 3556 3557 if (!to_mdev(c->ibucontext.device)->wc_support && 3558 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3559 return -EOPNOTSUPP; 3560 3561 entry = alloc_uar_entry(c, alloc_type); 3562 if (IS_ERR(entry)) 3563 return PTR_ERR(entry); 3564 3565 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3566 length = entry->rdma_entry.npages * PAGE_SIZE; 3567 uobj->object = entry; 3568 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3569 3570 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3571 &mmap_offset, sizeof(mmap_offset)); 3572 if (err) 3573 return err; 3574 3575 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3576 &entry->page_idx, sizeof(entry->page_idx)); 3577 if (err) 3578 return err; 3579 3580 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3581 &length, sizeof(length)); 3582 return err; 3583 } 3584 3585 DECLARE_UVERBS_NAMED_METHOD( 3586 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3587 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3588 MLX5_IB_OBJECT_UAR, 3589 UVERBS_ACCESS_NEW, 3590 UA_MANDATORY), 3591 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3592 enum mlx5_ib_uapi_uar_alloc_type, 3593 UA_MANDATORY), 3594 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3595 UVERBS_ATTR_TYPE(u32), 3596 UA_MANDATORY), 3597 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3598 UVERBS_ATTR_TYPE(u32), 3599 UA_MANDATORY), 3600 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3601 UVERBS_ATTR_TYPE(u64), 3602 UA_MANDATORY)); 3603 3604 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3605 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3606 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3607 MLX5_IB_OBJECT_UAR, 3608 UVERBS_ACCESS_DESTROY, 3609 UA_MANDATORY)); 3610 3611 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3612 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3613 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3614 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3615 3616 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3617 mlx5_ib_query_context, 3618 UVERBS_OBJECT_DEVICE, 3619 UVERBS_METHOD_QUERY_CONTEXT, 3620 UVERBS_ATTR_PTR_OUT( 3621 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3622 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3623 dump_fill_mkey), 3624 UA_MANDATORY)); 3625 3626 static const struct uapi_definition mlx5_ib_defs[] = { 3627 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3628 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3629 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3630 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3631 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3632 3633 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3634 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3635 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3636 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3637 {} 3638 }; 3639 3640 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3641 { 3642 mlx5_ib_cleanup_multiport_master(dev); 3643 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3644 mutex_destroy(&dev->cap_mask_mutex); 3645 WARN_ON(!xa_empty(&dev->sig_mrs)); 3646 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3647 } 3648 3649 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3650 { 3651 struct mlx5_core_dev *mdev = dev->mdev; 3652 int err; 3653 int i; 3654 3655 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3656 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3657 dev->ib_dev.phys_port_cnt = dev->num_ports; 3658 dev->ib_dev.dev.parent = mdev->device; 3659 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3660 3661 for (i = 0; i < dev->num_ports; i++) { 3662 spin_lock_init(&dev->port[i].mp.mpi_lock); 3663 rwlock_init(&dev->port[i].roce.netdev_lock); 3664 dev->port[i].roce.dev = dev; 3665 dev->port[i].roce.native_port_num = i + 1; 3666 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3667 } 3668 3669 err = mlx5r_cmd_query_special_mkeys(dev); 3670 if (err) 3671 return err; 3672 3673 err = mlx5_ib_init_multiport_master(dev); 3674 if (err) 3675 return err; 3676 3677 err = set_has_smi_cap(dev); 3678 if (err) 3679 goto err_mp; 3680 3681 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3682 if (err) 3683 goto err_mp; 3684 3685 if (mlx5_use_mad_ifc(dev)) 3686 get_ext_port_caps(dev); 3687 3688 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3689 3690 mutex_init(&dev->cap_mask_mutex); 3691 INIT_LIST_HEAD(&dev->qp_list); 3692 spin_lock_init(&dev->reset_flow_resource_lock); 3693 xa_init(&dev->odp_mkeys); 3694 xa_init(&dev->sig_mrs); 3695 atomic_set(&dev->mkey_var, 0); 3696 3697 spin_lock_init(&dev->dm.lock); 3698 dev->dm.dev = mdev; 3699 return 0; 3700 3701 err_mp: 3702 mlx5_ib_cleanup_multiport_master(dev); 3703 return err; 3704 } 3705 3706 static int mlx5_ib_enable_driver(struct ib_device *dev) 3707 { 3708 struct mlx5_ib_dev *mdev = to_mdev(dev); 3709 int ret; 3710 3711 ret = mlx5_ib_test_wc(mdev); 3712 mlx5_ib_dbg(mdev, "Write-Combining %s", 3713 mdev->wc_support ? "supported" : "not supported"); 3714 3715 return ret; 3716 } 3717 3718 static const struct ib_device_ops mlx5_ib_dev_ops = { 3719 .owner = THIS_MODULE, 3720 .driver_id = RDMA_DRIVER_MLX5, 3721 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3722 3723 .add_gid = mlx5_ib_add_gid, 3724 .alloc_mr = mlx5_ib_alloc_mr, 3725 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3726 .alloc_pd = mlx5_ib_alloc_pd, 3727 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3728 .attach_mcast = mlx5_ib_mcg_attach, 3729 .check_mr_status = mlx5_ib_check_mr_status, 3730 .create_ah = mlx5_ib_create_ah, 3731 .create_cq = mlx5_ib_create_cq, 3732 .create_qp = mlx5_ib_create_qp, 3733 .create_srq = mlx5_ib_create_srq, 3734 .create_user_ah = mlx5_ib_create_ah, 3735 .dealloc_pd = mlx5_ib_dealloc_pd, 3736 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3737 .del_gid = mlx5_ib_del_gid, 3738 .dereg_mr = mlx5_ib_dereg_mr, 3739 .destroy_ah = mlx5_ib_destroy_ah, 3740 .destroy_cq = mlx5_ib_destroy_cq, 3741 .destroy_qp = mlx5_ib_destroy_qp, 3742 .destroy_srq = mlx5_ib_destroy_srq, 3743 .detach_mcast = mlx5_ib_mcg_detach, 3744 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3745 .drain_rq = mlx5_ib_drain_rq, 3746 .drain_sq = mlx5_ib_drain_sq, 3747 .device_group = &mlx5_attr_group, 3748 .enable_driver = mlx5_ib_enable_driver, 3749 .get_dev_fw_str = get_dev_fw_str, 3750 .get_dma_mr = mlx5_ib_get_dma_mr, 3751 .get_link_layer = mlx5_ib_port_link_layer, 3752 .map_mr_sg = mlx5_ib_map_mr_sg, 3753 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3754 .mmap = mlx5_ib_mmap, 3755 .mmap_free = mlx5_ib_mmap_free, 3756 .modify_cq = mlx5_ib_modify_cq, 3757 .modify_device = mlx5_ib_modify_device, 3758 .modify_port = mlx5_ib_modify_port, 3759 .modify_qp = mlx5_ib_modify_qp, 3760 .modify_srq = mlx5_ib_modify_srq, 3761 .poll_cq = mlx5_ib_poll_cq, 3762 .post_recv = mlx5_ib_post_recv_nodrain, 3763 .post_send = mlx5_ib_post_send_nodrain, 3764 .post_srq_recv = mlx5_ib_post_srq_recv, 3765 .process_mad = mlx5_ib_process_mad, 3766 .query_ah = mlx5_ib_query_ah, 3767 .query_device = mlx5_ib_query_device, 3768 .query_gid = mlx5_ib_query_gid, 3769 .query_pkey = mlx5_ib_query_pkey, 3770 .query_qp = mlx5_ib_query_qp, 3771 .query_srq = mlx5_ib_query_srq, 3772 .query_ucontext = mlx5_ib_query_ucontext, 3773 .reg_user_mr = mlx5_ib_reg_user_mr, 3774 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3775 .req_notify_cq = mlx5_ib_arm_cq, 3776 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3777 .resize_cq = mlx5_ib_resize_cq, 3778 3779 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3780 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3781 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3782 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3783 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3784 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3785 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3786 }; 3787 3788 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3789 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3790 }; 3791 3792 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3793 .get_vf_config = mlx5_ib_get_vf_config, 3794 .get_vf_guid = mlx5_ib_get_vf_guid, 3795 .get_vf_stats = mlx5_ib_get_vf_stats, 3796 .set_vf_guid = mlx5_ib_set_vf_guid, 3797 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3798 }; 3799 3800 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3801 .alloc_mw = mlx5_ib_alloc_mw, 3802 .dealloc_mw = mlx5_ib_dealloc_mw, 3803 3804 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3805 }; 3806 3807 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3808 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3809 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3810 3811 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3812 }; 3813 3814 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3815 { 3816 struct mlx5_core_dev *mdev = dev->mdev; 3817 struct mlx5_var_table *var_table = &dev->var_table; 3818 u8 log_doorbell_bar_size; 3819 u8 log_doorbell_stride; 3820 u64 bar_size; 3821 3822 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3823 log_doorbell_bar_size); 3824 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3825 log_doorbell_stride); 3826 var_table->hw_start_addr = dev->mdev->bar_addr + 3827 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3828 doorbell_bar_offset); 3829 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3830 var_table->stride_size = 1ULL << log_doorbell_stride; 3831 var_table->num_var_hw_entries = div_u64(bar_size, 3832 var_table->stride_size); 3833 mutex_init(&var_table->bitmap_lock); 3834 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3835 GFP_KERNEL); 3836 return (var_table->bitmap) ? 0 : -ENOMEM; 3837 } 3838 3839 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3840 { 3841 bitmap_free(dev->var_table.bitmap); 3842 } 3843 3844 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3845 { 3846 struct mlx5_core_dev *mdev = dev->mdev; 3847 int err; 3848 3849 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3850 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3851 ib_set_device_ops(&dev->ib_dev, 3852 &mlx5_ib_dev_ipoib_enhanced_ops); 3853 3854 if (mlx5_core_is_pf(mdev)) 3855 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3856 3857 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3858 3859 if (MLX5_CAP_GEN(mdev, imaicl)) 3860 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3861 3862 if (MLX5_CAP_GEN(mdev, xrc)) 3863 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3864 3865 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3866 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3867 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3868 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3869 3870 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3871 3872 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3873 dev->ib_dev.driver_def = mlx5_ib_defs; 3874 3875 err = init_node_data(dev); 3876 if (err) 3877 return err; 3878 3879 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3880 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3881 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3882 mutex_init(&dev->lb.mutex); 3883 3884 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3885 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3886 err = mlx5_ib_init_var_table(dev); 3887 if (err) 3888 return err; 3889 } 3890 3891 dev->ib_dev.use_cq_dim = true; 3892 3893 return 0; 3894 } 3895 3896 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3897 .get_port_immutable = mlx5_port_immutable, 3898 .query_port = mlx5_ib_query_port, 3899 }; 3900 3901 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3902 { 3903 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3904 return 0; 3905 } 3906 3907 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3908 .get_port_immutable = mlx5_port_rep_immutable, 3909 .query_port = mlx5_ib_rep_query_port, 3910 .query_pkey = mlx5_ib_rep_query_pkey, 3911 }; 3912 3913 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3914 { 3915 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3916 return 0; 3917 } 3918 3919 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3920 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3921 .create_wq = mlx5_ib_create_wq, 3922 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3923 .destroy_wq = mlx5_ib_destroy_wq, 3924 .get_netdev = mlx5_ib_get_netdev, 3925 .modify_wq = mlx5_ib_modify_wq, 3926 3927 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3928 ib_rwq_ind_tbl), 3929 }; 3930 3931 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3932 { 3933 struct mlx5_core_dev *mdev = dev->mdev; 3934 enum rdma_link_layer ll; 3935 int port_type_cap; 3936 u32 port_num = 0; 3937 int err; 3938 3939 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3940 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3941 3942 if (ll == IB_LINK_LAYER_ETHERNET) { 3943 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3944 3945 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3946 3947 /* Register only for native ports */ 3948 mlx5_mdev_netdev_track(dev, port_num); 3949 3950 err = mlx5_enable_eth(dev); 3951 if (err) 3952 goto cleanup; 3953 } 3954 3955 return 0; 3956 cleanup: 3957 mlx5_mdev_netdev_untrack(dev, port_num); 3958 return err; 3959 } 3960 3961 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3962 { 3963 struct mlx5_core_dev *mdev = dev->mdev; 3964 enum rdma_link_layer ll; 3965 int port_type_cap; 3966 u32 port_num; 3967 3968 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3969 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3970 3971 if (ll == IB_LINK_LAYER_ETHERNET) { 3972 mlx5_disable_eth(dev); 3973 3974 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3975 mlx5_mdev_netdev_untrack(dev, port_num); 3976 } 3977 } 3978 3979 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3980 { 3981 mlx5_ib_init_cong_debugfs(dev, 3982 mlx5_core_native_port_num(dev->mdev) - 1); 3983 return 0; 3984 } 3985 3986 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 3987 { 3988 mlx5_ib_cleanup_cong_debugfs(dev, 3989 mlx5_core_native_port_num(dev->mdev) - 1); 3990 } 3991 3992 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 3993 { 3994 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3995 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 3996 } 3997 3998 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 3999 { 4000 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4001 } 4002 4003 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4004 { 4005 int err; 4006 4007 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4008 if (err) 4009 return err; 4010 4011 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4012 if (err) 4013 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4014 4015 return err; 4016 } 4017 4018 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4019 { 4020 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4021 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4022 } 4023 4024 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4025 { 4026 const char *name; 4027 4028 if (!mlx5_lag_is_active(dev->mdev)) 4029 name = "mlx5_%d"; 4030 else 4031 name = "mlx5_bond_%d"; 4032 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4033 } 4034 4035 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4036 { 4037 mlx5_mkey_cache_cleanup(dev); 4038 mlx5r_umr_resource_cleanup(dev); 4039 } 4040 4041 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4042 { 4043 ib_unregister_device(&dev->ib_dev); 4044 } 4045 4046 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4047 { 4048 int ret; 4049 4050 ret = mlx5r_umr_resource_init(dev); 4051 if (ret) 4052 return ret; 4053 4054 ret = mlx5_mkey_cache_init(dev); 4055 if (ret) { 4056 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4057 mlx5r_umr_resource_cleanup(dev); 4058 } 4059 return ret; 4060 } 4061 4062 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4063 { 4064 struct dentry *root; 4065 4066 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4067 return 0; 4068 4069 mutex_init(&dev->delay_drop.lock); 4070 dev->delay_drop.dev = dev; 4071 dev->delay_drop.activate = false; 4072 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4073 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4074 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4075 atomic_set(&dev->delay_drop.events_cnt, 0); 4076 4077 if (!mlx5_debugfs_root) 4078 return 0; 4079 4080 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4081 dev->delay_drop.dir_debugfs = root; 4082 4083 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4084 &dev->delay_drop.events_cnt); 4085 debugfs_create_atomic_t("num_rqs", 0400, root, 4086 &dev->delay_drop.rqs_cnt); 4087 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4088 &fops_delay_drop_timeout); 4089 return 0; 4090 } 4091 4092 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4093 { 4094 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4095 return; 4096 4097 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4098 if (!dev->delay_drop.dir_debugfs) 4099 return; 4100 4101 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4102 dev->delay_drop.dir_debugfs = NULL; 4103 } 4104 4105 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4106 { 4107 dev->mdev_events.notifier_call = mlx5_ib_event; 4108 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4109 return 0; 4110 } 4111 4112 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4113 { 4114 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4115 } 4116 4117 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4118 const struct mlx5_ib_profile *profile, 4119 int stage) 4120 { 4121 dev->ib_active = false; 4122 4123 /* Number of stages to cleanup */ 4124 while (stage) { 4125 stage--; 4126 if (profile->stage[stage].cleanup) 4127 profile->stage[stage].cleanup(dev); 4128 } 4129 4130 kfree(dev->port); 4131 ib_dealloc_device(&dev->ib_dev); 4132 } 4133 4134 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4135 const struct mlx5_ib_profile *profile) 4136 { 4137 int err; 4138 int i; 4139 4140 dev->profile = profile; 4141 4142 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4143 if (profile->stage[i].init) { 4144 err = profile->stage[i].init(dev); 4145 if (err) 4146 goto err_out; 4147 } 4148 } 4149 4150 dev->ib_active = true; 4151 return 0; 4152 4153 err_out: 4154 /* Clean up stages which were initialized */ 4155 while (i) { 4156 i--; 4157 if (profile->stage[i].cleanup) 4158 profile->stage[i].cleanup(dev); 4159 } 4160 return -ENOMEM; 4161 } 4162 4163 static const struct mlx5_ib_profile pf_profile = { 4164 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4165 mlx5_ib_stage_init_init, 4166 mlx5_ib_stage_init_cleanup), 4167 STAGE_CREATE(MLX5_IB_STAGE_FS, 4168 mlx5_ib_fs_init, 4169 mlx5_ib_fs_cleanup), 4170 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4171 mlx5_ib_stage_caps_init, 4172 mlx5_ib_stage_caps_cleanup), 4173 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4174 mlx5_ib_stage_non_default_cb, 4175 NULL), 4176 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4177 mlx5_ib_roce_init, 4178 mlx5_ib_roce_cleanup), 4179 STAGE_CREATE(MLX5_IB_STAGE_QP, 4180 mlx5_init_qp_table, 4181 mlx5_cleanup_qp_table), 4182 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4183 mlx5_init_srq_table, 4184 mlx5_cleanup_srq_table), 4185 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4186 mlx5_ib_dev_res_init, 4187 mlx5_ib_dev_res_cleanup), 4188 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4189 mlx5_ib_stage_dev_notifier_init, 4190 mlx5_ib_stage_dev_notifier_cleanup), 4191 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4192 mlx5_ib_odp_init_one, 4193 mlx5_ib_odp_cleanup_one), 4194 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4195 mlx5_ib_counters_init, 4196 mlx5_ib_counters_cleanup), 4197 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4198 mlx5_ib_stage_cong_debugfs_init, 4199 mlx5_ib_stage_cong_debugfs_cleanup), 4200 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4201 mlx5_ib_stage_uar_init, 4202 mlx5_ib_stage_uar_cleanup), 4203 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4204 mlx5_ib_stage_bfrag_init, 4205 mlx5_ib_stage_bfrag_cleanup), 4206 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4207 NULL, 4208 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4209 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4210 mlx5_ib_devx_init, 4211 mlx5_ib_devx_cleanup), 4212 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4213 mlx5_ib_stage_ib_reg_init, 4214 mlx5_ib_stage_ib_reg_cleanup), 4215 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4216 mlx5_ib_stage_post_ib_reg_umr_init, 4217 NULL), 4218 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4219 mlx5_ib_stage_delay_drop_init, 4220 mlx5_ib_stage_delay_drop_cleanup), 4221 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4222 mlx5_ib_restrack_init, 4223 NULL), 4224 }; 4225 4226 const struct mlx5_ib_profile raw_eth_profile = { 4227 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4228 mlx5_ib_stage_init_init, 4229 mlx5_ib_stage_init_cleanup), 4230 STAGE_CREATE(MLX5_IB_STAGE_FS, 4231 mlx5_ib_fs_init, 4232 mlx5_ib_fs_cleanup), 4233 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4234 mlx5_ib_stage_caps_init, 4235 mlx5_ib_stage_caps_cleanup), 4236 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4237 mlx5_ib_stage_raw_eth_non_default_cb, 4238 NULL), 4239 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4240 mlx5_ib_roce_init, 4241 mlx5_ib_roce_cleanup), 4242 STAGE_CREATE(MLX5_IB_STAGE_QP, 4243 mlx5_init_qp_table, 4244 mlx5_cleanup_qp_table), 4245 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4246 mlx5_init_srq_table, 4247 mlx5_cleanup_srq_table), 4248 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4249 mlx5_ib_dev_res_init, 4250 mlx5_ib_dev_res_cleanup), 4251 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4252 mlx5_ib_stage_dev_notifier_init, 4253 mlx5_ib_stage_dev_notifier_cleanup), 4254 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4255 mlx5_ib_counters_init, 4256 mlx5_ib_counters_cleanup), 4257 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4258 mlx5_ib_stage_cong_debugfs_init, 4259 mlx5_ib_stage_cong_debugfs_cleanup), 4260 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4261 mlx5_ib_stage_uar_init, 4262 mlx5_ib_stage_uar_cleanup), 4263 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4264 mlx5_ib_stage_bfrag_init, 4265 mlx5_ib_stage_bfrag_cleanup), 4266 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4267 NULL, 4268 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4269 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4270 mlx5_ib_devx_init, 4271 mlx5_ib_devx_cleanup), 4272 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4273 mlx5_ib_stage_ib_reg_init, 4274 mlx5_ib_stage_ib_reg_cleanup), 4275 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4276 mlx5_ib_stage_post_ib_reg_umr_init, 4277 NULL), 4278 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4279 mlx5_ib_stage_delay_drop_init, 4280 mlx5_ib_stage_delay_drop_cleanup), 4281 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4282 mlx5_ib_restrack_init, 4283 NULL), 4284 }; 4285 4286 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4287 const struct auxiliary_device_id *id) 4288 { 4289 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4290 struct mlx5_core_dev *mdev = idev->mdev; 4291 struct mlx5_ib_multiport_info *mpi; 4292 struct mlx5_ib_dev *dev; 4293 bool bound = false; 4294 int err; 4295 4296 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4297 if (!mpi) 4298 return -ENOMEM; 4299 4300 mpi->mdev = mdev; 4301 err = mlx5_query_nic_vport_system_image_guid(mdev, 4302 &mpi->sys_image_guid); 4303 if (err) { 4304 kfree(mpi); 4305 return err; 4306 } 4307 4308 mutex_lock(&mlx5_ib_multiport_mutex); 4309 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4310 if (dev->sys_image_guid == mpi->sys_image_guid) 4311 bound = mlx5_ib_bind_slave_port(dev, mpi); 4312 4313 if (bound) { 4314 rdma_roce_rescan_device(&dev->ib_dev); 4315 mpi->ibdev->ib_active = true; 4316 break; 4317 } 4318 } 4319 4320 if (!bound) { 4321 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4322 dev_dbg(mdev->device, 4323 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4324 } 4325 mutex_unlock(&mlx5_ib_multiport_mutex); 4326 4327 auxiliary_set_drvdata(adev, mpi); 4328 return 0; 4329 } 4330 4331 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4332 { 4333 struct mlx5_ib_multiport_info *mpi; 4334 4335 mpi = auxiliary_get_drvdata(adev); 4336 mutex_lock(&mlx5_ib_multiport_mutex); 4337 if (mpi->ibdev) 4338 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4339 else 4340 list_del(&mpi->list); 4341 mutex_unlock(&mlx5_ib_multiport_mutex); 4342 kfree(mpi); 4343 } 4344 4345 static int mlx5r_probe(struct auxiliary_device *adev, 4346 const struct auxiliary_device_id *id) 4347 { 4348 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4349 struct mlx5_core_dev *mdev = idev->mdev; 4350 const struct mlx5_ib_profile *profile; 4351 int port_type_cap, num_ports, ret; 4352 enum rdma_link_layer ll; 4353 struct mlx5_ib_dev *dev; 4354 4355 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4356 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4357 4358 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4359 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4360 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4361 if (!dev) 4362 return -ENOMEM; 4363 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4364 GFP_KERNEL); 4365 if (!dev->port) { 4366 ib_dealloc_device(&dev->ib_dev); 4367 return -ENOMEM; 4368 } 4369 4370 dev->mdev = mdev; 4371 dev->num_ports = num_ports; 4372 4373 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4374 profile = &raw_eth_profile; 4375 else 4376 profile = &pf_profile; 4377 4378 ret = __mlx5_ib_add(dev, profile); 4379 if (ret) { 4380 kfree(dev->port); 4381 ib_dealloc_device(&dev->ib_dev); 4382 return ret; 4383 } 4384 4385 auxiliary_set_drvdata(adev, dev); 4386 return 0; 4387 } 4388 4389 static void mlx5r_remove(struct auxiliary_device *adev) 4390 { 4391 struct mlx5_ib_dev *dev; 4392 4393 dev = auxiliary_get_drvdata(adev); 4394 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4395 } 4396 4397 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4398 { .name = MLX5_ADEV_NAME ".multiport", }, 4399 {}, 4400 }; 4401 4402 static const struct auxiliary_device_id mlx5r_id_table[] = { 4403 { .name = MLX5_ADEV_NAME ".rdma", }, 4404 {}, 4405 }; 4406 4407 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4408 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4409 4410 static struct auxiliary_driver mlx5r_mp_driver = { 4411 .name = "multiport", 4412 .probe = mlx5r_mp_probe, 4413 .remove = mlx5r_mp_remove, 4414 .id_table = mlx5r_mp_id_table, 4415 }; 4416 4417 static struct auxiliary_driver mlx5r_driver = { 4418 .name = "rdma", 4419 .probe = mlx5r_probe, 4420 .remove = mlx5r_remove, 4421 .id_table = mlx5r_id_table, 4422 }; 4423 4424 static int __init mlx5_ib_init(void) 4425 { 4426 int ret; 4427 4428 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4429 if (!xlt_emergency_page) 4430 return -ENOMEM; 4431 4432 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4433 if (!mlx5_ib_event_wq) { 4434 free_page((unsigned long)xlt_emergency_page); 4435 return -ENOMEM; 4436 } 4437 4438 ret = mlx5_ib_qp_event_init(); 4439 if (ret) 4440 goto qp_event_err; 4441 4442 mlx5_ib_odp_init(); 4443 ret = mlx5r_rep_init(); 4444 if (ret) 4445 goto rep_err; 4446 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4447 if (ret) 4448 goto mp_err; 4449 ret = auxiliary_driver_register(&mlx5r_driver); 4450 if (ret) 4451 goto drv_err; 4452 return 0; 4453 4454 drv_err: 4455 auxiliary_driver_unregister(&mlx5r_mp_driver); 4456 mp_err: 4457 mlx5r_rep_cleanup(); 4458 rep_err: 4459 mlx5_ib_qp_event_cleanup(); 4460 qp_event_err: 4461 destroy_workqueue(mlx5_ib_event_wq); 4462 free_page((unsigned long)xlt_emergency_page); 4463 return ret; 4464 } 4465 4466 static void __exit mlx5_ib_cleanup(void) 4467 { 4468 auxiliary_driver_unregister(&mlx5r_driver); 4469 auxiliary_driver_unregister(&mlx5r_mp_driver); 4470 mlx5r_rep_cleanup(); 4471 4472 mlx5_ib_qp_event_cleanup(); 4473 destroy_workqueue(mlx5_ib_event_wq); 4474 free_page((unsigned long)xlt_emergency_page); 4475 } 4476 4477 module_init(mlx5_ib_init); 4478 module_exit(mlx5_ib_cleanup); 4479