1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include "srq.h" 64 #include <linux/mlx5/fs_helpers.h> 65 #include <linux/mlx5/accel.h> 66 #include <rdma/uverbs_std_types.h> 67 #include <rdma/mlx5_user_ioctl_verbs.h> 68 #include <rdma/mlx5_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME mlx5_ib 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #define DRIVER_NAME "mlx5_ib" 74 #define DRIVER_VERSION "5.0-0" 75 76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 78 MODULE_LICENSE("Dual BSD/GPL"); 79 80 static char mlx5_version[] = 81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 82 DRIVER_VERSION "\n"; 83 84 struct mlx5_ib_event_work { 85 struct work_struct work; 86 union { 87 struct mlx5_ib_dev *dev; 88 struct mlx5_ib_multiport_info *mpi; 89 }; 90 bool is_slave; 91 unsigned int event; 92 void *param; 93 }; 94 95 enum { 96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 97 }; 98 99 static struct workqueue_struct *mlx5_ib_event_wq; 100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 101 static LIST_HEAD(mlx5_ib_dev_list); 102 /* 103 * This mutex should be held when accessing either of the above lists 104 */ 105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 106 107 /* We can't use an array for xlt_emergency_page because dma_map_single 108 * doesn't work on kernel modules memory 109 */ 110 static unsigned long xlt_emergency_page; 111 static struct mutex xlt_emergency_page_mutex; 112 113 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 114 { 115 struct mlx5_ib_dev *dev; 116 117 mutex_lock(&mlx5_ib_multiport_mutex); 118 dev = mpi->ibdev; 119 mutex_unlock(&mlx5_ib_multiport_mutex); 120 return dev; 121 } 122 123 static enum rdma_link_layer 124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 125 { 126 switch (port_type_cap) { 127 case MLX5_CAP_PORT_TYPE_IB: 128 return IB_LINK_LAYER_INFINIBAND; 129 case MLX5_CAP_PORT_TYPE_ETH: 130 return IB_LINK_LAYER_ETHERNET; 131 default: 132 return IB_LINK_LAYER_UNSPECIFIED; 133 } 134 } 135 136 static enum rdma_link_layer 137 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 141 142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 143 } 144 145 static int get_port_state(struct ib_device *ibdev, 146 u8 port_num, 147 enum ib_port_state *state) 148 { 149 struct ib_port_attr attr; 150 int ret; 151 152 memset(&attr, 0, sizeof(attr)); 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 154 if (!ret) 155 *state = attr.state; 156 return ret; 157 } 158 159 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 160 struct net_device *ndev, 161 u8 *port_num) 162 { 163 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 164 struct net_device *rep_ndev; 165 struct mlx5_ib_port *port; 166 int i; 167 168 for (i = 0; i < dev->num_ports; i++) { 169 port = &dev->port[i]; 170 if (!port->rep) 171 continue; 172 173 read_lock(&port->roce.netdev_lock); 174 rep_ndev = mlx5_ib_get_rep_netdev(esw, 175 port->rep->vport); 176 if (rep_ndev == ndev) { 177 read_unlock(&port->roce.netdev_lock); 178 *port_num = i + 1; 179 return &port->roce; 180 } 181 read_unlock(&port->roce.netdev_lock); 182 } 183 184 return NULL; 185 } 186 187 static int mlx5_netdev_event(struct notifier_block *this, 188 unsigned long event, void *ptr) 189 { 190 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 191 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 192 u8 port_num = roce->native_port_num; 193 struct mlx5_core_dev *mdev; 194 struct mlx5_ib_dev *ibdev; 195 196 ibdev = roce->dev; 197 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 198 if (!mdev) 199 return NOTIFY_DONE; 200 201 switch (event) { 202 case NETDEV_REGISTER: 203 /* Should already be registered during the load */ 204 if (ibdev->is_rep) 205 break; 206 write_lock(&roce->netdev_lock); 207 if (ndev->dev.parent == mdev->device) 208 roce->netdev = ndev; 209 write_unlock(&roce->netdev_lock); 210 break; 211 212 case NETDEV_UNREGISTER: 213 /* In case of reps, ib device goes away before the netdevs */ 214 write_lock(&roce->netdev_lock); 215 if (roce->netdev == ndev) 216 roce->netdev = NULL; 217 write_unlock(&roce->netdev_lock); 218 break; 219 220 case NETDEV_CHANGE: 221 case NETDEV_UP: 222 case NETDEV_DOWN: { 223 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 224 struct net_device *upper = NULL; 225 226 if (lag_ndev) { 227 upper = netdev_master_upper_dev_get(lag_ndev); 228 dev_put(lag_ndev); 229 } 230 231 if (ibdev->is_rep) 232 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 233 if (!roce) 234 return NOTIFY_DONE; 235 if ((upper == ndev || (!upper && ndev == roce->netdev)) 236 && ibdev->ib_active) { 237 struct ib_event ibev = { }; 238 enum ib_port_state port_state; 239 240 if (get_port_state(&ibdev->ib_dev, port_num, 241 &port_state)) 242 goto done; 243 244 if (roce->last_port_state == port_state) 245 goto done; 246 247 roce->last_port_state = port_state; 248 ibev.device = &ibdev->ib_dev; 249 if (port_state == IB_PORT_DOWN) 250 ibev.event = IB_EVENT_PORT_ERR; 251 else if (port_state == IB_PORT_ACTIVE) 252 ibev.event = IB_EVENT_PORT_ACTIVE; 253 else 254 goto done; 255 256 ibev.element.port_num = port_num; 257 ib_dispatch_event(&ibev); 258 } 259 break; 260 } 261 262 default: 263 break; 264 } 265 done: 266 mlx5_ib_put_native_port_mdev(ibdev, port_num); 267 return NOTIFY_DONE; 268 } 269 270 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 271 u8 port_num) 272 { 273 struct mlx5_ib_dev *ibdev = to_mdev(device); 274 struct net_device *ndev; 275 struct mlx5_core_dev *mdev; 276 277 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 278 if (!mdev) 279 return NULL; 280 281 ndev = mlx5_lag_get_roce_netdev(mdev); 282 if (ndev) 283 goto out; 284 285 /* Ensure ndev does not disappear before we invoke dev_hold() 286 */ 287 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 288 ndev = ibdev->port[port_num - 1].roce.netdev; 289 if (ndev) 290 dev_hold(ndev); 291 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 292 293 out: 294 mlx5_ib_put_native_port_mdev(ibdev, port_num); 295 return ndev; 296 } 297 298 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 299 u8 ib_port_num, 300 u8 *native_port_num) 301 { 302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 303 ib_port_num); 304 struct mlx5_core_dev *mdev = NULL; 305 struct mlx5_ib_multiport_info *mpi; 306 struct mlx5_ib_port *port; 307 308 if (!mlx5_core_mp_enabled(ibdev->mdev) || 309 ll != IB_LINK_LAYER_ETHERNET) { 310 if (native_port_num) 311 *native_port_num = ib_port_num; 312 return ibdev->mdev; 313 } 314 315 if (native_port_num) 316 *native_port_num = 1; 317 318 port = &ibdev->port[ib_port_num - 1]; 319 if (!port) 320 return NULL; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 324 if (mpi && !mpi->unaffiliate) { 325 mdev = mpi->mdev; 326 /* If it's the master no need to refcount, it'll exist 327 * as long as the ib_dev exists. 328 */ 329 if (!mpi->is_master) 330 mpi->mdev_refcnt++; 331 } 332 spin_unlock(&port->mp.mpi_lock); 333 334 return mdev; 335 } 336 337 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 338 { 339 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 340 port_num); 341 struct mlx5_ib_multiport_info *mpi; 342 struct mlx5_ib_port *port; 343 344 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 345 return; 346 347 port = &ibdev->port[port_num - 1]; 348 349 spin_lock(&port->mp.mpi_lock); 350 mpi = ibdev->port[port_num - 1].mp.mpi; 351 if (mpi->is_master) 352 goto out; 353 354 mpi->mdev_refcnt--; 355 if (mpi->unaffiliate) 356 complete(&mpi->unref_comp); 357 out: 358 spin_unlock(&port->mp.mpi_lock); 359 } 360 361 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed, 362 u8 *active_width) 363 { 364 switch (eth_proto_oper) { 365 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 366 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 367 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 368 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 369 *active_width = IB_WIDTH_1X; 370 *active_speed = IB_SPEED_SDR; 371 break; 372 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 373 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 374 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 376 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 377 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 378 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 379 *active_width = IB_WIDTH_1X; 380 *active_speed = IB_SPEED_QDR; 381 break; 382 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 383 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 384 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 385 *active_width = IB_WIDTH_1X; 386 *active_speed = IB_SPEED_EDR; 387 break; 388 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 389 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 390 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 391 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 392 *active_width = IB_WIDTH_4X; 393 *active_speed = IB_SPEED_QDR; 394 break; 395 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 396 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 397 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_HDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 402 *active_width = IB_WIDTH_4X; 403 *active_speed = IB_SPEED_FDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 406 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 407 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 408 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 409 *active_width = IB_WIDTH_4X; 410 *active_speed = IB_SPEED_EDR; 411 break; 412 default: 413 return -EINVAL; 414 } 415 416 return 0; 417 } 418 419 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 420 u8 *active_width) 421 { 422 switch (eth_proto_oper) { 423 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 424 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 425 *active_width = IB_WIDTH_1X; 426 *active_speed = IB_SPEED_SDR; 427 break; 428 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 429 *active_width = IB_WIDTH_1X; 430 *active_speed = IB_SPEED_DDR; 431 break; 432 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 433 *active_width = IB_WIDTH_1X; 434 *active_speed = IB_SPEED_QDR; 435 break; 436 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 437 *active_width = IB_WIDTH_4X; 438 *active_speed = IB_SPEED_QDR; 439 break; 440 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 441 *active_width = IB_WIDTH_1X; 442 *active_speed = IB_SPEED_EDR; 443 break; 444 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 445 *active_width = IB_WIDTH_2X; 446 *active_speed = IB_SPEED_EDR; 447 break; 448 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 449 *active_width = IB_WIDTH_1X; 450 *active_speed = IB_SPEED_HDR; 451 break; 452 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 453 *active_width = IB_WIDTH_4X; 454 *active_speed = IB_SPEED_EDR; 455 break; 456 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 457 *active_width = IB_WIDTH_2X; 458 *active_speed = IB_SPEED_HDR; 459 break; 460 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 461 *active_width = IB_WIDTH_4X; 462 *active_speed = IB_SPEED_HDR; 463 break; 464 default: 465 return -EINVAL; 466 } 467 468 return 0; 469 } 470 471 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 472 u8 *active_width, bool ext) 473 { 474 return ext ? 475 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 476 active_width) : 477 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 478 active_width); 479 } 480 481 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 482 struct ib_port_attr *props) 483 { 484 struct mlx5_ib_dev *dev = to_mdev(device); 485 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 486 struct mlx5_core_dev *mdev; 487 struct net_device *ndev, *upper; 488 enum ib_mtu ndev_ib_mtu; 489 bool put_mdev = true; 490 u16 qkey_viol_cntr; 491 u32 eth_prot_oper; 492 u8 mdev_port_num; 493 bool ext; 494 int err; 495 496 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 497 if (!mdev) { 498 /* This means the port isn't affiliated yet. Get the 499 * info for the master port instead. 500 */ 501 put_mdev = false; 502 mdev = dev->mdev; 503 mdev_port_num = 1; 504 port_num = 1; 505 } 506 507 /* Possible bad flows are checked before filling out props so in case 508 * of an error it will still be zeroed out. 509 * Use native port in case of reps 510 */ 511 if (dev->is_rep) 512 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 513 1); 514 else 515 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 516 mdev_port_num); 517 if (err) 518 goto out; 519 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 520 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 521 522 props->active_width = IB_WIDTH_4X; 523 props->active_speed = IB_SPEED_QDR; 524 525 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 526 &props->active_width, ext); 527 528 props->port_cap_flags |= IB_PORT_CM_SUP; 529 props->ip_gids = true; 530 531 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 532 roce_address_table_size); 533 props->max_mtu = IB_MTU_4096; 534 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 535 props->pkey_tbl_len = 1; 536 props->state = IB_PORT_DOWN; 537 props->phys_state = 3; 538 539 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 540 props->qkey_viol_cntr = qkey_viol_cntr; 541 542 /* If this is a stub query for an unaffiliated port stop here */ 543 if (!put_mdev) 544 goto out; 545 546 ndev = mlx5_ib_get_netdev(device, port_num); 547 if (!ndev) 548 goto out; 549 550 if (dev->lag_active) { 551 rcu_read_lock(); 552 upper = netdev_master_upper_dev_get_rcu(ndev); 553 if (upper) { 554 dev_put(ndev); 555 ndev = upper; 556 dev_hold(ndev); 557 } 558 rcu_read_unlock(); 559 } 560 561 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 562 props->state = IB_PORT_ACTIVE; 563 props->phys_state = 5; 564 } 565 566 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 567 568 dev_put(ndev); 569 570 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 571 out: 572 if (put_mdev) 573 mlx5_ib_put_native_port_mdev(dev, port_num); 574 return err; 575 } 576 577 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 578 unsigned int index, const union ib_gid *gid, 579 const struct ib_gid_attr *attr) 580 { 581 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 582 u16 vlan_id = 0xffff; 583 u8 roce_version = 0; 584 u8 roce_l3_type = 0; 585 u8 mac[ETH_ALEN]; 586 int ret; 587 588 if (gid) { 589 gid_type = attr->gid_type; 590 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 591 if (ret) 592 return ret; 593 } 594 595 switch (gid_type) { 596 case IB_GID_TYPE_IB: 597 roce_version = MLX5_ROCE_VERSION_1; 598 break; 599 case IB_GID_TYPE_ROCE_UDP_ENCAP: 600 roce_version = MLX5_ROCE_VERSION_2; 601 if (ipv6_addr_v4mapped((void *)gid)) 602 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 603 else 604 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 605 break; 606 607 default: 608 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 609 } 610 611 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 612 roce_l3_type, gid->raw, mac, 613 vlan_id < VLAN_CFI_MASK, vlan_id, 614 port_num); 615 } 616 617 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 618 __always_unused void **context) 619 { 620 return set_roce_addr(to_mdev(attr->device), attr->port_num, 621 attr->index, &attr->gid, attr); 622 } 623 624 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 625 __always_unused void **context) 626 { 627 return set_roce_addr(to_mdev(attr->device), attr->port_num, 628 attr->index, NULL, NULL); 629 } 630 631 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 632 const struct ib_gid_attr *attr) 633 { 634 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 635 return 0; 636 637 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 638 } 639 640 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 641 { 642 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 643 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 644 return 0; 645 } 646 647 enum { 648 MLX5_VPORT_ACCESS_METHOD_MAD, 649 MLX5_VPORT_ACCESS_METHOD_HCA, 650 MLX5_VPORT_ACCESS_METHOD_NIC, 651 }; 652 653 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 654 { 655 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 656 return MLX5_VPORT_ACCESS_METHOD_MAD; 657 658 if (mlx5_ib_port_link_layer(ibdev, 1) == 659 IB_LINK_LAYER_ETHERNET) 660 return MLX5_VPORT_ACCESS_METHOD_NIC; 661 662 return MLX5_VPORT_ACCESS_METHOD_HCA; 663 } 664 665 static void get_atomic_caps(struct mlx5_ib_dev *dev, 666 u8 atomic_size_qp, 667 struct ib_device_attr *props) 668 { 669 u8 tmp; 670 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 671 u8 atomic_req_8B_endianness_mode = 672 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 673 674 /* Check if HW supports 8 bytes standard atomic operations and capable 675 * of host endianness respond 676 */ 677 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 678 if (((atomic_operations & tmp) == tmp) && 679 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 680 (atomic_req_8B_endianness_mode)) { 681 props->atomic_cap = IB_ATOMIC_HCA; 682 } else { 683 props->atomic_cap = IB_ATOMIC_NONE; 684 } 685 } 686 687 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 688 struct ib_device_attr *props) 689 { 690 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 691 692 get_atomic_caps(dev, atomic_size_qp, props); 693 } 694 695 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 696 struct ib_device_attr *props) 697 { 698 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 699 700 get_atomic_caps(dev, atomic_size_qp, props); 701 } 702 703 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 704 { 705 struct ib_device_attr props = {}; 706 707 get_atomic_caps_dc(dev, &props); 708 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 709 } 710 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 711 __be64 *sys_image_guid) 712 { 713 struct mlx5_ib_dev *dev = to_mdev(ibdev); 714 struct mlx5_core_dev *mdev = dev->mdev; 715 u64 tmp; 716 int err; 717 718 switch (mlx5_get_vport_access_method(ibdev)) { 719 case MLX5_VPORT_ACCESS_METHOD_MAD: 720 return mlx5_query_mad_ifc_system_image_guid(ibdev, 721 sys_image_guid); 722 723 case MLX5_VPORT_ACCESS_METHOD_HCA: 724 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 725 break; 726 727 case MLX5_VPORT_ACCESS_METHOD_NIC: 728 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 729 break; 730 731 default: 732 return -EINVAL; 733 } 734 735 if (!err) 736 *sys_image_guid = cpu_to_be64(tmp); 737 738 return err; 739 740 } 741 742 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 743 u16 *max_pkeys) 744 { 745 struct mlx5_ib_dev *dev = to_mdev(ibdev); 746 struct mlx5_core_dev *mdev = dev->mdev; 747 748 switch (mlx5_get_vport_access_method(ibdev)) { 749 case MLX5_VPORT_ACCESS_METHOD_MAD: 750 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 751 752 case MLX5_VPORT_ACCESS_METHOD_HCA: 753 case MLX5_VPORT_ACCESS_METHOD_NIC: 754 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 755 pkey_table_size)); 756 return 0; 757 758 default: 759 return -EINVAL; 760 } 761 } 762 763 static int mlx5_query_vendor_id(struct ib_device *ibdev, 764 u32 *vendor_id) 765 { 766 struct mlx5_ib_dev *dev = to_mdev(ibdev); 767 768 switch (mlx5_get_vport_access_method(ibdev)) { 769 case MLX5_VPORT_ACCESS_METHOD_MAD: 770 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 771 772 case MLX5_VPORT_ACCESS_METHOD_HCA: 773 case MLX5_VPORT_ACCESS_METHOD_NIC: 774 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 775 776 default: 777 return -EINVAL; 778 } 779 } 780 781 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 782 __be64 *node_guid) 783 { 784 u64 tmp; 785 int err; 786 787 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 788 case MLX5_VPORT_ACCESS_METHOD_MAD: 789 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 790 791 case MLX5_VPORT_ACCESS_METHOD_HCA: 792 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 793 break; 794 795 case MLX5_VPORT_ACCESS_METHOD_NIC: 796 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 797 break; 798 799 default: 800 return -EINVAL; 801 } 802 803 if (!err) 804 *node_guid = cpu_to_be64(tmp); 805 806 return err; 807 } 808 809 struct mlx5_reg_node_desc { 810 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 811 }; 812 813 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 814 { 815 struct mlx5_reg_node_desc in; 816 817 if (mlx5_use_mad_ifc(dev)) 818 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 819 820 memset(&in, 0, sizeof(in)); 821 822 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 823 sizeof(struct mlx5_reg_node_desc), 824 MLX5_REG_NODE_DESC, 0, 0); 825 } 826 827 static int mlx5_ib_query_device(struct ib_device *ibdev, 828 struct ib_device_attr *props, 829 struct ib_udata *uhw) 830 { 831 struct mlx5_ib_dev *dev = to_mdev(ibdev); 832 struct mlx5_core_dev *mdev = dev->mdev; 833 int err = -ENOMEM; 834 int max_sq_desc; 835 int max_rq_sg; 836 int max_sq_sg; 837 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 838 bool raw_support = !mlx5_core_mp_enabled(mdev); 839 struct mlx5_ib_query_device_resp resp = {}; 840 size_t resp_len; 841 u64 max_tso; 842 843 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 844 if (uhw->outlen && uhw->outlen < resp_len) 845 return -EINVAL; 846 else 847 resp.response_length = resp_len; 848 849 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 850 return -EINVAL; 851 852 memset(props, 0, sizeof(*props)); 853 err = mlx5_query_system_image_guid(ibdev, 854 &props->sys_image_guid); 855 if (err) 856 return err; 857 858 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 859 if (err) 860 return err; 861 862 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 863 if (err) 864 return err; 865 866 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 867 (fw_rev_min(dev->mdev) << 16) | 868 fw_rev_sub(dev->mdev); 869 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 870 IB_DEVICE_PORT_ACTIVE_EVENT | 871 IB_DEVICE_SYS_IMAGE_GUID | 872 IB_DEVICE_RC_RNR_NAK_GEN; 873 874 if (MLX5_CAP_GEN(mdev, pkv)) 875 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 876 if (MLX5_CAP_GEN(mdev, qkv)) 877 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 878 if (MLX5_CAP_GEN(mdev, apm)) 879 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 880 if (MLX5_CAP_GEN(mdev, xrc)) 881 props->device_cap_flags |= IB_DEVICE_XRC; 882 if (MLX5_CAP_GEN(mdev, imaicl)) { 883 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 884 IB_DEVICE_MEM_WINDOW_TYPE_2B; 885 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 886 /* We support 'Gappy' memory registration too */ 887 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 888 } 889 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 890 if (MLX5_CAP_GEN(mdev, sho)) { 891 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 892 /* At this stage no support for signature handover */ 893 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 894 IB_PROT_T10DIF_TYPE_2 | 895 IB_PROT_T10DIF_TYPE_3; 896 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 897 IB_GUARD_T10DIF_CSUM; 898 } 899 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 900 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 901 902 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 903 if (MLX5_CAP_ETH(mdev, csum_cap)) { 904 /* Legacy bit to support old userspace libraries */ 905 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 906 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 907 } 908 909 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 910 props->raw_packet_caps |= 911 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 912 913 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 914 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 915 if (max_tso) { 916 resp.tso_caps.max_tso = 1 << max_tso; 917 resp.tso_caps.supported_qpts |= 918 1 << IB_QPT_RAW_PACKET; 919 resp.response_length += sizeof(resp.tso_caps); 920 } 921 } 922 923 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 924 resp.rss_caps.rx_hash_function = 925 MLX5_RX_HASH_FUNC_TOEPLITZ; 926 resp.rss_caps.rx_hash_fields_mask = 927 MLX5_RX_HASH_SRC_IPV4 | 928 MLX5_RX_HASH_DST_IPV4 | 929 MLX5_RX_HASH_SRC_IPV6 | 930 MLX5_RX_HASH_DST_IPV6 | 931 MLX5_RX_HASH_SRC_PORT_TCP | 932 MLX5_RX_HASH_DST_PORT_TCP | 933 MLX5_RX_HASH_SRC_PORT_UDP | 934 MLX5_RX_HASH_DST_PORT_UDP | 935 MLX5_RX_HASH_INNER; 936 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 937 MLX5_ACCEL_IPSEC_CAP_DEVICE) 938 resp.rss_caps.rx_hash_fields_mask |= 939 MLX5_RX_HASH_IPSEC_SPI; 940 resp.response_length += sizeof(resp.rss_caps); 941 } 942 } else { 943 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 944 resp.response_length += sizeof(resp.tso_caps); 945 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 946 resp.response_length += sizeof(resp.rss_caps); 947 } 948 949 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 950 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 951 props->device_cap_flags |= IB_DEVICE_UD_TSO; 952 } 953 954 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 955 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 956 raw_support) 957 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 958 959 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 960 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 961 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 962 963 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 964 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 965 raw_support) { 966 /* Legacy bit to support old userspace libraries */ 967 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 968 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 969 } 970 971 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 972 props->max_dm_size = 973 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 974 } 975 976 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 977 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 978 979 if (MLX5_CAP_GEN(mdev, end_pad)) 980 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 981 982 props->vendor_part_id = mdev->pdev->device; 983 props->hw_ver = mdev->pdev->revision; 984 985 props->max_mr_size = ~0ull; 986 props->page_size_cap = ~(min_page_size - 1); 987 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 988 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 989 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 990 sizeof(struct mlx5_wqe_data_seg); 991 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 992 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 993 sizeof(struct mlx5_wqe_raddr_seg)) / 994 sizeof(struct mlx5_wqe_data_seg); 995 props->max_send_sge = max_sq_sg; 996 props->max_recv_sge = max_rq_sg; 997 props->max_sge_rd = MLX5_MAX_SGE_RD; 998 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 999 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1000 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1001 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1002 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1003 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1004 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1005 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1006 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1007 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1008 props->max_srq_sge = max_rq_sg - 1; 1009 props->max_fast_reg_page_list_len = 1010 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1011 get_atomic_caps_qp(dev, props); 1012 props->masked_atomic_cap = IB_ATOMIC_NONE; 1013 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1014 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1015 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1016 props->max_mcast_grp; 1017 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 1018 props->max_ah = INT_MAX; 1019 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1020 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1021 1022 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1023 if (MLX5_CAP_GEN(mdev, pg)) 1024 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1025 props->odp_caps = dev->odp_caps; 1026 } 1027 1028 if (MLX5_CAP_GEN(mdev, cd)) 1029 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1030 1031 if (!mlx5_core_is_pf(mdev)) 1032 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1033 1034 if (mlx5_ib_port_link_layer(ibdev, 1) == 1035 IB_LINK_LAYER_ETHERNET && raw_support) { 1036 props->rss_caps.max_rwq_indirection_tables = 1037 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1038 props->rss_caps.max_rwq_indirection_table_size = 1039 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1040 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1041 props->max_wq_type_rq = 1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1043 } 1044 1045 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1046 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1047 props->tm_caps.max_num_tags = 1048 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1049 props->tm_caps.flags = IB_TM_CAP_RC; 1050 props->tm_caps.max_ops = 1051 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1052 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1053 } 1054 1055 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1056 props->cq_caps.max_cq_moderation_count = 1057 MLX5_MAX_CQ_COUNT; 1058 props->cq_caps.max_cq_moderation_period = 1059 MLX5_MAX_CQ_PERIOD; 1060 } 1061 1062 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 1063 resp.response_length += sizeof(resp.cqe_comp_caps); 1064 1065 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1066 resp.cqe_comp_caps.max_num = 1067 MLX5_CAP_GEN(dev->mdev, 1068 cqe_compression_max_num); 1069 1070 resp.cqe_comp_caps.supported_format = 1071 MLX5_IB_CQE_RES_FORMAT_HASH | 1072 MLX5_IB_CQE_RES_FORMAT_CSUM; 1073 1074 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1075 resp.cqe_comp_caps.supported_format |= 1076 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1077 } 1078 } 1079 1080 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 1081 raw_support) { 1082 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1083 MLX5_CAP_GEN(mdev, qos)) { 1084 resp.packet_pacing_caps.qp_rate_limit_max = 1085 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1086 resp.packet_pacing_caps.qp_rate_limit_min = 1087 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1088 resp.packet_pacing_caps.supported_qpts |= 1089 1 << IB_QPT_RAW_PACKET; 1090 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1091 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1092 resp.packet_pacing_caps.cap_flags |= 1093 MLX5_IB_PP_SUPPORT_BURST; 1094 } 1095 resp.response_length += sizeof(resp.packet_pacing_caps); 1096 } 1097 1098 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 1099 uhw->outlen)) { 1100 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1101 resp.mlx5_ib_support_multi_pkt_send_wqes = 1102 MLX5_IB_ALLOW_MPW; 1103 1104 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1105 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1106 MLX5_IB_SUPPORT_EMPW; 1107 1108 resp.response_length += 1109 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1110 } 1111 1112 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1113 resp.response_length += sizeof(resp.flags); 1114 1115 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1116 resp.flags |= 1117 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1118 1119 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1120 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1121 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1122 resp.flags |= 1123 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1124 1125 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1126 } 1127 1128 if (field_avail(typeof(resp), sw_parsing_caps, 1129 uhw->outlen)) { 1130 resp.response_length += sizeof(resp.sw_parsing_caps); 1131 if (MLX5_CAP_ETH(mdev, swp)) { 1132 resp.sw_parsing_caps.sw_parsing_offloads |= 1133 MLX5_IB_SW_PARSING; 1134 1135 if (MLX5_CAP_ETH(mdev, swp_csum)) 1136 resp.sw_parsing_caps.sw_parsing_offloads |= 1137 MLX5_IB_SW_PARSING_CSUM; 1138 1139 if (MLX5_CAP_ETH(mdev, swp_lso)) 1140 resp.sw_parsing_caps.sw_parsing_offloads |= 1141 MLX5_IB_SW_PARSING_LSO; 1142 1143 if (resp.sw_parsing_caps.sw_parsing_offloads) 1144 resp.sw_parsing_caps.supported_qpts = 1145 BIT(IB_QPT_RAW_PACKET); 1146 } 1147 } 1148 1149 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1150 raw_support) { 1151 resp.response_length += sizeof(resp.striding_rq_caps); 1152 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1153 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1154 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1155 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1156 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1157 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1158 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1159 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1160 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1161 resp.striding_rq_caps.supported_qpts = 1162 BIT(IB_QPT_RAW_PACKET); 1163 } 1164 } 1165 1166 if (field_avail(typeof(resp), tunnel_offloads_caps, 1167 uhw->outlen)) { 1168 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1170 resp.tunnel_offloads_caps |= 1171 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1173 resp.tunnel_offloads_caps |= 1174 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1176 resp.tunnel_offloads_caps |= 1177 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1178 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1179 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1180 resp.tunnel_offloads_caps |= 1181 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1182 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1183 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1184 resp.tunnel_offloads_caps |= 1185 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1186 } 1187 1188 if (uhw->outlen) { 1189 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1190 1191 if (err) 1192 return err; 1193 } 1194 1195 return 0; 1196 } 1197 1198 enum mlx5_ib_width { 1199 MLX5_IB_WIDTH_1X = 1 << 0, 1200 MLX5_IB_WIDTH_2X = 1 << 1, 1201 MLX5_IB_WIDTH_4X = 1 << 2, 1202 MLX5_IB_WIDTH_8X = 1 << 3, 1203 MLX5_IB_WIDTH_12X = 1 << 4 1204 }; 1205 1206 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1207 u8 *ib_width) 1208 { 1209 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1210 1211 if (active_width & MLX5_IB_WIDTH_1X) 1212 *ib_width = IB_WIDTH_1X; 1213 else if (active_width & MLX5_IB_WIDTH_2X) 1214 *ib_width = IB_WIDTH_2X; 1215 else if (active_width & MLX5_IB_WIDTH_4X) 1216 *ib_width = IB_WIDTH_4X; 1217 else if (active_width & MLX5_IB_WIDTH_8X) 1218 *ib_width = IB_WIDTH_8X; 1219 else if (active_width & MLX5_IB_WIDTH_12X) 1220 *ib_width = IB_WIDTH_12X; 1221 else { 1222 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1223 (int)active_width); 1224 *ib_width = IB_WIDTH_4X; 1225 } 1226 1227 return; 1228 } 1229 1230 static int mlx5_mtu_to_ib_mtu(int mtu) 1231 { 1232 switch (mtu) { 1233 case 256: return 1; 1234 case 512: return 2; 1235 case 1024: return 3; 1236 case 2048: return 4; 1237 case 4096: return 5; 1238 default: 1239 pr_warn("invalid mtu\n"); 1240 return -1; 1241 } 1242 } 1243 1244 enum ib_max_vl_num { 1245 __IB_MAX_VL_0 = 1, 1246 __IB_MAX_VL_0_1 = 2, 1247 __IB_MAX_VL_0_3 = 3, 1248 __IB_MAX_VL_0_7 = 4, 1249 __IB_MAX_VL_0_14 = 5, 1250 }; 1251 1252 enum mlx5_vl_hw_cap { 1253 MLX5_VL_HW_0 = 1, 1254 MLX5_VL_HW_0_1 = 2, 1255 MLX5_VL_HW_0_2 = 3, 1256 MLX5_VL_HW_0_3 = 4, 1257 MLX5_VL_HW_0_4 = 5, 1258 MLX5_VL_HW_0_5 = 6, 1259 MLX5_VL_HW_0_6 = 7, 1260 MLX5_VL_HW_0_7 = 8, 1261 MLX5_VL_HW_0_14 = 15 1262 }; 1263 1264 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1265 u8 *max_vl_num) 1266 { 1267 switch (vl_hw_cap) { 1268 case MLX5_VL_HW_0: 1269 *max_vl_num = __IB_MAX_VL_0; 1270 break; 1271 case MLX5_VL_HW_0_1: 1272 *max_vl_num = __IB_MAX_VL_0_1; 1273 break; 1274 case MLX5_VL_HW_0_3: 1275 *max_vl_num = __IB_MAX_VL_0_3; 1276 break; 1277 case MLX5_VL_HW_0_7: 1278 *max_vl_num = __IB_MAX_VL_0_7; 1279 break; 1280 case MLX5_VL_HW_0_14: 1281 *max_vl_num = __IB_MAX_VL_0_14; 1282 break; 1283 1284 default: 1285 return -EINVAL; 1286 } 1287 1288 return 0; 1289 } 1290 1291 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1292 struct ib_port_attr *props) 1293 { 1294 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1295 struct mlx5_core_dev *mdev = dev->mdev; 1296 struct mlx5_hca_vport_context *rep; 1297 u16 max_mtu; 1298 u16 oper_mtu; 1299 int err; 1300 u8 ib_link_width_oper; 1301 u8 vl_hw_cap; 1302 1303 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1304 if (!rep) { 1305 err = -ENOMEM; 1306 goto out; 1307 } 1308 1309 /* props being zeroed by the caller, avoid zeroing it here */ 1310 1311 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1312 if (err) 1313 goto out; 1314 1315 props->lid = rep->lid; 1316 props->lmc = rep->lmc; 1317 props->sm_lid = rep->sm_lid; 1318 props->sm_sl = rep->sm_sl; 1319 props->state = rep->vport_state; 1320 props->phys_state = rep->port_physical_state; 1321 props->port_cap_flags = rep->cap_mask1; 1322 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1323 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1324 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1325 props->bad_pkey_cntr = rep->pkey_violation_counter; 1326 props->qkey_viol_cntr = rep->qkey_violation_counter; 1327 props->subnet_timeout = rep->subnet_timeout; 1328 props->init_type_reply = rep->init_type_reply; 1329 1330 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1331 props->port_cap_flags2 = rep->cap_mask2; 1332 1333 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1334 if (err) 1335 goto out; 1336 1337 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1338 1339 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1340 if (err) 1341 goto out; 1342 1343 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1344 1345 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1346 1347 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1348 1349 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1350 1351 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1352 if (err) 1353 goto out; 1354 1355 err = translate_max_vl_num(ibdev, vl_hw_cap, 1356 &props->max_vl_num); 1357 out: 1358 kfree(rep); 1359 return err; 1360 } 1361 1362 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1363 struct ib_port_attr *props) 1364 { 1365 unsigned int count; 1366 int ret; 1367 1368 switch (mlx5_get_vport_access_method(ibdev)) { 1369 case MLX5_VPORT_ACCESS_METHOD_MAD: 1370 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1371 break; 1372 1373 case MLX5_VPORT_ACCESS_METHOD_HCA: 1374 ret = mlx5_query_hca_port(ibdev, port, props); 1375 break; 1376 1377 case MLX5_VPORT_ACCESS_METHOD_NIC: 1378 ret = mlx5_query_port_roce(ibdev, port, props); 1379 break; 1380 1381 default: 1382 ret = -EINVAL; 1383 } 1384 1385 if (!ret && props) { 1386 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1387 struct mlx5_core_dev *mdev; 1388 bool put_mdev = true; 1389 1390 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1391 if (!mdev) { 1392 /* If the port isn't affiliated yet query the master. 1393 * The master and slave will have the same values. 1394 */ 1395 mdev = dev->mdev; 1396 port = 1; 1397 put_mdev = false; 1398 } 1399 count = mlx5_core_reserved_gids_count(mdev); 1400 if (put_mdev) 1401 mlx5_ib_put_native_port_mdev(dev, port); 1402 props->gid_tbl_len -= count; 1403 } 1404 return ret; 1405 } 1406 1407 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1408 struct ib_port_attr *props) 1409 { 1410 int ret; 1411 1412 /* Only link layer == ethernet is valid for representors 1413 * and we always use port 1 1414 */ 1415 ret = mlx5_query_port_roce(ibdev, port, props); 1416 if (ret || !props) 1417 return ret; 1418 1419 /* We don't support GIDS */ 1420 props->gid_tbl_len = 0; 1421 1422 return ret; 1423 } 1424 1425 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1426 union ib_gid *gid) 1427 { 1428 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1429 struct mlx5_core_dev *mdev = dev->mdev; 1430 1431 switch (mlx5_get_vport_access_method(ibdev)) { 1432 case MLX5_VPORT_ACCESS_METHOD_MAD: 1433 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1434 1435 case MLX5_VPORT_ACCESS_METHOD_HCA: 1436 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1437 1438 default: 1439 return -EINVAL; 1440 } 1441 1442 } 1443 1444 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1445 u16 index, u16 *pkey) 1446 { 1447 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1448 struct mlx5_core_dev *mdev; 1449 bool put_mdev = true; 1450 u8 mdev_port_num; 1451 int err; 1452 1453 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1454 if (!mdev) { 1455 /* The port isn't affiliated yet, get the PKey from the master 1456 * port. For RoCE the PKey tables will be the same. 1457 */ 1458 put_mdev = false; 1459 mdev = dev->mdev; 1460 mdev_port_num = 1; 1461 } 1462 1463 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1464 index, pkey); 1465 if (put_mdev) 1466 mlx5_ib_put_native_port_mdev(dev, port); 1467 1468 return err; 1469 } 1470 1471 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1472 u16 *pkey) 1473 { 1474 switch (mlx5_get_vport_access_method(ibdev)) { 1475 case MLX5_VPORT_ACCESS_METHOD_MAD: 1476 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1477 1478 case MLX5_VPORT_ACCESS_METHOD_HCA: 1479 case MLX5_VPORT_ACCESS_METHOD_NIC: 1480 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1481 default: 1482 return -EINVAL; 1483 } 1484 } 1485 1486 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1487 struct ib_device_modify *props) 1488 { 1489 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1490 struct mlx5_reg_node_desc in; 1491 struct mlx5_reg_node_desc out; 1492 int err; 1493 1494 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1495 return -EOPNOTSUPP; 1496 1497 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1498 return 0; 1499 1500 /* 1501 * If possible, pass node desc to FW, so it can generate 1502 * a 144 trap. If cmd fails, just ignore. 1503 */ 1504 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1505 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1506 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1507 if (err) 1508 return err; 1509 1510 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1511 1512 return err; 1513 } 1514 1515 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1516 u32 value) 1517 { 1518 struct mlx5_hca_vport_context ctx = {}; 1519 struct mlx5_core_dev *mdev; 1520 u8 mdev_port_num; 1521 int err; 1522 1523 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1524 if (!mdev) 1525 return -ENODEV; 1526 1527 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1528 if (err) 1529 goto out; 1530 1531 if (~ctx.cap_mask1_perm & mask) { 1532 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1533 mask, ctx.cap_mask1_perm); 1534 err = -EINVAL; 1535 goto out; 1536 } 1537 1538 ctx.cap_mask1 = value; 1539 ctx.cap_mask1_perm = mask; 1540 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1541 0, &ctx); 1542 1543 out: 1544 mlx5_ib_put_native_port_mdev(dev, port_num); 1545 1546 return err; 1547 } 1548 1549 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1550 struct ib_port_modify *props) 1551 { 1552 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1553 struct ib_port_attr attr; 1554 u32 tmp; 1555 int err; 1556 u32 change_mask; 1557 u32 value; 1558 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1559 IB_LINK_LAYER_INFINIBAND); 1560 1561 /* CM layer calls ib_modify_port() regardless of the link layer. For 1562 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1563 */ 1564 if (!is_ib) 1565 return 0; 1566 1567 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1568 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1569 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1570 return set_port_caps_atomic(dev, port, change_mask, value); 1571 } 1572 1573 mutex_lock(&dev->cap_mask_mutex); 1574 1575 err = ib_query_port(ibdev, port, &attr); 1576 if (err) 1577 goto out; 1578 1579 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1580 ~props->clr_port_cap_mask; 1581 1582 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1583 1584 out: 1585 mutex_unlock(&dev->cap_mask_mutex); 1586 return err; 1587 } 1588 1589 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1590 { 1591 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1592 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1593 } 1594 1595 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1596 { 1597 /* Large page with non 4k uar support might limit the dynamic size */ 1598 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1599 return MLX5_MIN_DYN_BFREGS; 1600 1601 return MLX5_MAX_DYN_BFREGS; 1602 } 1603 1604 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1605 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1606 struct mlx5_bfreg_info *bfregi) 1607 { 1608 int uars_per_sys_page; 1609 int bfregs_per_sys_page; 1610 int ref_bfregs = req->total_num_bfregs; 1611 1612 if (req->total_num_bfregs == 0) 1613 return -EINVAL; 1614 1615 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1616 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1617 1618 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1619 return -ENOMEM; 1620 1621 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1622 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1623 /* This holds the required static allocation asked by the user */ 1624 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1625 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1626 return -EINVAL; 1627 1628 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1629 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1630 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1631 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1632 1633 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1634 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1635 lib_uar_4k ? "yes" : "no", ref_bfregs, 1636 req->total_num_bfregs, bfregi->total_num_bfregs, 1637 bfregi->num_sys_pages); 1638 1639 return 0; 1640 } 1641 1642 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1643 { 1644 struct mlx5_bfreg_info *bfregi; 1645 int err; 1646 int i; 1647 1648 bfregi = &context->bfregi; 1649 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1650 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1651 if (err) 1652 goto error; 1653 1654 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1655 } 1656 1657 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1658 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1659 1660 return 0; 1661 1662 error: 1663 for (--i; i >= 0; i--) 1664 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1665 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1666 1667 return err; 1668 } 1669 1670 static void deallocate_uars(struct mlx5_ib_dev *dev, 1671 struct mlx5_ib_ucontext *context) 1672 { 1673 struct mlx5_bfreg_info *bfregi; 1674 int i; 1675 1676 bfregi = &context->bfregi; 1677 for (i = 0; i < bfregi->num_sys_pages; i++) 1678 if (i < bfregi->num_static_sys_pages || 1679 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1680 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1681 } 1682 1683 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1684 { 1685 int err = 0; 1686 1687 mutex_lock(&dev->lb.mutex); 1688 if (td) 1689 dev->lb.user_td++; 1690 if (qp) 1691 dev->lb.qps++; 1692 1693 if (dev->lb.user_td == 2 || 1694 dev->lb.qps == 1) { 1695 if (!dev->lb.enabled) { 1696 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1697 dev->lb.enabled = true; 1698 } 1699 } 1700 1701 mutex_unlock(&dev->lb.mutex); 1702 1703 return err; 1704 } 1705 1706 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1707 { 1708 mutex_lock(&dev->lb.mutex); 1709 if (td) 1710 dev->lb.user_td--; 1711 if (qp) 1712 dev->lb.qps--; 1713 1714 if (dev->lb.user_td == 1 && 1715 dev->lb.qps == 0) { 1716 if (dev->lb.enabled) { 1717 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1718 dev->lb.enabled = false; 1719 } 1720 } 1721 1722 mutex_unlock(&dev->lb.mutex); 1723 } 1724 1725 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1726 u16 uid) 1727 { 1728 int err; 1729 1730 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1731 return 0; 1732 1733 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1734 if (err) 1735 return err; 1736 1737 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1738 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1739 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1740 return err; 1741 1742 return mlx5_ib_enable_lb(dev, true, false); 1743 } 1744 1745 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1746 u16 uid) 1747 { 1748 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1749 return; 1750 1751 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1752 1753 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1754 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1755 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1756 return; 1757 1758 mlx5_ib_disable_lb(dev, true, false); 1759 } 1760 1761 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1762 struct ib_udata *udata) 1763 { 1764 struct ib_device *ibdev = uctx->device; 1765 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1766 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1767 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1768 struct mlx5_core_dev *mdev = dev->mdev; 1769 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1770 struct mlx5_bfreg_info *bfregi; 1771 int ver; 1772 int err; 1773 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1774 max_cqe_version); 1775 u32 dump_fill_mkey; 1776 bool lib_uar_4k; 1777 1778 if (!dev->ib_active) 1779 return -EAGAIN; 1780 1781 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1782 ver = 0; 1783 else if (udata->inlen >= min_req_v2) 1784 ver = 2; 1785 else 1786 return -EINVAL; 1787 1788 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1789 if (err) 1790 return err; 1791 1792 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1793 return -EOPNOTSUPP; 1794 1795 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1796 return -EOPNOTSUPP; 1797 1798 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1799 MLX5_NON_FP_BFREGS_PER_UAR); 1800 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1801 return -EINVAL; 1802 1803 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1804 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1805 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1806 resp.cache_line_size = cache_line_size(); 1807 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1808 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1809 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1810 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1811 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1812 resp.cqe_version = min_t(__u8, 1813 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1814 req.max_cqe_version); 1815 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1816 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1817 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1818 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1819 resp.response_length = min(offsetof(typeof(resp), response_length) + 1820 sizeof(resp.response_length), udata->outlen); 1821 1822 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1823 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1824 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1825 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1826 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1827 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1828 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1830 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1831 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1832 } 1833 1834 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1835 bfregi = &context->bfregi; 1836 1837 /* updates req->total_num_bfregs */ 1838 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1839 if (err) 1840 goto out_ctx; 1841 1842 mutex_init(&bfregi->lock); 1843 bfregi->lib_uar_4k = lib_uar_4k; 1844 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1845 GFP_KERNEL); 1846 if (!bfregi->count) { 1847 err = -ENOMEM; 1848 goto out_ctx; 1849 } 1850 1851 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1852 sizeof(*bfregi->sys_pages), 1853 GFP_KERNEL); 1854 if (!bfregi->sys_pages) { 1855 err = -ENOMEM; 1856 goto out_count; 1857 } 1858 1859 err = allocate_uars(dev, context); 1860 if (err) 1861 goto out_sys_pages; 1862 1863 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING) 1864 context->ibucontext.invalidate_range = 1865 &mlx5_ib_invalidate_range; 1866 1867 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1868 err = mlx5_ib_devx_create(dev, true); 1869 if (err < 0) 1870 goto out_uars; 1871 context->devx_uid = err; 1872 } 1873 1874 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1875 context->devx_uid); 1876 if (err) 1877 goto out_devx; 1878 1879 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1880 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1881 if (err) 1882 goto out_mdev; 1883 } 1884 1885 INIT_LIST_HEAD(&context->db_page_list); 1886 mutex_init(&context->db_page_mutex); 1887 1888 resp.tot_bfregs = req.total_num_bfregs; 1889 resp.num_ports = dev->num_ports; 1890 1891 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1892 resp.response_length += sizeof(resp.cqe_version); 1893 1894 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1895 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1896 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1897 resp.response_length += sizeof(resp.cmds_supp_uhw); 1898 } 1899 1900 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1901 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1902 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1903 resp.eth_min_inline++; 1904 } 1905 resp.response_length += sizeof(resp.eth_min_inline); 1906 } 1907 1908 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1909 if (mdev->clock_info) 1910 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1911 resp.response_length += sizeof(resp.clock_info_versions); 1912 } 1913 1914 /* 1915 * We don't want to expose information from the PCI bar that is located 1916 * after 4096 bytes, so if the arch only supports larger pages, let's 1917 * pretend we don't support reading the HCA's core clock. This is also 1918 * forced by mmap function. 1919 */ 1920 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1921 if (PAGE_SIZE <= 4096) { 1922 resp.comp_mask |= 1923 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1924 resp.hca_core_clock_offset = 1925 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1926 } 1927 resp.response_length += sizeof(resp.hca_core_clock_offset); 1928 } 1929 1930 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1931 resp.response_length += sizeof(resp.log_uar_size); 1932 1933 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1934 resp.response_length += sizeof(resp.num_uars_per_page); 1935 1936 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1937 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1938 resp.response_length += sizeof(resp.num_dyn_bfregs); 1939 } 1940 1941 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1942 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1943 resp.dump_fill_mkey = dump_fill_mkey; 1944 resp.comp_mask |= 1945 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1946 } 1947 resp.response_length += sizeof(resp.dump_fill_mkey); 1948 } 1949 1950 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1951 if (err) 1952 goto out_mdev; 1953 1954 bfregi->ver = ver; 1955 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1956 context->cqe_version = resp.cqe_version; 1957 context->lib_caps = req.lib_caps; 1958 print_lib_caps(dev, context->lib_caps); 1959 1960 if (dev->lag_active) { 1961 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1962 1963 atomic_set(&context->tx_port_affinity, 1964 atomic_add_return( 1965 1, &dev->port[port].roce.tx_port_affinity)); 1966 } 1967 1968 return 0; 1969 1970 out_mdev: 1971 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1972 out_devx: 1973 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1974 mlx5_ib_devx_destroy(dev, context->devx_uid); 1975 1976 out_uars: 1977 deallocate_uars(dev, context); 1978 1979 out_sys_pages: 1980 kfree(bfregi->sys_pages); 1981 1982 out_count: 1983 kfree(bfregi->count); 1984 1985 out_ctx: 1986 return err; 1987 } 1988 1989 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1990 { 1991 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1992 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1993 struct mlx5_bfreg_info *bfregi; 1994 1995 /* All umem's must be destroyed before destroying the ucontext. */ 1996 mutex_lock(&ibcontext->per_mm_list_lock); 1997 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1998 mutex_unlock(&ibcontext->per_mm_list_lock); 1999 2000 bfregi = &context->bfregi; 2001 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2002 2003 if (context->devx_uid) 2004 mlx5_ib_devx_destroy(dev, context->devx_uid); 2005 2006 deallocate_uars(dev, context); 2007 kfree(bfregi->sys_pages); 2008 kfree(bfregi->count); 2009 } 2010 2011 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2012 int uar_idx) 2013 { 2014 int fw_uars_per_page; 2015 2016 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2017 2018 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2019 } 2020 2021 static int get_command(unsigned long offset) 2022 { 2023 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2024 } 2025 2026 static int get_arg(unsigned long offset) 2027 { 2028 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2029 } 2030 2031 static int get_index(unsigned long offset) 2032 { 2033 return get_arg(offset); 2034 } 2035 2036 /* Index resides in an extra byte to enable larger values than 255 */ 2037 static int get_extended_index(unsigned long offset) 2038 { 2039 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2040 } 2041 2042 2043 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2044 { 2045 } 2046 2047 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2048 { 2049 switch (cmd) { 2050 case MLX5_IB_MMAP_WC_PAGE: 2051 return "WC"; 2052 case MLX5_IB_MMAP_REGULAR_PAGE: 2053 return "best effort WC"; 2054 case MLX5_IB_MMAP_NC_PAGE: 2055 return "NC"; 2056 case MLX5_IB_MMAP_DEVICE_MEM: 2057 return "Device Memory"; 2058 default: 2059 return NULL; 2060 } 2061 } 2062 2063 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2064 struct vm_area_struct *vma, 2065 struct mlx5_ib_ucontext *context) 2066 { 2067 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2068 !(vma->vm_flags & VM_SHARED)) 2069 return -EINVAL; 2070 2071 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2072 return -EOPNOTSUPP; 2073 2074 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2075 return -EPERM; 2076 vma->vm_flags &= ~VM_MAYWRITE; 2077 2078 if (!dev->mdev->clock_info) 2079 return -EOPNOTSUPP; 2080 2081 return vm_insert_page(vma, vma->vm_start, 2082 virt_to_page(dev->mdev->clock_info)); 2083 } 2084 2085 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2086 struct vm_area_struct *vma, 2087 struct mlx5_ib_ucontext *context) 2088 { 2089 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2090 int err; 2091 unsigned long idx; 2092 phys_addr_t pfn; 2093 pgprot_t prot; 2094 u32 bfreg_dyn_idx = 0; 2095 u32 uar_index; 2096 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2097 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2098 bfregi->num_static_sys_pages; 2099 2100 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2101 return -EINVAL; 2102 2103 if (dyn_uar) 2104 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2105 else 2106 idx = get_index(vma->vm_pgoff); 2107 2108 if (idx >= max_valid_idx) { 2109 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2110 idx, max_valid_idx); 2111 return -EINVAL; 2112 } 2113 2114 switch (cmd) { 2115 case MLX5_IB_MMAP_WC_PAGE: 2116 case MLX5_IB_MMAP_ALLOC_WC: 2117 /* Some architectures don't support WC memory */ 2118 #if defined(CONFIG_X86) 2119 if (!pat_enabled()) 2120 return -EPERM; 2121 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2122 return -EPERM; 2123 #endif 2124 /* fall through */ 2125 case MLX5_IB_MMAP_REGULAR_PAGE: 2126 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2127 prot = pgprot_writecombine(vma->vm_page_prot); 2128 break; 2129 case MLX5_IB_MMAP_NC_PAGE: 2130 prot = pgprot_noncached(vma->vm_page_prot); 2131 break; 2132 default: 2133 return -EINVAL; 2134 } 2135 2136 if (dyn_uar) { 2137 int uars_per_page; 2138 2139 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2140 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2141 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2142 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2143 bfreg_dyn_idx, bfregi->total_num_bfregs); 2144 return -EINVAL; 2145 } 2146 2147 mutex_lock(&bfregi->lock); 2148 /* Fail if uar already allocated, first bfreg index of each 2149 * page holds its count. 2150 */ 2151 if (bfregi->count[bfreg_dyn_idx]) { 2152 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2153 mutex_unlock(&bfregi->lock); 2154 return -EINVAL; 2155 } 2156 2157 bfregi->count[bfreg_dyn_idx]++; 2158 mutex_unlock(&bfregi->lock); 2159 2160 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2161 if (err) { 2162 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2163 goto free_bfreg; 2164 } 2165 } else { 2166 uar_index = bfregi->sys_pages[idx]; 2167 } 2168 2169 pfn = uar_index2pfn(dev, uar_index); 2170 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2171 2172 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2173 prot); 2174 if (err) { 2175 mlx5_ib_err(dev, 2176 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2177 err, mmap_cmd2str(cmd)); 2178 goto err; 2179 } 2180 2181 if (dyn_uar) 2182 bfregi->sys_pages[idx] = uar_index; 2183 return 0; 2184 2185 err: 2186 if (!dyn_uar) 2187 return err; 2188 2189 mlx5_cmd_free_uar(dev->mdev, idx); 2190 2191 free_bfreg: 2192 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2193 2194 return err; 2195 } 2196 2197 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2198 { 2199 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2200 struct mlx5_ib_dev *dev = to_mdev(context->device); 2201 u16 page_idx = get_extended_index(vma->vm_pgoff); 2202 size_t map_size = vma->vm_end - vma->vm_start; 2203 u32 npages = map_size >> PAGE_SHIFT; 2204 phys_addr_t pfn; 2205 2206 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2207 page_idx + npages) 2208 return -EINVAL; 2209 2210 pfn = ((dev->mdev->bar_addr + 2211 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2212 PAGE_SHIFT) + 2213 page_idx; 2214 return rdma_user_mmap_io(context, vma, pfn, map_size, 2215 pgprot_writecombine(vma->vm_page_prot)); 2216 } 2217 2218 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2219 { 2220 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2221 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2222 unsigned long command; 2223 phys_addr_t pfn; 2224 2225 command = get_command(vma->vm_pgoff); 2226 switch (command) { 2227 case MLX5_IB_MMAP_WC_PAGE: 2228 case MLX5_IB_MMAP_NC_PAGE: 2229 case MLX5_IB_MMAP_REGULAR_PAGE: 2230 case MLX5_IB_MMAP_ALLOC_WC: 2231 return uar_mmap(dev, command, vma, context); 2232 2233 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2234 return -ENOSYS; 2235 2236 case MLX5_IB_MMAP_CORE_CLOCK: 2237 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2238 return -EINVAL; 2239 2240 if (vma->vm_flags & VM_WRITE) 2241 return -EPERM; 2242 vma->vm_flags &= ~VM_MAYWRITE; 2243 2244 /* Don't expose to user-space information it shouldn't have */ 2245 if (PAGE_SIZE > 4096) 2246 return -EOPNOTSUPP; 2247 2248 pfn = (dev->mdev->iseg_base + 2249 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2250 PAGE_SHIFT; 2251 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2252 PAGE_SIZE, 2253 pgprot_noncached(vma->vm_page_prot)); 2254 case MLX5_IB_MMAP_CLOCK_INFO: 2255 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2256 2257 case MLX5_IB_MMAP_DEVICE_MEM: 2258 return dm_mmap(ibcontext, vma); 2259 2260 default: 2261 return -EINVAL; 2262 } 2263 2264 return 0; 2265 } 2266 2267 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2268 u32 type) 2269 { 2270 switch (type) { 2271 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2272 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2273 return -EOPNOTSUPP; 2274 break; 2275 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2276 if (!capable(CAP_SYS_RAWIO) || 2277 !capable(CAP_NET_RAW)) 2278 return -EPERM; 2279 2280 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2281 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner))) 2282 return -EOPNOTSUPP; 2283 break; 2284 } 2285 2286 return 0; 2287 } 2288 2289 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2290 struct mlx5_ib_dm *dm, 2291 struct ib_dm_alloc_attr *attr, 2292 struct uverbs_attr_bundle *attrs) 2293 { 2294 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2295 u64 start_offset; 2296 u32 page_idx; 2297 int err; 2298 2299 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2300 2301 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2302 dm->size, attr->alignment); 2303 if (err) 2304 return err; 2305 2306 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) - 2307 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >> 2308 PAGE_SHIFT; 2309 2310 err = uverbs_copy_to(attrs, 2311 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2312 &page_idx, sizeof(page_idx)); 2313 if (err) 2314 goto err_dealloc; 2315 2316 start_offset = dm->dev_addr & ~PAGE_MASK; 2317 err = uverbs_copy_to(attrs, 2318 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2319 &start_offset, sizeof(start_offset)); 2320 if (err) 2321 goto err_dealloc; 2322 2323 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx, 2324 DIV_ROUND_UP(dm->size, PAGE_SIZE)); 2325 2326 return 0; 2327 2328 err_dealloc: 2329 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2330 2331 return err; 2332 } 2333 2334 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2335 struct mlx5_ib_dm *dm, 2336 struct ib_dm_alloc_attr *attr, 2337 struct uverbs_attr_bundle *attrs, 2338 int type) 2339 { 2340 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2341 u64 act_size; 2342 int err; 2343 2344 /* Allocation size must a multiple of the basic block size 2345 * and a power of 2. 2346 */ 2347 act_size = roundup(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev)); 2348 act_size = roundup_pow_of_two(act_size); 2349 2350 dm->size = act_size; 2351 err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size, 2352 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2353 &dm->icm_dm.obj_id); 2354 if (err) 2355 return err; 2356 2357 err = uverbs_copy_to(attrs, 2358 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2359 &dm->dev_addr, sizeof(dm->dev_addr)); 2360 if (err) 2361 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size, 2362 to_mucontext(ctx)->devx_uid, 2363 dm->dev_addr, dm->icm_dm.obj_id); 2364 2365 return err; 2366 } 2367 2368 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2369 struct ib_ucontext *context, 2370 struct ib_dm_alloc_attr *attr, 2371 struct uverbs_attr_bundle *attrs) 2372 { 2373 struct mlx5_ib_dm *dm; 2374 enum mlx5_ib_uapi_dm_type type; 2375 int err; 2376 2377 err = uverbs_get_const_default(&type, attrs, 2378 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2379 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2380 if (err) 2381 return ERR_PTR(err); 2382 2383 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2384 type, attr->length, attr->alignment); 2385 2386 err = check_dm_type_support(to_mdev(ibdev), type); 2387 if (err) 2388 return ERR_PTR(err); 2389 2390 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2391 if (!dm) 2392 return ERR_PTR(-ENOMEM); 2393 2394 dm->type = type; 2395 2396 switch (type) { 2397 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2398 err = handle_alloc_dm_memic(context, dm, 2399 attr, 2400 attrs); 2401 break; 2402 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2403 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2404 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type); 2405 break; 2406 default: 2407 err = -EOPNOTSUPP; 2408 } 2409 2410 if (err) 2411 goto err_free; 2412 2413 return &dm->ibdm; 2414 2415 err_free: 2416 kfree(dm); 2417 return ERR_PTR(err); 2418 } 2419 2420 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2421 { 2422 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2423 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2424 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm; 2425 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2426 u32 page_idx; 2427 int ret; 2428 2429 switch (dm->type) { 2430 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2431 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2432 if (ret) 2433 return ret; 2434 2435 page_idx = (dm->dev_addr - 2436 pci_resource_start(dm_db->dev->pdev, 0) - 2437 MLX5_CAP64_DEV_MEM(dm_db->dev, 2438 memic_bar_start_addr)) >> 2439 PAGE_SHIFT; 2440 bitmap_clear(ctx->dm_pages, page_idx, 2441 DIV_ROUND_UP(dm->size, PAGE_SIZE)); 2442 break; 2443 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2444 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2445 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size, 2446 ctx->devx_uid, dm->dev_addr, 2447 dm->icm_dm.obj_id); 2448 if (ret) 2449 return ret; 2450 break; 2451 default: 2452 return -EOPNOTSUPP; 2453 } 2454 2455 kfree(dm); 2456 2457 return 0; 2458 } 2459 2460 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2461 { 2462 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2463 struct ib_device *ibdev = ibpd->device; 2464 struct mlx5_ib_alloc_pd_resp resp; 2465 int err; 2466 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2467 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2468 u16 uid = 0; 2469 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2470 udata, struct mlx5_ib_ucontext, ibucontext); 2471 2472 uid = context ? context->devx_uid : 0; 2473 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2474 MLX5_SET(alloc_pd_in, in, uid, uid); 2475 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in), 2476 out, sizeof(out)); 2477 if (err) 2478 return err; 2479 2480 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2481 pd->uid = uid; 2482 if (udata) { 2483 resp.pdn = pd->pdn; 2484 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2485 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2486 return -EFAULT; 2487 } 2488 } 2489 2490 return 0; 2491 } 2492 2493 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2494 { 2495 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2496 struct mlx5_ib_pd *mpd = to_mpd(pd); 2497 2498 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2499 } 2500 2501 enum { 2502 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2503 MATCH_CRITERIA_ENABLE_MISC_BIT, 2504 MATCH_CRITERIA_ENABLE_INNER_BIT, 2505 MATCH_CRITERIA_ENABLE_MISC2_BIT 2506 }; 2507 2508 #define HEADER_IS_ZERO(match_criteria, headers) \ 2509 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2510 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2511 2512 static u8 get_match_criteria_enable(u32 *match_criteria) 2513 { 2514 u8 match_criteria_enable; 2515 2516 match_criteria_enable = 2517 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2518 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2519 match_criteria_enable |= 2520 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2521 MATCH_CRITERIA_ENABLE_MISC_BIT; 2522 match_criteria_enable |= 2523 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2524 MATCH_CRITERIA_ENABLE_INNER_BIT; 2525 match_criteria_enable |= 2526 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2527 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2528 2529 return match_criteria_enable; 2530 } 2531 2532 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2533 { 2534 u8 entry_mask; 2535 u8 entry_val; 2536 int err = 0; 2537 2538 if (!mask) 2539 goto out; 2540 2541 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c, 2542 ip_protocol); 2543 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v, 2544 ip_protocol); 2545 if (!entry_mask) { 2546 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2547 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2548 goto out; 2549 } 2550 /* Don't override existing ip protocol */ 2551 if (mask != entry_mask || val != entry_val) 2552 err = -EINVAL; 2553 out: 2554 return err; 2555 } 2556 2557 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2558 bool inner) 2559 { 2560 if (inner) { 2561 MLX5_SET(fte_match_set_misc, 2562 misc_c, inner_ipv6_flow_label, mask); 2563 MLX5_SET(fte_match_set_misc, 2564 misc_v, inner_ipv6_flow_label, val); 2565 } else { 2566 MLX5_SET(fte_match_set_misc, 2567 misc_c, outer_ipv6_flow_label, mask); 2568 MLX5_SET(fte_match_set_misc, 2569 misc_v, outer_ipv6_flow_label, val); 2570 } 2571 } 2572 2573 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2574 { 2575 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2576 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2577 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2578 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2579 } 2580 2581 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2582 { 2583 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2584 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2585 return -EOPNOTSUPP; 2586 2587 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2588 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2589 return -EOPNOTSUPP; 2590 2591 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2592 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2593 return -EOPNOTSUPP; 2594 2595 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2596 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2597 return -EOPNOTSUPP; 2598 2599 return 0; 2600 } 2601 2602 #define LAST_ETH_FIELD vlan_tag 2603 #define LAST_IB_FIELD sl 2604 #define LAST_IPV4_FIELD tos 2605 #define LAST_IPV6_FIELD traffic_class 2606 #define LAST_TCP_UDP_FIELD src_port 2607 #define LAST_TUNNEL_FIELD tunnel_id 2608 #define LAST_FLOW_TAG_FIELD tag_id 2609 #define LAST_DROP_FIELD size 2610 #define LAST_COUNTERS_FIELD counters 2611 2612 /* Field is the last supported field */ 2613 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2614 memchr_inv((void *)&filter.field +\ 2615 sizeof(filter.field), 0,\ 2616 sizeof(filter) -\ 2617 offsetof(typeof(filter), field) -\ 2618 sizeof(filter.field)) 2619 2620 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2621 bool is_egress, 2622 struct mlx5_flow_act *action) 2623 { 2624 2625 switch (maction->ib_action.type) { 2626 case IB_FLOW_ACTION_ESP: 2627 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2628 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2629 return -EINVAL; 2630 /* Currently only AES_GCM keymat is supported by the driver */ 2631 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2632 action->action |= is_egress ? 2633 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2634 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2635 return 0; 2636 case IB_FLOW_ACTION_UNSPECIFIED: 2637 if (maction->flow_action_raw.sub_type == 2638 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2639 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2640 return -EINVAL; 2641 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2642 action->modify_id = maction->flow_action_raw.action_id; 2643 return 0; 2644 } 2645 if (maction->flow_action_raw.sub_type == 2646 MLX5_IB_FLOW_ACTION_DECAP) { 2647 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2648 return -EINVAL; 2649 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2650 return 0; 2651 } 2652 if (maction->flow_action_raw.sub_type == 2653 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2654 if (action->action & 2655 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2656 return -EINVAL; 2657 action->action |= 2658 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2659 action->reformat_id = 2660 maction->flow_action_raw.action_id; 2661 return 0; 2662 } 2663 /* fall through */ 2664 default: 2665 return -EOPNOTSUPP; 2666 } 2667 } 2668 2669 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2670 u32 *match_v, const union ib_flow_spec *ib_spec, 2671 const struct ib_flow_attr *flow_attr, 2672 struct mlx5_flow_act *action, u32 prev_type) 2673 { 2674 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2675 misc_parameters); 2676 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2677 misc_parameters); 2678 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2679 misc_parameters_2); 2680 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2681 misc_parameters_2); 2682 void *headers_c; 2683 void *headers_v; 2684 int match_ipv; 2685 int ret; 2686 2687 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2688 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2689 inner_headers); 2690 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2691 inner_headers); 2692 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2693 ft_field_support.inner_ip_version); 2694 } else { 2695 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2696 outer_headers); 2697 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2698 outer_headers); 2699 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2700 ft_field_support.outer_ip_version); 2701 } 2702 2703 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2704 case IB_FLOW_SPEC_ETH: 2705 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2706 return -EOPNOTSUPP; 2707 2708 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2709 dmac_47_16), 2710 ib_spec->eth.mask.dst_mac); 2711 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2712 dmac_47_16), 2713 ib_spec->eth.val.dst_mac); 2714 2715 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2716 smac_47_16), 2717 ib_spec->eth.mask.src_mac); 2718 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2719 smac_47_16), 2720 ib_spec->eth.val.src_mac); 2721 2722 if (ib_spec->eth.mask.vlan_tag) { 2723 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2724 cvlan_tag, 1); 2725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2726 cvlan_tag, 1); 2727 2728 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2729 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2731 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2732 2733 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2734 first_cfi, 2735 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2737 first_cfi, 2738 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2739 2740 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2741 first_prio, 2742 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2743 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2744 first_prio, 2745 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2746 } 2747 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2748 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2750 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2751 break; 2752 case IB_FLOW_SPEC_IPV4: 2753 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2754 return -EOPNOTSUPP; 2755 2756 if (match_ipv) { 2757 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2758 ip_version, 0xf); 2759 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2760 ip_version, MLX5_FS_IPV4_VERSION); 2761 } else { 2762 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2763 ethertype, 0xffff); 2764 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2765 ethertype, ETH_P_IP); 2766 } 2767 2768 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2769 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2770 &ib_spec->ipv4.mask.src_ip, 2771 sizeof(ib_spec->ipv4.mask.src_ip)); 2772 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2773 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2774 &ib_spec->ipv4.val.src_ip, 2775 sizeof(ib_spec->ipv4.val.src_ip)); 2776 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2777 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2778 &ib_spec->ipv4.mask.dst_ip, 2779 sizeof(ib_spec->ipv4.mask.dst_ip)); 2780 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2781 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2782 &ib_spec->ipv4.val.dst_ip, 2783 sizeof(ib_spec->ipv4.val.dst_ip)); 2784 2785 set_tos(headers_c, headers_v, 2786 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2787 2788 if (set_proto(headers_c, headers_v, 2789 ib_spec->ipv4.mask.proto, 2790 ib_spec->ipv4.val.proto)) 2791 return -EINVAL; 2792 break; 2793 case IB_FLOW_SPEC_IPV6: 2794 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2795 return -EOPNOTSUPP; 2796 2797 if (match_ipv) { 2798 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2799 ip_version, 0xf); 2800 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2801 ip_version, MLX5_FS_IPV6_VERSION); 2802 } else { 2803 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2804 ethertype, 0xffff); 2805 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2806 ethertype, ETH_P_IPV6); 2807 } 2808 2809 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2810 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2811 &ib_spec->ipv6.mask.src_ip, 2812 sizeof(ib_spec->ipv6.mask.src_ip)); 2813 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2814 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2815 &ib_spec->ipv6.val.src_ip, 2816 sizeof(ib_spec->ipv6.val.src_ip)); 2817 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2818 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2819 &ib_spec->ipv6.mask.dst_ip, 2820 sizeof(ib_spec->ipv6.mask.dst_ip)); 2821 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2822 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2823 &ib_spec->ipv6.val.dst_ip, 2824 sizeof(ib_spec->ipv6.val.dst_ip)); 2825 2826 set_tos(headers_c, headers_v, 2827 ib_spec->ipv6.mask.traffic_class, 2828 ib_spec->ipv6.val.traffic_class); 2829 2830 if (set_proto(headers_c, headers_v, 2831 ib_spec->ipv6.mask.next_hdr, 2832 ib_spec->ipv6.val.next_hdr)) 2833 return -EINVAL; 2834 2835 set_flow_label(misc_params_c, misc_params_v, 2836 ntohl(ib_spec->ipv6.mask.flow_label), 2837 ntohl(ib_spec->ipv6.val.flow_label), 2838 ib_spec->type & IB_FLOW_SPEC_INNER); 2839 break; 2840 case IB_FLOW_SPEC_ESP: 2841 if (ib_spec->esp.mask.seq) 2842 return -EOPNOTSUPP; 2843 2844 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2845 ntohl(ib_spec->esp.mask.spi)); 2846 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2847 ntohl(ib_spec->esp.val.spi)); 2848 break; 2849 case IB_FLOW_SPEC_TCP: 2850 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2851 LAST_TCP_UDP_FIELD)) 2852 return -EOPNOTSUPP; 2853 2854 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP)) 2855 return -EINVAL; 2856 2857 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2858 ntohs(ib_spec->tcp_udp.mask.src_port)); 2859 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2860 ntohs(ib_spec->tcp_udp.val.src_port)); 2861 2862 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2863 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2864 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2865 ntohs(ib_spec->tcp_udp.val.dst_port)); 2866 break; 2867 case IB_FLOW_SPEC_UDP: 2868 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2869 LAST_TCP_UDP_FIELD)) 2870 return -EOPNOTSUPP; 2871 2872 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP)) 2873 return -EINVAL; 2874 2875 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2876 ntohs(ib_spec->tcp_udp.mask.src_port)); 2877 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2878 ntohs(ib_spec->tcp_udp.val.src_port)); 2879 2880 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2881 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2883 ntohs(ib_spec->tcp_udp.val.dst_port)); 2884 break; 2885 case IB_FLOW_SPEC_GRE: 2886 if (ib_spec->gre.mask.c_ks_res0_ver) 2887 return -EOPNOTSUPP; 2888 2889 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE)) 2890 return -EINVAL; 2891 2892 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2893 0xff); 2894 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2895 IPPROTO_GRE); 2896 2897 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2898 ntohs(ib_spec->gre.mask.protocol)); 2899 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2900 ntohs(ib_spec->gre.val.protocol)); 2901 2902 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2903 gre_key.nvgre.hi), 2904 &ib_spec->gre.mask.key, 2905 sizeof(ib_spec->gre.mask.key)); 2906 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2907 gre_key.nvgre.hi), 2908 &ib_spec->gre.val.key, 2909 sizeof(ib_spec->gre.val.key)); 2910 break; 2911 case IB_FLOW_SPEC_MPLS: 2912 switch (prev_type) { 2913 case IB_FLOW_SPEC_UDP: 2914 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2915 ft_field_support.outer_first_mpls_over_udp), 2916 &ib_spec->mpls.mask.tag)) 2917 return -EOPNOTSUPP; 2918 2919 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2920 outer_first_mpls_over_udp), 2921 &ib_spec->mpls.val.tag, 2922 sizeof(ib_spec->mpls.val.tag)); 2923 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2924 outer_first_mpls_over_udp), 2925 &ib_spec->mpls.mask.tag, 2926 sizeof(ib_spec->mpls.mask.tag)); 2927 break; 2928 case IB_FLOW_SPEC_GRE: 2929 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2930 ft_field_support.outer_first_mpls_over_gre), 2931 &ib_spec->mpls.mask.tag)) 2932 return -EOPNOTSUPP; 2933 2934 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2935 outer_first_mpls_over_gre), 2936 &ib_spec->mpls.val.tag, 2937 sizeof(ib_spec->mpls.val.tag)); 2938 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2939 outer_first_mpls_over_gre), 2940 &ib_spec->mpls.mask.tag, 2941 sizeof(ib_spec->mpls.mask.tag)); 2942 break; 2943 default: 2944 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2945 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2946 ft_field_support.inner_first_mpls), 2947 &ib_spec->mpls.mask.tag)) 2948 return -EOPNOTSUPP; 2949 2950 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2951 inner_first_mpls), 2952 &ib_spec->mpls.val.tag, 2953 sizeof(ib_spec->mpls.val.tag)); 2954 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2955 inner_first_mpls), 2956 &ib_spec->mpls.mask.tag, 2957 sizeof(ib_spec->mpls.mask.tag)); 2958 } else { 2959 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2960 ft_field_support.outer_first_mpls), 2961 &ib_spec->mpls.mask.tag)) 2962 return -EOPNOTSUPP; 2963 2964 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2965 outer_first_mpls), 2966 &ib_spec->mpls.val.tag, 2967 sizeof(ib_spec->mpls.val.tag)); 2968 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2969 outer_first_mpls), 2970 &ib_spec->mpls.mask.tag, 2971 sizeof(ib_spec->mpls.mask.tag)); 2972 } 2973 } 2974 break; 2975 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2976 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2977 LAST_TUNNEL_FIELD)) 2978 return -EOPNOTSUPP; 2979 2980 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2981 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2982 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2983 ntohl(ib_spec->tunnel.val.tunnel_id)); 2984 break; 2985 case IB_FLOW_SPEC_ACTION_TAG: 2986 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2987 LAST_FLOW_TAG_FIELD)) 2988 return -EOPNOTSUPP; 2989 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2990 return -EINVAL; 2991 2992 action->flow_tag = ib_spec->flow_tag.tag_id; 2993 action->flags |= FLOW_ACT_HAS_TAG; 2994 break; 2995 case IB_FLOW_SPEC_ACTION_DROP: 2996 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2997 LAST_DROP_FIELD)) 2998 return -EOPNOTSUPP; 2999 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 3000 break; 3001 case IB_FLOW_SPEC_ACTION_HANDLE: 3002 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 3003 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 3004 if (ret) 3005 return ret; 3006 break; 3007 case IB_FLOW_SPEC_ACTION_COUNT: 3008 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 3009 LAST_COUNTERS_FIELD)) 3010 return -EOPNOTSUPP; 3011 3012 /* for now support only one counters spec per flow */ 3013 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 3014 return -EINVAL; 3015 3016 action->counters = ib_spec->flow_count.counters; 3017 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 3018 break; 3019 default: 3020 return -EINVAL; 3021 } 3022 3023 return 0; 3024 } 3025 3026 /* If a flow could catch both multicast and unicast packets, 3027 * it won't fall into the multicast flow steering table and this rule 3028 * could steal other multicast packets. 3029 */ 3030 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 3031 { 3032 union ib_flow_spec *flow_spec; 3033 3034 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 3035 ib_attr->num_of_specs < 1) 3036 return false; 3037 3038 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 3039 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 3040 struct ib_flow_spec_ipv4 *ipv4_spec; 3041 3042 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 3043 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 3044 return true; 3045 3046 return false; 3047 } 3048 3049 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 3050 struct ib_flow_spec_eth *eth_spec; 3051 3052 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 3053 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 3054 is_multicast_ether_addr(eth_spec->val.dst_mac); 3055 } 3056 3057 return false; 3058 } 3059 3060 enum valid_spec { 3061 VALID_SPEC_INVALID, 3062 VALID_SPEC_VALID, 3063 VALID_SPEC_NA, 3064 }; 3065 3066 static enum valid_spec 3067 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 3068 const struct mlx5_flow_spec *spec, 3069 const struct mlx5_flow_act *flow_act, 3070 bool egress) 3071 { 3072 const u32 *match_c = spec->match_criteria; 3073 bool is_crypto = 3074 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 3075 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 3076 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 3077 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 3078 3079 /* 3080 * Currently only crypto is supported in egress, when regular egress 3081 * rules would be supported, always return VALID_SPEC_NA. 3082 */ 3083 if (!is_crypto) 3084 return VALID_SPEC_NA; 3085 3086 return is_crypto && is_ipsec && 3087 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ? 3088 VALID_SPEC_VALID : VALID_SPEC_INVALID; 3089 } 3090 3091 static bool is_valid_spec(struct mlx5_core_dev *mdev, 3092 const struct mlx5_flow_spec *spec, 3093 const struct mlx5_flow_act *flow_act, 3094 bool egress) 3095 { 3096 /* We curretly only support ipsec egress flow */ 3097 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 3098 } 3099 3100 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 3101 const struct ib_flow_attr *flow_attr, 3102 bool check_inner) 3103 { 3104 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 3105 int match_ipv = check_inner ? 3106 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3107 ft_field_support.inner_ip_version) : 3108 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3109 ft_field_support.outer_ip_version); 3110 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 3111 bool ipv4_spec_valid, ipv6_spec_valid; 3112 unsigned int ip_spec_type = 0; 3113 bool has_ethertype = false; 3114 unsigned int spec_index; 3115 bool mask_valid = true; 3116 u16 eth_type = 0; 3117 bool type_valid; 3118 3119 /* Validate that ethertype is correct */ 3120 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3121 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 3122 ib_spec->eth.mask.ether_type) { 3123 mask_valid = (ib_spec->eth.mask.ether_type == 3124 htons(0xffff)); 3125 has_ethertype = true; 3126 eth_type = ntohs(ib_spec->eth.val.ether_type); 3127 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 3128 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 3129 ip_spec_type = ib_spec->type; 3130 } 3131 ib_spec = (void *)ib_spec + ib_spec->size; 3132 } 3133 3134 type_valid = (!has_ethertype) || (!ip_spec_type); 3135 if (!type_valid && mask_valid) { 3136 ipv4_spec_valid = (eth_type == ETH_P_IP) && 3137 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 3138 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 3139 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 3140 3141 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 3142 (((eth_type == ETH_P_MPLS_UC) || 3143 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 3144 } 3145 3146 return type_valid; 3147 } 3148 3149 static bool is_valid_attr(struct mlx5_core_dev *mdev, 3150 const struct ib_flow_attr *flow_attr) 3151 { 3152 return is_valid_ethertype(mdev, flow_attr, false) && 3153 is_valid_ethertype(mdev, flow_attr, true); 3154 } 3155 3156 static void put_flow_table(struct mlx5_ib_dev *dev, 3157 struct mlx5_ib_flow_prio *prio, bool ft_added) 3158 { 3159 prio->refcount -= !!ft_added; 3160 if (!prio->refcount) { 3161 mlx5_destroy_flow_table(prio->flow_table); 3162 prio->flow_table = NULL; 3163 } 3164 } 3165 3166 static void counters_clear_description(struct ib_counters *counters) 3167 { 3168 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3169 3170 mutex_lock(&mcounters->mcntrs_mutex); 3171 kfree(mcounters->counters_data); 3172 mcounters->counters_data = NULL; 3173 mcounters->cntrs_max_index = 0; 3174 mutex_unlock(&mcounters->mcntrs_mutex); 3175 } 3176 3177 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 3178 { 3179 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 3180 struct mlx5_ib_flow_handler, 3181 ibflow); 3182 struct mlx5_ib_flow_handler *iter, *tmp; 3183 struct mlx5_ib_dev *dev = handler->dev; 3184 3185 mutex_lock(&dev->flow_db->lock); 3186 3187 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 3188 mlx5_del_flow_rules(iter->rule); 3189 put_flow_table(dev, iter->prio, true); 3190 list_del(&iter->list); 3191 kfree(iter); 3192 } 3193 3194 mlx5_del_flow_rules(handler->rule); 3195 put_flow_table(dev, handler->prio, true); 3196 if (handler->ibcounters && 3197 atomic_read(&handler->ibcounters->usecnt) == 1) 3198 counters_clear_description(handler->ibcounters); 3199 3200 mutex_unlock(&dev->flow_db->lock); 3201 if (handler->flow_matcher) 3202 atomic_dec(&handler->flow_matcher->usecnt); 3203 kfree(handler); 3204 3205 return 0; 3206 } 3207 3208 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 3209 { 3210 priority *= 2; 3211 if (!dont_trap) 3212 priority++; 3213 return priority; 3214 } 3215 3216 enum flow_table_type { 3217 MLX5_IB_FT_RX, 3218 MLX5_IB_FT_TX 3219 }; 3220 3221 #define MLX5_FS_MAX_TYPES 6 3222 #define MLX5_FS_MAX_ENTRIES BIT(16) 3223 3224 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3225 struct mlx5_ib_flow_prio *prio, 3226 int priority, 3227 int num_entries, int num_groups, 3228 u32 flags) 3229 { 3230 struct mlx5_flow_table *ft; 3231 3232 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3233 num_entries, 3234 num_groups, 3235 0, flags); 3236 if (IS_ERR(ft)) 3237 return ERR_CAST(ft); 3238 3239 prio->flow_table = ft; 3240 prio->refcount = 0; 3241 return prio; 3242 } 3243 3244 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3245 struct ib_flow_attr *flow_attr, 3246 enum flow_table_type ft_type) 3247 { 3248 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3249 struct mlx5_flow_namespace *ns = NULL; 3250 struct mlx5_ib_flow_prio *prio; 3251 struct mlx5_flow_table *ft; 3252 int max_table_size; 3253 int num_entries; 3254 int num_groups; 3255 u32 flags = 0; 3256 int priority; 3257 3258 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3259 log_max_ft_size)); 3260 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3261 enum mlx5_flow_namespace_type fn_type; 3262 3263 if (flow_is_multicast_only(flow_attr) && 3264 !dont_trap) 3265 priority = MLX5_IB_FLOW_MCAST_PRIO; 3266 else 3267 priority = ib_prio_to_core_prio(flow_attr->priority, 3268 dont_trap); 3269 if (ft_type == MLX5_IB_FT_RX) { 3270 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3271 prio = &dev->flow_db->prios[priority]; 3272 if (!dev->is_rep && 3273 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3274 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3275 if (!dev->is_rep && 3276 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3277 reformat_l3_tunnel_to_l2)) 3278 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3279 } else { 3280 max_table_size = 3281 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3282 log_max_ft_size)); 3283 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3284 prio = &dev->flow_db->egress_prios[priority]; 3285 if (!dev->is_rep && 3286 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3287 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3288 } 3289 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3290 num_entries = MLX5_FS_MAX_ENTRIES; 3291 num_groups = MLX5_FS_MAX_TYPES; 3292 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3293 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3294 ns = mlx5_get_flow_namespace(dev->mdev, 3295 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3296 build_leftovers_ft_param(&priority, 3297 &num_entries, 3298 &num_groups); 3299 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3300 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3301 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3302 allow_sniffer_and_nic_rx_shared_tir)) 3303 return ERR_PTR(-ENOTSUPP); 3304 3305 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3306 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3307 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3308 3309 prio = &dev->flow_db->sniffer[ft_type]; 3310 priority = 0; 3311 num_entries = 1; 3312 num_groups = 1; 3313 } 3314 3315 if (!ns) 3316 return ERR_PTR(-ENOTSUPP); 3317 3318 max_table_size = min_t(int, num_entries, max_table_size); 3319 3320 ft = prio->flow_table; 3321 if (!ft) 3322 return _get_prio(ns, prio, priority, max_table_size, num_groups, 3323 flags); 3324 3325 return prio; 3326 } 3327 3328 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3329 struct mlx5_flow_spec *spec, 3330 u32 underlay_qpn) 3331 { 3332 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3333 spec->match_criteria, 3334 misc_parameters); 3335 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3336 misc_parameters); 3337 3338 if (underlay_qpn && 3339 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3340 ft_field_support.bth_dst_qp)) { 3341 MLX5_SET(fte_match_set_misc, 3342 misc_params_v, bth_dst_qp, underlay_qpn); 3343 MLX5_SET(fte_match_set_misc, 3344 misc_params_c, bth_dst_qp, 0xffffff); 3345 } 3346 } 3347 3348 static int read_flow_counters(struct ib_device *ibdev, 3349 struct mlx5_read_counters_attr *read_attr) 3350 { 3351 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3352 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3353 3354 return mlx5_fc_query(dev->mdev, fc, 3355 &read_attr->out[IB_COUNTER_PACKETS], 3356 &read_attr->out[IB_COUNTER_BYTES]); 3357 } 3358 3359 /* flow counters currently expose two counters packets and bytes */ 3360 #define FLOW_COUNTERS_NUM 2 3361 static int counters_set_description(struct ib_counters *counters, 3362 enum mlx5_ib_counters_type counters_type, 3363 struct mlx5_ib_flow_counters_desc *desc_data, 3364 u32 ncounters) 3365 { 3366 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3367 u32 cntrs_max_index = 0; 3368 int i; 3369 3370 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3371 return -EINVAL; 3372 3373 /* init the fields for the object */ 3374 mcounters->type = counters_type; 3375 mcounters->read_counters = read_flow_counters; 3376 mcounters->counters_num = FLOW_COUNTERS_NUM; 3377 mcounters->ncounters = ncounters; 3378 /* each counter entry have both description and index pair */ 3379 for (i = 0; i < ncounters; i++) { 3380 if (desc_data[i].description > IB_COUNTER_BYTES) 3381 return -EINVAL; 3382 3383 if (cntrs_max_index <= desc_data[i].index) 3384 cntrs_max_index = desc_data[i].index + 1; 3385 } 3386 3387 mutex_lock(&mcounters->mcntrs_mutex); 3388 mcounters->counters_data = desc_data; 3389 mcounters->cntrs_max_index = cntrs_max_index; 3390 mutex_unlock(&mcounters->mcntrs_mutex); 3391 3392 return 0; 3393 } 3394 3395 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3396 static int flow_counters_set_data(struct ib_counters *ibcounters, 3397 struct mlx5_ib_create_flow *ucmd) 3398 { 3399 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3400 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3401 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3402 bool hw_hndl = false; 3403 int ret = 0; 3404 3405 if (ucmd && ucmd->ncounters_data != 0) { 3406 cntrs_data = ucmd->data; 3407 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3408 return -EINVAL; 3409 3410 desc_data = kcalloc(cntrs_data->ncounters, 3411 sizeof(*desc_data), 3412 GFP_KERNEL); 3413 if (!desc_data) 3414 return -ENOMEM; 3415 3416 if (copy_from_user(desc_data, 3417 u64_to_user_ptr(cntrs_data->counters_data), 3418 sizeof(*desc_data) * cntrs_data->ncounters)) { 3419 ret = -EFAULT; 3420 goto free; 3421 } 3422 } 3423 3424 if (!mcounters->hw_cntrs_hndl) { 3425 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3426 to_mdev(ibcounters->device)->mdev, false); 3427 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3428 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3429 goto free; 3430 } 3431 hw_hndl = true; 3432 } 3433 3434 if (desc_data) { 3435 /* counters already bound to at least one flow */ 3436 if (mcounters->cntrs_max_index) { 3437 ret = -EINVAL; 3438 goto free_hndl; 3439 } 3440 3441 ret = counters_set_description(ibcounters, 3442 MLX5_IB_COUNTERS_FLOW, 3443 desc_data, 3444 cntrs_data->ncounters); 3445 if (ret) 3446 goto free_hndl; 3447 3448 } else if (!mcounters->cntrs_max_index) { 3449 /* counters not bound yet, must have udata passed */ 3450 ret = -EINVAL; 3451 goto free_hndl; 3452 } 3453 3454 return 0; 3455 3456 free_hndl: 3457 if (hw_hndl) { 3458 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3459 mcounters->hw_cntrs_hndl); 3460 mcounters->hw_cntrs_hndl = NULL; 3461 } 3462 free: 3463 kfree(desc_data); 3464 return ret; 3465 } 3466 3467 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3468 struct mlx5_ib_flow_prio *ft_prio, 3469 const struct ib_flow_attr *flow_attr, 3470 struct mlx5_flow_destination *dst, 3471 u32 underlay_qpn, 3472 struct mlx5_ib_create_flow *ucmd) 3473 { 3474 struct mlx5_flow_table *ft = ft_prio->flow_table; 3475 struct mlx5_ib_flow_handler *handler; 3476 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3477 struct mlx5_flow_spec *spec; 3478 struct mlx5_flow_destination dest_arr[2] = {}; 3479 struct mlx5_flow_destination *rule_dst = dest_arr; 3480 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3481 unsigned int spec_index; 3482 u32 prev_type = 0; 3483 int err = 0; 3484 int dest_num = 0; 3485 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3486 3487 if (!is_valid_attr(dev->mdev, flow_attr)) 3488 return ERR_PTR(-EINVAL); 3489 3490 if (dev->is_rep && is_egress) 3491 return ERR_PTR(-EINVAL); 3492 3493 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3494 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3495 if (!handler || !spec) { 3496 err = -ENOMEM; 3497 goto free; 3498 } 3499 3500 INIT_LIST_HEAD(&handler->list); 3501 if (dst) { 3502 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3503 dest_num++; 3504 } 3505 3506 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3507 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3508 spec->match_value, 3509 ib_flow, flow_attr, &flow_act, 3510 prev_type); 3511 if (err < 0) 3512 goto free; 3513 3514 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3515 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3516 } 3517 3518 if (!flow_is_multicast_only(flow_attr)) 3519 set_underlay_qp(dev, spec, underlay_qpn); 3520 3521 if (dev->is_rep) { 3522 void *misc; 3523 3524 if (!dev->port[flow_attr->port - 1].rep) { 3525 err = -EINVAL; 3526 goto free; 3527 } 3528 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3529 misc_parameters); 3530 MLX5_SET(fte_match_set_misc, misc, source_port, 3531 dev->port[flow_attr->port - 1].rep->vport); 3532 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3533 misc_parameters); 3534 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3535 } 3536 3537 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3538 3539 if (is_egress && 3540 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3541 err = -EINVAL; 3542 goto free; 3543 } 3544 3545 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3546 struct mlx5_ib_mcounters *mcounters; 3547 3548 err = flow_counters_set_data(flow_act.counters, ucmd); 3549 if (err) 3550 goto free; 3551 3552 mcounters = to_mcounters(flow_act.counters); 3553 handler->ibcounters = flow_act.counters; 3554 dest_arr[dest_num].type = 3555 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3556 dest_arr[dest_num].counter_id = 3557 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3558 dest_num++; 3559 } 3560 3561 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3562 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3563 rule_dst = NULL; 3564 dest_num = 0; 3565 } 3566 } else { 3567 if (is_egress) 3568 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3569 else 3570 flow_act.action |= 3571 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3572 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3573 } 3574 3575 if ((flow_act.flags & FLOW_ACT_HAS_TAG) && 3576 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3577 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3578 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3579 flow_act.flow_tag, flow_attr->type); 3580 err = -EINVAL; 3581 goto free; 3582 } 3583 handler->rule = mlx5_add_flow_rules(ft, spec, 3584 &flow_act, 3585 rule_dst, dest_num); 3586 3587 if (IS_ERR(handler->rule)) { 3588 err = PTR_ERR(handler->rule); 3589 goto free; 3590 } 3591 3592 ft_prio->refcount++; 3593 handler->prio = ft_prio; 3594 handler->dev = dev; 3595 3596 ft_prio->flow_table = ft; 3597 free: 3598 if (err && handler) { 3599 if (handler->ibcounters && 3600 atomic_read(&handler->ibcounters->usecnt) == 1) 3601 counters_clear_description(handler->ibcounters); 3602 kfree(handler); 3603 } 3604 kvfree(spec); 3605 return err ? ERR_PTR(err) : handler; 3606 } 3607 3608 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3609 struct mlx5_ib_flow_prio *ft_prio, 3610 const struct ib_flow_attr *flow_attr, 3611 struct mlx5_flow_destination *dst) 3612 { 3613 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3614 } 3615 3616 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3617 struct mlx5_ib_flow_prio *ft_prio, 3618 struct ib_flow_attr *flow_attr, 3619 struct mlx5_flow_destination *dst) 3620 { 3621 struct mlx5_ib_flow_handler *handler_dst = NULL; 3622 struct mlx5_ib_flow_handler *handler = NULL; 3623 3624 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3625 if (!IS_ERR(handler)) { 3626 handler_dst = create_flow_rule(dev, ft_prio, 3627 flow_attr, dst); 3628 if (IS_ERR(handler_dst)) { 3629 mlx5_del_flow_rules(handler->rule); 3630 ft_prio->refcount--; 3631 kfree(handler); 3632 handler = handler_dst; 3633 } else { 3634 list_add(&handler_dst->list, &handler->list); 3635 } 3636 } 3637 3638 return handler; 3639 } 3640 enum { 3641 LEFTOVERS_MC, 3642 LEFTOVERS_UC, 3643 }; 3644 3645 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3646 struct mlx5_ib_flow_prio *ft_prio, 3647 struct ib_flow_attr *flow_attr, 3648 struct mlx5_flow_destination *dst) 3649 { 3650 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3651 struct mlx5_ib_flow_handler *handler = NULL; 3652 3653 static struct { 3654 struct ib_flow_attr flow_attr; 3655 struct ib_flow_spec_eth eth_flow; 3656 } leftovers_specs[] = { 3657 [LEFTOVERS_MC] = { 3658 .flow_attr = { 3659 .num_of_specs = 1, 3660 .size = sizeof(leftovers_specs[0]) 3661 }, 3662 .eth_flow = { 3663 .type = IB_FLOW_SPEC_ETH, 3664 .size = sizeof(struct ib_flow_spec_eth), 3665 .mask = {.dst_mac = {0x1} }, 3666 .val = {.dst_mac = {0x1} } 3667 } 3668 }, 3669 [LEFTOVERS_UC] = { 3670 .flow_attr = { 3671 .num_of_specs = 1, 3672 .size = sizeof(leftovers_specs[0]) 3673 }, 3674 .eth_flow = { 3675 .type = IB_FLOW_SPEC_ETH, 3676 .size = sizeof(struct ib_flow_spec_eth), 3677 .mask = {.dst_mac = {0x1} }, 3678 .val = {.dst_mac = {} } 3679 } 3680 } 3681 }; 3682 3683 handler = create_flow_rule(dev, ft_prio, 3684 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3685 dst); 3686 if (!IS_ERR(handler) && 3687 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3688 handler_ucast = create_flow_rule(dev, ft_prio, 3689 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3690 dst); 3691 if (IS_ERR(handler_ucast)) { 3692 mlx5_del_flow_rules(handler->rule); 3693 ft_prio->refcount--; 3694 kfree(handler); 3695 handler = handler_ucast; 3696 } else { 3697 list_add(&handler_ucast->list, &handler->list); 3698 } 3699 } 3700 3701 return handler; 3702 } 3703 3704 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3705 struct mlx5_ib_flow_prio *ft_rx, 3706 struct mlx5_ib_flow_prio *ft_tx, 3707 struct mlx5_flow_destination *dst) 3708 { 3709 struct mlx5_ib_flow_handler *handler_rx; 3710 struct mlx5_ib_flow_handler *handler_tx; 3711 int err; 3712 static const struct ib_flow_attr flow_attr = { 3713 .num_of_specs = 0, 3714 .size = sizeof(flow_attr) 3715 }; 3716 3717 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3718 if (IS_ERR(handler_rx)) { 3719 err = PTR_ERR(handler_rx); 3720 goto err; 3721 } 3722 3723 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3724 if (IS_ERR(handler_tx)) { 3725 err = PTR_ERR(handler_tx); 3726 goto err_tx; 3727 } 3728 3729 list_add(&handler_tx->list, &handler_rx->list); 3730 3731 return handler_rx; 3732 3733 err_tx: 3734 mlx5_del_flow_rules(handler_rx->rule); 3735 ft_rx->refcount--; 3736 kfree(handler_rx); 3737 err: 3738 return ERR_PTR(err); 3739 } 3740 3741 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3742 struct ib_flow_attr *flow_attr, 3743 int domain, 3744 struct ib_udata *udata) 3745 { 3746 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3747 struct mlx5_ib_qp *mqp = to_mqp(qp); 3748 struct mlx5_ib_flow_handler *handler = NULL; 3749 struct mlx5_flow_destination *dst = NULL; 3750 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3751 struct mlx5_ib_flow_prio *ft_prio; 3752 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3753 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3754 size_t min_ucmd_sz, required_ucmd_sz; 3755 int err; 3756 int underlay_qpn; 3757 3758 if (udata && udata->inlen) { 3759 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3760 sizeof(ucmd_hdr.reserved); 3761 if (udata->inlen < min_ucmd_sz) 3762 return ERR_PTR(-EOPNOTSUPP); 3763 3764 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3765 if (err) 3766 return ERR_PTR(err); 3767 3768 /* currently supports only one counters data */ 3769 if (ucmd_hdr.ncounters_data > 1) 3770 return ERR_PTR(-EINVAL); 3771 3772 required_ucmd_sz = min_ucmd_sz + 3773 sizeof(struct mlx5_ib_flow_counters_data) * 3774 ucmd_hdr.ncounters_data; 3775 if (udata->inlen > required_ucmd_sz && 3776 !ib_is_udata_cleared(udata, required_ucmd_sz, 3777 udata->inlen - required_ucmd_sz)) 3778 return ERR_PTR(-EOPNOTSUPP); 3779 3780 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3781 if (!ucmd) 3782 return ERR_PTR(-ENOMEM); 3783 3784 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3785 if (err) 3786 goto free_ucmd; 3787 } 3788 3789 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3790 err = -ENOMEM; 3791 goto free_ucmd; 3792 } 3793 3794 if (domain != IB_FLOW_DOMAIN_USER || 3795 flow_attr->port > dev->num_ports || 3796 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3797 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3798 err = -EINVAL; 3799 goto free_ucmd; 3800 } 3801 3802 if (is_egress && 3803 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3804 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3805 err = -EINVAL; 3806 goto free_ucmd; 3807 } 3808 3809 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3810 if (!dst) { 3811 err = -ENOMEM; 3812 goto free_ucmd; 3813 } 3814 3815 mutex_lock(&dev->flow_db->lock); 3816 3817 ft_prio = get_flow_table(dev, flow_attr, 3818 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3819 if (IS_ERR(ft_prio)) { 3820 err = PTR_ERR(ft_prio); 3821 goto unlock; 3822 } 3823 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3824 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3825 if (IS_ERR(ft_prio_tx)) { 3826 err = PTR_ERR(ft_prio_tx); 3827 ft_prio_tx = NULL; 3828 goto destroy_ft; 3829 } 3830 } 3831 3832 if (is_egress) { 3833 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3834 } else { 3835 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3836 if (mqp->flags & MLX5_IB_QP_RSS) 3837 dst->tir_num = mqp->rss_qp.tirn; 3838 else 3839 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3840 } 3841 3842 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3843 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3844 handler = create_dont_trap_rule(dev, ft_prio, 3845 flow_attr, dst); 3846 } else { 3847 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3848 mqp->underlay_qpn : 0; 3849 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3850 dst, underlay_qpn, ucmd); 3851 } 3852 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3853 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3854 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3855 dst); 3856 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3857 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3858 } else { 3859 err = -EINVAL; 3860 goto destroy_ft; 3861 } 3862 3863 if (IS_ERR(handler)) { 3864 err = PTR_ERR(handler); 3865 handler = NULL; 3866 goto destroy_ft; 3867 } 3868 3869 mutex_unlock(&dev->flow_db->lock); 3870 kfree(dst); 3871 kfree(ucmd); 3872 3873 return &handler->ibflow; 3874 3875 destroy_ft: 3876 put_flow_table(dev, ft_prio, false); 3877 if (ft_prio_tx) 3878 put_flow_table(dev, ft_prio_tx, false); 3879 unlock: 3880 mutex_unlock(&dev->flow_db->lock); 3881 kfree(dst); 3882 free_ucmd: 3883 kfree(ucmd); 3884 return ERR_PTR(err); 3885 } 3886 3887 static struct mlx5_ib_flow_prio * 3888 _get_flow_table(struct mlx5_ib_dev *dev, 3889 struct mlx5_ib_flow_matcher *fs_matcher, 3890 bool mcast) 3891 { 3892 struct mlx5_flow_namespace *ns = NULL; 3893 struct mlx5_ib_flow_prio *prio = NULL; 3894 int max_table_size = 0; 3895 u32 flags = 0; 3896 int priority; 3897 3898 if (mcast) 3899 priority = MLX5_IB_FLOW_MCAST_PRIO; 3900 else 3901 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3902 3903 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3904 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3905 log_max_ft_size)); 3906 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3907 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3908 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3909 reformat_l3_tunnel_to_l2)) 3910 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3911 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) { 3912 max_table_size = BIT( 3913 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size)); 3914 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3915 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3916 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) { 3917 max_table_size = BIT( 3918 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size)); 3919 priority = FDB_BYPASS_PATH; 3920 } 3921 3922 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES); 3923 3924 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3925 if (!ns) 3926 return ERR_PTR(-ENOTSUPP); 3927 3928 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3929 prio = &dev->flow_db->prios[priority]; 3930 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) 3931 prio = &dev->flow_db->egress_prios[priority]; 3932 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) 3933 prio = &dev->flow_db->fdb; 3934 3935 if (!prio) 3936 return ERR_PTR(-EINVAL); 3937 3938 if (prio->flow_table) 3939 return prio; 3940 3941 return _get_prio(ns, prio, priority, max_table_size, 3942 MLX5_FS_MAX_TYPES, flags); 3943 } 3944 3945 static struct mlx5_ib_flow_handler * 3946 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3947 struct mlx5_ib_flow_prio *ft_prio, 3948 struct mlx5_flow_destination *dst, 3949 struct mlx5_ib_flow_matcher *fs_matcher, 3950 struct mlx5_flow_act *flow_act, 3951 void *cmd_in, int inlen, 3952 int dst_num) 3953 { 3954 struct mlx5_ib_flow_handler *handler; 3955 struct mlx5_flow_spec *spec; 3956 struct mlx5_flow_table *ft = ft_prio->flow_table; 3957 int err = 0; 3958 3959 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3960 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3961 if (!handler || !spec) { 3962 err = -ENOMEM; 3963 goto free; 3964 } 3965 3966 INIT_LIST_HEAD(&handler->list); 3967 3968 memcpy(spec->match_value, cmd_in, inlen); 3969 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3970 fs_matcher->mask_len); 3971 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3972 3973 handler->rule = mlx5_add_flow_rules(ft, spec, 3974 flow_act, dst, dst_num); 3975 3976 if (IS_ERR(handler->rule)) { 3977 err = PTR_ERR(handler->rule); 3978 goto free; 3979 } 3980 3981 ft_prio->refcount++; 3982 handler->prio = ft_prio; 3983 handler->dev = dev; 3984 ft_prio->flow_table = ft; 3985 3986 free: 3987 if (err) 3988 kfree(handler); 3989 kvfree(spec); 3990 return err ? ERR_PTR(err) : handler; 3991 } 3992 3993 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3994 void *match_v) 3995 { 3996 void *match_c; 3997 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3998 void *dmac, *dmac_mask; 3999 void *ipv4, *ipv4_mask; 4000 4001 if (!(fs_matcher->match_criteria_enable & 4002 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 4003 return false; 4004 4005 match_c = fs_matcher->matcher_mask.match_params; 4006 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 4007 outer_headers); 4008 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 4009 outer_headers); 4010 4011 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 4012 dmac_47_16); 4013 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 4014 dmac_47_16); 4015 4016 if (is_multicast_ether_addr(dmac) && 4017 is_multicast_ether_addr(dmac_mask)) 4018 return true; 4019 4020 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 4021 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 4022 4023 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 4024 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 4025 4026 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 4027 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 4028 return true; 4029 4030 return false; 4031 } 4032 4033 struct mlx5_ib_flow_handler * 4034 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 4035 struct mlx5_ib_flow_matcher *fs_matcher, 4036 struct mlx5_flow_act *flow_act, 4037 u32 counter_id, 4038 void *cmd_in, int inlen, int dest_id, 4039 int dest_type) 4040 { 4041 struct mlx5_flow_destination *dst; 4042 struct mlx5_ib_flow_prio *ft_prio; 4043 struct mlx5_ib_flow_handler *handler; 4044 int dst_num = 0; 4045 bool mcast; 4046 int err; 4047 4048 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 4049 return ERR_PTR(-EOPNOTSUPP); 4050 4051 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 4052 return ERR_PTR(-ENOMEM); 4053 4054 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL); 4055 if (!dst) 4056 return ERR_PTR(-ENOMEM); 4057 4058 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 4059 mutex_lock(&dev->flow_db->lock); 4060 4061 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 4062 if (IS_ERR(ft_prio)) { 4063 err = PTR_ERR(ft_prio); 4064 goto unlock; 4065 } 4066 4067 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 4068 dst[dst_num].type = dest_type; 4069 dst[dst_num].tir_num = dest_id; 4070 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 4071 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 4072 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 4073 dst[dst_num].ft_num = dest_id; 4074 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 4075 } else { 4076 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT; 4077 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 4078 } 4079 4080 dst_num++; 4081 4082 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 4083 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; 4084 dst[dst_num].counter_id = counter_id; 4085 dst_num++; 4086 } 4087 4088 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 4089 cmd_in, inlen, dst_num); 4090 4091 if (IS_ERR(handler)) { 4092 err = PTR_ERR(handler); 4093 goto destroy_ft; 4094 } 4095 4096 mutex_unlock(&dev->flow_db->lock); 4097 atomic_inc(&fs_matcher->usecnt); 4098 handler->flow_matcher = fs_matcher; 4099 4100 kfree(dst); 4101 4102 return handler; 4103 4104 destroy_ft: 4105 put_flow_table(dev, ft_prio, false); 4106 unlock: 4107 mutex_unlock(&dev->flow_db->lock); 4108 kfree(dst); 4109 4110 return ERR_PTR(err); 4111 } 4112 4113 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 4114 { 4115 u32 flags = 0; 4116 4117 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 4118 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 4119 4120 return flags; 4121 } 4122 4123 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 4124 static struct ib_flow_action * 4125 mlx5_ib_create_flow_action_esp(struct ib_device *device, 4126 const struct ib_flow_action_attrs_esp *attr, 4127 struct uverbs_attr_bundle *attrs) 4128 { 4129 struct mlx5_ib_dev *mdev = to_mdev(device); 4130 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 4131 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 4132 struct mlx5_ib_flow_action *action; 4133 u64 action_flags; 4134 u64 flags; 4135 int err = 0; 4136 4137 err = uverbs_get_flags64( 4138 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 4139 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 4140 if (err) 4141 return ERR_PTR(err); 4142 4143 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 4144 4145 /* We current only support a subset of the standard features. Only a 4146 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 4147 * (with overlap). Full offload mode isn't supported. 4148 */ 4149 if (!attr->keymat || attr->replay || attr->encap || 4150 attr->spi || attr->seq || attr->tfc_pad || 4151 attr->hard_limit_pkts || 4152 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4153 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 4154 return ERR_PTR(-EOPNOTSUPP); 4155 4156 if (attr->keymat->protocol != 4157 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 4158 return ERR_PTR(-EOPNOTSUPP); 4159 4160 aes_gcm = &attr->keymat->keymat.aes_gcm; 4161 4162 if (aes_gcm->icv_len != 16 || 4163 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 4164 return ERR_PTR(-EOPNOTSUPP); 4165 4166 action = kmalloc(sizeof(*action), GFP_KERNEL); 4167 if (!action) 4168 return ERR_PTR(-ENOMEM); 4169 4170 action->esp_aes_gcm.ib_flags = attr->flags; 4171 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 4172 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 4173 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 4174 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 4175 sizeof(accel_attrs.keymat.aes_gcm.salt)); 4176 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 4177 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 4178 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 4179 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 4180 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 4181 4182 accel_attrs.esn = attr->esn; 4183 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 4184 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 4185 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4186 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4187 4188 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 4189 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 4190 4191 action->esp_aes_gcm.ctx = 4192 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 4193 if (IS_ERR(action->esp_aes_gcm.ctx)) { 4194 err = PTR_ERR(action->esp_aes_gcm.ctx); 4195 goto err_parse; 4196 } 4197 4198 action->esp_aes_gcm.ib_flags = attr->flags; 4199 4200 return &action->ib_action; 4201 4202 err_parse: 4203 kfree(action); 4204 return ERR_PTR(err); 4205 } 4206 4207 static int 4208 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 4209 const struct ib_flow_action_attrs_esp *attr, 4210 struct uverbs_attr_bundle *attrs) 4211 { 4212 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4213 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 4214 int err = 0; 4215 4216 if (attr->keymat || attr->replay || attr->encap || 4217 attr->spi || attr->seq || attr->tfc_pad || 4218 attr->hard_limit_pkts || 4219 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4220 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 4221 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 4222 return -EOPNOTSUPP; 4223 4224 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 4225 * be modified. 4226 */ 4227 if (!(maction->esp_aes_gcm.ib_flags & 4228 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 4229 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4230 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 4231 return -EINVAL; 4232 4233 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 4234 sizeof(accel_attrs)); 4235 4236 accel_attrs.esn = attr->esn; 4237 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4238 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4239 else 4240 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4241 4242 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 4243 &accel_attrs); 4244 if (err) 4245 return err; 4246 4247 maction->esp_aes_gcm.ib_flags &= 4248 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4249 maction->esp_aes_gcm.ib_flags |= 4250 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4251 4252 return 0; 4253 } 4254 4255 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4256 { 4257 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4258 4259 switch (action->type) { 4260 case IB_FLOW_ACTION_ESP: 4261 /* 4262 * We only support aes_gcm by now, so we implicitly know this is 4263 * the underline crypto. 4264 */ 4265 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4266 break; 4267 case IB_FLOW_ACTION_UNSPECIFIED: 4268 mlx5_ib_destroy_flow_action_raw(maction); 4269 break; 4270 default: 4271 WARN_ON(true); 4272 break; 4273 } 4274 4275 kfree(maction); 4276 return 0; 4277 } 4278 4279 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4280 { 4281 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4282 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4283 int err; 4284 u16 uid; 4285 4286 uid = ibqp->pd ? 4287 to_mpd(ibqp->pd)->uid : 0; 4288 4289 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4290 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4291 return -EOPNOTSUPP; 4292 } 4293 4294 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4295 if (err) 4296 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4297 ibqp->qp_num, gid->raw); 4298 4299 return err; 4300 } 4301 4302 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4303 { 4304 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4305 int err; 4306 u16 uid; 4307 4308 uid = ibqp->pd ? 4309 to_mpd(ibqp->pd)->uid : 0; 4310 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4311 if (err) 4312 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4313 ibqp->qp_num, gid->raw); 4314 4315 return err; 4316 } 4317 4318 static int init_node_data(struct mlx5_ib_dev *dev) 4319 { 4320 int err; 4321 4322 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4323 if (err) 4324 return err; 4325 4326 dev->mdev->rev_id = dev->mdev->pdev->revision; 4327 4328 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4329 } 4330 4331 static ssize_t fw_pages_show(struct device *device, 4332 struct device_attribute *attr, char *buf) 4333 { 4334 struct mlx5_ib_dev *dev = 4335 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4336 4337 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4338 } 4339 static DEVICE_ATTR_RO(fw_pages); 4340 4341 static ssize_t reg_pages_show(struct device *device, 4342 struct device_attribute *attr, char *buf) 4343 { 4344 struct mlx5_ib_dev *dev = 4345 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4346 4347 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4348 } 4349 static DEVICE_ATTR_RO(reg_pages); 4350 4351 static ssize_t hca_type_show(struct device *device, 4352 struct device_attribute *attr, char *buf) 4353 { 4354 struct mlx5_ib_dev *dev = 4355 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4356 4357 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4358 } 4359 static DEVICE_ATTR_RO(hca_type); 4360 4361 static ssize_t hw_rev_show(struct device *device, 4362 struct device_attribute *attr, char *buf) 4363 { 4364 struct mlx5_ib_dev *dev = 4365 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4366 4367 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4368 } 4369 static DEVICE_ATTR_RO(hw_rev); 4370 4371 static ssize_t board_id_show(struct device *device, 4372 struct device_attribute *attr, char *buf) 4373 { 4374 struct mlx5_ib_dev *dev = 4375 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4376 4377 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4378 dev->mdev->board_id); 4379 } 4380 static DEVICE_ATTR_RO(board_id); 4381 4382 static struct attribute *mlx5_class_attributes[] = { 4383 &dev_attr_hw_rev.attr, 4384 &dev_attr_hca_type.attr, 4385 &dev_attr_board_id.attr, 4386 &dev_attr_fw_pages.attr, 4387 &dev_attr_reg_pages.attr, 4388 NULL, 4389 }; 4390 4391 static const struct attribute_group mlx5_attr_group = { 4392 .attrs = mlx5_class_attributes, 4393 }; 4394 4395 static void pkey_change_handler(struct work_struct *work) 4396 { 4397 struct mlx5_ib_port_resources *ports = 4398 container_of(work, struct mlx5_ib_port_resources, 4399 pkey_change_work); 4400 4401 mutex_lock(&ports->devr->mutex); 4402 mlx5_ib_gsi_pkey_change(ports->gsi); 4403 mutex_unlock(&ports->devr->mutex); 4404 } 4405 4406 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4407 { 4408 struct mlx5_ib_qp *mqp; 4409 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4410 struct mlx5_core_cq *mcq; 4411 struct list_head cq_armed_list; 4412 unsigned long flags_qp; 4413 unsigned long flags_cq; 4414 unsigned long flags; 4415 4416 INIT_LIST_HEAD(&cq_armed_list); 4417 4418 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4419 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4420 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4421 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4422 if (mqp->sq.tail != mqp->sq.head) { 4423 send_mcq = to_mcq(mqp->ibqp.send_cq); 4424 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4425 if (send_mcq->mcq.comp && 4426 mqp->ibqp.send_cq->comp_handler) { 4427 if (!send_mcq->mcq.reset_notify_added) { 4428 send_mcq->mcq.reset_notify_added = 1; 4429 list_add_tail(&send_mcq->mcq.reset_notify, 4430 &cq_armed_list); 4431 } 4432 } 4433 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4434 } 4435 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4436 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4437 /* no handling is needed for SRQ */ 4438 if (!mqp->ibqp.srq) { 4439 if (mqp->rq.tail != mqp->rq.head) { 4440 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4441 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4442 if (recv_mcq->mcq.comp && 4443 mqp->ibqp.recv_cq->comp_handler) { 4444 if (!recv_mcq->mcq.reset_notify_added) { 4445 recv_mcq->mcq.reset_notify_added = 1; 4446 list_add_tail(&recv_mcq->mcq.reset_notify, 4447 &cq_armed_list); 4448 } 4449 } 4450 spin_unlock_irqrestore(&recv_mcq->lock, 4451 flags_cq); 4452 } 4453 } 4454 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4455 } 4456 /*At that point all inflight post send were put to be executed as of we 4457 * lock/unlock above locks Now need to arm all involved CQs. 4458 */ 4459 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4460 mcq->comp(mcq); 4461 } 4462 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4463 } 4464 4465 static void delay_drop_handler(struct work_struct *work) 4466 { 4467 int err; 4468 struct mlx5_ib_delay_drop *delay_drop = 4469 container_of(work, struct mlx5_ib_delay_drop, 4470 delay_drop_work); 4471 4472 atomic_inc(&delay_drop->events_cnt); 4473 4474 mutex_lock(&delay_drop->lock); 4475 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4476 delay_drop->timeout); 4477 if (err) { 4478 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4479 delay_drop->timeout); 4480 delay_drop->activate = false; 4481 } 4482 mutex_unlock(&delay_drop->lock); 4483 } 4484 4485 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4486 struct ib_event *ibev) 4487 { 4488 u8 port = (eqe->data.port.port >> 4) & 0xf; 4489 4490 switch (eqe->sub_type) { 4491 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 4492 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4493 IB_LINK_LAYER_ETHERNET) 4494 schedule_work(&ibdev->delay_drop.delay_drop_work); 4495 break; 4496 default: /* do nothing */ 4497 return; 4498 } 4499 } 4500 4501 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4502 struct ib_event *ibev) 4503 { 4504 u8 port = (eqe->data.port.port >> 4) & 0xf; 4505 4506 ibev->element.port_num = port; 4507 4508 switch (eqe->sub_type) { 4509 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 4510 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 4511 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 4512 /* In RoCE, port up/down events are handled in 4513 * mlx5_netdev_event(). 4514 */ 4515 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4516 IB_LINK_LAYER_ETHERNET) 4517 return -EINVAL; 4518 4519 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 4520 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4521 break; 4522 4523 case MLX5_PORT_CHANGE_SUBTYPE_LID: 4524 ibev->event = IB_EVENT_LID_CHANGE; 4525 break; 4526 4527 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 4528 ibev->event = IB_EVENT_PKEY_CHANGE; 4529 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4530 break; 4531 4532 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 4533 ibev->event = IB_EVENT_GID_CHANGE; 4534 break; 4535 4536 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 4537 ibev->event = IB_EVENT_CLIENT_REREGISTER; 4538 break; 4539 default: 4540 return -EINVAL; 4541 } 4542 4543 return 0; 4544 } 4545 4546 static void mlx5_ib_handle_event(struct work_struct *_work) 4547 { 4548 struct mlx5_ib_event_work *work = 4549 container_of(_work, struct mlx5_ib_event_work, work); 4550 struct mlx5_ib_dev *ibdev; 4551 struct ib_event ibev; 4552 bool fatal = false; 4553 4554 if (work->is_slave) { 4555 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 4556 if (!ibdev) 4557 goto out; 4558 } else { 4559 ibdev = work->dev; 4560 } 4561 4562 switch (work->event) { 4563 case MLX5_DEV_EVENT_SYS_ERROR: 4564 ibev.event = IB_EVENT_DEVICE_FATAL; 4565 mlx5_ib_handle_internal_error(ibdev); 4566 ibev.element.port_num = (u8)(unsigned long)work->param; 4567 fatal = true; 4568 break; 4569 case MLX5_EVENT_TYPE_PORT_CHANGE: 4570 if (handle_port_change(ibdev, work->param, &ibev)) 4571 goto out; 4572 break; 4573 case MLX5_EVENT_TYPE_GENERAL_EVENT: 4574 handle_general_event(ibdev, work->param, &ibev); 4575 /* fall through */ 4576 default: 4577 goto out; 4578 } 4579 4580 ibev.device = &ibdev->ib_dev; 4581 4582 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 4583 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 4584 goto out; 4585 } 4586 4587 if (ibdev->ib_active) 4588 ib_dispatch_event(&ibev); 4589 4590 if (fatal) 4591 ibdev->ib_active = false; 4592 out: 4593 kfree(work); 4594 } 4595 4596 static int mlx5_ib_event(struct notifier_block *nb, 4597 unsigned long event, void *param) 4598 { 4599 struct mlx5_ib_event_work *work; 4600 4601 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4602 if (!work) 4603 return NOTIFY_DONE; 4604 4605 INIT_WORK(&work->work, mlx5_ib_handle_event); 4606 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 4607 work->is_slave = false; 4608 work->param = param; 4609 work->event = event; 4610 4611 queue_work(mlx5_ib_event_wq, &work->work); 4612 4613 return NOTIFY_OK; 4614 } 4615 4616 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 4617 unsigned long event, void *param) 4618 { 4619 struct mlx5_ib_event_work *work; 4620 4621 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4622 if (!work) 4623 return NOTIFY_DONE; 4624 4625 INIT_WORK(&work->work, mlx5_ib_handle_event); 4626 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 4627 work->is_slave = true; 4628 work->param = param; 4629 work->event = event; 4630 queue_work(mlx5_ib_event_wq, &work->work); 4631 4632 return NOTIFY_OK; 4633 } 4634 4635 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4636 { 4637 struct mlx5_hca_vport_context vport_ctx; 4638 int err; 4639 int port; 4640 4641 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) { 4642 dev->mdev->port_caps[port - 1].has_smi = false; 4643 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4644 MLX5_CAP_PORT_TYPE_IB) { 4645 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4646 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4647 port, 0, 4648 &vport_ctx); 4649 if (err) { 4650 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4651 port, err); 4652 return err; 4653 } 4654 dev->mdev->port_caps[port - 1].has_smi = 4655 vport_ctx.has_smi; 4656 } else { 4657 dev->mdev->port_caps[port - 1].has_smi = true; 4658 } 4659 } 4660 } 4661 return 0; 4662 } 4663 4664 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4665 { 4666 int port; 4667 4668 for (port = 1; port <= dev->num_ports; port++) 4669 mlx5_query_ext_port_caps(dev, port); 4670 } 4671 4672 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4673 { 4674 struct ib_device_attr *dprops = NULL; 4675 struct ib_port_attr *pprops = NULL; 4676 int err = -ENOMEM; 4677 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4678 4679 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4680 if (!pprops) 4681 goto out; 4682 4683 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4684 if (!dprops) 4685 goto out; 4686 4687 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4688 if (err) { 4689 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4690 goto out; 4691 } 4692 4693 memset(pprops, 0, sizeof(*pprops)); 4694 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4695 if (err) { 4696 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4697 port, err); 4698 goto out; 4699 } 4700 4701 dev->mdev->port_caps[port - 1].pkey_table_len = 4702 dprops->max_pkeys; 4703 dev->mdev->port_caps[port - 1].gid_table_len = 4704 pprops->gid_tbl_len; 4705 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4706 port, dprops->max_pkeys, pprops->gid_tbl_len); 4707 4708 out: 4709 kfree(pprops); 4710 kfree(dprops); 4711 4712 return err; 4713 } 4714 4715 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4716 { 4717 /* For representors use port 1, is this is the only native 4718 * port 4719 */ 4720 if (dev->is_rep) 4721 return __get_port_caps(dev, 1); 4722 return __get_port_caps(dev, port); 4723 } 4724 4725 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4726 { 4727 int err; 4728 4729 err = mlx5_mr_cache_cleanup(dev); 4730 if (err) 4731 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4732 4733 if (dev->umrc.qp) 4734 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4735 if (dev->umrc.cq) 4736 ib_free_cq(dev->umrc.cq); 4737 if (dev->umrc.pd) 4738 ib_dealloc_pd(dev->umrc.pd); 4739 } 4740 4741 enum { 4742 MAX_UMR_WR = 128, 4743 }; 4744 4745 static int create_umr_res(struct mlx5_ib_dev *dev) 4746 { 4747 struct ib_qp_init_attr *init_attr = NULL; 4748 struct ib_qp_attr *attr = NULL; 4749 struct ib_pd *pd; 4750 struct ib_cq *cq; 4751 struct ib_qp *qp; 4752 int ret; 4753 4754 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4755 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4756 if (!attr || !init_attr) { 4757 ret = -ENOMEM; 4758 goto error_0; 4759 } 4760 4761 pd = ib_alloc_pd(&dev->ib_dev, 0); 4762 if (IS_ERR(pd)) { 4763 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4764 ret = PTR_ERR(pd); 4765 goto error_0; 4766 } 4767 4768 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4769 if (IS_ERR(cq)) { 4770 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4771 ret = PTR_ERR(cq); 4772 goto error_2; 4773 } 4774 4775 init_attr->send_cq = cq; 4776 init_attr->recv_cq = cq; 4777 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4778 init_attr->cap.max_send_wr = MAX_UMR_WR; 4779 init_attr->cap.max_send_sge = 1; 4780 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4781 init_attr->port_num = 1; 4782 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4783 if (IS_ERR(qp)) { 4784 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4785 ret = PTR_ERR(qp); 4786 goto error_3; 4787 } 4788 qp->device = &dev->ib_dev; 4789 qp->real_qp = qp; 4790 qp->uobject = NULL; 4791 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4792 qp->send_cq = init_attr->send_cq; 4793 qp->recv_cq = init_attr->recv_cq; 4794 4795 attr->qp_state = IB_QPS_INIT; 4796 attr->port_num = 1; 4797 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4798 IB_QP_PORT, NULL); 4799 if (ret) { 4800 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4801 goto error_4; 4802 } 4803 4804 memset(attr, 0, sizeof(*attr)); 4805 attr->qp_state = IB_QPS_RTR; 4806 attr->path_mtu = IB_MTU_256; 4807 4808 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4809 if (ret) { 4810 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4811 goto error_4; 4812 } 4813 4814 memset(attr, 0, sizeof(*attr)); 4815 attr->qp_state = IB_QPS_RTS; 4816 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4817 if (ret) { 4818 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4819 goto error_4; 4820 } 4821 4822 dev->umrc.qp = qp; 4823 dev->umrc.cq = cq; 4824 dev->umrc.pd = pd; 4825 4826 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4827 ret = mlx5_mr_cache_init(dev); 4828 if (ret) { 4829 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4830 goto error_4; 4831 } 4832 4833 kfree(attr); 4834 kfree(init_attr); 4835 4836 return 0; 4837 4838 error_4: 4839 mlx5_ib_destroy_qp(qp, NULL); 4840 dev->umrc.qp = NULL; 4841 4842 error_3: 4843 ib_free_cq(cq); 4844 dev->umrc.cq = NULL; 4845 4846 error_2: 4847 ib_dealloc_pd(pd); 4848 dev->umrc.pd = NULL; 4849 4850 error_0: 4851 kfree(attr); 4852 kfree(init_attr); 4853 return ret; 4854 } 4855 4856 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4857 { 4858 switch (umr_fence_cap) { 4859 case MLX5_CAP_UMR_FENCE_NONE: 4860 return MLX5_FENCE_MODE_NONE; 4861 case MLX5_CAP_UMR_FENCE_SMALL: 4862 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4863 default: 4864 return MLX5_FENCE_MODE_STRONG_ORDERING; 4865 } 4866 } 4867 4868 static int create_dev_resources(struct mlx5_ib_resources *devr) 4869 { 4870 struct ib_srq_init_attr attr; 4871 struct mlx5_ib_dev *dev; 4872 struct ib_device *ibdev; 4873 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4874 int port; 4875 int ret = 0; 4876 4877 dev = container_of(devr, struct mlx5_ib_dev, devr); 4878 ibdev = &dev->ib_dev; 4879 4880 mutex_init(&devr->mutex); 4881 4882 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 4883 if (!devr->p0) 4884 return -ENOMEM; 4885 4886 devr->p0->device = ibdev; 4887 devr->p0->uobject = NULL; 4888 atomic_set(&devr->p0->usecnt, 0); 4889 4890 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 4891 if (ret) 4892 goto error0; 4893 4894 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL); 4895 if (IS_ERR(devr->c0)) { 4896 ret = PTR_ERR(devr->c0); 4897 goto error1; 4898 } 4899 devr->c0->device = &dev->ib_dev; 4900 devr->c0->uobject = NULL; 4901 devr->c0->comp_handler = NULL; 4902 devr->c0->event_handler = NULL; 4903 devr->c0->cq_context = NULL; 4904 atomic_set(&devr->c0->usecnt, 0); 4905 4906 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 4907 if (IS_ERR(devr->x0)) { 4908 ret = PTR_ERR(devr->x0); 4909 goto error2; 4910 } 4911 devr->x0->device = &dev->ib_dev; 4912 devr->x0->inode = NULL; 4913 atomic_set(&devr->x0->usecnt, 0); 4914 mutex_init(&devr->x0->tgt_qp_mutex); 4915 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4916 4917 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 4918 if (IS_ERR(devr->x1)) { 4919 ret = PTR_ERR(devr->x1); 4920 goto error3; 4921 } 4922 devr->x1->device = &dev->ib_dev; 4923 devr->x1->inode = NULL; 4924 atomic_set(&devr->x1->usecnt, 0); 4925 mutex_init(&devr->x1->tgt_qp_mutex); 4926 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4927 4928 memset(&attr, 0, sizeof(attr)); 4929 attr.attr.max_sge = 1; 4930 attr.attr.max_wr = 1; 4931 attr.srq_type = IB_SRQT_XRC; 4932 attr.ext.cq = devr->c0; 4933 attr.ext.xrc.xrcd = devr->x0; 4934 4935 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 4936 if (!devr->s0) { 4937 ret = -ENOMEM; 4938 goto error4; 4939 } 4940 4941 devr->s0->device = &dev->ib_dev; 4942 devr->s0->pd = devr->p0; 4943 devr->s0->srq_type = IB_SRQT_XRC; 4944 devr->s0->ext.xrc.xrcd = devr->x0; 4945 devr->s0->ext.cq = devr->c0; 4946 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 4947 if (ret) 4948 goto err_create; 4949 4950 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4951 atomic_inc(&devr->s0->ext.cq->usecnt); 4952 atomic_inc(&devr->p0->usecnt); 4953 atomic_set(&devr->s0->usecnt, 0); 4954 4955 memset(&attr, 0, sizeof(attr)); 4956 attr.attr.max_sge = 1; 4957 attr.attr.max_wr = 1; 4958 attr.srq_type = IB_SRQT_BASIC; 4959 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 4960 if (!devr->s1) { 4961 ret = -ENOMEM; 4962 goto error5; 4963 } 4964 4965 devr->s1->device = &dev->ib_dev; 4966 devr->s1->pd = devr->p0; 4967 devr->s1->srq_type = IB_SRQT_BASIC; 4968 devr->s1->ext.cq = devr->c0; 4969 4970 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 4971 if (ret) 4972 goto error6; 4973 4974 atomic_inc(&devr->p0->usecnt); 4975 atomic_set(&devr->s1->usecnt, 0); 4976 4977 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4978 INIT_WORK(&devr->ports[port].pkey_change_work, 4979 pkey_change_handler); 4980 devr->ports[port].devr = devr; 4981 } 4982 4983 return 0; 4984 4985 error6: 4986 kfree(devr->s1); 4987 error5: 4988 mlx5_ib_destroy_srq(devr->s0, NULL); 4989 err_create: 4990 kfree(devr->s0); 4991 error4: 4992 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 4993 error3: 4994 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 4995 error2: 4996 mlx5_ib_destroy_cq(devr->c0, NULL); 4997 error1: 4998 mlx5_ib_dealloc_pd(devr->p0, NULL); 4999 error0: 5000 kfree(devr->p0); 5001 return ret; 5002 } 5003 5004 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 5005 { 5006 int port; 5007 5008 mlx5_ib_destroy_srq(devr->s1, NULL); 5009 kfree(devr->s1); 5010 mlx5_ib_destroy_srq(devr->s0, NULL); 5011 kfree(devr->s0); 5012 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 5013 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 5014 mlx5_ib_destroy_cq(devr->c0, NULL); 5015 mlx5_ib_dealloc_pd(devr->p0, NULL); 5016 kfree(devr->p0); 5017 5018 /* Make sure no change P_Key work items are still executing */ 5019 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5020 cancel_work_sync(&devr->ports[port].pkey_change_work); 5021 } 5022 5023 static u32 get_core_cap_flags(struct ib_device *ibdev, 5024 struct mlx5_hca_vport_context *rep) 5025 { 5026 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5027 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 5028 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 5029 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 5030 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 5031 u32 ret = 0; 5032 5033 if (rep->grh_required) 5034 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 5035 5036 if (ll == IB_LINK_LAYER_INFINIBAND) 5037 return ret | RDMA_CORE_PORT_IBA_IB; 5038 5039 if (raw_support) 5040 ret |= RDMA_CORE_PORT_RAW_PACKET; 5041 5042 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 5043 return ret; 5044 5045 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 5046 return ret; 5047 5048 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 5049 ret |= RDMA_CORE_PORT_IBA_ROCE; 5050 5051 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 5052 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 5053 5054 return ret; 5055 } 5056 5057 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 5058 struct ib_port_immutable *immutable) 5059 { 5060 struct ib_port_attr attr; 5061 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5062 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 5063 struct mlx5_hca_vport_context rep = {0}; 5064 int err; 5065 5066 err = ib_query_port(ibdev, port_num, &attr); 5067 if (err) 5068 return err; 5069 5070 if (ll == IB_LINK_LAYER_INFINIBAND) { 5071 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 5072 &rep); 5073 if (err) 5074 return err; 5075 } 5076 5077 immutable->pkey_tbl_len = attr.pkey_tbl_len; 5078 immutable->gid_tbl_len = attr.gid_tbl_len; 5079 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 5080 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 5081 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 5082 5083 return 0; 5084 } 5085 5086 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 5087 struct ib_port_immutable *immutable) 5088 { 5089 struct ib_port_attr attr; 5090 int err; 5091 5092 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 5093 5094 err = ib_query_port(ibdev, port_num, &attr); 5095 if (err) 5096 return err; 5097 5098 immutable->pkey_tbl_len = attr.pkey_tbl_len; 5099 immutable->gid_tbl_len = attr.gid_tbl_len; 5100 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 5101 5102 return 0; 5103 } 5104 5105 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 5106 { 5107 struct mlx5_ib_dev *dev = 5108 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 5109 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 5110 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 5111 fw_rev_sub(dev->mdev)); 5112 } 5113 5114 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 5115 { 5116 struct mlx5_core_dev *mdev = dev->mdev; 5117 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 5118 MLX5_FLOW_NAMESPACE_LAG); 5119 struct mlx5_flow_table *ft; 5120 int err; 5121 5122 if (!ns || !mlx5_lag_is_roce(mdev)) 5123 return 0; 5124 5125 err = mlx5_cmd_create_vport_lag(mdev); 5126 if (err) 5127 return err; 5128 5129 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 5130 if (IS_ERR(ft)) { 5131 err = PTR_ERR(ft); 5132 goto err_destroy_vport_lag; 5133 } 5134 5135 dev->flow_db->lag_demux_ft = ft; 5136 dev->lag_active = true; 5137 return 0; 5138 5139 err_destroy_vport_lag: 5140 mlx5_cmd_destroy_vport_lag(mdev); 5141 return err; 5142 } 5143 5144 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 5145 { 5146 struct mlx5_core_dev *mdev = dev->mdev; 5147 5148 if (dev->lag_active) { 5149 dev->lag_active = false; 5150 5151 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 5152 dev->flow_db->lag_demux_ft = NULL; 5153 5154 mlx5_cmd_destroy_vport_lag(mdev); 5155 } 5156 } 5157 5158 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5159 { 5160 int err; 5161 5162 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 5163 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 5164 if (err) { 5165 dev->port[port_num].roce.nb.notifier_call = NULL; 5166 return err; 5167 } 5168 5169 return 0; 5170 } 5171 5172 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5173 { 5174 if (dev->port[port_num].roce.nb.notifier_call) { 5175 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 5176 dev->port[port_num].roce.nb.notifier_call = NULL; 5177 } 5178 } 5179 5180 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 5181 { 5182 int err; 5183 5184 if (MLX5_CAP_GEN(dev->mdev, roce)) { 5185 err = mlx5_nic_vport_enable_roce(dev->mdev); 5186 if (err) 5187 return err; 5188 } 5189 5190 err = mlx5_eth_lag_init(dev); 5191 if (err) 5192 goto err_disable_roce; 5193 5194 return 0; 5195 5196 err_disable_roce: 5197 if (MLX5_CAP_GEN(dev->mdev, roce)) 5198 mlx5_nic_vport_disable_roce(dev->mdev); 5199 5200 return err; 5201 } 5202 5203 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 5204 { 5205 mlx5_eth_lag_cleanup(dev); 5206 if (MLX5_CAP_GEN(dev->mdev, roce)) 5207 mlx5_nic_vport_disable_roce(dev->mdev); 5208 } 5209 5210 struct mlx5_ib_counter { 5211 const char *name; 5212 size_t offset; 5213 }; 5214 5215 #define INIT_Q_COUNTER(_name) \ 5216 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 5217 5218 static const struct mlx5_ib_counter basic_q_cnts[] = { 5219 INIT_Q_COUNTER(rx_write_requests), 5220 INIT_Q_COUNTER(rx_read_requests), 5221 INIT_Q_COUNTER(rx_atomic_requests), 5222 INIT_Q_COUNTER(out_of_buffer), 5223 }; 5224 5225 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 5226 INIT_Q_COUNTER(out_of_sequence), 5227 }; 5228 5229 static const struct mlx5_ib_counter retrans_q_cnts[] = { 5230 INIT_Q_COUNTER(duplicate_request), 5231 INIT_Q_COUNTER(rnr_nak_retry_err), 5232 INIT_Q_COUNTER(packet_seq_err), 5233 INIT_Q_COUNTER(implied_nak_seq_err), 5234 INIT_Q_COUNTER(local_ack_timeout_err), 5235 }; 5236 5237 #define INIT_CONG_COUNTER(_name) \ 5238 { .name = #_name, .offset = \ 5239 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 5240 5241 static const struct mlx5_ib_counter cong_cnts[] = { 5242 INIT_CONG_COUNTER(rp_cnp_ignored), 5243 INIT_CONG_COUNTER(rp_cnp_handled), 5244 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 5245 INIT_CONG_COUNTER(np_cnp_sent), 5246 }; 5247 5248 static const struct mlx5_ib_counter extended_err_cnts[] = { 5249 INIT_Q_COUNTER(resp_local_length_error), 5250 INIT_Q_COUNTER(resp_cqe_error), 5251 INIT_Q_COUNTER(req_cqe_error), 5252 INIT_Q_COUNTER(req_remote_invalid_request), 5253 INIT_Q_COUNTER(req_remote_access_errors), 5254 INIT_Q_COUNTER(resp_remote_access_errors), 5255 INIT_Q_COUNTER(resp_cqe_flush_error), 5256 INIT_Q_COUNTER(req_cqe_flush_error), 5257 }; 5258 5259 #define INIT_EXT_PPCNT_COUNTER(_name) \ 5260 { .name = #_name, .offset = \ 5261 MLX5_BYTE_OFF(ppcnt_reg, \ 5262 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 5263 5264 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 5265 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 5266 }; 5267 5268 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 5269 { 5270 int i; 5271 5272 for (i = 0; i < dev->num_ports; i++) { 5273 if (dev->port[i].cnts.set_id_valid) 5274 mlx5_core_dealloc_q_counter(dev->mdev, 5275 dev->port[i].cnts.set_id); 5276 kfree(dev->port[i].cnts.names); 5277 kfree(dev->port[i].cnts.offsets); 5278 } 5279 } 5280 5281 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 5282 struct mlx5_ib_counters *cnts) 5283 { 5284 u32 num_counters; 5285 5286 num_counters = ARRAY_SIZE(basic_q_cnts); 5287 5288 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 5289 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 5290 5291 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 5292 num_counters += ARRAY_SIZE(retrans_q_cnts); 5293 5294 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 5295 num_counters += ARRAY_SIZE(extended_err_cnts); 5296 5297 cnts->num_q_counters = num_counters; 5298 5299 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5300 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 5301 num_counters += ARRAY_SIZE(cong_cnts); 5302 } 5303 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5304 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 5305 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 5306 } 5307 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 5308 if (!cnts->names) 5309 return -ENOMEM; 5310 5311 cnts->offsets = kcalloc(num_counters, 5312 sizeof(cnts->offsets), GFP_KERNEL); 5313 if (!cnts->offsets) 5314 goto err_names; 5315 5316 return 0; 5317 5318 err_names: 5319 kfree(cnts->names); 5320 cnts->names = NULL; 5321 return -ENOMEM; 5322 } 5323 5324 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 5325 const char **names, 5326 size_t *offsets) 5327 { 5328 int i; 5329 int j = 0; 5330 5331 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5332 names[j] = basic_q_cnts[i].name; 5333 offsets[j] = basic_q_cnts[i].offset; 5334 } 5335 5336 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5337 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5338 names[j] = out_of_seq_q_cnts[i].name; 5339 offsets[j] = out_of_seq_q_cnts[i].offset; 5340 } 5341 } 5342 5343 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5344 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5345 names[j] = retrans_q_cnts[i].name; 5346 offsets[j] = retrans_q_cnts[i].offset; 5347 } 5348 } 5349 5350 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5351 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5352 names[j] = extended_err_cnts[i].name; 5353 offsets[j] = extended_err_cnts[i].offset; 5354 } 5355 } 5356 5357 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5358 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5359 names[j] = cong_cnts[i].name; 5360 offsets[j] = cong_cnts[i].offset; 5361 } 5362 } 5363 5364 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5365 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5366 names[j] = ext_ppcnt_cnts[i].name; 5367 offsets[j] = ext_ppcnt_cnts[i].offset; 5368 } 5369 } 5370 } 5371 5372 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5373 { 5374 int err = 0; 5375 int i; 5376 bool is_shared; 5377 5378 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0; 5379 5380 for (i = 0; i < dev->num_ports; i++) { 5381 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5382 if (err) 5383 goto err_alloc; 5384 5385 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5386 dev->port[i].cnts.offsets); 5387 5388 err = mlx5_cmd_alloc_q_counter(dev->mdev, 5389 &dev->port[i].cnts.set_id, 5390 is_shared ? 5391 MLX5_SHARED_RESOURCE_UID : 0); 5392 if (err) { 5393 mlx5_ib_warn(dev, 5394 "couldn't allocate queue counter for port %d, err %d\n", 5395 i + 1, err); 5396 goto err_alloc; 5397 } 5398 dev->port[i].cnts.set_id_valid = true; 5399 } 5400 5401 return 0; 5402 5403 err_alloc: 5404 mlx5_ib_dealloc_counters(dev); 5405 return err; 5406 } 5407 5408 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5409 u8 port_num) 5410 { 5411 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5412 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5413 5414 /* We support only per port stats */ 5415 if (port_num == 0) 5416 return NULL; 5417 5418 return rdma_alloc_hw_stats_struct(port->cnts.names, 5419 port->cnts.num_q_counters + 5420 port->cnts.num_cong_counters + 5421 port->cnts.num_ext_ppcnt_counters, 5422 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5423 } 5424 5425 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5426 struct mlx5_ib_port *port, 5427 struct rdma_hw_stats *stats) 5428 { 5429 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5430 void *out; 5431 __be32 val; 5432 int ret, i; 5433 5434 out = kvzalloc(outlen, GFP_KERNEL); 5435 if (!out) 5436 return -ENOMEM; 5437 5438 ret = mlx5_core_query_q_counter(mdev, 5439 port->cnts.set_id, 0, 5440 out, outlen); 5441 if (ret) 5442 goto free; 5443 5444 for (i = 0; i < port->cnts.num_q_counters; i++) { 5445 val = *(__be32 *)(out + port->cnts.offsets[i]); 5446 stats->value[i] = (u64)be32_to_cpu(val); 5447 } 5448 5449 free: 5450 kvfree(out); 5451 return ret; 5452 } 5453 5454 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5455 struct mlx5_ib_port *port, 5456 struct rdma_hw_stats *stats) 5457 { 5458 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5459 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5460 int ret, i; 5461 void *out; 5462 5463 out = kvzalloc(sz, GFP_KERNEL); 5464 if (!out) 5465 return -ENOMEM; 5466 5467 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5468 if (ret) 5469 goto free; 5470 5471 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5472 stats->value[i + offset] = 5473 be64_to_cpup((__be64 *)(out + 5474 port->cnts.offsets[i + offset])); 5475 } 5476 5477 free: 5478 kvfree(out); 5479 return ret; 5480 } 5481 5482 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5483 struct rdma_hw_stats *stats, 5484 u8 port_num, int index) 5485 { 5486 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5487 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5488 struct mlx5_core_dev *mdev; 5489 int ret, num_counters; 5490 u8 mdev_port_num; 5491 5492 if (!stats) 5493 return -EINVAL; 5494 5495 num_counters = port->cnts.num_q_counters + 5496 port->cnts.num_cong_counters + 5497 port->cnts.num_ext_ppcnt_counters; 5498 5499 /* q_counters are per IB device, query the master mdev */ 5500 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5501 if (ret) 5502 return ret; 5503 5504 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5505 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5506 if (ret) 5507 return ret; 5508 } 5509 5510 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5511 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5512 &mdev_port_num); 5513 if (!mdev) { 5514 /* If port is not affiliated yet, its in down state 5515 * which doesn't have any counters yet, so it would be 5516 * zero. So no need to read from the HCA. 5517 */ 5518 goto done; 5519 } 5520 ret = mlx5_lag_query_cong_counters(dev->mdev, 5521 stats->value + 5522 port->cnts.num_q_counters, 5523 port->cnts.num_cong_counters, 5524 port->cnts.offsets + 5525 port->cnts.num_q_counters); 5526 5527 mlx5_ib_put_native_port_mdev(dev, port_num); 5528 if (ret) 5529 return ret; 5530 } 5531 5532 done: 5533 return num_counters; 5534 } 5535 5536 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5537 enum rdma_netdev_t type, 5538 struct rdma_netdev_alloc_params *params) 5539 { 5540 if (type != RDMA_NETDEV_IPOIB) 5541 return -EOPNOTSUPP; 5542 5543 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5544 } 5545 5546 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5547 { 5548 if (!dev->delay_drop.dbg) 5549 return; 5550 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5551 kfree(dev->delay_drop.dbg); 5552 dev->delay_drop.dbg = NULL; 5553 } 5554 5555 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5556 { 5557 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5558 return; 5559 5560 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5561 delay_drop_debugfs_cleanup(dev); 5562 } 5563 5564 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5565 size_t count, loff_t *pos) 5566 { 5567 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5568 char lbuf[20]; 5569 int len; 5570 5571 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5572 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5573 } 5574 5575 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5576 size_t count, loff_t *pos) 5577 { 5578 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5579 u32 timeout; 5580 u32 var; 5581 5582 if (kstrtouint_from_user(buf, count, 0, &var)) 5583 return -EFAULT; 5584 5585 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5586 1000); 5587 if (timeout != var) 5588 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5589 timeout); 5590 5591 delay_drop->timeout = timeout; 5592 5593 return count; 5594 } 5595 5596 static const struct file_operations fops_delay_drop_timeout = { 5597 .owner = THIS_MODULE, 5598 .open = simple_open, 5599 .write = delay_drop_timeout_write, 5600 .read = delay_drop_timeout_read, 5601 }; 5602 5603 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5604 { 5605 struct mlx5_ib_dbg_delay_drop *dbg; 5606 5607 if (!mlx5_debugfs_root) 5608 return 0; 5609 5610 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5611 if (!dbg) 5612 return -ENOMEM; 5613 5614 dev->delay_drop.dbg = dbg; 5615 5616 dbg->dir_debugfs = 5617 debugfs_create_dir("delay_drop", 5618 dev->mdev->priv.dbg_root); 5619 if (!dbg->dir_debugfs) 5620 goto out_debugfs; 5621 5622 dbg->events_cnt_debugfs = 5623 debugfs_create_atomic_t("num_timeout_events", 0400, 5624 dbg->dir_debugfs, 5625 &dev->delay_drop.events_cnt); 5626 if (!dbg->events_cnt_debugfs) 5627 goto out_debugfs; 5628 5629 dbg->rqs_cnt_debugfs = 5630 debugfs_create_atomic_t("num_rqs", 0400, 5631 dbg->dir_debugfs, 5632 &dev->delay_drop.rqs_cnt); 5633 if (!dbg->rqs_cnt_debugfs) 5634 goto out_debugfs; 5635 5636 dbg->timeout_debugfs = 5637 debugfs_create_file("timeout", 0600, 5638 dbg->dir_debugfs, 5639 &dev->delay_drop, 5640 &fops_delay_drop_timeout); 5641 if (!dbg->timeout_debugfs) 5642 goto out_debugfs; 5643 5644 return 0; 5645 5646 out_debugfs: 5647 delay_drop_debugfs_cleanup(dev); 5648 return -ENOMEM; 5649 } 5650 5651 static void init_delay_drop(struct mlx5_ib_dev *dev) 5652 { 5653 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5654 return; 5655 5656 mutex_init(&dev->delay_drop.lock); 5657 dev->delay_drop.dev = dev; 5658 dev->delay_drop.activate = false; 5659 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5660 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5661 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5662 atomic_set(&dev->delay_drop.events_cnt, 0); 5663 5664 if (delay_drop_debugfs_init(dev)) 5665 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5666 } 5667 5668 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5669 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5670 struct mlx5_ib_multiport_info *mpi) 5671 { 5672 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5673 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5674 int comps; 5675 int err; 5676 int i; 5677 5678 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5679 5680 spin_lock(&port->mp.mpi_lock); 5681 if (!mpi->ibdev) { 5682 spin_unlock(&port->mp.mpi_lock); 5683 return; 5684 } 5685 5686 if (mpi->mdev_events.notifier_call) 5687 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 5688 mpi->mdev_events.notifier_call = NULL; 5689 5690 mpi->ibdev = NULL; 5691 5692 spin_unlock(&port->mp.mpi_lock); 5693 mlx5_remove_netdev_notifier(ibdev, port_num); 5694 spin_lock(&port->mp.mpi_lock); 5695 5696 comps = mpi->mdev_refcnt; 5697 if (comps) { 5698 mpi->unaffiliate = true; 5699 init_completion(&mpi->unref_comp); 5700 spin_unlock(&port->mp.mpi_lock); 5701 5702 for (i = 0; i < comps; i++) 5703 wait_for_completion(&mpi->unref_comp); 5704 5705 spin_lock(&port->mp.mpi_lock); 5706 mpi->unaffiliate = false; 5707 } 5708 5709 port->mp.mpi = NULL; 5710 5711 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5712 5713 spin_unlock(&port->mp.mpi_lock); 5714 5715 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5716 5717 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5718 /* Log an error, still needed to cleanup the pointers and add 5719 * it back to the list. 5720 */ 5721 if (err) 5722 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5723 port_num + 1); 5724 5725 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 5726 } 5727 5728 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5729 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5730 struct mlx5_ib_multiport_info *mpi) 5731 { 5732 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5733 int err; 5734 5735 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5736 if (ibdev->port[port_num].mp.mpi) { 5737 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5738 port_num + 1); 5739 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5740 return false; 5741 } 5742 5743 ibdev->port[port_num].mp.mpi = mpi; 5744 mpi->ibdev = ibdev; 5745 mpi->mdev_events.notifier_call = NULL; 5746 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5747 5748 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5749 if (err) 5750 goto unbind; 5751 5752 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5753 if (err) 5754 goto unbind; 5755 5756 err = mlx5_add_netdev_notifier(ibdev, port_num); 5757 if (err) { 5758 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5759 port_num + 1); 5760 goto unbind; 5761 } 5762 5763 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 5764 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 5765 5766 mlx5_ib_init_cong_debugfs(ibdev, port_num); 5767 5768 return true; 5769 5770 unbind: 5771 mlx5_ib_unbind_slave_port(ibdev, mpi); 5772 return false; 5773 } 5774 5775 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5776 { 5777 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5778 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5779 port_num + 1); 5780 struct mlx5_ib_multiport_info *mpi; 5781 int err; 5782 int i; 5783 5784 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5785 return 0; 5786 5787 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5788 &dev->sys_image_guid); 5789 if (err) 5790 return err; 5791 5792 err = mlx5_nic_vport_enable_roce(dev->mdev); 5793 if (err) 5794 return err; 5795 5796 mutex_lock(&mlx5_ib_multiport_mutex); 5797 for (i = 0; i < dev->num_ports; i++) { 5798 bool bound = false; 5799 5800 /* build a stub multiport info struct for the native port. */ 5801 if (i == port_num) { 5802 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5803 if (!mpi) { 5804 mutex_unlock(&mlx5_ib_multiport_mutex); 5805 mlx5_nic_vport_disable_roce(dev->mdev); 5806 return -ENOMEM; 5807 } 5808 5809 mpi->is_master = true; 5810 mpi->mdev = dev->mdev; 5811 mpi->sys_image_guid = dev->sys_image_guid; 5812 dev->port[i].mp.mpi = mpi; 5813 mpi->ibdev = dev; 5814 mpi = NULL; 5815 continue; 5816 } 5817 5818 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5819 list) { 5820 if (dev->sys_image_guid == mpi->sys_image_guid && 5821 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5822 bound = mlx5_ib_bind_slave_port(dev, mpi); 5823 } 5824 5825 if (bound) { 5826 dev_dbg(mpi->mdev->device, 5827 "removing port from unaffiliated list.\n"); 5828 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5829 list_del(&mpi->list); 5830 break; 5831 } 5832 } 5833 if (!bound) { 5834 get_port_caps(dev, i + 1); 5835 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5836 i + 1); 5837 } 5838 } 5839 5840 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5841 mutex_unlock(&mlx5_ib_multiport_mutex); 5842 return err; 5843 } 5844 5845 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5846 { 5847 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5848 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5849 port_num + 1); 5850 int i; 5851 5852 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5853 return; 5854 5855 mutex_lock(&mlx5_ib_multiport_mutex); 5856 for (i = 0; i < dev->num_ports; i++) { 5857 if (dev->port[i].mp.mpi) { 5858 /* Destroy the native port stub */ 5859 if (i == port_num) { 5860 kfree(dev->port[i].mp.mpi); 5861 dev->port[i].mp.mpi = NULL; 5862 } else { 5863 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5864 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5865 } 5866 } 5867 } 5868 5869 mlx5_ib_dbg(dev, "removing from devlist\n"); 5870 list_del(&dev->ib_dev_list); 5871 mutex_unlock(&mlx5_ib_multiport_mutex); 5872 5873 mlx5_nic_vport_disable_roce(dev->mdev); 5874 } 5875 5876 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5877 mlx5_ib_dm, 5878 UVERBS_OBJECT_DM, 5879 UVERBS_METHOD_DM_ALLOC, 5880 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5881 UVERBS_ATTR_TYPE(u64), 5882 UA_MANDATORY), 5883 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5884 UVERBS_ATTR_TYPE(u16), 5885 UA_OPTIONAL), 5886 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 5887 enum mlx5_ib_uapi_dm_type, 5888 UA_OPTIONAL)); 5889 5890 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5891 mlx5_ib_flow_action, 5892 UVERBS_OBJECT_FLOW_ACTION, 5893 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5894 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5895 enum mlx5_ib_uapi_flow_action_flags)); 5896 5897 static const struct uapi_definition mlx5_ib_defs[] = { 5898 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 5899 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 5900 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 5901 #endif 5902 5903 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 5904 &mlx5_ib_flow_action), 5905 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 5906 {} 5907 }; 5908 5909 static int mlx5_ib_read_counters(struct ib_counters *counters, 5910 struct ib_counters_read_attr *read_attr, 5911 struct uverbs_attr_bundle *attrs) 5912 { 5913 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5914 struct mlx5_read_counters_attr mread_attr = {}; 5915 struct mlx5_ib_flow_counters_desc *desc; 5916 int ret, i; 5917 5918 mutex_lock(&mcounters->mcntrs_mutex); 5919 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5920 ret = -EINVAL; 5921 goto err_bound; 5922 } 5923 5924 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5925 GFP_KERNEL); 5926 if (!mread_attr.out) { 5927 ret = -ENOMEM; 5928 goto err_bound; 5929 } 5930 5931 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5932 mread_attr.flags = read_attr->flags; 5933 ret = mcounters->read_counters(counters->device, &mread_attr); 5934 if (ret) 5935 goto err_read; 5936 5937 /* do the pass over the counters data array to assign according to the 5938 * descriptions and indexing pairs 5939 */ 5940 desc = mcounters->counters_data; 5941 for (i = 0; i < mcounters->ncounters; i++) 5942 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5943 5944 err_read: 5945 kfree(mread_attr.out); 5946 err_bound: 5947 mutex_unlock(&mcounters->mcntrs_mutex); 5948 return ret; 5949 } 5950 5951 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5952 { 5953 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5954 5955 counters_clear_description(counters); 5956 if (mcounters->hw_cntrs_hndl) 5957 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5958 mcounters->hw_cntrs_hndl); 5959 5960 kfree(mcounters); 5961 5962 return 0; 5963 } 5964 5965 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5966 struct uverbs_attr_bundle *attrs) 5967 { 5968 struct mlx5_ib_mcounters *mcounters; 5969 5970 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5971 if (!mcounters) 5972 return ERR_PTR(-ENOMEM); 5973 5974 mutex_init(&mcounters->mcntrs_mutex); 5975 5976 return &mcounters->ibcntrs; 5977 } 5978 5979 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5980 { 5981 struct mlx5_core_dev *mdev = dev->mdev; 5982 5983 mlx5_ib_cleanup_multiport_master(dev); 5984 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 5985 srcu_barrier(&dev->mr_srcu); 5986 cleanup_srcu_struct(&dev->mr_srcu); 5987 } 5988 5989 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 5990 5991 WARN_ON(dev->dm.steering_sw_icm_alloc_blocks && 5992 !bitmap_empty( 5993 dev->dm.steering_sw_icm_alloc_blocks, 5994 BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) - 5995 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev)))); 5996 5997 kfree(dev->dm.steering_sw_icm_alloc_blocks); 5998 5999 WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks && 6000 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks, 6001 BIT(MLX5_CAP_DEV_MEM( 6002 mdev, log_header_modify_sw_icm_size) - 6003 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev)))); 6004 6005 kfree(dev->dm.header_modify_sw_icm_alloc_blocks); 6006 } 6007 6008 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 6009 { 6010 struct mlx5_core_dev *mdev = dev->mdev; 6011 u64 header_modify_icm_blocks = 0; 6012 u64 steering_icm_blocks = 0; 6013 int err; 6014 int i; 6015 6016 for (i = 0; i < dev->num_ports; i++) { 6017 spin_lock_init(&dev->port[i].mp.mpi_lock); 6018 rwlock_init(&dev->port[i].roce.netdev_lock); 6019 dev->port[i].roce.dev = dev; 6020 dev->port[i].roce.native_port_num = i + 1; 6021 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 6022 } 6023 6024 err = mlx5_ib_init_multiport_master(dev); 6025 if (err) 6026 return err; 6027 6028 err = set_has_smi_cap(dev); 6029 if (err) 6030 return err; 6031 6032 if (!mlx5_core_mp_enabled(mdev)) { 6033 for (i = 1; i <= dev->num_ports; i++) { 6034 err = get_port_caps(dev, i); 6035 if (err) 6036 break; 6037 } 6038 } else { 6039 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 6040 } 6041 if (err) 6042 goto err_mp; 6043 6044 if (mlx5_use_mad_ifc(dev)) 6045 get_ext_port_caps(dev); 6046 6047 dev->ib_dev.owner = THIS_MODULE; 6048 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 6049 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 6050 dev->ib_dev.phys_port_cnt = dev->num_ports; 6051 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 6052 dev->ib_dev.dev.parent = mdev->device; 6053 6054 mutex_init(&dev->cap_mask_mutex); 6055 INIT_LIST_HEAD(&dev->qp_list); 6056 spin_lock_init(&dev->reset_flow_resource_lock); 6057 6058 if (MLX5_CAP_GEN_64(mdev, general_obj_types) & 6059 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) { 6060 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) { 6061 steering_icm_blocks = 6062 BIT(MLX5_CAP_DEV_MEM(mdev, 6063 log_steering_sw_icm_size) - 6064 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev)); 6065 6066 dev->dm.steering_sw_icm_alloc_blocks = 6067 kcalloc(BITS_TO_LONGS(steering_icm_blocks), 6068 sizeof(unsigned long), GFP_KERNEL); 6069 if (!dev->dm.steering_sw_icm_alloc_blocks) 6070 goto err_mp; 6071 } 6072 6073 if (MLX5_CAP64_DEV_MEM(mdev, 6074 header_modify_sw_icm_start_address)) { 6075 header_modify_icm_blocks = BIT( 6076 MLX5_CAP_DEV_MEM( 6077 mdev, log_header_modify_sw_icm_size) - 6078 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev)); 6079 6080 dev->dm.header_modify_sw_icm_alloc_blocks = 6081 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks), 6082 sizeof(unsigned long), GFP_KERNEL); 6083 if (!dev->dm.header_modify_sw_icm_alloc_blocks) 6084 goto err_dm; 6085 } 6086 } 6087 6088 spin_lock_init(&dev->dm.lock); 6089 dev->dm.dev = mdev; 6090 6091 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 6092 err = init_srcu_struct(&dev->mr_srcu); 6093 if (err) 6094 goto err_dm; 6095 } 6096 6097 return 0; 6098 6099 err_dm: 6100 kfree(dev->dm.steering_sw_icm_alloc_blocks); 6101 kfree(dev->dm.header_modify_sw_icm_alloc_blocks); 6102 6103 err_mp: 6104 mlx5_ib_cleanup_multiport_master(dev); 6105 6106 return -ENOMEM; 6107 } 6108 6109 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 6110 { 6111 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 6112 6113 if (!dev->flow_db) 6114 return -ENOMEM; 6115 6116 mutex_init(&dev->flow_db->lock); 6117 6118 return 0; 6119 } 6120 6121 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 6122 { 6123 kfree(dev->flow_db); 6124 } 6125 6126 static const struct ib_device_ops mlx5_ib_dev_ops = { 6127 .add_gid = mlx5_ib_add_gid, 6128 .alloc_mr = mlx5_ib_alloc_mr, 6129 .alloc_pd = mlx5_ib_alloc_pd, 6130 .alloc_ucontext = mlx5_ib_alloc_ucontext, 6131 .attach_mcast = mlx5_ib_mcg_attach, 6132 .check_mr_status = mlx5_ib_check_mr_status, 6133 .create_ah = mlx5_ib_create_ah, 6134 .create_counters = mlx5_ib_create_counters, 6135 .create_cq = mlx5_ib_create_cq, 6136 .create_flow = mlx5_ib_create_flow, 6137 .create_qp = mlx5_ib_create_qp, 6138 .create_srq = mlx5_ib_create_srq, 6139 .dealloc_pd = mlx5_ib_dealloc_pd, 6140 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 6141 .del_gid = mlx5_ib_del_gid, 6142 .dereg_mr = mlx5_ib_dereg_mr, 6143 .destroy_ah = mlx5_ib_destroy_ah, 6144 .destroy_counters = mlx5_ib_destroy_counters, 6145 .destroy_cq = mlx5_ib_destroy_cq, 6146 .destroy_flow = mlx5_ib_destroy_flow, 6147 .destroy_flow_action = mlx5_ib_destroy_flow_action, 6148 .destroy_qp = mlx5_ib_destroy_qp, 6149 .destroy_srq = mlx5_ib_destroy_srq, 6150 .detach_mcast = mlx5_ib_mcg_detach, 6151 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 6152 .drain_rq = mlx5_ib_drain_rq, 6153 .drain_sq = mlx5_ib_drain_sq, 6154 .get_dev_fw_str = get_dev_fw_str, 6155 .get_dma_mr = mlx5_ib_get_dma_mr, 6156 .get_link_layer = mlx5_ib_port_link_layer, 6157 .map_mr_sg = mlx5_ib_map_mr_sg, 6158 .mmap = mlx5_ib_mmap, 6159 .modify_cq = mlx5_ib_modify_cq, 6160 .modify_device = mlx5_ib_modify_device, 6161 .modify_port = mlx5_ib_modify_port, 6162 .modify_qp = mlx5_ib_modify_qp, 6163 .modify_srq = mlx5_ib_modify_srq, 6164 .poll_cq = mlx5_ib_poll_cq, 6165 .post_recv = mlx5_ib_post_recv, 6166 .post_send = mlx5_ib_post_send, 6167 .post_srq_recv = mlx5_ib_post_srq_recv, 6168 .process_mad = mlx5_ib_process_mad, 6169 .query_ah = mlx5_ib_query_ah, 6170 .query_device = mlx5_ib_query_device, 6171 .query_gid = mlx5_ib_query_gid, 6172 .query_pkey = mlx5_ib_query_pkey, 6173 .query_qp = mlx5_ib_query_qp, 6174 .query_srq = mlx5_ib_query_srq, 6175 .read_counters = mlx5_ib_read_counters, 6176 .reg_user_mr = mlx5_ib_reg_user_mr, 6177 .req_notify_cq = mlx5_ib_arm_cq, 6178 .rereg_user_mr = mlx5_ib_rereg_user_mr, 6179 .resize_cq = mlx5_ib_resize_cq, 6180 6181 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 6182 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 6183 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 6184 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 6185 }; 6186 6187 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = { 6188 .create_flow_action_esp = mlx5_ib_create_flow_action_esp, 6189 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp, 6190 }; 6191 6192 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 6193 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 6194 }; 6195 6196 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 6197 .get_vf_config = mlx5_ib_get_vf_config, 6198 .get_vf_stats = mlx5_ib_get_vf_stats, 6199 .set_vf_guid = mlx5_ib_set_vf_guid, 6200 .set_vf_link_state = mlx5_ib_set_vf_link_state, 6201 }; 6202 6203 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 6204 .alloc_mw = mlx5_ib_alloc_mw, 6205 .dealloc_mw = mlx5_ib_dealloc_mw, 6206 }; 6207 6208 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 6209 .alloc_xrcd = mlx5_ib_alloc_xrcd, 6210 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 6211 }; 6212 6213 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 6214 .alloc_dm = mlx5_ib_alloc_dm, 6215 .dealloc_dm = mlx5_ib_dealloc_dm, 6216 .reg_dm_mr = mlx5_ib_reg_dm_mr, 6217 }; 6218 6219 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 6220 { 6221 struct mlx5_core_dev *mdev = dev->mdev; 6222 int err; 6223 6224 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 6225 dev->ib_dev.uverbs_cmd_mask = 6226 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 6227 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 6228 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 6229 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 6230 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 6231 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 6232 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 6233 (1ull << IB_USER_VERBS_CMD_REG_MR) | 6234 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 6235 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 6236 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 6237 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 6238 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 6239 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 6240 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 6241 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 6242 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 6243 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 6244 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 6245 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 6246 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 6247 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 6248 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 6249 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 6250 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 6251 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 6252 dev->ib_dev.uverbs_ex_cmd_mask = 6253 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 6254 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 6255 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 6256 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 6257 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 6258 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 6259 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 6260 6261 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 6262 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 6263 ib_set_device_ops(&dev->ib_dev, 6264 &mlx5_ib_dev_ipoib_enhanced_ops); 6265 6266 if (mlx5_core_is_pf(mdev)) 6267 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 6268 6269 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 6270 6271 if (MLX5_CAP_GEN(mdev, imaicl)) { 6272 dev->ib_dev.uverbs_cmd_mask |= 6273 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 6274 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 6275 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 6276 } 6277 6278 if (MLX5_CAP_GEN(mdev, xrc)) { 6279 dev->ib_dev.uverbs_cmd_mask |= 6280 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 6281 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 6282 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 6283 } 6284 6285 if (MLX5_CAP_DEV_MEM(mdev, memic) || 6286 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 6287 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 6288 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 6289 6290 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 6291 MLX5_ACCEL_IPSEC_CAP_DEVICE) 6292 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops); 6293 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 6294 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 6295 6296 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 6297 dev->ib_dev.driver_def = mlx5_ib_defs; 6298 6299 err = init_node_data(dev); 6300 if (err) 6301 return err; 6302 6303 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 6304 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 6305 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 6306 mutex_init(&dev->lb.mutex); 6307 6308 return 0; 6309 } 6310 6311 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 6312 .get_port_immutable = mlx5_port_immutable, 6313 .query_port = mlx5_ib_query_port, 6314 }; 6315 6316 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 6317 { 6318 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 6319 return 0; 6320 } 6321 6322 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 6323 .get_port_immutable = mlx5_port_rep_immutable, 6324 .query_port = mlx5_ib_rep_query_port, 6325 }; 6326 6327 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 6328 { 6329 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 6330 return 0; 6331 } 6332 6333 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 6334 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 6335 .create_wq = mlx5_ib_create_wq, 6336 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 6337 .destroy_wq = mlx5_ib_destroy_wq, 6338 .get_netdev = mlx5_ib_get_netdev, 6339 .modify_wq = mlx5_ib_modify_wq, 6340 }; 6341 6342 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 6343 { 6344 u8 port_num; 6345 6346 dev->ib_dev.uverbs_ex_cmd_mask |= 6347 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 6348 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 6349 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 6350 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 6351 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 6352 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 6353 6354 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6355 6356 /* Register only for native ports */ 6357 return mlx5_add_netdev_notifier(dev, port_num); 6358 } 6359 6360 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 6361 { 6362 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6363 6364 mlx5_remove_netdev_notifier(dev, port_num); 6365 } 6366 6367 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 6368 { 6369 struct mlx5_core_dev *mdev = dev->mdev; 6370 enum rdma_link_layer ll; 6371 int port_type_cap; 6372 int err = 0; 6373 6374 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6375 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6376 6377 if (ll == IB_LINK_LAYER_ETHERNET) 6378 err = mlx5_ib_stage_common_roce_init(dev); 6379 6380 return err; 6381 } 6382 6383 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 6384 { 6385 mlx5_ib_stage_common_roce_cleanup(dev); 6386 } 6387 6388 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 6389 { 6390 struct mlx5_core_dev *mdev = dev->mdev; 6391 enum rdma_link_layer ll; 6392 int port_type_cap; 6393 int err; 6394 6395 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6396 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6397 6398 if (ll == IB_LINK_LAYER_ETHERNET) { 6399 err = mlx5_ib_stage_common_roce_init(dev); 6400 if (err) 6401 return err; 6402 6403 err = mlx5_enable_eth(dev); 6404 if (err) 6405 goto cleanup; 6406 } 6407 6408 return 0; 6409 cleanup: 6410 mlx5_ib_stage_common_roce_cleanup(dev); 6411 6412 return err; 6413 } 6414 6415 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6416 { 6417 struct mlx5_core_dev *mdev = dev->mdev; 6418 enum rdma_link_layer ll; 6419 int port_type_cap; 6420 6421 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6422 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6423 6424 if (ll == IB_LINK_LAYER_ETHERNET) { 6425 mlx5_disable_eth(dev); 6426 mlx5_ib_stage_common_roce_cleanup(dev); 6427 } 6428 } 6429 6430 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6431 { 6432 return create_dev_resources(&dev->devr); 6433 } 6434 6435 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6436 { 6437 destroy_dev_resources(&dev->devr); 6438 } 6439 6440 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6441 { 6442 mlx5_ib_internal_fill_odp_caps(dev); 6443 6444 return mlx5_ib_odp_init_one(dev); 6445 } 6446 6447 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 6448 { 6449 mlx5_ib_odp_cleanup_one(dev); 6450 } 6451 6452 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = { 6453 .alloc_hw_stats = mlx5_ib_alloc_hw_stats, 6454 .get_hw_stats = mlx5_ib_get_hw_stats, 6455 }; 6456 6457 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6458 { 6459 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6460 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops); 6461 6462 return mlx5_ib_alloc_counters(dev); 6463 } 6464 6465 return 0; 6466 } 6467 6468 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6469 { 6470 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6471 mlx5_ib_dealloc_counters(dev); 6472 } 6473 6474 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6475 { 6476 mlx5_ib_init_cong_debugfs(dev, 6477 mlx5_core_native_port_num(dev->mdev) - 1); 6478 return 0; 6479 } 6480 6481 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6482 { 6483 mlx5_ib_cleanup_cong_debugfs(dev, 6484 mlx5_core_native_port_num(dev->mdev) - 1); 6485 } 6486 6487 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6488 { 6489 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6490 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6491 } 6492 6493 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6494 { 6495 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6496 } 6497 6498 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6499 { 6500 int err; 6501 6502 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6503 if (err) 6504 return err; 6505 6506 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6507 if (err) 6508 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6509 6510 return err; 6511 } 6512 6513 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6514 { 6515 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6516 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6517 } 6518 6519 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6520 { 6521 const char *name; 6522 6523 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 6524 if (!mlx5_lag_is_roce(dev->mdev)) 6525 name = "mlx5_%d"; 6526 else 6527 name = "mlx5_bond_%d"; 6528 return ib_register_device(&dev->ib_dev, name); 6529 } 6530 6531 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6532 { 6533 destroy_umrc_res(dev); 6534 } 6535 6536 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6537 { 6538 ib_unregister_device(&dev->ib_dev); 6539 } 6540 6541 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6542 { 6543 return create_umr_res(dev); 6544 } 6545 6546 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6547 { 6548 init_delay_drop(dev); 6549 6550 return 0; 6551 } 6552 6553 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6554 { 6555 cancel_delay_drop(dev); 6556 } 6557 6558 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 6559 { 6560 dev->mdev_events.notifier_call = mlx5_ib_event; 6561 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 6562 return 0; 6563 } 6564 6565 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 6566 { 6567 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 6568 } 6569 6570 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev) 6571 { 6572 int uid; 6573 6574 uid = mlx5_ib_devx_create(dev, false); 6575 if (uid > 0) 6576 dev->devx_whitelist_uid = uid; 6577 6578 return 0; 6579 } 6580 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev) 6581 { 6582 if (dev->devx_whitelist_uid) 6583 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 6584 } 6585 6586 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6587 const struct mlx5_ib_profile *profile, 6588 int stage) 6589 { 6590 /* Number of stages to cleanup */ 6591 while (stage) { 6592 stage--; 6593 if (profile->stage[stage].cleanup) 6594 profile->stage[stage].cleanup(dev); 6595 } 6596 6597 kfree(dev->port); 6598 ib_dealloc_device(&dev->ib_dev); 6599 } 6600 6601 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6602 const struct mlx5_ib_profile *profile) 6603 { 6604 int err; 6605 int i; 6606 6607 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6608 if (profile->stage[i].init) { 6609 err = profile->stage[i].init(dev); 6610 if (err) 6611 goto err_out; 6612 } 6613 } 6614 6615 dev->profile = profile; 6616 dev->ib_active = true; 6617 6618 return dev; 6619 6620 err_out: 6621 __mlx5_ib_remove(dev, profile, i); 6622 6623 return NULL; 6624 } 6625 6626 static const struct mlx5_ib_profile pf_profile = { 6627 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6628 mlx5_ib_stage_init_init, 6629 mlx5_ib_stage_init_cleanup), 6630 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6631 mlx5_ib_stage_flow_db_init, 6632 mlx5_ib_stage_flow_db_cleanup), 6633 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6634 mlx5_ib_stage_caps_init, 6635 NULL), 6636 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6637 mlx5_ib_stage_non_default_cb, 6638 NULL), 6639 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6640 mlx5_ib_stage_roce_init, 6641 mlx5_ib_stage_roce_cleanup), 6642 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6643 mlx5_init_srq_table, 6644 mlx5_cleanup_srq_table), 6645 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6646 mlx5_ib_stage_dev_res_init, 6647 mlx5_ib_stage_dev_res_cleanup), 6648 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6649 mlx5_ib_stage_dev_notifier_init, 6650 mlx5_ib_stage_dev_notifier_cleanup), 6651 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6652 mlx5_ib_stage_odp_init, 6653 mlx5_ib_stage_odp_cleanup), 6654 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6655 mlx5_ib_stage_counters_init, 6656 mlx5_ib_stage_counters_cleanup), 6657 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6658 mlx5_ib_stage_cong_debugfs_init, 6659 mlx5_ib_stage_cong_debugfs_cleanup), 6660 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6661 mlx5_ib_stage_uar_init, 6662 mlx5_ib_stage_uar_cleanup), 6663 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6664 mlx5_ib_stage_bfrag_init, 6665 mlx5_ib_stage_bfrag_cleanup), 6666 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6667 NULL, 6668 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6669 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 6670 mlx5_ib_stage_devx_init, 6671 mlx5_ib_stage_devx_cleanup), 6672 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6673 mlx5_ib_stage_ib_reg_init, 6674 mlx5_ib_stage_ib_reg_cleanup), 6675 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6676 mlx5_ib_stage_post_ib_reg_umr_init, 6677 NULL), 6678 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6679 mlx5_ib_stage_delay_drop_init, 6680 mlx5_ib_stage_delay_drop_cleanup), 6681 }; 6682 6683 const struct mlx5_ib_profile uplink_rep_profile = { 6684 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6685 mlx5_ib_stage_init_init, 6686 mlx5_ib_stage_init_cleanup), 6687 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6688 mlx5_ib_stage_flow_db_init, 6689 mlx5_ib_stage_flow_db_cleanup), 6690 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6691 mlx5_ib_stage_caps_init, 6692 NULL), 6693 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6694 mlx5_ib_stage_rep_non_default_cb, 6695 NULL), 6696 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6697 mlx5_ib_stage_rep_roce_init, 6698 mlx5_ib_stage_rep_roce_cleanup), 6699 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6700 mlx5_init_srq_table, 6701 mlx5_cleanup_srq_table), 6702 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6703 mlx5_ib_stage_dev_res_init, 6704 mlx5_ib_stage_dev_res_cleanup), 6705 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6706 mlx5_ib_stage_dev_notifier_init, 6707 mlx5_ib_stage_dev_notifier_cleanup), 6708 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6709 mlx5_ib_stage_counters_init, 6710 mlx5_ib_stage_counters_cleanup), 6711 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6712 mlx5_ib_stage_uar_init, 6713 mlx5_ib_stage_uar_cleanup), 6714 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6715 mlx5_ib_stage_bfrag_init, 6716 mlx5_ib_stage_bfrag_cleanup), 6717 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6718 NULL, 6719 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6720 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 6721 mlx5_ib_stage_devx_init, 6722 mlx5_ib_stage_devx_cleanup), 6723 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6724 mlx5_ib_stage_ib_reg_init, 6725 mlx5_ib_stage_ib_reg_cleanup), 6726 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6727 mlx5_ib_stage_post_ib_reg_umr_init, 6728 NULL), 6729 }; 6730 6731 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6732 { 6733 struct mlx5_ib_multiport_info *mpi; 6734 struct mlx5_ib_dev *dev; 6735 bool bound = false; 6736 int err; 6737 6738 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6739 if (!mpi) 6740 return NULL; 6741 6742 mpi->mdev = mdev; 6743 6744 err = mlx5_query_nic_vport_system_image_guid(mdev, 6745 &mpi->sys_image_guid); 6746 if (err) { 6747 kfree(mpi); 6748 return NULL; 6749 } 6750 6751 mutex_lock(&mlx5_ib_multiport_mutex); 6752 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6753 if (dev->sys_image_guid == mpi->sys_image_guid) 6754 bound = mlx5_ib_bind_slave_port(dev, mpi); 6755 6756 if (bound) { 6757 rdma_roce_rescan_device(&dev->ib_dev); 6758 break; 6759 } 6760 } 6761 6762 if (!bound) { 6763 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6764 dev_dbg(mdev->device, 6765 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6766 } 6767 mutex_unlock(&mlx5_ib_multiport_mutex); 6768 6769 return mpi; 6770 } 6771 6772 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6773 { 6774 enum rdma_link_layer ll; 6775 struct mlx5_ib_dev *dev; 6776 int port_type_cap; 6777 int num_ports; 6778 6779 printk_once(KERN_INFO "%s", mlx5_version); 6780 6781 if (MLX5_ESWITCH_MANAGER(mdev) && 6782 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6783 if (!mlx5_core_mp_enabled(mdev)) 6784 mlx5_ib_register_vport_reps(mdev); 6785 return mdev; 6786 } 6787 6788 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6789 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6790 6791 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6792 return mlx5_ib_add_slave_port(mdev); 6793 6794 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6795 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6796 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 6797 if (!dev) 6798 return NULL; 6799 dev->port = kcalloc(num_ports, sizeof(*dev->port), 6800 GFP_KERNEL); 6801 if (!dev->port) { 6802 ib_dealloc_device((struct ib_device *)dev); 6803 return NULL; 6804 } 6805 6806 dev->mdev = mdev; 6807 dev->num_ports = num_ports; 6808 6809 return __mlx5_ib_add(dev, &pf_profile); 6810 } 6811 6812 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6813 { 6814 struct mlx5_ib_multiport_info *mpi; 6815 struct mlx5_ib_dev *dev; 6816 6817 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 6818 mlx5_ib_unregister_vport_reps(mdev); 6819 return; 6820 } 6821 6822 if (mlx5_core_is_mp_slave(mdev)) { 6823 mpi = context; 6824 mutex_lock(&mlx5_ib_multiport_mutex); 6825 if (mpi->ibdev) 6826 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6827 list_del(&mpi->list); 6828 mutex_unlock(&mlx5_ib_multiport_mutex); 6829 return; 6830 } 6831 6832 dev = context; 6833 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6834 } 6835 6836 static struct mlx5_interface mlx5_ib_interface = { 6837 .add = mlx5_ib_add, 6838 .remove = mlx5_ib_remove, 6839 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6840 }; 6841 6842 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6843 { 6844 mutex_lock(&xlt_emergency_page_mutex); 6845 return xlt_emergency_page; 6846 } 6847 6848 void mlx5_ib_put_xlt_emergency_page(void) 6849 { 6850 mutex_unlock(&xlt_emergency_page_mutex); 6851 } 6852 6853 static int __init mlx5_ib_init(void) 6854 { 6855 int err; 6856 6857 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6858 if (!xlt_emergency_page) 6859 return -ENOMEM; 6860 6861 mutex_init(&xlt_emergency_page_mutex); 6862 6863 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6864 if (!mlx5_ib_event_wq) { 6865 free_page(xlt_emergency_page); 6866 return -ENOMEM; 6867 } 6868 6869 mlx5_ib_odp_init(); 6870 6871 err = mlx5_register_interface(&mlx5_ib_interface); 6872 6873 return err; 6874 } 6875 6876 static void __exit mlx5_ib_cleanup(void) 6877 { 6878 mlx5_unregister_interface(&mlx5_ib_interface); 6879 destroy_workqueue(mlx5_ib_event_wq); 6880 mutex_destroy(&xlt_emergency_page_mutex); 6881 free_page(xlt_emergency_page); 6882 } 6883 6884 module_init(mlx5_ib_init); 6885 module_exit(mlx5_ib_cleanup); 6886