1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include "srq.h" 64 #include <linux/mlx5/fs_helpers.h> 65 #include <linux/mlx5/accel.h> 66 #include <rdma/uverbs_std_types.h> 67 #include <rdma/mlx5_user_ioctl_verbs.h> 68 #include <rdma/mlx5_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME mlx5_ib 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #define DRIVER_NAME "mlx5_ib" 74 #define DRIVER_VERSION "5.0-0" 75 76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 78 MODULE_LICENSE("Dual BSD/GPL"); 79 80 static char mlx5_version[] = 81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 82 DRIVER_VERSION "\n"; 83 84 struct mlx5_ib_event_work { 85 struct work_struct work; 86 union { 87 struct mlx5_ib_dev *dev; 88 struct mlx5_ib_multiport_info *mpi; 89 }; 90 bool is_slave; 91 unsigned int event; 92 void *param; 93 }; 94 95 enum { 96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 97 }; 98 99 static struct workqueue_struct *mlx5_ib_event_wq; 100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 101 static LIST_HEAD(mlx5_ib_dev_list); 102 /* 103 * This mutex should be held when accessing either of the above lists 104 */ 105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 106 107 /* We can't use an array for xlt_emergency_page because dma_map_single 108 * doesn't work on kernel modules memory 109 */ 110 static unsigned long xlt_emergency_page; 111 static struct mutex xlt_emergency_page_mutex; 112 113 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 114 { 115 struct mlx5_ib_dev *dev; 116 117 mutex_lock(&mlx5_ib_multiport_mutex); 118 dev = mpi->ibdev; 119 mutex_unlock(&mlx5_ib_multiport_mutex); 120 return dev; 121 } 122 123 static enum rdma_link_layer 124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 125 { 126 switch (port_type_cap) { 127 case MLX5_CAP_PORT_TYPE_IB: 128 return IB_LINK_LAYER_INFINIBAND; 129 case MLX5_CAP_PORT_TYPE_ETH: 130 return IB_LINK_LAYER_ETHERNET; 131 default: 132 return IB_LINK_LAYER_UNSPECIFIED; 133 } 134 } 135 136 static enum rdma_link_layer 137 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 141 142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 143 } 144 145 static int get_port_state(struct ib_device *ibdev, 146 u8 port_num, 147 enum ib_port_state *state) 148 { 149 struct ib_port_attr attr; 150 int ret; 151 152 memset(&attr, 0, sizeof(attr)); 153 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 154 if (!ret) 155 *state = attr.state; 156 return ret; 157 } 158 159 static int mlx5_netdev_event(struct notifier_block *this, 160 unsigned long event, void *ptr) 161 { 162 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 163 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 164 u8 port_num = roce->native_port_num; 165 struct mlx5_core_dev *mdev; 166 struct mlx5_ib_dev *ibdev; 167 168 ibdev = roce->dev; 169 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 170 if (!mdev) 171 return NOTIFY_DONE; 172 173 switch (event) { 174 case NETDEV_REGISTER: 175 write_lock(&roce->netdev_lock); 176 if (ibdev->rep) { 177 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 178 struct net_device *rep_ndev; 179 180 rep_ndev = mlx5_ib_get_rep_netdev(esw, 181 ibdev->rep->vport); 182 if (rep_ndev == ndev) 183 roce->netdev = ndev; 184 } else if (ndev->dev.parent == &mdev->pdev->dev) { 185 roce->netdev = ndev; 186 } 187 write_unlock(&roce->netdev_lock); 188 break; 189 190 case NETDEV_UNREGISTER: 191 write_lock(&roce->netdev_lock); 192 if (roce->netdev == ndev) 193 roce->netdev = NULL; 194 write_unlock(&roce->netdev_lock); 195 break; 196 197 case NETDEV_CHANGE: 198 case NETDEV_UP: 199 case NETDEV_DOWN: { 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 201 struct net_device *upper = NULL; 202 203 if (lag_ndev) { 204 upper = netdev_master_upper_dev_get(lag_ndev); 205 dev_put(lag_ndev); 206 } 207 208 if ((upper == ndev || (!upper && ndev == roce->netdev)) 209 && ibdev->ib_active) { 210 struct ib_event ibev = { }; 211 enum ib_port_state port_state; 212 213 if (get_port_state(&ibdev->ib_dev, port_num, 214 &port_state)) 215 goto done; 216 217 if (roce->last_port_state == port_state) 218 goto done; 219 220 roce->last_port_state = port_state; 221 ibev.device = &ibdev->ib_dev; 222 if (port_state == IB_PORT_DOWN) 223 ibev.event = IB_EVENT_PORT_ERR; 224 else if (port_state == IB_PORT_ACTIVE) 225 ibev.event = IB_EVENT_PORT_ACTIVE; 226 else 227 goto done; 228 229 ibev.element.port_num = port_num; 230 ib_dispatch_event(&ibev); 231 } 232 break; 233 } 234 235 default: 236 break; 237 } 238 done: 239 mlx5_ib_put_native_port_mdev(ibdev, port_num); 240 return NOTIFY_DONE; 241 } 242 243 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 244 u8 port_num) 245 { 246 struct mlx5_ib_dev *ibdev = to_mdev(device); 247 struct net_device *ndev; 248 struct mlx5_core_dev *mdev; 249 250 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 251 if (!mdev) 252 return NULL; 253 254 ndev = mlx5_lag_get_roce_netdev(mdev); 255 if (ndev) 256 goto out; 257 258 /* Ensure ndev does not disappear before we invoke dev_hold() 259 */ 260 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 261 ndev = ibdev->roce[port_num - 1].netdev; 262 if (ndev) 263 dev_hold(ndev); 264 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 265 266 out: 267 mlx5_ib_put_native_port_mdev(ibdev, port_num); 268 return ndev; 269 } 270 271 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 272 u8 ib_port_num, 273 u8 *native_port_num) 274 { 275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 276 ib_port_num); 277 struct mlx5_core_dev *mdev = NULL; 278 struct mlx5_ib_multiport_info *mpi; 279 struct mlx5_ib_port *port; 280 281 if (!mlx5_core_mp_enabled(ibdev->mdev) || 282 ll != IB_LINK_LAYER_ETHERNET) { 283 if (native_port_num) 284 *native_port_num = ib_port_num; 285 return ibdev->mdev; 286 } 287 288 if (native_port_num) 289 *native_port_num = 1; 290 291 port = &ibdev->port[ib_port_num - 1]; 292 if (!port) 293 return NULL; 294 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 297 if (mpi && !mpi->unaffiliate) { 298 mdev = mpi->mdev; 299 /* If it's the master no need to refcount, it'll exist 300 * as long as the ib_dev exists. 301 */ 302 if (!mpi->is_master) 303 mpi->mdev_refcnt++; 304 } 305 spin_unlock(&port->mp.mpi_lock); 306 307 return mdev; 308 } 309 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 311 { 312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 313 port_num); 314 struct mlx5_ib_multiport_info *mpi; 315 struct mlx5_ib_port *port; 316 317 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 318 return; 319 320 port = &ibdev->port[port_num - 1]; 321 322 spin_lock(&port->mp.mpi_lock); 323 mpi = ibdev->port[port_num - 1].mp.mpi; 324 if (mpi->is_master) 325 goto out; 326 327 mpi->mdev_refcnt--; 328 if (mpi->unaffiliate) 329 complete(&mpi->unref_comp); 330 out: 331 spin_unlock(&port->mp.mpi_lock); 332 } 333 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed, 335 u8 *active_width) 336 { 337 switch (eth_proto_oper) { 338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_SDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 352 *active_width = IB_WIDTH_1X; 353 *active_speed = IB_SPEED_QDR; 354 break; 355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 358 *active_width = IB_WIDTH_1X; 359 *active_speed = IB_SPEED_EDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_QDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_HDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_FDR; 377 break; 378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 382 *active_width = IB_WIDTH_4X; 383 *active_speed = IB_SPEED_EDR; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 return 0; 390 } 391 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 393 u8 *active_width) 394 { 395 switch (eth_proto_oper) { 396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_SDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 402 *active_width = IB_WIDTH_1X; 403 *active_speed = IB_SPEED_DDR; 404 break; 405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 406 *active_width = IB_WIDTH_1X; 407 *active_speed = IB_SPEED_QDR; 408 break; 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 414 *active_width = IB_WIDTH_1X; 415 *active_speed = IB_SPEED_EDR; 416 break; 417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 418 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 419 *active_width = IB_WIDTH_1X; 420 *active_speed = IB_SPEED_HDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 423 *active_width = IB_WIDTH_2X; 424 *active_speed = IB_SPEED_HDR; 425 break; 426 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_HDR; 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 438 u8 *active_width, bool ext) 439 { 440 return ext ? 441 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 442 active_width) : 443 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 444 active_width); 445 } 446 447 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 448 struct ib_port_attr *props) 449 { 450 struct mlx5_ib_dev *dev = to_mdev(device); 451 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 452 struct mlx5_core_dev *mdev; 453 struct net_device *ndev, *upper; 454 enum ib_mtu ndev_ib_mtu; 455 bool put_mdev = true; 456 u16 qkey_viol_cntr; 457 u32 eth_prot_oper; 458 u8 mdev_port_num; 459 bool ext; 460 int err; 461 462 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 463 if (!mdev) { 464 /* This means the port isn't affiliated yet. Get the 465 * info for the master port instead. 466 */ 467 put_mdev = false; 468 mdev = dev->mdev; 469 mdev_port_num = 1; 470 port_num = 1; 471 } 472 473 /* Possible bad flows are checked before filling out props so in case 474 * of an error it will still be zeroed out. 475 */ 476 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 477 mdev_port_num); 478 if (err) 479 goto out; 480 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 481 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 482 483 props->active_width = IB_WIDTH_4X; 484 props->active_speed = IB_SPEED_QDR; 485 486 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 487 &props->active_width, ext); 488 489 props->port_cap_flags |= IB_PORT_CM_SUP; 490 props->ip_gids = true; 491 492 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 493 roce_address_table_size); 494 props->max_mtu = IB_MTU_4096; 495 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 496 props->pkey_tbl_len = 1; 497 props->state = IB_PORT_DOWN; 498 props->phys_state = 3; 499 500 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 501 props->qkey_viol_cntr = qkey_viol_cntr; 502 503 /* If this is a stub query for an unaffiliated port stop here */ 504 if (!put_mdev) 505 goto out; 506 507 ndev = mlx5_ib_get_netdev(device, port_num); 508 if (!ndev) 509 goto out; 510 511 if (dev->lag_active) { 512 rcu_read_lock(); 513 upper = netdev_master_upper_dev_get_rcu(ndev); 514 if (upper) { 515 dev_put(ndev); 516 ndev = upper; 517 dev_hold(ndev); 518 } 519 rcu_read_unlock(); 520 } 521 522 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 523 props->state = IB_PORT_ACTIVE; 524 props->phys_state = 5; 525 } 526 527 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 528 529 dev_put(ndev); 530 531 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 532 out: 533 if (put_mdev) 534 mlx5_ib_put_native_port_mdev(dev, port_num); 535 return err; 536 } 537 538 struct mlx5_ib_vlan_info { 539 u16 vlan_id; 540 bool vlan; 541 }; 542 543 static int get_lower_dev_vlan(struct net_device *lower_dev, void *data) 544 { 545 struct mlx5_ib_vlan_info *vlan_info = data; 546 547 if (is_vlan_dev(lower_dev)) { 548 vlan_info->vlan = true; 549 vlan_info->vlan_id = vlan_dev_vlan_id(lower_dev); 550 } 551 /* We are interested only in first level vlan device, so 552 * always return 1 to stop iterating over next level devices. 553 */ 554 return 1; 555 } 556 557 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 558 unsigned int index, const union ib_gid *gid, 559 const struct ib_gid_attr *attr) 560 { 561 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 562 struct mlx5_ib_vlan_info vlan_info = { }; 563 u8 roce_version = 0; 564 u8 roce_l3_type = 0; 565 u8 mac[ETH_ALEN]; 566 567 if (gid) { 568 gid_type = attr->gid_type; 569 ether_addr_copy(mac, attr->ndev->dev_addr); 570 571 if (is_vlan_dev(attr->ndev)) { 572 vlan_info.vlan = true; 573 vlan_info.vlan_id = vlan_dev_vlan_id(attr->ndev); 574 } else { 575 /* If the netdev is upper device and if it's lower 576 * lower device is vlan device, consider vlan id of 577 * the lower vlan device for this gid entry. 578 */ 579 rcu_read_lock(); 580 netdev_walk_all_lower_dev_rcu(attr->ndev, 581 get_lower_dev_vlan, &vlan_info); 582 rcu_read_unlock(); 583 } 584 } 585 586 switch (gid_type) { 587 case IB_GID_TYPE_IB: 588 roce_version = MLX5_ROCE_VERSION_1; 589 break; 590 case IB_GID_TYPE_ROCE_UDP_ENCAP: 591 roce_version = MLX5_ROCE_VERSION_2; 592 if (ipv6_addr_v4mapped((void *)gid)) 593 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 594 else 595 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 596 break; 597 598 default: 599 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 600 } 601 602 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 603 roce_l3_type, gid->raw, mac, 604 vlan_info.vlan, vlan_info.vlan_id, 605 port_num); 606 } 607 608 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 609 __always_unused void **context) 610 { 611 return set_roce_addr(to_mdev(attr->device), attr->port_num, 612 attr->index, &attr->gid, attr); 613 } 614 615 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 616 __always_unused void **context) 617 { 618 return set_roce_addr(to_mdev(attr->device), attr->port_num, 619 attr->index, NULL, NULL); 620 } 621 622 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 623 const struct ib_gid_attr *attr) 624 { 625 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 626 return 0; 627 628 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 629 } 630 631 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 632 { 633 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 634 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 635 return 0; 636 } 637 638 enum { 639 MLX5_VPORT_ACCESS_METHOD_MAD, 640 MLX5_VPORT_ACCESS_METHOD_HCA, 641 MLX5_VPORT_ACCESS_METHOD_NIC, 642 }; 643 644 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 645 { 646 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 647 return MLX5_VPORT_ACCESS_METHOD_MAD; 648 649 if (mlx5_ib_port_link_layer(ibdev, 1) == 650 IB_LINK_LAYER_ETHERNET) 651 return MLX5_VPORT_ACCESS_METHOD_NIC; 652 653 return MLX5_VPORT_ACCESS_METHOD_HCA; 654 } 655 656 static void get_atomic_caps(struct mlx5_ib_dev *dev, 657 u8 atomic_size_qp, 658 struct ib_device_attr *props) 659 { 660 u8 tmp; 661 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 662 u8 atomic_req_8B_endianness_mode = 663 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 664 665 /* Check if HW supports 8 bytes standard atomic operations and capable 666 * of host endianness respond 667 */ 668 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 669 if (((atomic_operations & tmp) == tmp) && 670 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 671 (atomic_req_8B_endianness_mode)) { 672 props->atomic_cap = IB_ATOMIC_HCA; 673 } else { 674 props->atomic_cap = IB_ATOMIC_NONE; 675 } 676 } 677 678 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 679 struct ib_device_attr *props) 680 { 681 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 682 683 get_atomic_caps(dev, atomic_size_qp, props); 684 } 685 686 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 687 struct ib_device_attr *props) 688 { 689 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 690 691 get_atomic_caps(dev, atomic_size_qp, props); 692 } 693 694 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 695 { 696 struct ib_device_attr props = {}; 697 698 get_atomic_caps_dc(dev, &props); 699 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 700 } 701 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 702 __be64 *sys_image_guid) 703 { 704 struct mlx5_ib_dev *dev = to_mdev(ibdev); 705 struct mlx5_core_dev *mdev = dev->mdev; 706 u64 tmp; 707 int err; 708 709 switch (mlx5_get_vport_access_method(ibdev)) { 710 case MLX5_VPORT_ACCESS_METHOD_MAD: 711 return mlx5_query_mad_ifc_system_image_guid(ibdev, 712 sys_image_guid); 713 714 case MLX5_VPORT_ACCESS_METHOD_HCA: 715 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 716 break; 717 718 case MLX5_VPORT_ACCESS_METHOD_NIC: 719 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 720 break; 721 722 default: 723 return -EINVAL; 724 } 725 726 if (!err) 727 *sys_image_guid = cpu_to_be64(tmp); 728 729 return err; 730 731 } 732 733 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 734 u16 *max_pkeys) 735 { 736 struct mlx5_ib_dev *dev = to_mdev(ibdev); 737 struct mlx5_core_dev *mdev = dev->mdev; 738 739 switch (mlx5_get_vport_access_method(ibdev)) { 740 case MLX5_VPORT_ACCESS_METHOD_MAD: 741 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 742 743 case MLX5_VPORT_ACCESS_METHOD_HCA: 744 case MLX5_VPORT_ACCESS_METHOD_NIC: 745 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 746 pkey_table_size)); 747 return 0; 748 749 default: 750 return -EINVAL; 751 } 752 } 753 754 static int mlx5_query_vendor_id(struct ib_device *ibdev, 755 u32 *vendor_id) 756 { 757 struct mlx5_ib_dev *dev = to_mdev(ibdev); 758 759 switch (mlx5_get_vport_access_method(ibdev)) { 760 case MLX5_VPORT_ACCESS_METHOD_MAD: 761 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 762 763 case MLX5_VPORT_ACCESS_METHOD_HCA: 764 case MLX5_VPORT_ACCESS_METHOD_NIC: 765 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 766 767 default: 768 return -EINVAL; 769 } 770 } 771 772 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 773 __be64 *node_guid) 774 { 775 u64 tmp; 776 int err; 777 778 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 779 case MLX5_VPORT_ACCESS_METHOD_MAD: 780 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 781 782 case MLX5_VPORT_ACCESS_METHOD_HCA: 783 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 784 break; 785 786 case MLX5_VPORT_ACCESS_METHOD_NIC: 787 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 788 break; 789 790 default: 791 return -EINVAL; 792 } 793 794 if (!err) 795 *node_guid = cpu_to_be64(tmp); 796 797 return err; 798 } 799 800 struct mlx5_reg_node_desc { 801 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 802 }; 803 804 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 805 { 806 struct mlx5_reg_node_desc in; 807 808 if (mlx5_use_mad_ifc(dev)) 809 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 810 811 memset(&in, 0, sizeof(in)); 812 813 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 814 sizeof(struct mlx5_reg_node_desc), 815 MLX5_REG_NODE_DESC, 0, 0); 816 } 817 818 static int mlx5_ib_query_device(struct ib_device *ibdev, 819 struct ib_device_attr *props, 820 struct ib_udata *uhw) 821 { 822 struct mlx5_ib_dev *dev = to_mdev(ibdev); 823 struct mlx5_core_dev *mdev = dev->mdev; 824 int err = -ENOMEM; 825 int max_sq_desc; 826 int max_rq_sg; 827 int max_sq_sg; 828 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 829 bool raw_support = !mlx5_core_mp_enabled(mdev); 830 struct mlx5_ib_query_device_resp resp = {}; 831 size_t resp_len; 832 u64 max_tso; 833 834 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 835 if (uhw->outlen && uhw->outlen < resp_len) 836 return -EINVAL; 837 else 838 resp.response_length = resp_len; 839 840 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 841 return -EINVAL; 842 843 memset(props, 0, sizeof(*props)); 844 err = mlx5_query_system_image_guid(ibdev, 845 &props->sys_image_guid); 846 if (err) 847 return err; 848 849 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 850 if (err) 851 return err; 852 853 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 854 if (err) 855 return err; 856 857 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 858 (fw_rev_min(dev->mdev) << 16) | 859 fw_rev_sub(dev->mdev); 860 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 861 IB_DEVICE_PORT_ACTIVE_EVENT | 862 IB_DEVICE_SYS_IMAGE_GUID | 863 IB_DEVICE_RC_RNR_NAK_GEN; 864 865 if (MLX5_CAP_GEN(mdev, pkv)) 866 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 867 if (MLX5_CAP_GEN(mdev, qkv)) 868 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 869 if (MLX5_CAP_GEN(mdev, apm)) 870 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 871 if (MLX5_CAP_GEN(mdev, xrc)) 872 props->device_cap_flags |= IB_DEVICE_XRC; 873 if (MLX5_CAP_GEN(mdev, imaicl)) { 874 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 875 IB_DEVICE_MEM_WINDOW_TYPE_2B; 876 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 877 /* We support 'Gappy' memory registration too */ 878 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 879 } 880 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 881 if (MLX5_CAP_GEN(mdev, sho)) { 882 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 883 /* At this stage no support for signature handover */ 884 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 885 IB_PROT_T10DIF_TYPE_2 | 886 IB_PROT_T10DIF_TYPE_3; 887 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 888 IB_GUARD_T10DIF_CSUM; 889 } 890 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 891 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 892 893 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 894 if (MLX5_CAP_ETH(mdev, csum_cap)) { 895 /* Legacy bit to support old userspace libraries */ 896 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 897 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 898 } 899 900 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 901 props->raw_packet_caps |= 902 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 903 904 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 905 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 906 if (max_tso) { 907 resp.tso_caps.max_tso = 1 << max_tso; 908 resp.tso_caps.supported_qpts |= 909 1 << IB_QPT_RAW_PACKET; 910 resp.response_length += sizeof(resp.tso_caps); 911 } 912 } 913 914 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 915 resp.rss_caps.rx_hash_function = 916 MLX5_RX_HASH_FUNC_TOEPLITZ; 917 resp.rss_caps.rx_hash_fields_mask = 918 MLX5_RX_HASH_SRC_IPV4 | 919 MLX5_RX_HASH_DST_IPV4 | 920 MLX5_RX_HASH_SRC_IPV6 | 921 MLX5_RX_HASH_DST_IPV6 | 922 MLX5_RX_HASH_SRC_PORT_TCP | 923 MLX5_RX_HASH_DST_PORT_TCP | 924 MLX5_RX_HASH_SRC_PORT_UDP | 925 MLX5_RX_HASH_DST_PORT_UDP | 926 MLX5_RX_HASH_INNER; 927 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 928 MLX5_ACCEL_IPSEC_CAP_DEVICE) 929 resp.rss_caps.rx_hash_fields_mask |= 930 MLX5_RX_HASH_IPSEC_SPI; 931 resp.response_length += sizeof(resp.rss_caps); 932 } 933 } else { 934 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 935 resp.response_length += sizeof(resp.tso_caps); 936 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 937 resp.response_length += sizeof(resp.rss_caps); 938 } 939 940 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 941 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 942 props->device_cap_flags |= IB_DEVICE_UD_TSO; 943 } 944 945 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 946 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 947 raw_support) 948 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 949 950 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 951 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 952 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 953 954 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 955 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 956 raw_support) { 957 /* Legacy bit to support old userspace libraries */ 958 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 959 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 960 } 961 962 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 963 props->max_dm_size = 964 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 965 } 966 967 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 968 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 969 970 if (MLX5_CAP_GEN(mdev, end_pad)) 971 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 972 973 props->vendor_part_id = mdev->pdev->device; 974 props->hw_ver = mdev->pdev->revision; 975 976 props->max_mr_size = ~0ull; 977 props->page_size_cap = ~(min_page_size - 1); 978 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 979 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 980 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 981 sizeof(struct mlx5_wqe_data_seg); 982 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 983 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 984 sizeof(struct mlx5_wqe_raddr_seg)) / 985 sizeof(struct mlx5_wqe_data_seg); 986 props->max_send_sge = max_sq_sg; 987 props->max_recv_sge = max_rq_sg; 988 props->max_sge_rd = MLX5_MAX_SGE_RD; 989 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 990 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 991 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 992 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 993 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 994 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 995 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 996 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 997 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 998 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 999 props->max_srq_sge = max_rq_sg - 1; 1000 props->max_fast_reg_page_list_len = 1001 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1002 get_atomic_caps_qp(dev, props); 1003 props->masked_atomic_cap = IB_ATOMIC_NONE; 1004 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1005 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1006 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1007 props->max_mcast_grp; 1008 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 1009 props->max_ah = INT_MAX; 1010 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1011 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1012 1013 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1014 if (MLX5_CAP_GEN(mdev, pg)) 1015 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1016 props->odp_caps = dev->odp_caps; 1017 } 1018 1019 if (MLX5_CAP_GEN(mdev, cd)) 1020 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1021 1022 if (!mlx5_core_is_pf(mdev)) 1023 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1024 1025 if (mlx5_ib_port_link_layer(ibdev, 1) == 1026 IB_LINK_LAYER_ETHERNET && raw_support) { 1027 props->rss_caps.max_rwq_indirection_tables = 1028 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1029 props->rss_caps.max_rwq_indirection_table_size = 1030 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1031 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1032 props->max_wq_type_rq = 1033 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1034 } 1035 1036 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1037 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1038 props->tm_caps.max_num_tags = 1039 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1040 props->tm_caps.flags = IB_TM_CAP_RC; 1041 props->tm_caps.max_ops = 1042 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1043 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1044 } 1045 1046 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1047 props->cq_caps.max_cq_moderation_count = 1048 MLX5_MAX_CQ_COUNT; 1049 props->cq_caps.max_cq_moderation_period = 1050 MLX5_MAX_CQ_PERIOD; 1051 } 1052 1053 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 1054 resp.response_length += sizeof(resp.cqe_comp_caps); 1055 1056 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1057 resp.cqe_comp_caps.max_num = 1058 MLX5_CAP_GEN(dev->mdev, 1059 cqe_compression_max_num); 1060 1061 resp.cqe_comp_caps.supported_format = 1062 MLX5_IB_CQE_RES_FORMAT_HASH | 1063 MLX5_IB_CQE_RES_FORMAT_CSUM; 1064 1065 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1066 resp.cqe_comp_caps.supported_format |= 1067 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1068 } 1069 } 1070 1071 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 1072 raw_support) { 1073 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1074 MLX5_CAP_GEN(mdev, qos)) { 1075 resp.packet_pacing_caps.qp_rate_limit_max = 1076 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1077 resp.packet_pacing_caps.qp_rate_limit_min = 1078 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1079 resp.packet_pacing_caps.supported_qpts |= 1080 1 << IB_QPT_RAW_PACKET; 1081 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1082 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1083 resp.packet_pacing_caps.cap_flags |= 1084 MLX5_IB_PP_SUPPORT_BURST; 1085 } 1086 resp.response_length += sizeof(resp.packet_pacing_caps); 1087 } 1088 1089 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 1090 uhw->outlen)) { 1091 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1092 resp.mlx5_ib_support_multi_pkt_send_wqes = 1093 MLX5_IB_ALLOW_MPW; 1094 1095 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1096 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1097 MLX5_IB_SUPPORT_EMPW; 1098 1099 resp.response_length += 1100 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1101 } 1102 1103 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1104 resp.response_length += sizeof(resp.flags); 1105 1106 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1107 resp.flags |= 1108 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1109 1110 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1111 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1112 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1113 resp.flags |= 1114 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1115 } 1116 1117 if (field_avail(typeof(resp), sw_parsing_caps, 1118 uhw->outlen)) { 1119 resp.response_length += sizeof(resp.sw_parsing_caps); 1120 if (MLX5_CAP_ETH(mdev, swp)) { 1121 resp.sw_parsing_caps.sw_parsing_offloads |= 1122 MLX5_IB_SW_PARSING; 1123 1124 if (MLX5_CAP_ETH(mdev, swp_csum)) 1125 resp.sw_parsing_caps.sw_parsing_offloads |= 1126 MLX5_IB_SW_PARSING_CSUM; 1127 1128 if (MLX5_CAP_ETH(mdev, swp_lso)) 1129 resp.sw_parsing_caps.sw_parsing_offloads |= 1130 MLX5_IB_SW_PARSING_LSO; 1131 1132 if (resp.sw_parsing_caps.sw_parsing_offloads) 1133 resp.sw_parsing_caps.supported_qpts = 1134 BIT(IB_QPT_RAW_PACKET); 1135 } 1136 } 1137 1138 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1139 raw_support) { 1140 resp.response_length += sizeof(resp.striding_rq_caps); 1141 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1142 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1143 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1144 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1145 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1146 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1147 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1148 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1149 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1150 resp.striding_rq_caps.supported_qpts = 1151 BIT(IB_QPT_RAW_PACKET); 1152 } 1153 } 1154 1155 if (field_avail(typeof(resp), tunnel_offloads_caps, 1156 uhw->outlen)) { 1157 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1158 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1159 resp.tunnel_offloads_caps |= 1160 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1161 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1162 resp.tunnel_offloads_caps |= 1163 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1164 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1165 resp.tunnel_offloads_caps |= 1166 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1167 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1168 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1169 resp.tunnel_offloads_caps |= 1170 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1171 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1172 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1173 resp.tunnel_offloads_caps |= 1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1175 } 1176 1177 if (uhw->outlen) { 1178 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1179 1180 if (err) 1181 return err; 1182 } 1183 1184 return 0; 1185 } 1186 1187 enum mlx5_ib_width { 1188 MLX5_IB_WIDTH_1X = 1 << 0, 1189 MLX5_IB_WIDTH_2X = 1 << 1, 1190 MLX5_IB_WIDTH_4X = 1 << 2, 1191 MLX5_IB_WIDTH_8X = 1 << 3, 1192 MLX5_IB_WIDTH_12X = 1 << 4 1193 }; 1194 1195 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1196 u8 *ib_width) 1197 { 1198 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1199 1200 if (active_width & MLX5_IB_WIDTH_1X) 1201 *ib_width = IB_WIDTH_1X; 1202 else if (active_width & MLX5_IB_WIDTH_2X) 1203 *ib_width = IB_WIDTH_2X; 1204 else if (active_width & MLX5_IB_WIDTH_4X) 1205 *ib_width = IB_WIDTH_4X; 1206 else if (active_width & MLX5_IB_WIDTH_8X) 1207 *ib_width = IB_WIDTH_8X; 1208 else if (active_width & MLX5_IB_WIDTH_12X) 1209 *ib_width = IB_WIDTH_12X; 1210 else { 1211 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1212 (int)active_width); 1213 *ib_width = IB_WIDTH_4X; 1214 } 1215 1216 return; 1217 } 1218 1219 static int mlx5_mtu_to_ib_mtu(int mtu) 1220 { 1221 switch (mtu) { 1222 case 256: return 1; 1223 case 512: return 2; 1224 case 1024: return 3; 1225 case 2048: return 4; 1226 case 4096: return 5; 1227 default: 1228 pr_warn("invalid mtu\n"); 1229 return -1; 1230 } 1231 } 1232 1233 enum ib_max_vl_num { 1234 __IB_MAX_VL_0 = 1, 1235 __IB_MAX_VL_0_1 = 2, 1236 __IB_MAX_VL_0_3 = 3, 1237 __IB_MAX_VL_0_7 = 4, 1238 __IB_MAX_VL_0_14 = 5, 1239 }; 1240 1241 enum mlx5_vl_hw_cap { 1242 MLX5_VL_HW_0 = 1, 1243 MLX5_VL_HW_0_1 = 2, 1244 MLX5_VL_HW_0_2 = 3, 1245 MLX5_VL_HW_0_3 = 4, 1246 MLX5_VL_HW_0_4 = 5, 1247 MLX5_VL_HW_0_5 = 6, 1248 MLX5_VL_HW_0_6 = 7, 1249 MLX5_VL_HW_0_7 = 8, 1250 MLX5_VL_HW_0_14 = 15 1251 }; 1252 1253 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1254 u8 *max_vl_num) 1255 { 1256 switch (vl_hw_cap) { 1257 case MLX5_VL_HW_0: 1258 *max_vl_num = __IB_MAX_VL_0; 1259 break; 1260 case MLX5_VL_HW_0_1: 1261 *max_vl_num = __IB_MAX_VL_0_1; 1262 break; 1263 case MLX5_VL_HW_0_3: 1264 *max_vl_num = __IB_MAX_VL_0_3; 1265 break; 1266 case MLX5_VL_HW_0_7: 1267 *max_vl_num = __IB_MAX_VL_0_7; 1268 break; 1269 case MLX5_VL_HW_0_14: 1270 *max_vl_num = __IB_MAX_VL_0_14; 1271 break; 1272 1273 default: 1274 return -EINVAL; 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1281 struct ib_port_attr *props) 1282 { 1283 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1284 struct mlx5_core_dev *mdev = dev->mdev; 1285 struct mlx5_hca_vport_context *rep; 1286 u16 max_mtu; 1287 u16 oper_mtu; 1288 int err; 1289 u8 ib_link_width_oper; 1290 u8 vl_hw_cap; 1291 1292 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1293 if (!rep) { 1294 err = -ENOMEM; 1295 goto out; 1296 } 1297 1298 /* props being zeroed by the caller, avoid zeroing it here */ 1299 1300 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1301 if (err) 1302 goto out; 1303 1304 props->lid = rep->lid; 1305 props->lmc = rep->lmc; 1306 props->sm_lid = rep->sm_lid; 1307 props->sm_sl = rep->sm_sl; 1308 props->state = rep->vport_state; 1309 props->phys_state = rep->port_physical_state; 1310 props->port_cap_flags = rep->cap_mask1; 1311 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1312 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1313 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1314 props->bad_pkey_cntr = rep->pkey_violation_counter; 1315 props->qkey_viol_cntr = rep->qkey_violation_counter; 1316 props->subnet_timeout = rep->subnet_timeout; 1317 props->init_type_reply = rep->init_type_reply; 1318 1319 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1320 props->port_cap_flags2 = rep->cap_mask2; 1321 1322 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1323 if (err) 1324 goto out; 1325 1326 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1327 1328 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1329 if (err) 1330 goto out; 1331 1332 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1333 1334 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1335 1336 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1337 1338 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1339 1340 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1341 if (err) 1342 goto out; 1343 1344 err = translate_max_vl_num(ibdev, vl_hw_cap, 1345 &props->max_vl_num); 1346 out: 1347 kfree(rep); 1348 return err; 1349 } 1350 1351 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1352 struct ib_port_attr *props) 1353 { 1354 unsigned int count; 1355 int ret; 1356 1357 switch (mlx5_get_vport_access_method(ibdev)) { 1358 case MLX5_VPORT_ACCESS_METHOD_MAD: 1359 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1360 break; 1361 1362 case MLX5_VPORT_ACCESS_METHOD_HCA: 1363 ret = mlx5_query_hca_port(ibdev, port, props); 1364 break; 1365 1366 case MLX5_VPORT_ACCESS_METHOD_NIC: 1367 ret = mlx5_query_port_roce(ibdev, port, props); 1368 break; 1369 1370 default: 1371 ret = -EINVAL; 1372 } 1373 1374 if (!ret && props) { 1375 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1376 struct mlx5_core_dev *mdev; 1377 bool put_mdev = true; 1378 1379 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1380 if (!mdev) { 1381 /* If the port isn't affiliated yet query the master. 1382 * The master and slave will have the same values. 1383 */ 1384 mdev = dev->mdev; 1385 port = 1; 1386 put_mdev = false; 1387 } 1388 count = mlx5_core_reserved_gids_count(mdev); 1389 if (put_mdev) 1390 mlx5_ib_put_native_port_mdev(dev, port); 1391 props->gid_tbl_len -= count; 1392 } 1393 return ret; 1394 } 1395 1396 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1397 struct ib_port_attr *props) 1398 { 1399 int ret; 1400 1401 /* Only link layer == ethernet is valid for representors */ 1402 ret = mlx5_query_port_roce(ibdev, port, props); 1403 if (ret || !props) 1404 return ret; 1405 1406 /* We don't support GIDS */ 1407 props->gid_tbl_len = 0; 1408 1409 return ret; 1410 } 1411 1412 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1413 union ib_gid *gid) 1414 { 1415 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1416 struct mlx5_core_dev *mdev = dev->mdev; 1417 1418 switch (mlx5_get_vport_access_method(ibdev)) { 1419 case MLX5_VPORT_ACCESS_METHOD_MAD: 1420 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1421 1422 case MLX5_VPORT_ACCESS_METHOD_HCA: 1423 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1424 1425 default: 1426 return -EINVAL; 1427 } 1428 1429 } 1430 1431 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1432 u16 index, u16 *pkey) 1433 { 1434 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1435 struct mlx5_core_dev *mdev; 1436 bool put_mdev = true; 1437 u8 mdev_port_num; 1438 int err; 1439 1440 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1441 if (!mdev) { 1442 /* The port isn't affiliated yet, get the PKey from the master 1443 * port. For RoCE the PKey tables will be the same. 1444 */ 1445 put_mdev = false; 1446 mdev = dev->mdev; 1447 mdev_port_num = 1; 1448 } 1449 1450 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1451 index, pkey); 1452 if (put_mdev) 1453 mlx5_ib_put_native_port_mdev(dev, port); 1454 1455 return err; 1456 } 1457 1458 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1459 u16 *pkey) 1460 { 1461 switch (mlx5_get_vport_access_method(ibdev)) { 1462 case MLX5_VPORT_ACCESS_METHOD_MAD: 1463 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1464 1465 case MLX5_VPORT_ACCESS_METHOD_HCA: 1466 case MLX5_VPORT_ACCESS_METHOD_NIC: 1467 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1468 default: 1469 return -EINVAL; 1470 } 1471 } 1472 1473 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1474 struct ib_device_modify *props) 1475 { 1476 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1477 struct mlx5_reg_node_desc in; 1478 struct mlx5_reg_node_desc out; 1479 int err; 1480 1481 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1482 return -EOPNOTSUPP; 1483 1484 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1485 return 0; 1486 1487 /* 1488 * If possible, pass node desc to FW, so it can generate 1489 * a 144 trap. If cmd fails, just ignore. 1490 */ 1491 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1492 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1493 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1494 if (err) 1495 return err; 1496 1497 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1498 1499 return err; 1500 } 1501 1502 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1503 u32 value) 1504 { 1505 struct mlx5_hca_vport_context ctx = {}; 1506 struct mlx5_core_dev *mdev; 1507 u8 mdev_port_num; 1508 int err; 1509 1510 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1511 if (!mdev) 1512 return -ENODEV; 1513 1514 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1515 if (err) 1516 goto out; 1517 1518 if (~ctx.cap_mask1_perm & mask) { 1519 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1520 mask, ctx.cap_mask1_perm); 1521 err = -EINVAL; 1522 goto out; 1523 } 1524 1525 ctx.cap_mask1 = value; 1526 ctx.cap_mask1_perm = mask; 1527 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1528 0, &ctx); 1529 1530 out: 1531 mlx5_ib_put_native_port_mdev(dev, port_num); 1532 1533 return err; 1534 } 1535 1536 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1537 struct ib_port_modify *props) 1538 { 1539 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1540 struct ib_port_attr attr; 1541 u32 tmp; 1542 int err; 1543 u32 change_mask; 1544 u32 value; 1545 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1546 IB_LINK_LAYER_INFINIBAND); 1547 1548 /* CM layer calls ib_modify_port() regardless of the link layer. For 1549 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1550 */ 1551 if (!is_ib) 1552 return 0; 1553 1554 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1555 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1556 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1557 return set_port_caps_atomic(dev, port, change_mask, value); 1558 } 1559 1560 mutex_lock(&dev->cap_mask_mutex); 1561 1562 err = ib_query_port(ibdev, port, &attr); 1563 if (err) 1564 goto out; 1565 1566 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1567 ~props->clr_port_cap_mask; 1568 1569 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1570 1571 out: 1572 mutex_unlock(&dev->cap_mask_mutex); 1573 return err; 1574 } 1575 1576 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1577 { 1578 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1579 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1580 } 1581 1582 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1583 { 1584 /* Large page with non 4k uar support might limit the dynamic size */ 1585 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1586 return MLX5_MIN_DYN_BFREGS; 1587 1588 return MLX5_MAX_DYN_BFREGS; 1589 } 1590 1591 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1592 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1593 struct mlx5_bfreg_info *bfregi) 1594 { 1595 int uars_per_sys_page; 1596 int bfregs_per_sys_page; 1597 int ref_bfregs = req->total_num_bfregs; 1598 1599 if (req->total_num_bfregs == 0) 1600 return -EINVAL; 1601 1602 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1603 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1604 1605 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1606 return -ENOMEM; 1607 1608 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1609 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1610 /* This holds the required static allocation asked by the user */ 1611 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1612 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1613 return -EINVAL; 1614 1615 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1616 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1617 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1618 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1619 1620 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1621 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1622 lib_uar_4k ? "yes" : "no", ref_bfregs, 1623 req->total_num_bfregs, bfregi->total_num_bfregs, 1624 bfregi->num_sys_pages); 1625 1626 return 0; 1627 } 1628 1629 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1630 { 1631 struct mlx5_bfreg_info *bfregi; 1632 int err; 1633 int i; 1634 1635 bfregi = &context->bfregi; 1636 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1637 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1638 if (err) 1639 goto error; 1640 1641 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1642 } 1643 1644 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1645 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1646 1647 return 0; 1648 1649 error: 1650 for (--i; i >= 0; i--) 1651 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1652 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1653 1654 return err; 1655 } 1656 1657 static void deallocate_uars(struct mlx5_ib_dev *dev, 1658 struct mlx5_ib_ucontext *context) 1659 { 1660 struct mlx5_bfreg_info *bfregi; 1661 int i; 1662 1663 bfregi = &context->bfregi; 1664 for (i = 0; i < bfregi->num_sys_pages; i++) 1665 if (i < bfregi->num_static_sys_pages || 1666 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1667 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1668 } 1669 1670 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1671 { 1672 int err = 0; 1673 1674 mutex_lock(&dev->lb.mutex); 1675 if (td) 1676 dev->lb.user_td++; 1677 if (qp) 1678 dev->lb.qps++; 1679 1680 if (dev->lb.user_td == 2 || 1681 dev->lb.qps == 1) { 1682 if (!dev->lb.enabled) { 1683 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1684 dev->lb.enabled = true; 1685 } 1686 } 1687 1688 mutex_unlock(&dev->lb.mutex); 1689 1690 return err; 1691 } 1692 1693 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1694 { 1695 mutex_lock(&dev->lb.mutex); 1696 if (td) 1697 dev->lb.user_td--; 1698 if (qp) 1699 dev->lb.qps--; 1700 1701 if (dev->lb.user_td == 1 && 1702 dev->lb.qps == 0) { 1703 if (dev->lb.enabled) { 1704 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1705 dev->lb.enabled = false; 1706 } 1707 } 1708 1709 mutex_unlock(&dev->lb.mutex); 1710 } 1711 1712 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1713 u16 uid) 1714 { 1715 int err; 1716 1717 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1718 return 0; 1719 1720 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1721 if (err) 1722 return err; 1723 1724 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1725 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1726 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1727 return err; 1728 1729 return mlx5_ib_enable_lb(dev, true, false); 1730 } 1731 1732 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1733 u16 uid) 1734 { 1735 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1736 return; 1737 1738 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1739 1740 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1741 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1742 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1743 return; 1744 1745 mlx5_ib_disable_lb(dev, true, false); 1746 } 1747 1748 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1749 struct ib_udata *udata) 1750 { 1751 struct ib_device *ibdev = uctx->device; 1752 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1753 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1754 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1755 struct mlx5_core_dev *mdev = dev->mdev; 1756 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1757 struct mlx5_bfreg_info *bfregi; 1758 int ver; 1759 int err; 1760 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1761 max_cqe_version); 1762 u32 dump_fill_mkey; 1763 bool lib_uar_4k; 1764 1765 if (!dev->ib_active) 1766 return -EAGAIN; 1767 1768 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1769 ver = 0; 1770 else if (udata->inlen >= min_req_v2) 1771 ver = 2; 1772 else 1773 return -EINVAL; 1774 1775 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1776 if (err) 1777 return err; 1778 1779 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1780 return -EOPNOTSUPP; 1781 1782 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1783 return -EOPNOTSUPP; 1784 1785 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1786 MLX5_NON_FP_BFREGS_PER_UAR); 1787 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1788 return -EINVAL; 1789 1790 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1791 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1792 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1793 resp.cache_line_size = cache_line_size(); 1794 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1795 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1796 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1797 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1798 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1799 resp.cqe_version = min_t(__u8, 1800 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1801 req.max_cqe_version); 1802 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1803 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1804 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1805 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1806 resp.response_length = min(offsetof(typeof(resp), response_length) + 1807 sizeof(resp.response_length), udata->outlen); 1808 1809 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1810 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1811 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1812 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1813 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1814 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1815 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1816 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1817 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1818 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1819 } 1820 1821 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1822 bfregi = &context->bfregi; 1823 1824 /* updates req->total_num_bfregs */ 1825 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1826 if (err) 1827 goto out_ctx; 1828 1829 mutex_init(&bfregi->lock); 1830 bfregi->lib_uar_4k = lib_uar_4k; 1831 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1832 GFP_KERNEL); 1833 if (!bfregi->count) { 1834 err = -ENOMEM; 1835 goto out_ctx; 1836 } 1837 1838 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1839 sizeof(*bfregi->sys_pages), 1840 GFP_KERNEL); 1841 if (!bfregi->sys_pages) { 1842 err = -ENOMEM; 1843 goto out_count; 1844 } 1845 1846 err = allocate_uars(dev, context); 1847 if (err) 1848 goto out_sys_pages; 1849 1850 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING) 1851 context->ibucontext.invalidate_range = 1852 &mlx5_ib_invalidate_range; 1853 1854 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1855 err = mlx5_ib_devx_create(dev, true); 1856 if (err < 0) 1857 goto out_uars; 1858 context->devx_uid = err; 1859 } 1860 1861 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1862 context->devx_uid); 1863 if (err) 1864 goto out_devx; 1865 1866 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1867 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1868 if (err) 1869 goto out_mdev; 1870 } 1871 1872 INIT_LIST_HEAD(&context->db_page_list); 1873 mutex_init(&context->db_page_mutex); 1874 1875 resp.tot_bfregs = req.total_num_bfregs; 1876 resp.num_ports = dev->num_ports; 1877 1878 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1879 resp.response_length += sizeof(resp.cqe_version); 1880 1881 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1882 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1883 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1884 resp.response_length += sizeof(resp.cmds_supp_uhw); 1885 } 1886 1887 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1888 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1889 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1890 resp.eth_min_inline++; 1891 } 1892 resp.response_length += sizeof(resp.eth_min_inline); 1893 } 1894 1895 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1896 if (mdev->clock_info) 1897 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1898 resp.response_length += sizeof(resp.clock_info_versions); 1899 } 1900 1901 /* 1902 * We don't want to expose information from the PCI bar that is located 1903 * after 4096 bytes, so if the arch only supports larger pages, let's 1904 * pretend we don't support reading the HCA's core clock. This is also 1905 * forced by mmap function. 1906 */ 1907 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1908 if (PAGE_SIZE <= 4096) { 1909 resp.comp_mask |= 1910 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1911 resp.hca_core_clock_offset = 1912 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1913 } 1914 resp.response_length += sizeof(resp.hca_core_clock_offset); 1915 } 1916 1917 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1918 resp.response_length += sizeof(resp.log_uar_size); 1919 1920 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1921 resp.response_length += sizeof(resp.num_uars_per_page); 1922 1923 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1924 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1925 resp.response_length += sizeof(resp.num_dyn_bfregs); 1926 } 1927 1928 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1929 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1930 resp.dump_fill_mkey = dump_fill_mkey; 1931 resp.comp_mask |= 1932 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1933 } 1934 resp.response_length += sizeof(resp.dump_fill_mkey); 1935 } 1936 1937 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1938 if (err) 1939 goto out_mdev; 1940 1941 bfregi->ver = ver; 1942 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1943 context->cqe_version = resp.cqe_version; 1944 context->lib_caps = req.lib_caps; 1945 print_lib_caps(dev, context->lib_caps); 1946 1947 if (dev->lag_active) { 1948 u8 port = mlx5_core_native_port_num(dev->mdev); 1949 1950 atomic_set(&context->tx_port_affinity, 1951 atomic_add_return( 1952 1, &dev->roce[port].tx_port_affinity)); 1953 } 1954 1955 return 0; 1956 1957 out_mdev: 1958 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1959 out_devx: 1960 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1961 mlx5_ib_devx_destroy(dev, context->devx_uid); 1962 1963 out_uars: 1964 deallocate_uars(dev, context); 1965 1966 out_sys_pages: 1967 kfree(bfregi->sys_pages); 1968 1969 out_count: 1970 kfree(bfregi->count); 1971 1972 out_ctx: 1973 return err; 1974 } 1975 1976 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1977 { 1978 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1979 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1980 struct mlx5_bfreg_info *bfregi; 1981 1982 /* All umem's must be destroyed before destroying the ucontext. */ 1983 mutex_lock(&ibcontext->per_mm_list_lock); 1984 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1985 mutex_unlock(&ibcontext->per_mm_list_lock); 1986 1987 bfregi = &context->bfregi; 1988 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1989 1990 if (context->devx_uid) 1991 mlx5_ib_devx_destroy(dev, context->devx_uid); 1992 1993 deallocate_uars(dev, context); 1994 kfree(bfregi->sys_pages); 1995 kfree(bfregi->count); 1996 } 1997 1998 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1999 int uar_idx) 2000 { 2001 int fw_uars_per_page; 2002 2003 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2004 2005 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2006 } 2007 2008 static int get_command(unsigned long offset) 2009 { 2010 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2011 } 2012 2013 static int get_arg(unsigned long offset) 2014 { 2015 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2016 } 2017 2018 static int get_index(unsigned long offset) 2019 { 2020 return get_arg(offset); 2021 } 2022 2023 /* Index resides in an extra byte to enable larger values than 255 */ 2024 static int get_extended_index(unsigned long offset) 2025 { 2026 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2027 } 2028 2029 2030 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2031 { 2032 } 2033 2034 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2035 { 2036 switch (cmd) { 2037 case MLX5_IB_MMAP_WC_PAGE: 2038 return "WC"; 2039 case MLX5_IB_MMAP_REGULAR_PAGE: 2040 return "best effort WC"; 2041 case MLX5_IB_MMAP_NC_PAGE: 2042 return "NC"; 2043 case MLX5_IB_MMAP_DEVICE_MEM: 2044 return "Device Memory"; 2045 default: 2046 return NULL; 2047 } 2048 } 2049 2050 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2051 struct vm_area_struct *vma, 2052 struct mlx5_ib_ucontext *context) 2053 { 2054 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2055 return -EINVAL; 2056 2057 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2058 return -EOPNOTSUPP; 2059 2060 if (vma->vm_flags & VM_WRITE) 2061 return -EPERM; 2062 2063 if (!dev->mdev->clock_info_page) 2064 return -EOPNOTSUPP; 2065 2066 return rdma_user_mmap_page(&context->ibucontext, vma, 2067 dev->mdev->clock_info_page, PAGE_SIZE); 2068 } 2069 2070 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2071 struct vm_area_struct *vma, 2072 struct mlx5_ib_ucontext *context) 2073 { 2074 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2075 int err; 2076 unsigned long idx; 2077 phys_addr_t pfn; 2078 pgprot_t prot; 2079 u32 bfreg_dyn_idx = 0; 2080 u32 uar_index; 2081 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2082 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2083 bfregi->num_static_sys_pages; 2084 2085 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2086 return -EINVAL; 2087 2088 if (dyn_uar) 2089 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2090 else 2091 idx = get_index(vma->vm_pgoff); 2092 2093 if (idx >= max_valid_idx) { 2094 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2095 idx, max_valid_idx); 2096 return -EINVAL; 2097 } 2098 2099 switch (cmd) { 2100 case MLX5_IB_MMAP_WC_PAGE: 2101 case MLX5_IB_MMAP_ALLOC_WC: 2102 /* Some architectures don't support WC memory */ 2103 #if defined(CONFIG_X86) 2104 if (!pat_enabled()) 2105 return -EPERM; 2106 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2107 return -EPERM; 2108 #endif 2109 /* fall through */ 2110 case MLX5_IB_MMAP_REGULAR_PAGE: 2111 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2112 prot = pgprot_writecombine(vma->vm_page_prot); 2113 break; 2114 case MLX5_IB_MMAP_NC_PAGE: 2115 prot = pgprot_noncached(vma->vm_page_prot); 2116 break; 2117 default: 2118 return -EINVAL; 2119 } 2120 2121 if (dyn_uar) { 2122 int uars_per_page; 2123 2124 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2125 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2126 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2127 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2128 bfreg_dyn_idx, bfregi->total_num_bfregs); 2129 return -EINVAL; 2130 } 2131 2132 mutex_lock(&bfregi->lock); 2133 /* Fail if uar already allocated, first bfreg index of each 2134 * page holds its count. 2135 */ 2136 if (bfregi->count[bfreg_dyn_idx]) { 2137 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2138 mutex_unlock(&bfregi->lock); 2139 return -EINVAL; 2140 } 2141 2142 bfregi->count[bfreg_dyn_idx]++; 2143 mutex_unlock(&bfregi->lock); 2144 2145 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2146 if (err) { 2147 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2148 goto free_bfreg; 2149 } 2150 } else { 2151 uar_index = bfregi->sys_pages[idx]; 2152 } 2153 2154 pfn = uar_index2pfn(dev, uar_index); 2155 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2156 2157 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2158 prot); 2159 if (err) { 2160 mlx5_ib_err(dev, 2161 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2162 err, mmap_cmd2str(cmd)); 2163 goto err; 2164 } 2165 2166 if (dyn_uar) 2167 bfregi->sys_pages[idx] = uar_index; 2168 return 0; 2169 2170 err: 2171 if (!dyn_uar) 2172 return err; 2173 2174 mlx5_cmd_free_uar(dev->mdev, idx); 2175 2176 free_bfreg: 2177 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2178 2179 return err; 2180 } 2181 2182 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2183 { 2184 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2185 struct mlx5_ib_dev *dev = to_mdev(context->device); 2186 u16 page_idx = get_extended_index(vma->vm_pgoff); 2187 size_t map_size = vma->vm_end - vma->vm_start; 2188 u32 npages = map_size >> PAGE_SHIFT; 2189 phys_addr_t pfn; 2190 2191 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2192 page_idx + npages) 2193 return -EINVAL; 2194 2195 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2196 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2197 PAGE_SHIFT) + 2198 page_idx; 2199 return rdma_user_mmap_io(context, vma, pfn, map_size, 2200 pgprot_writecombine(vma->vm_page_prot)); 2201 } 2202 2203 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2204 { 2205 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2206 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2207 unsigned long command; 2208 phys_addr_t pfn; 2209 2210 command = get_command(vma->vm_pgoff); 2211 switch (command) { 2212 case MLX5_IB_MMAP_WC_PAGE: 2213 case MLX5_IB_MMAP_NC_PAGE: 2214 case MLX5_IB_MMAP_REGULAR_PAGE: 2215 case MLX5_IB_MMAP_ALLOC_WC: 2216 return uar_mmap(dev, command, vma, context); 2217 2218 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2219 return -ENOSYS; 2220 2221 case MLX5_IB_MMAP_CORE_CLOCK: 2222 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2223 return -EINVAL; 2224 2225 if (vma->vm_flags & VM_WRITE) 2226 return -EPERM; 2227 2228 /* Don't expose to user-space information it shouldn't have */ 2229 if (PAGE_SIZE > 4096) 2230 return -EOPNOTSUPP; 2231 2232 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2233 pfn = (dev->mdev->iseg_base + 2234 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2235 PAGE_SHIFT; 2236 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2237 PAGE_SIZE, vma->vm_page_prot)) 2238 return -EAGAIN; 2239 break; 2240 case MLX5_IB_MMAP_CLOCK_INFO: 2241 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2242 2243 case MLX5_IB_MMAP_DEVICE_MEM: 2244 return dm_mmap(ibcontext, vma); 2245 2246 default: 2247 return -EINVAL; 2248 } 2249 2250 return 0; 2251 } 2252 2253 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2254 struct ib_ucontext *context, 2255 struct ib_dm_alloc_attr *attr, 2256 struct uverbs_attr_bundle *attrs) 2257 { 2258 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2259 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2260 phys_addr_t memic_addr; 2261 struct mlx5_ib_dm *dm; 2262 u64 start_offset; 2263 u32 page_idx; 2264 int err; 2265 2266 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2267 if (!dm) 2268 return ERR_PTR(-ENOMEM); 2269 2270 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2271 attr->length, act_size, attr->alignment); 2272 2273 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2274 act_size, attr->alignment); 2275 if (err) 2276 goto err_free; 2277 2278 start_offset = memic_addr & ~PAGE_MASK; 2279 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2280 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2281 PAGE_SHIFT; 2282 2283 err = uverbs_copy_to(attrs, 2284 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2285 &start_offset, sizeof(start_offset)); 2286 if (err) 2287 goto err_dealloc; 2288 2289 err = uverbs_copy_to(attrs, 2290 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2291 &page_idx, sizeof(page_idx)); 2292 if (err) 2293 goto err_dealloc; 2294 2295 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2296 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2297 2298 dm->dev_addr = memic_addr; 2299 2300 return &dm->ibdm; 2301 2302 err_dealloc: 2303 mlx5_cmd_dealloc_memic(memic, memic_addr, 2304 act_size); 2305 err_free: 2306 kfree(dm); 2307 return ERR_PTR(err); 2308 } 2309 2310 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2311 { 2312 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2313 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2314 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2315 u32 page_idx; 2316 int ret; 2317 2318 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2319 if (ret) 2320 return ret; 2321 2322 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2323 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2324 PAGE_SHIFT; 2325 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2326 page_idx, 2327 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2328 2329 kfree(dm); 2330 2331 return 0; 2332 } 2333 2334 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_ucontext *context, 2335 struct ib_udata *udata) 2336 { 2337 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2338 struct ib_device *ibdev = ibpd->device; 2339 struct mlx5_ib_alloc_pd_resp resp; 2340 int err; 2341 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2342 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2343 u16 uid = 0; 2344 2345 uid = context ? to_mucontext(context)->devx_uid : 0; 2346 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2347 MLX5_SET(alloc_pd_in, in, uid, uid); 2348 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in), 2349 out, sizeof(out)); 2350 if (err) 2351 return err; 2352 2353 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2354 pd->uid = uid; 2355 if (context) { 2356 resp.pdn = pd->pdn; 2357 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2358 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2359 return -EFAULT; 2360 } 2361 } 2362 2363 return 0; 2364 } 2365 2366 static void mlx5_ib_dealloc_pd(struct ib_pd *pd) 2367 { 2368 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2369 struct mlx5_ib_pd *mpd = to_mpd(pd); 2370 2371 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2372 } 2373 2374 enum { 2375 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2376 MATCH_CRITERIA_ENABLE_MISC_BIT, 2377 MATCH_CRITERIA_ENABLE_INNER_BIT, 2378 MATCH_CRITERIA_ENABLE_MISC2_BIT 2379 }; 2380 2381 #define HEADER_IS_ZERO(match_criteria, headers) \ 2382 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2383 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2384 2385 static u8 get_match_criteria_enable(u32 *match_criteria) 2386 { 2387 u8 match_criteria_enable; 2388 2389 match_criteria_enable = 2390 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2391 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2392 match_criteria_enable |= 2393 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2394 MATCH_CRITERIA_ENABLE_MISC_BIT; 2395 match_criteria_enable |= 2396 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2397 MATCH_CRITERIA_ENABLE_INNER_BIT; 2398 match_criteria_enable |= 2399 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2400 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2401 2402 return match_criteria_enable; 2403 } 2404 2405 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2406 { 2407 u8 entry_mask; 2408 u8 entry_val; 2409 int err = 0; 2410 2411 if (!mask) 2412 goto out; 2413 2414 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c, 2415 ip_protocol); 2416 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v, 2417 ip_protocol); 2418 if (!entry_mask) { 2419 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2420 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2421 goto out; 2422 } 2423 /* Don't override existing ip protocol */ 2424 if (mask != entry_mask || val != entry_val) 2425 err = -EINVAL; 2426 out: 2427 return err; 2428 } 2429 2430 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2431 bool inner) 2432 { 2433 if (inner) { 2434 MLX5_SET(fte_match_set_misc, 2435 misc_c, inner_ipv6_flow_label, mask); 2436 MLX5_SET(fte_match_set_misc, 2437 misc_v, inner_ipv6_flow_label, val); 2438 } else { 2439 MLX5_SET(fte_match_set_misc, 2440 misc_c, outer_ipv6_flow_label, mask); 2441 MLX5_SET(fte_match_set_misc, 2442 misc_v, outer_ipv6_flow_label, val); 2443 } 2444 } 2445 2446 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2447 { 2448 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2449 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2450 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2451 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2452 } 2453 2454 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2455 { 2456 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2457 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2458 return -EOPNOTSUPP; 2459 2460 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2461 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2462 return -EOPNOTSUPP; 2463 2464 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2465 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2466 return -EOPNOTSUPP; 2467 2468 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2469 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2470 return -EOPNOTSUPP; 2471 2472 return 0; 2473 } 2474 2475 #define LAST_ETH_FIELD vlan_tag 2476 #define LAST_IB_FIELD sl 2477 #define LAST_IPV4_FIELD tos 2478 #define LAST_IPV6_FIELD traffic_class 2479 #define LAST_TCP_UDP_FIELD src_port 2480 #define LAST_TUNNEL_FIELD tunnel_id 2481 #define LAST_FLOW_TAG_FIELD tag_id 2482 #define LAST_DROP_FIELD size 2483 #define LAST_COUNTERS_FIELD counters 2484 2485 /* Field is the last supported field */ 2486 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2487 memchr_inv((void *)&filter.field +\ 2488 sizeof(filter.field), 0,\ 2489 sizeof(filter) -\ 2490 offsetof(typeof(filter), field) -\ 2491 sizeof(filter.field)) 2492 2493 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2494 bool is_egress, 2495 struct mlx5_flow_act *action) 2496 { 2497 2498 switch (maction->ib_action.type) { 2499 case IB_FLOW_ACTION_ESP: 2500 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2501 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2502 return -EINVAL; 2503 /* Currently only AES_GCM keymat is supported by the driver */ 2504 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2505 action->action |= is_egress ? 2506 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2507 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2508 return 0; 2509 case IB_FLOW_ACTION_UNSPECIFIED: 2510 if (maction->flow_action_raw.sub_type == 2511 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2512 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2513 return -EINVAL; 2514 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2515 action->modify_id = maction->flow_action_raw.action_id; 2516 return 0; 2517 } 2518 if (maction->flow_action_raw.sub_type == 2519 MLX5_IB_FLOW_ACTION_DECAP) { 2520 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2521 return -EINVAL; 2522 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2523 return 0; 2524 } 2525 if (maction->flow_action_raw.sub_type == 2526 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2527 if (action->action & 2528 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2529 return -EINVAL; 2530 action->action |= 2531 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2532 action->reformat_id = 2533 maction->flow_action_raw.action_id; 2534 return 0; 2535 } 2536 /* fall through */ 2537 default: 2538 return -EOPNOTSUPP; 2539 } 2540 } 2541 2542 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2543 u32 *match_v, const union ib_flow_spec *ib_spec, 2544 const struct ib_flow_attr *flow_attr, 2545 struct mlx5_flow_act *action, u32 prev_type) 2546 { 2547 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2548 misc_parameters); 2549 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2550 misc_parameters); 2551 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2552 misc_parameters_2); 2553 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2554 misc_parameters_2); 2555 void *headers_c; 2556 void *headers_v; 2557 int match_ipv; 2558 int ret; 2559 2560 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2561 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2562 inner_headers); 2563 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2564 inner_headers); 2565 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2566 ft_field_support.inner_ip_version); 2567 } else { 2568 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2569 outer_headers); 2570 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2571 outer_headers); 2572 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2573 ft_field_support.outer_ip_version); 2574 } 2575 2576 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2577 case IB_FLOW_SPEC_ETH: 2578 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2579 return -EOPNOTSUPP; 2580 2581 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2582 dmac_47_16), 2583 ib_spec->eth.mask.dst_mac); 2584 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2585 dmac_47_16), 2586 ib_spec->eth.val.dst_mac); 2587 2588 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2589 smac_47_16), 2590 ib_spec->eth.mask.src_mac); 2591 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2592 smac_47_16), 2593 ib_spec->eth.val.src_mac); 2594 2595 if (ib_spec->eth.mask.vlan_tag) { 2596 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2597 cvlan_tag, 1); 2598 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2599 cvlan_tag, 1); 2600 2601 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2602 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2603 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2604 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2605 2606 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2607 first_cfi, 2608 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2609 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2610 first_cfi, 2611 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2612 2613 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2614 first_prio, 2615 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2617 first_prio, 2618 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2619 } 2620 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2621 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2623 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2624 break; 2625 case IB_FLOW_SPEC_IPV4: 2626 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2627 return -EOPNOTSUPP; 2628 2629 if (match_ipv) { 2630 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2631 ip_version, 0xf); 2632 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2633 ip_version, MLX5_FS_IPV4_VERSION); 2634 } else { 2635 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2636 ethertype, 0xffff); 2637 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2638 ethertype, ETH_P_IP); 2639 } 2640 2641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2642 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2643 &ib_spec->ipv4.mask.src_ip, 2644 sizeof(ib_spec->ipv4.mask.src_ip)); 2645 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2646 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2647 &ib_spec->ipv4.val.src_ip, 2648 sizeof(ib_spec->ipv4.val.src_ip)); 2649 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2650 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2651 &ib_spec->ipv4.mask.dst_ip, 2652 sizeof(ib_spec->ipv4.mask.dst_ip)); 2653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2654 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2655 &ib_spec->ipv4.val.dst_ip, 2656 sizeof(ib_spec->ipv4.val.dst_ip)); 2657 2658 set_tos(headers_c, headers_v, 2659 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2660 2661 if (set_proto(headers_c, headers_v, 2662 ib_spec->ipv4.mask.proto, 2663 ib_spec->ipv4.val.proto)) 2664 return -EINVAL; 2665 break; 2666 case IB_FLOW_SPEC_IPV6: 2667 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2668 return -EOPNOTSUPP; 2669 2670 if (match_ipv) { 2671 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2672 ip_version, 0xf); 2673 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2674 ip_version, MLX5_FS_IPV6_VERSION); 2675 } else { 2676 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2677 ethertype, 0xffff); 2678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2679 ethertype, ETH_P_IPV6); 2680 } 2681 2682 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2683 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2684 &ib_spec->ipv6.mask.src_ip, 2685 sizeof(ib_spec->ipv6.mask.src_ip)); 2686 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2687 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2688 &ib_spec->ipv6.val.src_ip, 2689 sizeof(ib_spec->ipv6.val.src_ip)); 2690 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2691 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2692 &ib_spec->ipv6.mask.dst_ip, 2693 sizeof(ib_spec->ipv6.mask.dst_ip)); 2694 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2695 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2696 &ib_spec->ipv6.val.dst_ip, 2697 sizeof(ib_spec->ipv6.val.dst_ip)); 2698 2699 set_tos(headers_c, headers_v, 2700 ib_spec->ipv6.mask.traffic_class, 2701 ib_spec->ipv6.val.traffic_class); 2702 2703 if (set_proto(headers_c, headers_v, 2704 ib_spec->ipv6.mask.next_hdr, 2705 ib_spec->ipv6.val.next_hdr)) 2706 return -EINVAL; 2707 2708 set_flow_label(misc_params_c, misc_params_v, 2709 ntohl(ib_spec->ipv6.mask.flow_label), 2710 ntohl(ib_spec->ipv6.val.flow_label), 2711 ib_spec->type & IB_FLOW_SPEC_INNER); 2712 break; 2713 case IB_FLOW_SPEC_ESP: 2714 if (ib_spec->esp.mask.seq) 2715 return -EOPNOTSUPP; 2716 2717 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2718 ntohl(ib_spec->esp.mask.spi)); 2719 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2720 ntohl(ib_spec->esp.val.spi)); 2721 break; 2722 case IB_FLOW_SPEC_TCP: 2723 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2724 LAST_TCP_UDP_FIELD)) 2725 return -EOPNOTSUPP; 2726 2727 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP)) 2728 return -EINVAL; 2729 2730 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2731 ntohs(ib_spec->tcp_udp.mask.src_port)); 2732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2733 ntohs(ib_spec->tcp_udp.val.src_port)); 2734 2735 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2736 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2738 ntohs(ib_spec->tcp_udp.val.dst_port)); 2739 break; 2740 case IB_FLOW_SPEC_UDP: 2741 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2742 LAST_TCP_UDP_FIELD)) 2743 return -EOPNOTSUPP; 2744 2745 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP)) 2746 return -EINVAL; 2747 2748 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2749 ntohs(ib_spec->tcp_udp.mask.src_port)); 2750 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2751 ntohs(ib_spec->tcp_udp.val.src_port)); 2752 2753 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2754 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2755 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2756 ntohs(ib_spec->tcp_udp.val.dst_port)); 2757 break; 2758 case IB_FLOW_SPEC_GRE: 2759 if (ib_spec->gre.mask.c_ks_res0_ver) 2760 return -EOPNOTSUPP; 2761 2762 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE)) 2763 return -EINVAL; 2764 2765 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2766 0xff); 2767 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2768 IPPROTO_GRE); 2769 2770 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2771 ntohs(ib_spec->gre.mask.protocol)); 2772 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2773 ntohs(ib_spec->gre.val.protocol)); 2774 2775 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2776 gre_key.nvgre.hi), 2777 &ib_spec->gre.mask.key, 2778 sizeof(ib_spec->gre.mask.key)); 2779 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2780 gre_key.nvgre.hi), 2781 &ib_spec->gre.val.key, 2782 sizeof(ib_spec->gre.val.key)); 2783 break; 2784 case IB_FLOW_SPEC_MPLS: 2785 switch (prev_type) { 2786 case IB_FLOW_SPEC_UDP: 2787 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2788 ft_field_support.outer_first_mpls_over_udp), 2789 &ib_spec->mpls.mask.tag)) 2790 return -EOPNOTSUPP; 2791 2792 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2793 outer_first_mpls_over_udp), 2794 &ib_spec->mpls.val.tag, 2795 sizeof(ib_spec->mpls.val.tag)); 2796 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2797 outer_first_mpls_over_udp), 2798 &ib_spec->mpls.mask.tag, 2799 sizeof(ib_spec->mpls.mask.tag)); 2800 break; 2801 case IB_FLOW_SPEC_GRE: 2802 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2803 ft_field_support.outer_first_mpls_over_gre), 2804 &ib_spec->mpls.mask.tag)) 2805 return -EOPNOTSUPP; 2806 2807 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2808 outer_first_mpls_over_gre), 2809 &ib_spec->mpls.val.tag, 2810 sizeof(ib_spec->mpls.val.tag)); 2811 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2812 outer_first_mpls_over_gre), 2813 &ib_spec->mpls.mask.tag, 2814 sizeof(ib_spec->mpls.mask.tag)); 2815 break; 2816 default: 2817 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2818 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2819 ft_field_support.inner_first_mpls), 2820 &ib_spec->mpls.mask.tag)) 2821 return -EOPNOTSUPP; 2822 2823 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2824 inner_first_mpls), 2825 &ib_spec->mpls.val.tag, 2826 sizeof(ib_spec->mpls.val.tag)); 2827 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2828 inner_first_mpls), 2829 &ib_spec->mpls.mask.tag, 2830 sizeof(ib_spec->mpls.mask.tag)); 2831 } else { 2832 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2833 ft_field_support.outer_first_mpls), 2834 &ib_spec->mpls.mask.tag)) 2835 return -EOPNOTSUPP; 2836 2837 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2838 outer_first_mpls), 2839 &ib_spec->mpls.val.tag, 2840 sizeof(ib_spec->mpls.val.tag)); 2841 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2842 outer_first_mpls), 2843 &ib_spec->mpls.mask.tag, 2844 sizeof(ib_spec->mpls.mask.tag)); 2845 } 2846 } 2847 break; 2848 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2849 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2850 LAST_TUNNEL_FIELD)) 2851 return -EOPNOTSUPP; 2852 2853 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2854 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2855 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2856 ntohl(ib_spec->tunnel.val.tunnel_id)); 2857 break; 2858 case IB_FLOW_SPEC_ACTION_TAG: 2859 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2860 LAST_FLOW_TAG_FIELD)) 2861 return -EOPNOTSUPP; 2862 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2863 return -EINVAL; 2864 2865 action->flow_tag = ib_spec->flow_tag.tag_id; 2866 action->flags |= FLOW_ACT_HAS_TAG; 2867 break; 2868 case IB_FLOW_SPEC_ACTION_DROP: 2869 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2870 LAST_DROP_FIELD)) 2871 return -EOPNOTSUPP; 2872 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2873 break; 2874 case IB_FLOW_SPEC_ACTION_HANDLE: 2875 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 2876 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 2877 if (ret) 2878 return ret; 2879 break; 2880 case IB_FLOW_SPEC_ACTION_COUNT: 2881 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2882 LAST_COUNTERS_FIELD)) 2883 return -EOPNOTSUPP; 2884 2885 /* for now support only one counters spec per flow */ 2886 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2887 return -EINVAL; 2888 2889 action->counters = ib_spec->flow_count.counters; 2890 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2891 break; 2892 default: 2893 return -EINVAL; 2894 } 2895 2896 return 0; 2897 } 2898 2899 /* If a flow could catch both multicast and unicast packets, 2900 * it won't fall into the multicast flow steering table and this rule 2901 * could steal other multicast packets. 2902 */ 2903 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2904 { 2905 union ib_flow_spec *flow_spec; 2906 2907 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2908 ib_attr->num_of_specs < 1) 2909 return false; 2910 2911 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2912 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2913 struct ib_flow_spec_ipv4 *ipv4_spec; 2914 2915 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2916 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2917 return true; 2918 2919 return false; 2920 } 2921 2922 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2923 struct ib_flow_spec_eth *eth_spec; 2924 2925 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2926 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2927 is_multicast_ether_addr(eth_spec->val.dst_mac); 2928 } 2929 2930 return false; 2931 } 2932 2933 enum valid_spec { 2934 VALID_SPEC_INVALID, 2935 VALID_SPEC_VALID, 2936 VALID_SPEC_NA, 2937 }; 2938 2939 static enum valid_spec 2940 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2941 const struct mlx5_flow_spec *spec, 2942 const struct mlx5_flow_act *flow_act, 2943 bool egress) 2944 { 2945 const u32 *match_c = spec->match_criteria; 2946 bool is_crypto = 2947 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2948 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2949 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2950 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2951 2952 /* 2953 * Currently only crypto is supported in egress, when regular egress 2954 * rules would be supported, always return VALID_SPEC_NA. 2955 */ 2956 if (!is_crypto) 2957 return VALID_SPEC_NA; 2958 2959 return is_crypto && is_ipsec && 2960 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ? 2961 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2962 } 2963 2964 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2965 const struct mlx5_flow_spec *spec, 2966 const struct mlx5_flow_act *flow_act, 2967 bool egress) 2968 { 2969 /* We curretly only support ipsec egress flow */ 2970 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2971 } 2972 2973 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2974 const struct ib_flow_attr *flow_attr, 2975 bool check_inner) 2976 { 2977 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2978 int match_ipv = check_inner ? 2979 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2980 ft_field_support.inner_ip_version) : 2981 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2982 ft_field_support.outer_ip_version); 2983 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2984 bool ipv4_spec_valid, ipv6_spec_valid; 2985 unsigned int ip_spec_type = 0; 2986 bool has_ethertype = false; 2987 unsigned int spec_index; 2988 bool mask_valid = true; 2989 u16 eth_type = 0; 2990 bool type_valid; 2991 2992 /* Validate that ethertype is correct */ 2993 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2994 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2995 ib_spec->eth.mask.ether_type) { 2996 mask_valid = (ib_spec->eth.mask.ether_type == 2997 htons(0xffff)); 2998 has_ethertype = true; 2999 eth_type = ntohs(ib_spec->eth.val.ether_type); 3000 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 3001 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 3002 ip_spec_type = ib_spec->type; 3003 } 3004 ib_spec = (void *)ib_spec + ib_spec->size; 3005 } 3006 3007 type_valid = (!has_ethertype) || (!ip_spec_type); 3008 if (!type_valid && mask_valid) { 3009 ipv4_spec_valid = (eth_type == ETH_P_IP) && 3010 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 3011 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 3012 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 3013 3014 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 3015 (((eth_type == ETH_P_MPLS_UC) || 3016 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 3017 } 3018 3019 return type_valid; 3020 } 3021 3022 static bool is_valid_attr(struct mlx5_core_dev *mdev, 3023 const struct ib_flow_attr *flow_attr) 3024 { 3025 return is_valid_ethertype(mdev, flow_attr, false) && 3026 is_valid_ethertype(mdev, flow_attr, true); 3027 } 3028 3029 static void put_flow_table(struct mlx5_ib_dev *dev, 3030 struct mlx5_ib_flow_prio *prio, bool ft_added) 3031 { 3032 prio->refcount -= !!ft_added; 3033 if (!prio->refcount) { 3034 mlx5_destroy_flow_table(prio->flow_table); 3035 prio->flow_table = NULL; 3036 } 3037 } 3038 3039 static void counters_clear_description(struct ib_counters *counters) 3040 { 3041 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3042 3043 mutex_lock(&mcounters->mcntrs_mutex); 3044 kfree(mcounters->counters_data); 3045 mcounters->counters_data = NULL; 3046 mcounters->cntrs_max_index = 0; 3047 mutex_unlock(&mcounters->mcntrs_mutex); 3048 } 3049 3050 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 3051 { 3052 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 3053 struct mlx5_ib_flow_handler, 3054 ibflow); 3055 struct mlx5_ib_flow_handler *iter, *tmp; 3056 struct mlx5_ib_dev *dev = handler->dev; 3057 3058 mutex_lock(&dev->flow_db->lock); 3059 3060 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 3061 mlx5_del_flow_rules(iter->rule); 3062 put_flow_table(dev, iter->prio, true); 3063 list_del(&iter->list); 3064 kfree(iter); 3065 } 3066 3067 mlx5_del_flow_rules(handler->rule); 3068 put_flow_table(dev, handler->prio, true); 3069 if (handler->ibcounters && 3070 atomic_read(&handler->ibcounters->usecnt) == 1) 3071 counters_clear_description(handler->ibcounters); 3072 3073 mutex_unlock(&dev->flow_db->lock); 3074 if (handler->flow_matcher) 3075 atomic_dec(&handler->flow_matcher->usecnt); 3076 kfree(handler); 3077 3078 return 0; 3079 } 3080 3081 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 3082 { 3083 priority *= 2; 3084 if (!dont_trap) 3085 priority++; 3086 return priority; 3087 } 3088 3089 enum flow_table_type { 3090 MLX5_IB_FT_RX, 3091 MLX5_IB_FT_TX 3092 }; 3093 3094 #define MLX5_FS_MAX_TYPES 6 3095 #define MLX5_FS_MAX_ENTRIES BIT(16) 3096 3097 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3098 struct mlx5_ib_flow_prio *prio, 3099 int priority, 3100 int num_entries, int num_groups, 3101 u32 flags) 3102 { 3103 struct mlx5_flow_table *ft; 3104 3105 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3106 num_entries, 3107 num_groups, 3108 0, flags); 3109 if (IS_ERR(ft)) 3110 return ERR_CAST(ft); 3111 3112 prio->flow_table = ft; 3113 prio->refcount = 0; 3114 return prio; 3115 } 3116 3117 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3118 struct ib_flow_attr *flow_attr, 3119 enum flow_table_type ft_type) 3120 { 3121 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3122 struct mlx5_flow_namespace *ns = NULL; 3123 struct mlx5_ib_flow_prio *prio; 3124 struct mlx5_flow_table *ft; 3125 int max_table_size; 3126 int num_entries; 3127 int num_groups; 3128 u32 flags = 0; 3129 int priority; 3130 3131 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3132 log_max_ft_size)); 3133 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3134 enum mlx5_flow_namespace_type fn_type; 3135 3136 if (flow_is_multicast_only(flow_attr) && 3137 !dont_trap) 3138 priority = MLX5_IB_FLOW_MCAST_PRIO; 3139 else 3140 priority = ib_prio_to_core_prio(flow_attr->priority, 3141 dont_trap); 3142 if (ft_type == MLX5_IB_FT_RX) { 3143 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3144 prio = &dev->flow_db->prios[priority]; 3145 if (!dev->rep && 3146 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3147 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3148 if (!dev->rep && 3149 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3150 reformat_l3_tunnel_to_l2)) 3151 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3152 } else { 3153 max_table_size = 3154 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3155 log_max_ft_size)); 3156 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3157 prio = &dev->flow_db->egress_prios[priority]; 3158 if (!dev->rep && 3159 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3160 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3161 } 3162 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3163 num_entries = MLX5_FS_MAX_ENTRIES; 3164 num_groups = MLX5_FS_MAX_TYPES; 3165 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3166 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3167 ns = mlx5_get_flow_namespace(dev->mdev, 3168 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3169 build_leftovers_ft_param(&priority, 3170 &num_entries, 3171 &num_groups); 3172 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3173 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3174 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3175 allow_sniffer_and_nic_rx_shared_tir)) 3176 return ERR_PTR(-ENOTSUPP); 3177 3178 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3179 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3180 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3181 3182 prio = &dev->flow_db->sniffer[ft_type]; 3183 priority = 0; 3184 num_entries = 1; 3185 num_groups = 1; 3186 } 3187 3188 if (!ns) 3189 return ERR_PTR(-ENOTSUPP); 3190 3191 if (num_entries > max_table_size) 3192 return ERR_PTR(-ENOMEM); 3193 3194 ft = prio->flow_table; 3195 if (!ft) 3196 return _get_prio(ns, prio, priority, num_entries, num_groups, 3197 flags); 3198 3199 return prio; 3200 } 3201 3202 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3203 struct mlx5_flow_spec *spec, 3204 u32 underlay_qpn) 3205 { 3206 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3207 spec->match_criteria, 3208 misc_parameters); 3209 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3210 misc_parameters); 3211 3212 if (underlay_qpn && 3213 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3214 ft_field_support.bth_dst_qp)) { 3215 MLX5_SET(fte_match_set_misc, 3216 misc_params_v, bth_dst_qp, underlay_qpn); 3217 MLX5_SET(fte_match_set_misc, 3218 misc_params_c, bth_dst_qp, 0xffffff); 3219 } 3220 } 3221 3222 static int read_flow_counters(struct ib_device *ibdev, 3223 struct mlx5_read_counters_attr *read_attr) 3224 { 3225 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3226 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3227 3228 return mlx5_fc_query(dev->mdev, fc, 3229 &read_attr->out[IB_COUNTER_PACKETS], 3230 &read_attr->out[IB_COUNTER_BYTES]); 3231 } 3232 3233 /* flow counters currently expose two counters packets and bytes */ 3234 #define FLOW_COUNTERS_NUM 2 3235 static int counters_set_description(struct ib_counters *counters, 3236 enum mlx5_ib_counters_type counters_type, 3237 struct mlx5_ib_flow_counters_desc *desc_data, 3238 u32 ncounters) 3239 { 3240 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3241 u32 cntrs_max_index = 0; 3242 int i; 3243 3244 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3245 return -EINVAL; 3246 3247 /* init the fields for the object */ 3248 mcounters->type = counters_type; 3249 mcounters->read_counters = read_flow_counters; 3250 mcounters->counters_num = FLOW_COUNTERS_NUM; 3251 mcounters->ncounters = ncounters; 3252 /* each counter entry have both description and index pair */ 3253 for (i = 0; i < ncounters; i++) { 3254 if (desc_data[i].description > IB_COUNTER_BYTES) 3255 return -EINVAL; 3256 3257 if (cntrs_max_index <= desc_data[i].index) 3258 cntrs_max_index = desc_data[i].index + 1; 3259 } 3260 3261 mutex_lock(&mcounters->mcntrs_mutex); 3262 mcounters->counters_data = desc_data; 3263 mcounters->cntrs_max_index = cntrs_max_index; 3264 mutex_unlock(&mcounters->mcntrs_mutex); 3265 3266 return 0; 3267 } 3268 3269 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3270 static int flow_counters_set_data(struct ib_counters *ibcounters, 3271 struct mlx5_ib_create_flow *ucmd) 3272 { 3273 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3274 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3275 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3276 bool hw_hndl = false; 3277 int ret = 0; 3278 3279 if (ucmd && ucmd->ncounters_data != 0) { 3280 cntrs_data = ucmd->data; 3281 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3282 return -EINVAL; 3283 3284 desc_data = kcalloc(cntrs_data->ncounters, 3285 sizeof(*desc_data), 3286 GFP_KERNEL); 3287 if (!desc_data) 3288 return -ENOMEM; 3289 3290 if (copy_from_user(desc_data, 3291 u64_to_user_ptr(cntrs_data->counters_data), 3292 sizeof(*desc_data) * cntrs_data->ncounters)) { 3293 ret = -EFAULT; 3294 goto free; 3295 } 3296 } 3297 3298 if (!mcounters->hw_cntrs_hndl) { 3299 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3300 to_mdev(ibcounters->device)->mdev, false); 3301 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3302 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3303 goto free; 3304 } 3305 hw_hndl = true; 3306 } 3307 3308 if (desc_data) { 3309 /* counters already bound to at least one flow */ 3310 if (mcounters->cntrs_max_index) { 3311 ret = -EINVAL; 3312 goto free_hndl; 3313 } 3314 3315 ret = counters_set_description(ibcounters, 3316 MLX5_IB_COUNTERS_FLOW, 3317 desc_data, 3318 cntrs_data->ncounters); 3319 if (ret) 3320 goto free_hndl; 3321 3322 } else if (!mcounters->cntrs_max_index) { 3323 /* counters not bound yet, must have udata passed */ 3324 ret = -EINVAL; 3325 goto free_hndl; 3326 } 3327 3328 return 0; 3329 3330 free_hndl: 3331 if (hw_hndl) { 3332 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3333 mcounters->hw_cntrs_hndl); 3334 mcounters->hw_cntrs_hndl = NULL; 3335 } 3336 free: 3337 kfree(desc_data); 3338 return ret; 3339 } 3340 3341 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3342 struct mlx5_ib_flow_prio *ft_prio, 3343 const struct ib_flow_attr *flow_attr, 3344 struct mlx5_flow_destination *dst, 3345 u32 underlay_qpn, 3346 struct mlx5_ib_create_flow *ucmd) 3347 { 3348 struct mlx5_flow_table *ft = ft_prio->flow_table; 3349 struct mlx5_ib_flow_handler *handler; 3350 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3351 struct mlx5_flow_spec *spec; 3352 struct mlx5_flow_destination dest_arr[2] = {}; 3353 struct mlx5_flow_destination *rule_dst = dest_arr; 3354 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3355 unsigned int spec_index; 3356 u32 prev_type = 0; 3357 int err = 0; 3358 int dest_num = 0; 3359 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3360 3361 if (!is_valid_attr(dev->mdev, flow_attr)) 3362 return ERR_PTR(-EINVAL); 3363 3364 if (dev->rep && is_egress) 3365 return ERR_PTR(-EINVAL); 3366 3367 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3368 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3369 if (!handler || !spec) { 3370 err = -ENOMEM; 3371 goto free; 3372 } 3373 3374 INIT_LIST_HEAD(&handler->list); 3375 if (dst) { 3376 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3377 dest_num++; 3378 } 3379 3380 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3381 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3382 spec->match_value, 3383 ib_flow, flow_attr, &flow_act, 3384 prev_type); 3385 if (err < 0) 3386 goto free; 3387 3388 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3389 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3390 } 3391 3392 if (!flow_is_multicast_only(flow_attr)) 3393 set_underlay_qp(dev, spec, underlay_qpn); 3394 3395 if (dev->rep) { 3396 void *misc; 3397 3398 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3399 misc_parameters); 3400 MLX5_SET(fte_match_set_misc, misc, source_port, 3401 dev->rep->vport); 3402 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3403 misc_parameters); 3404 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3405 } 3406 3407 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3408 3409 if (is_egress && 3410 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3411 err = -EINVAL; 3412 goto free; 3413 } 3414 3415 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3416 struct mlx5_ib_mcounters *mcounters; 3417 3418 err = flow_counters_set_data(flow_act.counters, ucmd); 3419 if (err) 3420 goto free; 3421 3422 mcounters = to_mcounters(flow_act.counters); 3423 handler->ibcounters = flow_act.counters; 3424 dest_arr[dest_num].type = 3425 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3426 dest_arr[dest_num].counter_id = 3427 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3428 dest_num++; 3429 } 3430 3431 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3432 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3433 rule_dst = NULL; 3434 dest_num = 0; 3435 } 3436 } else { 3437 if (is_egress) 3438 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3439 else 3440 flow_act.action |= 3441 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3442 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3443 } 3444 3445 if ((flow_act.flags & FLOW_ACT_HAS_TAG) && 3446 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3447 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3448 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3449 flow_act.flow_tag, flow_attr->type); 3450 err = -EINVAL; 3451 goto free; 3452 } 3453 handler->rule = mlx5_add_flow_rules(ft, spec, 3454 &flow_act, 3455 rule_dst, dest_num); 3456 3457 if (IS_ERR(handler->rule)) { 3458 err = PTR_ERR(handler->rule); 3459 goto free; 3460 } 3461 3462 ft_prio->refcount++; 3463 handler->prio = ft_prio; 3464 handler->dev = dev; 3465 3466 ft_prio->flow_table = ft; 3467 free: 3468 if (err && handler) { 3469 if (handler->ibcounters && 3470 atomic_read(&handler->ibcounters->usecnt) == 1) 3471 counters_clear_description(handler->ibcounters); 3472 kfree(handler); 3473 } 3474 kvfree(spec); 3475 return err ? ERR_PTR(err) : handler; 3476 } 3477 3478 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3479 struct mlx5_ib_flow_prio *ft_prio, 3480 const struct ib_flow_attr *flow_attr, 3481 struct mlx5_flow_destination *dst) 3482 { 3483 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3484 } 3485 3486 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3487 struct mlx5_ib_flow_prio *ft_prio, 3488 struct ib_flow_attr *flow_attr, 3489 struct mlx5_flow_destination *dst) 3490 { 3491 struct mlx5_ib_flow_handler *handler_dst = NULL; 3492 struct mlx5_ib_flow_handler *handler = NULL; 3493 3494 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3495 if (!IS_ERR(handler)) { 3496 handler_dst = create_flow_rule(dev, ft_prio, 3497 flow_attr, dst); 3498 if (IS_ERR(handler_dst)) { 3499 mlx5_del_flow_rules(handler->rule); 3500 ft_prio->refcount--; 3501 kfree(handler); 3502 handler = handler_dst; 3503 } else { 3504 list_add(&handler_dst->list, &handler->list); 3505 } 3506 } 3507 3508 return handler; 3509 } 3510 enum { 3511 LEFTOVERS_MC, 3512 LEFTOVERS_UC, 3513 }; 3514 3515 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3516 struct mlx5_ib_flow_prio *ft_prio, 3517 struct ib_flow_attr *flow_attr, 3518 struct mlx5_flow_destination *dst) 3519 { 3520 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3521 struct mlx5_ib_flow_handler *handler = NULL; 3522 3523 static struct { 3524 struct ib_flow_attr flow_attr; 3525 struct ib_flow_spec_eth eth_flow; 3526 } leftovers_specs[] = { 3527 [LEFTOVERS_MC] = { 3528 .flow_attr = { 3529 .num_of_specs = 1, 3530 .size = sizeof(leftovers_specs[0]) 3531 }, 3532 .eth_flow = { 3533 .type = IB_FLOW_SPEC_ETH, 3534 .size = sizeof(struct ib_flow_spec_eth), 3535 .mask = {.dst_mac = {0x1} }, 3536 .val = {.dst_mac = {0x1} } 3537 } 3538 }, 3539 [LEFTOVERS_UC] = { 3540 .flow_attr = { 3541 .num_of_specs = 1, 3542 .size = sizeof(leftovers_specs[0]) 3543 }, 3544 .eth_flow = { 3545 .type = IB_FLOW_SPEC_ETH, 3546 .size = sizeof(struct ib_flow_spec_eth), 3547 .mask = {.dst_mac = {0x1} }, 3548 .val = {.dst_mac = {} } 3549 } 3550 } 3551 }; 3552 3553 handler = create_flow_rule(dev, ft_prio, 3554 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3555 dst); 3556 if (!IS_ERR(handler) && 3557 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3558 handler_ucast = create_flow_rule(dev, ft_prio, 3559 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3560 dst); 3561 if (IS_ERR(handler_ucast)) { 3562 mlx5_del_flow_rules(handler->rule); 3563 ft_prio->refcount--; 3564 kfree(handler); 3565 handler = handler_ucast; 3566 } else { 3567 list_add(&handler_ucast->list, &handler->list); 3568 } 3569 } 3570 3571 return handler; 3572 } 3573 3574 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3575 struct mlx5_ib_flow_prio *ft_rx, 3576 struct mlx5_ib_flow_prio *ft_tx, 3577 struct mlx5_flow_destination *dst) 3578 { 3579 struct mlx5_ib_flow_handler *handler_rx; 3580 struct mlx5_ib_flow_handler *handler_tx; 3581 int err; 3582 static const struct ib_flow_attr flow_attr = { 3583 .num_of_specs = 0, 3584 .size = sizeof(flow_attr) 3585 }; 3586 3587 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3588 if (IS_ERR(handler_rx)) { 3589 err = PTR_ERR(handler_rx); 3590 goto err; 3591 } 3592 3593 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3594 if (IS_ERR(handler_tx)) { 3595 err = PTR_ERR(handler_tx); 3596 goto err_tx; 3597 } 3598 3599 list_add(&handler_tx->list, &handler_rx->list); 3600 3601 return handler_rx; 3602 3603 err_tx: 3604 mlx5_del_flow_rules(handler_rx->rule); 3605 ft_rx->refcount--; 3606 kfree(handler_rx); 3607 err: 3608 return ERR_PTR(err); 3609 } 3610 3611 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3612 struct ib_flow_attr *flow_attr, 3613 int domain, 3614 struct ib_udata *udata) 3615 { 3616 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3617 struct mlx5_ib_qp *mqp = to_mqp(qp); 3618 struct mlx5_ib_flow_handler *handler = NULL; 3619 struct mlx5_flow_destination *dst = NULL; 3620 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3621 struct mlx5_ib_flow_prio *ft_prio; 3622 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3623 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3624 size_t min_ucmd_sz, required_ucmd_sz; 3625 int err; 3626 int underlay_qpn; 3627 3628 if (udata && udata->inlen) { 3629 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3630 sizeof(ucmd_hdr.reserved); 3631 if (udata->inlen < min_ucmd_sz) 3632 return ERR_PTR(-EOPNOTSUPP); 3633 3634 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3635 if (err) 3636 return ERR_PTR(err); 3637 3638 /* currently supports only one counters data */ 3639 if (ucmd_hdr.ncounters_data > 1) 3640 return ERR_PTR(-EINVAL); 3641 3642 required_ucmd_sz = min_ucmd_sz + 3643 sizeof(struct mlx5_ib_flow_counters_data) * 3644 ucmd_hdr.ncounters_data; 3645 if (udata->inlen > required_ucmd_sz && 3646 !ib_is_udata_cleared(udata, required_ucmd_sz, 3647 udata->inlen - required_ucmd_sz)) 3648 return ERR_PTR(-EOPNOTSUPP); 3649 3650 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3651 if (!ucmd) 3652 return ERR_PTR(-ENOMEM); 3653 3654 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3655 if (err) 3656 goto free_ucmd; 3657 } 3658 3659 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3660 err = -ENOMEM; 3661 goto free_ucmd; 3662 } 3663 3664 if (domain != IB_FLOW_DOMAIN_USER || 3665 flow_attr->port > dev->num_ports || 3666 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3667 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3668 err = -EINVAL; 3669 goto free_ucmd; 3670 } 3671 3672 if (is_egress && 3673 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3674 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3675 err = -EINVAL; 3676 goto free_ucmd; 3677 } 3678 3679 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3680 if (!dst) { 3681 err = -ENOMEM; 3682 goto free_ucmd; 3683 } 3684 3685 mutex_lock(&dev->flow_db->lock); 3686 3687 ft_prio = get_flow_table(dev, flow_attr, 3688 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3689 if (IS_ERR(ft_prio)) { 3690 err = PTR_ERR(ft_prio); 3691 goto unlock; 3692 } 3693 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3694 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3695 if (IS_ERR(ft_prio_tx)) { 3696 err = PTR_ERR(ft_prio_tx); 3697 ft_prio_tx = NULL; 3698 goto destroy_ft; 3699 } 3700 } 3701 3702 if (is_egress) { 3703 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3704 } else { 3705 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3706 if (mqp->flags & MLX5_IB_QP_RSS) 3707 dst->tir_num = mqp->rss_qp.tirn; 3708 else 3709 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3710 } 3711 3712 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3713 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3714 handler = create_dont_trap_rule(dev, ft_prio, 3715 flow_attr, dst); 3716 } else { 3717 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3718 mqp->underlay_qpn : 0; 3719 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3720 dst, underlay_qpn, ucmd); 3721 } 3722 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3723 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3724 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3725 dst); 3726 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3727 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3728 } else { 3729 err = -EINVAL; 3730 goto destroy_ft; 3731 } 3732 3733 if (IS_ERR(handler)) { 3734 err = PTR_ERR(handler); 3735 handler = NULL; 3736 goto destroy_ft; 3737 } 3738 3739 mutex_unlock(&dev->flow_db->lock); 3740 kfree(dst); 3741 kfree(ucmd); 3742 3743 return &handler->ibflow; 3744 3745 destroy_ft: 3746 put_flow_table(dev, ft_prio, false); 3747 if (ft_prio_tx) 3748 put_flow_table(dev, ft_prio_tx, false); 3749 unlock: 3750 mutex_unlock(&dev->flow_db->lock); 3751 kfree(dst); 3752 free_ucmd: 3753 kfree(ucmd); 3754 return ERR_PTR(err); 3755 } 3756 3757 static struct mlx5_ib_flow_prio * 3758 _get_flow_table(struct mlx5_ib_dev *dev, 3759 struct mlx5_ib_flow_matcher *fs_matcher, 3760 bool mcast) 3761 { 3762 struct mlx5_flow_namespace *ns = NULL; 3763 struct mlx5_ib_flow_prio *prio; 3764 int max_table_size; 3765 u32 flags = 0; 3766 int priority; 3767 3768 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3769 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3770 log_max_ft_size)); 3771 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3772 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3773 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3774 reformat_l3_tunnel_to_l2)) 3775 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3776 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */ 3777 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3778 log_max_ft_size)); 3779 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3780 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3781 } 3782 3783 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3784 return ERR_PTR(-ENOMEM); 3785 3786 if (mcast) 3787 priority = MLX5_IB_FLOW_MCAST_PRIO; 3788 else 3789 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3790 3791 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3792 if (!ns) 3793 return ERR_PTR(-ENOTSUPP); 3794 3795 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3796 prio = &dev->flow_db->prios[priority]; 3797 else 3798 prio = &dev->flow_db->egress_prios[priority]; 3799 3800 if (prio->flow_table) 3801 return prio; 3802 3803 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3804 MLX5_FS_MAX_TYPES, flags); 3805 } 3806 3807 static struct mlx5_ib_flow_handler * 3808 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3809 struct mlx5_ib_flow_prio *ft_prio, 3810 struct mlx5_flow_destination *dst, 3811 struct mlx5_ib_flow_matcher *fs_matcher, 3812 struct mlx5_flow_act *flow_act, 3813 void *cmd_in, int inlen, 3814 int dst_num) 3815 { 3816 struct mlx5_ib_flow_handler *handler; 3817 struct mlx5_flow_spec *spec; 3818 struct mlx5_flow_table *ft = ft_prio->flow_table; 3819 int err = 0; 3820 3821 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3822 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3823 if (!handler || !spec) { 3824 err = -ENOMEM; 3825 goto free; 3826 } 3827 3828 INIT_LIST_HEAD(&handler->list); 3829 3830 memcpy(spec->match_value, cmd_in, inlen); 3831 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3832 fs_matcher->mask_len); 3833 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3834 3835 handler->rule = mlx5_add_flow_rules(ft, spec, 3836 flow_act, dst, dst_num); 3837 3838 if (IS_ERR(handler->rule)) { 3839 err = PTR_ERR(handler->rule); 3840 goto free; 3841 } 3842 3843 ft_prio->refcount++; 3844 handler->prio = ft_prio; 3845 handler->dev = dev; 3846 ft_prio->flow_table = ft; 3847 3848 free: 3849 if (err) 3850 kfree(handler); 3851 kvfree(spec); 3852 return err ? ERR_PTR(err) : handler; 3853 } 3854 3855 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3856 void *match_v) 3857 { 3858 void *match_c; 3859 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3860 void *dmac, *dmac_mask; 3861 void *ipv4, *ipv4_mask; 3862 3863 if (!(fs_matcher->match_criteria_enable & 3864 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3865 return false; 3866 3867 match_c = fs_matcher->matcher_mask.match_params; 3868 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3869 outer_headers); 3870 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3871 outer_headers); 3872 3873 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3874 dmac_47_16); 3875 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3876 dmac_47_16); 3877 3878 if (is_multicast_ether_addr(dmac) && 3879 is_multicast_ether_addr(dmac_mask)) 3880 return true; 3881 3882 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3883 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3884 3885 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3886 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3887 3888 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3889 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3890 return true; 3891 3892 return false; 3893 } 3894 3895 struct mlx5_ib_flow_handler * 3896 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3897 struct mlx5_ib_flow_matcher *fs_matcher, 3898 struct mlx5_flow_act *flow_act, 3899 u32 counter_id, 3900 void *cmd_in, int inlen, int dest_id, 3901 int dest_type) 3902 { 3903 struct mlx5_flow_destination *dst; 3904 struct mlx5_ib_flow_prio *ft_prio; 3905 struct mlx5_ib_flow_handler *handler; 3906 int dst_num = 0; 3907 bool mcast; 3908 int err; 3909 3910 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3911 return ERR_PTR(-EOPNOTSUPP); 3912 3913 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3914 return ERR_PTR(-ENOMEM); 3915 3916 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL); 3917 if (!dst) 3918 return ERR_PTR(-ENOMEM); 3919 3920 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3921 mutex_lock(&dev->flow_db->lock); 3922 3923 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 3924 if (IS_ERR(ft_prio)) { 3925 err = PTR_ERR(ft_prio); 3926 goto unlock; 3927 } 3928 3929 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3930 dst[dst_num].type = dest_type; 3931 dst[dst_num].tir_num = dest_id; 3932 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3933 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 3934 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3935 dst[dst_num].ft_num = dest_id; 3936 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3937 } else { 3938 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3939 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3940 } 3941 3942 dst_num++; 3943 3944 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3945 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3946 dst[dst_num].counter_id = counter_id; 3947 dst_num++; 3948 } 3949 3950 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 3951 cmd_in, inlen, dst_num); 3952 3953 if (IS_ERR(handler)) { 3954 err = PTR_ERR(handler); 3955 goto destroy_ft; 3956 } 3957 3958 mutex_unlock(&dev->flow_db->lock); 3959 atomic_inc(&fs_matcher->usecnt); 3960 handler->flow_matcher = fs_matcher; 3961 3962 kfree(dst); 3963 3964 return handler; 3965 3966 destroy_ft: 3967 put_flow_table(dev, ft_prio, false); 3968 unlock: 3969 mutex_unlock(&dev->flow_db->lock); 3970 kfree(dst); 3971 3972 return ERR_PTR(err); 3973 } 3974 3975 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3976 { 3977 u32 flags = 0; 3978 3979 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3980 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3981 3982 return flags; 3983 } 3984 3985 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3986 static struct ib_flow_action * 3987 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3988 const struct ib_flow_action_attrs_esp *attr, 3989 struct uverbs_attr_bundle *attrs) 3990 { 3991 struct mlx5_ib_dev *mdev = to_mdev(device); 3992 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3993 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3994 struct mlx5_ib_flow_action *action; 3995 u64 action_flags; 3996 u64 flags; 3997 int err = 0; 3998 3999 err = uverbs_get_flags64( 4000 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 4001 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 4002 if (err) 4003 return ERR_PTR(err); 4004 4005 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 4006 4007 /* We current only support a subset of the standard features. Only a 4008 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 4009 * (with overlap). Full offload mode isn't supported. 4010 */ 4011 if (!attr->keymat || attr->replay || attr->encap || 4012 attr->spi || attr->seq || attr->tfc_pad || 4013 attr->hard_limit_pkts || 4014 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4015 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 4016 return ERR_PTR(-EOPNOTSUPP); 4017 4018 if (attr->keymat->protocol != 4019 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 4020 return ERR_PTR(-EOPNOTSUPP); 4021 4022 aes_gcm = &attr->keymat->keymat.aes_gcm; 4023 4024 if (aes_gcm->icv_len != 16 || 4025 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 4026 return ERR_PTR(-EOPNOTSUPP); 4027 4028 action = kmalloc(sizeof(*action), GFP_KERNEL); 4029 if (!action) 4030 return ERR_PTR(-ENOMEM); 4031 4032 action->esp_aes_gcm.ib_flags = attr->flags; 4033 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 4034 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 4035 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 4036 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 4037 sizeof(accel_attrs.keymat.aes_gcm.salt)); 4038 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 4039 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 4040 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 4041 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 4042 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 4043 4044 accel_attrs.esn = attr->esn; 4045 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 4046 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 4047 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4048 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4049 4050 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 4051 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 4052 4053 action->esp_aes_gcm.ctx = 4054 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 4055 if (IS_ERR(action->esp_aes_gcm.ctx)) { 4056 err = PTR_ERR(action->esp_aes_gcm.ctx); 4057 goto err_parse; 4058 } 4059 4060 action->esp_aes_gcm.ib_flags = attr->flags; 4061 4062 return &action->ib_action; 4063 4064 err_parse: 4065 kfree(action); 4066 return ERR_PTR(err); 4067 } 4068 4069 static int 4070 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 4071 const struct ib_flow_action_attrs_esp *attr, 4072 struct uverbs_attr_bundle *attrs) 4073 { 4074 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4075 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 4076 int err = 0; 4077 4078 if (attr->keymat || attr->replay || attr->encap || 4079 attr->spi || attr->seq || attr->tfc_pad || 4080 attr->hard_limit_pkts || 4081 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4082 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 4083 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 4084 return -EOPNOTSUPP; 4085 4086 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 4087 * be modified. 4088 */ 4089 if (!(maction->esp_aes_gcm.ib_flags & 4090 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 4091 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4092 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 4093 return -EINVAL; 4094 4095 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 4096 sizeof(accel_attrs)); 4097 4098 accel_attrs.esn = attr->esn; 4099 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4100 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4101 else 4102 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4103 4104 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 4105 &accel_attrs); 4106 if (err) 4107 return err; 4108 4109 maction->esp_aes_gcm.ib_flags &= 4110 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4111 maction->esp_aes_gcm.ib_flags |= 4112 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4113 4114 return 0; 4115 } 4116 4117 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4118 { 4119 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4120 4121 switch (action->type) { 4122 case IB_FLOW_ACTION_ESP: 4123 /* 4124 * We only support aes_gcm by now, so we implicitly know this is 4125 * the underline crypto. 4126 */ 4127 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4128 break; 4129 case IB_FLOW_ACTION_UNSPECIFIED: 4130 mlx5_ib_destroy_flow_action_raw(maction); 4131 break; 4132 default: 4133 WARN_ON(true); 4134 break; 4135 } 4136 4137 kfree(maction); 4138 return 0; 4139 } 4140 4141 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4142 { 4143 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4144 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4145 int err; 4146 u16 uid; 4147 4148 uid = ibqp->pd ? 4149 to_mpd(ibqp->pd)->uid : 0; 4150 4151 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4152 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4153 return -EOPNOTSUPP; 4154 } 4155 4156 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4157 if (err) 4158 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4159 ibqp->qp_num, gid->raw); 4160 4161 return err; 4162 } 4163 4164 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4165 { 4166 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4167 int err; 4168 u16 uid; 4169 4170 uid = ibqp->pd ? 4171 to_mpd(ibqp->pd)->uid : 0; 4172 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4173 if (err) 4174 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4175 ibqp->qp_num, gid->raw); 4176 4177 return err; 4178 } 4179 4180 static int init_node_data(struct mlx5_ib_dev *dev) 4181 { 4182 int err; 4183 4184 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4185 if (err) 4186 return err; 4187 4188 dev->mdev->rev_id = dev->mdev->pdev->revision; 4189 4190 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4191 } 4192 4193 static ssize_t fw_pages_show(struct device *device, 4194 struct device_attribute *attr, char *buf) 4195 { 4196 struct mlx5_ib_dev *dev = 4197 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4198 4199 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4200 } 4201 static DEVICE_ATTR_RO(fw_pages); 4202 4203 static ssize_t reg_pages_show(struct device *device, 4204 struct device_attribute *attr, char *buf) 4205 { 4206 struct mlx5_ib_dev *dev = 4207 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4208 4209 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4210 } 4211 static DEVICE_ATTR_RO(reg_pages); 4212 4213 static ssize_t hca_type_show(struct device *device, 4214 struct device_attribute *attr, char *buf) 4215 { 4216 struct mlx5_ib_dev *dev = 4217 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4218 4219 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4220 } 4221 static DEVICE_ATTR_RO(hca_type); 4222 4223 static ssize_t hw_rev_show(struct device *device, 4224 struct device_attribute *attr, char *buf) 4225 { 4226 struct mlx5_ib_dev *dev = 4227 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4228 4229 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4230 } 4231 static DEVICE_ATTR_RO(hw_rev); 4232 4233 static ssize_t board_id_show(struct device *device, 4234 struct device_attribute *attr, char *buf) 4235 { 4236 struct mlx5_ib_dev *dev = 4237 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4238 4239 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4240 dev->mdev->board_id); 4241 } 4242 static DEVICE_ATTR_RO(board_id); 4243 4244 static struct attribute *mlx5_class_attributes[] = { 4245 &dev_attr_hw_rev.attr, 4246 &dev_attr_hca_type.attr, 4247 &dev_attr_board_id.attr, 4248 &dev_attr_fw_pages.attr, 4249 &dev_attr_reg_pages.attr, 4250 NULL, 4251 }; 4252 4253 static const struct attribute_group mlx5_attr_group = { 4254 .attrs = mlx5_class_attributes, 4255 }; 4256 4257 static void pkey_change_handler(struct work_struct *work) 4258 { 4259 struct mlx5_ib_port_resources *ports = 4260 container_of(work, struct mlx5_ib_port_resources, 4261 pkey_change_work); 4262 4263 mutex_lock(&ports->devr->mutex); 4264 mlx5_ib_gsi_pkey_change(ports->gsi); 4265 mutex_unlock(&ports->devr->mutex); 4266 } 4267 4268 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4269 { 4270 struct mlx5_ib_qp *mqp; 4271 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4272 struct mlx5_core_cq *mcq; 4273 struct list_head cq_armed_list; 4274 unsigned long flags_qp; 4275 unsigned long flags_cq; 4276 unsigned long flags; 4277 4278 INIT_LIST_HEAD(&cq_armed_list); 4279 4280 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4281 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4282 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4283 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4284 if (mqp->sq.tail != mqp->sq.head) { 4285 send_mcq = to_mcq(mqp->ibqp.send_cq); 4286 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4287 if (send_mcq->mcq.comp && 4288 mqp->ibqp.send_cq->comp_handler) { 4289 if (!send_mcq->mcq.reset_notify_added) { 4290 send_mcq->mcq.reset_notify_added = 1; 4291 list_add_tail(&send_mcq->mcq.reset_notify, 4292 &cq_armed_list); 4293 } 4294 } 4295 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4296 } 4297 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4298 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4299 /* no handling is needed for SRQ */ 4300 if (!mqp->ibqp.srq) { 4301 if (mqp->rq.tail != mqp->rq.head) { 4302 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4303 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4304 if (recv_mcq->mcq.comp && 4305 mqp->ibqp.recv_cq->comp_handler) { 4306 if (!recv_mcq->mcq.reset_notify_added) { 4307 recv_mcq->mcq.reset_notify_added = 1; 4308 list_add_tail(&recv_mcq->mcq.reset_notify, 4309 &cq_armed_list); 4310 } 4311 } 4312 spin_unlock_irqrestore(&recv_mcq->lock, 4313 flags_cq); 4314 } 4315 } 4316 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4317 } 4318 /*At that point all inflight post send were put to be executed as of we 4319 * lock/unlock above locks Now need to arm all involved CQs. 4320 */ 4321 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4322 mcq->comp(mcq); 4323 } 4324 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4325 } 4326 4327 static void delay_drop_handler(struct work_struct *work) 4328 { 4329 int err; 4330 struct mlx5_ib_delay_drop *delay_drop = 4331 container_of(work, struct mlx5_ib_delay_drop, 4332 delay_drop_work); 4333 4334 atomic_inc(&delay_drop->events_cnt); 4335 4336 mutex_lock(&delay_drop->lock); 4337 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4338 delay_drop->timeout); 4339 if (err) { 4340 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4341 delay_drop->timeout); 4342 delay_drop->activate = false; 4343 } 4344 mutex_unlock(&delay_drop->lock); 4345 } 4346 4347 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4348 struct ib_event *ibev) 4349 { 4350 switch (eqe->sub_type) { 4351 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 4352 schedule_work(&ibdev->delay_drop.delay_drop_work); 4353 break; 4354 default: /* do nothing */ 4355 return; 4356 } 4357 } 4358 4359 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4360 struct ib_event *ibev) 4361 { 4362 u8 port = (eqe->data.port.port >> 4) & 0xf; 4363 4364 ibev->element.port_num = port; 4365 4366 switch (eqe->sub_type) { 4367 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 4368 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 4369 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 4370 /* In RoCE, port up/down events are handled in 4371 * mlx5_netdev_event(). 4372 */ 4373 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4374 IB_LINK_LAYER_ETHERNET) 4375 return -EINVAL; 4376 4377 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 4378 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4379 break; 4380 4381 case MLX5_PORT_CHANGE_SUBTYPE_LID: 4382 ibev->event = IB_EVENT_LID_CHANGE; 4383 break; 4384 4385 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 4386 ibev->event = IB_EVENT_PKEY_CHANGE; 4387 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4388 break; 4389 4390 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 4391 ibev->event = IB_EVENT_GID_CHANGE; 4392 break; 4393 4394 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 4395 ibev->event = IB_EVENT_CLIENT_REREGISTER; 4396 break; 4397 default: 4398 return -EINVAL; 4399 } 4400 4401 return 0; 4402 } 4403 4404 static void mlx5_ib_handle_event(struct work_struct *_work) 4405 { 4406 struct mlx5_ib_event_work *work = 4407 container_of(_work, struct mlx5_ib_event_work, work); 4408 struct mlx5_ib_dev *ibdev; 4409 struct ib_event ibev; 4410 bool fatal = false; 4411 4412 if (work->is_slave) { 4413 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 4414 if (!ibdev) 4415 goto out; 4416 } else { 4417 ibdev = work->dev; 4418 } 4419 4420 switch (work->event) { 4421 case MLX5_DEV_EVENT_SYS_ERROR: 4422 ibev.event = IB_EVENT_DEVICE_FATAL; 4423 mlx5_ib_handle_internal_error(ibdev); 4424 ibev.element.port_num = (u8)(unsigned long)work->param; 4425 fatal = true; 4426 break; 4427 case MLX5_EVENT_TYPE_PORT_CHANGE: 4428 if (handle_port_change(ibdev, work->param, &ibev)) 4429 goto out; 4430 break; 4431 case MLX5_EVENT_TYPE_GENERAL_EVENT: 4432 handle_general_event(ibdev, work->param, &ibev); 4433 /* fall through */ 4434 default: 4435 goto out; 4436 } 4437 4438 ibev.device = &ibdev->ib_dev; 4439 4440 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 4441 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 4442 goto out; 4443 } 4444 4445 if (ibdev->ib_active) 4446 ib_dispatch_event(&ibev); 4447 4448 if (fatal) 4449 ibdev->ib_active = false; 4450 out: 4451 kfree(work); 4452 } 4453 4454 static int mlx5_ib_event(struct notifier_block *nb, 4455 unsigned long event, void *param) 4456 { 4457 struct mlx5_ib_event_work *work; 4458 4459 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4460 if (!work) 4461 return NOTIFY_DONE; 4462 4463 INIT_WORK(&work->work, mlx5_ib_handle_event); 4464 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 4465 work->is_slave = false; 4466 work->param = param; 4467 work->event = event; 4468 4469 queue_work(mlx5_ib_event_wq, &work->work); 4470 4471 return NOTIFY_OK; 4472 } 4473 4474 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 4475 unsigned long event, void *param) 4476 { 4477 struct mlx5_ib_event_work *work; 4478 4479 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4480 if (!work) 4481 return NOTIFY_DONE; 4482 4483 INIT_WORK(&work->work, mlx5_ib_handle_event); 4484 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 4485 work->is_slave = true; 4486 work->param = param; 4487 work->event = event; 4488 queue_work(mlx5_ib_event_wq, &work->work); 4489 4490 return NOTIFY_OK; 4491 } 4492 4493 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4494 { 4495 struct mlx5_hca_vport_context vport_ctx; 4496 int err; 4497 int port; 4498 4499 for (port = 1; port <= dev->num_ports; port++) { 4500 dev->mdev->port_caps[port - 1].has_smi = false; 4501 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4502 MLX5_CAP_PORT_TYPE_IB) { 4503 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4504 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4505 port, 0, 4506 &vport_ctx); 4507 if (err) { 4508 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4509 port, err); 4510 return err; 4511 } 4512 dev->mdev->port_caps[port - 1].has_smi = 4513 vport_ctx.has_smi; 4514 } else { 4515 dev->mdev->port_caps[port - 1].has_smi = true; 4516 } 4517 } 4518 } 4519 return 0; 4520 } 4521 4522 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4523 { 4524 int port; 4525 4526 for (port = 1; port <= dev->num_ports; port++) 4527 mlx5_query_ext_port_caps(dev, port); 4528 } 4529 4530 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4531 { 4532 struct ib_device_attr *dprops = NULL; 4533 struct ib_port_attr *pprops = NULL; 4534 int err = -ENOMEM; 4535 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4536 4537 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4538 if (!pprops) 4539 goto out; 4540 4541 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4542 if (!dprops) 4543 goto out; 4544 4545 err = set_has_smi_cap(dev); 4546 if (err) 4547 goto out; 4548 4549 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4550 if (err) { 4551 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4552 goto out; 4553 } 4554 4555 memset(pprops, 0, sizeof(*pprops)); 4556 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4557 if (err) { 4558 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4559 port, err); 4560 goto out; 4561 } 4562 4563 dev->mdev->port_caps[port - 1].pkey_table_len = 4564 dprops->max_pkeys; 4565 dev->mdev->port_caps[port - 1].gid_table_len = 4566 pprops->gid_tbl_len; 4567 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4568 port, dprops->max_pkeys, pprops->gid_tbl_len); 4569 4570 out: 4571 kfree(pprops); 4572 kfree(dprops); 4573 4574 return err; 4575 } 4576 4577 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4578 { 4579 int err; 4580 4581 err = mlx5_mr_cache_cleanup(dev); 4582 if (err) 4583 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4584 4585 if (dev->umrc.qp) 4586 mlx5_ib_destroy_qp(dev->umrc.qp); 4587 if (dev->umrc.cq) 4588 ib_free_cq(dev->umrc.cq); 4589 if (dev->umrc.pd) 4590 ib_dealloc_pd(dev->umrc.pd); 4591 } 4592 4593 enum { 4594 MAX_UMR_WR = 128, 4595 }; 4596 4597 static int create_umr_res(struct mlx5_ib_dev *dev) 4598 { 4599 struct ib_qp_init_attr *init_attr = NULL; 4600 struct ib_qp_attr *attr = NULL; 4601 struct ib_pd *pd; 4602 struct ib_cq *cq; 4603 struct ib_qp *qp; 4604 int ret; 4605 4606 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4607 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4608 if (!attr || !init_attr) { 4609 ret = -ENOMEM; 4610 goto error_0; 4611 } 4612 4613 pd = ib_alloc_pd(&dev->ib_dev, 0); 4614 if (IS_ERR(pd)) { 4615 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4616 ret = PTR_ERR(pd); 4617 goto error_0; 4618 } 4619 4620 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4621 if (IS_ERR(cq)) { 4622 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4623 ret = PTR_ERR(cq); 4624 goto error_2; 4625 } 4626 4627 init_attr->send_cq = cq; 4628 init_attr->recv_cq = cq; 4629 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4630 init_attr->cap.max_send_wr = MAX_UMR_WR; 4631 init_attr->cap.max_send_sge = 1; 4632 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4633 init_attr->port_num = 1; 4634 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4635 if (IS_ERR(qp)) { 4636 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4637 ret = PTR_ERR(qp); 4638 goto error_3; 4639 } 4640 qp->device = &dev->ib_dev; 4641 qp->real_qp = qp; 4642 qp->uobject = NULL; 4643 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4644 qp->send_cq = init_attr->send_cq; 4645 qp->recv_cq = init_attr->recv_cq; 4646 4647 attr->qp_state = IB_QPS_INIT; 4648 attr->port_num = 1; 4649 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4650 IB_QP_PORT, NULL); 4651 if (ret) { 4652 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4653 goto error_4; 4654 } 4655 4656 memset(attr, 0, sizeof(*attr)); 4657 attr->qp_state = IB_QPS_RTR; 4658 attr->path_mtu = IB_MTU_256; 4659 4660 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4661 if (ret) { 4662 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4663 goto error_4; 4664 } 4665 4666 memset(attr, 0, sizeof(*attr)); 4667 attr->qp_state = IB_QPS_RTS; 4668 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4669 if (ret) { 4670 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4671 goto error_4; 4672 } 4673 4674 dev->umrc.qp = qp; 4675 dev->umrc.cq = cq; 4676 dev->umrc.pd = pd; 4677 4678 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4679 ret = mlx5_mr_cache_init(dev); 4680 if (ret) { 4681 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4682 goto error_4; 4683 } 4684 4685 kfree(attr); 4686 kfree(init_attr); 4687 4688 return 0; 4689 4690 error_4: 4691 mlx5_ib_destroy_qp(qp); 4692 dev->umrc.qp = NULL; 4693 4694 error_3: 4695 ib_free_cq(cq); 4696 dev->umrc.cq = NULL; 4697 4698 error_2: 4699 ib_dealloc_pd(pd); 4700 dev->umrc.pd = NULL; 4701 4702 error_0: 4703 kfree(attr); 4704 kfree(init_attr); 4705 return ret; 4706 } 4707 4708 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4709 { 4710 switch (umr_fence_cap) { 4711 case MLX5_CAP_UMR_FENCE_NONE: 4712 return MLX5_FENCE_MODE_NONE; 4713 case MLX5_CAP_UMR_FENCE_SMALL: 4714 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4715 default: 4716 return MLX5_FENCE_MODE_STRONG_ORDERING; 4717 } 4718 } 4719 4720 static int create_dev_resources(struct mlx5_ib_resources *devr) 4721 { 4722 struct ib_srq_init_attr attr; 4723 struct mlx5_ib_dev *dev; 4724 struct ib_device *ibdev; 4725 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4726 int port; 4727 int ret = 0; 4728 4729 dev = container_of(devr, struct mlx5_ib_dev, devr); 4730 ibdev = &dev->ib_dev; 4731 4732 mutex_init(&devr->mutex); 4733 4734 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 4735 if (!devr->p0) 4736 return -ENOMEM; 4737 4738 devr->p0->device = ibdev; 4739 devr->p0->uobject = NULL; 4740 atomic_set(&devr->p0->usecnt, 0); 4741 4742 ret = mlx5_ib_alloc_pd(devr->p0, NULL, NULL); 4743 if (ret) 4744 goto error0; 4745 4746 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4747 if (IS_ERR(devr->c0)) { 4748 ret = PTR_ERR(devr->c0); 4749 goto error1; 4750 } 4751 devr->c0->device = &dev->ib_dev; 4752 devr->c0->uobject = NULL; 4753 devr->c0->comp_handler = NULL; 4754 devr->c0->event_handler = NULL; 4755 devr->c0->cq_context = NULL; 4756 atomic_set(&devr->c0->usecnt, 0); 4757 4758 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4759 if (IS_ERR(devr->x0)) { 4760 ret = PTR_ERR(devr->x0); 4761 goto error2; 4762 } 4763 devr->x0->device = &dev->ib_dev; 4764 devr->x0->inode = NULL; 4765 atomic_set(&devr->x0->usecnt, 0); 4766 mutex_init(&devr->x0->tgt_qp_mutex); 4767 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4768 4769 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4770 if (IS_ERR(devr->x1)) { 4771 ret = PTR_ERR(devr->x1); 4772 goto error3; 4773 } 4774 devr->x1->device = &dev->ib_dev; 4775 devr->x1->inode = NULL; 4776 atomic_set(&devr->x1->usecnt, 0); 4777 mutex_init(&devr->x1->tgt_qp_mutex); 4778 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4779 4780 memset(&attr, 0, sizeof(attr)); 4781 attr.attr.max_sge = 1; 4782 attr.attr.max_wr = 1; 4783 attr.srq_type = IB_SRQT_XRC; 4784 attr.ext.cq = devr->c0; 4785 attr.ext.xrc.xrcd = devr->x0; 4786 4787 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4788 if (IS_ERR(devr->s0)) { 4789 ret = PTR_ERR(devr->s0); 4790 goto error4; 4791 } 4792 devr->s0->device = &dev->ib_dev; 4793 devr->s0->pd = devr->p0; 4794 devr->s0->uobject = NULL; 4795 devr->s0->event_handler = NULL; 4796 devr->s0->srq_context = NULL; 4797 devr->s0->srq_type = IB_SRQT_XRC; 4798 devr->s0->ext.xrc.xrcd = devr->x0; 4799 devr->s0->ext.cq = devr->c0; 4800 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4801 atomic_inc(&devr->s0->ext.cq->usecnt); 4802 atomic_inc(&devr->p0->usecnt); 4803 atomic_set(&devr->s0->usecnt, 0); 4804 4805 memset(&attr, 0, sizeof(attr)); 4806 attr.attr.max_sge = 1; 4807 attr.attr.max_wr = 1; 4808 attr.srq_type = IB_SRQT_BASIC; 4809 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4810 if (IS_ERR(devr->s1)) { 4811 ret = PTR_ERR(devr->s1); 4812 goto error5; 4813 } 4814 devr->s1->device = &dev->ib_dev; 4815 devr->s1->pd = devr->p0; 4816 devr->s1->uobject = NULL; 4817 devr->s1->event_handler = NULL; 4818 devr->s1->srq_context = NULL; 4819 devr->s1->srq_type = IB_SRQT_BASIC; 4820 devr->s1->ext.cq = devr->c0; 4821 atomic_inc(&devr->p0->usecnt); 4822 atomic_set(&devr->s1->usecnt, 0); 4823 4824 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4825 INIT_WORK(&devr->ports[port].pkey_change_work, 4826 pkey_change_handler); 4827 devr->ports[port].devr = devr; 4828 } 4829 4830 return 0; 4831 4832 error5: 4833 mlx5_ib_destroy_srq(devr->s0); 4834 error4: 4835 mlx5_ib_dealloc_xrcd(devr->x1); 4836 error3: 4837 mlx5_ib_dealloc_xrcd(devr->x0); 4838 error2: 4839 mlx5_ib_destroy_cq(devr->c0); 4840 error1: 4841 mlx5_ib_dealloc_pd(devr->p0); 4842 error0: 4843 kfree(devr->p0); 4844 return ret; 4845 } 4846 4847 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4848 { 4849 struct mlx5_ib_dev *dev = 4850 container_of(devr, struct mlx5_ib_dev, devr); 4851 int port; 4852 4853 mlx5_ib_destroy_srq(devr->s1); 4854 mlx5_ib_destroy_srq(devr->s0); 4855 mlx5_ib_dealloc_xrcd(devr->x0); 4856 mlx5_ib_dealloc_xrcd(devr->x1); 4857 mlx5_ib_destroy_cq(devr->c0); 4858 mlx5_ib_dealloc_pd(devr->p0); 4859 kfree(devr->p0); 4860 4861 /* Make sure no change P_Key work items are still executing */ 4862 for (port = 0; port < dev->num_ports; ++port) 4863 cancel_work_sync(&devr->ports[port].pkey_change_work); 4864 } 4865 4866 static u32 get_core_cap_flags(struct ib_device *ibdev, 4867 struct mlx5_hca_vport_context *rep) 4868 { 4869 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4870 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4871 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4872 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4873 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4874 u32 ret = 0; 4875 4876 if (rep->grh_required) 4877 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4878 4879 if (ll == IB_LINK_LAYER_INFINIBAND) 4880 return ret | RDMA_CORE_PORT_IBA_IB; 4881 4882 if (raw_support) 4883 ret |= RDMA_CORE_PORT_RAW_PACKET; 4884 4885 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4886 return ret; 4887 4888 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4889 return ret; 4890 4891 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4892 ret |= RDMA_CORE_PORT_IBA_ROCE; 4893 4894 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4895 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4896 4897 return ret; 4898 } 4899 4900 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4901 struct ib_port_immutable *immutable) 4902 { 4903 struct ib_port_attr attr; 4904 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4905 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4906 struct mlx5_hca_vport_context rep = {0}; 4907 int err; 4908 4909 err = ib_query_port(ibdev, port_num, &attr); 4910 if (err) 4911 return err; 4912 4913 if (ll == IB_LINK_LAYER_INFINIBAND) { 4914 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4915 &rep); 4916 if (err) 4917 return err; 4918 } 4919 4920 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4921 immutable->gid_tbl_len = attr.gid_tbl_len; 4922 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4923 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4924 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4925 4926 return 0; 4927 } 4928 4929 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4930 struct ib_port_immutable *immutable) 4931 { 4932 struct ib_port_attr attr; 4933 int err; 4934 4935 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4936 4937 err = ib_query_port(ibdev, port_num, &attr); 4938 if (err) 4939 return err; 4940 4941 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4942 immutable->gid_tbl_len = attr.gid_tbl_len; 4943 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4944 4945 return 0; 4946 } 4947 4948 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4949 { 4950 struct mlx5_ib_dev *dev = 4951 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4952 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4953 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4954 fw_rev_sub(dev->mdev)); 4955 } 4956 4957 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4958 { 4959 struct mlx5_core_dev *mdev = dev->mdev; 4960 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4961 MLX5_FLOW_NAMESPACE_LAG); 4962 struct mlx5_flow_table *ft; 4963 int err; 4964 4965 if (!ns || !mlx5_lag_is_roce(mdev)) 4966 return 0; 4967 4968 err = mlx5_cmd_create_vport_lag(mdev); 4969 if (err) 4970 return err; 4971 4972 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4973 if (IS_ERR(ft)) { 4974 err = PTR_ERR(ft); 4975 goto err_destroy_vport_lag; 4976 } 4977 4978 dev->flow_db->lag_demux_ft = ft; 4979 dev->lag_active = true; 4980 return 0; 4981 4982 err_destroy_vport_lag: 4983 mlx5_cmd_destroy_vport_lag(mdev); 4984 return err; 4985 } 4986 4987 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4988 { 4989 struct mlx5_core_dev *mdev = dev->mdev; 4990 4991 if (dev->lag_active) { 4992 dev->lag_active = false; 4993 4994 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4995 dev->flow_db->lag_demux_ft = NULL; 4996 4997 mlx5_cmd_destroy_vport_lag(mdev); 4998 } 4999 } 5000 5001 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5002 { 5003 int err; 5004 5005 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 5006 err = register_netdevice_notifier(&dev->roce[port_num].nb); 5007 if (err) { 5008 dev->roce[port_num].nb.notifier_call = NULL; 5009 return err; 5010 } 5011 5012 return 0; 5013 } 5014 5015 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5016 { 5017 if (dev->roce[port_num].nb.notifier_call) { 5018 unregister_netdevice_notifier(&dev->roce[port_num].nb); 5019 dev->roce[port_num].nb.notifier_call = NULL; 5020 } 5021 } 5022 5023 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 5024 { 5025 int err; 5026 5027 if (MLX5_CAP_GEN(dev->mdev, roce)) { 5028 err = mlx5_nic_vport_enable_roce(dev->mdev); 5029 if (err) 5030 return err; 5031 } 5032 5033 err = mlx5_eth_lag_init(dev); 5034 if (err) 5035 goto err_disable_roce; 5036 5037 return 0; 5038 5039 err_disable_roce: 5040 if (MLX5_CAP_GEN(dev->mdev, roce)) 5041 mlx5_nic_vport_disable_roce(dev->mdev); 5042 5043 return err; 5044 } 5045 5046 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 5047 { 5048 mlx5_eth_lag_cleanup(dev); 5049 if (MLX5_CAP_GEN(dev->mdev, roce)) 5050 mlx5_nic_vport_disable_roce(dev->mdev); 5051 } 5052 5053 struct mlx5_ib_counter { 5054 const char *name; 5055 size_t offset; 5056 }; 5057 5058 #define INIT_Q_COUNTER(_name) \ 5059 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 5060 5061 static const struct mlx5_ib_counter basic_q_cnts[] = { 5062 INIT_Q_COUNTER(rx_write_requests), 5063 INIT_Q_COUNTER(rx_read_requests), 5064 INIT_Q_COUNTER(rx_atomic_requests), 5065 INIT_Q_COUNTER(out_of_buffer), 5066 }; 5067 5068 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 5069 INIT_Q_COUNTER(out_of_sequence), 5070 }; 5071 5072 static const struct mlx5_ib_counter retrans_q_cnts[] = { 5073 INIT_Q_COUNTER(duplicate_request), 5074 INIT_Q_COUNTER(rnr_nak_retry_err), 5075 INIT_Q_COUNTER(packet_seq_err), 5076 INIT_Q_COUNTER(implied_nak_seq_err), 5077 INIT_Q_COUNTER(local_ack_timeout_err), 5078 }; 5079 5080 #define INIT_CONG_COUNTER(_name) \ 5081 { .name = #_name, .offset = \ 5082 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 5083 5084 static const struct mlx5_ib_counter cong_cnts[] = { 5085 INIT_CONG_COUNTER(rp_cnp_ignored), 5086 INIT_CONG_COUNTER(rp_cnp_handled), 5087 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 5088 INIT_CONG_COUNTER(np_cnp_sent), 5089 }; 5090 5091 static const struct mlx5_ib_counter extended_err_cnts[] = { 5092 INIT_Q_COUNTER(resp_local_length_error), 5093 INIT_Q_COUNTER(resp_cqe_error), 5094 INIT_Q_COUNTER(req_cqe_error), 5095 INIT_Q_COUNTER(req_remote_invalid_request), 5096 INIT_Q_COUNTER(req_remote_access_errors), 5097 INIT_Q_COUNTER(resp_remote_access_errors), 5098 INIT_Q_COUNTER(resp_cqe_flush_error), 5099 INIT_Q_COUNTER(req_cqe_flush_error), 5100 }; 5101 5102 #define INIT_EXT_PPCNT_COUNTER(_name) \ 5103 { .name = #_name, .offset = \ 5104 MLX5_BYTE_OFF(ppcnt_reg, \ 5105 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 5106 5107 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 5108 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 5109 }; 5110 5111 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 5112 { 5113 int i; 5114 5115 for (i = 0; i < dev->num_ports; i++) { 5116 if (dev->port[i].cnts.set_id_valid) 5117 mlx5_core_dealloc_q_counter(dev->mdev, 5118 dev->port[i].cnts.set_id); 5119 kfree(dev->port[i].cnts.names); 5120 kfree(dev->port[i].cnts.offsets); 5121 } 5122 } 5123 5124 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 5125 struct mlx5_ib_counters *cnts) 5126 { 5127 u32 num_counters; 5128 5129 num_counters = ARRAY_SIZE(basic_q_cnts); 5130 5131 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 5132 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 5133 5134 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 5135 num_counters += ARRAY_SIZE(retrans_q_cnts); 5136 5137 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 5138 num_counters += ARRAY_SIZE(extended_err_cnts); 5139 5140 cnts->num_q_counters = num_counters; 5141 5142 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5143 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 5144 num_counters += ARRAY_SIZE(cong_cnts); 5145 } 5146 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5147 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 5148 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 5149 } 5150 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 5151 if (!cnts->names) 5152 return -ENOMEM; 5153 5154 cnts->offsets = kcalloc(num_counters, 5155 sizeof(cnts->offsets), GFP_KERNEL); 5156 if (!cnts->offsets) 5157 goto err_names; 5158 5159 return 0; 5160 5161 err_names: 5162 kfree(cnts->names); 5163 cnts->names = NULL; 5164 return -ENOMEM; 5165 } 5166 5167 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 5168 const char **names, 5169 size_t *offsets) 5170 { 5171 int i; 5172 int j = 0; 5173 5174 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5175 names[j] = basic_q_cnts[i].name; 5176 offsets[j] = basic_q_cnts[i].offset; 5177 } 5178 5179 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5180 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5181 names[j] = out_of_seq_q_cnts[i].name; 5182 offsets[j] = out_of_seq_q_cnts[i].offset; 5183 } 5184 } 5185 5186 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5187 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5188 names[j] = retrans_q_cnts[i].name; 5189 offsets[j] = retrans_q_cnts[i].offset; 5190 } 5191 } 5192 5193 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5194 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5195 names[j] = extended_err_cnts[i].name; 5196 offsets[j] = extended_err_cnts[i].offset; 5197 } 5198 } 5199 5200 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5201 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5202 names[j] = cong_cnts[i].name; 5203 offsets[j] = cong_cnts[i].offset; 5204 } 5205 } 5206 5207 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5208 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5209 names[j] = ext_ppcnt_cnts[i].name; 5210 offsets[j] = ext_ppcnt_cnts[i].offset; 5211 } 5212 } 5213 } 5214 5215 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5216 { 5217 int err = 0; 5218 int i; 5219 bool is_shared; 5220 5221 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0; 5222 5223 for (i = 0; i < dev->num_ports; i++) { 5224 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5225 if (err) 5226 goto err_alloc; 5227 5228 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5229 dev->port[i].cnts.offsets); 5230 5231 err = mlx5_cmd_alloc_q_counter(dev->mdev, 5232 &dev->port[i].cnts.set_id, 5233 is_shared ? 5234 MLX5_SHARED_RESOURCE_UID : 0); 5235 if (err) { 5236 mlx5_ib_warn(dev, 5237 "couldn't allocate queue counter for port %d, err %d\n", 5238 i + 1, err); 5239 goto err_alloc; 5240 } 5241 dev->port[i].cnts.set_id_valid = true; 5242 } 5243 5244 return 0; 5245 5246 err_alloc: 5247 mlx5_ib_dealloc_counters(dev); 5248 return err; 5249 } 5250 5251 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5252 u8 port_num) 5253 { 5254 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5255 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5256 5257 /* We support only per port stats */ 5258 if (port_num == 0) 5259 return NULL; 5260 5261 return rdma_alloc_hw_stats_struct(port->cnts.names, 5262 port->cnts.num_q_counters + 5263 port->cnts.num_cong_counters + 5264 port->cnts.num_ext_ppcnt_counters, 5265 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5266 } 5267 5268 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5269 struct mlx5_ib_port *port, 5270 struct rdma_hw_stats *stats) 5271 { 5272 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5273 void *out; 5274 __be32 val; 5275 int ret, i; 5276 5277 out = kvzalloc(outlen, GFP_KERNEL); 5278 if (!out) 5279 return -ENOMEM; 5280 5281 ret = mlx5_core_query_q_counter(mdev, 5282 port->cnts.set_id, 0, 5283 out, outlen); 5284 if (ret) 5285 goto free; 5286 5287 for (i = 0; i < port->cnts.num_q_counters; i++) { 5288 val = *(__be32 *)(out + port->cnts.offsets[i]); 5289 stats->value[i] = (u64)be32_to_cpu(val); 5290 } 5291 5292 free: 5293 kvfree(out); 5294 return ret; 5295 } 5296 5297 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5298 struct mlx5_ib_port *port, 5299 struct rdma_hw_stats *stats) 5300 { 5301 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5302 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5303 int ret, i; 5304 void *out; 5305 5306 out = kvzalloc(sz, GFP_KERNEL); 5307 if (!out) 5308 return -ENOMEM; 5309 5310 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5311 if (ret) 5312 goto free; 5313 5314 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5315 stats->value[i + offset] = 5316 be64_to_cpup((__be64 *)(out + 5317 port->cnts.offsets[i + offset])); 5318 } 5319 5320 free: 5321 kvfree(out); 5322 return ret; 5323 } 5324 5325 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5326 struct rdma_hw_stats *stats, 5327 u8 port_num, int index) 5328 { 5329 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5330 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5331 struct mlx5_core_dev *mdev; 5332 int ret, num_counters; 5333 u8 mdev_port_num; 5334 5335 if (!stats) 5336 return -EINVAL; 5337 5338 num_counters = port->cnts.num_q_counters + 5339 port->cnts.num_cong_counters + 5340 port->cnts.num_ext_ppcnt_counters; 5341 5342 /* q_counters are per IB device, query the master mdev */ 5343 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5344 if (ret) 5345 return ret; 5346 5347 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5348 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5349 if (ret) 5350 return ret; 5351 } 5352 5353 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5354 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5355 &mdev_port_num); 5356 if (!mdev) { 5357 /* If port is not affiliated yet, its in down state 5358 * which doesn't have any counters yet, so it would be 5359 * zero. So no need to read from the HCA. 5360 */ 5361 goto done; 5362 } 5363 ret = mlx5_lag_query_cong_counters(dev->mdev, 5364 stats->value + 5365 port->cnts.num_q_counters, 5366 port->cnts.num_cong_counters, 5367 port->cnts.offsets + 5368 port->cnts.num_q_counters); 5369 5370 mlx5_ib_put_native_port_mdev(dev, port_num); 5371 if (ret) 5372 return ret; 5373 } 5374 5375 done: 5376 return num_counters; 5377 } 5378 5379 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5380 enum rdma_netdev_t type, 5381 struct rdma_netdev_alloc_params *params) 5382 { 5383 if (type != RDMA_NETDEV_IPOIB) 5384 return -EOPNOTSUPP; 5385 5386 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5387 } 5388 5389 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5390 { 5391 if (!dev->delay_drop.dbg) 5392 return; 5393 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5394 kfree(dev->delay_drop.dbg); 5395 dev->delay_drop.dbg = NULL; 5396 } 5397 5398 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5399 { 5400 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5401 return; 5402 5403 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5404 delay_drop_debugfs_cleanup(dev); 5405 } 5406 5407 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5408 size_t count, loff_t *pos) 5409 { 5410 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5411 char lbuf[20]; 5412 int len; 5413 5414 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5415 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5416 } 5417 5418 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5419 size_t count, loff_t *pos) 5420 { 5421 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5422 u32 timeout; 5423 u32 var; 5424 5425 if (kstrtouint_from_user(buf, count, 0, &var)) 5426 return -EFAULT; 5427 5428 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5429 1000); 5430 if (timeout != var) 5431 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5432 timeout); 5433 5434 delay_drop->timeout = timeout; 5435 5436 return count; 5437 } 5438 5439 static const struct file_operations fops_delay_drop_timeout = { 5440 .owner = THIS_MODULE, 5441 .open = simple_open, 5442 .write = delay_drop_timeout_write, 5443 .read = delay_drop_timeout_read, 5444 }; 5445 5446 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5447 { 5448 struct mlx5_ib_dbg_delay_drop *dbg; 5449 5450 if (!mlx5_debugfs_root) 5451 return 0; 5452 5453 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5454 if (!dbg) 5455 return -ENOMEM; 5456 5457 dev->delay_drop.dbg = dbg; 5458 5459 dbg->dir_debugfs = 5460 debugfs_create_dir("delay_drop", 5461 dev->mdev->priv.dbg_root); 5462 if (!dbg->dir_debugfs) 5463 goto out_debugfs; 5464 5465 dbg->events_cnt_debugfs = 5466 debugfs_create_atomic_t("num_timeout_events", 0400, 5467 dbg->dir_debugfs, 5468 &dev->delay_drop.events_cnt); 5469 if (!dbg->events_cnt_debugfs) 5470 goto out_debugfs; 5471 5472 dbg->rqs_cnt_debugfs = 5473 debugfs_create_atomic_t("num_rqs", 0400, 5474 dbg->dir_debugfs, 5475 &dev->delay_drop.rqs_cnt); 5476 if (!dbg->rqs_cnt_debugfs) 5477 goto out_debugfs; 5478 5479 dbg->timeout_debugfs = 5480 debugfs_create_file("timeout", 0600, 5481 dbg->dir_debugfs, 5482 &dev->delay_drop, 5483 &fops_delay_drop_timeout); 5484 if (!dbg->timeout_debugfs) 5485 goto out_debugfs; 5486 5487 return 0; 5488 5489 out_debugfs: 5490 delay_drop_debugfs_cleanup(dev); 5491 return -ENOMEM; 5492 } 5493 5494 static void init_delay_drop(struct mlx5_ib_dev *dev) 5495 { 5496 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5497 return; 5498 5499 mutex_init(&dev->delay_drop.lock); 5500 dev->delay_drop.dev = dev; 5501 dev->delay_drop.activate = false; 5502 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5503 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5504 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5505 atomic_set(&dev->delay_drop.events_cnt, 0); 5506 5507 if (delay_drop_debugfs_init(dev)) 5508 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5509 } 5510 5511 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5512 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5513 struct mlx5_ib_multiport_info *mpi) 5514 { 5515 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5516 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5517 int comps; 5518 int err; 5519 int i; 5520 5521 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5522 5523 spin_lock(&port->mp.mpi_lock); 5524 if (!mpi->ibdev) { 5525 spin_unlock(&port->mp.mpi_lock); 5526 return; 5527 } 5528 5529 if (mpi->mdev_events.notifier_call) 5530 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 5531 mpi->mdev_events.notifier_call = NULL; 5532 5533 mpi->ibdev = NULL; 5534 5535 spin_unlock(&port->mp.mpi_lock); 5536 mlx5_remove_netdev_notifier(ibdev, port_num); 5537 spin_lock(&port->mp.mpi_lock); 5538 5539 comps = mpi->mdev_refcnt; 5540 if (comps) { 5541 mpi->unaffiliate = true; 5542 init_completion(&mpi->unref_comp); 5543 spin_unlock(&port->mp.mpi_lock); 5544 5545 for (i = 0; i < comps; i++) 5546 wait_for_completion(&mpi->unref_comp); 5547 5548 spin_lock(&port->mp.mpi_lock); 5549 mpi->unaffiliate = false; 5550 } 5551 5552 port->mp.mpi = NULL; 5553 5554 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5555 5556 spin_unlock(&port->mp.mpi_lock); 5557 5558 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5559 5560 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5561 /* Log an error, still needed to cleanup the pointers and add 5562 * it back to the list. 5563 */ 5564 if (err) 5565 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5566 port_num + 1); 5567 5568 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5569 } 5570 5571 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5572 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5573 struct mlx5_ib_multiport_info *mpi) 5574 { 5575 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5576 int err; 5577 5578 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5579 if (ibdev->port[port_num].mp.mpi) { 5580 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5581 port_num + 1); 5582 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5583 return false; 5584 } 5585 5586 ibdev->port[port_num].mp.mpi = mpi; 5587 mpi->ibdev = ibdev; 5588 mpi->mdev_events.notifier_call = NULL; 5589 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5590 5591 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5592 if (err) 5593 goto unbind; 5594 5595 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5596 if (err) 5597 goto unbind; 5598 5599 err = mlx5_add_netdev_notifier(ibdev, port_num); 5600 if (err) { 5601 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5602 port_num + 1); 5603 goto unbind; 5604 } 5605 5606 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 5607 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 5608 5609 mlx5_ib_init_cong_debugfs(ibdev, port_num); 5610 5611 return true; 5612 5613 unbind: 5614 mlx5_ib_unbind_slave_port(ibdev, mpi); 5615 return false; 5616 } 5617 5618 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5619 { 5620 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5621 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5622 port_num + 1); 5623 struct mlx5_ib_multiport_info *mpi; 5624 int err; 5625 int i; 5626 5627 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5628 return 0; 5629 5630 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5631 &dev->sys_image_guid); 5632 if (err) 5633 return err; 5634 5635 err = mlx5_nic_vport_enable_roce(dev->mdev); 5636 if (err) 5637 return err; 5638 5639 mutex_lock(&mlx5_ib_multiport_mutex); 5640 for (i = 0; i < dev->num_ports; i++) { 5641 bool bound = false; 5642 5643 /* build a stub multiport info struct for the native port. */ 5644 if (i == port_num) { 5645 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5646 if (!mpi) { 5647 mutex_unlock(&mlx5_ib_multiport_mutex); 5648 mlx5_nic_vport_disable_roce(dev->mdev); 5649 return -ENOMEM; 5650 } 5651 5652 mpi->is_master = true; 5653 mpi->mdev = dev->mdev; 5654 mpi->sys_image_guid = dev->sys_image_guid; 5655 dev->port[i].mp.mpi = mpi; 5656 mpi->ibdev = dev; 5657 mpi = NULL; 5658 continue; 5659 } 5660 5661 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5662 list) { 5663 if (dev->sys_image_guid == mpi->sys_image_guid && 5664 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5665 bound = mlx5_ib_bind_slave_port(dev, mpi); 5666 } 5667 5668 if (bound) { 5669 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5670 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5671 list_del(&mpi->list); 5672 break; 5673 } 5674 } 5675 if (!bound) { 5676 get_port_caps(dev, i + 1); 5677 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5678 i + 1); 5679 } 5680 } 5681 5682 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5683 mutex_unlock(&mlx5_ib_multiport_mutex); 5684 return err; 5685 } 5686 5687 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5688 { 5689 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5690 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5691 port_num + 1); 5692 int i; 5693 5694 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5695 return; 5696 5697 mutex_lock(&mlx5_ib_multiport_mutex); 5698 for (i = 0; i < dev->num_ports; i++) { 5699 if (dev->port[i].mp.mpi) { 5700 /* Destroy the native port stub */ 5701 if (i == port_num) { 5702 kfree(dev->port[i].mp.mpi); 5703 dev->port[i].mp.mpi = NULL; 5704 } else { 5705 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5706 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5707 } 5708 } 5709 } 5710 5711 mlx5_ib_dbg(dev, "removing from devlist\n"); 5712 list_del(&dev->ib_dev_list); 5713 mutex_unlock(&mlx5_ib_multiport_mutex); 5714 5715 mlx5_nic_vport_disable_roce(dev->mdev); 5716 } 5717 5718 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5719 mlx5_ib_dm, 5720 UVERBS_OBJECT_DM, 5721 UVERBS_METHOD_DM_ALLOC, 5722 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5723 UVERBS_ATTR_TYPE(u64), 5724 UA_MANDATORY), 5725 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5726 UVERBS_ATTR_TYPE(u16), 5727 UA_MANDATORY)); 5728 5729 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5730 mlx5_ib_flow_action, 5731 UVERBS_OBJECT_FLOW_ACTION, 5732 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5733 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5734 enum mlx5_ib_uapi_flow_action_flags)); 5735 5736 static const struct uapi_definition mlx5_ib_defs[] = { 5737 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 5738 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 5739 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 5740 #endif 5741 5742 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 5743 &mlx5_ib_flow_action), 5744 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 5745 {} 5746 }; 5747 5748 static int mlx5_ib_read_counters(struct ib_counters *counters, 5749 struct ib_counters_read_attr *read_attr, 5750 struct uverbs_attr_bundle *attrs) 5751 { 5752 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5753 struct mlx5_read_counters_attr mread_attr = {}; 5754 struct mlx5_ib_flow_counters_desc *desc; 5755 int ret, i; 5756 5757 mutex_lock(&mcounters->mcntrs_mutex); 5758 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5759 ret = -EINVAL; 5760 goto err_bound; 5761 } 5762 5763 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5764 GFP_KERNEL); 5765 if (!mread_attr.out) { 5766 ret = -ENOMEM; 5767 goto err_bound; 5768 } 5769 5770 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5771 mread_attr.flags = read_attr->flags; 5772 ret = mcounters->read_counters(counters->device, &mread_attr); 5773 if (ret) 5774 goto err_read; 5775 5776 /* do the pass over the counters data array to assign according to the 5777 * descriptions and indexing pairs 5778 */ 5779 desc = mcounters->counters_data; 5780 for (i = 0; i < mcounters->ncounters; i++) 5781 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5782 5783 err_read: 5784 kfree(mread_attr.out); 5785 err_bound: 5786 mutex_unlock(&mcounters->mcntrs_mutex); 5787 return ret; 5788 } 5789 5790 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5791 { 5792 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5793 5794 counters_clear_description(counters); 5795 if (mcounters->hw_cntrs_hndl) 5796 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5797 mcounters->hw_cntrs_hndl); 5798 5799 kfree(mcounters); 5800 5801 return 0; 5802 } 5803 5804 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5805 struct uverbs_attr_bundle *attrs) 5806 { 5807 struct mlx5_ib_mcounters *mcounters; 5808 5809 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5810 if (!mcounters) 5811 return ERR_PTR(-ENOMEM); 5812 5813 mutex_init(&mcounters->mcntrs_mutex); 5814 5815 return &mcounters->ibcntrs; 5816 } 5817 5818 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5819 { 5820 mlx5_ib_cleanup_multiport_master(dev); 5821 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 5822 srcu_barrier(&dev->mr_srcu); 5823 cleanup_srcu_struct(&dev->mr_srcu); 5824 } 5825 kfree(dev->port); 5826 } 5827 5828 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5829 { 5830 struct mlx5_core_dev *mdev = dev->mdev; 5831 int err; 5832 int i; 5833 5834 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5835 GFP_KERNEL); 5836 if (!dev->port) 5837 return -ENOMEM; 5838 5839 for (i = 0; i < dev->num_ports; i++) { 5840 spin_lock_init(&dev->port[i].mp.mpi_lock); 5841 rwlock_init(&dev->roce[i].netdev_lock); 5842 } 5843 5844 err = mlx5_ib_init_multiport_master(dev); 5845 if (err) 5846 goto err_free_port; 5847 5848 if (!mlx5_core_mp_enabled(mdev)) { 5849 for (i = 1; i <= dev->num_ports; i++) { 5850 err = get_port_caps(dev, i); 5851 if (err) 5852 break; 5853 } 5854 } else { 5855 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5856 } 5857 if (err) 5858 goto err_mp; 5859 5860 if (mlx5_use_mad_ifc(dev)) 5861 get_ext_port_caps(dev); 5862 5863 dev->ib_dev.owner = THIS_MODULE; 5864 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5865 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5866 dev->ib_dev.phys_port_cnt = dev->num_ports; 5867 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 5868 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5869 5870 mutex_init(&dev->cap_mask_mutex); 5871 INIT_LIST_HEAD(&dev->qp_list); 5872 spin_lock_init(&dev->reset_flow_resource_lock); 5873 5874 spin_lock_init(&dev->memic.memic_lock); 5875 dev->memic.dev = mdev; 5876 5877 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 5878 err = init_srcu_struct(&dev->mr_srcu); 5879 if (err) 5880 goto err_mp; 5881 } 5882 5883 return 0; 5884 err_mp: 5885 mlx5_ib_cleanup_multiport_master(dev); 5886 5887 err_free_port: 5888 kfree(dev->port); 5889 5890 return -ENOMEM; 5891 } 5892 5893 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5894 { 5895 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5896 5897 if (!dev->flow_db) 5898 return -ENOMEM; 5899 5900 mutex_init(&dev->flow_db->lock); 5901 5902 return 0; 5903 } 5904 5905 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5906 { 5907 struct mlx5_ib_dev *nic_dev; 5908 5909 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5910 5911 if (!nic_dev) 5912 return -EINVAL; 5913 5914 dev->flow_db = nic_dev->flow_db; 5915 5916 return 0; 5917 } 5918 5919 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5920 { 5921 kfree(dev->flow_db); 5922 } 5923 5924 static const struct ib_device_ops mlx5_ib_dev_ops = { 5925 .add_gid = mlx5_ib_add_gid, 5926 .alloc_mr = mlx5_ib_alloc_mr, 5927 .alloc_pd = mlx5_ib_alloc_pd, 5928 .alloc_ucontext = mlx5_ib_alloc_ucontext, 5929 .attach_mcast = mlx5_ib_mcg_attach, 5930 .check_mr_status = mlx5_ib_check_mr_status, 5931 .create_ah = mlx5_ib_create_ah, 5932 .create_counters = mlx5_ib_create_counters, 5933 .create_cq = mlx5_ib_create_cq, 5934 .create_flow = mlx5_ib_create_flow, 5935 .create_qp = mlx5_ib_create_qp, 5936 .create_srq = mlx5_ib_create_srq, 5937 .dealloc_pd = mlx5_ib_dealloc_pd, 5938 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 5939 .del_gid = mlx5_ib_del_gid, 5940 .dereg_mr = mlx5_ib_dereg_mr, 5941 .destroy_ah = mlx5_ib_destroy_ah, 5942 .destroy_counters = mlx5_ib_destroy_counters, 5943 .destroy_cq = mlx5_ib_destroy_cq, 5944 .destroy_flow = mlx5_ib_destroy_flow, 5945 .destroy_flow_action = mlx5_ib_destroy_flow_action, 5946 .destroy_qp = mlx5_ib_destroy_qp, 5947 .destroy_srq = mlx5_ib_destroy_srq, 5948 .detach_mcast = mlx5_ib_mcg_detach, 5949 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 5950 .drain_rq = mlx5_ib_drain_rq, 5951 .drain_sq = mlx5_ib_drain_sq, 5952 .get_dev_fw_str = get_dev_fw_str, 5953 .get_dma_mr = mlx5_ib_get_dma_mr, 5954 .get_link_layer = mlx5_ib_port_link_layer, 5955 .map_mr_sg = mlx5_ib_map_mr_sg, 5956 .mmap = mlx5_ib_mmap, 5957 .modify_cq = mlx5_ib_modify_cq, 5958 .modify_device = mlx5_ib_modify_device, 5959 .modify_port = mlx5_ib_modify_port, 5960 .modify_qp = mlx5_ib_modify_qp, 5961 .modify_srq = mlx5_ib_modify_srq, 5962 .poll_cq = mlx5_ib_poll_cq, 5963 .post_recv = mlx5_ib_post_recv, 5964 .post_send = mlx5_ib_post_send, 5965 .post_srq_recv = mlx5_ib_post_srq_recv, 5966 .process_mad = mlx5_ib_process_mad, 5967 .query_ah = mlx5_ib_query_ah, 5968 .query_device = mlx5_ib_query_device, 5969 .query_gid = mlx5_ib_query_gid, 5970 .query_pkey = mlx5_ib_query_pkey, 5971 .query_qp = mlx5_ib_query_qp, 5972 .query_srq = mlx5_ib_query_srq, 5973 .read_counters = mlx5_ib_read_counters, 5974 .reg_user_mr = mlx5_ib_reg_user_mr, 5975 .req_notify_cq = mlx5_ib_arm_cq, 5976 .rereg_user_mr = mlx5_ib_rereg_user_mr, 5977 .resize_cq = mlx5_ib_resize_cq, 5978 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 5979 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 5980 }; 5981 5982 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = { 5983 .create_flow_action_esp = mlx5_ib_create_flow_action_esp, 5984 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp, 5985 }; 5986 5987 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 5988 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 5989 }; 5990 5991 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 5992 .get_vf_config = mlx5_ib_get_vf_config, 5993 .get_vf_stats = mlx5_ib_get_vf_stats, 5994 .set_vf_guid = mlx5_ib_set_vf_guid, 5995 .set_vf_link_state = mlx5_ib_set_vf_link_state, 5996 }; 5997 5998 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 5999 .alloc_mw = mlx5_ib_alloc_mw, 6000 .dealloc_mw = mlx5_ib_dealloc_mw, 6001 }; 6002 6003 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 6004 .alloc_xrcd = mlx5_ib_alloc_xrcd, 6005 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 6006 }; 6007 6008 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 6009 .alloc_dm = mlx5_ib_alloc_dm, 6010 .dealloc_dm = mlx5_ib_dealloc_dm, 6011 .reg_dm_mr = mlx5_ib_reg_dm_mr, 6012 }; 6013 6014 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 6015 { 6016 struct mlx5_core_dev *mdev = dev->mdev; 6017 int err; 6018 6019 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 6020 dev->ib_dev.uverbs_cmd_mask = 6021 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 6022 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 6023 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 6024 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 6025 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 6026 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 6027 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 6028 (1ull << IB_USER_VERBS_CMD_REG_MR) | 6029 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 6030 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 6031 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 6032 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 6033 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 6034 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 6035 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 6036 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 6037 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 6038 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 6039 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 6040 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 6041 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 6042 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 6043 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 6044 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 6045 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 6046 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 6047 dev->ib_dev.uverbs_ex_cmd_mask = 6048 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 6049 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 6050 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 6051 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 6052 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 6053 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 6054 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 6055 6056 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 6057 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 6058 ib_set_device_ops(&dev->ib_dev, 6059 &mlx5_ib_dev_ipoib_enhanced_ops); 6060 6061 if (mlx5_core_is_pf(mdev)) 6062 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 6063 6064 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 6065 6066 if (MLX5_CAP_GEN(mdev, imaicl)) { 6067 dev->ib_dev.uverbs_cmd_mask |= 6068 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 6069 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 6070 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 6071 } 6072 6073 if (MLX5_CAP_GEN(mdev, xrc)) { 6074 dev->ib_dev.uverbs_cmd_mask |= 6075 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 6076 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 6077 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 6078 } 6079 6080 if (MLX5_CAP_DEV_MEM(mdev, memic)) 6081 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 6082 6083 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 6084 MLX5_ACCEL_IPSEC_CAP_DEVICE) 6085 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops); 6086 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 6087 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 6088 6089 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 6090 dev->ib_dev.driver_def = mlx5_ib_defs; 6091 6092 err = init_node_data(dev); 6093 if (err) 6094 return err; 6095 6096 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 6097 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 6098 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 6099 mutex_init(&dev->lb.mutex); 6100 6101 return 0; 6102 } 6103 6104 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 6105 .get_port_immutable = mlx5_port_immutable, 6106 .query_port = mlx5_ib_query_port, 6107 }; 6108 6109 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 6110 { 6111 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 6112 return 0; 6113 } 6114 6115 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 6116 .get_port_immutable = mlx5_port_rep_immutable, 6117 .query_port = mlx5_ib_rep_query_port, 6118 }; 6119 6120 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 6121 { 6122 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 6123 return 0; 6124 } 6125 6126 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 6127 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 6128 .create_wq = mlx5_ib_create_wq, 6129 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 6130 .destroy_wq = mlx5_ib_destroy_wq, 6131 .get_netdev = mlx5_ib_get_netdev, 6132 .modify_wq = mlx5_ib_modify_wq, 6133 }; 6134 6135 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 6136 { 6137 u8 port_num; 6138 int i; 6139 6140 for (i = 0; i < dev->num_ports; i++) { 6141 dev->roce[i].dev = dev; 6142 dev->roce[i].native_port_num = i + 1; 6143 dev->roce[i].last_port_state = IB_PORT_DOWN; 6144 } 6145 6146 dev->ib_dev.uverbs_ex_cmd_mask |= 6147 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 6148 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 6149 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 6150 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 6151 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 6152 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 6153 6154 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6155 6156 return mlx5_add_netdev_notifier(dev, port_num); 6157 } 6158 6159 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 6160 { 6161 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6162 6163 mlx5_remove_netdev_notifier(dev, port_num); 6164 } 6165 6166 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 6167 { 6168 struct mlx5_core_dev *mdev = dev->mdev; 6169 enum rdma_link_layer ll; 6170 int port_type_cap; 6171 int err = 0; 6172 6173 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6174 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6175 6176 if (ll == IB_LINK_LAYER_ETHERNET) 6177 err = mlx5_ib_stage_common_roce_init(dev); 6178 6179 return err; 6180 } 6181 6182 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 6183 { 6184 mlx5_ib_stage_common_roce_cleanup(dev); 6185 } 6186 6187 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 6188 { 6189 struct mlx5_core_dev *mdev = dev->mdev; 6190 enum rdma_link_layer ll; 6191 int port_type_cap; 6192 int err; 6193 6194 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6195 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6196 6197 if (ll == IB_LINK_LAYER_ETHERNET) { 6198 err = mlx5_ib_stage_common_roce_init(dev); 6199 if (err) 6200 return err; 6201 6202 err = mlx5_enable_eth(dev); 6203 if (err) 6204 goto cleanup; 6205 } 6206 6207 return 0; 6208 cleanup: 6209 mlx5_ib_stage_common_roce_cleanup(dev); 6210 6211 return err; 6212 } 6213 6214 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6215 { 6216 struct mlx5_core_dev *mdev = dev->mdev; 6217 enum rdma_link_layer ll; 6218 int port_type_cap; 6219 6220 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6221 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6222 6223 if (ll == IB_LINK_LAYER_ETHERNET) { 6224 mlx5_disable_eth(dev); 6225 mlx5_ib_stage_common_roce_cleanup(dev); 6226 } 6227 } 6228 6229 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6230 { 6231 return create_dev_resources(&dev->devr); 6232 } 6233 6234 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6235 { 6236 destroy_dev_resources(&dev->devr); 6237 } 6238 6239 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6240 { 6241 mlx5_ib_internal_fill_odp_caps(dev); 6242 6243 return mlx5_ib_odp_init_one(dev); 6244 } 6245 6246 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 6247 { 6248 mlx5_ib_odp_cleanup_one(dev); 6249 } 6250 6251 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = { 6252 .alloc_hw_stats = mlx5_ib_alloc_hw_stats, 6253 .get_hw_stats = mlx5_ib_get_hw_stats, 6254 }; 6255 6256 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6257 { 6258 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6259 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops); 6260 6261 return mlx5_ib_alloc_counters(dev); 6262 } 6263 6264 return 0; 6265 } 6266 6267 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6268 { 6269 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6270 mlx5_ib_dealloc_counters(dev); 6271 } 6272 6273 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6274 { 6275 mlx5_ib_init_cong_debugfs(dev, 6276 mlx5_core_native_port_num(dev->mdev) - 1); 6277 return 0; 6278 } 6279 6280 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6281 { 6282 mlx5_ib_cleanup_cong_debugfs(dev, 6283 mlx5_core_native_port_num(dev->mdev) - 1); 6284 } 6285 6286 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6287 { 6288 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6289 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6290 } 6291 6292 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6293 { 6294 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6295 } 6296 6297 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6298 { 6299 int err; 6300 6301 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6302 if (err) 6303 return err; 6304 6305 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6306 if (err) 6307 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6308 6309 return err; 6310 } 6311 6312 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6313 { 6314 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6315 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6316 } 6317 6318 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6319 { 6320 const char *name; 6321 6322 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 6323 if (!mlx5_lag_is_roce(dev->mdev)) 6324 name = "mlx5_%d"; 6325 else 6326 name = "mlx5_bond_%d"; 6327 return ib_register_device(&dev->ib_dev, name); 6328 } 6329 6330 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6331 { 6332 destroy_umrc_res(dev); 6333 } 6334 6335 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6336 { 6337 ib_unregister_device(&dev->ib_dev); 6338 } 6339 6340 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6341 { 6342 return create_umr_res(dev); 6343 } 6344 6345 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6346 { 6347 init_delay_drop(dev); 6348 6349 return 0; 6350 } 6351 6352 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6353 { 6354 cancel_delay_drop(dev); 6355 } 6356 6357 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 6358 { 6359 dev->mdev_events.notifier_call = mlx5_ib_event; 6360 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 6361 return 0; 6362 } 6363 6364 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 6365 { 6366 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 6367 } 6368 6369 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev) 6370 { 6371 int uid; 6372 6373 uid = mlx5_ib_devx_create(dev, false); 6374 if (uid > 0) 6375 dev->devx_whitelist_uid = uid; 6376 6377 return 0; 6378 } 6379 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev) 6380 { 6381 if (dev->devx_whitelist_uid) 6382 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 6383 } 6384 6385 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6386 const struct mlx5_ib_profile *profile, 6387 int stage) 6388 { 6389 /* Number of stages to cleanup */ 6390 while (stage) { 6391 stage--; 6392 if (profile->stage[stage].cleanup) 6393 profile->stage[stage].cleanup(dev); 6394 } 6395 } 6396 6397 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6398 const struct mlx5_ib_profile *profile) 6399 { 6400 int err; 6401 int i; 6402 6403 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6404 if (profile->stage[i].init) { 6405 err = profile->stage[i].init(dev); 6406 if (err) 6407 goto err_out; 6408 } 6409 } 6410 6411 dev->profile = profile; 6412 dev->ib_active = true; 6413 6414 return dev; 6415 6416 err_out: 6417 __mlx5_ib_remove(dev, profile, i); 6418 6419 return NULL; 6420 } 6421 6422 static const struct mlx5_ib_profile pf_profile = { 6423 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6424 mlx5_ib_stage_init_init, 6425 mlx5_ib_stage_init_cleanup), 6426 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6427 mlx5_ib_stage_flow_db_init, 6428 mlx5_ib_stage_flow_db_cleanup), 6429 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6430 mlx5_ib_stage_caps_init, 6431 NULL), 6432 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6433 mlx5_ib_stage_non_default_cb, 6434 NULL), 6435 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6436 mlx5_ib_stage_roce_init, 6437 mlx5_ib_stage_roce_cleanup), 6438 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6439 mlx5_init_srq_table, 6440 mlx5_cleanup_srq_table), 6441 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6442 mlx5_ib_stage_dev_res_init, 6443 mlx5_ib_stage_dev_res_cleanup), 6444 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6445 mlx5_ib_stage_dev_notifier_init, 6446 mlx5_ib_stage_dev_notifier_cleanup), 6447 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6448 mlx5_ib_stage_odp_init, 6449 mlx5_ib_stage_odp_cleanup), 6450 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6451 mlx5_ib_stage_counters_init, 6452 mlx5_ib_stage_counters_cleanup), 6453 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6454 mlx5_ib_stage_cong_debugfs_init, 6455 mlx5_ib_stage_cong_debugfs_cleanup), 6456 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6457 mlx5_ib_stage_uar_init, 6458 mlx5_ib_stage_uar_cleanup), 6459 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6460 mlx5_ib_stage_bfrag_init, 6461 mlx5_ib_stage_bfrag_cleanup), 6462 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6463 NULL, 6464 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6465 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 6466 mlx5_ib_stage_devx_init, 6467 mlx5_ib_stage_devx_cleanup), 6468 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6469 mlx5_ib_stage_ib_reg_init, 6470 mlx5_ib_stage_ib_reg_cleanup), 6471 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6472 mlx5_ib_stage_post_ib_reg_umr_init, 6473 NULL), 6474 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6475 mlx5_ib_stage_delay_drop_init, 6476 mlx5_ib_stage_delay_drop_cleanup), 6477 }; 6478 6479 const struct mlx5_ib_profile uplink_rep_profile = { 6480 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6481 mlx5_ib_stage_init_init, 6482 mlx5_ib_stage_init_cleanup), 6483 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6484 mlx5_ib_stage_flow_db_init, 6485 mlx5_ib_stage_flow_db_cleanup), 6486 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6487 mlx5_ib_stage_caps_init, 6488 NULL), 6489 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6490 mlx5_ib_stage_rep_non_default_cb, 6491 NULL), 6492 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6493 mlx5_ib_stage_rep_roce_init, 6494 mlx5_ib_stage_rep_roce_cleanup), 6495 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6496 mlx5_init_srq_table, 6497 mlx5_cleanup_srq_table), 6498 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6499 mlx5_ib_stage_dev_res_init, 6500 mlx5_ib_stage_dev_res_cleanup), 6501 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6502 mlx5_ib_stage_dev_notifier_init, 6503 mlx5_ib_stage_dev_notifier_cleanup), 6504 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6505 mlx5_ib_stage_counters_init, 6506 mlx5_ib_stage_counters_cleanup), 6507 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6508 mlx5_ib_stage_uar_init, 6509 mlx5_ib_stage_uar_cleanup), 6510 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6511 mlx5_ib_stage_bfrag_init, 6512 mlx5_ib_stage_bfrag_cleanup), 6513 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6514 NULL, 6515 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6516 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6517 mlx5_ib_stage_ib_reg_init, 6518 mlx5_ib_stage_ib_reg_cleanup), 6519 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6520 mlx5_ib_stage_post_ib_reg_umr_init, 6521 NULL), 6522 }; 6523 6524 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6525 { 6526 struct mlx5_ib_multiport_info *mpi; 6527 struct mlx5_ib_dev *dev; 6528 bool bound = false; 6529 int err; 6530 6531 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6532 if (!mpi) 6533 return NULL; 6534 6535 mpi->mdev = mdev; 6536 6537 err = mlx5_query_nic_vport_system_image_guid(mdev, 6538 &mpi->sys_image_guid); 6539 if (err) { 6540 kfree(mpi); 6541 return NULL; 6542 } 6543 6544 mutex_lock(&mlx5_ib_multiport_mutex); 6545 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6546 if (dev->sys_image_guid == mpi->sys_image_guid) 6547 bound = mlx5_ib_bind_slave_port(dev, mpi); 6548 6549 if (bound) { 6550 rdma_roce_rescan_device(&dev->ib_dev); 6551 break; 6552 } 6553 } 6554 6555 if (!bound) { 6556 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6557 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6558 } 6559 mutex_unlock(&mlx5_ib_multiport_mutex); 6560 6561 return mpi; 6562 } 6563 6564 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6565 { 6566 enum rdma_link_layer ll; 6567 struct mlx5_ib_dev *dev; 6568 int port_type_cap; 6569 6570 printk_once(KERN_INFO "%s", mlx5_version); 6571 6572 if (MLX5_ESWITCH_MANAGER(mdev) && 6573 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6574 mlx5_ib_register_vport_reps(mdev); 6575 return mdev; 6576 } 6577 6578 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6579 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6580 6581 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6582 return mlx5_ib_add_slave_port(mdev); 6583 6584 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 6585 if (!dev) 6586 return NULL; 6587 6588 dev->mdev = mdev; 6589 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6590 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6591 6592 return __mlx5_ib_add(dev, &pf_profile); 6593 } 6594 6595 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6596 { 6597 struct mlx5_ib_multiport_info *mpi; 6598 struct mlx5_ib_dev *dev; 6599 6600 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 6601 mlx5_ib_unregister_vport_reps(mdev); 6602 return; 6603 } 6604 6605 if (mlx5_core_is_mp_slave(mdev)) { 6606 mpi = context; 6607 mutex_lock(&mlx5_ib_multiport_mutex); 6608 if (mpi->ibdev) 6609 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6610 list_del(&mpi->list); 6611 mutex_unlock(&mlx5_ib_multiport_mutex); 6612 return; 6613 } 6614 6615 dev = context; 6616 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6617 6618 ib_dealloc_device((struct ib_device *)dev); 6619 } 6620 6621 static struct mlx5_interface mlx5_ib_interface = { 6622 .add = mlx5_ib_add, 6623 .remove = mlx5_ib_remove, 6624 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6625 }; 6626 6627 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6628 { 6629 mutex_lock(&xlt_emergency_page_mutex); 6630 return xlt_emergency_page; 6631 } 6632 6633 void mlx5_ib_put_xlt_emergency_page(void) 6634 { 6635 mutex_unlock(&xlt_emergency_page_mutex); 6636 } 6637 6638 static int __init mlx5_ib_init(void) 6639 { 6640 int err; 6641 6642 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6643 if (!xlt_emergency_page) 6644 return -ENOMEM; 6645 6646 mutex_init(&xlt_emergency_page_mutex); 6647 6648 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6649 if (!mlx5_ib_event_wq) { 6650 free_page(xlt_emergency_page); 6651 return -ENOMEM; 6652 } 6653 6654 mlx5_ib_odp_init(); 6655 6656 err = mlx5_register_interface(&mlx5_ib_interface); 6657 6658 return err; 6659 } 6660 6661 static void __exit mlx5_ib_cleanup(void) 6662 { 6663 mlx5_unregister_interface(&mlx5_ib_interface); 6664 destroy_workqueue(mlx5_ib_event_wq); 6665 mutex_destroy(&xlt_emergency_page_mutex); 6666 free_page(xlt_emergency_page); 6667 } 6668 6669 module_init(mlx5_ib_init); 6670 module_exit(mlx5_ib_cleanup); 6671