1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem_odp.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include "umr.h" 45 #include <rdma/uverbs_std_types.h> 46 #include <rdma/uverbs_ioctl.h> 47 #include <rdma/mlx5_user_ioctl_verbs.h> 48 #include <rdma/mlx5_user_ioctl_cmds.h> 49 #include "macsec.h" 50 51 #define UVERBS_MODULE_NAME mlx5_ib 52 #include <rdma/uverbs_named_ioctl.h> 53 54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 56 MODULE_LICENSE("Dual BSD/GPL"); 57 58 struct mlx5_ib_event_work { 59 struct work_struct work; 60 union { 61 struct mlx5_ib_dev *dev; 62 struct mlx5_ib_multiport_info *mpi; 63 }; 64 bool is_slave; 65 unsigned int event; 66 void *param; 67 }; 68 69 enum { 70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 71 }; 72 73 static struct workqueue_struct *mlx5_ib_event_wq; 74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 75 static LIST_HEAD(mlx5_ib_dev_list); 76 /* 77 * This mutex should be held when accessing either of the above lists 78 */ 79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 80 81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 82 { 83 struct mlx5_ib_dev *dev; 84 85 mutex_lock(&mlx5_ib_multiport_mutex); 86 dev = mpi->ibdev; 87 mutex_unlock(&mlx5_ib_multiport_mutex); 88 return dev; 89 } 90 91 static enum rdma_link_layer 92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 93 { 94 switch (port_type_cap) { 95 case MLX5_CAP_PORT_TYPE_IB: 96 return IB_LINK_LAYER_INFINIBAND; 97 case MLX5_CAP_PORT_TYPE_ETH: 98 return IB_LINK_LAYER_ETHERNET; 99 default: 100 return IB_LINK_LAYER_UNSPECIFIED; 101 } 102 } 103 104 static enum rdma_link_layer 105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 106 { 107 struct mlx5_ib_dev *dev = to_mdev(device); 108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 109 110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 111 } 112 113 static int get_port_state(struct ib_device *ibdev, 114 u32 port_num, 115 enum ib_port_state *state) 116 { 117 struct ib_port_attr attr; 118 int ret; 119 120 memset(&attr, 0, sizeof(attr)); 121 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 122 if (!ret) 123 *state = attr.state; 124 return ret; 125 } 126 127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 128 struct net_device *ndev, 129 struct net_device *upper, 130 u32 *port_num) 131 { 132 struct net_device *rep_ndev; 133 struct mlx5_ib_port *port; 134 int i; 135 136 for (i = 0; i < dev->num_ports; i++) { 137 port = &dev->port[i]; 138 if (!port->rep) 139 continue; 140 141 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 142 *port_num = i + 1; 143 return &port->roce; 144 } 145 146 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 147 continue; 148 149 read_lock(&port->roce.netdev_lock); 150 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 151 port->rep->vport); 152 if (rep_ndev == ndev) { 153 read_unlock(&port->roce.netdev_lock); 154 *port_num = i + 1; 155 return &port->roce; 156 } 157 read_unlock(&port->roce.netdev_lock); 158 } 159 160 return NULL; 161 } 162 163 static int mlx5_netdev_event(struct notifier_block *this, 164 unsigned long event, void *ptr) 165 { 166 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 167 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 168 u32 port_num = roce->native_port_num; 169 struct mlx5_core_dev *mdev; 170 struct mlx5_ib_dev *ibdev; 171 172 ibdev = roce->dev; 173 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 174 if (!mdev) 175 return NOTIFY_DONE; 176 177 switch (event) { 178 case NETDEV_REGISTER: 179 /* Should already be registered during the load */ 180 if (ibdev->is_rep) 181 break; 182 write_lock(&roce->netdev_lock); 183 if (ndev->dev.parent == mdev->device) 184 roce->netdev = ndev; 185 write_unlock(&roce->netdev_lock); 186 break; 187 188 case NETDEV_UNREGISTER: 189 /* In case of reps, ib device goes away before the netdevs */ 190 write_lock(&roce->netdev_lock); 191 if (roce->netdev == ndev) 192 roce->netdev = NULL; 193 write_unlock(&roce->netdev_lock); 194 break; 195 196 case NETDEV_CHANGE: 197 case NETDEV_UP: 198 case NETDEV_DOWN: { 199 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 200 struct net_device *upper = NULL; 201 202 if (lag_ndev) { 203 upper = netdev_master_upper_dev_get(lag_ndev); 204 dev_put(lag_ndev); 205 } 206 207 if (ibdev->is_rep) 208 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 209 if (!roce) 210 return NOTIFY_DONE; 211 if ((upper == ndev || 212 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 213 ibdev->ib_active) { 214 struct ib_event ibev = { }; 215 enum ib_port_state port_state; 216 217 if (get_port_state(&ibdev->ib_dev, port_num, 218 &port_state)) 219 goto done; 220 221 if (roce->last_port_state == port_state) 222 goto done; 223 224 roce->last_port_state = port_state; 225 ibev.device = &ibdev->ib_dev; 226 if (port_state == IB_PORT_DOWN) 227 ibev.event = IB_EVENT_PORT_ERR; 228 else if (port_state == IB_PORT_ACTIVE) 229 ibev.event = IB_EVENT_PORT_ACTIVE; 230 else 231 goto done; 232 233 ibev.element.port_num = port_num; 234 ib_dispatch_event(&ibev); 235 } 236 break; 237 } 238 239 default: 240 break; 241 } 242 done: 243 mlx5_ib_put_native_port_mdev(ibdev, port_num); 244 return NOTIFY_DONE; 245 } 246 247 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 248 u32 port_num) 249 { 250 struct mlx5_ib_dev *ibdev = to_mdev(device); 251 struct net_device *ndev; 252 struct mlx5_core_dev *mdev; 253 254 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 255 if (!mdev) 256 return NULL; 257 258 ndev = mlx5_lag_get_roce_netdev(mdev); 259 if (ndev) 260 goto out; 261 262 /* Ensure ndev does not disappear before we invoke dev_hold() 263 */ 264 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 265 ndev = ibdev->port[port_num - 1].roce.netdev; 266 if (ndev) 267 dev_hold(ndev); 268 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 269 270 out: 271 mlx5_ib_put_native_port_mdev(ibdev, port_num); 272 return ndev; 273 } 274 275 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 276 u32 ib_port_num, 277 u32 *native_port_num) 278 { 279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 280 ib_port_num); 281 struct mlx5_core_dev *mdev = NULL; 282 struct mlx5_ib_multiport_info *mpi; 283 struct mlx5_ib_port *port; 284 285 if (!mlx5_core_mp_enabled(ibdev->mdev) || 286 ll != IB_LINK_LAYER_ETHERNET) { 287 if (native_port_num) 288 *native_port_num = ib_port_num; 289 return ibdev->mdev; 290 } 291 292 if (native_port_num) 293 *native_port_num = 1; 294 295 port = &ibdev->port[ib_port_num - 1]; 296 spin_lock(&port->mp.mpi_lock); 297 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 298 if (mpi && !mpi->unaffiliate) { 299 mdev = mpi->mdev; 300 /* If it's the master no need to refcount, it'll exist 301 * as long as the ib_dev exists. 302 */ 303 if (!mpi->is_master) 304 mpi->mdev_refcnt++; 305 } 306 spin_unlock(&port->mp.mpi_lock); 307 308 return mdev; 309 } 310 311 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 312 { 313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 314 port_num); 315 struct mlx5_ib_multiport_info *mpi; 316 struct mlx5_ib_port *port; 317 318 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 319 return; 320 321 port = &ibdev->port[port_num - 1]; 322 323 spin_lock(&port->mp.mpi_lock); 324 mpi = ibdev->port[port_num - 1].mp.mpi; 325 if (mpi->is_master) 326 goto out; 327 328 mpi->mdev_refcnt--; 329 if (mpi->unaffiliate) 330 complete(&mpi->unref_comp); 331 out: 332 spin_unlock(&port->mp.mpi_lock); 333 } 334 335 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 336 u16 *active_speed, u8 *active_width) 337 { 338 switch (eth_proto_oper) { 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 340 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 341 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 342 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 343 *active_width = IB_WIDTH_1X; 344 *active_speed = IB_SPEED_SDR; 345 break; 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 352 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 353 *active_width = IB_WIDTH_1X; 354 *active_speed = IB_SPEED_QDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 358 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 359 *active_width = IB_WIDTH_1X; 360 *active_speed = IB_SPEED_EDR; 361 break; 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 365 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 366 *active_width = IB_WIDTH_4X; 367 *active_speed = IB_SPEED_QDR; 368 break; 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 371 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 372 *active_width = IB_WIDTH_1X; 373 *active_speed = IB_SPEED_HDR; 374 break; 375 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 376 *active_width = IB_WIDTH_4X; 377 *active_speed = IB_SPEED_FDR; 378 break; 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 382 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 383 *active_width = IB_WIDTH_4X; 384 *active_speed = IB_SPEED_EDR; 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 return 0; 391 } 392 393 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 394 u8 *active_width) 395 { 396 switch (eth_proto_oper) { 397 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 398 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 399 *active_width = IB_WIDTH_1X; 400 *active_speed = IB_SPEED_SDR; 401 break; 402 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_DDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 407 *active_width = IB_WIDTH_1X; 408 *active_speed = IB_SPEED_QDR; 409 break; 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 415 *active_width = IB_WIDTH_1X; 416 *active_speed = IB_SPEED_EDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 419 *active_width = IB_WIDTH_2X; 420 *active_speed = IB_SPEED_EDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 423 *active_width = IB_WIDTH_1X; 424 *active_speed = IB_SPEED_HDR; 425 break; 426 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 431 *active_width = IB_WIDTH_2X; 432 *active_speed = IB_SPEED_HDR; 433 break; 434 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 435 *active_width = IB_WIDTH_1X; 436 *active_speed = IB_SPEED_NDR; 437 break; 438 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 439 *active_width = IB_WIDTH_4X; 440 *active_speed = IB_SPEED_HDR; 441 break; 442 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 443 *active_width = IB_WIDTH_2X; 444 *active_speed = IB_SPEED_NDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_400GAUI_8): 447 *active_width = IB_WIDTH_8X; 448 *active_speed = IB_SPEED_HDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 451 *active_width = IB_WIDTH_4X; 452 *active_speed = IB_SPEED_NDR; 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 462 u8 *active_width, bool ext) 463 { 464 return ext ? 465 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 466 active_width) : 467 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 468 active_width); 469 } 470 471 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 472 struct ib_port_attr *props) 473 { 474 struct mlx5_ib_dev *dev = to_mdev(device); 475 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 476 struct mlx5_core_dev *mdev; 477 struct net_device *ndev, *upper; 478 enum ib_mtu ndev_ib_mtu; 479 bool put_mdev = true; 480 u32 eth_prot_oper; 481 u32 mdev_port_num; 482 bool ext; 483 int err; 484 485 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 486 if (!mdev) { 487 /* This means the port isn't affiliated yet. Get the 488 * info for the master port instead. 489 */ 490 put_mdev = false; 491 mdev = dev->mdev; 492 mdev_port_num = 1; 493 port_num = 1; 494 } 495 496 /* Possible bad flows are checked before filling out props so in case 497 * of an error it will still be zeroed out. 498 * Use native port in case of reps 499 */ 500 if (dev->is_rep) 501 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 502 1); 503 else 504 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 505 mdev_port_num); 506 if (err) 507 goto out; 508 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 509 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 510 511 props->active_width = IB_WIDTH_4X; 512 props->active_speed = IB_SPEED_QDR; 513 514 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 515 &props->active_width, ext); 516 517 if (!dev->is_rep && dev->mdev->roce.roce_en) { 518 u16 qkey_viol_cntr; 519 520 props->port_cap_flags |= IB_PORT_CM_SUP; 521 props->ip_gids = true; 522 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 523 roce_address_table_size); 524 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 525 props->qkey_viol_cntr = qkey_viol_cntr; 526 } 527 props->max_mtu = IB_MTU_4096; 528 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 529 props->pkey_tbl_len = 1; 530 props->state = IB_PORT_DOWN; 531 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 532 533 /* If this is a stub query for an unaffiliated port stop here */ 534 if (!put_mdev) 535 goto out; 536 537 ndev = mlx5_ib_get_netdev(device, port_num); 538 if (!ndev) 539 goto out; 540 541 if (dev->lag_active) { 542 rcu_read_lock(); 543 upper = netdev_master_upper_dev_get_rcu(ndev); 544 if (upper) { 545 dev_put(ndev); 546 ndev = upper; 547 dev_hold(ndev); 548 } 549 rcu_read_unlock(); 550 } 551 552 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 553 props->state = IB_PORT_ACTIVE; 554 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 555 } 556 557 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 558 559 dev_put(ndev); 560 561 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 562 out: 563 if (put_mdev) 564 mlx5_ib_put_native_port_mdev(dev, port_num); 565 return err; 566 } 567 568 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 569 unsigned int index, const union ib_gid *gid, 570 const struct ib_gid_attr *attr) 571 { 572 enum ib_gid_type gid_type; 573 u16 vlan_id = 0xffff; 574 u8 roce_version = 0; 575 u8 roce_l3_type = 0; 576 u8 mac[ETH_ALEN]; 577 int ret; 578 579 gid_type = attr->gid_type; 580 if (gid) { 581 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 582 if (ret) 583 return ret; 584 } 585 586 switch (gid_type) { 587 case IB_GID_TYPE_ROCE: 588 roce_version = MLX5_ROCE_VERSION_1; 589 break; 590 case IB_GID_TYPE_ROCE_UDP_ENCAP: 591 roce_version = MLX5_ROCE_VERSION_2; 592 if (gid && ipv6_addr_v4mapped((void *)gid)) 593 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 594 else 595 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 596 break; 597 598 default: 599 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 600 } 601 602 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 603 roce_l3_type, gid->raw, mac, 604 vlan_id < VLAN_CFI_MASK, vlan_id, 605 port_num); 606 } 607 608 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 609 __always_unused void **context) 610 { 611 int ret; 612 613 ret = mlx5r_add_gid_macsec_operations(attr); 614 if (ret) 615 return ret; 616 617 return set_roce_addr(to_mdev(attr->device), attr->port_num, 618 attr->index, &attr->gid, attr); 619 } 620 621 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 622 __always_unused void **context) 623 { 624 int ret; 625 626 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 627 attr->index, NULL, attr); 628 if (ret) 629 return ret; 630 631 mlx5r_del_gid_macsec_operations(attr); 632 return 0; 633 } 634 635 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 636 const struct ib_gid_attr *attr) 637 { 638 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 639 return 0; 640 641 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 642 } 643 644 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 645 { 646 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 647 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 648 return 0; 649 } 650 651 enum { 652 MLX5_VPORT_ACCESS_METHOD_MAD, 653 MLX5_VPORT_ACCESS_METHOD_HCA, 654 MLX5_VPORT_ACCESS_METHOD_NIC, 655 }; 656 657 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 658 { 659 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 660 return MLX5_VPORT_ACCESS_METHOD_MAD; 661 662 if (mlx5_ib_port_link_layer(ibdev, 1) == 663 IB_LINK_LAYER_ETHERNET) 664 return MLX5_VPORT_ACCESS_METHOD_NIC; 665 666 return MLX5_VPORT_ACCESS_METHOD_HCA; 667 } 668 669 static void get_atomic_caps(struct mlx5_ib_dev *dev, 670 u8 atomic_size_qp, 671 struct ib_device_attr *props) 672 { 673 u8 tmp; 674 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 675 u8 atomic_req_8B_endianness_mode = 676 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 677 678 /* Check if HW supports 8 bytes standard atomic operations and capable 679 * of host endianness respond 680 */ 681 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 682 if (((atomic_operations & tmp) == tmp) && 683 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 684 (atomic_req_8B_endianness_mode)) { 685 props->atomic_cap = IB_ATOMIC_HCA; 686 } else { 687 props->atomic_cap = IB_ATOMIC_NONE; 688 } 689 } 690 691 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 692 struct ib_device_attr *props) 693 { 694 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 695 696 get_atomic_caps(dev, atomic_size_qp, props); 697 } 698 699 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 700 __be64 *sys_image_guid) 701 { 702 struct mlx5_ib_dev *dev = to_mdev(ibdev); 703 struct mlx5_core_dev *mdev = dev->mdev; 704 u64 tmp; 705 int err; 706 707 switch (mlx5_get_vport_access_method(ibdev)) { 708 case MLX5_VPORT_ACCESS_METHOD_MAD: 709 return mlx5_query_mad_ifc_system_image_guid(ibdev, 710 sys_image_guid); 711 712 case MLX5_VPORT_ACCESS_METHOD_HCA: 713 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 714 break; 715 716 case MLX5_VPORT_ACCESS_METHOD_NIC: 717 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 718 break; 719 720 default: 721 return -EINVAL; 722 } 723 724 if (!err) 725 *sys_image_guid = cpu_to_be64(tmp); 726 727 return err; 728 729 } 730 731 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 732 u16 *max_pkeys) 733 { 734 struct mlx5_ib_dev *dev = to_mdev(ibdev); 735 struct mlx5_core_dev *mdev = dev->mdev; 736 737 switch (mlx5_get_vport_access_method(ibdev)) { 738 case MLX5_VPORT_ACCESS_METHOD_MAD: 739 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 740 741 case MLX5_VPORT_ACCESS_METHOD_HCA: 742 case MLX5_VPORT_ACCESS_METHOD_NIC: 743 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 744 pkey_table_size)); 745 return 0; 746 747 default: 748 return -EINVAL; 749 } 750 } 751 752 static int mlx5_query_vendor_id(struct ib_device *ibdev, 753 u32 *vendor_id) 754 { 755 struct mlx5_ib_dev *dev = to_mdev(ibdev); 756 757 switch (mlx5_get_vport_access_method(ibdev)) { 758 case MLX5_VPORT_ACCESS_METHOD_MAD: 759 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 760 761 case MLX5_VPORT_ACCESS_METHOD_HCA: 762 case MLX5_VPORT_ACCESS_METHOD_NIC: 763 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 764 765 default: 766 return -EINVAL; 767 } 768 } 769 770 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 771 __be64 *node_guid) 772 { 773 u64 tmp; 774 int err; 775 776 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 777 case MLX5_VPORT_ACCESS_METHOD_MAD: 778 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 779 780 case MLX5_VPORT_ACCESS_METHOD_HCA: 781 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 782 break; 783 784 case MLX5_VPORT_ACCESS_METHOD_NIC: 785 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 786 break; 787 788 default: 789 return -EINVAL; 790 } 791 792 if (!err) 793 *node_guid = cpu_to_be64(tmp); 794 795 return err; 796 } 797 798 struct mlx5_reg_node_desc { 799 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 800 }; 801 802 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 803 { 804 struct mlx5_reg_node_desc in; 805 806 if (mlx5_use_mad_ifc(dev)) 807 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 808 809 memset(&in, 0, sizeof(in)); 810 811 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 812 sizeof(struct mlx5_reg_node_desc), 813 MLX5_REG_NODE_DESC, 0, 0); 814 } 815 816 static int mlx5_ib_query_device(struct ib_device *ibdev, 817 struct ib_device_attr *props, 818 struct ib_udata *uhw) 819 { 820 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 821 struct mlx5_ib_dev *dev = to_mdev(ibdev); 822 struct mlx5_core_dev *mdev = dev->mdev; 823 int err = -ENOMEM; 824 int max_sq_desc; 825 int max_rq_sg; 826 int max_sq_sg; 827 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 828 bool raw_support = !mlx5_core_mp_enabled(mdev); 829 struct mlx5_ib_query_device_resp resp = {}; 830 size_t resp_len; 831 u64 max_tso; 832 833 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 834 if (uhw_outlen && uhw_outlen < resp_len) 835 return -EINVAL; 836 837 resp.response_length = resp_len; 838 839 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 840 return -EINVAL; 841 842 memset(props, 0, sizeof(*props)); 843 err = mlx5_query_system_image_guid(ibdev, 844 &props->sys_image_guid); 845 if (err) 846 return err; 847 848 props->max_pkeys = dev->pkey_table_len; 849 850 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 851 if (err) 852 return err; 853 854 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 855 (fw_rev_min(dev->mdev) << 16) | 856 fw_rev_sub(dev->mdev); 857 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 858 IB_DEVICE_PORT_ACTIVE_EVENT | 859 IB_DEVICE_SYS_IMAGE_GUID | 860 IB_DEVICE_RC_RNR_NAK_GEN; 861 862 if (MLX5_CAP_GEN(mdev, pkv)) 863 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 864 if (MLX5_CAP_GEN(mdev, qkv)) 865 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 866 if (MLX5_CAP_GEN(mdev, apm)) 867 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 868 if (MLX5_CAP_GEN(mdev, xrc)) 869 props->device_cap_flags |= IB_DEVICE_XRC; 870 if (MLX5_CAP_GEN(mdev, imaicl)) { 871 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 872 IB_DEVICE_MEM_WINDOW_TYPE_2B; 873 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 874 /* We support 'Gappy' memory registration too */ 875 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 876 } 877 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 878 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 879 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 880 if (MLX5_CAP_GEN(mdev, sho)) { 881 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 882 /* At this stage no support for signature handover */ 883 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 884 IB_PROT_T10DIF_TYPE_2 | 885 IB_PROT_T10DIF_TYPE_3; 886 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 887 IB_GUARD_T10DIF_CSUM; 888 } 889 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 890 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 891 892 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 893 if (MLX5_CAP_ETH(mdev, csum_cap)) { 894 /* Legacy bit to support old userspace libraries */ 895 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 896 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 897 } 898 899 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 900 props->raw_packet_caps |= 901 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 902 903 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 904 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 905 if (max_tso) { 906 resp.tso_caps.max_tso = 1 << max_tso; 907 resp.tso_caps.supported_qpts |= 908 1 << IB_QPT_RAW_PACKET; 909 resp.response_length += sizeof(resp.tso_caps); 910 } 911 } 912 913 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 914 resp.rss_caps.rx_hash_function = 915 MLX5_RX_HASH_FUNC_TOEPLITZ; 916 resp.rss_caps.rx_hash_fields_mask = 917 MLX5_RX_HASH_SRC_IPV4 | 918 MLX5_RX_HASH_DST_IPV4 | 919 MLX5_RX_HASH_SRC_IPV6 | 920 MLX5_RX_HASH_DST_IPV6 | 921 MLX5_RX_HASH_SRC_PORT_TCP | 922 MLX5_RX_HASH_DST_PORT_TCP | 923 MLX5_RX_HASH_SRC_PORT_UDP | 924 MLX5_RX_HASH_DST_PORT_UDP | 925 MLX5_RX_HASH_INNER; 926 resp.response_length += sizeof(resp.rss_caps); 927 } 928 } else { 929 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 930 resp.response_length += sizeof(resp.tso_caps); 931 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 932 resp.response_length += sizeof(resp.rss_caps); 933 } 934 935 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 936 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 937 props->kernel_cap_flags |= IBK_UD_TSO; 938 } 939 940 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 941 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 942 raw_support) 943 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 944 945 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 946 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 947 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 948 949 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 950 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 951 raw_support) { 952 /* Legacy bit to support old userspace libraries */ 953 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 954 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 955 } 956 957 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 958 props->max_dm_size = 959 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 960 } 961 962 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 963 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 964 965 if (MLX5_CAP_GEN(mdev, end_pad)) 966 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 967 968 props->vendor_part_id = mdev->pdev->device; 969 props->hw_ver = mdev->pdev->revision; 970 971 props->max_mr_size = ~0ull; 972 props->page_size_cap = ~(min_page_size - 1); 973 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 974 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 975 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 976 sizeof(struct mlx5_wqe_data_seg); 977 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 978 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 979 sizeof(struct mlx5_wqe_raddr_seg)) / 980 sizeof(struct mlx5_wqe_data_seg); 981 props->max_send_sge = max_sq_sg; 982 props->max_recv_sge = max_rq_sg; 983 props->max_sge_rd = MLX5_MAX_SGE_RD; 984 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 985 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 986 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 987 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 988 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 989 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 990 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 991 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 992 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 993 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 994 props->max_srq_sge = max_rq_sg - 1; 995 props->max_fast_reg_page_list_len = 996 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 997 props->max_pi_fast_reg_page_list_len = 998 props->max_fast_reg_page_list_len / 2; 999 props->max_sgl_rd = 1000 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1001 get_atomic_caps_qp(dev, props); 1002 props->masked_atomic_cap = IB_ATOMIC_NONE; 1003 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1004 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1005 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1006 props->max_mcast_grp; 1007 props->max_ah = INT_MAX; 1008 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1009 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1010 1011 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1012 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1013 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1014 props->odp_caps = dev->odp_caps; 1015 if (!uhw) { 1016 /* ODP for kernel QPs is not implemented for receive 1017 * WQEs and SRQ WQEs 1018 */ 1019 props->odp_caps.per_transport_caps.rc_odp_caps &= 1020 ~(IB_ODP_SUPPORT_READ | 1021 IB_ODP_SUPPORT_SRQ_RECV); 1022 props->odp_caps.per_transport_caps.uc_odp_caps &= 1023 ~(IB_ODP_SUPPORT_READ | 1024 IB_ODP_SUPPORT_SRQ_RECV); 1025 props->odp_caps.per_transport_caps.ud_odp_caps &= 1026 ~(IB_ODP_SUPPORT_READ | 1027 IB_ODP_SUPPORT_SRQ_RECV); 1028 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1029 ~(IB_ODP_SUPPORT_READ | 1030 IB_ODP_SUPPORT_SRQ_RECV); 1031 } 1032 } 1033 1034 if (mlx5_core_is_vf(mdev)) 1035 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1036 1037 if (mlx5_ib_port_link_layer(ibdev, 1) == 1038 IB_LINK_LAYER_ETHERNET && raw_support) { 1039 props->rss_caps.max_rwq_indirection_tables = 1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1041 props->rss_caps.max_rwq_indirection_table_size = 1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1043 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1044 props->max_wq_type_rq = 1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1046 } 1047 1048 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1049 props->tm_caps.max_num_tags = 1050 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1051 props->tm_caps.max_ops = 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1054 } 1055 1056 if (MLX5_CAP_GEN(mdev, tag_matching) && 1057 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1058 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1059 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1060 } 1061 1062 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1063 props->cq_caps.max_cq_moderation_count = 1064 MLX5_MAX_CQ_COUNT; 1065 props->cq_caps.max_cq_moderation_period = 1066 MLX5_MAX_CQ_PERIOD; 1067 } 1068 1069 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1070 resp.response_length += sizeof(resp.cqe_comp_caps); 1071 1072 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1073 resp.cqe_comp_caps.max_num = 1074 MLX5_CAP_GEN(dev->mdev, 1075 cqe_compression_max_num); 1076 1077 resp.cqe_comp_caps.supported_format = 1078 MLX5_IB_CQE_RES_FORMAT_HASH | 1079 MLX5_IB_CQE_RES_FORMAT_CSUM; 1080 1081 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1082 resp.cqe_comp_caps.supported_format |= 1083 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1084 } 1085 } 1086 1087 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1088 raw_support) { 1089 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1090 MLX5_CAP_GEN(mdev, qos)) { 1091 resp.packet_pacing_caps.qp_rate_limit_max = 1092 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1093 resp.packet_pacing_caps.qp_rate_limit_min = 1094 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1095 resp.packet_pacing_caps.supported_qpts |= 1096 1 << IB_QPT_RAW_PACKET; 1097 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1098 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1099 resp.packet_pacing_caps.cap_flags |= 1100 MLX5_IB_PP_SUPPORT_BURST; 1101 } 1102 resp.response_length += sizeof(resp.packet_pacing_caps); 1103 } 1104 1105 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1106 uhw_outlen) { 1107 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1108 resp.mlx5_ib_support_multi_pkt_send_wqes = 1109 MLX5_IB_ALLOW_MPW; 1110 1111 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1112 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1113 MLX5_IB_SUPPORT_EMPW; 1114 1115 resp.response_length += 1116 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1117 } 1118 1119 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1120 resp.response_length += sizeof(resp.flags); 1121 1122 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1123 resp.flags |= 1124 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1125 1126 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1127 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1128 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1129 resp.flags |= 1130 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1131 1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1133 } 1134 1135 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1136 resp.response_length += sizeof(resp.sw_parsing_caps); 1137 if (MLX5_CAP_ETH(mdev, swp)) { 1138 resp.sw_parsing_caps.sw_parsing_offloads |= 1139 MLX5_IB_SW_PARSING; 1140 1141 if (MLX5_CAP_ETH(mdev, swp_csum)) 1142 resp.sw_parsing_caps.sw_parsing_offloads |= 1143 MLX5_IB_SW_PARSING_CSUM; 1144 1145 if (MLX5_CAP_ETH(mdev, swp_lso)) 1146 resp.sw_parsing_caps.sw_parsing_offloads |= 1147 MLX5_IB_SW_PARSING_LSO; 1148 1149 if (resp.sw_parsing_caps.sw_parsing_offloads) 1150 resp.sw_parsing_caps.supported_qpts = 1151 BIT(IB_QPT_RAW_PACKET); 1152 } 1153 } 1154 1155 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1156 raw_support) { 1157 resp.response_length += sizeof(resp.striding_rq_caps); 1158 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1159 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1160 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1161 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1162 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1163 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1164 resp.striding_rq_caps 1165 .min_single_wqe_log_num_of_strides = 1166 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1167 else 1168 resp.striding_rq_caps 1169 .min_single_wqe_log_num_of_strides = 1170 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1171 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1172 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1173 resp.striding_rq_caps.supported_qpts = 1174 BIT(IB_QPT_RAW_PACKET); 1175 } 1176 } 1177 1178 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1179 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1180 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1181 resp.tunnel_offloads_caps |= 1182 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1183 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1184 resp.tunnel_offloads_caps |= 1185 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1186 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1187 resp.tunnel_offloads_caps |= 1188 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1189 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1190 resp.tunnel_offloads_caps |= 1191 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1192 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1193 resp.tunnel_offloads_caps |= 1194 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1195 } 1196 1197 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1198 resp.response_length += sizeof(resp.dci_streams_caps); 1199 1200 resp.dci_streams_caps.max_log_num_concurent = 1201 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1202 1203 resp.dci_streams_caps.max_log_num_errored = 1204 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1205 } 1206 1207 if (uhw_outlen) { 1208 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1209 1210 if (err) 1211 return err; 1212 } 1213 1214 return 0; 1215 } 1216 1217 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1218 u8 *ib_width) 1219 { 1220 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1221 1222 if (active_width & MLX5_PTYS_WIDTH_1X) 1223 *ib_width = IB_WIDTH_1X; 1224 else if (active_width & MLX5_PTYS_WIDTH_2X) 1225 *ib_width = IB_WIDTH_2X; 1226 else if (active_width & MLX5_PTYS_WIDTH_4X) 1227 *ib_width = IB_WIDTH_4X; 1228 else if (active_width & MLX5_PTYS_WIDTH_8X) 1229 *ib_width = IB_WIDTH_8X; 1230 else if (active_width & MLX5_PTYS_WIDTH_12X) 1231 *ib_width = IB_WIDTH_12X; 1232 else { 1233 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1234 active_width); 1235 *ib_width = IB_WIDTH_4X; 1236 } 1237 1238 return; 1239 } 1240 1241 static int mlx5_mtu_to_ib_mtu(int mtu) 1242 { 1243 switch (mtu) { 1244 case 256: return 1; 1245 case 512: return 2; 1246 case 1024: return 3; 1247 case 2048: return 4; 1248 case 4096: return 5; 1249 default: 1250 pr_warn("invalid mtu\n"); 1251 return -1; 1252 } 1253 } 1254 1255 enum ib_max_vl_num { 1256 __IB_MAX_VL_0 = 1, 1257 __IB_MAX_VL_0_1 = 2, 1258 __IB_MAX_VL_0_3 = 3, 1259 __IB_MAX_VL_0_7 = 4, 1260 __IB_MAX_VL_0_14 = 5, 1261 }; 1262 1263 enum mlx5_vl_hw_cap { 1264 MLX5_VL_HW_0 = 1, 1265 MLX5_VL_HW_0_1 = 2, 1266 MLX5_VL_HW_0_2 = 3, 1267 MLX5_VL_HW_0_3 = 4, 1268 MLX5_VL_HW_0_4 = 5, 1269 MLX5_VL_HW_0_5 = 6, 1270 MLX5_VL_HW_0_6 = 7, 1271 MLX5_VL_HW_0_7 = 8, 1272 MLX5_VL_HW_0_14 = 15 1273 }; 1274 1275 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1276 u8 *max_vl_num) 1277 { 1278 switch (vl_hw_cap) { 1279 case MLX5_VL_HW_0: 1280 *max_vl_num = __IB_MAX_VL_0; 1281 break; 1282 case MLX5_VL_HW_0_1: 1283 *max_vl_num = __IB_MAX_VL_0_1; 1284 break; 1285 case MLX5_VL_HW_0_3: 1286 *max_vl_num = __IB_MAX_VL_0_3; 1287 break; 1288 case MLX5_VL_HW_0_7: 1289 *max_vl_num = __IB_MAX_VL_0_7; 1290 break; 1291 case MLX5_VL_HW_0_14: 1292 *max_vl_num = __IB_MAX_VL_0_14; 1293 break; 1294 1295 default: 1296 return -EINVAL; 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1303 struct ib_port_attr *props) 1304 { 1305 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1306 struct mlx5_core_dev *mdev = dev->mdev; 1307 struct mlx5_hca_vport_context *rep; 1308 u16 max_mtu; 1309 u16 oper_mtu; 1310 int err; 1311 u16 ib_link_width_oper; 1312 u8 vl_hw_cap; 1313 1314 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1315 if (!rep) { 1316 err = -ENOMEM; 1317 goto out; 1318 } 1319 1320 /* props being zeroed by the caller, avoid zeroing it here */ 1321 1322 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1323 if (err) 1324 goto out; 1325 1326 props->lid = rep->lid; 1327 props->lmc = rep->lmc; 1328 props->sm_lid = rep->sm_lid; 1329 props->sm_sl = rep->sm_sl; 1330 props->state = rep->vport_state; 1331 props->phys_state = rep->port_physical_state; 1332 props->port_cap_flags = rep->cap_mask1; 1333 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1334 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1335 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1336 props->bad_pkey_cntr = rep->pkey_violation_counter; 1337 props->qkey_viol_cntr = rep->qkey_violation_counter; 1338 props->subnet_timeout = rep->subnet_timeout; 1339 props->init_type_reply = rep->init_type_reply; 1340 1341 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1342 props->port_cap_flags2 = rep->cap_mask2; 1343 1344 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1345 &props->active_speed, port); 1346 if (err) 1347 goto out; 1348 1349 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1350 1351 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1352 1353 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1354 1355 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1356 1357 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1358 1359 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1360 if (err) 1361 goto out; 1362 1363 err = translate_max_vl_num(ibdev, vl_hw_cap, 1364 &props->max_vl_num); 1365 out: 1366 kfree(rep); 1367 return err; 1368 } 1369 1370 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1371 struct ib_port_attr *props) 1372 { 1373 unsigned int count; 1374 int ret; 1375 1376 switch (mlx5_get_vport_access_method(ibdev)) { 1377 case MLX5_VPORT_ACCESS_METHOD_MAD: 1378 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1379 break; 1380 1381 case MLX5_VPORT_ACCESS_METHOD_HCA: 1382 ret = mlx5_query_hca_port(ibdev, port, props); 1383 break; 1384 1385 case MLX5_VPORT_ACCESS_METHOD_NIC: 1386 ret = mlx5_query_port_roce(ibdev, port, props); 1387 break; 1388 1389 default: 1390 ret = -EINVAL; 1391 } 1392 1393 if (!ret && props) { 1394 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1395 struct mlx5_core_dev *mdev; 1396 bool put_mdev = true; 1397 1398 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1399 if (!mdev) { 1400 /* If the port isn't affiliated yet query the master. 1401 * The master and slave will have the same values. 1402 */ 1403 mdev = dev->mdev; 1404 port = 1; 1405 put_mdev = false; 1406 } 1407 count = mlx5_core_reserved_gids_count(mdev); 1408 if (put_mdev) 1409 mlx5_ib_put_native_port_mdev(dev, port); 1410 props->gid_tbl_len -= count; 1411 } 1412 return ret; 1413 } 1414 1415 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1416 struct ib_port_attr *props) 1417 { 1418 return mlx5_query_port_roce(ibdev, port, props); 1419 } 1420 1421 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1422 u16 *pkey) 1423 { 1424 /* Default special Pkey for representor device port as per the 1425 * IB specification 1.3 section 10.9.1.2. 1426 */ 1427 *pkey = 0xffff; 1428 return 0; 1429 } 1430 1431 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1432 union ib_gid *gid) 1433 { 1434 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1435 struct mlx5_core_dev *mdev = dev->mdev; 1436 1437 switch (mlx5_get_vport_access_method(ibdev)) { 1438 case MLX5_VPORT_ACCESS_METHOD_MAD: 1439 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1440 1441 case MLX5_VPORT_ACCESS_METHOD_HCA: 1442 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1443 1444 default: 1445 return -EINVAL; 1446 } 1447 1448 } 1449 1450 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1451 u16 index, u16 *pkey) 1452 { 1453 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1454 struct mlx5_core_dev *mdev; 1455 bool put_mdev = true; 1456 u32 mdev_port_num; 1457 int err; 1458 1459 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1460 if (!mdev) { 1461 /* The port isn't affiliated yet, get the PKey from the master 1462 * port. For RoCE the PKey tables will be the same. 1463 */ 1464 put_mdev = false; 1465 mdev = dev->mdev; 1466 mdev_port_num = 1; 1467 } 1468 1469 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1470 index, pkey); 1471 if (put_mdev) 1472 mlx5_ib_put_native_port_mdev(dev, port); 1473 1474 return err; 1475 } 1476 1477 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1478 u16 *pkey) 1479 { 1480 switch (mlx5_get_vport_access_method(ibdev)) { 1481 case MLX5_VPORT_ACCESS_METHOD_MAD: 1482 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1483 1484 case MLX5_VPORT_ACCESS_METHOD_HCA: 1485 case MLX5_VPORT_ACCESS_METHOD_NIC: 1486 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1487 default: 1488 return -EINVAL; 1489 } 1490 } 1491 1492 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1493 struct ib_device_modify *props) 1494 { 1495 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1496 struct mlx5_reg_node_desc in; 1497 struct mlx5_reg_node_desc out; 1498 int err; 1499 1500 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1501 return -EOPNOTSUPP; 1502 1503 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1504 return 0; 1505 1506 /* 1507 * If possible, pass node desc to FW, so it can generate 1508 * a 144 trap. If cmd fails, just ignore. 1509 */ 1510 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1511 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1512 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1513 if (err) 1514 return err; 1515 1516 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1517 1518 return err; 1519 } 1520 1521 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1522 u32 value) 1523 { 1524 struct mlx5_hca_vport_context ctx = {}; 1525 struct mlx5_core_dev *mdev; 1526 u32 mdev_port_num; 1527 int err; 1528 1529 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1530 if (!mdev) 1531 return -ENODEV; 1532 1533 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1534 if (err) 1535 goto out; 1536 1537 if (~ctx.cap_mask1_perm & mask) { 1538 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1539 mask, ctx.cap_mask1_perm); 1540 err = -EINVAL; 1541 goto out; 1542 } 1543 1544 ctx.cap_mask1 = value; 1545 ctx.cap_mask1_perm = mask; 1546 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1547 0, &ctx); 1548 1549 out: 1550 mlx5_ib_put_native_port_mdev(dev, port_num); 1551 1552 return err; 1553 } 1554 1555 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1556 struct ib_port_modify *props) 1557 { 1558 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1559 struct ib_port_attr attr; 1560 u32 tmp; 1561 int err; 1562 u32 change_mask; 1563 u32 value; 1564 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1565 IB_LINK_LAYER_INFINIBAND); 1566 1567 /* CM layer calls ib_modify_port() regardless of the link layer. For 1568 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1569 */ 1570 if (!is_ib) 1571 return 0; 1572 1573 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1574 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1575 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1576 return set_port_caps_atomic(dev, port, change_mask, value); 1577 } 1578 1579 mutex_lock(&dev->cap_mask_mutex); 1580 1581 err = ib_query_port(ibdev, port, &attr); 1582 if (err) 1583 goto out; 1584 1585 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1586 ~props->clr_port_cap_mask; 1587 1588 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1589 1590 out: 1591 mutex_unlock(&dev->cap_mask_mutex); 1592 return err; 1593 } 1594 1595 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1596 { 1597 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1598 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1599 } 1600 1601 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1602 { 1603 /* Large page with non 4k uar support might limit the dynamic size */ 1604 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1605 return MLX5_MIN_DYN_BFREGS; 1606 1607 return MLX5_MAX_DYN_BFREGS; 1608 } 1609 1610 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1611 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1612 struct mlx5_bfreg_info *bfregi) 1613 { 1614 int uars_per_sys_page; 1615 int bfregs_per_sys_page; 1616 int ref_bfregs = req->total_num_bfregs; 1617 1618 if (req->total_num_bfregs == 0) 1619 return -EINVAL; 1620 1621 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1622 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1623 1624 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1625 return -ENOMEM; 1626 1627 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1628 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1629 /* This holds the required static allocation asked by the user */ 1630 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1631 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1632 return -EINVAL; 1633 1634 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1635 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1636 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1637 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1638 1639 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1640 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1641 lib_uar_4k ? "yes" : "no", ref_bfregs, 1642 req->total_num_bfregs, bfregi->total_num_bfregs, 1643 bfregi->num_sys_pages); 1644 1645 return 0; 1646 } 1647 1648 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1649 { 1650 struct mlx5_bfreg_info *bfregi; 1651 int err; 1652 int i; 1653 1654 bfregi = &context->bfregi; 1655 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1656 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1657 context->devx_uid); 1658 if (err) 1659 goto error; 1660 1661 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1662 } 1663 1664 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1665 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1666 1667 return 0; 1668 1669 error: 1670 for (--i; i >= 0; i--) 1671 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1672 context->devx_uid)) 1673 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1674 1675 return err; 1676 } 1677 1678 static void deallocate_uars(struct mlx5_ib_dev *dev, 1679 struct mlx5_ib_ucontext *context) 1680 { 1681 struct mlx5_bfreg_info *bfregi; 1682 int i; 1683 1684 bfregi = &context->bfregi; 1685 for (i = 0; i < bfregi->num_sys_pages; i++) 1686 if (i < bfregi->num_static_sys_pages || 1687 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1688 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1689 context->devx_uid); 1690 } 1691 1692 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1693 { 1694 int err = 0; 1695 1696 mutex_lock(&dev->lb.mutex); 1697 if (td) 1698 dev->lb.user_td++; 1699 if (qp) 1700 dev->lb.qps++; 1701 1702 if (dev->lb.user_td == 2 || 1703 dev->lb.qps == 1) { 1704 if (!dev->lb.enabled) { 1705 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1706 dev->lb.enabled = true; 1707 } 1708 } 1709 1710 mutex_unlock(&dev->lb.mutex); 1711 1712 return err; 1713 } 1714 1715 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1716 { 1717 mutex_lock(&dev->lb.mutex); 1718 if (td) 1719 dev->lb.user_td--; 1720 if (qp) 1721 dev->lb.qps--; 1722 1723 if (dev->lb.user_td == 1 && 1724 dev->lb.qps == 0) { 1725 if (dev->lb.enabled) { 1726 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1727 dev->lb.enabled = false; 1728 } 1729 } 1730 1731 mutex_unlock(&dev->lb.mutex); 1732 } 1733 1734 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1735 u16 uid) 1736 { 1737 int err; 1738 1739 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1740 return 0; 1741 1742 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1743 if (err) 1744 return err; 1745 1746 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1747 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1748 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1749 return err; 1750 1751 return mlx5_ib_enable_lb(dev, true, false); 1752 } 1753 1754 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1755 u16 uid) 1756 { 1757 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1758 return; 1759 1760 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1761 1762 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1763 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1764 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1765 return; 1766 1767 mlx5_ib_disable_lb(dev, true, false); 1768 } 1769 1770 static int set_ucontext_resp(struct ib_ucontext *uctx, 1771 struct mlx5_ib_alloc_ucontext_resp *resp) 1772 { 1773 struct ib_device *ibdev = uctx->device; 1774 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1775 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1776 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1777 1778 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1779 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1780 resp->comp_mask |= 1781 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1782 } 1783 1784 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1785 if (dev->wc_support) 1786 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1787 log_bf_reg_size); 1788 resp->cache_line_size = cache_line_size(); 1789 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1790 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1791 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1792 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1793 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1794 resp->cqe_version = context->cqe_version; 1795 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1796 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1797 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1798 MLX5_CAP_GEN(dev->mdev, 1799 num_of_uars_per_page) : 1; 1800 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1801 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1802 resp->num_ports = dev->num_ports; 1803 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1804 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1805 1806 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1807 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1808 resp->eth_min_inline++; 1809 } 1810 1811 if (dev->mdev->clock_info) 1812 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1813 1814 /* 1815 * We don't want to expose information from the PCI bar that is located 1816 * after 4096 bytes, so if the arch only supports larger pages, let's 1817 * pretend we don't support reading the HCA's core clock. This is also 1818 * forced by mmap function. 1819 */ 1820 if (PAGE_SIZE <= 4096) { 1821 resp->comp_mask |= 1822 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1823 resp->hca_core_clock_offset = 1824 offsetof(struct mlx5_init_seg, 1825 internal_timer_h) % PAGE_SIZE; 1826 } 1827 1828 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1829 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1830 1831 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1832 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1833 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1834 resp->comp_mask |= 1835 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1836 1837 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1838 1839 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1840 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1841 1842 resp->comp_mask |= 1843 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1844 1845 return 0; 1846 } 1847 1848 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1849 struct ib_udata *udata) 1850 { 1851 struct ib_device *ibdev = uctx->device; 1852 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1853 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1854 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1855 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1856 struct mlx5_bfreg_info *bfregi; 1857 int ver; 1858 int err; 1859 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1860 max_cqe_version); 1861 bool lib_uar_4k; 1862 bool lib_uar_dyn; 1863 1864 if (!dev->ib_active) 1865 return -EAGAIN; 1866 1867 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1868 ver = 0; 1869 else if (udata->inlen >= min_req_v2) 1870 ver = 2; 1871 else 1872 return -EINVAL; 1873 1874 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1875 if (err) 1876 return err; 1877 1878 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1879 return -EOPNOTSUPP; 1880 1881 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1882 return -EOPNOTSUPP; 1883 1884 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1885 MLX5_NON_FP_BFREGS_PER_UAR); 1886 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1887 return -EINVAL; 1888 1889 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1890 err = mlx5_ib_devx_create(dev, true); 1891 if (err < 0) 1892 goto out_ctx; 1893 context->devx_uid = err; 1894 } 1895 1896 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1897 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1898 bfregi = &context->bfregi; 1899 1900 if (lib_uar_dyn) { 1901 bfregi->lib_uar_dyn = lib_uar_dyn; 1902 goto uar_done; 1903 } 1904 1905 /* updates req->total_num_bfregs */ 1906 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1907 if (err) 1908 goto out_devx; 1909 1910 mutex_init(&bfregi->lock); 1911 bfregi->lib_uar_4k = lib_uar_4k; 1912 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1913 GFP_KERNEL); 1914 if (!bfregi->count) { 1915 err = -ENOMEM; 1916 goto out_devx; 1917 } 1918 1919 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1920 sizeof(*bfregi->sys_pages), 1921 GFP_KERNEL); 1922 if (!bfregi->sys_pages) { 1923 err = -ENOMEM; 1924 goto out_count; 1925 } 1926 1927 err = allocate_uars(dev, context); 1928 if (err) 1929 goto out_sys_pages; 1930 1931 uar_done: 1932 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1933 context->devx_uid); 1934 if (err) 1935 goto out_uars; 1936 1937 INIT_LIST_HEAD(&context->db_page_list); 1938 mutex_init(&context->db_page_mutex); 1939 1940 context->cqe_version = min_t(__u8, 1941 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1942 req.max_cqe_version); 1943 1944 err = set_ucontext_resp(uctx, &resp); 1945 if (err) 1946 goto out_mdev; 1947 1948 resp.response_length = min(udata->outlen, sizeof(resp)); 1949 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1950 if (err) 1951 goto out_mdev; 1952 1953 bfregi->ver = ver; 1954 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1955 context->lib_caps = req.lib_caps; 1956 print_lib_caps(dev, context->lib_caps); 1957 1958 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1959 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1960 1961 atomic_set(&context->tx_port_affinity, 1962 atomic_add_return( 1963 1, &dev->port[port].roce.tx_port_affinity)); 1964 } 1965 1966 return 0; 1967 1968 out_mdev: 1969 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1970 1971 out_uars: 1972 deallocate_uars(dev, context); 1973 1974 out_sys_pages: 1975 kfree(bfregi->sys_pages); 1976 1977 out_count: 1978 kfree(bfregi->count); 1979 1980 out_devx: 1981 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1982 mlx5_ib_devx_destroy(dev, context->devx_uid); 1983 1984 out_ctx: 1985 return err; 1986 } 1987 1988 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1989 struct uverbs_attr_bundle *attrs) 1990 { 1991 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1992 int ret; 1993 1994 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1995 if (ret) 1996 return ret; 1997 1998 uctx_resp.response_length = 1999 min_t(size_t, 2000 uverbs_attr_get_len(attrs, 2001 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2002 sizeof(uctx_resp)); 2003 2004 ret = uverbs_copy_to_struct_or_zero(attrs, 2005 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2006 &uctx_resp, 2007 sizeof(uctx_resp)); 2008 return ret; 2009 } 2010 2011 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2012 { 2013 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2014 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2015 struct mlx5_bfreg_info *bfregi; 2016 2017 bfregi = &context->bfregi; 2018 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2019 2020 deallocate_uars(dev, context); 2021 kfree(bfregi->sys_pages); 2022 kfree(bfregi->count); 2023 2024 if (context->devx_uid) 2025 mlx5_ib_devx_destroy(dev, context->devx_uid); 2026 } 2027 2028 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2029 int uar_idx) 2030 { 2031 int fw_uars_per_page; 2032 2033 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2034 2035 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2036 } 2037 2038 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2039 int uar_idx) 2040 { 2041 unsigned int fw_uars_per_page; 2042 2043 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2044 MLX5_UARS_IN_PAGE : 1; 2045 2046 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2047 } 2048 2049 static int get_command(unsigned long offset) 2050 { 2051 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2052 } 2053 2054 static int get_arg(unsigned long offset) 2055 { 2056 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2057 } 2058 2059 static int get_index(unsigned long offset) 2060 { 2061 return get_arg(offset); 2062 } 2063 2064 /* Index resides in an extra byte to enable larger values than 255 */ 2065 static int get_extended_index(unsigned long offset) 2066 { 2067 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2068 } 2069 2070 2071 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2072 { 2073 } 2074 2075 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2076 { 2077 switch (cmd) { 2078 case MLX5_IB_MMAP_WC_PAGE: 2079 return "WC"; 2080 case MLX5_IB_MMAP_REGULAR_PAGE: 2081 return "best effort WC"; 2082 case MLX5_IB_MMAP_NC_PAGE: 2083 return "NC"; 2084 case MLX5_IB_MMAP_DEVICE_MEM: 2085 return "Device Memory"; 2086 default: 2087 return "Unknown"; 2088 } 2089 } 2090 2091 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2092 struct vm_area_struct *vma, 2093 struct mlx5_ib_ucontext *context) 2094 { 2095 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2096 !(vma->vm_flags & VM_SHARED)) 2097 return -EINVAL; 2098 2099 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2100 return -EOPNOTSUPP; 2101 2102 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2103 return -EPERM; 2104 vm_flags_clear(vma, VM_MAYWRITE); 2105 2106 if (!dev->mdev->clock_info) 2107 return -EOPNOTSUPP; 2108 2109 return vm_insert_page(vma, vma->vm_start, 2110 virt_to_page(dev->mdev->clock_info)); 2111 } 2112 2113 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2114 { 2115 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2116 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2117 struct mlx5_var_table *var_table = &dev->var_table; 2118 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2119 2120 switch (mentry->mmap_flag) { 2121 case MLX5_IB_MMAP_TYPE_MEMIC: 2122 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2123 mlx5_ib_dm_mmap_free(dev, mentry); 2124 break; 2125 case MLX5_IB_MMAP_TYPE_VAR: 2126 mutex_lock(&var_table->bitmap_lock); 2127 clear_bit(mentry->page_idx, var_table->bitmap); 2128 mutex_unlock(&var_table->bitmap_lock); 2129 kfree(mentry); 2130 break; 2131 case MLX5_IB_MMAP_TYPE_UAR_WC: 2132 case MLX5_IB_MMAP_TYPE_UAR_NC: 2133 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2134 context->devx_uid); 2135 kfree(mentry); 2136 break; 2137 default: 2138 WARN_ON(true); 2139 } 2140 } 2141 2142 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2143 struct vm_area_struct *vma, 2144 struct mlx5_ib_ucontext *context) 2145 { 2146 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2147 int err; 2148 unsigned long idx; 2149 phys_addr_t pfn; 2150 pgprot_t prot; 2151 u32 bfreg_dyn_idx = 0; 2152 u32 uar_index; 2153 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2154 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2155 bfregi->num_static_sys_pages; 2156 2157 if (bfregi->lib_uar_dyn) 2158 return -EINVAL; 2159 2160 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2161 return -EINVAL; 2162 2163 if (dyn_uar) 2164 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2165 else 2166 idx = get_index(vma->vm_pgoff); 2167 2168 if (idx >= max_valid_idx) { 2169 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2170 idx, max_valid_idx); 2171 return -EINVAL; 2172 } 2173 2174 switch (cmd) { 2175 case MLX5_IB_MMAP_WC_PAGE: 2176 case MLX5_IB_MMAP_ALLOC_WC: 2177 case MLX5_IB_MMAP_REGULAR_PAGE: 2178 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2179 prot = pgprot_writecombine(vma->vm_page_prot); 2180 break; 2181 case MLX5_IB_MMAP_NC_PAGE: 2182 prot = pgprot_noncached(vma->vm_page_prot); 2183 break; 2184 default: 2185 return -EINVAL; 2186 } 2187 2188 if (dyn_uar) { 2189 int uars_per_page; 2190 2191 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2192 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2193 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2194 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2195 bfreg_dyn_idx, bfregi->total_num_bfregs); 2196 return -EINVAL; 2197 } 2198 2199 mutex_lock(&bfregi->lock); 2200 /* Fail if uar already allocated, first bfreg index of each 2201 * page holds its count. 2202 */ 2203 if (bfregi->count[bfreg_dyn_idx]) { 2204 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2205 mutex_unlock(&bfregi->lock); 2206 return -EINVAL; 2207 } 2208 2209 bfregi->count[bfreg_dyn_idx]++; 2210 mutex_unlock(&bfregi->lock); 2211 2212 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2213 context->devx_uid); 2214 if (err) { 2215 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2216 goto free_bfreg; 2217 } 2218 } else { 2219 uar_index = bfregi->sys_pages[idx]; 2220 } 2221 2222 pfn = uar_index2pfn(dev, uar_index); 2223 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2224 2225 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2226 prot, NULL); 2227 if (err) { 2228 mlx5_ib_err(dev, 2229 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2230 err, mmap_cmd2str(cmd)); 2231 goto err; 2232 } 2233 2234 if (dyn_uar) 2235 bfregi->sys_pages[idx] = uar_index; 2236 return 0; 2237 2238 err: 2239 if (!dyn_uar) 2240 return err; 2241 2242 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2243 2244 free_bfreg: 2245 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2246 2247 return err; 2248 } 2249 2250 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2251 { 2252 unsigned long idx; 2253 u8 command; 2254 2255 command = get_command(vma->vm_pgoff); 2256 idx = get_extended_index(vma->vm_pgoff); 2257 2258 return (command << 16 | idx); 2259 } 2260 2261 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2262 struct vm_area_struct *vma, 2263 struct ib_ucontext *ucontext) 2264 { 2265 struct mlx5_user_mmap_entry *mentry; 2266 struct rdma_user_mmap_entry *entry; 2267 unsigned long pgoff; 2268 pgprot_t prot; 2269 phys_addr_t pfn; 2270 int ret; 2271 2272 pgoff = mlx5_vma_to_pgoff(vma); 2273 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2274 if (!entry) 2275 return -EINVAL; 2276 2277 mentry = to_mmmap(entry); 2278 pfn = (mentry->address >> PAGE_SHIFT); 2279 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2280 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2281 prot = pgprot_noncached(vma->vm_page_prot); 2282 else 2283 prot = pgprot_writecombine(vma->vm_page_prot); 2284 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2285 entry->npages * PAGE_SIZE, 2286 prot, 2287 entry); 2288 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2289 return ret; 2290 } 2291 2292 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2293 { 2294 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2295 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2296 2297 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2298 (index & 0xFF)) << PAGE_SHIFT; 2299 } 2300 2301 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2302 { 2303 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2304 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2305 unsigned long command; 2306 phys_addr_t pfn; 2307 2308 command = get_command(vma->vm_pgoff); 2309 switch (command) { 2310 case MLX5_IB_MMAP_WC_PAGE: 2311 case MLX5_IB_MMAP_ALLOC_WC: 2312 if (!dev->wc_support) 2313 return -EPERM; 2314 fallthrough; 2315 case MLX5_IB_MMAP_NC_PAGE: 2316 case MLX5_IB_MMAP_REGULAR_PAGE: 2317 return uar_mmap(dev, command, vma, context); 2318 2319 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2320 return -ENOSYS; 2321 2322 case MLX5_IB_MMAP_CORE_CLOCK: 2323 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2324 return -EINVAL; 2325 2326 if (vma->vm_flags & VM_WRITE) 2327 return -EPERM; 2328 vm_flags_clear(vma, VM_MAYWRITE); 2329 2330 /* Don't expose to user-space information it shouldn't have */ 2331 if (PAGE_SIZE > 4096) 2332 return -EOPNOTSUPP; 2333 2334 pfn = (dev->mdev->iseg_base + 2335 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2336 PAGE_SHIFT; 2337 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2338 PAGE_SIZE, 2339 pgprot_noncached(vma->vm_page_prot), 2340 NULL); 2341 case MLX5_IB_MMAP_CLOCK_INFO: 2342 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2343 2344 default: 2345 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2346 } 2347 2348 return 0; 2349 } 2350 2351 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2352 { 2353 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2354 struct ib_device *ibdev = ibpd->device; 2355 struct mlx5_ib_alloc_pd_resp resp; 2356 int err; 2357 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2358 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2359 u16 uid = 0; 2360 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2361 udata, struct mlx5_ib_ucontext, ibucontext); 2362 2363 uid = context ? context->devx_uid : 0; 2364 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2365 MLX5_SET(alloc_pd_in, in, uid, uid); 2366 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2367 if (err) 2368 return err; 2369 2370 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2371 pd->uid = uid; 2372 if (udata) { 2373 resp.pdn = pd->pdn; 2374 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2375 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2376 return -EFAULT; 2377 } 2378 } 2379 2380 return 0; 2381 } 2382 2383 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2384 { 2385 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2386 struct mlx5_ib_pd *mpd = to_mpd(pd); 2387 2388 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2389 } 2390 2391 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2392 { 2393 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2394 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2395 int err; 2396 u16 uid; 2397 2398 uid = ibqp->pd ? 2399 to_mpd(ibqp->pd)->uid : 0; 2400 2401 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2402 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2403 return -EOPNOTSUPP; 2404 } 2405 2406 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2407 if (err) 2408 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2409 ibqp->qp_num, gid->raw); 2410 2411 return err; 2412 } 2413 2414 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2415 { 2416 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2417 int err; 2418 u16 uid; 2419 2420 uid = ibqp->pd ? 2421 to_mpd(ibqp->pd)->uid : 0; 2422 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2423 if (err) 2424 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2425 ibqp->qp_num, gid->raw); 2426 2427 return err; 2428 } 2429 2430 static int init_node_data(struct mlx5_ib_dev *dev) 2431 { 2432 int err; 2433 2434 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2435 if (err) 2436 return err; 2437 2438 dev->mdev->rev_id = dev->mdev->pdev->revision; 2439 2440 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2441 } 2442 2443 static ssize_t fw_pages_show(struct device *device, 2444 struct device_attribute *attr, char *buf) 2445 { 2446 struct mlx5_ib_dev *dev = 2447 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2448 2449 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2450 } 2451 static DEVICE_ATTR_RO(fw_pages); 2452 2453 static ssize_t reg_pages_show(struct device *device, 2454 struct device_attribute *attr, char *buf) 2455 { 2456 struct mlx5_ib_dev *dev = 2457 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2458 2459 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2460 } 2461 static DEVICE_ATTR_RO(reg_pages); 2462 2463 static ssize_t hca_type_show(struct device *device, 2464 struct device_attribute *attr, char *buf) 2465 { 2466 struct mlx5_ib_dev *dev = 2467 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2468 2469 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2470 } 2471 static DEVICE_ATTR_RO(hca_type); 2472 2473 static ssize_t hw_rev_show(struct device *device, 2474 struct device_attribute *attr, char *buf) 2475 { 2476 struct mlx5_ib_dev *dev = 2477 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2478 2479 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2480 } 2481 static DEVICE_ATTR_RO(hw_rev); 2482 2483 static ssize_t board_id_show(struct device *device, 2484 struct device_attribute *attr, char *buf) 2485 { 2486 struct mlx5_ib_dev *dev = 2487 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2488 2489 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2490 dev->mdev->board_id); 2491 } 2492 static DEVICE_ATTR_RO(board_id); 2493 2494 static struct attribute *mlx5_class_attributes[] = { 2495 &dev_attr_hw_rev.attr, 2496 &dev_attr_hca_type.attr, 2497 &dev_attr_board_id.attr, 2498 &dev_attr_fw_pages.attr, 2499 &dev_attr_reg_pages.attr, 2500 NULL, 2501 }; 2502 2503 static const struct attribute_group mlx5_attr_group = { 2504 .attrs = mlx5_class_attributes, 2505 }; 2506 2507 static void pkey_change_handler(struct work_struct *work) 2508 { 2509 struct mlx5_ib_port_resources *ports = 2510 container_of(work, struct mlx5_ib_port_resources, 2511 pkey_change_work); 2512 2513 if (!ports->gsi) 2514 /* 2515 * We got this event before device was fully configured 2516 * and MAD registration code wasn't called/finished yet. 2517 */ 2518 return; 2519 2520 mlx5_ib_gsi_pkey_change(ports->gsi); 2521 } 2522 2523 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2524 { 2525 struct mlx5_ib_qp *mqp; 2526 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2527 struct mlx5_core_cq *mcq; 2528 struct list_head cq_armed_list; 2529 unsigned long flags_qp; 2530 unsigned long flags_cq; 2531 unsigned long flags; 2532 2533 INIT_LIST_HEAD(&cq_armed_list); 2534 2535 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2536 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2537 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2538 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2539 if (mqp->sq.tail != mqp->sq.head) { 2540 send_mcq = to_mcq(mqp->ibqp.send_cq); 2541 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2542 if (send_mcq->mcq.comp && 2543 mqp->ibqp.send_cq->comp_handler) { 2544 if (!send_mcq->mcq.reset_notify_added) { 2545 send_mcq->mcq.reset_notify_added = 1; 2546 list_add_tail(&send_mcq->mcq.reset_notify, 2547 &cq_armed_list); 2548 } 2549 } 2550 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2551 } 2552 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2553 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2554 /* no handling is needed for SRQ */ 2555 if (!mqp->ibqp.srq) { 2556 if (mqp->rq.tail != mqp->rq.head) { 2557 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2558 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2559 if (recv_mcq->mcq.comp && 2560 mqp->ibqp.recv_cq->comp_handler) { 2561 if (!recv_mcq->mcq.reset_notify_added) { 2562 recv_mcq->mcq.reset_notify_added = 1; 2563 list_add_tail(&recv_mcq->mcq.reset_notify, 2564 &cq_armed_list); 2565 } 2566 } 2567 spin_unlock_irqrestore(&recv_mcq->lock, 2568 flags_cq); 2569 } 2570 } 2571 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2572 } 2573 /*At that point all inflight post send were put to be executed as of we 2574 * lock/unlock above locks Now need to arm all involved CQs. 2575 */ 2576 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2577 mcq->comp(mcq, NULL); 2578 } 2579 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2580 } 2581 2582 static void delay_drop_handler(struct work_struct *work) 2583 { 2584 int err; 2585 struct mlx5_ib_delay_drop *delay_drop = 2586 container_of(work, struct mlx5_ib_delay_drop, 2587 delay_drop_work); 2588 2589 atomic_inc(&delay_drop->events_cnt); 2590 2591 mutex_lock(&delay_drop->lock); 2592 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2593 if (err) { 2594 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2595 delay_drop->timeout); 2596 delay_drop->activate = false; 2597 } 2598 mutex_unlock(&delay_drop->lock); 2599 } 2600 2601 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2602 struct ib_event *ibev) 2603 { 2604 u32 port = (eqe->data.port.port >> 4) & 0xf; 2605 2606 switch (eqe->sub_type) { 2607 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2608 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2609 IB_LINK_LAYER_ETHERNET) 2610 schedule_work(&ibdev->delay_drop.delay_drop_work); 2611 break; 2612 default: /* do nothing */ 2613 return; 2614 } 2615 } 2616 2617 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2618 struct ib_event *ibev) 2619 { 2620 u32 port = (eqe->data.port.port >> 4) & 0xf; 2621 2622 ibev->element.port_num = port; 2623 2624 switch (eqe->sub_type) { 2625 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2626 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2627 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2628 /* In RoCE, port up/down events are handled in 2629 * mlx5_netdev_event(). 2630 */ 2631 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2632 IB_LINK_LAYER_ETHERNET) 2633 return -EINVAL; 2634 2635 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2636 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2637 break; 2638 2639 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2640 ibev->event = IB_EVENT_LID_CHANGE; 2641 break; 2642 2643 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2644 ibev->event = IB_EVENT_PKEY_CHANGE; 2645 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2646 break; 2647 2648 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2649 ibev->event = IB_EVENT_GID_CHANGE; 2650 break; 2651 2652 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2653 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2654 break; 2655 default: 2656 return -EINVAL; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static void mlx5_ib_handle_event(struct work_struct *_work) 2663 { 2664 struct mlx5_ib_event_work *work = 2665 container_of(_work, struct mlx5_ib_event_work, work); 2666 struct mlx5_ib_dev *ibdev; 2667 struct ib_event ibev; 2668 bool fatal = false; 2669 2670 if (work->is_slave) { 2671 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2672 if (!ibdev) 2673 goto out; 2674 } else { 2675 ibdev = work->dev; 2676 } 2677 2678 switch (work->event) { 2679 case MLX5_DEV_EVENT_SYS_ERROR: 2680 ibev.event = IB_EVENT_DEVICE_FATAL; 2681 mlx5_ib_handle_internal_error(ibdev); 2682 ibev.element.port_num = (u8)(unsigned long)work->param; 2683 fatal = true; 2684 break; 2685 case MLX5_EVENT_TYPE_PORT_CHANGE: 2686 if (handle_port_change(ibdev, work->param, &ibev)) 2687 goto out; 2688 break; 2689 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2690 handle_general_event(ibdev, work->param, &ibev); 2691 fallthrough; 2692 default: 2693 goto out; 2694 } 2695 2696 ibev.device = &ibdev->ib_dev; 2697 2698 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2699 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2700 goto out; 2701 } 2702 2703 if (ibdev->ib_active) 2704 ib_dispatch_event(&ibev); 2705 2706 if (fatal) 2707 ibdev->ib_active = false; 2708 out: 2709 kfree(work); 2710 } 2711 2712 static int mlx5_ib_event(struct notifier_block *nb, 2713 unsigned long event, void *param) 2714 { 2715 struct mlx5_ib_event_work *work; 2716 2717 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2718 if (!work) 2719 return NOTIFY_DONE; 2720 2721 INIT_WORK(&work->work, mlx5_ib_handle_event); 2722 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2723 work->is_slave = false; 2724 work->param = param; 2725 work->event = event; 2726 2727 queue_work(mlx5_ib_event_wq, &work->work); 2728 2729 return NOTIFY_OK; 2730 } 2731 2732 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2733 unsigned long event, void *param) 2734 { 2735 struct mlx5_ib_event_work *work; 2736 2737 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2738 if (!work) 2739 return NOTIFY_DONE; 2740 2741 INIT_WORK(&work->work, mlx5_ib_handle_event); 2742 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2743 work->is_slave = true; 2744 work->param = param; 2745 work->event = event; 2746 queue_work(mlx5_ib_event_wq, &work->work); 2747 2748 return NOTIFY_OK; 2749 } 2750 2751 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2752 { 2753 struct mlx5_hca_vport_context vport_ctx; 2754 int err; 2755 int port; 2756 2757 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2758 return 0; 2759 2760 for (port = 1; port <= dev->num_ports; port++) { 2761 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2762 dev->port_caps[port - 1].has_smi = true; 2763 continue; 2764 } 2765 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2766 &vport_ctx); 2767 if (err) { 2768 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2769 port, err); 2770 return err; 2771 } 2772 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2773 } 2774 2775 return 0; 2776 } 2777 2778 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2779 { 2780 unsigned int port; 2781 2782 rdma_for_each_port (&dev->ib_dev, port) 2783 mlx5_query_ext_port_caps(dev, port); 2784 } 2785 2786 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2787 { 2788 switch (umr_fence_cap) { 2789 case MLX5_CAP_UMR_FENCE_NONE: 2790 return MLX5_FENCE_MODE_NONE; 2791 case MLX5_CAP_UMR_FENCE_SMALL: 2792 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2793 default: 2794 return MLX5_FENCE_MODE_STRONG_ORDERING; 2795 } 2796 } 2797 2798 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2799 { 2800 struct mlx5_ib_resources *devr = &dev->devr; 2801 struct ib_srq_init_attr attr; 2802 struct ib_device *ibdev; 2803 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2804 int port; 2805 int ret = 0; 2806 2807 ibdev = &dev->ib_dev; 2808 2809 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2810 return -EOPNOTSUPP; 2811 2812 devr->p0 = ib_alloc_pd(ibdev, 0); 2813 if (IS_ERR(devr->p0)) 2814 return PTR_ERR(devr->p0); 2815 2816 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2817 if (IS_ERR(devr->c0)) { 2818 ret = PTR_ERR(devr->c0); 2819 goto error1; 2820 } 2821 2822 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2823 if (ret) 2824 goto error2; 2825 2826 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2827 if (ret) 2828 goto error3; 2829 2830 memset(&attr, 0, sizeof(attr)); 2831 attr.attr.max_sge = 1; 2832 attr.attr.max_wr = 1; 2833 attr.srq_type = IB_SRQT_XRC; 2834 attr.ext.cq = devr->c0; 2835 2836 devr->s0 = ib_create_srq(devr->p0, &attr); 2837 if (IS_ERR(devr->s0)) { 2838 ret = PTR_ERR(devr->s0); 2839 goto err_create; 2840 } 2841 2842 memset(&attr, 0, sizeof(attr)); 2843 attr.attr.max_sge = 1; 2844 attr.attr.max_wr = 1; 2845 attr.srq_type = IB_SRQT_BASIC; 2846 2847 devr->s1 = ib_create_srq(devr->p0, &attr); 2848 if (IS_ERR(devr->s1)) { 2849 ret = PTR_ERR(devr->s1); 2850 goto error6; 2851 } 2852 2853 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2854 INIT_WORK(&devr->ports[port].pkey_change_work, 2855 pkey_change_handler); 2856 2857 return 0; 2858 2859 error6: 2860 ib_destroy_srq(devr->s0); 2861 err_create: 2862 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2863 error3: 2864 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2865 error2: 2866 ib_destroy_cq(devr->c0); 2867 error1: 2868 ib_dealloc_pd(devr->p0); 2869 return ret; 2870 } 2871 2872 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2873 { 2874 struct mlx5_ib_resources *devr = &dev->devr; 2875 int port; 2876 2877 /* 2878 * Make sure no change P_Key work items are still executing. 2879 * 2880 * At this stage, the mlx5_ib_event should be unregistered 2881 * and it ensures that no new works are added. 2882 */ 2883 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2884 cancel_work_sync(&devr->ports[port].pkey_change_work); 2885 2886 ib_destroy_srq(devr->s1); 2887 ib_destroy_srq(devr->s0); 2888 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2889 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2890 ib_destroy_cq(devr->c0); 2891 ib_dealloc_pd(devr->p0); 2892 } 2893 2894 static u32 get_core_cap_flags(struct ib_device *ibdev, 2895 struct mlx5_hca_vport_context *rep) 2896 { 2897 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2898 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2899 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2900 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2901 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2902 u32 ret = 0; 2903 2904 if (rep->grh_required) 2905 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2906 2907 if (ll == IB_LINK_LAYER_INFINIBAND) 2908 return ret | RDMA_CORE_PORT_IBA_IB; 2909 2910 if (raw_support) 2911 ret |= RDMA_CORE_PORT_RAW_PACKET; 2912 2913 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2914 return ret; 2915 2916 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2917 return ret; 2918 2919 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2920 ret |= RDMA_CORE_PORT_IBA_ROCE; 2921 2922 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2923 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2924 2925 return ret; 2926 } 2927 2928 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2929 struct ib_port_immutable *immutable) 2930 { 2931 struct ib_port_attr attr; 2932 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2933 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2934 struct mlx5_hca_vport_context rep = {0}; 2935 int err; 2936 2937 err = ib_query_port(ibdev, port_num, &attr); 2938 if (err) 2939 return err; 2940 2941 if (ll == IB_LINK_LAYER_INFINIBAND) { 2942 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2943 &rep); 2944 if (err) 2945 return err; 2946 } 2947 2948 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2949 immutable->gid_tbl_len = attr.gid_tbl_len; 2950 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2951 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2952 2953 return 0; 2954 } 2955 2956 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2957 struct ib_port_immutable *immutable) 2958 { 2959 struct ib_port_attr attr; 2960 int err; 2961 2962 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2963 2964 err = ib_query_port(ibdev, port_num, &attr); 2965 if (err) 2966 return err; 2967 2968 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2969 immutable->gid_tbl_len = attr.gid_tbl_len; 2970 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2971 2972 return 0; 2973 } 2974 2975 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2976 { 2977 struct mlx5_ib_dev *dev = 2978 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2979 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2980 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2981 fw_rev_sub(dev->mdev)); 2982 } 2983 2984 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2985 { 2986 struct mlx5_core_dev *mdev = dev->mdev; 2987 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2988 MLX5_FLOW_NAMESPACE_LAG); 2989 struct mlx5_flow_table *ft; 2990 int err; 2991 2992 if (!ns || !mlx5_lag_is_active(mdev)) 2993 return 0; 2994 2995 err = mlx5_cmd_create_vport_lag(mdev); 2996 if (err) 2997 return err; 2998 2999 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3000 if (IS_ERR(ft)) { 3001 err = PTR_ERR(ft); 3002 goto err_destroy_vport_lag; 3003 } 3004 3005 dev->flow_db->lag_demux_ft = ft; 3006 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3007 dev->lag_active = true; 3008 return 0; 3009 3010 err_destroy_vport_lag: 3011 mlx5_cmd_destroy_vport_lag(mdev); 3012 return err; 3013 } 3014 3015 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3016 { 3017 struct mlx5_core_dev *mdev = dev->mdev; 3018 3019 if (dev->lag_active) { 3020 dev->lag_active = false; 3021 3022 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3023 dev->flow_db->lag_demux_ft = NULL; 3024 3025 mlx5_cmd_destroy_vport_lag(mdev); 3026 } 3027 } 3028 3029 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3030 struct net_device *netdev) 3031 { 3032 int err; 3033 3034 if (roce->tracking_netdev) 3035 return; 3036 roce->tracking_netdev = netdev; 3037 roce->nb.notifier_call = mlx5_netdev_event; 3038 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3039 WARN_ON(err); 3040 } 3041 3042 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3043 { 3044 if (!roce->tracking_netdev) 3045 return; 3046 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3047 &roce->nn); 3048 roce->tracking_netdev = NULL; 3049 } 3050 3051 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3052 unsigned long event, void *data) 3053 { 3054 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3055 struct net_device *netdev = data; 3056 3057 switch (event) { 3058 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3059 if (netdev) 3060 mlx5_netdev_notifier_register(roce, netdev); 3061 else 3062 mlx5_netdev_notifier_unregister(roce); 3063 break; 3064 default: 3065 return NOTIFY_DONE; 3066 } 3067 3068 return NOTIFY_OK; 3069 } 3070 3071 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3072 { 3073 struct mlx5_roce *roce = &dev->port[port_num].roce; 3074 3075 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3076 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3077 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3078 } 3079 3080 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3081 { 3082 struct mlx5_roce *roce = &dev->port[port_num].roce; 3083 3084 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3085 mlx5_netdev_notifier_unregister(roce); 3086 } 3087 3088 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3089 { 3090 int err; 3091 3092 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3093 err = mlx5_nic_vport_enable_roce(dev->mdev); 3094 if (err) 3095 return err; 3096 } 3097 3098 err = mlx5_eth_lag_init(dev); 3099 if (err) 3100 goto err_disable_roce; 3101 3102 return 0; 3103 3104 err_disable_roce: 3105 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3106 mlx5_nic_vport_disable_roce(dev->mdev); 3107 3108 return err; 3109 } 3110 3111 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3112 { 3113 mlx5_eth_lag_cleanup(dev); 3114 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3115 mlx5_nic_vport_disable_roce(dev->mdev); 3116 } 3117 3118 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3119 enum rdma_netdev_t type, 3120 struct rdma_netdev_alloc_params *params) 3121 { 3122 if (type != RDMA_NETDEV_IPOIB) 3123 return -EOPNOTSUPP; 3124 3125 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3126 } 3127 3128 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3129 size_t count, loff_t *pos) 3130 { 3131 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3132 char lbuf[20]; 3133 int len; 3134 3135 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3136 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3137 } 3138 3139 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3140 size_t count, loff_t *pos) 3141 { 3142 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3143 u32 timeout; 3144 u32 var; 3145 3146 if (kstrtouint_from_user(buf, count, 0, &var)) 3147 return -EFAULT; 3148 3149 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3150 1000); 3151 if (timeout != var) 3152 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3153 timeout); 3154 3155 delay_drop->timeout = timeout; 3156 3157 return count; 3158 } 3159 3160 static const struct file_operations fops_delay_drop_timeout = { 3161 .owner = THIS_MODULE, 3162 .open = simple_open, 3163 .write = delay_drop_timeout_write, 3164 .read = delay_drop_timeout_read, 3165 }; 3166 3167 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3168 struct mlx5_ib_multiport_info *mpi) 3169 { 3170 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3171 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3172 int comps; 3173 int err; 3174 int i; 3175 3176 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3177 3178 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3179 3180 spin_lock(&port->mp.mpi_lock); 3181 if (!mpi->ibdev) { 3182 spin_unlock(&port->mp.mpi_lock); 3183 return; 3184 } 3185 3186 mpi->ibdev = NULL; 3187 3188 spin_unlock(&port->mp.mpi_lock); 3189 if (mpi->mdev_events.notifier_call) 3190 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3191 mpi->mdev_events.notifier_call = NULL; 3192 mlx5_mdev_netdev_untrack(ibdev, port_num); 3193 spin_lock(&port->mp.mpi_lock); 3194 3195 comps = mpi->mdev_refcnt; 3196 if (comps) { 3197 mpi->unaffiliate = true; 3198 init_completion(&mpi->unref_comp); 3199 spin_unlock(&port->mp.mpi_lock); 3200 3201 for (i = 0; i < comps; i++) 3202 wait_for_completion(&mpi->unref_comp); 3203 3204 spin_lock(&port->mp.mpi_lock); 3205 mpi->unaffiliate = false; 3206 } 3207 3208 port->mp.mpi = NULL; 3209 3210 spin_unlock(&port->mp.mpi_lock); 3211 3212 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3213 3214 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3215 /* Log an error, still needed to cleanup the pointers and add 3216 * it back to the list. 3217 */ 3218 if (err) 3219 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3220 port_num + 1); 3221 3222 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3223 } 3224 3225 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3226 struct mlx5_ib_multiport_info *mpi) 3227 { 3228 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3229 int err; 3230 3231 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3232 3233 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3234 if (ibdev->port[port_num].mp.mpi) { 3235 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3236 port_num + 1); 3237 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3238 return false; 3239 } 3240 3241 ibdev->port[port_num].mp.mpi = mpi; 3242 mpi->ibdev = ibdev; 3243 mpi->mdev_events.notifier_call = NULL; 3244 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3245 3246 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3247 if (err) 3248 goto unbind; 3249 3250 mlx5_mdev_netdev_track(ibdev, port_num); 3251 3252 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3253 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3254 3255 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3256 3257 return true; 3258 3259 unbind: 3260 mlx5_ib_unbind_slave_port(ibdev, mpi); 3261 return false; 3262 } 3263 3264 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3265 { 3266 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3268 port_num + 1); 3269 struct mlx5_ib_multiport_info *mpi; 3270 int err; 3271 u32 i; 3272 3273 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3274 return 0; 3275 3276 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3277 &dev->sys_image_guid); 3278 if (err) 3279 return err; 3280 3281 err = mlx5_nic_vport_enable_roce(dev->mdev); 3282 if (err) 3283 return err; 3284 3285 mutex_lock(&mlx5_ib_multiport_mutex); 3286 for (i = 0; i < dev->num_ports; i++) { 3287 bool bound = false; 3288 3289 /* build a stub multiport info struct for the native port. */ 3290 if (i == port_num) { 3291 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3292 if (!mpi) { 3293 mutex_unlock(&mlx5_ib_multiport_mutex); 3294 mlx5_nic_vport_disable_roce(dev->mdev); 3295 return -ENOMEM; 3296 } 3297 3298 mpi->is_master = true; 3299 mpi->mdev = dev->mdev; 3300 mpi->sys_image_guid = dev->sys_image_guid; 3301 dev->port[i].mp.mpi = mpi; 3302 mpi->ibdev = dev; 3303 mpi = NULL; 3304 continue; 3305 } 3306 3307 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3308 list) { 3309 if (dev->sys_image_guid == mpi->sys_image_guid && 3310 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3311 bound = mlx5_ib_bind_slave_port(dev, mpi); 3312 } 3313 3314 if (bound) { 3315 dev_dbg(mpi->mdev->device, 3316 "removing port from unaffiliated list.\n"); 3317 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3318 list_del(&mpi->list); 3319 break; 3320 } 3321 } 3322 if (!bound) 3323 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3324 i + 1); 3325 } 3326 3327 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3328 mutex_unlock(&mlx5_ib_multiport_mutex); 3329 return err; 3330 } 3331 3332 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3333 { 3334 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3335 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3336 port_num + 1); 3337 u32 i; 3338 3339 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3340 return; 3341 3342 mutex_lock(&mlx5_ib_multiport_mutex); 3343 for (i = 0; i < dev->num_ports; i++) { 3344 if (dev->port[i].mp.mpi) { 3345 /* Destroy the native port stub */ 3346 if (i == port_num) { 3347 kfree(dev->port[i].mp.mpi); 3348 dev->port[i].mp.mpi = NULL; 3349 } else { 3350 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3351 i + 1); 3352 list_add_tail(&dev->port[i].mp.mpi->list, 3353 &mlx5_ib_unaffiliated_port_list); 3354 mlx5_ib_unbind_slave_port(dev, 3355 dev->port[i].mp.mpi); 3356 } 3357 } 3358 } 3359 3360 mlx5_ib_dbg(dev, "removing from devlist\n"); 3361 list_del(&dev->ib_dev_list); 3362 mutex_unlock(&mlx5_ib_multiport_mutex); 3363 3364 mlx5_nic_vport_disable_roce(dev->mdev); 3365 } 3366 3367 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3368 enum rdma_remove_reason why, 3369 struct uverbs_attr_bundle *attrs) 3370 { 3371 struct mlx5_user_mmap_entry *obj = uobject->object; 3372 3373 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3374 return 0; 3375 } 3376 3377 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3378 struct mlx5_user_mmap_entry *entry, 3379 size_t length) 3380 { 3381 return rdma_user_mmap_entry_insert_range( 3382 &c->ibucontext, &entry->rdma_entry, length, 3383 (MLX5_IB_MMAP_OFFSET_START << 16), 3384 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3385 } 3386 3387 static struct mlx5_user_mmap_entry * 3388 alloc_var_entry(struct mlx5_ib_ucontext *c) 3389 { 3390 struct mlx5_user_mmap_entry *entry; 3391 struct mlx5_var_table *var_table; 3392 u32 page_idx; 3393 int err; 3394 3395 var_table = &to_mdev(c->ibucontext.device)->var_table; 3396 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3397 if (!entry) 3398 return ERR_PTR(-ENOMEM); 3399 3400 mutex_lock(&var_table->bitmap_lock); 3401 page_idx = find_first_zero_bit(var_table->bitmap, 3402 var_table->num_var_hw_entries); 3403 if (page_idx >= var_table->num_var_hw_entries) { 3404 err = -ENOSPC; 3405 mutex_unlock(&var_table->bitmap_lock); 3406 goto end; 3407 } 3408 3409 set_bit(page_idx, var_table->bitmap); 3410 mutex_unlock(&var_table->bitmap_lock); 3411 3412 entry->address = var_table->hw_start_addr + 3413 (page_idx * var_table->stride_size); 3414 entry->page_idx = page_idx; 3415 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3416 3417 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3418 var_table->stride_size); 3419 if (err) 3420 goto err_insert; 3421 3422 return entry; 3423 3424 err_insert: 3425 mutex_lock(&var_table->bitmap_lock); 3426 clear_bit(page_idx, var_table->bitmap); 3427 mutex_unlock(&var_table->bitmap_lock); 3428 end: 3429 kfree(entry); 3430 return ERR_PTR(err); 3431 } 3432 3433 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3434 struct uverbs_attr_bundle *attrs) 3435 { 3436 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3437 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3438 struct mlx5_ib_ucontext *c; 3439 struct mlx5_user_mmap_entry *entry; 3440 u64 mmap_offset; 3441 u32 length; 3442 int err; 3443 3444 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3445 if (IS_ERR(c)) 3446 return PTR_ERR(c); 3447 3448 entry = alloc_var_entry(c); 3449 if (IS_ERR(entry)) 3450 return PTR_ERR(entry); 3451 3452 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3453 length = entry->rdma_entry.npages * PAGE_SIZE; 3454 uobj->object = entry; 3455 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3456 3457 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3458 &mmap_offset, sizeof(mmap_offset)); 3459 if (err) 3460 return err; 3461 3462 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3463 &entry->page_idx, sizeof(entry->page_idx)); 3464 if (err) 3465 return err; 3466 3467 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3468 &length, sizeof(length)); 3469 return err; 3470 } 3471 3472 DECLARE_UVERBS_NAMED_METHOD( 3473 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3474 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3475 MLX5_IB_OBJECT_VAR, 3476 UVERBS_ACCESS_NEW, 3477 UA_MANDATORY), 3478 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3479 UVERBS_ATTR_TYPE(u32), 3480 UA_MANDATORY), 3481 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3482 UVERBS_ATTR_TYPE(u32), 3483 UA_MANDATORY), 3484 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3485 UVERBS_ATTR_TYPE(u64), 3486 UA_MANDATORY)); 3487 3488 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3489 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3490 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3491 MLX5_IB_OBJECT_VAR, 3492 UVERBS_ACCESS_DESTROY, 3493 UA_MANDATORY)); 3494 3495 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3496 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3497 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3498 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3499 3500 static bool var_is_supported(struct ib_device *device) 3501 { 3502 struct mlx5_ib_dev *dev = to_mdev(device); 3503 3504 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3505 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3506 } 3507 3508 static struct mlx5_user_mmap_entry * 3509 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3510 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3511 { 3512 struct mlx5_user_mmap_entry *entry; 3513 struct mlx5_ib_dev *dev; 3514 u32 uar_index; 3515 int err; 3516 3517 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3518 if (!entry) 3519 return ERR_PTR(-ENOMEM); 3520 3521 dev = to_mdev(c->ibucontext.device); 3522 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3523 if (err) 3524 goto end; 3525 3526 entry->page_idx = uar_index; 3527 entry->address = uar_index2paddress(dev, uar_index); 3528 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3529 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3530 else 3531 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3532 3533 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3534 if (err) 3535 goto err_insert; 3536 3537 return entry; 3538 3539 err_insert: 3540 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3541 end: 3542 kfree(entry); 3543 return ERR_PTR(err); 3544 } 3545 3546 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3547 struct uverbs_attr_bundle *attrs) 3548 { 3549 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3550 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3551 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3552 struct mlx5_ib_ucontext *c; 3553 struct mlx5_user_mmap_entry *entry; 3554 u64 mmap_offset; 3555 u32 length; 3556 int err; 3557 3558 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3559 if (IS_ERR(c)) 3560 return PTR_ERR(c); 3561 3562 err = uverbs_get_const(&alloc_type, attrs, 3563 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3564 if (err) 3565 return err; 3566 3567 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3568 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3569 return -EOPNOTSUPP; 3570 3571 if (!to_mdev(c->ibucontext.device)->wc_support && 3572 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3573 return -EOPNOTSUPP; 3574 3575 entry = alloc_uar_entry(c, alloc_type); 3576 if (IS_ERR(entry)) 3577 return PTR_ERR(entry); 3578 3579 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3580 length = entry->rdma_entry.npages * PAGE_SIZE; 3581 uobj->object = entry; 3582 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3583 3584 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3585 &mmap_offset, sizeof(mmap_offset)); 3586 if (err) 3587 return err; 3588 3589 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3590 &entry->page_idx, sizeof(entry->page_idx)); 3591 if (err) 3592 return err; 3593 3594 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3595 &length, sizeof(length)); 3596 return err; 3597 } 3598 3599 DECLARE_UVERBS_NAMED_METHOD( 3600 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3601 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3602 MLX5_IB_OBJECT_UAR, 3603 UVERBS_ACCESS_NEW, 3604 UA_MANDATORY), 3605 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3606 enum mlx5_ib_uapi_uar_alloc_type, 3607 UA_MANDATORY), 3608 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3609 UVERBS_ATTR_TYPE(u32), 3610 UA_MANDATORY), 3611 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3612 UVERBS_ATTR_TYPE(u32), 3613 UA_MANDATORY), 3614 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3615 UVERBS_ATTR_TYPE(u64), 3616 UA_MANDATORY)); 3617 3618 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3619 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3620 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3621 MLX5_IB_OBJECT_UAR, 3622 UVERBS_ACCESS_DESTROY, 3623 UA_MANDATORY)); 3624 3625 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3626 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3627 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3628 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3629 3630 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3631 mlx5_ib_query_context, 3632 UVERBS_OBJECT_DEVICE, 3633 UVERBS_METHOD_QUERY_CONTEXT, 3634 UVERBS_ATTR_PTR_OUT( 3635 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3636 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3637 dump_fill_mkey), 3638 UA_MANDATORY)); 3639 3640 static const struct uapi_definition mlx5_ib_defs[] = { 3641 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3642 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3643 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3644 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3645 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3646 3647 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3648 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3649 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3650 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3651 {} 3652 }; 3653 3654 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3655 { 3656 mlx5_ib_cleanup_multiport_master(dev); 3657 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3658 mutex_destroy(&dev->cap_mask_mutex); 3659 WARN_ON(!xa_empty(&dev->sig_mrs)); 3660 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3661 mlx5r_macsec_dealloc_gids(dev); 3662 } 3663 3664 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3665 { 3666 struct mlx5_core_dev *mdev = dev->mdev; 3667 int err, i; 3668 3669 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3670 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3671 dev->ib_dev.phys_port_cnt = dev->num_ports; 3672 dev->ib_dev.dev.parent = mdev->device; 3673 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3674 3675 for (i = 0; i < dev->num_ports; i++) { 3676 spin_lock_init(&dev->port[i].mp.mpi_lock); 3677 rwlock_init(&dev->port[i].roce.netdev_lock); 3678 dev->port[i].roce.dev = dev; 3679 dev->port[i].roce.native_port_num = i + 1; 3680 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3681 } 3682 3683 err = mlx5r_cmd_query_special_mkeys(dev); 3684 if (err) 3685 return err; 3686 3687 err = mlx5r_macsec_init_gids_and_devlist(dev); 3688 if (err) 3689 return err; 3690 3691 err = mlx5_ib_init_multiport_master(dev); 3692 if (err) 3693 goto err; 3694 3695 err = set_has_smi_cap(dev); 3696 if (err) 3697 goto err_mp; 3698 3699 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3700 if (err) 3701 goto err_mp; 3702 3703 if (mlx5_use_mad_ifc(dev)) 3704 get_ext_port_caps(dev); 3705 3706 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 3707 3708 mutex_init(&dev->cap_mask_mutex); 3709 INIT_LIST_HEAD(&dev->qp_list); 3710 spin_lock_init(&dev->reset_flow_resource_lock); 3711 xa_init(&dev->odp_mkeys); 3712 xa_init(&dev->sig_mrs); 3713 atomic_set(&dev->mkey_var, 0); 3714 3715 spin_lock_init(&dev->dm.lock); 3716 dev->dm.dev = mdev; 3717 return 0; 3718 err: 3719 mlx5r_macsec_dealloc_gids(dev); 3720 err_mp: 3721 mlx5_ib_cleanup_multiport_master(dev); 3722 return err; 3723 } 3724 3725 static int mlx5_ib_enable_driver(struct ib_device *dev) 3726 { 3727 struct mlx5_ib_dev *mdev = to_mdev(dev); 3728 int ret; 3729 3730 ret = mlx5_ib_test_wc(mdev); 3731 mlx5_ib_dbg(mdev, "Write-Combining %s", 3732 mdev->wc_support ? "supported" : "not supported"); 3733 3734 return ret; 3735 } 3736 3737 static const struct ib_device_ops mlx5_ib_dev_ops = { 3738 .owner = THIS_MODULE, 3739 .driver_id = RDMA_DRIVER_MLX5, 3740 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3741 3742 .add_gid = mlx5_ib_add_gid, 3743 .alloc_mr = mlx5_ib_alloc_mr, 3744 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3745 .alloc_pd = mlx5_ib_alloc_pd, 3746 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3747 .attach_mcast = mlx5_ib_mcg_attach, 3748 .check_mr_status = mlx5_ib_check_mr_status, 3749 .create_ah = mlx5_ib_create_ah, 3750 .create_cq = mlx5_ib_create_cq, 3751 .create_qp = mlx5_ib_create_qp, 3752 .create_srq = mlx5_ib_create_srq, 3753 .create_user_ah = mlx5_ib_create_ah, 3754 .dealloc_pd = mlx5_ib_dealloc_pd, 3755 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3756 .del_gid = mlx5_ib_del_gid, 3757 .dereg_mr = mlx5_ib_dereg_mr, 3758 .destroy_ah = mlx5_ib_destroy_ah, 3759 .destroy_cq = mlx5_ib_destroy_cq, 3760 .destroy_qp = mlx5_ib_destroy_qp, 3761 .destroy_srq = mlx5_ib_destroy_srq, 3762 .detach_mcast = mlx5_ib_mcg_detach, 3763 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3764 .drain_rq = mlx5_ib_drain_rq, 3765 .drain_sq = mlx5_ib_drain_sq, 3766 .device_group = &mlx5_attr_group, 3767 .enable_driver = mlx5_ib_enable_driver, 3768 .get_dev_fw_str = get_dev_fw_str, 3769 .get_dma_mr = mlx5_ib_get_dma_mr, 3770 .get_link_layer = mlx5_ib_port_link_layer, 3771 .map_mr_sg = mlx5_ib_map_mr_sg, 3772 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3773 .mmap = mlx5_ib_mmap, 3774 .mmap_free = mlx5_ib_mmap_free, 3775 .modify_cq = mlx5_ib_modify_cq, 3776 .modify_device = mlx5_ib_modify_device, 3777 .modify_port = mlx5_ib_modify_port, 3778 .modify_qp = mlx5_ib_modify_qp, 3779 .modify_srq = mlx5_ib_modify_srq, 3780 .poll_cq = mlx5_ib_poll_cq, 3781 .post_recv = mlx5_ib_post_recv_nodrain, 3782 .post_send = mlx5_ib_post_send_nodrain, 3783 .post_srq_recv = mlx5_ib_post_srq_recv, 3784 .process_mad = mlx5_ib_process_mad, 3785 .query_ah = mlx5_ib_query_ah, 3786 .query_device = mlx5_ib_query_device, 3787 .query_gid = mlx5_ib_query_gid, 3788 .query_pkey = mlx5_ib_query_pkey, 3789 .query_qp = mlx5_ib_query_qp, 3790 .query_srq = mlx5_ib_query_srq, 3791 .query_ucontext = mlx5_ib_query_ucontext, 3792 .reg_user_mr = mlx5_ib_reg_user_mr, 3793 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3794 .req_notify_cq = mlx5_ib_arm_cq, 3795 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3796 .resize_cq = mlx5_ib_resize_cq, 3797 3798 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3799 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3800 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3801 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3802 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3803 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3804 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3805 }; 3806 3807 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3808 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3809 }; 3810 3811 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3812 .get_vf_config = mlx5_ib_get_vf_config, 3813 .get_vf_guid = mlx5_ib_get_vf_guid, 3814 .get_vf_stats = mlx5_ib_get_vf_stats, 3815 .set_vf_guid = mlx5_ib_set_vf_guid, 3816 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3817 }; 3818 3819 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3820 .alloc_mw = mlx5_ib_alloc_mw, 3821 .dealloc_mw = mlx5_ib_dealloc_mw, 3822 3823 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3824 }; 3825 3826 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3827 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3828 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3829 3830 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3831 }; 3832 3833 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3834 { 3835 struct mlx5_core_dev *mdev = dev->mdev; 3836 struct mlx5_var_table *var_table = &dev->var_table; 3837 u8 log_doorbell_bar_size; 3838 u8 log_doorbell_stride; 3839 u64 bar_size; 3840 3841 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3842 log_doorbell_bar_size); 3843 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3844 log_doorbell_stride); 3845 var_table->hw_start_addr = dev->mdev->bar_addr + 3846 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3847 doorbell_bar_offset); 3848 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3849 var_table->stride_size = 1ULL << log_doorbell_stride; 3850 var_table->num_var_hw_entries = div_u64(bar_size, 3851 var_table->stride_size); 3852 mutex_init(&var_table->bitmap_lock); 3853 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3854 GFP_KERNEL); 3855 return (var_table->bitmap) ? 0 : -ENOMEM; 3856 } 3857 3858 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3859 { 3860 bitmap_free(dev->var_table.bitmap); 3861 } 3862 3863 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3864 { 3865 struct mlx5_core_dev *mdev = dev->mdev; 3866 int err; 3867 3868 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3869 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3870 ib_set_device_ops(&dev->ib_dev, 3871 &mlx5_ib_dev_ipoib_enhanced_ops); 3872 3873 if (mlx5_core_is_pf(mdev)) 3874 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3875 3876 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3877 3878 if (MLX5_CAP_GEN(mdev, imaicl)) 3879 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3880 3881 if (MLX5_CAP_GEN(mdev, xrc)) 3882 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3883 3884 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3885 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3886 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3887 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3888 3889 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3890 3891 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3892 dev->ib_dev.driver_def = mlx5_ib_defs; 3893 3894 err = init_node_data(dev); 3895 if (err) 3896 return err; 3897 3898 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3899 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3900 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3901 mutex_init(&dev->lb.mutex); 3902 3903 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3904 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3905 err = mlx5_ib_init_var_table(dev); 3906 if (err) 3907 return err; 3908 } 3909 3910 dev->ib_dev.use_cq_dim = true; 3911 3912 return 0; 3913 } 3914 3915 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3916 .get_port_immutable = mlx5_port_immutable, 3917 .query_port = mlx5_ib_query_port, 3918 }; 3919 3920 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3921 { 3922 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3923 return 0; 3924 } 3925 3926 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3927 .get_port_immutable = mlx5_port_rep_immutable, 3928 .query_port = mlx5_ib_rep_query_port, 3929 .query_pkey = mlx5_ib_rep_query_pkey, 3930 }; 3931 3932 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3933 { 3934 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3935 return 0; 3936 } 3937 3938 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3939 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3940 .create_wq = mlx5_ib_create_wq, 3941 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3942 .destroy_wq = mlx5_ib_destroy_wq, 3943 .get_netdev = mlx5_ib_get_netdev, 3944 .modify_wq = mlx5_ib_modify_wq, 3945 3946 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3947 ib_rwq_ind_tbl), 3948 }; 3949 3950 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3951 { 3952 struct mlx5_core_dev *mdev = dev->mdev; 3953 enum rdma_link_layer ll; 3954 int port_type_cap; 3955 u32 port_num = 0; 3956 int err; 3957 3958 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3959 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3960 3961 if (ll == IB_LINK_LAYER_ETHERNET) { 3962 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3963 3964 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3965 3966 /* Register only for native ports */ 3967 mlx5_mdev_netdev_track(dev, port_num); 3968 3969 err = mlx5_enable_eth(dev); 3970 if (err) 3971 goto cleanup; 3972 } 3973 3974 return 0; 3975 cleanup: 3976 mlx5_mdev_netdev_untrack(dev, port_num); 3977 return err; 3978 } 3979 3980 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3981 { 3982 struct mlx5_core_dev *mdev = dev->mdev; 3983 enum rdma_link_layer ll; 3984 int port_type_cap; 3985 u32 port_num; 3986 3987 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3988 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3989 3990 if (ll == IB_LINK_LAYER_ETHERNET) { 3991 mlx5_disable_eth(dev); 3992 3993 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3994 mlx5_mdev_netdev_untrack(dev, port_num); 3995 } 3996 } 3997 3998 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3999 { 4000 mlx5_ib_init_cong_debugfs(dev, 4001 mlx5_core_native_port_num(dev->mdev) - 1); 4002 return 0; 4003 } 4004 4005 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4006 { 4007 mlx5_ib_cleanup_cong_debugfs(dev, 4008 mlx5_core_native_port_num(dev->mdev) - 1); 4009 } 4010 4011 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4012 { 4013 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4014 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4015 } 4016 4017 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4018 { 4019 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4020 } 4021 4022 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4023 { 4024 int err; 4025 4026 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4027 if (err) 4028 return err; 4029 4030 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4031 if (err) 4032 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4033 4034 return err; 4035 } 4036 4037 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4038 { 4039 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4040 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4041 } 4042 4043 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4044 { 4045 const char *name; 4046 4047 if (!mlx5_lag_is_active(dev->mdev)) 4048 name = "mlx5_%d"; 4049 else 4050 name = "mlx5_bond_%d"; 4051 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4052 } 4053 4054 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4055 { 4056 mlx5_mkey_cache_cleanup(dev); 4057 mlx5r_umr_resource_cleanup(dev); 4058 } 4059 4060 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4061 { 4062 ib_unregister_device(&dev->ib_dev); 4063 } 4064 4065 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4066 { 4067 int ret; 4068 4069 ret = mlx5r_umr_resource_init(dev); 4070 if (ret) 4071 return ret; 4072 4073 ret = mlx5_mkey_cache_init(dev); 4074 if (ret) { 4075 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4076 mlx5r_umr_resource_cleanup(dev); 4077 } 4078 return ret; 4079 } 4080 4081 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4082 { 4083 struct dentry *root; 4084 4085 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4086 return 0; 4087 4088 mutex_init(&dev->delay_drop.lock); 4089 dev->delay_drop.dev = dev; 4090 dev->delay_drop.activate = false; 4091 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4092 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4093 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4094 atomic_set(&dev->delay_drop.events_cnt, 0); 4095 4096 if (!mlx5_debugfs_root) 4097 return 0; 4098 4099 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4100 dev->delay_drop.dir_debugfs = root; 4101 4102 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4103 &dev->delay_drop.events_cnt); 4104 debugfs_create_atomic_t("num_rqs", 0400, root, 4105 &dev->delay_drop.rqs_cnt); 4106 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4107 &fops_delay_drop_timeout); 4108 return 0; 4109 } 4110 4111 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4112 { 4113 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4114 return; 4115 4116 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4117 if (!dev->delay_drop.dir_debugfs) 4118 return; 4119 4120 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4121 dev->delay_drop.dir_debugfs = NULL; 4122 } 4123 4124 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4125 { 4126 dev->mdev_events.notifier_call = mlx5_ib_event; 4127 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4128 4129 mlx5r_macsec_event_register(dev); 4130 4131 return 0; 4132 } 4133 4134 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4135 { 4136 mlx5r_macsec_event_unregister(dev); 4137 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4138 } 4139 4140 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4141 const struct mlx5_ib_profile *profile, 4142 int stage) 4143 { 4144 dev->ib_active = false; 4145 4146 /* Number of stages to cleanup */ 4147 while (stage) { 4148 stage--; 4149 if (profile->stage[stage].cleanup) 4150 profile->stage[stage].cleanup(dev); 4151 } 4152 4153 kfree(dev->port); 4154 ib_dealloc_device(&dev->ib_dev); 4155 } 4156 4157 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4158 const struct mlx5_ib_profile *profile) 4159 { 4160 int err; 4161 int i; 4162 4163 dev->profile = profile; 4164 4165 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4166 if (profile->stage[i].init) { 4167 err = profile->stage[i].init(dev); 4168 if (err) 4169 goto err_out; 4170 } 4171 } 4172 4173 dev->ib_active = true; 4174 return 0; 4175 4176 err_out: 4177 /* Clean up stages which were initialized */ 4178 while (i) { 4179 i--; 4180 if (profile->stage[i].cleanup) 4181 profile->stage[i].cleanup(dev); 4182 } 4183 return -ENOMEM; 4184 } 4185 4186 static const struct mlx5_ib_profile pf_profile = { 4187 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4188 mlx5_ib_stage_init_init, 4189 mlx5_ib_stage_init_cleanup), 4190 STAGE_CREATE(MLX5_IB_STAGE_FS, 4191 mlx5_ib_fs_init, 4192 mlx5_ib_fs_cleanup), 4193 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4194 mlx5_ib_stage_caps_init, 4195 mlx5_ib_stage_caps_cleanup), 4196 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4197 mlx5_ib_stage_non_default_cb, 4198 NULL), 4199 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4200 mlx5_ib_roce_init, 4201 mlx5_ib_roce_cleanup), 4202 STAGE_CREATE(MLX5_IB_STAGE_QP, 4203 mlx5_init_qp_table, 4204 mlx5_cleanup_qp_table), 4205 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4206 mlx5_init_srq_table, 4207 mlx5_cleanup_srq_table), 4208 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4209 mlx5_ib_dev_res_init, 4210 mlx5_ib_dev_res_cleanup), 4211 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4212 mlx5_ib_stage_dev_notifier_init, 4213 mlx5_ib_stage_dev_notifier_cleanup), 4214 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4215 mlx5_ib_odp_init_one, 4216 mlx5_ib_odp_cleanup_one), 4217 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4218 mlx5_ib_counters_init, 4219 mlx5_ib_counters_cleanup), 4220 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4221 mlx5_ib_stage_cong_debugfs_init, 4222 mlx5_ib_stage_cong_debugfs_cleanup), 4223 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4224 mlx5_ib_stage_uar_init, 4225 mlx5_ib_stage_uar_cleanup), 4226 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4227 mlx5_ib_stage_bfrag_init, 4228 mlx5_ib_stage_bfrag_cleanup), 4229 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4230 NULL, 4231 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4232 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4233 mlx5_ib_devx_init, 4234 mlx5_ib_devx_cleanup), 4235 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4236 mlx5_ib_stage_ib_reg_init, 4237 mlx5_ib_stage_ib_reg_cleanup), 4238 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4239 mlx5_ib_stage_post_ib_reg_umr_init, 4240 NULL), 4241 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4242 mlx5_ib_stage_delay_drop_init, 4243 mlx5_ib_stage_delay_drop_cleanup), 4244 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4245 mlx5_ib_restrack_init, 4246 NULL), 4247 }; 4248 4249 const struct mlx5_ib_profile raw_eth_profile = { 4250 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4251 mlx5_ib_stage_init_init, 4252 mlx5_ib_stage_init_cleanup), 4253 STAGE_CREATE(MLX5_IB_STAGE_FS, 4254 mlx5_ib_fs_init, 4255 mlx5_ib_fs_cleanup), 4256 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4257 mlx5_ib_stage_caps_init, 4258 mlx5_ib_stage_caps_cleanup), 4259 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4260 mlx5_ib_stage_raw_eth_non_default_cb, 4261 NULL), 4262 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4263 mlx5_ib_roce_init, 4264 mlx5_ib_roce_cleanup), 4265 STAGE_CREATE(MLX5_IB_STAGE_QP, 4266 mlx5_init_qp_table, 4267 mlx5_cleanup_qp_table), 4268 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4269 mlx5_init_srq_table, 4270 mlx5_cleanup_srq_table), 4271 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4272 mlx5_ib_dev_res_init, 4273 mlx5_ib_dev_res_cleanup), 4274 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4275 mlx5_ib_stage_dev_notifier_init, 4276 mlx5_ib_stage_dev_notifier_cleanup), 4277 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4278 mlx5_ib_counters_init, 4279 mlx5_ib_counters_cleanup), 4280 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4281 mlx5_ib_stage_cong_debugfs_init, 4282 mlx5_ib_stage_cong_debugfs_cleanup), 4283 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4284 mlx5_ib_stage_uar_init, 4285 mlx5_ib_stage_uar_cleanup), 4286 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4287 mlx5_ib_stage_bfrag_init, 4288 mlx5_ib_stage_bfrag_cleanup), 4289 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4290 NULL, 4291 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4292 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4293 mlx5_ib_devx_init, 4294 mlx5_ib_devx_cleanup), 4295 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4296 mlx5_ib_stage_ib_reg_init, 4297 mlx5_ib_stage_ib_reg_cleanup), 4298 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4299 mlx5_ib_stage_post_ib_reg_umr_init, 4300 NULL), 4301 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4302 mlx5_ib_stage_delay_drop_init, 4303 mlx5_ib_stage_delay_drop_cleanup), 4304 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4305 mlx5_ib_restrack_init, 4306 NULL), 4307 }; 4308 4309 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4310 const struct auxiliary_device_id *id) 4311 { 4312 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4313 struct mlx5_core_dev *mdev = idev->mdev; 4314 struct mlx5_ib_multiport_info *mpi; 4315 struct mlx5_ib_dev *dev; 4316 bool bound = false; 4317 int err; 4318 4319 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4320 if (!mpi) 4321 return -ENOMEM; 4322 4323 mpi->mdev = mdev; 4324 err = mlx5_query_nic_vport_system_image_guid(mdev, 4325 &mpi->sys_image_guid); 4326 if (err) { 4327 kfree(mpi); 4328 return err; 4329 } 4330 4331 mutex_lock(&mlx5_ib_multiport_mutex); 4332 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4333 if (dev->sys_image_guid == mpi->sys_image_guid) 4334 bound = mlx5_ib_bind_slave_port(dev, mpi); 4335 4336 if (bound) { 4337 rdma_roce_rescan_device(&dev->ib_dev); 4338 mpi->ibdev->ib_active = true; 4339 break; 4340 } 4341 } 4342 4343 if (!bound) { 4344 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4345 dev_dbg(mdev->device, 4346 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4347 } 4348 mutex_unlock(&mlx5_ib_multiport_mutex); 4349 4350 auxiliary_set_drvdata(adev, mpi); 4351 return 0; 4352 } 4353 4354 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4355 { 4356 struct mlx5_ib_multiport_info *mpi; 4357 4358 mpi = auxiliary_get_drvdata(adev); 4359 mutex_lock(&mlx5_ib_multiport_mutex); 4360 if (mpi->ibdev) 4361 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4362 else 4363 list_del(&mpi->list); 4364 mutex_unlock(&mlx5_ib_multiport_mutex); 4365 kfree(mpi); 4366 } 4367 4368 static int mlx5r_probe(struct auxiliary_device *adev, 4369 const struct auxiliary_device_id *id) 4370 { 4371 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4372 struct mlx5_core_dev *mdev = idev->mdev; 4373 const struct mlx5_ib_profile *profile; 4374 int port_type_cap, num_ports, ret; 4375 enum rdma_link_layer ll; 4376 struct mlx5_ib_dev *dev; 4377 4378 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4379 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4380 4381 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4382 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4383 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4384 if (!dev) 4385 return -ENOMEM; 4386 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4387 GFP_KERNEL); 4388 if (!dev->port) { 4389 ib_dealloc_device(&dev->ib_dev); 4390 return -ENOMEM; 4391 } 4392 4393 dev->mdev = mdev; 4394 dev->num_ports = num_ports; 4395 4396 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4397 profile = &raw_eth_profile; 4398 else 4399 profile = &pf_profile; 4400 4401 ret = __mlx5_ib_add(dev, profile); 4402 if (ret) { 4403 kfree(dev->port); 4404 ib_dealloc_device(&dev->ib_dev); 4405 return ret; 4406 } 4407 4408 auxiliary_set_drvdata(adev, dev); 4409 return 0; 4410 } 4411 4412 static void mlx5r_remove(struct auxiliary_device *adev) 4413 { 4414 struct mlx5_ib_dev *dev; 4415 4416 dev = auxiliary_get_drvdata(adev); 4417 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4418 } 4419 4420 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4421 { .name = MLX5_ADEV_NAME ".multiport", }, 4422 {}, 4423 }; 4424 4425 static const struct auxiliary_device_id mlx5r_id_table[] = { 4426 { .name = MLX5_ADEV_NAME ".rdma", }, 4427 {}, 4428 }; 4429 4430 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4431 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4432 4433 static struct auxiliary_driver mlx5r_mp_driver = { 4434 .name = "multiport", 4435 .probe = mlx5r_mp_probe, 4436 .remove = mlx5r_mp_remove, 4437 .id_table = mlx5r_mp_id_table, 4438 }; 4439 4440 static struct auxiliary_driver mlx5r_driver = { 4441 .name = "rdma", 4442 .probe = mlx5r_probe, 4443 .remove = mlx5r_remove, 4444 .id_table = mlx5r_id_table, 4445 }; 4446 4447 static int __init mlx5_ib_init(void) 4448 { 4449 int ret; 4450 4451 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4452 if (!xlt_emergency_page) 4453 return -ENOMEM; 4454 4455 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4456 if (!mlx5_ib_event_wq) { 4457 free_page((unsigned long)xlt_emergency_page); 4458 return -ENOMEM; 4459 } 4460 4461 ret = mlx5_ib_qp_event_init(); 4462 if (ret) 4463 goto qp_event_err; 4464 4465 mlx5_ib_odp_init(); 4466 ret = mlx5r_rep_init(); 4467 if (ret) 4468 goto rep_err; 4469 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4470 if (ret) 4471 goto mp_err; 4472 ret = auxiliary_driver_register(&mlx5r_driver); 4473 if (ret) 4474 goto drv_err; 4475 return 0; 4476 4477 drv_err: 4478 auxiliary_driver_unregister(&mlx5r_mp_driver); 4479 mp_err: 4480 mlx5r_rep_cleanup(); 4481 rep_err: 4482 mlx5_ib_qp_event_cleanup(); 4483 qp_event_err: 4484 destroy_workqueue(mlx5_ib_event_wq); 4485 free_page((unsigned long)xlt_emergency_page); 4486 return ret; 4487 } 4488 4489 static void __exit mlx5_ib_cleanup(void) 4490 { 4491 auxiliary_driver_unregister(&mlx5r_driver); 4492 auxiliary_driver_unregister(&mlx5r_mp_driver); 4493 mlx5r_rep_cleanup(); 4494 4495 mlx5_ib_qp_event_cleanup(); 4496 destroy_workqueue(mlx5_ib_event_wq); 4497 free_page((unsigned long)xlt_emergency_page); 4498 } 4499 4500 module_init(mlx5_ib_init); 4501 module_exit(mlx5_ib_cleanup); 4502