1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 */ 5 6 #include <linux/debugfs.h> 7 #include <linux/highmem.h> 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/slab.h> 14 #include <linux/bitmap.h> 15 #include <linux/sched.h> 16 #include <linux/sched/mm.h> 17 #include <linux/sched/task.h> 18 #include <linux/delay.h> 19 #include <rdma/ib_user_verbs.h> 20 #include <rdma/ib_addr.h> 21 #include <rdma/ib_cache.h> 22 #include <linux/mlx5/port.h> 23 #include <linux/mlx5/vport.h> 24 #include <linux/mlx5/fs.h> 25 #include <linux/mlx5/eswitch.h> 26 #include <linux/list.h> 27 #include <rdma/ib_smi.h> 28 #include <rdma/ib_umem.h> 29 #include <rdma/lag.h> 30 #include <linux/in.h> 31 #include <linux/etherdevice.h> 32 #include "mlx5_ib.h" 33 #include "ib_rep.h" 34 #include "cmd.h" 35 #include "devx.h" 36 #include "fs.h" 37 #include "srq.h" 38 #include "qp.h" 39 #include "wr.h" 40 #include "restrack.h" 41 #include "counters.h" 42 #include <linux/mlx5/accel.h> 43 #include <rdma/uverbs_std_types.h> 44 #include <rdma/mlx5_user_ioctl_verbs.h> 45 #include <rdma/mlx5_user_ioctl_cmds.h> 46 #include <rdma/ib_umem_odp.h> 47 48 #define UVERBS_MODULE_NAME mlx5_ib 49 #include <rdma/uverbs_named_ioctl.h> 50 51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 52 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 53 MODULE_LICENSE("Dual BSD/GPL"); 54 55 struct mlx5_ib_event_work { 56 struct work_struct work; 57 union { 58 struct mlx5_ib_dev *dev; 59 struct mlx5_ib_multiport_info *mpi; 60 }; 61 bool is_slave; 62 unsigned int event; 63 void *param; 64 }; 65 66 enum { 67 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 68 }; 69 70 static struct workqueue_struct *mlx5_ib_event_wq; 71 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 72 static LIST_HEAD(mlx5_ib_dev_list); 73 /* 74 * This mutex should be held when accessing either of the above lists 75 */ 76 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 77 78 /* We can't use an array for xlt_emergency_page because dma_map_single 79 * doesn't work on kernel modules memory 80 */ 81 static unsigned long xlt_emergency_page; 82 static struct mutex xlt_emergency_page_mutex; 83 84 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 85 { 86 struct mlx5_ib_dev *dev; 87 88 mutex_lock(&mlx5_ib_multiport_mutex); 89 dev = mpi->ibdev; 90 mutex_unlock(&mlx5_ib_multiport_mutex); 91 return dev; 92 } 93 94 static enum rdma_link_layer 95 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 96 { 97 switch (port_type_cap) { 98 case MLX5_CAP_PORT_TYPE_IB: 99 return IB_LINK_LAYER_INFINIBAND; 100 case MLX5_CAP_PORT_TYPE_ETH: 101 return IB_LINK_LAYER_ETHERNET; 102 default: 103 return IB_LINK_LAYER_UNSPECIFIED; 104 } 105 } 106 107 static enum rdma_link_layer 108 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 109 { 110 struct mlx5_ib_dev *dev = to_mdev(device); 111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 112 113 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 114 } 115 116 static int get_port_state(struct ib_device *ibdev, 117 u8 port_num, 118 enum ib_port_state *state) 119 { 120 struct ib_port_attr attr; 121 int ret; 122 123 memset(&attr, 0, sizeof(attr)); 124 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 125 if (!ret) 126 *state = attr.state; 127 return ret; 128 } 129 130 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 131 struct net_device *ndev, 132 u8 *port_num) 133 { 134 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 135 struct net_device *rep_ndev; 136 struct mlx5_ib_port *port; 137 int i; 138 139 for (i = 0; i < dev->num_ports; i++) { 140 port = &dev->port[i]; 141 if (!port->rep) 142 continue; 143 144 read_lock(&port->roce.netdev_lock); 145 rep_ndev = mlx5_ib_get_rep_netdev(esw, 146 port->rep->vport); 147 if (rep_ndev == ndev) { 148 read_unlock(&port->roce.netdev_lock); 149 *port_num = i + 1; 150 return &port->roce; 151 } 152 read_unlock(&port->roce.netdev_lock); 153 } 154 155 return NULL; 156 } 157 158 static int mlx5_netdev_event(struct notifier_block *this, 159 unsigned long event, void *ptr) 160 { 161 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 162 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 163 u8 port_num = roce->native_port_num; 164 struct mlx5_core_dev *mdev; 165 struct mlx5_ib_dev *ibdev; 166 167 ibdev = roce->dev; 168 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 169 if (!mdev) 170 return NOTIFY_DONE; 171 172 switch (event) { 173 case NETDEV_REGISTER: 174 /* Should already be registered during the load */ 175 if (ibdev->is_rep) 176 break; 177 write_lock(&roce->netdev_lock); 178 if (ndev->dev.parent == mdev->device) 179 roce->netdev = ndev; 180 write_unlock(&roce->netdev_lock); 181 break; 182 183 case NETDEV_UNREGISTER: 184 /* In case of reps, ib device goes away before the netdevs */ 185 write_lock(&roce->netdev_lock); 186 if (roce->netdev == ndev) 187 roce->netdev = NULL; 188 write_unlock(&roce->netdev_lock); 189 break; 190 191 case NETDEV_CHANGE: 192 case NETDEV_UP: 193 case NETDEV_DOWN: { 194 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 195 struct net_device *upper = NULL; 196 197 if (lag_ndev) { 198 upper = netdev_master_upper_dev_get(lag_ndev); 199 dev_put(lag_ndev); 200 } 201 202 if (ibdev->is_rep) 203 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 204 if (!roce) 205 return NOTIFY_DONE; 206 if ((upper == ndev || (!upper && ndev == roce->netdev)) 207 && ibdev->ib_active) { 208 struct ib_event ibev = { }; 209 enum ib_port_state port_state; 210 211 if (get_port_state(&ibdev->ib_dev, port_num, 212 &port_state)) 213 goto done; 214 215 if (roce->last_port_state == port_state) 216 goto done; 217 218 roce->last_port_state = port_state; 219 ibev.device = &ibdev->ib_dev; 220 if (port_state == IB_PORT_DOWN) 221 ibev.event = IB_EVENT_PORT_ERR; 222 else if (port_state == IB_PORT_ACTIVE) 223 ibev.event = IB_EVENT_PORT_ACTIVE; 224 else 225 goto done; 226 227 ibev.element.port_num = port_num; 228 ib_dispatch_event(&ibev); 229 } 230 break; 231 } 232 233 default: 234 break; 235 } 236 done: 237 mlx5_ib_put_native_port_mdev(ibdev, port_num); 238 return NOTIFY_DONE; 239 } 240 241 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 242 u8 port_num) 243 { 244 struct mlx5_ib_dev *ibdev = to_mdev(device); 245 struct net_device *ndev; 246 struct mlx5_core_dev *mdev; 247 248 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 249 if (!mdev) 250 return NULL; 251 252 ndev = mlx5_lag_get_roce_netdev(mdev); 253 if (ndev) 254 goto out; 255 256 /* Ensure ndev does not disappear before we invoke dev_hold() 257 */ 258 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 259 ndev = ibdev->port[port_num - 1].roce.netdev; 260 if (ndev) 261 dev_hold(ndev); 262 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 263 264 out: 265 mlx5_ib_put_native_port_mdev(ibdev, port_num); 266 return ndev; 267 } 268 269 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 270 u8 ib_port_num, 271 u8 *native_port_num) 272 { 273 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 274 ib_port_num); 275 struct mlx5_core_dev *mdev = NULL; 276 struct mlx5_ib_multiport_info *mpi; 277 struct mlx5_ib_port *port; 278 279 if (!mlx5_core_mp_enabled(ibdev->mdev) || 280 ll != IB_LINK_LAYER_ETHERNET) { 281 if (native_port_num) 282 *native_port_num = ib_port_num; 283 return ibdev->mdev; 284 } 285 286 if (native_port_num) 287 *native_port_num = 1; 288 289 port = &ibdev->port[ib_port_num - 1]; 290 spin_lock(&port->mp.mpi_lock); 291 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 292 if (mpi && !mpi->unaffiliate) { 293 mdev = mpi->mdev; 294 /* If it's the master no need to refcount, it'll exist 295 * as long as the ib_dev exists. 296 */ 297 if (!mpi->is_master) 298 mpi->mdev_refcnt++; 299 } 300 spin_unlock(&port->mp.mpi_lock); 301 302 return mdev; 303 } 304 305 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 306 { 307 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 308 port_num); 309 struct mlx5_ib_multiport_info *mpi; 310 struct mlx5_ib_port *port; 311 312 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 313 return; 314 315 port = &ibdev->port[port_num - 1]; 316 317 spin_lock(&port->mp.mpi_lock); 318 mpi = ibdev->port[port_num - 1].mp.mpi; 319 if (mpi->is_master) 320 goto out; 321 322 mpi->mdev_refcnt--; 323 if (mpi->unaffiliate) 324 complete(&mpi->unref_comp); 325 out: 326 spin_unlock(&port->mp.mpi_lock); 327 } 328 329 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed, 330 u8 *active_width) 331 { 332 switch (eth_proto_oper) { 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 334 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 335 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 336 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 337 *active_width = IB_WIDTH_1X; 338 *active_speed = IB_SPEED_SDR; 339 break; 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 344 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 347 *active_width = IB_WIDTH_1X; 348 *active_speed = IB_SPEED_QDR; 349 break; 350 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 351 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 352 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 353 *active_width = IB_WIDTH_1X; 354 *active_speed = IB_SPEED_EDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 357 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 358 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 359 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 360 *active_width = IB_WIDTH_4X; 361 *active_speed = IB_SPEED_QDR; 362 break; 363 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 364 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 365 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 366 *active_width = IB_WIDTH_1X; 367 *active_speed = IB_SPEED_HDR; 368 break; 369 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 370 *active_width = IB_WIDTH_4X; 371 *active_speed = IB_SPEED_FDR; 372 break; 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 374 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 375 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 376 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 377 *active_width = IB_WIDTH_4X; 378 *active_speed = IB_SPEED_EDR; 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 return 0; 385 } 386 387 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 388 u8 *active_width) 389 { 390 switch (eth_proto_oper) { 391 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 392 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 393 *active_width = IB_WIDTH_1X; 394 *active_speed = IB_SPEED_SDR; 395 break; 396 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 397 *active_width = IB_WIDTH_1X; 398 *active_speed = IB_SPEED_DDR; 399 break; 400 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 401 *active_width = IB_WIDTH_1X; 402 *active_speed = IB_SPEED_QDR; 403 break; 404 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 405 *active_width = IB_WIDTH_4X; 406 *active_speed = IB_SPEED_QDR; 407 break; 408 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 409 *active_width = IB_WIDTH_1X; 410 *active_speed = IB_SPEED_EDR; 411 break; 412 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 413 *active_width = IB_WIDTH_2X; 414 *active_speed = IB_SPEED_EDR; 415 break; 416 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 417 *active_width = IB_WIDTH_1X; 418 *active_speed = IB_SPEED_HDR; 419 break; 420 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 421 *active_width = IB_WIDTH_4X; 422 *active_speed = IB_SPEED_EDR; 423 break; 424 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 425 *active_width = IB_WIDTH_2X; 426 *active_speed = IB_SPEED_HDR; 427 break; 428 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 429 *active_width = IB_WIDTH_4X; 430 *active_speed = IB_SPEED_HDR; 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 440 u8 *active_width, bool ext) 441 { 442 return ext ? 443 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 444 active_width) : 445 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 446 active_width); 447 } 448 449 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 450 struct ib_port_attr *props) 451 { 452 struct mlx5_ib_dev *dev = to_mdev(device); 453 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 454 struct mlx5_core_dev *mdev; 455 struct net_device *ndev, *upper; 456 enum ib_mtu ndev_ib_mtu; 457 bool put_mdev = true; 458 u16 qkey_viol_cntr; 459 u32 eth_prot_oper; 460 u8 mdev_port_num; 461 bool ext; 462 int err; 463 464 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 465 if (!mdev) { 466 /* This means the port isn't affiliated yet. Get the 467 * info for the master port instead. 468 */ 469 put_mdev = false; 470 mdev = dev->mdev; 471 mdev_port_num = 1; 472 port_num = 1; 473 } 474 475 /* Possible bad flows are checked before filling out props so in case 476 * of an error it will still be zeroed out. 477 * Use native port in case of reps 478 */ 479 if (dev->is_rep) 480 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 481 1); 482 else 483 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 484 mdev_port_num); 485 if (err) 486 goto out; 487 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 488 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 489 490 props->active_width = IB_WIDTH_4X; 491 props->active_speed = IB_SPEED_QDR; 492 493 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 494 &props->active_width, ext); 495 496 props->port_cap_flags |= IB_PORT_CM_SUP; 497 props->ip_gids = true; 498 499 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 500 roce_address_table_size); 501 props->max_mtu = IB_MTU_4096; 502 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 503 props->pkey_tbl_len = 1; 504 props->state = IB_PORT_DOWN; 505 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 506 507 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 508 props->qkey_viol_cntr = qkey_viol_cntr; 509 510 /* If this is a stub query for an unaffiliated port stop here */ 511 if (!put_mdev) 512 goto out; 513 514 ndev = mlx5_ib_get_netdev(device, port_num); 515 if (!ndev) 516 goto out; 517 518 if (dev->lag_active) { 519 rcu_read_lock(); 520 upper = netdev_master_upper_dev_get_rcu(ndev); 521 if (upper) { 522 dev_put(ndev); 523 ndev = upper; 524 dev_hold(ndev); 525 } 526 rcu_read_unlock(); 527 } 528 529 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 530 props->state = IB_PORT_ACTIVE; 531 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 532 } 533 534 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 535 536 dev_put(ndev); 537 538 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 539 out: 540 if (put_mdev) 541 mlx5_ib_put_native_port_mdev(dev, port_num); 542 return err; 543 } 544 545 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 546 unsigned int index, const union ib_gid *gid, 547 const struct ib_gid_attr *attr) 548 { 549 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 550 u16 vlan_id = 0xffff; 551 u8 roce_version = 0; 552 u8 roce_l3_type = 0; 553 u8 mac[ETH_ALEN]; 554 int ret; 555 556 if (gid) { 557 gid_type = attr->gid_type; 558 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 559 if (ret) 560 return ret; 561 } 562 563 switch (gid_type) { 564 case IB_GID_TYPE_IB: 565 roce_version = MLX5_ROCE_VERSION_1; 566 break; 567 case IB_GID_TYPE_ROCE_UDP_ENCAP: 568 roce_version = MLX5_ROCE_VERSION_2; 569 if (ipv6_addr_v4mapped((void *)gid)) 570 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 571 else 572 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 573 break; 574 575 default: 576 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 577 } 578 579 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 580 roce_l3_type, gid->raw, mac, 581 vlan_id < VLAN_CFI_MASK, vlan_id, 582 port_num); 583 } 584 585 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 586 __always_unused void **context) 587 { 588 return set_roce_addr(to_mdev(attr->device), attr->port_num, 589 attr->index, &attr->gid, attr); 590 } 591 592 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 593 __always_unused void **context) 594 { 595 return set_roce_addr(to_mdev(attr->device), attr->port_num, 596 attr->index, NULL, NULL); 597 } 598 599 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 600 const struct ib_gid_attr *attr) 601 { 602 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 603 return 0; 604 605 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 606 } 607 608 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 609 { 610 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 611 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 612 return 0; 613 } 614 615 enum { 616 MLX5_VPORT_ACCESS_METHOD_MAD, 617 MLX5_VPORT_ACCESS_METHOD_HCA, 618 MLX5_VPORT_ACCESS_METHOD_NIC, 619 }; 620 621 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 622 { 623 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 624 return MLX5_VPORT_ACCESS_METHOD_MAD; 625 626 if (mlx5_ib_port_link_layer(ibdev, 1) == 627 IB_LINK_LAYER_ETHERNET) 628 return MLX5_VPORT_ACCESS_METHOD_NIC; 629 630 return MLX5_VPORT_ACCESS_METHOD_HCA; 631 } 632 633 static void get_atomic_caps(struct mlx5_ib_dev *dev, 634 u8 atomic_size_qp, 635 struct ib_device_attr *props) 636 { 637 u8 tmp; 638 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 639 u8 atomic_req_8B_endianness_mode = 640 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 641 642 /* Check if HW supports 8 bytes standard atomic operations and capable 643 * of host endianness respond 644 */ 645 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 646 if (((atomic_operations & tmp) == tmp) && 647 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 648 (atomic_req_8B_endianness_mode)) { 649 props->atomic_cap = IB_ATOMIC_HCA; 650 } else { 651 props->atomic_cap = IB_ATOMIC_NONE; 652 } 653 } 654 655 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 656 struct ib_device_attr *props) 657 { 658 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 659 660 get_atomic_caps(dev, atomic_size_qp, props); 661 } 662 663 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 664 __be64 *sys_image_guid) 665 { 666 struct mlx5_ib_dev *dev = to_mdev(ibdev); 667 struct mlx5_core_dev *mdev = dev->mdev; 668 u64 tmp; 669 int err; 670 671 switch (mlx5_get_vport_access_method(ibdev)) { 672 case MLX5_VPORT_ACCESS_METHOD_MAD: 673 return mlx5_query_mad_ifc_system_image_guid(ibdev, 674 sys_image_guid); 675 676 case MLX5_VPORT_ACCESS_METHOD_HCA: 677 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 678 break; 679 680 case MLX5_VPORT_ACCESS_METHOD_NIC: 681 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 682 break; 683 684 default: 685 return -EINVAL; 686 } 687 688 if (!err) 689 *sys_image_guid = cpu_to_be64(tmp); 690 691 return err; 692 693 } 694 695 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 696 u16 *max_pkeys) 697 { 698 struct mlx5_ib_dev *dev = to_mdev(ibdev); 699 struct mlx5_core_dev *mdev = dev->mdev; 700 701 switch (mlx5_get_vport_access_method(ibdev)) { 702 case MLX5_VPORT_ACCESS_METHOD_MAD: 703 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 704 705 case MLX5_VPORT_ACCESS_METHOD_HCA: 706 case MLX5_VPORT_ACCESS_METHOD_NIC: 707 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 708 pkey_table_size)); 709 return 0; 710 711 default: 712 return -EINVAL; 713 } 714 } 715 716 static int mlx5_query_vendor_id(struct ib_device *ibdev, 717 u32 *vendor_id) 718 { 719 struct mlx5_ib_dev *dev = to_mdev(ibdev); 720 721 switch (mlx5_get_vport_access_method(ibdev)) { 722 case MLX5_VPORT_ACCESS_METHOD_MAD: 723 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 724 725 case MLX5_VPORT_ACCESS_METHOD_HCA: 726 case MLX5_VPORT_ACCESS_METHOD_NIC: 727 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 728 729 default: 730 return -EINVAL; 731 } 732 } 733 734 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 735 __be64 *node_guid) 736 { 737 u64 tmp; 738 int err; 739 740 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 741 case MLX5_VPORT_ACCESS_METHOD_MAD: 742 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 743 744 case MLX5_VPORT_ACCESS_METHOD_HCA: 745 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 746 break; 747 748 case MLX5_VPORT_ACCESS_METHOD_NIC: 749 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 750 break; 751 752 default: 753 return -EINVAL; 754 } 755 756 if (!err) 757 *node_guid = cpu_to_be64(tmp); 758 759 return err; 760 } 761 762 struct mlx5_reg_node_desc { 763 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 764 }; 765 766 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 767 { 768 struct mlx5_reg_node_desc in; 769 770 if (mlx5_use_mad_ifc(dev)) 771 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 772 773 memset(&in, 0, sizeof(in)); 774 775 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 776 sizeof(struct mlx5_reg_node_desc), 777 MLX5_REG_NODE_DESC, 0, 0); 778 } 779 780 static int mlx5_ib_query_device(struct ib_device *ibdev, 781 struct ib_device_attr *props, 782 struct ib_udata *uhw) 783 { 784 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 785 struct mlx5_ib_dev *dev = to_mdev(ibdev); 786 struct mlx5_core_dev *mdev = dev->mdev; 787 int err = -ENOMEM; 788 int max_sq_desc; 789 int max_rq_sg; 790 int max_sq_sg; 791 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 792 bool raw_support = !mlx5_core_mp_enabled(mdev); 793 struct mlx5_ib_query_device_resp resp = {}; 794 size_t resp_len; 795 u64 max_tso; 796 797 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 798 if (uhw_outlen && uhw_outlen < resp_len) 799 return -EINVAL; 800 801 resp.response_length = resp_len; 802 803 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 804 return -EINVAL; 805 806 memset(props, 0, sizeof(*props)); 807 err = mlx5_query_system_image_guid(ibdev, 808 &props->sys_image_guid); 809 if (err) 810 return err; 811 812 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 813 if (err) 814 return err; 815 816 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 817 if (err) 818 return err; 819 820 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 821 (fw_rev_min(dev->mdev) << 16) | 822 fw_rev_sub(dev->mdev); 823 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 824 IB_DEVICE_PORT_ACTIVE_EVENT | 825 IB_DEVICE_SYS_IMAGE_GUID | 826 IB_DEVICE_RC_RNR_NAK_GEN; 827 828 if (MLX5_CAP_GEN(mdev, pkv)) 829 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 830 if (MLX5_CAP_GEN(mdev, qkv)) 831 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 832 if (MLX5_CAP_GEN(mdev, apm)) 833 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 834 if (MLX5_CAP_GEN(mdev, xrc)) 835 props->device_cap_flags |= IB_DEVICE_XRC; 836 if (MLX5_CAP_GEN(mdev, imaicl)) { 837 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 838 IB_DEVICE_MEM_WINDOW_TYPE_2B; 839 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 840 /* We support 'Gappy' memory registration too */ 841 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 842 } 843 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 844 if (MLX5_CAP_GEN(mdev, sho)) { 845 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 846 /* At this stage no support for signature handover */ 847 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 848 IB_PROT_T10DIF_TYPE_2 | 849 IB_PROT_T10DIF_TYPE_3; 850 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 851 IB_GUARD_T10DIF_CSUM; 852 } 853 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 854 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 855 856 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 857 if (MLX5_CAP_ETH(mdev, csum_cap)) { 858 /* Legacy bit to support old userspace libraries */ 859 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 860 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 861 } 862 863 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 864 props->raw_packet_caps |= 865 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 866 867 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 868 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 869 if (max_tso) { 870 resp.tso_caps.max_tso = 1 << max_tso; 871 resp.tso_caps.supported_qpts |= 872 1 << IB_QPT_RAW_PACKET; 873 resp.response_length += sizeof(resp.tso_caps); 874 } 875 } 876 877 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 878 resp.rss_caps.rx_hash_function = 879 MLX5_RX_HASH_FUNC_TOEPLITZ; 880 resp.rss_caps.rx_hash_fields_mask = 881 MLX5_RX_HASH_SRC_IPV4 | 882 MLX5_RX_HASH_DST_IPV4 | 883 MLX5_RX_HASH_SRC_IPV6 | 884 MLX5_RX_HASH_DST_IPV6 | 885 MLX5_RX_HASH_SRC_PORT_TCP | 886 MLX5_RX_HASH_DST_PORT_TCP | 887 MLX5_RX_HASH_SRC_PORT_UDP | 888 MLX5_RX_HASH_DST_PORT_UDP | 889 MLX5_RX_HASH_INNER; 890 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 891 MLX5_ACCEL_IPSEC_CAP_DEVICE) 892 resp.rss_caps.rx_hash_fields_mask |= 893 MLX5_RX_HASH_IPSEC_SPI; 894 resp.response_length += sizeof(resp.rss_caps); 895 } 896 } else { 897 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 898 resp.response_length += sizeof(resp.tso_caps); 899 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 900 resp.response_length += sizeof(resp.rss_caps); 901 } 902 903 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 904 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 905 props->device_cap_flags |= IB_DEVICE_UD_TSO; 906 } 907 908 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 909 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 910 raw_support) 911 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 912 913 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 914 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 915 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 916 917 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 918 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 919 raw_support) { 920 /* Legacy bit to support old userspace libraries */ 921 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 922 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 923 } 924 925 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 926 props->max_dm_size = 927 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 928 } 929 930 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 931 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 932 933 if (MLX5_CAP_GEN(mdev, end_pad)) 934 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 935 936 props->vendor_part_id = mdev->pdev->device; 937 props->hw_ver = mdev->pdev->revision; 938 939 props->max_mr_size = ~0ull; 940 props->page_size_cap = ~(min_page_size - 1); 941 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 942 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 943 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 944 sizeof(struct mlx5_wqe_data_seg); 945 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 946 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 947 sizeof(struct mlx5_wqe_raddr_seg)) / 948 sizeof(struct mlx5_wqe_data_seg); 949 props->max_send_sge = max_sq_sg; 950 props->max_recv_sge = max_rq_sg; 951 props->max_sge_rd = MLX5_MAX_SGE_RD; 952 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 953 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 954 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 955 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 956 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 957 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 958 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 959 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 960 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 961 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 962 props->max_srq_sge = max_rq_sg - 1; 963 props->max_fast_reg_page_list_len = 964 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 965 props->max_pi_fast_reg_page_list_len = 966 props->max_fast_reg_page_list_len / 2; 967 props->max_sgl_rd = 968 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 969 get_atomic_caps_qp(dev, props); 970 props->masked_atomic_cap = IB_ATOMIC_NONE; 971 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 972 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 973 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 974 props->max_mcast_grp; 975 props->max_ah = INT_MAX; 976 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 977 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 978 979 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 980 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 981 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 982 props->odp_caps = dev->odp_caps; 983 if (!uhw) { 984 /* ODP for kernel QPs is not implemented for receive 985 * WQEs and SRQ WQEs 986 */ 987 props->odp_caps.per_transport_caps.rc_odp_caps &= 988 ~(IB_ODP_SUPPORT_READ | 989 IB_ODP_SUPPORT_SRQ_RECV); 990 props->odp_caps.per_transport_caps.uc_odp_caps &= 991 ~(IB_ODP_SUPPORT_READ | 992 IB_ODP_SUPPORT_SRQ_RECV); 993 props->odp_caps.per_transport_caps.ud_odp_caps &= 994 ~(IB_ODP_SUPPORT_READ | 995 IB_ODP_SUPPORT_SRQ_RECV); 996 props->odp_caps.per_transport_caps.xrc_odp_caps &= 997 ~(IB_ODP_SUPPORT_READ | 998 IB_ODP_SUPPORT_SRQ_RECV); 999 } 1000 } 1001 1002 if (MLX5_CAP_GEN(mdev, cd)) 1003 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1004 1005 if (mlx5_core_is_vf(mdev)) 1006 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1007 1008 if (mlx5_ib_port_link_layer(ibdev, 1) == 1009 IB_LINK_LAYER_ETHERNET && raw_support) { 1010 props->rss_caps.max_rwq_indirection_tables = 1011 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1012 props->rss_caps.max_rwq_indirection_table_size = 1013 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1014 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1015 props->max_wq_type_rq = 1016 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1017 } 1018 1019 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1020 props->tm_caps.max_num_tags = 1021 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1022 props->tm_caps.max_ops = 1023 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1024 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1025 } 1026 1027 if (MLX5_CAP_GEN(mdev, tag_matching) && 1028 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1029 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1030 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1031 } 1032 1033 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1034 props->cq_caps.max_cq_moderation_count = 1035 MLX5_MAX_CQ_COUNT; 1036 props->cq_caps.max_cq_moderation_period = 1037 MLX5_MAX_CQ_PERIOD; 1038 } 1039 1040 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1041 resp.response_length += sizeof(resp.cqe_comp_caps); 1042 1043 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1044 resp.cqe_comp_caps.max_num = 1045 MLX5_CAP_GEN(dev->mdev, 1046 cqe_compression_max_num); 1047 1048 resp.cqe_comp_caps.supported_format = 1049 MLX5_IB_CQE_RES_FORMAT_HASH | 1050 MLX5_IB_CQE_RES_FORMAT_CSUM; 1051 1052 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1053 resp.cqe_comp_caps.supported_format |= 1054 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1055 } 1056 } 1057 1058 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1059 raw_support) { 1060 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1061 MLX5_CAP_GEN(mdev, qos)) { 1062 resp.packet_pacing_caps.qp_rate_limit_max = 1063 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1064 resp.packet_pacing_caps.qp_rate_limit_min = 1065 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1066 resp.packet_pacing_caps.supported_qpts |= 1067 1 << IB_QPT_RAW_PACKET; 1068 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1069 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1070 resp.packet_pacing_caps.cap_flags |= 1071 MLX5_IB_PP_SUPPORT_BURST; 1072 } 1073 resp.response_length += sizeof(resp.packet_pacing_caps); 1074 } 1075 1076 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1077 uhw_outlen) { 1078 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1079 resp.mlx5_ib_support_multi_pkt_send_wqes = 1080 MLX5_IB_ALLOW_MPW; 1081 1082 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1083 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1084 MLX5_IB_SUPPORT_EMPW; 1085 1086 resp.response_length += 1087 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1088 } 1089 1090 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1091 resp.response_length += sizeof(resp.flags); 1092 1093 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1094 resp.flags |= 1095 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1096 1097 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1098 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1099 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1100 resp.flags |= 1101 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1102 1103 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1104 } 1105 1106 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1107 resp.response_length += sizeof(resp.sw_parsing_caps); 1108 if (MLX5_CAP_ETH(mdev, swp)) { 1109 resp.sw_parsing_caps.sw_parsing_offloads |= 1110 MLX5_IB_SW_PARSING; 1111 1112 if (MLX5_CAP_ETH(mdev, swp_csum)) 1113 resp.sw_parsing_caps.sw_parsing_offloads |= 1114 MLX5_IB_SW_PARSING_CSUM; 1115 1116 if (MLX5_CAP_ETH(mdev, swp_lso)) 1117 resp.sw_parsing_caps.sw_parsing_offloads |= 1118 MLX5_IB_SW_PARSING_LSO; 1119 1120 if (resp.sw_parsing_caps.sw_parsing_offloads) 1121 resp.sw_parsing_caps.supported_qpts = 1122 BIT(IB_QPT_RAW_PACKET); 1123 } 1124 } 1125 1126 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1127 raw_support) { 1128 resp.response_length += sizeof(resp.striding_rq_caps); 1129 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1130 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1131 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1132 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1133 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1134 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1135 resp.striding_rq_caps 1136 .min_single_wqe_log_num_of_strides = 1137 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1138 else 1139 resp.striding_rq_caps 1140 .min_single_wqe_log_num_of_strides = 1141 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1142 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1143 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1144 resp.striding_rq_caps.supported_qpts = 1145 BIT(IB_QPT_RAW_PACKET); 1146 } 1147 } 1148 1149 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1150 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1151 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1152 resp.tunnel_offloads_caps |= 1153 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1154 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1155 resp.tunnel_offloads_caps |= 1156 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1157 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1158 resp.tunnel_offloads_caps |= 1159 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1161 resp.tunnel_offloads_caps |= 1162 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1164 resp.tunnel_offloads_caps |= 1165 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1166 } 1167 1168 if (uhw_outlen) { 1169 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1170 1171 if (err) 1172 return err; 1173 } 1174 1175 return 0; 1176 } 1177 1178 enum mlx5_ib_width { 1179 MLX5_IB_WIDTH_1X = 1 << 0, 1180 MLX5_IB_WIDTH_2X = 1 << 1, 1181 MLX5_IB_WIDTH_4X = 1 << 2, 1182 MLX5_IB_WIDTH_8X = 1 << 3, 1183 MLX5_IB_WIDTH_12X = 1 << 4 1184 }; 1185 1186 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1187 u8 *ib_width) 1188 { 1189 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1190 1191 if (active_width & MLX5_IB_WIDTH_1X) 1192 *ib_width = IB_WIDTH_1X; 1193 else if (active_width & MLX5_IB_WIDTH_2X) 1194 *ib_width = IB_WIDTH_2X; 1195 else if (active_width & MLX5_IB_WIDTH_4X) 1196 *ib_width = IB_WIDTH_4X; 1197 else if (active_width & MLX5_IB_WIDTH_8X) 1198 *ib_width = IB_WIDTH_8X; 1199 else if (active_width & MLX5_IB_WIDTH_12X) 1200 *ib_width = IB_WIDTH_12X; 1201 else { 1202 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1203 (int)active_width); 1204 *ib_width = IB_WIDTH_4X; 1205 } 1206 1207 return; 1208 } 1209 1210 static int mlx5_mtu_to_ib_mtu(int mtu) 1211 { 1212 switch (mtu) { 1213 case 256: return 1; 1214 case 512: return 2; 1215 case 1024: return 3; 1216 case 2048: return 4; 1217 case 4096: return 5; 1218 default: 1219 pr_warn("invalid mtu\n"); 1220 return -1; 1221 } 1222 } 1223 1224 enum ib_max_vl_num { 1225 __IB_MAX_VL_0 = 1, 1226 __IB_MAX_VL_0_1 = 2, 1227 __IB_MAX_VL_0_3 = 3, 1228 __IB_MAX_VL_0_7 = 4, 1229 __IB_MAX_VL_0_14 = 5, 1230 }; 1231 1232 enum mlx5_vl_hw_cap { 1233 MLX5_VL_HW_0 = 1, 1234 MLX5_VL_HW_0_1 = 2, 1235 MLX5_VL_HW_0_2 = 3, 1236 MLX5_VL_HW_0_3 = 4, 1237 MLX5_VL_HW_0_4 = 5, 1238 MLX5_VL_HW_0_5 = 6, 1239 MLX5_VL_HW_0_6 = 7, 1240 MLX5_VL_HW_0_7 = 8, 1241 MLX5_VL_HW_0_14 = 15 1242 }; 1243 1244 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1245 u8 *max_vl_num) 1246 { 1247 switch (vl_hw_cap) { 1248 case MLX5_VL_HW_0: 1249 *max_vl_num = __IB_MAX_VL_0; 1250 break; 1251 case MLX5_VL_HW_0_1: 1252 *max_vl_num = __IB_MAX_VL_0_1; 1253 break; 1254 case MLX5_VL_HW_0_3: 1255 *max_vl_num = __IB_MAX_VL_0_3; 1256 break; 1257 case MLX5_VL_HW_0_7: 1258 *max_vl_num = __IB_MAX_VL_0_7; 1259 break; 1260 case MLX5_VL_HW_0_14: 1261 *max_vl_num = __IB_MAX_VL_0_14; 1262 break; 1263 1264 default: 1265 return -EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1272 struct ib_port_attr *props) 1273 { 1274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1275 struct mlx5_core_dev *mdev = dev->mdev; 1276 struct mlx5_hca_vport_context *rep; 1277 u16 max_mtu; 1278 u16 oper_mtu; 1279 int err; 1280 u8 ib_link_width_oper; 1281 u8 vl_hw_cap; 1282 1283 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1284 if (!rep) { 1285 err = -ENOMEM; 1286 goto out; 1287 } 1288 1289 /* props being zeroed by the caller, avoid zeroing it here */ 1290 1291 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1292 if (err) 1293 goto out; 1294 1295 props->lid = rep->lid; 1296 props->lmc = rep->lmc; 1297 props->sm_lid = rep->sm_lid; 1298 props->sm_sl = rep->sm_sl; 1299 props->state = rep->vport_state; 1300 props->phys_state = rep->port_physical_state; 1301 props->port_cap_flags = rep->cap_mask1; 1302 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1303 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1304 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1305 props->bad_pkey_cntr = rep->pkey_violation_counter; 1306 props->qkey_viol_cntr = rep->qkey_violation_counter; 1307 props->subnet_timeout = rep->subnet_timeout; 1308 props->init_type_reply = rep->init_type_reply; 1309 1310 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1311 props->port_cap_flags2 = rep->cap_mask2; 1312 1313 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1314 if (err) 1315 goto out; 1316 1317 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1318 1319 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1320 if (err) 1321 goto out; 1322 1323 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1324 1325 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1326 1327 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1328 1329 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1330 1331 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1332 if (err) 1333 goto out; 1334 1335 err = translate_max_vl_num(ibdev, vl_hw_cap, 1336 &props->max_vl_num); 1337 out: 1338 kfree(rep); 1339 return err; 1340 } 1341 1342 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1343 struct ib_port_attr *props) 1344 { 1345 unsigned int count; 1346 int ret; 1347 1348 switch (mlx5_get_vport_access_method(ibdev)) { 1349 case MLX5_VPORT_ACCESS_METHOD_MAD: 1350 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1351 break; 1352 1353 case MLX5_VPORT_ACCESS_METHOD_HCA: 1354 ret = mlx5_query_hca_port(ibdev, port, props); 1355 break; 1356 1357 case MLX5_VPORT_ACCESS_METHOD_NIC: 1358 ret = mlx5_query_port_roce(ibdev, port, props); 1359 break; 1360 1361 default: 1362 ret = -EINVAL; 1363 } 1364 1365 if (!ret && props) { 1366 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1367 struct mlx5_core_dev *mdev; 1368 bool put_mdev = true; 1369 1370 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1371 if (!mdev) { 1372 /* If the port isn't affiliated yet query the master. 1373 * The master and slave will have the same values. 1374 */ 1375 mdev = dev->mdev; 1376 port = 1; 1377 put_mdev = false; 1378 } 1379 count = mlx5_core_reserved_gids_count(mdev); 1380 if (put_mdev) 1381 mlx5_ib_put_native_port_mdev(dev, port); 1382 props->gid_tbl_len -= count; 1383 } 1384 return ret; 1385 } 1386 1387 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1388 struct ib_port_attr *props) 1389 { 1390 int ret; 1391 1392 /* Only link layer == ethernet is valid for representors 1393 * and we always use port 1 1394 */ 1395 ret = mlx5_query_port_roce(ibdev, port, props); 1396 if (ret || !props) 1397 return ret; 1398 1399 /* We don't support GIDS */ 1400 props->gid_tbl_len = 0; 1401 1402 return ret; 1403 } 1404 1405 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1406 union ib_gid *gid) 1407 { 1408 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1409 struct mlx5_core_dev *mdev = dev->mdev; 1410 1411 switch (mlx5_get_vport_access_method(ibdev)) { 1412 case MLX5_VPORT_ACCESS_METHOD_MAD: 1413 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1414 1415 case MLX5_VPORT_ACCESS_METHOD_HCA: 1416 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1417 1418 default: 1419 return -EINVAL; 1420 } 1421 1422 } 1423 1424 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1425 u16 index, u16 *pkey) 1426 { 1427 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1428 struct mlx5_core_dev *mdev; 1429 bool put_mdev = true; 1430 u8 mdev_port_num; 1431 int err; 1432 1433 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1434 if (!mdev) { 1435 /* The port isn't affiliated yet, get the PKey from the master 1436 * port. For RoCE the PKey tables will be the same. 1437 */ 1438 put_mdev = false; 1439 mdev = dev->mdev; 1440 mdev_port_num = 1; 1441 } 1442 1443 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1444 index, pkey); 1445 if (put_mdev) 1446 mlx5_ib_put_native_port_mdev(dev, port); 1447 1448 return err; 1449 } 1450 1451 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1452 u16 *pkey) 1453 { 1454 switch (mlx5_get_vport_access_method(ibdev)) { 1455 case MLX5_VPORT_ACCESS_METHOD_MAD: 1456 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1457 1458 case MLX5_VPORT_ACCESS_METHOD_HCA: 1459 case MLX5_VPORT_ACCESS_METHOD_NIC: 1460 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1461 default: 1462 return -EINVAL; 1463 } 1464 } 1465 1466 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1467 struct ib_device_modify *props) 1468 { 1469 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1470 struct mlx5_reg_node_desc in; 1471 struct mlx5_reg_node_desc out; 1472 int err; 1473 1474 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1475 return -EOPNOTSUPP; 1476 1477 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1478 return 0; 1479 1480 /* 1481 * If possible, pass node desc to FW, so it can generate 1482 * a 144 trap. If cmd fails, just ignore. 1483 */ 1484 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1485 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1486 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1487 if (err) 1488 return err; 1489 1490 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1491 1492 return err; 1493 } 1494 1495 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1496 u32 value) 1497 { 1498 struct mlx5_hca_vport_context ctx = {}; 1499 struct mlx5_core_dev *mdev; 1500 u8 mdev_port_num; 1501 int err; 1502 1503 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1504 if (!mdev) 1505 return -ENODEV; 1506 1507 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1508 if (err) 1509 goto out; 1510 1511 if (~ctx.cap_mask1_perm & mask) { 1512 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1513 mask, ctx.cap_mask1_perm); 1514 err = -EINVAL; 1515 goto out; 1516 } 1517 1518 ctx.cap_mask1 = value; 1519 ctx.cap_mask1_perm = mask; 1520 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1521 0, &ctx); 1522 1523 out: 1524 mlx5_ib_put_native_port_mdev(dev, port_num); 1525 1526 return err; 1527 } 1528 1529 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1530 struct ib_port_modify *props) 1531 { 1532 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1533 struct ib_port_attr attr; 1534 u32 tmp; 1535 int err; 1536 u32 change_mask; 1537 u32 value; 1538 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1539 IB_LINK_LAYER_INFINIBAND); 1540 1541 /* CM layer calls ib_modify_port() regardless of the link layer. For 1542 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1543 */ 1544 if (!is_ib) 1545 return 0; 1546 1547 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1548 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1549 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1550 return set_port_caps_atomic(dev, port, change_mask, value); 1551 } 1552 1553 mutex_lock(&dev->cap_mask_mutex); 1554 1555 err = ib_query_port(ibdev, port, &attr); 1556 if (err) 1557 goto out; 1558 1559 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1560 ~props->clr_port_cap_mask; 1561 1562 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1563 1564 out: 1565 mutex_unlock(&dev->cap_mask_mutex); 1566 return err; 1567 } 1568 1569 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1570 { 1571 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1572 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1573 } 1574 1575 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1576 { 1577 /* Large page with non 4k uar support might limit the dynamic size */ 1578 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1579 return MLX5_MIN_DYN_BFREGS; 1580 1581 return MLX5_MAX_DYN_BFREGS; 1582 } 1583 1584 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1585 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1586 struct mlx5_bfreg_info *bfregi) 1587 { 1588 int uars_per_sys_page; 1589 int bfregs_per_sys_page; 1590 int ref_bfregs = req->total_num_bfregs; 1591 1592 if (req->total_num_bfregs == 0) 1593 return -EINVAL; 1594 1595 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1596 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1597 1598 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1599 return -ENOMEM; 1600 1601 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1602 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1603 /* This holds the required static allocation asked by the user */ 1604 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1605 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1606 return -EINVAL; 1607 1608 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1609 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1610 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1611 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1612 1613 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1614 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1615 lib_uar_4k ? "yes" : "no", ref_bfregs, 1616 req->total_num_bfregs, bfregi->total_num_bfregs, 1617 bfregi->num_sys_pages); 1618 1619 return 0; 1620 } 1621 1622 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1623 { 1624 struct mlx5_bfreg_info *bfregi; 1625 int err; 1626 int i; 1627 1628 bfregi = &context->bfregi; 1629 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1630 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1631 if (err) 1632 goto error; 1633 1634 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1635 } 1636 1637 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1638 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1639 1640 return 0; 1641 1642 error: 1643 for (--i; i >= 0; i--) 1644 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1645 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1646 1647 return err; 1648 } 1649 1650 static void deallocate_uars(struct mlx5_ib_dev *dev, 1651 struct mlx5_ib_ucontext *context) 1652 { 1653 struct mlx5_bfreg_info *bfregi; 1654 int i; 1655 1656 bfregi = &context->bfregi; 1657 for (i = 0; i < bfregi->num_sys_pages; i++) 1658 if (i < bfregi->num_static_sys_pages || 1659 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1660 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1661 } 1662 1663 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1664 { 1665 int err = 0; 1666 1667 mutex_lock(&dev->lb.mutex); 1668 if (td) 1669 dev->lb.user_td++; 1670 if (qp) 1671 dev->lb.qps++; 1672 1673 if (dev->lb.user_td == 2 || 1674 dev->lb.qps == 1) { 1675 if (!dev->lb.enabled) { 1676 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1677 dev->lb.enabled = true; 1678 } 1679 } 1680 1681 mutex_unlock(&dev->lb.mutex); 1682 1683 return err; 1684 } 1685 1686 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1687 { 1688 mutex_lock(&dev->lb.mutex); 1689 if (td) 1690 dev->lb.user_td--; 1691 if (qp) 1692 dev->lb.qps--; 1693 1694 if (dev->lb.user_td == 1 && 1695 dev->lb.qps == 0) { 1696 if (dev->lb.enabled) { 1697 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1698 dev->lb.enabled = false; 1699 } 1700 } 1701 1702 mutex_unlock(&dev->lb.mutex); 1703 } 1704 1705 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1706 u16 uid) 1707 { 1708 int err; 1709 1710 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1711 return 0; 1712 1713 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1714 if (err) 1715 return err; 1716 1717 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1718 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1719 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1720 return err; 1721 1722 return mlx5_ib_enable_lb(dev, true, false); 1723 } 1724 1725 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1726 u16 uid) 1727 { 1728 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1729 return; 1730 1731 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1732 1733 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1734 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1735 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1736 return; 1737 1738 mlx5_ib_disable_lb(dev, true, false); 1739 } 1740 1741 static int set_ucontext_resp(struct ib_ucontext *uctx, 1742 struct mlx5_ib_alloc_ucontext_resp *resp) 1743 { 1744 struct ib_device *ibdev = uctx->device; 1745 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1746 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1747 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1748 int err; 1749 1750 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1751 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1752 &resp->dump_fill_mkey); 1753 if (err) 1754 return err; 1755 resp->comp_mask |= 1756 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1757 } 1758 1759 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1760 if (dev->wc_support) 1761 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1762 log_bf_reg_size); 1763 resp->cache_line_size = cache_line_size(); 1764 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1765 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1766 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1767 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1768 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1769 resp->cqe_version = context->cqe_version; 1770 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1771 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1772 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1773 MLX5_CAP_GEN(dev->mdev, 1774 num_of_uars_per_page) : 1; 1775 1776 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1777 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1778 if (mlx5_get_flow_namespace(dev->mdev, 1779 MLX5_FLOW_NAMESPACE_EGRESS)) 1780 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1781 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1782 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1783 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1784 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1785 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1786 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1787 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1788 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1789 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1790 } 1791 1792 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1793 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1794 resp->num_ports = dev->num_ports; 1795 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1796 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1797 1798 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1799 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1800 resp->eth_min_inline++; 1801 } 1802 1803 if (dev->mdev->clock_info) 1804 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1805 1806 /* 1807 * We don't want to expose information from the PCI bar that is located 1808 * after 4096 bytes, so if the arch only supports larger pages, let's 1809 * pretend we don't support reading the HCA's core clock. This is also 1810 * forced by mmap function. 1811 */ 1812 if (PAGE_SIZE <= 4096) { 1813 resp->comp_mask |= 1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1815 resp->hca_core_clock_offset = 1816 offsetof(struct mlx5_init_seg, 1817 internal_timer_h) % PAGE_SIZE; 1818 } 1819 1820 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1821 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1822 1823 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1824 return 0; 1825 } 1826 1827 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1828 struct ib_udata *udata) 1829 { 1830 struct ib_device *ibdev = uctx->device; 1831 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1832 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1833 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1834 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1835 struct mlx5_bfreg_info *bfregi; 1836 int ver; 1837 int err; 1838 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1839 max_cqe_version); 1840 bool lib_uar_4k; 1841 bool lib_uar_dyn; 1842 1843 if (!dev->ib_active) 1844 return -EAGAIN; 1845 1846 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1847 ver = 0; 1848 else if (udata->inlen >= min_req_v2) 1849 ver = 2; 1850 else 1851 return -EINVAL; 1852 1853 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1854 if (err) 1855 return err; 1856 1857 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1858 return -EOPNOTSUPP; 1859 1860 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1861 return -EOPNOTSUPP; 1862 1863 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1864 MLX5_NON_FP_BFREGS_PER_UAR); 1865 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1866 return -EINVAL; 1867 1868 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1869 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1870 bfregi = &context->bfregi; 1871 1872 if (lib_uar_dyn) { 1873 bfregi->lib_uar_dyn = lib_uar_dyn; 1874 goto uar_done; 1875 } 1876 1877 /* updates req->total_num_bfregs */ 1878 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1879 if (err) 1880 goto out_ctx; 1881 1882 mutex_init(&bfregi->lock); 1883 bfregi->lib_uar_4k = lib_uar_4k; 1884 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1885 GFP_KERNEL); 1886 if (!bfregi->count) { 1887 err = -ENOMEM; 1888 goto out_ctx; 1889 } 1890 1891 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1892 sizeof(*bfregi->sys_pages), 1893 GFP_KERNEL); 1894 if (!bfregi->sys_pages) { 1895 err = -ENOMEM; 1896 goto out_count; 1897 } 1898 1899 err = allocate_uars(dev, context); 1900 if (err) 1901 goto out_sys_pages; 1902 1903 uar_done: 1904 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1905 err = mlx5_ib_devx_create(dev, true); 1906 if (err < 0) 1907 goto out_uars; 1908 context->devx_uid = err; 1909 } 1910 1911 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1912 context->devx_uid); 1913 if (err) 1914 goto out_devx; 1915 1916 INIT_LIST_HEAD(&context->db_page_list); 1917 mutex_init(&context->db_page_mutex); 1918 1919 context->cqe_version = min_t(__u8, 1920 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1921 req.max_cqe_version); 1922 1923 err = set_ucontext_resp(uctx, &resp); 1924 if (err) 1925 goto out_mdev; 1926 1927 resp.response_length = min(udata->outlen, sizeof(resp)); 1928 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1929 if (err) 1930 goto out_mdev; 1931 1932 bfregi->ver = ver; 1933 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1934 context->lib_caps = req.lib_caps; 1935 print_lib_caps(dev, context->lib_caps); 1936 1937 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1938 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1939 1940 atomic_set(&context->tx_port_affinity, 1941 atomic_add_return( 1942 1, &dev->port[port].roce.tx_port_affinity)); 1943 } 1944 1945 return 0; 1946 1947 out_mdev: 1948 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1949 out_devx: 1950 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1951 mlx5_ib_devx_destroy(dev, context->devx_uid); 1952 1953 out_uars: 1954 deallocate_uars(dev, context); 1955 1956 out_sys_pages: 1957 kfree(bfregi->sys_pages); 1958 1959 out_count: 1960 kfree(bfregi->count); 1961 1962 out_ctx: 1963 return err; 1964 } 1965 1966 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1967 struct uverbs_attr_bundle *attrs) 1968 { 1969 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1970 int ret; 1971 1972 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1973 if (ret) 1974 return ret; 1975 1976 uctx_resp.response_length = 1977 min_t(size_t, 1978 uverbs_attr_get_len(attrs, 1979 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1980 sizeof(uctx_resp)); 1981 1982 ret = uverbs_copy_to_struct_or_zero(attrs, 1983 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1984 &uctx_resp, 1985 sizeof(uctx_resp)); 1986 return ret; 1987 } 1988 1989 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1990 { 1991 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1992 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1993 struct mlx5_bfreg_info *bfregi; 1994 1995 bfregi = &context->bfregi; 1996 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1997 1998 if (context->devx_uid) 1999 mlx5_ib_devx_destroy(dev, context->devx_uid); 2000 2001 deallocate_uars(dev, context); 2002 kfree(bfregi->sys_pages); 2003 kfree(bfregi->count); 2004 } 2005 2006 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2007 int uar_idx) 2008 { 2009 int fw_uars_per_page; 2010 2011 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2012 2013 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2014 } 2015 2016 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2017 int uar_idx) 2018 { 2019 unsigned int fw_uars_per_page; 2020 2021 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2022 MLX5_UARS_IN_PAGE : 1; 2023 2024 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2025 } 2026 2027 static int get_command(unsigned long offset) 2028 { 2029 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2030 } 2031 2032 static int get_arg(unsigned long offset) 2033 { 2034 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2035 } 2036 2037 static int get_index(unsigned long offset) 2038 { 2039 return get_arg(offset); 2040 } 2041 2042 /* Index resides in an extra byte to enable larger values than 255 */ 2043 static int get_extended_index(unsigned long offset) 2044 { 2045 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2046 } 2047 2048 2049 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2050 { 2051 } 2052 2053 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2054 { 2055 switch (cmd) { 2056 case MLX5_IB_MMAP_WC_PAGE: 2057 return "WC"; 2058 case MLX5_IB_MMAP_REGULAR_PAGE: 2059 return "best effort WC"; 2060 case MLX5_IB_MMAP_NC_PAGE: 2061 return "NC"; 2062 case MLX5_IB_MMAP_DEVICE_MEM: 2063 return "Device Memory"; 2064 default: 2065 return NULL; 2066 } 2067 } 2068 2069 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2070 struct vm_area_struct *vma, 2071 struct mlx5_ib_ucontext *context) 2072 { 2073 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2074 !(vma->vm_flags & VM_SHARED)) 2075 return -EINVAL; 2076 2077 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2078 return -EOPNOTSUPP; 2079 2080 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2081 return -EPERM; 2082 vma->vm_flags &= ~VM_MAYWRITE; 2083 2084 if (!dev->mdev->clock_info) 2085 return -EOPNOTSUPP; 2086 2087 return vm_insert_page(vma, vma->vm_start, 2088 virt_to_page(dev->mdev->clock_info)); 2089 } 2090 2091 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2092 { 2093 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2094 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2095 struct mlx5_var_table *var_table = &dev->var_table; 2096 struct mlx5_ib_dm *mdm; 2097 2098 switch (mentry->mmap_flag) { 2099 case MLX5_IB_MMAP_TYPE_MEMIC: 2100 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2101 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2102 mdm->size); 2103 kfree(mdm); 2104 break; 2105 case MLX5_IB_MMAP_TYPE_VAR: 2106 mutex_lock(&var_table->bitmap_lock); 2107 clear_bit(mentry->page_idx, var_table->bitmap); 2108 mutex_unlock(&var_table->bitmap_lock); 2109 kfree(mentry); 2110 break; 2111 case MLX5_IB_MMAP_TYPE_UAR_WC: 2112 case MLX5_IB_MMAP_TYPE_UAR_NC: 2113 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2114 kfree(mentry); 2115 break; 2116 default: 2117 WARN_ON(true); 2118 } 2119 } 2120 2121 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2122 struct vm_area_struct *vma, 2123 struct mlx5_ib_ucontext *context) 2124 { 2125 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2126 int err; 2127 unsigned long idx; 2128 phys_addr_t pfn; 2129 pgprot_t prot; 2130 u32 bfreg_dyn_idx = 0; 2131 u32 uar_index; 2132 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2133 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2134 bfregi->num_static_sys_pages; 2135 2136 if (bfregi->lib_uar_dyn) 2137 return -EINVAL; 2138 2139 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2140 return -EINVAL; 2141 2142 if (dyn_uar) 2143 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2144 else 2145 idx = get_index(vma->vm_pgoff); 2146 2147 if (idx >= max_valid_idx) { 2148 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2149 idx, max_valid_idx); 2150 return -EINVAL; 2151 } 2152 2153 switch (cmd) { 2154 case MLX5_IB_MMAP_WC_PAGE: 2155 case MLX5_IB_MMAP_ALLOC_WC: 2156 case MLX5_IB_MMAP_REGULAR_PAGE: 2157 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2158 prot = pgprot_writecombine(vma->vm_page_prot); 2159 break; 2160 case MLX5_IB_MMAP_NC_PAGE: 2161 prot = pgprot_noncached(vma->vm_page_prot); 2162 break; 2163 default: 2164 return -EINVAL; 2165 } 2166 2167 if (dyn_uar) { 2168 int uars_per_page; 2169 2170 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2171 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2172 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2173 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2174 bfreg_dyn_idx, bfregi->total_num_bfregs); 2175 return -EINVAL; 2176 } 2177 2178 mutex_lock(&bfregi->lock); 2179 /* Fail if uar already allocated, first bfreg index of each 2180 * page holds its count. 2181 */ 2182 if (bfregi->count[bfreg_dyn_idx]) { 2183 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2184 mutex_unlock(&bfregi->lock); 2185 return -EINVAL; 2186 } 2187 2188 bfregi->count[bfreg_dyn_idx]++; 2189 mutex_unlock(&bfregi->lock); 2190 2191 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2192 if (err) { 2193 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2194 goto free_bfreg; 2195 } 2196 } else { 2197 uar_index = bfregi->sys_pages[idx]; 2198 } 2199 2200 pfn = uar_index2pfn(dev, uar_index); 2201 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2202 2203 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2204 prot, NULL); 2205 if (err) { 2206 mlx5_ib_err(dev, 2207 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2208 err, mmap_cmd2str(cmd)); 2209 goto err; 2210 } 2211 2212 if (dyn_uar) 2213 bfregi->sys_pages[idx] = uar_index; 2214 return 0; 2215 2216 err: 2217 if (!dyn_uar) 2218 return err; 2219 2220 mlx5_cmd_free_uar(dev->mdev, idx); 2221 2222 free_bfreg: 2223 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2224 2225 return err; 2226 } 2227 2228 static int add_dm_mmap_entry(struct ib_ucontext *context, 2229 struct mlx5_ib_dm *mdm, 2230 u64 address) 2231 { 2232 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2233 mdm->mentry.address = address; 2234 return rdma_user_mmap_entry_insert_range( 2235 context, &mdm->mentry.rdma_entry, 2236 mdm->size, 2237 MLX5_IB_MMAP_DEVICE_MEM << 16, 2238 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2239 } 2240 2241 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2242 { 2243 unsigned long idx; 2244 u8 command; 2245 2246 command = get_command(vma->vm_pgoff); 2247 idx = get_extended_index(vma->vm_pgoff); 2248 2249 return (command << 16 | idx); 2250 } 2251 2252 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2253 struct vm_area_struct *vma, 2254 struct ib_ucontext *ucontext) 2255 { 2256 struct mlx5_user_mmap_entry *mentry; 2257 struct rdma_user_mmap_entry *entry; 2258 unsigned long pgoff; 2259 pgprot_t prot; 2260 phys_addr_t pfn; 2261 int ret; 2262 2263 pgoff = mlx5_vma_to_pgoff(vma); 2264 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2265 if (!entry) 2266 return -EINVAL; 2267 2268 mentry = to_mmmap(entry); 2269 pfn = (mentry->address >> PAGE_SHIFT); 2270 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2271 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2272 prot = pgprot_noncached(vma->vm_page_prot); 2273 else 2274 prot = pgprot_writecombine(vma->vm_page_prot); 2275 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2276 entry->npages * PAGE_SIZE, 2277 prot, 2278 entry); 2279 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2280 return ret; 2281 } 2282 2283 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2284 { 2285 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2286 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2287 2288 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2289 (index & 0xFF)) << PAGE_SHIFT; 2290 } 2291 2292 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2293 { 2294 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2295 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2296 unsigned long command; 2297 phys_addr_t pfn; 2298 2299 command = get_command(vma->vm_pgoff); 2300 switch (command) { 2301 case MLX5_IB_MMAP_WC_PAGE: 2302 case MLX5_IB_MMAP_ALLOC_WC: 2303 if (!dev->wc_support) 2304 return -EPERM; 2305 fallthrough; 2306 case MLX5_IB_MMAP_NC_PAGE: 2307 case MLX5_IB_MMAP_REGULAR_PAGE: 2308 return uar_mmap(dev, command, vma, context); 2309 2310 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2311 return -ENOSYS; 2312 2313 case MLX5_IB_MMAP_CORE_CLOCK: 2314 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2315 return -EINVAL; 2316 2317 if (vma->vm_flags & VM_WRITE) 2318 return -EPERM; 2319 vma->vm_flags &= ~VM_MAYWRITE; 2320 2321 /* Don't expose to user-space information it shouldn't have */ 2322 if (PAGE_SIZE > 4096) 2323 return -EOPNOTSUPP; 2324 2325 pfn = (dev->mdev->iseg_base + 2326 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2327 PAGE_SHIFT; 2328 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2329 PAGE_SIZE, 2330 pgprot_noncached(vma->vm_page_prot), 2331 NULL); 2332 case MLX5_IB_MMAP_CLOCK_INFO: 2333 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2334 2335 default: 2336 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2337 } 2338 2339 return 0; 2340 } 2341 2342 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2343 u32 type) 2344 { 2345 switch (type) { 2346 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2347 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2348 return -EOPNOTSUPP; 2349 break; 2350 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2351 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2352 if (!capable(CAP_SYS_RAWIO) || 2353 !capable(CAP_NET_RAW)) 2354 return -EPERM; 2355 2356 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2357 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner))) 2358 return -EOPNOTSUPP; 2359 break; 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2366 struct mlx5_ib_dm *dm, 2367 struct ib_dm_alloc_attr *attr, 2368 struct uverbs_attr_bundle *attrs) 2369 { 2370 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2371 u64 start_offset; 2372 u16 page_idx; 2373 int err; 2374 u64 address; 2375 2376 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2377 2378 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2379 dm->size, attr->alignment); 2380 if (err) 2381 return err; 2382 2383 address = dm->dev_addr & PAGE_MASK; 2384 err = add_dm_mmap_entry(ctx, dm, address); 2385 if (err) 2386 goto err_dealloc; 2387 2388 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2389 err = uverbs_copy_to(attrs, 2390 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2391 &page_idx, 2392 sizeof(page_idx)); 2393 if (err) 2394 goto err_copy; 2395 2396 start_offset = dm->dev_addr & ~PAGE_MASK; 2397 err = uverbs_copy_to(attrs, 2398 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2399 &start_offset, sizeof(start_offset)); 2400 if (err) 2401 goto err_copy; 2402 2403 return 0; 2404 2405 err_copy: 2406 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2407 err_dealloc: 2408 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2409 2410 return err; 2411 } 2412 2413 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2414 struct mlx5_ib_dm *dm, 2415 struct ib_dm_alloc_attr *attr, 2416 struct uverbs_attr_bundle *attrs, 2417 int type) 2418 { 2419 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2420 u64 act_size; 2421 int err; 2422 2423 /* Allocation size must a multiple of the basic block size 2424 * and a power of 2. 2425 */ 2426 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2427 act_size = roundup_pow_of_two(act_size); 2428 2429 dm->size = act_size; 2430 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2431 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2432 &dm->icm_dm.obj_id); 2433 if (err) 2434 return err; 2435 2436 err = uverbs_copy_to(attrs, 2437 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2438 &dm->dev_addr, sizeof(dm->dev_addr)); 2439 if (err) 2440 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2441 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2442 dm->icm_dm.obj_id); 2443 2444 return err; 2445 } 2446 2447 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2448 struct ib_ucontext *context, 2449 struct ib_dm_alloc_attr *attr, 2450 struct uverbs_attr_bundle *attrs) 2451 { 2452 struct mlx5_ib_dm *dm; 2453 enum mlx5_ib_uapi_dm_type type; 2454 int err; 2455 2456 err = uverbs_get_const_default(&type, attrs, 2457 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2458 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2459 if (err) 2460 return ERR_PTR(err); 2461 2462 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2463 type, attr->length, attr->alignment); 2464 2465 err = check_dm_type_support(to_mdev(ibdev), type); 2466 if (err) 2467 return ERR_PTR(err); 2468 2469 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2470 if (!dm) 2471 return ERR_PTR(-ENOMEM); 2472 2473 dm->type = type; 2474 2475 switch (type) { 2476 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2477 err = handle_alloc_dm_memic(context, dm, 2478 attr, 2479 attrs); 2480 break; 2481 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2482 err = handle_alloc_dm_sw_icm(context, dm, 2483 attr, attrs, 2484 MLX5_SW_ICM_TYPE_STEERING); 2485 break; 2486 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2487 err = handle_alloc_dm_sw_icm(context, dm, 2488 attr, attrs, 2489 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2490 break; 2491 default: 2492 err = -EOPNOTSUPP; 2493 } 2494 2495 if (err) 2496 goto err_free; 2497 2498 return &dm->ibdm; 2499 2500 err_free: 2501 kfree(dm); 2502 return ERR_PTR(err); 2503 } 2504 2505 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2506 { 2507 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2508 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2509 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2510 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2511 int ret; 2512 2513 switch (dm->type) { 2514 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2515 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2516 return 0; 2517 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2518 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2519 dm->size, ctx->devx_uid, dm->dev_addr, 2520 dm->icm_dm.obj_id); 2521 if (ret) 2522 return ret; 2523 break; 2524 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2525 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2526 dm->size, ctx->devx_uid, dm->dev_addr, 2527 dm->icm_dm.obj_id); 2528 if (ret) 2529 return ret; 2530 break; 2531 default: 2532 return -EOPNOTSUPP; 2533 } 2534 2535 kfree(dm); 2536 2537 return 0; 2538 } 2539 2540 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2541 { 2542 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2543 struct ib_device *ibdev = ibpd->device; 2544 struct mlx5_ib_alloc_pd_resp resp; 2545 int err; 2546 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2547 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2548 u16 uid = 0; 2549 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2550 udata, struct mlx5_ib_ucontext, ibucontext); 2551 2552 uid = context ? context->devx_uid : 0; 2553 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2554 MLX5_SET(alloc_pd_in, in, uid, uid); 2555 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2556 if (err) 2557 return err; 2558 2559 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2560 pd->uid = uid; 2561 if (udata) { 2562 resp.pdn = pd->pdn; 2563 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2564 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2565 return -EFAULT; 2566 } 2567 } 2568 2569 return 0; 2570 } 2571 2572 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2573 { 2574 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2575 struct mlx5_ib_pd *mpd = to_mpd(pd); 2576 2577 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2578 } 2579 2580 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2581 { 2582 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2583 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2584 int err; 2585 u16 uid; 2586 2587 uid = ibqp->pd ? 2588 to_mpd(ibqp->pd)->uid : 0; 2589 2590 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2591 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2592 return -EOPNOTSUPP; 2593 } 2594 2595 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2596 if (err) 2597 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2598 ibqp->qp_num, gid->raw); 2599 2600 return err; 2601 } 2602 2603 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2604 { 2605 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2606 int err; 2607 u16 uid; 2608 2609 uid = ibqp->pd ? 2610 to_mpd(ibqp->pd)->uid : 0; 2611 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2612 if (err) 2613 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2614 ibqp->qp_num, gid->raw); 2615 2616 return err; 2617 } 2618 2619 static int init_node_data(struct mlx5_ib_dev *dev) 2620 { 2621 int err; 2622 2623 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2624 if (err) 2625 return err; 2626 2627 dev->mdev->rev_id = dev->mdev->pdev->revision; 2628 2629 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2630 } 2631 2632 static ssize_t fw_pages_show(struct device *device, 2633 struct device_attribute *attr, char *buf) 2634 { 2635 struct mlx5_ib_dev *dev = 2636 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2637 2638 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2639 } 2640 static DEVICE_ATTR_RO(fw_pages); 2641 2642 static ssize_t reg_pages_show(struct device *device, 2643 struct device_attribute *attr, char *buf) 2644 { 2645 struct mlx5_ib_dev *dev = 2646 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2647 2648 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2649 } 2650 static DEVICE_ATTR_RO(reg_pages); 2651 2652 static ssize_t hca_type_show(struct device *device, 2653 struct device_attribute *attr, char *buf) 2654 { 2655 struct mlx5_ib_dev *dev = 2656 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2657 2658 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2659 } 2660 static DEVICE_ATTR_RO(hca_type); 2661 2662 static ssize_t hw_rev_show(struct device *device, 2663 struct device_attribute *attr, char *buf) 2664 { 2665 struct mlx5_ib_dev *dev = 2666 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2667 2668 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2669 } 2670 static DEVICE_ATTR_RO(hw_rev); 2671 2672 static ssize_t board_id_show(struct device *device, 2673 struct device_attribute *attr, char *buf) 2674 { 2675 struct mlx5_ib_dev *dev = 2676 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2677 2678 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2679 dev->mdev->board_id); 2680 } 2681 static DEVICE_ATTR_RO(board_id); 2682 2683 static struct attribute *mlx5_class_attributes[] = { 2684 &dev_attr_hw_rev.attr, 2685 &dev_attr_hca_type.attr, 2686 &dev_attr_board_id.attr, 2687 &dev_attr_fw_pages.attr, 2688 &dev_attr_reg_pages.attr, 2689 NULL, 2690 }; 2691 2692 static const struct attribute_group mlx5_attr_group = { 2693 .attrs = mlx5_class_attributes, 2694 }; 2695 2696 static void pkey_change_handler(struct work_struct *work) 2697 { 2698 struct mlx5_ib_port_resources *ports = 2699 container_of(work, struct mlx5_ib_port_resources, 2700 pkey_change_work); 2701 2702 mutex_lock(&ports->devr->mutex); 2703 mlx5_ib_gsi_pkey_change(ports->gsi); 2704 mutex_unlock(&ports->devr->mutex); 2705 } 2706 2707 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2708 { 2709 struct mlx5_ib_qp *mqp; 2710 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2711 struct mlx5_core_cq *mcq; 2712 struct list_head cq_armed_list; 2713 unsigned long flags_qp; 2714 unsigned long flags_cq; 2715 unsigned long flags; 2716 2717 INIT_LIST_HEAD(&cq_armed_list); 2718 2719 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2720 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2721 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2722 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2723 if (mqp->sq.tail != mqp->sq.head) { 2724 send_mcq = to_mcq(mqp->ibqp.send_cq); 2725 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2726 if (send_mcq->mcq.comp && 2727 mqp->ibqp.send_cq->comp_handler) { 2728 if (!send_mcq->mcq.reset_notify_added) { 2729 send_mcq->mcq.reset_notify_added = 1; 2730 list_add_tail(&send_mcq->mcq.reset_notify, 2731 &cq_armed_list); 2732 } 2733 } 2734 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2735 } 2736 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2737 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2738 /* no handling is needed for SRQ */ 2739 if (!mqp->ibqp.srq) { 2740 if (mqp->rq.tail != mqp->rq.head) { 2741 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2742 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2743 if (recv_mcq->mcq.comp && 2744 mqp->ibqp.recv_cq->comp_handler) { 2745 if (!recv_mcq->mcq.reset_notify_added) { 2746 recv_mcq->mcq.reset_notify_added = 1; 2747 list_add_tail(&recv_mcq->mcq.reset_notify, 2748 &cq_armed_list); 2749 } 2750 } 2751 spin_unlock_irqrestore(&recv_mcq->lock, 2752 flags_cq); 2753 } 2754 } 2755 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2756 } 2757 /*At that point all inflight post send were put to be executed as of we 2758 * lock/unlock above locks Now need to arm all involved CQs. 2759 */ 2760 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2761 mcq->comp(mcq, NULL); 2762 } 2763 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2764 } 2765 2766 static void delay_drop_handler(struct work_struct *work) 2767 { 2768 int err; 2769 struct mlx5_ib_delay_drop *delay_drop = 2770 container_of(work, struct mlx5_ib_delay_drop, 2771 delay_drop_work); 2772 2773 atomic_inc(&delay_drop->events_cnt); 2774 2775 mutex_lock(&delay_drop->lock); 2776 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2777 if (err) { 2778 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2779 delay_drop->timeout); 2780 delay_drop->activate = false; 2781 } 2782 mutex_unlock(&delay_drop->lock); 2783 } 2784 2785 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2786 struct ib_event *ibev) 2787 { 2788 u8 port = (eqe->data.port.port >> 4) & 0xf; 2789 2790 switch (eqe->sub_type) { 2791 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2792 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2793 IB_LINK_LAYER_ETHERNET) 2794 schedule_work(&ibdev->delay_drop.delay_drop_work); 2795 break; 2796 default: /* do nothing */ 2797 return; 2798 } 2799 } 2800 2801 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2802 struct ib_event *ibev) 2803 { 2804 u8 port = (eqe->data.port.port >> 4) & 0xf; 2805 2806 ibev->element.port_num = port; 2807 2808 switch (eqe->sub_type) { 2809 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2810 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2811 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2812 /* In RoCE, port up/down events are handled in 2813 * mlx5_netdev_event(). 2814 */ 2815 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2816 IB_LINK_LAYER_ETHERNET) 2817 return -EINVAL; 2818 2819 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2820 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2821 break; 2822 2823 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2824 ibev->event = IB_EVENT_LID_CHANGE; 2825 break; 2826 2827 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2828 ibev->event = IB_EVENT_PKEY_CHANGE; 2829 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2830 break; 2831 2832 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2833 ibev->event = IB_EVENT_GID_CHANGE; 2834 break; 2835 2836 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2837 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2838 break; 2839 default: 2840 return -EINVAL; 2841 } 2842 2843 return 0; 2844 } 2845 2846 static void mlx5_ib_handle_event(struct work_struct *_work) 2847 { 2848 struct mlx5_ib_event_work *work = 2849 container_of(_work, struct mlx5_ib_event_work, work); 2850 struct mlx5_ib_dev *ibdev; 2851 struct ib_event ibev; 2852 bool fatal = false; 2853 2854 if (work->is_slave) { 2855 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2856 if (!ibdev) 2857 goto out; 2858 } else { 2859 ibdev = work->dev; 2860 } 2861 2862 switch (work->event) { 2863 case MLX5_DEV_EVENT_SYS_ERROR: 2864 ibev.event = IB_EVENT_DEVICE_FATAL; 2865 mlx5_ib_handle_internal_error(ibdev); 2866 ibev.element.port_num = (u8)(unsigned long)work->param; 2867 fatal = true; 2868 break; 2869 case MLX5_EVENT_TYPE_PORT_CHANGE: 2870 if (handle_port_change(ibdev, work->param, &ibev)) 2871 goto out; 2872 break; 2873 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2874 handle_general_event(ibdev, work->param, &ibev); 2875 /* fall through */ 2876 default: 2877 goto out; 2878 } 2879 2880 ibev.device = &ibdev->ib_dev; 2881 2882 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2883 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2884 goto out; 2885 } 2886 2887 if (ibdev->ib_active) 2888 ib_dispatch_event(&ibev); 2889 2890 if (fatal) 2891 ibdev->ib_active = false; 2892 out: 2893 kfree(work); 2894 } 2895 2896 static int mlx5_ib_event(struct notifier_block *nb, 2897 unsigned long event, void *param) 2898 { 2899 struct mlx5_ib_event_work *work; 2900 2901 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2902 if (!work) 2903 return NOTIFY_DONE; 2904 2905 INIT_WORK(&work->work, mlx5_ib_handle_event); 2906 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2907 work->is_slave = false; 2908 work->param = param; 2909 work->event = event; 2910 2911 queue_work(mlx5_ib_event_wq, &work->work); 2912 2913 return NOTIFY_OK; 2914 } 2915 2916 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2917 unsigned long event, void *param) 2918 { 2919 struct mlx5_ib_event_work *work; 2920 2921 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2922 if (!work) 2923 return NOTIFY_DONE; 2924 2925 INIT_WORK(&work->work, mlx5_ib_handle_event); 2926 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2927 work->is_slave = true; 2928 work->param = param; 2929 work->event = event; 2930 queue_work(mlx5_ib_event_wq, &work->work); 2931 2932 return NOTIFY_OK; 2933 } 2934 2935 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2936 { 2937 struct mlx5_hca_vport_context vport_ctx; 2938 int err; 2939 int port; 2940 2941 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) { 2942 dev->mdev->port_caps[port - 1].has_smi = false; 2943 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2944 MLX5_CAP_PORT_TYPE_IB) { 2945 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2946 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2947 port, 0, 2948 &vport_ctx); 2949 if (err) { 2950 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2951 port, err); 2952 return err; 2953 } 2954 dev->mdev->port_caps[port - 1].has_smi = 2955 vport_ctx.has_smi; 2956 } else { 2957 dev->mdev->port_caps[port - 1].has_smi = true; 2958 } 2959 } 2960 } 2961 return 0; 2962 } 2963 2964 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2965 { 2966 int port; 2967 2968 for (port = 1; port <= dev->num_ports; port++) 2969 mlx5_query_ext_port_caps(dev, port); 2970 } 2971 2972 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 2973 { 2974 struct ib_device_attr *dprops = NULL; 2975 struct ib_port_attr *pprops = NULL; 2976 int err = -ENOMEM; 2977 2978 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL); 2979 if (!pprops) 2980 goto out; 2981 2982 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2983 if (!dprops) 2984 goto out; 2985 2986 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL); 2987 if (err) { 2988 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2989 goto out; 2990 } 2991 2992 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2993 if (err) { 2994 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2995 port, err); 2996 goto out; 2997 } 2998 2999 dev->mdev->port_caps[port - 1].pkey_table_len = 3000 dprops->max_pkeys; 3001 dev->mdev->port_caps[port - 1].gid_table_len = 3002 pprops->gid_tbl_len; 3003 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3004 port, dprops->max_pkeys, pprops->gid_tbl_len); 3005 3006 out: 3007 kfree(pprops); 3008 kfree(dprops); 3009 3010 return err; 3011 } 3012 3013 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3014 { 3015 /* For representors use port 1, is this is the only native 3016 * port 3017 */ 3018 if (dev->is_rep) 3019 return __get_port_caps(dev, 1); 3020 return __get_port_caps(dev, port); 3021 } 3022 3023 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3024 { 3025 switch (umr_fence_cap) { 3026 case MLX5_CAP_UMR_FENCE_NONE: 3027 return MLX5_FENCE_MODE_NONE; 3028 case MLX5_CAP_UMR_FENCE_SMALL: 3029 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3030 default: 3031 return MLX5_FENCE_MODE_STRONG_ORDERING; 3032 } 3033 } 3034 3035 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3036 { 3037 struct mlx5_ib_resources *devr = &dev->devr; 3038 struct ib_srq_init_attr attr; 3039 struct ib_device *ibdev; 3040 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3041 int port; 3042 int ret = 0; 3043 3044 ibdev = &dev->ib_dev; 3045 3046 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3047 return -EOPNOTSUPP; 3048 3049 mutex_init(&devr->mutex); 3050 3051 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 3052 if (!devr->p0) 3053 return -ENOMEM; 3054 3055 devr->p0->device = ibdev; 3056 devr->p0->uobject = NULL; 3057 atomic_set(&devr->p0->usecnt, 0); 3058 3059 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3060 if (ret) 3061 goto error0; 3062 3063 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3064 if (!devr->c0) { 3065 ret = -ENOMEM; 3066 goto error1; 3067 } 3068 3069 devr->c0->device = &dev->ib_dev; 3070 atomic_set(&devr->c0->usecnt, 0); 3071 3072 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3073 if (ret) 3074 goto err_create_cq; 3075 3076 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3077 if (ret) 3078 goto error2; 3079 3080 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3081 if (ret) 3082 goto error3; 3083 3084 memset(&attr, 0, sizeof(attr)); 3085 attr.attr.max_sge = 1; 3086 attr.attr.max_wr = 1; 3087 attr.srq_type = IB_SRQT_XRC; 3088 attr.ext.cq = devr->c0; 3089 3090 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3091 if (!devr->s0) { 3092 ret = -ENOMEM; 3093 goto error4; 3094 } 3095 3096 devr->s0->device = &dev->ib_dev; 3097 devr->s0->pd = devr->p0; 3098 devr->s0->srq_type = IB_SRQT_XRC; 3099 devr->s0->ext.cq = devr->c0; 3100 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3101 if (ret) 3102 goto err_create; 3103 3104 atomic_inc(&devr->s0->ext.cq->usecnt); 3105 atomic_inc(&devr->p0->usecnt); 3106 atomic_set(&devr->s0->usecnt, 0); 3107 3108 memset(&attr, 0, sizeof(attr)); 3109 attr.attr.max_sge = 1; 3110 attr.attr.max_wr = 1; 3111 attr.srq_type = IB_SRQT_BASIC; 3112 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3113 if (!devr->s1) { 3114 ret = -ENOMEM; 3115 goto error5; 3116 } 3117 3118 devr->s1->device = &dev->ib_dev; 3119 devr->s1->pd = devr->p0; 3120 devr->s1->srq_type = IB_SRQT_BASIC; 3121 devr->s1->ext.cq = devr->c0; 3122 3123 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3124 if (ret) 3125 goto error6; 3126 3127 atomic_inc(&devr->p0->usecnt); 3128 atomic_set(&devr->s1->usecnt, 0); 3129 3130 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3131 INIT_WORK(&devr->ports[port].pkey_change_work, 3132 pkey_change_handler); 3133 devr->ports[port].devr = devr; 3134 } 3135 3136 return 0; 3137 3138 error6: 3139 kfree(devr->s1); 3140 error5: 3141 mlx5_ib_destroy_srq(devr->s0, NULL); 3142 err_create: 3143 kfree(devr->s0); 3144 error4: 3145 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3146 error3: 3147 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3148 error2: 3149 mlx5_ib_destroy_cq(devr->c0, NULL); 3150 err_create_cq: 3151 kfree(devr->c0); 3152 error1: 3153 mlx5_ib_dealloc_pd(devr->p0, NULL); 3154 error0: 3155 kfree(devr->p0); 3156 return ret; 3157 } 3158 3159 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3160 { 3161 struct mlx5_ib_resources *devr = &dev->devr; 3162 int port; 3163 3164 mlx5_ib_destroy_srq(devr->s1, NULL); 3165 kfree(devr->s1); 3166 mlx5_ib_destroy_srq(devr->s0, NULL); 3167 kfree(devr->s0); 3168 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3169 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3170 mlx5_ib_destroy_cq(devr->c0, NULL); 3171 kfree(devr->c0); 3172 mlx5_ib_dealloc_pd(devr->p0, NULL); 3173 kfree(devr->p0); 3174 3175 /* Make sure no change P_Key work items are still executing */ 3176 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3177 cancel_work_sync(&devr->ports[port].pkey_change_work); 3178 } 3179 3180 static u32 get_core_cap_flags(struct ib_device *ibdev, 3181 struct mlx5_hca_vport_context *rep) 3182 { 3183 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3184 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3185 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3186 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3187 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3188 u32 ret = 0; 3189 3190 if (rep->grh_required) 3191 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3192 3193 if (ll == IB_LINK_LAYER_INFINIBAND) 3194 return ret | RDMA_CORE_PORT_IBA_IB; 3195 3196 if (raw_support) 3197 ret |= RDMA_CORE_PORT_RAW_PACKET; 3198 3199 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3200 return ret; 3201 3202 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3203 return ret; 3204 3205 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3206 ret |= RDMA_CORE_PORT_IBA_ROCE; 3207 3208 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3209 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3210 3211 return ret; 3212 } 3213 3214 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3215 struct ib_port_immutable *immutable) 3216 { 3217 struct ib_port_attr attr; 3218 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3219 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3220 struct mlx5_hca_vport_context rep = {0}; 3221 int err; 3222 3223 err = ib_query_port(ibdev, port_num, &attr); 3224 if (err) 3225 return err; 3226 3227 if (ll == IB_LINK_LAYER_INFINIBAND) { 3228 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3229 &rep); 3230 if (err) 3231 return err; 3232 } 3233 3234 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3235 immutable->gid_tbl_len = attr.gid_tbl_len; 3236 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3237 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3238 3239 return 0; 3240 } 3241 3242 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3243 struct ib_port_immutable *immutable) 3244 { 3245 struct ib_port_attr attr; 3246 int err; 3247 3248 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3249 3250 err = ib_query_port(ibdev, port_num, &attr); 3251 if (err) 3252 return err; 3253 3254 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3255 immutable->gid_tbl_len = attr.gid_tbl_len; 3256 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3257 3258 return 0; 3259 } 3260 3261 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3262 { 3263 struct mlx5_ib_dev *dev = 3264 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3265 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3266 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3267 fw_rev_sub(dev->mdev)); 3268 } 3269 3270 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3271 { 3272 struct mlx5_core_dev *mdev = dev->mdev; 3273 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3274 MLX5_FLOW_NAMESPACE_LAG); 3275 struct mlx5_flow_table *ft; 3276 int err; 3277 3278 if (!ns || !mlx5_lag_is_roce(mdev)) 3279 return 0; 3280 3281 err = mlx5_cmd_create_vport_lag(mdev); 3282 if (err) 3283 return err; 3284 3285 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3286 if (IS_ERR(ft)) { 3287 err = PTR_ERR(ft); 3288 goto err_destroy_vport_lag; 3289 } 3290 3291 dev->flow_db->lag_demux_ft = ft; 3292 dev->lag_active = true; 3293 return 0; 3294 3295 err_destroy_vport_lag: 3296 mlx5_cmd_destroy_vport_lag(mdev); 3297 return err; 3298 } 3299 3300 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3301 { 3302 struct mlx5_core_dev *mdev = dev->mdev; 3303 3304 if (dev->lag_active) { 3305 dev->lag_active = false; 3306 3307 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3308 dev->flow_db->lag_demux_ft = NULL; 3309 3310 mlx5_cmd_destroy_vport_lag(mdev); 3311 } 3312 } 3313 3314 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3315 { 3316 int err; 3317 3318 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3319 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3320 if (err) { 3321 dev->port[port_num].roce.nb.notifier_call = NULL; 3322 return err; 3323 } 3324 3325 return 0; 3326 } 3327 3328 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3329 { 3330 if (dev->port[port_num].roce.nb.notifier_call) { 3331 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3332 dev->port[port_num].roce.nb.notifier_call = NULL; 3333 } 3334 } 3335 3336 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3337 { 3338 int err; 3339 3340 err = mlx5_nic_vport_enable_roce(dev->mdev); 3341 if (err) 3342 return err; 3343 3344 err = mlx5_eth_lag_init(dev); 3345 if (err) 3346 goto err_disable_roce; 3347 3348 return 0; 3349 3350 err_disable_roce: 3351 mlx5_nic_vport_disable_roce(dev->mdev); 3352 3353 return err; 3354 } 3355 3356 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3357 { 3358 mlx5_eth_lag_cleanup(dev); 3359 mlx5_nic_vport_disable_roce(dev->mdev); 3360 } 3361 3362 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3363 enum rdma_netdev_t type, 3364 struct rdma_netdev_alloc_params *params) 3365 { 3366 if (type != RDMA_NETDEV_IPOIB) 3367 return -EOPNOTSUPP; 3368 3369 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3370 } 3371 3372 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3373 size_t count, loff_t *pos) 3374 { 3375 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3376 char lbuf[20]; 3377 int len; 3378 3379 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3380 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3381 } 3382 3383 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3384 size_t count, loff_t *pos) 3385 { 3386 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3387 u32 timeout; 3388 u32 var; 3389 3390 if (kstrtouint_from_user(buf, count, 0, &var)) 3391 return -EFAULT; 3392 3393 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3394 1000); 3395 if (timeout != var) 3396 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3397 timeout); 3398 3399 delay_drop->timeout = timeout; 3400 3401 return count; 3402 } 3403 3404 static const struct file_operations fops_delay_drop_timeout = { 3405 .owner = THIS_MODULE, 3406 .open = simple_open, 3407 .write = delay_drop_timeout_write, 3408 .read = delay_drop_timeout_read, 3409 }; 3410 3411 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3412 struct mlx5_ib_multiport_info *mpi) 3413 { 3414 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3415 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3416 int comps; 3417 int err; 3418 int i; 3419 3420 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3421 3422 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3423 3424 spin_lock(&port->mp.mpi_lock); 3425 if (!mpi->ibdev) { 3426 spin_unlock(&port->mp.mpi_lock); 3427 return; 3428 } 3429 3430 mpi->ibdev = NULL; 3431 3432 spin_unlock(&port->mp.mpi_lock); 3433 if (mpi->mdev_events.notifier_call) 3434 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3435 mpi->mdev_events.notifier_call = NULL; 3436 mlx5_remove_netdev_notifier(ibdev, port_num); 3437 spin_lock(&port->mp.mpi_lock); 3438 3439 comps = mpi->mdev_refcnt; 3440 if (comps) { 3441 mpi->unaffiliate = true; 3442 init_completion(&mpi->unref_comp); 3443 spin_unlock(&port->mp.mpi_lock); 3444 3445 for (i = 0; i < comps; i++) 3446 wait_for_completion(&mpi->unref_comp); 3447 3448 spin_lock(&port->mp.mpi_lock); 3449 mpi->unaffiliate = false; 3450 } 3451 3452 port->mp.mpi = NULL; 3453 3454 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3455 3456 spin_unlock(&port->mp.mpi_lock); 3457 3458 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3459 3460 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3461 /* Log an error, still needed to cleanup the pointers and add 3462 * it back to the list. 3463 */ 3464 if (err) 3465 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3466 port_num + 1); 3467 3468 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3469 } 3470 3471 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3472 struct mlx5_ib_multiport_info *mpi) 3473 { 3474 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3475 int err; 3476 3477 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3478 3479 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3480 if (ibdev->port[port_num].mp.mpi) { 3481 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3482 port_num + 1); 3483 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3484 return false; 3485 } 3486 3487 ibdev->port[port_num].mp.mpi = mpi; 3488 mpi->ibdev = ibdev; 3489 mpi->mdev_events.notifier_call = NULL; 3490 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3491 3492 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3493 if (err) 3494 goto unbind; 3495 3496 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 3497 if (err) 3498 goto unbind; 3499 3500 err = mlx5_add_netdev_notifier(ibdev, port_num); 3501 if (err) { 3502 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3503 port_num + 1); 3504 goto unbind; 3505 } 3506 3507 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3508 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3509 3510 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3511 3512 return true; 3513 3514 unbind: 3515 mlx5_ib_unbind_slave_port(ibdev, mpi); 3516 return false; 3517 } 3518 3519 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3520 { 3521 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3522 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3523 port_num + 1); 3524 struct mlx5_ib_multiport_info *mpi; 3525 int err; 3526 int i; 3527 3528 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3529 return 0; 3530 3531 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3532 &dev->sys_image_guid); 3533 if (err) 3534 return err; 3535 3536 err = mlx5_nic_vport_enable_roce(dev->mdev); 3537 if (err) 3538 return err; 3539 3540 mutex_lock(&mlx5_ib_multiport_mutex); 3541 for (i = 0; i < dev->num_ports; i++) { 3542 bool bound = false; 3543 3544 /* build a stub multiport info struct for the native port. */ 3545 if (i == port_num) { 3546 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3547 if (!mpi) { 3548 mutex_unlock(&mlx5_ib_multiport_mutex); 3549 mlx5_nic_vport_disable_roce(dev->mdev); 3550 return -ENOMEM; 3551 } 3552 3553 mpi->is_master = true; 3554 mpi->mdev = dev->mdev; 3555 mpi->sys_image_guid = dev->sys_image_guid; 3556 dev->port[i].mp.mpi = mpi; 3557 mpi->ibdev = dev; 3558 mpi = NULL; 3559 continue; 3560 } 3561 3562 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3563 list) { 3564 if (dev->sys_image_guid == mpi->sys_image_guid && 3565 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3566 bound = mlx5_ib_bind_slave_port(dev, mpi); 3567 } 3568 3569 if (bound) { 3570 dev_dbg(mpi->mdev->device, 3571 "removing port from unaffiliated list.\n"); 3572 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3573 list_del(&mpi->list); 3574 break; 3575 } 3576 } 3577 if (!bound) { 3578 get_port_caps(dev, i + 1); 3579 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3580 i + 1); 3581 } 3582 } 3583 3584 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3585 mutex_unlock(&mlx5_ib_multiport_mutex); 3586 return err; 3587 } 3588 3589 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3590 { 3591 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3592 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3593 port_num + 1); 3594 int i; 3595 3596 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3597 return; 3598 3599 mutex_lock(&mlx5_ib_multiport_mutex); 3600 for (i = 0; i < dev->num_ports; i++) { 3601 if (dev->port[i].mp.mpi) { 3602 /* Destroy the native port stub */ 3603 if (i == port_num) { 3604 kfree(dev->port[i].mp.mpi); 3605 dev->port[i].mp.mpi = NULL; 3606 } else { 3607 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3608 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3609 } 3610 } 3611 } 3612 3613 mlx5_ib_dbg(dev, "removing from devlist\n"); 3614 list_del(&dev->ib_dev_list); 3615 mutex_unlock(&mlx5_ib_multiport_mutex); 3616 3617 mlx5_nic_vport_disable_roce(dev->mdev); 3618 } 3619 3620 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3621 enum rdma_remove_reason why, 3622 struct uverbs_attr_bundle *attrs) 3623 { 3624 struct mlx5_user_mmap_entry *obj = uobject->object; 3625 3626 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3627 return 0; 3628 } 3629 3630 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3631 struct mlx5_user_mmap_entry *entry, 3632 size_t length) 3633 { 3634 return rdma_user_mmap_entry_insert_range( 3635 &c->ibucontext, &entry->rdma_entry, length, 3636 (MLX5_IB_MMAP_OFFSET_START << 16), 3637 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3638 } 3639 3640 static struct mlx5_user_mmap_entry * 3641 alloc_var_entry(struct mlx5_ib_ucontext *c) 3642 { 3643 struct mlx5_user_mmap_entry *entry; 3644 struct mlx5_var_table *var_table; 3645 u32 page_idx; 3646 int err; 3647 3648 var_table = &to_mdev(c->ibucontext.device)->var_table; 3649 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3650 if (!entry) 3651 return ERR_PTR(-ENOMEM); 3652 3653 mutex_lock(&var_table->bitmap_lock); 3654 page_idx = find_first_zero_bit(var_table->bitmap, 3655 var_table->num_var_hw_entries); 3656 if (page_idx >= var_table->num_var_hw_entries) { 3657 err = -ENOSPC; 3658 mutex_unlock(&var_table->bitmap_lock); 3659 goto end; 3660 } 3661 3662 set_bit(page_idx, var_table->bitmap); 3663 mutex_unlock(&var_table->bitmap_lock); 3664 3665 entry->address = var_table->hw_start_addr + 3666 (page_idx * var_table->stride_size); 3667 entry->page_idx = page_idx; 3668 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3669 3670 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3671 var_table->stride_size); 3672 if (err) 3673 goto err_insert; 3674 3675 return entry; 3676 3677 err_insert: 3678 mutex_lock(&var_table->bitmap_lock); 3679 clear_bit(page_idx, var_table->bitmap); 3680 mutex_unlock(&var_table->bitmap_lock); 3681 end: 3682 kfree(entry); 3683 return ERR_PTR(err); 3684 } 3685 3686 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3687 struct uverbs_attr_bundle *attrs) 3688 { 3689 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3690 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3691 struct mlx5_ib_ucontext *c; 3692 struct mlx5_user_mmap_entry *entry; 3693 u64 mmap_offset; 3694 u32 length; 3695 int err; 3696 3697 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3698 if (IS_ERR(c)) 3699 return PTR_ERR(c); 3700 3701 entry = alloc_var_entry(c); 3702 if (IS_ERR(entry)) 3703 return PTR_ERR(entry); 3704 3705 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3706 length = entry->rdma_entry.npages * PAGE_SIZE; 3707 uobj->object = entry; 3708 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3709 3710 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3711 &mmap_offset, sizeof(mmap_offset)); 3712 if (err) 3713 return err; 3714 3715 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3716 &entry->page_idx, sizeof(entry->page_idx)); 3717 if (err) 3718 return err; 3719 3720 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3721 &length, sizeof(length)); 3722 return err; 3723 } 3724 3725 DECLARE_UVERBS_NAMED_METHOD( 3726 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3727 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3728 MLX5_IB_OBJECT_VAR, 3729 UVERBS_ACCESS_NEW, 3730 UA_MANDATORY), 3731 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3732 UVERBS_ATTR_TYPE(u32), 3733 UA_MANDATORY), 3734 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3735 UVERBS_ATTR_TYPE(u32), 3736 UA_MANDATORY), 3737 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3738 UVERBS_ATTR_TYPE(u64), 3739 UA_MANDATORY)); 3740 3741 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3742 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3743 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3744 MLX5_IB_OBJECT_VAR, 3745 UVERBS_ACCESS_DESTROY, 3746 UA_MANDATORY)); 3747 3748 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3749 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3750 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3751 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3752 3753 static bool var_is_supported(struct ib_device *device) 3754 { 3755 struct mlx5_ib_dev *dev = to_mdev(device); 3756 3757 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3758 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3759 } 3760 3761 static struct mlx5_user_mmap_entry * 3762 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3763 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3764 { 3765 struct mlx5_user_mmap_entry *entry; 3766 struct mlx5_ib_dev *dev; 3767 u32 uar_index; 3768 int err; 3769 3770 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3771 if (!entry) 3772 return ERR_PTR(-ENOMEM); 3773 3774 dev = to_mdev(c->ibucontext.device); 3775 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3776 if (err) 3777 goto end; 3778 3779 entry->page_idx = uar_index; 3780 entry->address = uar_index2paddress(dev, uar_index); 3781 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3782 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3783 else 3784 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3785 3786 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3787 if (err) 3788 goto err_insert; 3789 3790 return entry; 3791 3792 err_insert: 3793 mlx5_cmd_free_uar(dev->mdev, uar_index); 3794 end: 3795 kfree(entry); 3796 return ERR_PTR(err); 3797 } 3798 3799 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3800 struct uverbs_attr_bundle *attrs) 3801 { 3802 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3803 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3804 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3805 struct mlx5_ib_ucontext *c; 3806 struct mlx5_user_mmap_entry *entry; 3807 u64 mmap_offset; 3808 u32 length; 3809 int err; 3810 3811 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3812 if (IS_ERR(c)) 3813 return PTR_ERR(c); 3814 3815 err = uverbs_get_const(&alloc_type, attrs, 3816 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3817 if (err) 3818 return err; 3819 3820 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3821 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3822 return -EOPNOTSUPP; 3823 3824 if (!to_mdev(c->ibucontext.device)->wc_support && 3825 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3826 return -EOPNOTSUPP; 3827 3828 entry = alloc_uar_entry(c, alloc_type); 3829 if (IS_ERR(entry)) 3830 return PTR_ERR(entry); 3831 3832 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3833 length = entry->rdma_entry.npages * PAGE_SIZE; 3834 uobj->object = entry; 3835 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3836 3837 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3838 &mmap_offset, sizeof(mmap_offset)); 3839 if (err) 3840 return err; 3841 3842 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3843 &entry->page_idx, sizeof(entry->page_idx)); 3844 if (err) 3845 return err; 3846 3847 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3848 &length, sizeof(length)); 3849 return err; 3850 } 3851 3852 DECLARE_UVERBS_NAMED_METHOD( 3853 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3854 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3855 MLX5_IB_OBJECT_UAR, 3856 UVERBS_ACCESS_NEW, 3857 UA_MANDATORY), 3858 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3859 enum mlx5_ib_uapi_uar_alloc_type, 3860 UA_MANDATORY), 3861 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3862 UVERBS_ATTR_TYPE(u32), 3863 UA_MANDATORY), 3864 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3865 UVERBS_ATTR_TYPE(u32), 3866 UA_MANDATORY), 3867 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3868 UVERBS_ATTR_TYPE(u64), 3869 UA_MANDATORY)); 3870 3871 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3872 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3873 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3874 MLX5_IB_OBJECT_UAR, 3875 UVERBS_ACCESS_DESTROY, 3876 UA_MANDATORY)); 3877 3878 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3879 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3880 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3881 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3882 3883 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3884 mlx5_ib_dm, 3885 UVERBS_OBJECT_DM, 3886 UVERBS_METHOD_DM_ALLOC, 3887 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3888 UVERBS_ATTR_TYPE(u64), 3889 UA_MANDATORY), 3890 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3891 UVERBS_ATTR_TYPE(u16), 3892 UA_OPTIONAL), 3893 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3894 enum mlx5_ib_uapi_dm_type, 3895 UA_OPTIONAL)); 3896 3897 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3898 mlx5_ib_flow_action, 3899 UVERBS_OBJECT_FLOW_ACTION, 3900 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3901 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3902 enum mlx5_ib_uapi_flow_action_flags)); 3903 3904 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3905 mlx5_ib_query_context, 3906 UVERBS_OBJECT_DEVICE, 3907 UVERBS_METHOD_QUERY_CONTEXT, 3908 UVERBS_ATTR_PTR_OUT( 3909 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3910 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3911 dump_fill_mkey), 3912 UA_MANDATORY)); 3913 3914 static const struct uapi_definition mlx5_ib_defs[] = { 3915 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3916 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3917 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3918 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3919 3920 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3921 &mlx5_ib_flow_action), 3922 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3923 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3924 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3925 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3926 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3927 {} 3928 }; 3929 3930 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3931 { 3932 mlx5_ib_cleanup_multiport_master(dev); 3933 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3934 cleanup_srcu_struct(&dev->odp_srcu); 3935 3936 WARN_ON(!xa_empty(&dev->sig_mrs)); 3937 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3938 } 3939 3940 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3941 { 3942 struct mlx5_core_dev *mdev = dev->mdev; 3943 int err; 3944 int i; 3945 3946 for (i = 0; i < dev->num_ports; i++) { 3947 spin_lock_init(&dev->port[i].mp.mpi_lock); 3948 rwlock_init(&dev->port[i].roce.netdev_lock); 3949 dev->port[i].roce.dev = dev; 3950 dev->port[i].roce.native_port_num = i + 1; 3951 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3952 } 3953 3954 mlx5_ib_internal_fill_odp_caps(dev); 3955 3956 err = mlx5_ib_init_multiport_master(dev); 3957 if (err) 3958 return err; 3959 3960 err = set_has_smi_cap(dev); 3961 if (err) 3962 return err; 3963 3964 if (!mlx5_core_mp_enabled(mdev)) { 3965 for (i = 1; i <= dev->num_ports; i++) { 3966 err = get_port_caps(dev, i); 3967 if (err) 3968 break; 3969 } 3970 } else { 3971 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 3972 } 3973 if (err) 3974 goto err_mp; 3975 3976 if (mlx5_use_mad_ifc(dev)) 3977 get_ext_port_caps(dev); 3978 3979 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3980 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3981 dev->ib_dev.phys_port_cnt = dev->num_ports; 3982 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3983 dev->ib_dev.dev.parent = mdev->device; 3984 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3985 3986 mutex_init(&dev->cap_mask_mutex); 3987 INIT_LIST_HEAD(&dev->qp_list); 3988 spin_lock_init(&dev->reset_flow_resource_lock); 3989 xa_init(&dev->odp_mkeys); 3990 xa_init(&dev->sig_mrs); 3991 atomic_set(&dev->mkey_var, 0); 3992 3993 spin_lock_init(&dev->dm.lock); 3994 dev->dm.dev = mdev; 3995 3996 err = init_srcu_struct(&dev->odp_srcu); 3997 if (err) 3998 goto err_mp; 3999 4000 return 0; 4001 4002 err_mp: 4003 mlx5_ib_cleanup_multiport_master(dev); 4004 4005 return -ENOMEM; 4006 } 4007 4008 static int mlx5_ib_enable_driver(struct ib_device *dev) 4009 { 4010 struct mlx5_ib_dev *mdev = to_mdev(dev); 4011 int ret; 4012 4013 ret = mlx5_ib_test_wc(mdev); 4014 mlx5_ib_dbg(mdev, "Write-Combining %s", 4015 mdev->wc_support ? "supported" : "not supported"); 4016 4017 return ret; 4018 } 4019 4020 static const struct ib_device_ops mlx5_ib_dev_ops = { 4021 .owner = THIS_MODULE, 4022 .driver_id = RDMA_DRIVER_MLX5, 4023 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4024 4025 .add_gid = mlx5_ib_add_gid, 4026 .alloc_mr = mlx5_ib_alloc_mr, 4027 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4028 .alloc_pd = mlx5_ib_alloc_pd, 4029 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4030 .attach_mcast = mlx5_ib_mcg_attach, 4031 .check_mr_status = mlx5_ib_check_mr_status, 4032 .create_ah = mlx5_ib_create_ah, 4033 .create_cq = mlx5_ib_create_cq, 4034 .create_qp = mlx5_ib_create_qp, 4035 .create_srq = mlx5_ib_create_srq, 4036 .dealloc_pd = mlx5_ib_dealloc_pd, 4037 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4038 .del_gid = mlx5_ib_del_gid, 4039 .dereg_mr = mlx5_ib_dereg_mr, 4040 .destroy_ah = mlx5_ib_destroy_ah, 4041 .destroy_cq = mlx5_ib_destroy_cq, 4042 .destroy_qp = mlx5_ib_destroy_qp, 4043 .destroy_srq = mlx5_ib_destroy_srq, 4044 .detach_mcast = mlx5_ib_mcg_detach, 4045 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4046 .drain_rq = mlx5_ib_drain_rq, 4047 .drain_sq = mlx5_ib_drain_sq, 4048 .enable_driver = mlx5_ib_enable_driver, 4049 .get_dev_fw_str = get_dev_fw_str, 4050 .get_dma_mr = mlx5_ib_get_dma_mr, 4051 .get_link_layer = mlx5_ib_port_link_layer, 4052 .map_mr_sg = mlx5_ib_map_mr_sg, 4053 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4054 .mmap = mlx5_ib_mmap, 4055 .mmap_free = mlx5_ib_mmap_free, 4056 .modify_cq = mlx5_ib_modify_cq, 4057 .modify_device = mlx5_ib_modify_device, 4058 .modify_port = mlx5_ib_modify_port, 4059 .modify_qp = mlx5_ib_modify_qp, 4060 .modify_srq = mlx5_ib_modify_srq, 4061 .poll_cq = mlx5_ib_poll_cq, 4062 .post_recv = mlx5_ib_post_recv_nodrain, 4063 .post_send = mlx5_ib_post_send_nodrain, 4064 .post_srq_recv = mlx5_ib_post_srq_recv, 4065 .process_mad = mlx5_ib_process_mad, 4066 .query_ah = mlx5_ib_query_ah, 4067 .query_device = mlx5_ib_query_device, 4068 .query_gid = mlx5_ib_query_gid, 4069 .query_pkey = mlx5_ib_query_pkey, 4070 .query_qp = mlx5_ib_query_qp, 4071 .query_srq = mlx5_ib_query_srq, 4072 .query_ucontext = mlx5_ib_query_ucontext, 4073 .reg_user_mr = mlx5_ib_reg_user_mr, 4074 .req_notify_cq = mlx5_ib_arm_cq, 4075 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4076 .resize_cq = mlx5_ib_resize_cq, 4077 4078 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4079 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4080 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4081 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4082 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4083 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4084 }; 4085 4086 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4087 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4088 }; 4089 4090 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4091 .get_vf_config = mlx5_ib_get_vf_config, 4092 .get_vf_guid = mlx5_ib_get_vf_guid, 4093 .get_vf_stats = mlx5_ib_get_vf_stats, 4094 .set_vf_guid = mlx5_ib_set_vf_guid, 4095 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4096 }; 4097 4098 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4099 .alloc_mw = mlx5_ib_alloc_mw, 4100 .dealloc_mw = mlx5_ib_dealloc_mw, 4101 }; 4102 4103 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4104 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4105 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4106 4107 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4108 }; 4109 4110 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4111 .alloc_dm = mlx5_ib_alloc_dm, 4112 .dealloc_dm = mlx5_ib_dealloc_dm, 4113 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4114 }; 4115 4116 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4117 { 4118 struct mlx5_core_dev *mdev = dev->mdev; 4119 struct mlx5_var_table *var_table = &dev->var_table; 4120 u8 log_doorbell_bar_size; 4121 u8 log_doorbell_stride; 4122 u64 bar_size; 4123 4124 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4125 log_doorbell_bar_size); 4126 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4127 log_doorbell_stride); 4128 var_table->hw_start_addr = dev->mdev->bar_addr + 4129 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4130 doorbell_bar_offset); 4131 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4132 var_table->stride_size = 1ULL << log_doorbell_stride; 4133 var_table->num_var_hw_entries = div_u64(bar_size, 4134 var_table->stride_size); 4135 mutex_init(&var_table->bitmap_lock); 4136 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4137 GFP_KERNEL); 4138 return (var_table->bitmap) ? 0 : -ENOMEM; 4139 } 4140 4141 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4142 { 4143 bitmap_free(dev->var_table.bitmap); 4144 } 4145 4146 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4147 { 4148 struct mlx5_core_dev *mdev = dev->mdev; 4149 int err; 4150 4151 dev->ib_dev.uverbs_cmd_mask = 4152 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 4153 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 4154 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 4155 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 4156 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 4157 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 4158 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4159 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4160 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4161 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4162 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4163 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4164 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4165 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4166 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4167 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4168 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4169 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4170 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4171 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4172 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4173 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4174 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4175 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4176 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4177 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4178 dev->ib_dev.uverbs_ex_cmd_mask = 4179 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4180 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4181 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4182 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 4183 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 4184 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4185 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4186 4187 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4188 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4189 ib_set_device_ops(&dev->ib_dev, 4190 &mlx5_ib_dev_ipoib_enhanced_ops); 4191 4192 if (mlx5_core_is_pf(mdev)) 4193 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4194 4195 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4196 4197 if (MLX5_CAP_GEN(mdev, imaicl)) { 4198 dev->ib_dev.uverbs_cmd_mask |= 4199 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4200 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4201 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4202 } 4203 4204 if (MLX5_CAP_GEN(mdev, xrc)) { 4205 dev->ib_dev.uverbs_cmd_mask |= 4206 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4207 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4208 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4209 } 4210 4211 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4212 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4213 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4214 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4215 4216 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4217 4218 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4219 dev->ib_dev.driver_def = mlx5_ib_defs; 4220 4221 err = init_node_data(dev); 4222 if (err) 4223 return err; 4224 4225 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4226 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4227 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4228 mutex_init(&dev->lb.mutex); 4229 4230 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4231 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4232 err = mlx5_ib_init_var_table(dev); 4233 if (err) 4234 return err; 4235 } 4236 4237 dev->ib_dev.use_cq_dim = true; 4238 4239 return 0; 4240 } 4241 4242 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4243 .get_port_immutable = mlx5_port_immutable, 4244 .query_port = mlx5_ib_query_port, 4245 }; 4246 4247 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4248 { 4249 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4250 return 0; 4251 } 4252 4253 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4254 .get_port_immutable = mlx5_port_rep_immutable, 4255 .query_port = mlx5_ib_rep_query_port, 4256 }; 4257 4258 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4259 { 4260 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4261 return 0; 4262 } 4263 4264 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4265 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4266 .create_wq = mlx5_ib_create_wq, 4267 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4268 .destroy_wq = mlx5_ib_destroy_wq, 4269 .get_netdev = mlx5_ib_get_netdev, 4270 .modify_wq = mlx5_ib_modify_wq, 4271 }; 4272 4273 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4274 { 4275 struct mlx5_core_dev *mdev = dev->mdev; 4276 enum rdma_link_layer ll; 4277 int port_type_cap; 4278 u8 port_num = 0; 4279 int err; 4280 4281 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4282 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4283 4284 if (ll == IB_LINK_LAYER_ETHERNET) { 4285 dev->ib_dev.uverbs_ex_cmd_mask |= 4286 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4287 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4288 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4289 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4290 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4291 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4292 4293 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4294 4295 /* Register only for native ports */ 4296 err = mlx5_add_netdev_notifier(dev, port_num); 4297 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4298 /* 4299 * We don't enable ETH interface for 4300 * 1. IB representors 4301 * 2. User disabled ROCE through devlink interface 4302 */ 4303 return err; 4304 4305 err = mlx5_enable_eth(dev); 4306 if (err) 4307 goto cleanup; 4308 } 4309 4310 return 0; 4311 cleanup: 4312 mlx5_remove_netdev_notifier(dev, port_num); 4313 return err; 4314 } 4315 4316 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4317 { 4318 struct mlx5_core_dev *mdev = dev->mdev; 4319 enum rdma_link_layer ll; 4320 int port_type_cap; 4321 u8 port_num; 4322 4323 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4324 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4325 4326 if (ll == IB_LINK_LAYER_ETHERNET) { 4327 if (!dev->is_rep) 4328 mlx5_disable_eth(dev); 4329 4330 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4331 mlx5_remove_netdev_notifier(dev, port_num); 4332 } 4333 } 4334 4335 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4336 { 4337 mlx5_ib_init_cong_debugfs(dev, 4338 mlx5_core_native_port_num(dev->mdev) - 1); 4339 return 0; 4340 } 4341 4342 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4343 { 4344 mlx5_ib_cleanup_cong_debugfs(dev, 4345 mlx5_core_native_port_num(dev->mdev) - 1); 4346 } 4347 4348 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4349 { 4350 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4351 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4352 } 4353 4354 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4355 { 4356 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4357 } 4358 4359 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4360 { 4361 int err; 4362 4363 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4364 if (err) 4365 return err; 4366 4367 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4368 if (err) 4369 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4370 4371 return err; 4372 } 4373 4374 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4375 { 4376 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4377 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4378 } 4379 4380 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4381 { 4382 const char *name; 4383 4384 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4385 if (!mlx5_lag_is_roce(dev->mdev)) 4386 name = "mlx5_%d"; 4387 else 4388 name = "mlx5_bond_%d"; 4389 return ib_register_device(&dev->ib_dev, name); 4390 } 4391 4392 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4393 { 4394 int err; 4395 4396 err = mlx5_mr_cache_cleanup(dev); 4397 if (err) 4398 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4399 4400 if (dev->umrc.qp) 4401 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4402 if (dev->umrc.cq) 4403 ib_free_cq(dev->umrc.cq); 4404 if (dev->umrc.pd) 4405 ib_dealloc_pd(dev->umrc.pd); 4406 } 4407 4408 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4409 { 4410 ib_unregister_device(&dev->ib_dev); 4411 } 4412 4413 enum { 4414 MAX_UMR_WR = 128, 4415 }; 4416 4417 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4418 { 4419 struct ib_qp_init_attr *init_attr = NULL; 4420 struct ib_qp_attr *attr = NULL; 4421 struct ib_pd *pd; 4422 struct ib_cq *cq; 4423 struct ib_qp *qp; 4424 int ret; 4425 4426 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4427 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4428 if (!attr || !init_attr) { 4429 ret = -ENOMEM; 4430 goto error_0; 4431 } 4432 4433 pd = ib_alloc_pd(&dev->ib_dev, 0); 4434 if (IS_ERR(pd)) { 4435 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4436 ret = PTR_ERR(pd); 4437 goto error_0; 4438 } 4439 4440 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4441 if (IS_ERR(cq)) { 4442 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4443 ret = PTR_ERR(cq); 4444 goto error_2; 4445 } 4446 4447 init_attr->send_cq = cq; 4448 init_attr->recv_cq = cq; 4449 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4450 init_attr->cap.max_send_wr = MAX_UMR_WR; 4451 init_attr->cap.max_send_sge = 1; 4452 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4453 init_attr->port_num = 1; 4454 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4455 if (IS_ERR(qp)) { 4456 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4457 ret = PTR_ERR(qp); 4458 goto error_3; 4459 } 4460 qp->device = &dev->ib_dev; 4461 qp->real_qp = qp; 4462 qp->uobject = NULL; 4463 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4464 qp->send_cq = init_attr->send_cq; 4465 qp->recv_cq = init_attr->recv_cq; 4466 4467 attr->qp_state = IB_QPS_INIT; 4468 attr->port_num = 1; 4469 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4470 IB_QP_PORT, NULL); 4471 if (ret) { 4472 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4473 goto error_4; 4474 } 4475 4476 memset(attr, 0, sizeof(*attr)); 4477 attr->qp_state = IB_QPS_RTR; 4478 attr->path_mtu = IB_MTU_256; 4479 4480 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4481 if (ret) { 4482 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4483 goto error_4; 4484 } 4485 4486 memset(attr, 0, sizeof(*attr)); 4487 attr->qp_state = IB_QPS_RTS; 4488 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4489 if (ret) { 4490 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4491 goto error_4; 4492 } 4493 4494 dev->umrc.qp = qp; 4495 dev->umrc.cq = cq; 4496 dev->umrc.pd = pd; 4497 4498 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4499 ret = mlx5_mr_cache_init(dev); 4500 if (ret) { 4501 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4502 goto error_4; 4503 } 4504 4505 kfree(attr); 4506 kfree(init_attr); 4507 4508 return 0; 4509 4510 error_4: 4511 mlx5_ib_destroy_qp(qp, NULL); 4512 dev->umrc.qp = NULL; 4513 4514 error_3: 4515 ib_free_cq(cq); 4516 dev->umrc.cq = NULL; 4517 4518 error_2: 4519 ib_dealloc_pd(pd); 4520 dev->umrc.pd = NULL; 4521 4522 error_0: 4523 kfree(attr); 4524 kfree(init_attr); 4525 return ret; 4526 } 4527 4528 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4529 { 4530 struct dentry *root; 4531 4532 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4533 return 0; 4534 4535 mutex_init(&dev->delay_drop.lock); 4536 dev->delay_drop.dev = dev; 4537 dev->delay_drop.activate = false; 4538 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4539 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4540 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4541 atomic_set(&dev->delay_drop.events_cnt, 0); 4542 4543 if (!mlx5_debugfs_root) 4544 return 0; 4545 4546 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4547 dev->delay_drop.dir_debugfs = root; 4548 4549 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4550 &dev->delay_drop.events_cnt); 4551 debugfs_create_atomic_t("num_rqs", 0400, root, 4552 &dev->delay_drop.rqs_cnt); 4553 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4554 &fops_delay_drop_timeout); 4555 return 0; 4556 } 4557 4558 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4559 { 4560 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4561 return; 4562 4563 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4564 if (!dev->delay_drop.dir_debugfs) 4565 return; 4566 4567 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4568 dev->delay_drop.dir_debugfs = NULL; 4569 } 4570 4571 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4572 { 4573 dev->mdev_events.notifier_call = mlx5_ib_event; 4574 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4575 return 0; 4576 } 4577 4578 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4579 { 4580 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4581 } 4582 4583 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4584 const struct mlx5_ib_profile *profile, 4585 int stage) 4586 { 4587 dev->ib_active = false; 4588 4589 /* Number of stages to cleanup */ 4590 while (stage) { 4591 stage--; 4592 if (profile->stage[stage].cleanup) 4593 profile->stage[stage].cleanup(dev); 4594 } 4595 4596 kfree(dev->port); 4597 ib_dealloc_device(&dev->ib_dev); 4598 } 4599 4600 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 4601 const struct mlx5_ib_profile *profile) 4602 { 4603 int err; 4604 int i; 4605 4606 dev->profile = profile; 4607 4608 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4609 if (profile->stage[i].init) { 4610 err = profile->stage[i].init(dev); 4611 if (err) 4612 goto err_out; 4613 } 4614 } 4615 4616 dev->ib_active = true; 4617 4618 return dev; 4619 4620 err_out: 4621 __mlx5_ib_remove(dev, profile, i); 4622 4623 return NULL; 4624 } 4625 4626 static const struct mlx5_ib_profile pf_profile = { 4627 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4628 mlx5_ib_stage_init_init, 4629 mlx5_ib_stage_init_cleanup), 4630 STAGE_CREATE(MLX5_IB_STAGE_FS, 4631 mlx5_ib_fs_init, 4632 mlx5_ib_fs_cleanup), 4633 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4634 mlx5_ib_stage_caps_init, 4635 mlx5_ib_stage_caps_cleanup), 4636 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4637 mlx5_ib_stage_non_default_cb, 4638 NULL), 4639 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4640 mlx5_ib_roce_init, 4641 mlx5_ib_roce_cleanup), 4642 STAGE_CREATE(MLX5_IB_STAGE_QP, 4643 mlx5_init_qp_table, 4644 mlx5_cleanup_qp_table), 4645 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4646 mlx5_init_srq_table, 4647 mlx5_cleanup_srq_table), 4648 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4649 mlx5_ib_dev_res_init, 4650 mlx5_ib_dev_res_cleanup), 4651 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4652 mlx5_ib_stage_dev_notifier_init, 4653 mlx5_ib_stage_dev_notifier_cleanup), 4654 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4655 mlx5_ib_odp_init_one, 4656 mlx5_ib_odp_cleanup_one), 4657 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4658 mlx5_ib_counters_init, 4659 mlx5_ib_counters_cleanup), 4660 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4661 mlx5_ib_stage_cong_debugfs_init, 4662 mlx5_ib_stage_cong_debugfs_cleanup), 4663 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4664 mlx5_ib_stage_uar_init, 4665 mlx5_ib_stage_uar_cleanup), 4666 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4667 mlx5_ib_stage_bfrag_init, 4668 mlx5_ib_stage_bfrag_cleanup), 4669 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4670 NULL, 4671 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4672 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4673 mlx5_ib_devx_init, 4674 mlx5_ib_devx_cleanup), 4675 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4676 mlx5_ib_stage_ib_reg_init, 4677 mlx5_ib_stage_ib_reg_cleanup), 4678 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4679 mlx5_ib_stage_post_ib_reg_umr_init, 4680 NULL), 4681 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4682 mlx5_ib_stage_delay_drop_init, 4683 mlx5_ib_stage_delay_drop_cleanup), 4684 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4685 mlx5_ib_restrack_init, 4686 NULL), 4687 }; 4688 4689 const struct mlx5_ib_profile raw_eth_profile = { 4690 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4691 mlx5_ib_stage_init_init, 4692 mlx5_ib_stage_init_cleanup), 4693 STAGE_CREATE(MLX5_IB_STAGE_FS, 4694 mlx5_ib_fs_init, 4695 mlx5_ib_fs_cleanup), 4696 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4697 mlx5_ib_stage_caps_init, 4698 mlx5_ib_stage_caps_cleanup), 4699 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4700 mlx5_ib_stage_raw_eth_non_default_cb, 4701 NULL), 4702 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4703 mlx5_ib_roce_init, 4704 mlx5_ib_roce_cleanup), 4705 STAGE_CREATE(MLX5_IB_STAGE_QP, 4706 mlx5_init_qp_table, 4707 mlx5_cleanup_qp_table), 4708 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4709 mlx5_init_srq_table, 4710 mlx5_cleanup_srq_table), 4711 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4712 mlx5_ib_dev_res_init, 4713 mlx5_ib_dev_res_cleanup), 4714 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4715 mlx5_ib_stage_dev_notifier_init, 4716 mlx5_ib_stage_dev_notifier_cleanup), 4717 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4718 mlx5_ib_counters_init, 4719 mlx5_ib_counters_cleanup), 4720 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4721 mlx5_ib_stage_cong_debugfs_init, 4722 mlx5_ib_stage_cong_debugfs_cleanup), 4723 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4724 mlx5_ib_stage_uar_init, 4725 mlx5_ib_stage_uar_cleanup), 4726 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4727 mlx5_ib_stage_bfrag_init, 4728 mlx5_ib_stage_bfrag_cleanup), 4729 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4730 NULL, 4731 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4732 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4733 mlx5_ib_devx_init, 4734 mlx5_ib_devx_cleanup), 4735 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4736 mlx5_ib_stage_ib_reg_init, 4737 mlx5_ib_stage_ib_reg_cleanup), 4738 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4739 mlx5_ib_stage_post_ib_reg_umr_init, 4740 NULL), 4741 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4742 mlx5_ib_restrack_init, 4743 NULL), 4744 }; 4745 4746 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 4747 { 4748 struct mlx5_ib_multiport_info *mpi; 4749 struct mlx5_ib_dev *dev; 4750 bool bound = false; 4751 int err; 4752 4753 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4754 if (!mpi) 4755 return NULL; 4756 4757 mpi->mdev = mdev; 4758 4759 err = mlx5_query_nic_vport_system_image_guid(mdev, 4760 &mpi->sys_image_guid); 4761 if (err) { 4762 kfree(mpi); 4763 return NULL; 4764 } 4765 4766 mutex_lock(&mlx5_ib_multiport_mutex); 4767 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4768 if (dev->sys_image_guid == mpi->sys_image_guid) 4769 bound = mlx5_ib_bind_slave_port(dev, mpi); 4770 4771 if (bound) { 4772 rdma_roce_rescan_device(&dev->ib_dev); 4773 break; 4774 } 4775 } 4776 4777 if (!bound) { 4778 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4779 dev_dbg(mdev->device, 4780 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4781 } 4782 mutex_unlock(&mlx5_ib_multiport_mutex); 4783 4784 return mpi; 4785 } 4786 4787 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 4788 { 4789 const struct mlx5_ib_profile *profile; 4790 enum rdma_link_layer ll; 4791 struct mlx5_ib_dev *dev; 4792 int port_type_cap; 4793 int num_ports; 4794 4795 if (MLX5_ESWITCH_MANAGER(mdev) && 4796 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) { 4797 if (!mlx5_core_mp_enabled(mdev)) 4798 mlx5_ib_register_vport_reps(mdev); 4799 return mdev; 4800 } 4801 4802 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4803 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4804 4805 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 4806 return mlx5_ib_add_slave_port(mdev); 4807 4808 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4809 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4810 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4811 if (!dev) 4812 return NULL; 4813 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4814 GFP_KERNEL); 4815 if (!dev->port) { 4816 ib_dealloc_device(&dev->ib_dev); 4817 return NULL; 4818 } 4819 4820 dev->mdev = mdev; 4821 dev->num_ports = num_ports; 4822 4823 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4824 profile = &raw_eth_profile; 4825 else 4826 profile = &pf_profile; 4827 4828 return __mlx5_ib_add(dev, profile); 4829 } 4830 4831 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4832 { 4833 struct mlx5_ib_multiport_info *mpi; 4834 struct mlx5_ib_dev *dev; 4835 4836 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 4837 mlx5_ib_unregister_vport_reps(mdev); 4838 return; 4839 } 4840 4841 if (mlx5_core_is_mp_slave(mdev)) { 4842 mpi = context; 4843 mutex_lock(&mlx5_ib_multiport_mutex); 4844 if (mpi->ibdev) 4845 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4846 list_del(&mpi->list); 4847 mutex_unlock(&mlx5_ib_multiport_mutex); 4848 kfree(mpi); 4849 return; 4850 } 4851 4852 dev = context; 4853 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4854 } 4855 4856 static struct mlx5_interface mlx5_ib_interface = { 4857 .add = mlx5_ib_add, 4858 .remove = mlx5_ib_remove, 4859 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4860 }; 4861 4862 unsigned long mlx5_ib_get_xlt_emergency_page(void) 4863 { 4864 mutex_lock(&xlt_emergency_page_mutex); 4865 return xlt_emergency_page; 4866 } 4867 4868 void mlx5_ib_put_xlt_emergency_page(void) 4869 { 4870 mutex_unlock(&xlt_emergency_page_mutex); 4871 } 4872 4873 static int __init mlx5_ib_init(void) 4874 { 4875 int err; 4876 4877 xlt_emergency_page = __get_free_page(GFP_KERNEL); 4878 if (!xlt_emergency_page) 4879 return -ENOMEM; 4880 4881 mutex_init(&xlt_emergency_page_mutex); 4882 4883 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4884 if (!mlx5_ib_event_wq) { 4885 free_page(xlt_emergency_page); 4886 return -ENOMEM; 4887 } 4888 4889 mlx5_ib_odp_init(); 4890 4891 err = mlx5_register_interface(&mlx5_ib_interface); 4892 4893 return err; 4894 } 4895 4896 static void __exit mlx5_ib_cleanup(void) 4897 { 4898 mlx5_unregister_interface(&mlx5_ib_interface); 4899 destroy_workqueue(mlx5_ib_event_wq); 4900 mutex_destroy(&xlt_emergency_page_mutex); 4901 free_page(xlt_emergency_page); 4902 } 4903 4904 module_init(mlx5_ib_init); 4905 module_exit(mlx5_ib_cleanup); 4906