1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include <linux/mlx5/fs_helpers.h> 64 #include <linux/mlx5/accel.h> 65 #include <rdma/uverbs_std_types.h> 66 #include <rdma/mlx5_user_ioctl_verbs.h> 67 #include <rdma/mlx5_user_ioctl_cmds.h> 68 69 #define UVERBS_MODULE_NAME mlx5_ib 70 #include <rdma/uverbs_named_ioctl.h> 71 72 #define DRIVER_NAME "mlx5_ib" 73 #define DRIVER_VERSION "5.0-0" 74 75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 79 static char mlx5_version[] = 80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 81 DRIVER_VERSION "\n"; 82 83 struct mlx5_ib_event_work { 84 struct work_struct work; 85 struct mlx5_core_dev *dev; 86 void *context; 87 enum mlx5_dev_event event; 88 unsigned long param; 89 }; 90 91 enum { 92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 93 }; 94 95 static struct workqueue_struct *mlx5_ib_event_wq; 96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 97 static LIST_HEAD(mlx5_ib_dev_list); 98 /* 99 * This mutex should be held when accessing either of the above lists 100 */ 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 102 103 /* We can't use an array for xlt_emergency_page because dma_map_single 104 * doesn't work on kernel modules memory 105 */ 106 static unsigned long xlt_emergency_page; 107 static struct mutex xlt_emergency_page_mutex; 108 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 110 { 111 struct mlx5_ib_dev *dev; 112 113 mutex_lock(&mlx5_ib_multiport_mutex); 114 dev = mpi->ibdev; 115 mutex_unlock(&mlx5_ib_multiport_mutex); 116 return dev; 117 } 118 119 static enum rdma_link_layer 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 121 { 122 switch (port_type_cap) { 123 case MLX5_CAP_PORT_TYPE_IB: 124 return IB_LINK_LAYER_INFINIBAND; 125 case MLX5_CAP_PORT_TYPE_ETH: 126 return IB_LINK_LAYER_ETHERNET; 127 default: 128 return IB_LINK_LAYER_UNSPECIFIED; 129 } 130 } 131 132 static enum rdma_link_layer 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 137 138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 139 } 140 141 static int get_port_state(struct ib_device *ibdev, 142 u8 port_num, 143 enum ib_port_state *state) 144 { 145 struct ib_port_attr attr; 146 int ret; 147 148 memset(&attr, 0, sizeof(attr)); 149 ret = ibdev->query_port(ibdev, port_num, &attr); 150 if (!ret) 151 *state = attr.state; 152 return ret; 153 } 154 155 static int mlx5_netdev_event(struct notifier_block *this, 156 unsigned long event, void *ptr) 157 { 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 160 u8 port_num = roce->native_port_num; 161 struct mlx5_core_dev *mdev; 162 struct mlx5_ib_dev *ibdev; 163 164 ibdev = roce->dev; 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 166 if (!mdev) 167 return NOTIFY_DONE; 168 169 switch (event) { 170 case NETDEV_REGISTER: 171 case NETDEV_UNREGISTER: 172 write_lock(&roce->netdev_lock); 173 if (ibdev->rep) { 174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 175 struct net_device *rep_ndev; 176 177 rep_ndev = mlx5_ib_get_rep_netdev(esw, 178 ibdev->rep->vport); 179 if (rep_ndev == ndev) 180 roce->netdev = (event == NETDEV_UNREGISTER) ? 181 NULL : ndev; 182 } else if (ndev->dev.parent == &mdev->pdev->dev) { 183 roce->netdev = (event == NETDEV_UNREGISTER) ? 184 NULL : ndev; 185 } 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_CHANGE: 190 case NETDEV_UP: 191 case NETDEV_DOWN: { 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 193 struct net_device *upper = NULL; 194 195 if (lag_ndev) { 196 upper = netdev_master_upper_dev_get(lag_ndev); 197 dev_put(lag_ndev); 198 } 199 200 if ((upper == ndev || (!upper && ndev == roce->netdev)) 201 && ibdev->ib_active) { 202 struct ib_event ibev = { }; 203 enum ib_port_state port_state; 204 205 if (get_port_state(&ibdev->ib_dev, port_num, 206 &port_state)) 207 goto done; 208 209 if (roce->last_port_state == port_state) 210 goto done; 211 212 roce->last_port_state = port_state; 213 ibev.device = &ibdev->ib_dev; 214 if (port_state == IB_PORT_DOWN) 215 ibev.event = IB_EVENT_PORT_ERR; 216 else if (port_state == IB_PORT_ACTIVE) 217 ibev.event = IB_EVENT_PORT_ACTIVE; 218 else 219 goto done; 220 221 ibev.element.port_num = port_num; 222 ib_dispatch_event(&ibev); 223 } 224 break; 225 } 226 227 default: 228 break; 229 } 230 done: 231 mlx5_ib_put_native_port_mdev(ibdev, port_num); 232 return NOTIFY_DONE; 233 } 234 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 236 u8 port_num) 237 { 238 struct mlx5_ib_dev *ibdev = to_mdev(device); 239 struct net_device *ndev; 240 struct mlx5_core_dev *mdev; 241 242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 243 if (!mdev) 244 return NULL; 245 246 ndev = mlx5_lag_get_roce_netdev(mdev); 247 if (ndev) 248 goto out; 249 250 /* Ensure ndev does not disappear before we invoke dev_hold() 251 */ 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 253 ndev = ibdev->roce[port_num - 1].netdev; 254 if (ndev) 255 dev_hold(ndev); 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 257 258 out: 259 mlx5_ib_put_native_port_mdev(ibdev, port_num); 260 return ndev; 261 } 262 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 264 u8 ib_port_num, 265 u8 *native_port_num) 266 { 267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 268 ib_port_num); 269 struct mlx5_core_dev *mdev = NULL; 270 struct mlx5_ib_multiport_info *mpi; 271 struct mlx5_ib_port *port; 272 273 if (!mlx5_core_mp_enabled(ibdev->mdev) || 274 ll != IB_LINK_LAYER_ETHERNET) { 275 if (native_port_num) 276 *native_port_num = ib_port_num; 277 return ibdev->mdev; 278 } 279 280 if (native_port_num) 281 *native_port_num = 1; 282 283 port = &ibdev->port[ib_port_num - 1]; 284 if (!port) 285 return NULL; 286 287 spin_lock(&port->mp.mpi_lock); 288 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 289 if (mpi && !mpi->unaffiliate) { 290 mdev = mpi->mdev; 291 /* If it's the master no need to refcount, it'll exist 292 * as long as the ib_dev exists. 293 */ 294 if (!mpi->is_master) 295 mpi->mdev_refcnt++; 296 } 297 spin_unlock(&port->mp.mpi_lock); 298 299 return mdev; 300 } 301 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 303 { 304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 305 port_num); 306 struct mlx5_ib_multiport_info *mpi; 307 struct mlx5_ib_port *port; 308 309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 310 return; 311 312 port = &ibdev->port[port_num - 1]; 313 314 spin_lock(&port->mp.mpi_lock); 315 mpi = ibdev->port[port_num - 1].mp.mpi; 316 if (mpi->is_master) 317 goto out; 318 319 mpi->mdev_refcnt--; 320 if (mpi->unaffiliate) 321 complete(&mpi->unref_comp); 322 out: 323 spin_unlock(&port->mp.mpi_lock); 324 } 325 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 327 u8 *active_width) 328 { 329 switch (eth_proto_oper) { 330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 334 *active_width = IB_WIDTH_1X; 335 *active_speed = IB_SPEED_SDR; 336 break; 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_QDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 350 *active_width = IB_WIDTH_1X; 351 *active_speed = IB_SPEED_EDR; 352 break; 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 357 *active_width = IB_WIDTH_4X; 358 *active_speed = IB_SPEED_QDR; 359 break; 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 363 *active_width = IB_WIDTH_1X; 364 *active_speed = IB_SPEED_HDR; 365 break; 366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_FDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 374 *active_width = IB_WIDTH_4X; 375 *active_speed = IB_SPEED_EDR; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 385 struct ib_port_attr *props) 386 { 387 struct mlx5_ib_dev *dev = to_mdev(device); 388 struct mlx5_core_dev *mdev; 389 struct net_device *ndev, *upper; 390 enum ib_mtu ndev_ib_mtu; 391 bool put_mdev = true; 392 u16 qkey_viol_cntr; 393 u32 eth_prot_oper; 394 u8 mdev_port_num; 395 int err; 396 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 398 if (!mdev) { 399 /* This means the port isn't affiliated yet. Get the 400 * info for the master port instead. 401 */ 402 put_mdev = false; 403 mdev = dev->mdev; 404 mdev_port_num = 1; 405 port_num = 1; 406 } 407 408 /* Possible bad flows are checked before filling out props so in case 409 * of an error it will still be zeroed out. 410 */ 411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 412 mdev_port_num); 413 if (err) 414 goto out; 415 416 props->active_width = IB_WIDTH_4X; 417 props->active_speed = IB_SPEED_QDR; 418 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 420 &props->active_width); 421 422 props->port_cap_flags |= IB_PORT_CM_SUP; 423 props->ip_gids = true; 424 425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 426 roce_address_table_size); 427 props->max_mtu = IB_MTU_4096; 428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 429 props->pkey_tbl_len = 1; 430 props->state = IB_PORT_DOWN; 431 props->phys_state = 3; 432 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 434 props->qkey_viol_cntr = qkey_viol_cntr; 435 436 /* If this is a stub query for an unaffiliated port stop here */ 437 if (!put_mdev) 438 goto out; 439 440 ndev = mlx5_ib_get_netdev(device, port_num); 441 if (!ndev) 442 goto out; 443 444 if (mlx5_lag_is_active(dev->mdev)) { 445 rcu_read_lock(); 446 upper = netdev_master_upper_dev_get_rcu(ndev); 447 if (upper) { 448 dev_put(ndev); 449 ndev = upper; 450 dev_hold(ndev); 451 } 452 rcu_read_unlock(); 453 } 454 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 456 props->state = IB_PORT_ACTIVE; 457 props->phys_state = 5; 458 } 459 460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 461 462 dev_put(ndev); 463 464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 465 out: 466 if (put_mdev) 467 mlx5_ib_put_native_port_mdev(dev, port_num); 468 return err; 469 } 470 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 472 unsigned int index, const union ib_gid *gid, 473 const struct ib_gid_attr *attr) 474 { 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 476 u8 roce_version = 0; 477 u8 roce_l3_type = 0; 478 bool vlan = false; 479 u8 mac[ETH_ALEN]; 480 u16 vlan_id = 0; 481 482 if (gid) { 483 gid_type = attr->gid_type; 484 ether_addr_copy(mac, attr->ndev->dev_addr); 485 486 if (is_vlan_dev(attr->ndev)) { 487 vlan = true; 488 vlan_id = vlan_dev_vlan_id(attr->ndev); 489 } 490 } 491 492 switch (gid_type) { 493 case IB_GID_TYPE_IB: 494 roce_version = MLX5_ROCE_VERSION_1; 495 break; 496 case IB_GID_TYPE_ROCE_UDP_ENCAP: 497 roce_version = MLX5_ROCE_VERSION_2; 498 if (ipv6_addr_v4mapped((void *)gid)) 499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 500 else 501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 502 break; 503 504 default: 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 506 } 507 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 509 roce_l3_type, gid->raw, mac, vlan, 510 vlan_id, port_num); 511 } 512 513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 514 __always_unused void **context) 515 { 516 return set_roce_addr(to_mdev(attr->device), attr->port_num, 517 attr->index, &attr->gid, attr); 518 } 519 520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 521 __always_unused void **context) 522 { 523 return set_roce_addr(to_mdev(attr->device), attr->port_num, 524 attr->index, NULL, NULL); 525 } 526 527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 528 const struct ib_gid_attr *attr) 529 { 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 531 return 0; 532 533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 534 } 535 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 537 { 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 539 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 540 return 0; 541 } 542 543 enum { 544 MLX5_VPORT_ACCESS_METHOD_MAD, 545 MLX5_VPORT_ACCESS_METHOD_HCA, 546 MLX5_VPORT_ACCESS_METHOD_NIC, 547 }; 548 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 550 { 551 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 552 return MLX5_VPORT_ACCESS_METHOD_MAD; 553 554 if (mlx5_ib_port_link_layer(ibdev, 1) == 555 IB_LINK_LAYER_ETHERNET) 556 return MLX5_VPORT_ACCESS_METHOD_NIC; 557 558 return MLX5_VPORT_ACCESS_METHOD_HCA; 559 } 560 561 static void get_atomic_caps(struct mlx5_ib_dev *dev, 562 u8 atomic_size_qp, 563 struct ib_device_attr *props) 564 { 565 u8 tmp; 566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 567 u8 atomic_req_8B_endianness_mode = 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 569 570 /* Check if HW supports 8 bytes standard atomic operations and capable 571 * of host endianness respond 572 */ 573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 574 if (((atomic_operations & tmp) == tmp) && 575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 576 (atomic_req_8B_endianness_mode)) { 577 props->atomic_cap = IB_ATOMIC_HCA; 578 } else { 579 props->atomic_cap = IB_ATOMIC_NONE; 580 } 581 } 582 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 584 struct ib_device_attr *props) 585 { 586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 587 588 get_atomic_caps(dev, atomic_size_qp, props); 589 } 590 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 592 struct ib_device_attr *props) 593 { 594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 595 596 get_atomic_caps(dev, atomic_size_qp, props); 597 } 598 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 600 { 601 struct ib_device_attr props = {}; 602 603 get_atomic_caps_dc(dev, &props); 604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 605 } 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 607 __be64 *sys_image_guid) 608 { 609 struct mlx5_ib_dev *dev = to_mdev(ibdev); 610 struct mlx5_core_dev *mdev = dev->mdev; 611 u64 tmp; 612 int err; 613 614 switch (mlx5_get_vport_access_method(ibdev)) { 615 case MLX5_VPORT_ACCESS_METHOD_MAD: 616 return mlx5_query_mad_ifc_system_image_guid(ibdev, 617 sys_image_guid); 618 619 case MLX5_VPORT_ACCESS_METHOD_HCA: 620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 621 break; 622 623 case MLX5_VPORT_ACCESS_METHOD_NIC: 624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 631 if (!err) 632 *sys_image_guid = cpu_to_be64(tmp); 633 634 return err; 635 636 } 637 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 639 u16 *max_pkeys) 640 { 641 struct mlx5_ib_dev *dev = to_mdev(ibdev); 642 struct mlx5_core_dev *mdev = dev->mdev; 643 644 switch (mlx5_get_vport_access_method(ibdev)) { 645 case MLX5_VPORT_ACCESS_METHOD_MAD: 646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 647 648 case MLX5_VPORT_ACCESS_METHOD_HCA: 649 case MLX5_VPORT_ACCESS_METHOD_NIC: 650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 651 pkey_table_size)); 652 return 0; 653 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int mlx5_query_vendor_id(struct ib_device *ibdev, 660 u32 *vendor_id) 661 { 662 struct mlx5_ib_dev *dev = to_mdev(ibdev); 663 664 switch (mlx5_get_vport_access_method(ibdev)) { 665 case MLX5_VPORT_ACCESS_METHOD_MAD: 666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 667 668 case MLX5_VPORT_ACCESS_METHOD_HCA: 669 case MLX5_VPORT_ACCESS_METHOD_NIC: 670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 671 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 678 __be64 *node_guid) 679 { 680 u64 tmp; 681 int err; 682 683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 684 case MLX5_VPORT_ACCESS_METHOD_MAD: 685 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 686 687 case MLX5_VPORT_ACCESS_METHOD_HCA: 688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 689 break; 690 691 case MLX5_VPORT_ACCESS_METHOD_NIC: 692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 default: 696 return -EINVAL; 697 } 698 699 if (!err) 700 *node_guid = cpu_to_be64(tmp); 701 702 return err; 703 } 704 705 struct mlx5_reg_node_desc { 706 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 707 }; 708 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 710 { 711 struct mlx5_reg_node_desc in; 712 713 if (mlx5_use_mad_ifc(dev)) 714 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 715 716 memset(&in, 0, sizeof(in)); 717 718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 719 sizeof(struct mlx5_reg_node_desc), 720 MLX5_REG_NODE_DESC, 0, 0); 721 } 722 723 static int mlx5_ib_query_device(struct ib_device *ibdev, 724 struct ib_device_attr *props, 725 struct ib_udata *uhw) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 struct mlx5_core_dev *mdev = dev->mdev; 729 int err = -ENOMEM; 730 int max_sq_desc; 731 int max_rq_sg; 732 int max_sq_sg; 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 734 bool raw_support = !mlx5_core_mp_enabled(mdev); 735 struct mlx5_ib_query_device_resp resp = {}; 736 size_t resp_len; 737 u64 max_tso; 738 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 740 if (uhw->outlen && uhw->outlen < resp_len) 741 return -EINVAL; 742 else 743 resp.response_length = resp_len; 744 745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 746 return -EINVAL; 747 748 memset(props, 0, sizeof(*props)); 749 err = mlx5_query_system_image_guid(ibdev, 750 &props->sys_image_guid); 751 if (err) 752 return err; 753 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 755 if (err) 756 return err; 757 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 759 if (err) 760 return err; 761 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 763 (fw_rev_min(dev->mdev) << 16) | 764 fw_rev_sub(dev->mdev); 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 766 IB_DEVICE_PORT_ACTIVE_EVENT | 767 IB_DEVICE_SYS_IMAGE_GUID | 768 IB_DEVICE_RC_RNR_NAK_GEN; 769 770 if (MLX5_CAP_GEN(mdev, pkv)) 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 772 if (MLX5_CAP_GEN(mdev, qkv)) 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 774 if (MLX5_CAP_GEN(mdev, apm)) 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 776 if (MLX5_CAP_GEN(mdev, xrc)) 777 props->device_cap_flags |= IB_DEVICE_XRC; 778 if (MLX5_CAP_GEN(mdev, imaicl)) { 779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 780 IB_DEVICE_MEM_WINDOW_TYPE_2B; 781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 782 /* We support 'Gappy' memory registration too */ 783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 784 } 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 786 if (MLX5_CAP_GEN(mdev, sho)) { 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 788 /* At this stage no support for signature handover */ 789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 790 IB_PROT_T10DIF_TYPE_2 | 791 IB_PROT_T10DIF_TYPE_3; 792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 793 IB_GUARD_T10DIF_CSUM; 794 } 795 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 797 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 799 if (MLX5_CAP_ETH(mdev, csum_cap)) { 800 /* Legacy bit to support old userspace libraries */ 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 803 } 804 805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 806 props->raw_packet_caps |= 807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 808 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 811 if (max_tso) { 812 resp.tso_caps.max_tso = 1 << max_tso; 813 resp.tso_caps.supported_qpts |= 814 1 << IB_QPT_RAW_PACKET; 815 resp.response_length += sizeof(resp.tso_caps); 816 } 817 } 818 819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 820 resp.rss_caps.rx_hash_function = 821 MLX5_RX_HASH_FUNC_TOEPLITZ; 822 resp.rss_caps.rx_hash_fields_mask = 823 MLX5_RX_HASH_SRC_IPV4 | 824 MLX5_RX_HASH_DST_IPV4 | 825 MLX5_RX_HASH_SRC_IPV6 | 826 MLX5_RX_HASH_DST_IPV6 | 827 MLX5_RX_HASH_SRC_PORT_TCP | 828 MLX5_RX_HASH_DST_PORT_TCP | 829 MLX5_RX_HASH_SRC_PORT_UDP | 830 MLX5_RX_HASH_DST_PORT_UDP | 831 MLX5_RX_HASH_INNER; 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 833 MLX5_ACCEL_IPSEC_CAP_DEVICE) 834 resp.rss_caps.rx_hash_fields_mask |= 835 MLX5_RX_HASH_IPSEC_SPI; 836 resp.response_length += sizeof(resp.rss_caps); 837 } 838 } else { 839 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 840 resp.response_length += sizeof(resp.tso_caps); 841 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 842 resp.response_length += sizeof(resp.rss_caps); 843 } 844 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 847 props->device_cap_flags |= IB_DEVICE_UD_TSO; 848 } 849 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 852 raw_support) 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 854 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 858 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 861 raw_support) { 862 /* Legacy bit to support old userspace libraries */ 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 865 } 866 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 868 props->max_dm_size = 869 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 870 } 871 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 874 875 if (MLX5_CAP_GEN(mdev, end_pad)) 876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 877 878 props->vendor_part_id = mdev->pdev->device; 879 props->hw_ver = mdev->pdev->revision; 880 881 props->max_mr_size = ~0ull; 882 props->page_size_cap = ~(min_page_size - 1); 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 886 sizeof(struct mlx5_wqe_data_seg); 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 889 sizeof(struct mlx5_wqe_raddr_seg)) / 890 sizeof(struct mlx5_wqe_data_seg); 891 props->max_send_sge = max_sq_sg; 892 props->max_recv_sge = max_rq_sg; 893 props->max_sge_rd = MLX5_MAX_SGE_RD; 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 904 props->max_srq_sge = max_rq_sg - 1; 905 props->max_fast_reg_page_list_len = 906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 907 get_atomic_caps_qp(dev, props); 908 props->masked_atomic_cap = IB_ATOMIC_NONE; 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 912 props->max_mcast_grp; 913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 914 props->max_ah = INT_MAX; 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 917 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 919 if (MLX5_CAP_GEN(mdev, pg)) 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 921 props->odp_caps = dev->odp_caps; 922 #endif 923 924 if (MLX5_CAP_GEN(mdev, cd)) 925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 926 927 if (!mlx5_core_is_pf(mdev)) 928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 929 930 if (mlx5_ib_port_link_layer(ibdev, 1) == 931 IB_LINK_LAYER_ETHERNET && raw_support) { 932 props->rss_caps.max_rwq_indirection_tables = 933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 934 props->rss_caps.max_rwq_indirection_table_size = 935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 937 props->max_wq_type_rq = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 939 } 940 941 if (MLX5_CAP_GEN(mdev, tag_matching)) { 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 943 props->tm_caps.max_num_tags = 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 945 props->tm_caps.flags = IB_TM_CAP_RC; 946 props->tm_caps.max_ops = 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 949 } 950 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 952 props->cq_caps.max_cq_moderation_count = 953 MLX5_MAX_CQ_COUNT; 954 props->cq_caps.max_cq_moderation_period = 955 MLX5_MAX_CQ_PERIOD; 956 } 957 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 959 resp.response_length += sizeof(resp.cqe_comp_caps); 960 961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 962 resp.cqe_comp_caps.max_num = 963 MLX5_CAP_GEN(dev->mdev, 964 cqe_compression_max_num); 965 966 resp.cqe_comp_caps.supported_format = 967 MLX5_IB_CQE_RES_FORMAT_HASH | 968 MLX5_IB_CQE_RES_FORMAT_CSUM; 969 970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 971 resp.cqe_comp_caps.supported_format |= 972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 973 } 974 } 975 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 977 raw_support) { 978 if (MLX5_CAP_QOS(mdev, packet_pacing) && 979 MLX5_CAP_GEN(mdev, qos)) { 980 resp.packet_pacing_caps.qp_rate_limit_max = 981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 982 resp.packet_pacing_caps.qp_rate_limit_min = 983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 984 resp.packet_pacing_caps.supported_qpts |= 985 1 << IB_QPT_RAW_PACKET; 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 988 resp.packet_pacing_caps.cap_flags |= 989 MLX5_IB_PP_SUPPORT_BURST; 990 } 991 resp.response_length += sizeof(resp.packet_pacing_caps); 992 } 993 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 995 uhw->outlen)) { 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 997 resp.mlx5_ib_support_multi_pkt_send_wqes = 998 MLX5_IB_ALLOW_MPW; 999 1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1001 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1002 MLX5_IB_SUPPORT_EMPW; 1003 1004 resp.response_length += 1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1006 } 1007 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1009 resp.response_length += sizeof(resp.flags); 1010 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1012 resp.flags |= 1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1014 1015 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1017 } 1018 1019 if (field_avail(typeof(resp), sw_parsing_caps, 1020 uhw->outlen)) { 1021 resp.response_length += sizeof(resp.sw_parsing_caps); 1022 if (MLX5_CAP_ETH(mdev, swp)) { 1023 resp.sw_parsing_caps.sw_parsing_offloads |= 1024 MLX5_IB_SW_PARSING; 1025 1026 if (MLX5_CAP_ETH(mdev, swp_csum)) 1027 resp.sw_parsing_caps.sw_parsing_offloads |= 1028 MLX5_IB_SW_PARSING_CSUM; 1029 1030 if (MLX5_CAP_ETH(mdev, swp_lso)) 1031 resp.sw_parsing_caps.sw_parsing_offloads |= 1032 MLX5_IB_SW_PARSING_LSO; 1033 1034 if (resp.sw_parsing_caps.sw_parsing_offloads) 1035 resp.sw_parsing_caps.supported_qpts = 1036 BIT(IB_QPT_RAW_PACKET); 1037 } 1038 } 1039 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1041 raw_support) { 1042 resp.response_length += sizeof(resp.striding_rq_caps); 1043 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1052 resp.striding_rq_caps.supported_qpts = 1053 BIT(IB_QPT_RAW_PACKET); 1054 } 1055 } 1056 1057 if (field_avail(typeof(resp), tunnel_offloads_caps, 1058 uhw->outlen)) { 1059 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1061 resp.tunnel_offloads_caps |= 1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1064 resp.tunnel_offloads_caps |= 1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1067 resp.tunnel_offloads_caps |= 1068 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1070 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1071 resp.tunnel_offloads_caps |= 1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1074 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1075 resp.tunnel_offloads_caps |= 1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1077 } 1078 1079 if (uhw->outlen) { 1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1081 1082 if (err) 1083 return err; 1084 } 1085 1086 return 0; 1087 } 1088 1089 enum mlx5_ib_width { 1090 MLX5_IB_WIDTH_1X = 1 << 0, 1091 MLX5_IB_WIDTH_2X = 1 << 1, 1092 MLX5_IB_WIDTH_4X = 1 << 2, 1093 MLX5_IB_WIDTH_8X = 1 << 3, 1094 MLX5_IB_WIDTH_12X = 1 << 4 1095 }; 1096 1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1098 u8 *ib_width) 1099 { 1100 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1101 int err = 0; 1102 1103 if (active_width & MLX5_IB_WIDTH_1X) { 1104 *ib_width = IB_WIDTH_1X; 1105 } else if (active_width & MLX5_IB_WIDTH_2X) { 1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1107 (int)active_width); 1108 err = -EINVAL; 1109 } else if (active_width & MLX5_IB_WIDTH_4X) { 1110 *ib_width = IB_WIDTH_4X; 1111 } else if (active_width & MLX5_IB_WIDTH_8X) { 1112 *ib_width = IB_WIDTH_8X; 1113 } else if (active_width & MLX5_IB_WIDTH_12X) { 1114 *ib_width = IB_WIDTH_12X; 1115 } else { 1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1117 (int)active_width); 1118 err = -EINVAL; 1119 } 1120 1121 return err; 1122 } 1123 1124 static int mlx5_mtu_to_ib_mtu(int mtu) 1125 { 1126 switch (mtu) { 1127 case 256: return 1; 1128 case 512: return 2; 1129 case 1024: return 3; 1130 case 2048: return 4; 1131 case 4096: return 5; 1132 default: 1133 pr_warn("invalid mtu\n"); 1134 return -1; 1135 } 1136 } 1137 1138 enum ib_max_vl_num { 1139 __IB_MAX_VL_0 = 1, 1140 __IB_MAX_VL_0_1 = 2, 1141 __IB_MAX_VL_0_3 = 3, 1142 __IB_MAX_VL_0_7 = 4, 1143 __IB_MAX_VL_0_14 = 5, 1144 }; 1145 1146 enum mlx5_vl_hw_cap { 1147 MLX5_VL_HW_0 = 1, 1148 MLX5_VL_HW_0_1 = 2, 1149 MLX5_VL_HW_0_2 = 3, 1150 MLX5_VL_HW_0_3 = 4, 1151 MLX5_VL_HW_0_4 = 5, 1152 MLX5_VL_HW_0_5 = 6, 1153 MLX5_VL_HW_0_6 = 7, 1154 MLX5_VL_HW_0_7 = 8, 1155 MLX5_VL_HW_0_14 = 15 1156 }; 1157 1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1159 u8 *max_vl_num) 1160 { 1161 switch (vl_hw_cap) { 1162 case MLX5_VL_HW_0: 1163 *max_vl_num = __IB_MAX_VL_0; 1164 break; 1165 case MLX5_VL_HW_0_1: 1166 *max_vl_num = __IB_MAX_VL_0_1; 1167 break; 1168 case MLX5_VL_HW_0_3: 1169 *max_vl_num = __IB_MAX_VL_0_3; 1170 break; 1171 case MLX5_VL_HW_0_7: 1172 *max_vl_num = __IB_MAX_VL_0_7; 1173 break; 1174 case MLX5_VL_HW_0_14: 1175 *max_vl_num = __IB_MAX_VL_0_14; 1176 break; 1177 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1186 struct ib_port_attr *props) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 struct mlx5_core_dev *mdev = dev->mdev; 1190 struct mlx5_hca_vport_context *rep; 1191 u16 max_mtu; 1192 u16 oper_mtu; 1193 int err; 1194 u8 ib_link_width_oper; 1195 u8 vl_hw_cap; 1196 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1198 if (!rep) { 1199 err = -ENOMEM; 1200 goto out; 1201 } 1202 1203 /* props being zeroed by the caller, avoid zeroing it here */ 1204 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1206 if (err) 1207 goto out; 1208 1209 props->lid = rep->lid; 1210 props->lmc = rep->lmc; 1211 props->sm_lid = rep->sm_lid; 1212 props->sm_sl = rep->sm_sl; 1213 props->state = rep->vport_state; 1214 props->phys_state = rep->port_physical_state; 1215 props->port_cap_flags = rep->cap_mask1; 1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1219 props->bad_pkey_cntr = rep->pkey_violation_counter; 1220 props->qkey_viol_cntr = rep->qkey_violation_counter; 1221 props->subnet_timeout = rep->subnet_timeout; 1222 props->init_type_reply = rep->init_type_reply; 1223 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1225 if (err) 1226 goto out; 1227 1228 err = translate_active_width(ibdev, ib_link_width_oper, 1229 &props->active_width); 1230 if (err) 1231 goto out; 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1233 if (err) 1234 goto out; 1235 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1237 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1239 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1241 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1243 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1245 if (err) 1246 goto out; 1247 1248 err = translate_max_vl_num(ibdev, vl_hw_cap, 1249 &props->max_vl_num); 1250 out: 1251 kfree(rep); 1252 return err; 1253 } 1254 1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1256 struct ib_port_attr *props) 1257 { 1258 unsigned int count; 1259 int ret; 1260 1261 switch (mlx5_get_vport_access_method(ibdev)) { 1262 case MLX5_VPORT_ACCESS_METHOD_MAD: 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1264 break; 1265 1266 case MLX5_VPORT_ACCESS_METHOD_HCA: 1267 ret = mlx5_query_hca_port(ibdev, port, props); 1268 break; 1269 1270 case MLX5_VPORT_ACCESS_METHOD_NIC: 1271 ret = mlx5_query_port_roce(ibdev, port, props); 1272 break; 1273 1274 default: 1275 ret = -EINVAL; 1276 } 1277 1278 if (!ret && props) { 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1280 struct mlx5_core_dev *mdev; 1281 bool put_mdev = true; 1282 1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1284 if (!mdev) { 1285 /* If the port isn't affiliated yet query the master. 1286 * The master and slave will have the same values. 1287 */ 1288 mdev = dev->mdev; 1289 port = 1; 1290 put_mdev = false; 1291 } 1292 count = mlx5_core_reserved_gids_count(mdev); 1293 if (put_mdev) 1294 mlx5_ib_put_native_port_mdev(dev, port); 1295 props->gid_tbl_len -= count; 1296 } 1297 return ret; 1298 } 1299 1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1301 struct ib_port_attr *props) 1302 { 1303 int ret; 1304 1305 /* Only link layer == ethernet is valid for representors */ 1306 ret = mlx5_query_port_roce(ibdev, port, props); 1307 if (ret || !props) 1308 return ret; 1309 1310 /* We don't support GIDS */ 1311 props->gid_tbl_len = 0; 1312 1313 return ret; 1314 } 1315 1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1317 union ib_gid *gid) 1318 { 1319 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1320 struct mlx5_core_dev *mdev = dev->mdev; 1321 1322 switch (mlx5_get_vport_access_method(ibdev)) { 1323 case MLX5_VPORT_ACCESS_METHOD_MAD: 1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1325 1326 case MLX5_VPORT_ACCESS_METHOD_HCA: 1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1328 1329 default: 1330 return -EINVAL; 1331 } 1332 1333 } 1334 1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1336 u16 index, u16 *pkey) 1337 { 1338 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1339 struct mlx5_core_dev *mdev; 1340 bool put_mdev = true; 1341 u8 mdev_port_num; 1342 int err; 1343 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1345 if (!mdev) { 1346 /* The port isn't affiliated yet, get the PKey from the master 1347 * port. For RoCE the PKey tables will be the same. 1348 */ 1349 put_mdev = false; 1350 mdev = dev->mdev; 1351 mdev_port_num = 1; 1352 } 1353 1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1355 index, pkey); 1356 if (put_mdev) 1357 mlx5_ib_put_native_port_mdev(dev, port); 1358 1359 return err; 1360 } 1361 1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1363 u16 *pkey) 1364 { 1365 switch (mlx5_get_vport_access_method(ibdev)) { 1366 case MLX5_VPORT_ACCESS_METHOD_MAD: 1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1368 1369 case MLX5_VPORT_ACCESS_METHOD_HCA: 1370 case MLX5_VPORT_ACCESS_METHOD_NIC: 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1372 default: 1373 return -EINVAL; 1374 } 1375 } 1376 1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1378 struct ib_device_modify *props) 1379 { 1380 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1381 struct mlx5_reg_node_desc in; 1382 struct mlx5_reg_node_desc out; 1383 int err; 1384 1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1386 return -EOPNOTSUPP; 1387 1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1389 return 0; 1390 1391 /* 1392 * If possible, pass node desc to FW, so it can generate 1393 * a 144 trap. If cmd fails, just ignore. 1394 */ 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1398 if (err) 1399 return err; 1400 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1402 1403 return err; 1404 } 1405 1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1407 u32 value) 1408 { 1409 struct mlx5_hca_vport_context ctx = {}; 1410 struct mlx5_core_dev *mdev; 1411 u8 mdev_port_num; 1412 int err; 1413 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1415 if (!mdev) 1416 return -ENODEV; 1417 1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1419 if (err) 1420 goto out; 1421 1422 if (~ctx.cap_mask1_perm & mask) { 1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1424 mask, ctx.cap_mask1_perm); 1425 err = -EINVAL; 1426 goto out; 1427 } 1428 1429 ctx.cap_mask1 = value; 1430 ctx.cap_mask1_perm = mask; 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1432 0, &ctx); 1433 1434 out: 1435 mlx5_ib_put_native_port_mdev(dev, port_num); 1436 1437 return err; 1438 } 1439 1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1441 struct ib_port_modify *props) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct ib_port_attr attr; 1445 u32 tmp; 1446 int err; 1447 u32 change_mask; 1448 u32 value; 1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1450 IB_LINK_LAYER_INFINIBAND); 1451 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For 1453 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1454 */ 1455 if (!is_ib) 1456 return 0; 1457 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1461 return set_port_caps_atomic(dev, port, change_mask, value); 1462 } 1463 1464 mutex_lock(&dev->cap_mask_mutex); 1465 1466 err = ib_query_port(ibdev, port, &attr); 1467 if (err) 1468 goto out; 1469 1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1471 ~props->clr_port_cap_mask; 1472 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1474 1475 out: 1476 mutex_unlock(&dev->cap_mask_mutex); 1477 return err; 1478 } 1479 1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1481 { 1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1484 } 1485 1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1487 { 1488 /* Large page with non 4k uar support might limit the dynamic size */ 1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1490 return MLX5_MIN_DYN_BFREGS; 1491 1492 return MLX5_MAX_DYN_BFREGS; 1493 } 1494 1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1496 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1497 struct mlx5_bfreg_info *bfregi) 1498 { 1499 int uars_per_sys_page; 1500 int bfregs_per_sys_page; 1501 int ref_bfregs = req->total_num_bfregs; 1502 1503 if (req->total_num_bfregs == 0) 1504 return -EINVAL; 1505 1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1508 1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1510 return -ENOMEM; 1511 1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1514 /* This holds the required static allocation asked by the user */ 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1517 return -EINVAL; 1518 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1523 1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1526 lib_uar_4k ? "yes" : "no", ref_bfregs, 1527 req->total_num_bfregs, bfregi->total_num_bfregs, 1528 bfregi->num_sys_pages); 1529 1530 return 0; 1531 } 1532 1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1534 { 1535 struct mlx5_bfreg_info *bfregi; 1536 int err; 1537 int i; 1538 1539 bfregi = &context->bfregi; 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1542 if (err) 1543 goto error; 1544 1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1546 } 1547 1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1550 1551 return 0; 1552 1553 error: 1554 for (--i; i >= 0; i--) 1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1557 1558 return err; 1559 } 1560 1561 static void deallocate_uars(struct mlx5_ib_dev *dev, 1562 struct mlx5_ib_ucontext *context) 1563 { 1564 struct mlx5_bfreg_info *bfregi; 1565 int i; 1566 1567 bfregi = &context->bfregi; 1568 for (i = 0; i < bfregi->num_sys_pages; i++) 1569 if (i < bfregi->num_static_sys_pages || 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1572 } 1573 1574 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1575 { 1576 int err = 0; 1577 1578 mutex_lock(&dev->lb.mutex); 1579 if (td) 1580 dev->lb.user_td++; 1581 if (qp) 1582 dev->lb.qps++; 1583 1584 if (dev->lb.user_td == 2 || 1585 dev->lb.qps == 1) { 1586 if (!dev->lb.enabled) { 1587 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1588 dev->lb.enabled = true; 1589 } 1590 } 1591 1592 mutex_unlock(&dev->lb.mutex); 1593 1594 return err; 1595 } 1596 1597 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1598 { 1599 mutex_lock(&dev->lb.mutex); 1600 if (td) 1601 dev->lb.user_td--; 1602 if (qp) 1603 dev->lb.qps--; 1604 1605 if (dev->lb.user_td == 1 && 1606 dev->lb.qps == 0) { 1607 if (dev->lb.enabled) { 1608 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1609 dev->lb.enabled = false; 1610 } 1611 } 1612 1613 mutex_unlock(&dev->lb.mutex); 1614 } 1615 1616 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1617 u16 uid) 1618 { 1619 int err; 1620 1621 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1622 return 0; 1623 1624 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1625 if (err) 1626 return err; 1627 1628 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1629 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1630 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1631 return err; 1632 1633 return mlx5_ib_enable_lb(dev, true, false); 1634 } 1635 1636 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1637 u16 uid) 1638 { 1639 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1640 return; 1641 1642 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1643 1644 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1645 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1646 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1647 return; 1648 1649 mlx5_ib_disable_lb(dev, true, false); 1650 } 1651 1652 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1653 struct ib_udata *udata) 1654 { 1655 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1656 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1657 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1658 struct mlx5_core_dev *mdev = dev->mdev; 1659 struct mlx5_ib_ucontext *context; 1660 struct mlx5_bfreg_info *bfregi; 1661 int ver; 1662 int err; 1663 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1664 max_cqe_version); 1665 u32 dump_fill_mkey; 1666 bool lib_uar_4k; 1667 1668 if (!dev->ib_active) 1669 return ERR_PTR(-EAGAIN); 1670 1671 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1672 ver = 0; 1673 else if (udata->inlen >= min_req_v2) 1674 ver = 2; 1675 else 1676 return ERR_PTR(-EINVAL); 1677 1678 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1679 if (err) 1680 return ERR_PTR(err); 1681 1682 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1683 return ERR_PTR(-EOPNOTSUPP); 1684 1685 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1686 return ERR_PTR(-EOPNOTSUPP); 1687 1688 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1689 MLX5_NON_FP_BFREGS_PER_UAR); 1690 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1691 return ERR_PTR(-EINVAL); 1692 1693 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1694 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1695 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1696 resp.cache_line_size = cache_line_size(); 1697 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1698 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1699 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1700 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1701 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1702 resp.cqe_version = min_t(__u8, 1703 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1704 req.max_cqe_version); 1705 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1706 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1707 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1708 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1709 resp.response_length = min(offsetof(typeof(resp), response_length) + 1710 sizeof(resp.response_length), udata->outlen); 1711 1712 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1713 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1714 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1715 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1716 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1717 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1718 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1719 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1720 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1721 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1722 } 1723 1724 context = kzalloc(sizeof(*context), GFP_KERNEL); 1725 if (!context) 1726 return ERR_PTR(-ENOMEM); 1727 1728 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1729 bfregi = &context->bfregi; 1730 1731 /* updates req->total_num_bfregs */ 1732 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1733 if (err) 1734 goto out_ctx; 1735 1736 mutex_init(&bfregi->lock); 1737 bfregi->lib_uar_4k = lib_uar_4k; 1738 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1739 GFP_KERNEL); 1740 if (!bfregi->count) { 1741 err = -ENOMEM; 1742 goto out_ctx; 1743 } 1744 1745 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1746 sizeof(*bfregi->sys_pages), 1747 GFP_KERNEL); 1748 if (!bfregi->sys_pages) { 1749 err = -ENOMEM; 1750 goto out_count; 1751 } 1752 1753 err = allocate_uars(dev, context); 1754 if (err) 1755 goto out_sys_pages; 1756 1757 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1758 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1759 #endif 1760 1761 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1762 err = mlx5_ib_devx_create(dev); 1763 if (err < 0) 1764 goto out_uars; 1765 context->devx_uid = err; 1766 } 1767 1768 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1769 context->devx_uid); 1770 if (err) 1771 goto out_devx; 1772 1773 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1774 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1775 if (err) 1776 goto out_mdev; 1777 } 1778 1779 INIT_LIST_HEAD(&context->db_page_list); 1780 mutex_init(&context->db_page_mutex); 1781 1782 resp.tot_bfregs = req.total_num_bfregs; 1783 resp.num_ports = dev->num_ports; 1784 1785 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1786 resp.response_length += sizeof(resp.cqe_version); 1787 1788 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1789 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1790 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1791 resp.response_length += sizeof(resp.cmds_supp_uhw); 1792 } 1793 1794 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1795 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1796 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1797 resp.eth_min_inline++; 1798 } 1799 resp.response_length += sizeof(resp.eth_min_inline); 1800 } 1801 1802 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1803 if (mdev->clock_info) 1804 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1805 resp.response_length += sizeof(resp.clock_info_versions); 1806 } 1807 1808 /* 1809 * We don't want to expose information from the PCI bar that is located 1810 * after 4096 bytes, so if the arch only supports larger pages, let's 1811 * pretend we don't support reading the HCA's core clock. This is also 1812 * forced by mmap function. 1813 */ 1814 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1815 if (PAGE_SIZE <= 4096) { 1816 resp.comp_mask |= 1817 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1818 resp.hca_core_clock_offset = 1819 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1820 } 1821 resp.response_length += sizeof(resp.hca_core_clock_offset); 1822 } 1823 1824 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1825 resp.response_length += sizeof(resp.log_uar_size); 1826 1827 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1828 resp.response_length += sizeof(resp.num_uars_per_page); 1829 1830 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1831 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1832 resp.response_length += sizeof(resp.num_dyn_bfregs); 1833 } 1834 1835 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1836 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1837 resp.dump_fill_mkey = dump_fill_mkey; 1838 resp.comp_mask |= 1839 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1840 } 1841 resp.response_length += sizeof(resp.dump_fill_mkey); 1842 } 1843 1844 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1845 if (err) 1846 goto out_mdev; 1847 1848 bfregi->ver = ver; 1849 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1850 context->cqe_version = resp.cqe_version; 1851 context->lib_caps = req.lib_caps; 1852 print_lib_caps(dev, context->lib_caps); 1853 1854 if (mlx5_lag_is_active(dev->mdev)) { 1855 u8 port = mlx5_core_native_port_num(dev->mdev); 1856 1857 atomic_set(&context->tx_port_affinity, 1858 atomic_add_return( 1859 1, &dev->roce[port].tx_port_affinity)); 1860 } 1861 1862 return &context->ibucontext; 1863 1864 out_mdev: 1865 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1866 out_devx: 1867 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1868 mlx5_ib_devx_destroy(dev, context->devx_uid); 1869 1870 out_uars: 1871 deallocate_uars(dev, context); 1872 1873 out_sys_pages: 1874 kfree(bfregi->sys_pages); 1875 1876 out_count: 1877 kfree(bfregi->count); 1878 1879 out_ctx: 1880 kfree(context); 1881 1882 return ERR_PTR(err); 1883 } 1884 1885 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1886 { 1887 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1888 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1889 struct mlx5_bfreg_info *bfregi; 1890 1891 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1892 /* All umem's must be destroyed before destroying the ucontext. */ 1893 mutex_lock(&ibcontext->per_mm_list_lock); 1894 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1895 mutex_unlock(&ibcontext->per_mm_list_lock); 1896 #endif 1897 1898 bfregi = &context->bfregi; 1899 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1900 1901 if (context->devx_uid) 1902 mlx5_ib_devx_destroy(dev, context->devx_uid); 1903 1904 deallocate_uars(dev, context); 1905 kfree(bfregi->sys_pages); 1906 kfree(bfregi->count); 1907 kfree(context); 1908 1909 return 0; 1910 } 1911 1912 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1913 int uar_idx) 1914 { 1915 int fw_uars_per_page; 1916 1917 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1918 1919 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1920 } 1921 1922 static int get_command(unsigned long offset) 1923 { 1924 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1925 } 1926 1927 static int get_arg(unsigned long offset) 1928 { 1929 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1930 } 1931 1932 static int get_index(unsigned long offset) 1933 { 1934 return get_arg(offset); 1935 } 1936 1937 /* Index resides in an extra byte to enable larger values than 255 */ 1938 static int get_extended_index(unsigned long offset) 1939 { 1940 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1941 } 1942 1943 1944 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1945 { 1946 } 1947 1948 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1949 { 1950 switch (cmd) { 1951 case MLX5_IB_MMAP_WC_PAGE: 1952 return "WC"; 1953 case MLX5_IB_MMAP_REGULAR_PAGE: 1954 return "best effort WC"; 1955 case MLX5_IB_MMAP_NC_PAGE: 1956 return "NC"; 1957 case MLX5_IB_MMAP_DEVICE_MEM: 1958 return "Device Memory"; 1959 default: 1960 return NULL; 1961 } 1962 } 1963 1964 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1965 struct vm_area_struct *vma, 1966 struct mlx5_ib_ucontext *context) 1967 { 1968 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1969 return -EINVAL; 1970 1971 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1972 return -EOPNOTSUPP; 1973 1974 if (vma->vm_flags & VM_WRITE) 1975 return -EPERM; 1976 1977 if (!dev->mdev->clock_info_page) 1978 return -EOPNOTSUPP; 1979 1980 return rdma_user_mmap_page(&context->ibucontext, vma, 1981 dev->mdev->clock_info_page, PAGE_SIZE); 1982 } 1983 1984 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1985 struct vm_area_struct *vma, 1986 struct mlx5_ib_ucontext *context) 1987 { 1988 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1989 int err; 1990 unsigned long idx; 1991 phys_addr_t pfn; 1992 pgprot_t prot; 1993 u32 bfreg_dyn_idx = 0; 1994 u32 uar_index; 1995 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1996 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1997 bfregi->num_static_sys_pages; 1998 1999 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2000 return -EINVAL; 2001 2002 if (dyn_uar) 2003 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2004 else 2005 idx = get_index(vma->vm_pgoff); 2006 2007 if (idx >= max_valid_idx) { 2008 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2009 idx, max_valid_idx); 2010 return -EINVAL; 2011 } 2012 2013 switch (cmd) { 2014 case MLX5_IB_MMAP_WC_PAGE: 2015 case MLX5_IB_MMAP_ALLOC_WC: 2016 /* Some architectures don't support WC memory */ 2017 #if defined(CONFIG_X86) 2018 if (!pat_enabled()) 2019 return -EPERM; 2020 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2021 return -EPERM; 2022 #endif 2023 /* fall through */ 2024 case MLX5_IB_MMAP_REGULAR_PAGE: 2025 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2026 prot = pgprot_writecombine(vma->vm_page_prot); 2027 break; 2028 case MLX5_IB_MMAP_NC_PAGE: 2029 prot = pgprot_noncached(vma->vm_page_prot); 2030 break; 2031 default: 2032 return -EINVAL; 2033 } 2034 2035 if (dyn_uar) { 2036 int uars_per_page; 2037 2038 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2039 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2040 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2041 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2042 bfreg_dyn_idx, bfregi->total_num_bfregs); 2043 return -EINVAL; 2044 } 2045 2046 mutex_lock(&bfregi->lock); 2047 /* Fail if uar already allocated, first bfreg index of each 2048 * page holds its count. 2049 */ 2050 if (bfregi->count[bfreg_dyn_idx]) { 2051 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2052 mutex_unlock(&bfregi->lock); 2053 return -EINVAL; 2054 } 2055 2056 bfregi->count[bfreg_dyn_idx]++; 2057 mutex_unlock(&bfregi->lock); 2058 2059 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2060 if (err) { 2061 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2062 goto free_bfreg; 2063 } 2064 } else { 2065 uar_index = bfregi->sys_pages[idx]; 2066 } 2067 2068 pfn = uar_index2pfn(dev, uar_index); 2069 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2070 2071 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2072 prot); 2073 if (err) { 2074 mlx5_ib_err(dev, 2075 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2076 err, mmap_cmd2str(cmd)); 2077 goto err; 2078 } 2079 2080 if (dyn_uar) 2081 bfregi->sys_pages[idx] = uar_index; 2082 return 0; 2083 2084 err: 2085 if (!dyn_uar) 2086 return err; 2087 2088 mlx5_cmd_free_uar(dev->mdev, idx); 2089 2090 free_bfreg: 2091 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2092 2093 return err; 2094 } 2095 2096 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2097 { 2098 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2099 struct mlx5_ib_dev *dev = to_mdev(context->device); 2100 u16 page_idx = get_extended_index(vma->vm_pgoff); 2101 size_t map_size = vma->vm_end - vma->vm_start; 2102 u32 npages = map_size >> PAGE_SHIFT; 2103 phys_addr_t pfn; 2104 2105 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2106 page_idx + npages) 2107 return -EINVAL; 2108 2109 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2110 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2111 PAGE_SHIFT) + 2112 page_idx; 2113 return rdma_user_mmap_io(context, vma, pfn, map_size, 2114 pgprot_writecombine(vma->vm_page_prot)); 2115 } 2116 2117 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2118 { 2119 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2120 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2121 unsigned long command; 2122 phys_addr_t pfn; 2123 2124 command = get_command(vma->vm_pgoff); 2125 switch (command) { 2126 case MLX5_IB_MMAP_WC_PAGE: 2127 case MLX5_IB_MMAP_NC_PAGE: 2128 case MLX5_IB_MMAP_REGULAR_PAGE: 2129 case MLX5_IB_MMAP_ALLOC_WC: 2130 return uar_mmap(dev, command, vma, context); 2131 2132 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2133 return -ENOSYS; 2134 2135 case MLX5_IB_MMAP_CORE_CLOCK: 2136 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2137 return -EINVAL; 2138 2139 if (vma->vm_flags & VM_WRITE) 2140 return -EPERM; 2141 2142 /* Don't expose to user-space information it shouldn't have */ 2143 if (PAGE_SIZE > 4096) 2144 return -EOPNOTSUPP; 2145 2146 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2147 pfn = (dev->mdev->iseg_base + 2148 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2149 PAGE_SHIFT; 2150 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2151 PAGE_SIZE, vma->vm_page_prot)) 2152 return -EAGAIN; 2153 break; 2154 case MLX5_IB_MMAP_CLOCK_INFO: 2155 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2156 2157 case MLX5_IB_MMAP_DEVICE_MEM: 2158 return dm_mmap(ibcontext, vma); 2159 2160 default: 2161 return -EINVAL; 2162 } 2163 2164 return 0; 2165 } 2166 2167 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2168 struct ib_ucontext *context, 2169 struct ib_dm_alloc_attr *attr, 2170 struct uverbs_attr_bundle *attrs) 2171 { 2172 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2173 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2174 phys_addr_t memic_addr; 2175 struct mlx5_ib_dm *dm; 2176 u64 start_offset; 2177 u32 page_idx; 2178 int err; 2179 2180 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2181 if (!dm) 2182 return ERR_PTR(-ENOMEM); 2183 2184 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2185 attr->length, act_size, attr->alignment); 2186 2187 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2188 act_size, attr->alignment); 2189 if (err) 2190 goto err_free; 2191 2192 start_offset = memic_addr & ~PAGE_MASK; 2193 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2194 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2195 PAGE_SHIFT; 2196 2197 err = uverbs_copy_to(attrs, 2198 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2199 &start_offset, sizeof(start_offset)); 2200 if (err) 2201 goto err_dealloc; 2202 2203 err = uverbs_copy_to(attrs, 2204 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2205 &page_idx, sizeof(page_idx)); 2206 if (err) 2207 goto err_dealloc; 2208 2209 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2210 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2211 2212 dm->dev_addr = memic_addr; 2213 2214 return &dm->ibdm; 2215 2216 err_dealloc: 2217 mlx5_cmd_dealloc_memic(memic, memic_addr, 2218 act_size); 2219 err_free: 2220 kfree(dm); 2221 return ERR_PTR(err); 2222 } 2223 2224 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2225 { 2226 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2227 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2228 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2229 u32 page_idx; 2230 int ret; 2231 2232 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2233 if (ret) 2234 return ret; 2235 2236 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2237 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2238 PAGE_SHIFT; 2239 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2240 page_idx, 2241 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2242 2243 kfree(dm); 2244 2245 return 0; 2246 } 2247 2248 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2249 struct ib_ucontext *context, 2250 struct ib_udata *udata) 2251 { 2252 struct mlx5_ib_alloc_pd_resp resp; 2253 struct mlx5_ib_pd *pd; 2254 int err; 2255 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2256 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2257 u16 uid = 0; 2258 2259 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2260 if (!pd) 2261 return ERR_PTR(-ENOMEM); 2262 2263 uid = context ? to_mucontext(context)->devx_uid : 0; 2264 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2265 MLX5_SET(alloc_pd_in, in, uid, uid); 2266 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in), 2267 out, sizeof(out)); 2268 if (err) { 2269 kfree(pd); 2270 return ERR_PTR(err); 2271 } 2272 2273 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2274 pd->uid = uid; 2275 if (context) { 2276 resp.pdn = pd->pdn; 2277 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2278 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2279 kfree(pd); 2280 return ERR_PTR(-EFAULT); 2281 } 2282 } 2283 2284 return &pd->ibpd; 2285 } 2286 2287 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2288 { 2289 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2290 struct mlx5_ib_pd *mpd = to_mpd(pd); 2291 2292 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2293 kfree(mpd); 2294 2295 return 0; 2296 } 2297 2298 enum { 2299 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2300 MATCH_CRITERIA_ENABLE_MISC_BIT, 2301 MATCH_CRITERIA_ENABLE_INNER_BIT, 2302 MATCH_CRITERIA_ENABLE_MISC2_BIT 2303 }; 2304 2305 #define HEADER_IS_ZERO(match_criteria, headers) \ 2306 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2307 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2308 2309 static u8 get_match_criteria_enable(u32 *match_criteria) 2310 { 2311 u8 match_criteria_enable; 2312 2313 match_criteria_enable = 2314 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2315 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2316 match_criteria_enable |= 2317 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2318 MATCH_CRITERIA_ENABLE_MISC_BIT; 2319 match_criteria_enable |= 2320 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2321 MATCH_CRITERIA_ENABLE_INNER_BIT; 2322 match_criteria_enable |= 2323 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2324 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2325 2326 return match_criteria_enable; 2327 } 2328 2329 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2330 { 2331 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2332 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2333 } 2334 2335 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2336 bool inner) 2337 { 2338 if (inner) { 2339 MLX5_SET(fte_match_set_misc, 2340 misc_c, inner_ipv6_flow_label, mask); 2341 MLX5_SET(fte_match_set_misc, 2342 misc_v, inner_ipv6_flow_label, val); 2343 } else { 2344 MLX5_SET(fte_match_set_misc, 2345 misc_c, outer_ipv6_flow_label, mask); 2346 MLX5_SET(fte_match_set_misc, 2347 misc_v, outer_ipv6_flow_label, val); 2348 } 2349 } 2350 2351 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2352 { 2353 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2354 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2355 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2356 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2357 } 2358 2359 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2360 { 2361 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2362 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2363 return -EOPNOTSUPP; 2364 2365 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2366 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2367 return -EOPNOTSUPP; 2368 2369 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2370 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2371 return -EOPNOTSUPP; 2372 2373 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2374 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2375 return -EOPNOTSUPP; 2376 2377 return 0; 2378 } 2379 2380 #define LAST_ETH_FIELD vlan_tag 2381 #define LAST_IB_FIELD sl 2382 #define LAST_IPV4_FIELD tos 2383 #define LAST_IPV6_FIELD traffic_class 2384 #define LAST_TCP_UDP_FIELD src_port 2385 #define LAST_TUNNEL_FIELD tunnel_id 2386 #define LAST_FLOW_TAG_FIELD tag_id 2387 #define LAST_DROP_FIELD size 2388 #define LAST_COUNTERS_FIELD counters 2389 2390 /* Field is the last supported field */ 2391 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2392 memchr_inv((void *)&filter.field +\ 2393 sizeof(filter.field), 0,\ 2394 sizeof(filter) -\ 2395 offsetof(typeof(filter), field) -\ 2396 sizeof(filter.field)) 2397 2398 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2399 bool is_egress, 2400 struct mlx5_flow_act *action) 2401 { 2402 2403 switch (maction->ib_action.type) { 2404 case IB_FLOW_ACTION_ESP: 2405 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2406 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2407 return -EINVAL; 2408 /* Currently only AES_GCM keymat is supported by the driver */ 2409 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2410 action->action |= is_egress ? 2411 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2412 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2413 return 0; 2414 case IB_FLOW_ACTION_UNSPECIFIED: 2415 if (maction->flow_action_raw.sub_type == 2416 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2417 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2418 return -EINVAL; 2419 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2420 action->modify_id = maction->flow_action_raw.action_id; 2421 return 0; 2422 } 2423 if (maction->flow_action_raw.sub_type == 2424 MLX5_IB_FLOW_ACTION_DECAP) { 2425 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2426 return -EINVAL; 2427 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2428 return 0; 2429 } 2430 if (maction->flow_action_raw.sub_type == 2431 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2432 if (action->action & 2433 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2434 return -EINVAL; 2435 action->action |= 2436 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2437 action->reformat_id = 2438 maction->flow_action_raw.action_id; 2439 return 0; 2440 } 2441 /* fall through */ 2442 default: 2443 return -EOPNOTSUPP; 2444 } 2445 } 2446 2447 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2448 u32 *match_v, const union ib_flow_spec *ib_spec, 2449 const struct ib_flow_attr *flow_attr, 2450 struct mlx5_flow_act *action, u32 prev_type) 2451 { 2452 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2453 misc_parameters); 2454 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2455 misc_parameters); 2456 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2457 misc_parameters_2); 2458 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2459 misc_parameters_2); 2460 void *headers_c; 2461 void *headers_v; 2462 int match_ipv; 2463 int ret; 2464 2465 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2466 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2467 inner_headers); 2468 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2469 inner_headers); 2470 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2471 ft_field_support.inner_ip_version); 2472 } else { 2473 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2474 outer_headers); 2475 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2476 outer_headers); 2477 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2478 ft_field_support.outer_ip_version); 2479 } 2480 2481 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2482 case IB_FLOW_SPEC_ETH: 2483 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2484 return -EOPNOTSUPP; 2485 2486 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2487 dmac_47_16), 2488 ib_spec->eth.mask.dst_mac); 2489 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2490 dmac_47_16), 2491 ib_spec->eth.val.dst_mac); 2492 2493 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2494 smac_47_16), 2495 ib_spec->eth.mask.src_mac); 2496 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2497 smac_47_16), 2498 ib_spec->eth.val.src_mac); 2499 2500 if (ib_spec->eth.mask.vlan_tag) { 2501 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2502 cvlan_tag, 1); 2503 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2504 cvlan_tag, 1); 2505 2506 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2507 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2508 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2509 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2510 2511 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2512 first_cfi, 2513 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2514 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2515 first_cfi, 2516 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2517 2518 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2519 first_prio, 2520 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2521 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2522 first_prio, 2523 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2524 } 2525 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2526 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2527 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2528 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2529 break; 2530 case IB_FLOW_SPEC_IPV4: 2531 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2532 return -EOPNOTSUPP; 2533 2534 if (match_ipv) { 2535 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2536 ip_version, 0xf); 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2538 ip_version, MLX5_FS_IPV4_VERSION); 2539 } else { 2540 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2541 ethertype, 0xffff); 2542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2543 ethertype, ETH_P_IP); 2544 } 2545 2546 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2547 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2548 &ib_spec->ipv4.mask.src_ip, 2549 sizeof(ib_spec->ipv4.mask.src_ip)); 2550 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2551 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2552 &ib_spec->ipv4.val.src_ip, 2553 sizeof(ib_spec->ipv4.val.src_ip)); 2554 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2555 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2556 &ib_spec->ipv4.mask.dst_ip, 2557 sizeof(ib_spec->ipv4.mask.dst_ip)); 2558 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2559 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2560 &ib_spec->ipv4.val.dst_ip, 2561 sizeof(ib_spec->ipv4.val.dst_ip)); 2562 2563 set_tos(headers_c, headers_v, 2564 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2565 2566 set_proto(headers_c, headers_v, 2567 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2568 break; 2569 case IB_FLOW_SPEC_IPV6: 2570 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2571 return -EOPNOTSUPP; 2572 2573 if (match_ipv) { 2574 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2575 ip_version, 0xf); 2576 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2577 ip_version, MLX5_FS_IPV6_VERSION); 2578 } else { 2579 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2580 ethertype, 0xffff); 2581 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2582 ethertype, ETH_P_IPV6); 2583 } 2584 2585 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2586 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2587 &ib_spec->ipv6.mask.src_ip, 2588 sizeof(ib_spec->ipv6.mask.src_ip)); 2589 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2590 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2591 &ib_spec->ipv6.val.src_ip, 2592 sizeof(ib_spec->ipv6.val.src_ip)); 2593 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2594 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2595 &ib_spec->ipv6.mask.dst_ip, 2596 sizeof(ib_spec->ipv6.mask.dst_ip)); 2597 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2598 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2599 &ib_spec->ipv6.val.dst_ip, 2600 sizeof(ib_spec->ipv6.val.dst_ip)); 2601 2602 set_tos(headers_c, headers_v, 2603 ib_spec->ipv6.mask.traffic_class, 2604 ib_spec->ipv6.val.traffic_class); 2605 2606 set_proto(headers_c, headers_v, 2607 ib_spec->ipv6.mask.next_hdr, 2608 ib_spec->ipv6.val.next_hdr); 2609 2610 set_flow_label(misc_params_c, misc_params_v, 2611 ntohl(ib_spec->ipv6.mask.flow_label), 2612 ntohl(ib_spec->ipv6.val.flow_label), 2613 ib_spec->type & IB_FLOW_SPEC_INNER); 2614 break; 2615 case IB_FLOW_SPEC_ESP: 2616 if (ib_spec->esp.mask.seq) 2617 return -EOPNOTSUPP; 2618 2619 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2620 ntohl(ib_spec->esp.mask.spi)); 2621 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2622 ntohl(ib_spec->esp.val.spi)); 2623 break; 2624 case IB_FLOW_SPEC_TCP: 2625 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2626 LAST_TCP_UDP_FIELD)) 2627 return -EOPNOTSUPP; 2628 2629 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2630 0xff); 2631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2632 IPPROTO_TCP); 2633 2634 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2635 ntohs(ib_spec->tcp_udp.mask.src_port)); 2636 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2637 ntohs(ib_spec->tcp_udp.val.src_port)); 2638 2639 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2640 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2641 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2642 ntohs(ib_spec->tcp_udp.val.dst_port)); 2643 break; 2644 case IB_FLOW_SPEC_UDP: 2645 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2646 LAST_TCP_UDP_FIELD)) 2647 return -EOPNOTSUPP; 2648 2649 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2650 0xff); 2651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2652 IPPROTO_UDP); 2653 2654 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2655 ntohs(ib_spec->tcp_udp.mask.src_port)); 2656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2657 ntohs(ib_spec->tcp_udp.val.src_port)); 2658 2659 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2660 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2662 ntohs(ib_spec->tcp_udp.val.dst_port)); 2663 break; 2664 case IB_FLOW_SPEC_GRE: 2665 if (ib_spec->gre.mask.c_ks_res0_ver) 2666 return -EOPNOTSUPP; 2667 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2669 0xff); 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2671 IPPROTO_GRE); 2672 2673 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2674 ntohs(ib_spec->gre.mask.protocol)); 2675 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2676 ntohs(ib_spec->gre.val.protocol)); 2677 2678 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2679 gre_key_h), 2680 &ib_spec->gre.mask.key, 2681 sizeof(ib_spec->gre.mask.key)); 2682 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2683 gre_key_h), 2684 &ib_spec->gre.val.key, 2685 sizeof(ib_spec->gre.val.key)); 2686 break; 2687 case IB_FLOW_SPEC_MPLS: 2688 switch (prev_type) { 2689 case IB_FLOW_SPEC_UDP: 2690 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2691 ft_field_support.outer_first_mpls_over_udp), 2692 &ib_spec->mpls.mask.tag)) 2693 return -EOPNOTSUPP; 2694 2695 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2696 outer_first_mpls_over_udp), 2697 &ib_spec->mpls.val.tag, 2698 sizeof(ib_spec->mpls.val.tag)); 2699 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2700 outer_first_mpls_over_udp), 2701 &ib_spec->mpls.mask.tag, 2702 sizeof(ib_spec->mpls.mask.tag)); 2703 break; 2704 case IB_FLOW_SPEC_GRE: 2705 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2706 ft_field_support.outer_first_mpls_over_gre), 2707 &ib_spec->mpls.mask.tag)) 2708 return -EOPNOTSUPP; 2709 2710 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2711 outer_first_mpls_over_gre), 2712 &ib_spec->mpls.val.tag, 2713 sizeof(ib_spec->mpls.val.tag)); 2714 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2715 outer_first_mpls_over_gre), 2716 &ib_spec->mpls.mask.tag, 2717 sizeof(ib_spec->mpls.mask.tag)); 2718 break; 2719 default: 2720 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2721 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2722 ft_field_support.inner_first_mpls), 2723 &ib_spec->mpls.mask.tag)) 2724 return -EOPNOTSUPP; 2725 2726 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2727 inner_first_mpls), 2728 &ib_spec->mpls.val.tag, 2729 sizeof(ib_spec->mpls.val.tag)); 2730 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2731 inner_first_mpls), 2732 &ib_spec->mpls.mask.tag, 2733 sizeof(ib_spec->mpls.mask.tag)); 2734 } else { 2735 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2736 ft_field_support.outer_first_mpls), 2737 &ib_spec->mpls.mask.tag)) 2738 return -EOPNOTSUPP; 2739 2740 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2741 outer_first_mpls), 2742 &ib_spec->mpls.val.tag, 2743 sizeof(ib_spec->mpls.val.tag)); 2744 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2745 outer_first_mpls), 2746 &ib_spec->mpls.mask.tag, 2747 sizeof(ib_spec->mpls.mask.tag)); 2748 } 2749 } 2750 break; 2751 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2752 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2753 LAST_TUNNEL_FIELD)) 2754 return -EOPNOTSUPP; 2755 2756 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2757 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2758 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2759 ntohl(ib_spec->tunnel.val.tunnel_id)); 2760 break; 2761 case IB_FLOW_SPEC_ACTION_TAG: 2762 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2763 LAST_FLOW_TAG_FIELD)) 2764 return -EOPNOTSUPP; 2765 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2766 return -EINVAL; 2767 2768 action->flow_tag = ib_spec->flow_tag.tag_id; 2769 action->flags |= FLOW_ACT_HAS_TAG; 2770 break; 2771 case IB_FLOW_SPEC_ACTION_DROP: 2772 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2773 LAST_DROP_FIELD)) 2774 return -EOPNOTSUPP; 2775 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2776 break; 2777 case IB_FLOW_SPEC_ACTION_HANDLE: 2778 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 2779 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 2780 if (ret) 2781 return ret; 2782 break; 2783 case IB_FLOW_SPEC_ACTION_COUNT: 2784 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2785 LAST_COUNTERS_FIELD)) 2786 return -EOPNOTSUPP; 2787 2788 /* for now support only one counters spec per flow */ 2789 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2790 return -EINVAL; 2791 2792 action->counters = ib_spec->flow_count.counters; 2793 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2794 break; 2795 default: 2796 return -EINVAL; 2797 } 2798 2799 return 0; 2800 } 2801 2802 /* If a flow could catch both multicast and unicast packets, 2803 * it won't fall into the multicast flow steering table and this rule 2804 * could steal other multicast packets. 2805 */ 2806 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2807 { 2808 union ib_flow_spec *flow_spec; 2809 2810 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2811 ib_attr->num_of_specs < 1) 2812 return false; 2813 2814 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2815 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2816 struct ib_flow_spec_ipv4 *ipv4_spec; 2817 2818 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2819 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2820 return true; 2821 2822 return false; 2823 } 2824 2825 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2826 struct ib_flow_spec_eth *eth_spec; 2827 2828 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2829 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2830 is_multicast_ether_addr(eth_spec->val.dst_mac); 2831 } 2832 2833 return false; 2834 } 2835 2836 enum valid_spec { 2837 VALID_SPEC_INVALID, 2838 VALID_SPEC_VALID, 2839 VALID_SPEC_NA, 2840 }; 2841 2842 static enum valid_spec 2843 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2844 const struct mlx5_flow_spec *spec, 2845 const struct mlx5_flow_act *flow_act, 2846 bool egress) 2847 { 2848 const u32 *match_c = spec->match_criteria; 2849 bool is_crypto = 2850 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2851 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2852 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2853 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2854 2855 /* 2856 * Currently only crypto is supported in egress, when regular egress 2857 * rules would be supported, always return VALID_SPEC_NA. 2858 */ 2859 if (!is_crypto) 2860 return VALID_SPEC_NA; 2861 2862 return is_crypto && is_ipsec && 2863 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ? 2864 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2865 } 2866 2867 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2868 const struct mlx5_flow_spec *spec, 2869 const struct mlx5_flow_act *flow_act, 2870 bool egress) 2871 { 2872 /* We curretly only support ipsec egress flow */ 2873 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2874 } 2875 2876 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2877 const struct ib_flow_attr *flow_attr, 2878 bool check_inner) 2879 { 2880 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2881 int match_ipv = check_inner ? 2882 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2883 ft_field_support.inner_ip_version) : 2884 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2885 ft_field_support.outer_ip_version); 2886 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2887 bool ipv4_spec_valid, ipv6_spec_valid; 2888 unsigned int ip_spec_type = 0; 2889 bool has_ethertype = false; 2890 unsigned int spec_index; 2891 bool mask_valid = true; 2892 u16 eth_type = 0; 2893 bool type_valid; 2894 2895 /* Validate that ethertype is correct */ 2896 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2897 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2898 ib_spec->eth.mask.ether_type) { 2899 mask_valid = (ib_spec->eth.mask.ether_type == 2900 htons(0xffff)); 2901 has_ethertype = true; 2902 eth_type = ntohs(ib_spec->eth.val.ether_type); 2903 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2904 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2905 ip_spec_type = ib_spec->type; 2906 } 2907 ib_spec = (void *)ib_spec + ib_spec->size; 2908 } 2909 2910 type_valid = (!has_ethertype) || (!ip_spec_type); 2911 if (!type_valid && mask_valid) { 2912 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2913 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2914 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2915 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2916 2917 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2918 (((eth_type == ETH_P_MPLS_UC) || 2919 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2920 } 2921 2922 return type_valid; 2923 } 2924 2925 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2926 const struct ib_flow_attr *flow_attr) 2927 { 2928 return is_valid_ethertype(mdev, flow_attr, false) && 2929 is_valid_ethertype(mdev, flow_attr, true); 2930 } 2931 2932 static void put_flow_table(struct mlx5_ib_dev *dev, 2933 struct mlx5_ib_flow_prio *prio, bool ft_added) 2934 { 2935 prio->refcount -= !!ft_added; 2936 if (!prio->refcount) { 2937 mlx5_destroy_flow_table(prio->flow_table); 2938 prio->flow_table = NULL; 2939 } 2940 } 2941 2942 static void counters_clear_description(struct ib_counters *counters) 2943 { 2944 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 2945 2946 mutex_lock(&mcounters->mcntrs_mutex); 2947 kfree(mcounters->counters_data); 2948 mcounters->counters_data = NULL; 2949 mcounters->cntrs_max_index = 0; 2950 mutex_unlock(&mcounters->mcntrs_mutex); 2951 } 2952 2953 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2954 { 2955 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2956 struct mlx5_ib_flow_handler, 2957 ibflow); 2958 struct mlx5_ib_flow_handler *iter, *tmp; 2959 struct mlx5_ib_dev *dev = handler->dev; 2960 2961 mutex_lock(&dev->flow_db->lock); 2962 2963 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2964 mlx5_del_flow_rules(iter->rule); 2965 put_flow_table(dev, iter->prio, true); 2966 list_del(&iter->list); 2967 kfree(iter); 2968 } 2969 2970 mlx5_del_flow_rules(handler->rule); 2971 put_flow_table(dev, handler->prio, true); 2972 if (handler->ibcounters && 2973 atomic_read(&handler->ibcounters->usecnt) == 1) 2974 counters_clear_description(handler->ibcounters); 2975 2976 mutex_unlock(&dev->flow_db->lock); 2977 if (handler->flow_matcher) 2978 atomic_dec(&handler->flow_matcher->usecnt); 2979 kfree(handler); 2980 2981 return 0; 2982 } 2983 2984 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2985 { 2986 priority *= 2; 2987 if (!dont_trap) 2988 priority++; 2989 return priority; 2990 } 2991 2992 enum flow_table_type { 2993 MLX5_IB_FT_RX, 2994 MLX5_IB_FT_TX 2995 }; 2996 2997 #define MLX5_FS_MAX_TYPES 6 2998 #define MLX5_FS_MAX_ENTRIES BIT(16) 2999 3000 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3001 struct mlx5_ib_flow_prio *prio, 3002 int priority, 3003 int num_entries, int num_groups, 3004 u32 flags) 3005 { 3006 struct mlx5_flow_table *ft; 3007 3008 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3009 num_entries, 3010 num_groups, 3011 0, flags); 3012 if (IS_ERR(ft)) 3013 return ERR_CAST(ft); 3014 3015 prio->flow_table = ft; 3016 prio->refcount = 0; 3017 return prio; 3018 } 3019 3020 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3021 struct ib_flow_attr *flow_attr, 3022 enum flow_table_type ft_type) 3023 { 3024 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3025 struct mlx5_flow_namespace *ns = NULL; 3026 struct mlx5_ib_flow_prio *prio; 3027 struct mlx5_flow_table *ft; 3028 int max_table_size; 3029 int num_entries; 3030 int num_groups; 3031 u32 flags = 0; 3032 int priority; 3033 3034 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3035 log_max_ft_size)); 3036 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3037 enum mlx5_flow_namespace_type fn_type; 3038 3039 if (flow_is_multicast_only(flow_attr) && 3040 !dont_trap) 3041 priority = MLX5_IB_FLOW_MCAST_PRIO; 3042 else 3043 priority = ib_prio_to_core_prio(flow_attr->priority, 3044 dont_trap); 3045 if (ft_type == MLX5_IB_FT_RX) { 3046 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3047 prio = &dev->flow_db->prios[priority]; 3048 if (!dev->rep && 3049 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3050 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3051 if (!dev->rep && 3052 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3053 reformat_l3_tunnel_to_l2)) 3054 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3055 } else { 3056 max_table_size = 3057 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3058 log_max_ft_size)); 3059 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3060 prio = &dev->flow_db->egress_prios[priority]; 3061 if (!dev->rep && 3062 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3063 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3064 } 3065 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3066 num_entries = MLX5_FS_MAX_ENTRIES; 3067 num_groups = MLX5_FS_MAX_TYPES; 3068 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3069 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3070 ns = mlx5_get_flow_namespace(dev->mdev, 3071 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3072 build_leftovers_ft_param(&priority, 3073 &num_entries, 3074 &num_groups); 3075 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3076 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3077 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3078 allow_sniffer_and_nic_rx_shared_tir)) 3079 return ERR_PTR(-ENOTSUPP); 3080 3081 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3082 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3083 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3084 3085 prio = &dev->flow_db->sniffer[ft_type]; 3086 priority = 0; 3087 num_entries = 1; 3088 num_groups = 1; 3089 } 3090 3091 if (!ns) 3092 return ERR_PTR(-ENOTSUPP); 3093 3094 if (num_entries > max_table_size) 3095 return ERR_PTR(-ENOMEM); 3096 3097 ft = prio->flow_table; 3098 if (!ft) 3099 return _get_prio(ns, prio, priority, num_entries, num_groups, 3100 flags); 3101 3102 return prio; 3103 } 3104 3105 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3106 struct mlx5_flow_spec *spec, 3107 u32 underlay_qpn) 3108 { 3109 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3110 spec->match_criteria, 3111 misc_parameters); 3112 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3113 misc_parameters); 3114 3115 if (underlay_qpn && 3116 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3117 ft_field_support.bth_dst_qp)) { 3118 MLX5_SET(fte_match_set_misc, 3119 misc_params_v, bth_dst_qp, underlay_qpn); 3120 MLX5_SET(fte_match_set_misc, 3121 misc_params_c, bth_dst_qp, 0xffffff); 3122 } 3123 } 3124 3125 static int read_flow_counters(struct ib_device *ibdev, 3126 struct mlx5_read_counters_attr *read_attr) 3127 { 3128 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3129 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3130 3131 return mlx5_fc_query(dev->mdev, fc, 3132 &read_attr->out[IB_COUNTER_PACKETS], 3133 &read_attr->out[IB_COUNTER_BYTES]); 3134 } 3135 3136 /* flow counters currently expose two counters packets and bytes */ 3137 #define FLOW_COUNTERS_NUM 2 3138 static int counters_set_description(struct ib_counters *counters, 3139 enum mlx5_ib_counters_type counters_type, 3140 struct mlx5_ib_flow_counters_desc *desc_data, 3141 u32 ncounters) 3142 { 3143 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3144 u32 cntrs_max_index = 0; 3145 int i; 3146 3147 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3148 return -EINVAL; 3149 3150 /* init the fields for the object */ 3151 mcounters->type = counters_type; 3152 mcounters->read_counters = read_flow_counters; 3153 mcounters->counters_num = FLOW_COUNTERS_NUM; 3154 mcounters->ncounters = ncounters; 3155 /* each counter entry have both description and index pair */ 3156 for (i = 0; i < ncounters; i++) { 3157 if (desc_data[i].description > IB_COUNTER_BYTES) 3158 return -EINVAL; 3159 3160 if (cntrs_max_index <= desc_data[i].index) 3161 cntrs_max_index = desc_data[i].index + 1; 3162 } 3163 3164 mutex_lock(&mcounters->mcntrs_mutex); 3165 mcounters->counters_data = desc_data; 3166 mcounters->cntrs_max_index = cntrs_max_index; 3167 mutex_unlock(&mcounters->mcntrs_mutex); 3168 3169 return 0; 3170 } 3171 3172 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3173 static int flow_counters_set_data(struct ib_counters *ibcounters, 3174 struct mlx5_ib_create_flow *ucmd) 3175 { 3176 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3177 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3178 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3179 bool hw_hndl = false; 3180 int ret = 0; 3181 3182 if (ucmd && ucmd->ncounters_data != 0) { 3183 cntrs_data = ucmd->data; 3184 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3185 return -EINVAL; 3186 3187 desc_data = kcalloc(cntrs_data->ncounters, 3188 sizeof(*desc_data), 3189 GFP_KERNEL); 3190 if (!desc_data) 3191 return -ENOMEM; 3192 3193 if (copy_from_user(desc_data, 3194 u64_to_user_ptr(cntrs_data->counters_data), 3195 sizeof(*desc_data) * cntrs_data->ncounters)) { 3196 ret = -EFAULT; 3197 goto free; 3198 } 3199 } 3200 3201 if (!mcounters->hw_cntrs_hndl) { 3202 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3203 to_mdev(ibcounters->device)->mdev, false); 3204 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3205 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3206 goto free; 3207 } 3208 hw_hndl = true; 3209 } 3210 3211 if (desc_data) { 3212 /* counters already bound to at least one flow */ 3213 if (mcounters->cntrs_max_index) { 3214 ret = -EINVAL; 3215 goto free_hndl; 3216 } 3217 3218 ret = counters_set_description(ibcounters, 3219 MLX5_IB_COUNTERS_FLOW, 3220 desc_data, 3221 cntrs_data->ncounters); 3222 if (ret) 3223 goto free_hndl; 3224 3225 } else if (!mcounters->cntrs_max_index) { 3226 /* counters not bound yet, must have udata passed */ 3227 ret = -EINVAL; 3228 goto free_hndl; 3229 } 3230 3231 return 0; 3232 3233 free_hndl: 3234 if (hw_hndl) { 3235 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3236 mcounters->hw_cntrs_hndl); 3237 mcounters->hw_cntrs_hndl = NULL; 3238 } 3239 free: 3240 kfree(desc_data); 3241 return ret; 3242 } 3243 3244 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3245 struct mlx5_ib_flow_prio *ft_prio, 3246 const struct ib_flow_attr *flow_attr, 3247 struct mlx5_flow_destination *dst, 3248 u32 underlay_qpn, 3249 struct mlx5_ib_create_flow *ucmd) 3250 { 3251 struct mlx5_flow_table *ft = ft_prio->flow_table; 3252 struct mlx5_ib_flow_handler *handler; 3253 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3254 struct mlx5_flow_spec *spec; 3255 struct mlx5_flow_destination dest_arr[2] = {}; 3256 struct mlx5_flow_destination *rule_dst = dest_arr; 3257 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3258 unsigned int spec_index; 3259 u32 prev_type = 0; 3260 int err = 0; 3261 int dest_num = 0; 3262 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3263 3264 if (!is_valid_attr(dev->mdev, flow_attr)) 3265 return ERR_PTR(-EINVAL); 3266 3267 if (dev->rep && is_egress) 3268 return ERR_PTR(-EINVAL); 3269 3270 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3271 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3272 if (!handler || !spec) { 3273 err = -ENOMEM; 3274 goto free; 3275 } 3276 3277 INIT_LIST_HEAD(&handler->list); 3278 if (dst) { 3279 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3280 dest_num++; 3281 } 3282 3283 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3284 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3285 spec->match_value, 3286 ib_flow, flow_attr, &flow_act, 3287 prev_type); 3288 if (err < 0) 3289 goto free; 3290 3291 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3292 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3293 } 3294 3295 if (!flow_is_multicast_only(flow_attr)) 3296 set_underlay_qp(dev, spec, underlay_qpn); 3297 3298 if (dev->rep) { 3299 void *misc; 3300 3301 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3302 misc_parameters); 3303 MLX5_SET(fte_match_set_misc, misc, source_port, 3304 dev->rep->vport); 3305 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3306 misc_parameters); 3307 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3308 } 3309 3310 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3311 3312 if (is_egress && 3313 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3314 err = -EINVAL; 3315 goto free; 3316 } 3317 3318 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3319 struct mlx5_ib_mcounters *mcounters; 3320 3321 err = flow_counters_set_data(flow_act.counters, ucmd); 3322 if (err) 3323 goto free; 3324 3325 mcounters = to_mcounters(flow_act.counters); 3326 handler->ibcounters = flow_act.counters; 3327 dest_arr[dest_num].type = 3328 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3329 dest_arr[dest_num].counter_id = 3330 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3331 dest_num++; 3332 } 3333 3334 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3335 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3336 rule_dst = NULL; 3337 dest_num = 0; 3338 } 3339 } else { 3340 if (is_egress) 3341 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3342 else 3343 flow_act.action |= 3344 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3345 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3346 } 3347 3348 if ((flow_act.flags & FLOW_ACT_HAS_TAG) && 3349 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3350 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3351 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3352 flow_act.flow_tag, flow_attr->type); 3353 err = -EINVAL; 3354 goto free; 3355 } 3356 handler->rule = mlx5_add_flow_rules(ft, spec, 3357 &flow_act, 3358 rule_dst, dest_num); 3359 3360 if (IS_ERR(handler->rule)) { 3361 err = PTR_ERR(handler->rule); 3362 goto free; 3363 } 3364 3365 ft_prio->refcount++; 3366 handler->prio = ft_prio; 3367 handler->dev = dev; 3368 3369 ft_prio->flow_table = ft; 3370 free: 3371 if (err && handler) { 3372 if (handler->ibcounters && 3373 atomic_read(&handler->ibcounters->usecnt) == 1) 3374 counters_clear_description(handler->ibcounters); 3375 kfree(handler); 3376 } 3377 kvfree(spec); 3378 return err ? ERR_PTR(err) : handler; 3379 } 3380 3381 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3382 struct mlx5_ib_flow_prio *ft_prio, 3383 const struct ib_flow_attr *flow_attr, 3384 struct mlx5_flow_destination *dst) 3385 { 3386 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3387 } 3388 3389 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3390 struct mlx5_ib_flow_prio *ft_prio, 3391 struct ib_flow_attr *flow_attr, 3392 struct mlx5_flow_destination *dst) 3393 { 3394 struct mlx5_ib_flow_handler *handler_dst = NULL; 3395 struct mlx5_ib_flow_handler *handler = NULL; 3396 3397 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3398 if (!IS_ERR(handler)) { 3399 handler_dst = create_flow_rule(dev, ft_prio, 3400 flow_attr, dst); 3401 if (IS_ERR(handler_dst)) { 3402 mlx5_del_flow_rules(handler->rule); 3403 ft_prio->refcount--; 3404 kfree(handler); 3405 handler = handler_dst; 3406 } else { 3407 list_add(&handler_dst->list, &handler->list); 3408 } 3409 } 3410 3411 return handler; 3412 } 3413 enum { 3414 LEFTOVERS_MC, 3415 LEFTOVERS_UC, 3416 }; 3417 3418 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3419 struct mlx5_ib_flow_prio *ft_prio, 3420 struct ib_flow_attr *flow_attr, 3421 struct mlx5_flow_destination *dst) 3422 { 3423 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3424 struct mlx5_ib_flow_handler *handler = NULL; 3425 3426 static struct { 3427 struct ib_flow_attr flow_attr; 3428 struct ib_flow_spec_eth eth_flow; 3429 } leftovers_specs[] = { 3430 [LEFTOVERS_MC] = { 3431 .flow_attr = { 3432 .num_of_specs = 1, 3433 .size = sizeof(leftovers_specs[0]) 3434 }, 3435 .eth_flow = { 3436 .type = IB_FLOW_SPEC_ETH, 3437 .size = sizeof(struct ib_flow_spec_eth), 3438 .mask = {.dst_mac = {0x1} }, 3439 .val = {.dst_mac = {0x1} } 3440 } 3441 }, 3442 [LEFTOVERS_UC] = { 3443 .flow_attr = { 3444 .num_of_specs = 1, 3445 .size = sizeof(leftovers_specs[0]) 3446 }, 3447 .eth_flow = { 3448 .type = IB_FLOW_SPEC_ETH, 3449 .size = sizeof(struct ib_flow_spec_eth), 3450 .mask = {.dst_mac = {0x1} }, 3451 .val = {.dst_mac = {} } 3452 } 3453 } 3454 }; 3455 3456 handler = create_flow_rule(dev, ft_prio, 3457 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3458 dst); 3459 if (!IS_ERR(handler) && 3460 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3461 handler_ucast = create_flow_rule(dev, ft_prio, 3462 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3463 dst); 3464 if (IS_ERR(handler_ucast)) { 3465 mlx5_del_flow_rules(handler->rule); 3466 ft_prio->refcount--; 3467 kfree(handler); 3468 handler = handler_ucast; 3469 } else { 3470 list_add(&handler_ucast->list, &handler->list); 3471 } 3472 } 3473 3474 return handler; 3475 } 3476 3477 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3478 struct mlx5_ib_flow_prio *ft_rx, 3479 struct mlx5_ib_flow_prio *ft_tx, 3480 struct mlx5_flow_destination *dst) 3481 { 3482 struct mlx5_ib_flow_handler *handler_rx; 3483 struct mlx5_ib_flow_handler *handler_tx; 3484 int err; 3485 static const struct ib_flow_attr flow_attr = { 3486 .num_of_specs = 0, 3487 .size = sizeof(flow_attr) 3488 }; 3489 3490 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3491 if (IS_ERR(handler_rx)) { 3492 err = PTR_ERR(handler_rx); 3493 goto err; 3494 } 3495 3496 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3497 if (IS_ERR(handler_tx)) { 3498 err = PTR_ERR(handler_tx); 3499 goto err_tx; 3500 } 3501 3502 list_add(&handler_tx->list, &handler_rx->list); 3503 3504 return handler_rx; 3505 3506 err_tx: 3507 mlx5_del_flow_rules(handler_rx->rule); 3508 ft_rx->refcount--; 3509 kfree(handler_rx); 3510 err: 3511 return ERR_PTR(err); 3512 } 3513 3514 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3515 struct ib_flow_attr *flow_attr, 3516 int domain, 3517 struct ib_udata *udata) 3518 { 3519 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3520 struct mlx5_ib_qp *mqp = to_mqp(qp); 3521 struct mlx5_ib_flow_handler *handler = NULL; 3522 struct mlx5_flow_destination *dst = NULL; 3523 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3524 struct mlx5_ib_flow_prio *ft_prio; 3525 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3526 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3527 size_t min_ucmd_sz, required_ucmd_sz; 3528 int err; 3529 int underlay_qpn; 3530 3531 if (udata && udata->inlen) { 3532 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3533 sizeof(ucmd_hdr.reserved); 3534 if (udata->inlen < min_ucmd_sz) 3535 return ERR_PTR(-EOPNOTSUPP); 3536 3537 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3538 if (err) 3539 return ERR_PTR(err); 3540 3541 /* currently supports only one counters data */ 3542 if (ucmd_hdr.ncounters_data > 1) 3543 return ERR_PTR(-EINVAL); 3544 3545 required_ucmd_sz = min_ucmd_sz + 3546 sizeof(struct mlx5_ib_flow_counters_data) * 3547 ucmd_hdr.ncounters_data; 3548 if (udata->inlen > required_ucmd_sz && 3549 !ib_is_udata_cleared(udata, required_ucmd_sz, 3550 udata->inlen - required_ucmd_sz)) 3551 return ERR_PTR(-EOPNOTSUPP); 3552 3553 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3554 if (!ucmd) 3555 return ERR_PTR(-ENOMEM); 3556 3557 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3558 if (err) 3559 goto free_ucmd; 3560 } 3561 3562 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3563 err = -ENOMEM; 3564 goto free_ucmd; 3565 } 3566 3567 if (domain != IB_FLOW_DOMAIN_USER || 3568 flow_attr->port > dev->num_ports || 3569 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3570 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3571 err = -EINVAL; 3572 goto free_ucmd; 3573 } 3574 3575 if (is_egress && 3576 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3577 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3578 err = -EINVAL; 3579 goto free_ucmd; 3580 } 3581 3582 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3583 if (!dst) { 3584 err = -ENOMEM; 3585 goto free_ucmd; 3586 } 3587 3588 mutex_lock(&dev->flow_db->lock); 3589 3590 ft_prio = get_flow_table(dev, flow_attr, 3591 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3592 if (IS_ERR(ft_prio)) { 3593 err = PTR_ERR(ft_prio); 3594 goto unlock; 3595 } 3596 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3597 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3598 if (IS_ERR(ft_prio_tx)) { 3599 err = PTR_ERR(ft_prio_tx); 3600 ft_prio_tx = NULL; 3601 goto destroy_ft; 3602 } 3603 } 3604 3605 if (is_egress) { 3606 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3607 } else { 3608 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3609 if (mqp->flags & MLX5_IB_QP_RSS) 3610 dst->tir_num = mqp->rss_qp.tirn; 3611 else 3612 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3613 } 3614 3615 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3616 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3617 handler = create_dont_trap_rule(dev, ft_prio, 3618 flow_attr, dst); 3619 } else { 3620 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3621 mqp->underlay_qpn : 0; 3622 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3623 dst, underlay_qpn, ucmd); 3624 } 3625 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3626 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3627 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3628 dst); 3629 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3630 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3631 } else { 3632 err = -EINVAL; 3633 goto destroy_ft; 3634 } 3635 3636 if (IS_ERR(handler)) { 3637 err = PTR_ERR(handler); 3638 handler = NULL; 3639 goto destroy_ft; 3640 } 3641 3642 mutex_unlock(&dev->flow_db->lock); 3643 kfree(dst); 3644 kfree(ucmd); 3645 3646 return &handler->ibflow; 3647 3648 destroy_ft: 3649 put_flow_table(dev, ft_prio, false); 3650 if (ft_prio_tx) 3651 put_flow_table(dev, ft_prio_tx, false); 3652 unlock: 3653 mutex_unlock(&dev->flow_db->lock); 3654 kfree(dst); 3655 free_ucmd: 3656 kfree(ucmd); 3657 return ERR_PTR(err); 3658 } 3659 3660 static struct mlx5_ib_flow_prio * 3661 _get_flow_table(struct mlx5_ib_dev *dev, 3662 struct mlx5_ib_flow_matcher *fs_matcher, 3663 bool mcast) 3664 { 3665 struct mlx5_flow_namespace *ns = NULL; 3666 struct mlx5_ib_flow_prio *prio; 3667 int max_table_size; 3668 u32 flags = 0; 3669 int priority; 3670 3671 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3672 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3673 log_max_ft_size)); 3674 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3675 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3676 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3677 reformat_l3_tunnel_to_l2)) 3678 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3679 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */ 3680 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3681 log_max_ft_size)); 3682 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3683 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3684 } 3685 3686 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3687 return ERR_PTR(-ENOMEM); 3688 3689 if (mcast) 3690 priority = MLX5_IB_FLOW_MCAST_PRIO; 3691 else 3692 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3693 3694 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3695 if (!ns) 3696 return ERR_PTR(-ENOTSUPP); 3697 3698 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3699 prio = &dev->flow_db->prios[priority]; 3700 else 3701 prio = &dev->flow_db->egress_prios[priority]; 3702 3703 if (prio->flow_table) 3704 return prio; 3705 3706 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3707 MLX5_FS_MAX_TYPES, flags); 3708 } 3709 3710 static struct mlx5_ib_flow_handler * 3711 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3712 struct mlx5_ib_flow_prio *ft_prio, 3713 struct mlx5_flow_destination *dst, 3714 struct mlx5_ib_flow_matcher *fs_matcher, 3715 struct mlx5_flow_act *flow_act, 3716 void *cmd_in, int inlen) 3717 { 3718 struct mlx5_ib_flow_handler *handler; 3719 struct mlx5_flow_spec *spec; 3720 struct mlx5_flow_table *ft = ft_prio->flow_table; 3721 int err = 0; 3722 3723 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3724 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3725 if (!handler || !spec) { 3726 err = -ENOMEM; 3727 goto free; 3728 } 3729 3730 INIT_LIST_HEAD(&handler->list); 3731 3732 memcpy(spec->match_value, cmd_in, inlen); 3733 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3734 fs_matcher->mask_len); 3735 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3736 3737 handler->rule = mlx5_add_flow_rules(ft, spec, 3738 flow_act, dst, 1); 3739 3740 if (IS_ERR(handler->rule)) { 3741 err = PTR_ERR(handler->rule); 3742 goto free; 3743 } 3744 3745 ft_prio->refcount++; 3746 handler->prio = ft_prio; 3747 handler->dev = dev; 3748 ft_prio->flow_table = ft; 3749 3750 free: 3751 if (err) 3752 kfree(handler); 3753 kvfree(spec); 3754 return err ? ERR_PTR(err) : handler; 3755 } 3756 3757 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3758 void *match_v) 3759 { 3760 void *match_c; 3761 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3762 void *dmac, *dmac_mask; 3763 void *ipv4, *ipv4_mask; 3764 3765 if (!(fs_matcher->match_criteria_enable & 3766 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3767 return false; 3768 3769 match_c = fs_matcher->matcher_mask.match_params; 3770 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3771 outer_headers); 3772 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3773 outer_headers); 3774 3775 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3776 dmac_47_16); 3777 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3778 dmac_47_16); 3779 3780 if (is_multicast_ether_addr(dmac) && 3781 is_multicast_ether_addr(dmac_mask)) 3782 return true; 3783 3784 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3785 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3786 3787 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3788 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3789 3790 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3791 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3792 return true; 3793 3794 return false; 3795 } 3796 3797 struct mlx5_ib_flow_handler * 3798 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3799 struct mlx5_ib_flow_matcher *fs_matcher, 3800 struct mlx5_flow_act *flow_act, 3801 void *cmd_in, int inlen, int dest_id, 3802 int dest_type) 3803 { 3804 struct mlx5_flow_destination *dst; 3805 struct mlx5_ib_flow_prio *ft_prio; 3806 struct mlx5_ib_flow_handler *handler; 3807 bool mcast; 3808 int err; 3809 3810 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3811 return ERR_PTR(-EOPNOTSUPP); 3812 3813 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3814 return ERR_PTR(-ENOMEM); 3815 3816 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3817 if (!dst) 3818 return ERR_PTR(-ENOMEM); 3819 3820 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3821 mutex_lock(&dev->flow_db->lock); 3822 3823 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 3824 if (IS_ERR(ft_prio)) { 3825 err = PTR_ERR(ft_prio); 3826 goto unlock; 3827 } 3828 3829 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3830 dst->type = dest_type; 3831 dst->tir_num = dest_id; 3832 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3833 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 3834 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3835 dst->ft_num = dest_id; 3836 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3837 } else { 3838 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3839 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3840 } 3841 3842 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 3843 cmd_in, inlen); 3844 3845 if (IS_ERR(handler)) { 3846 err = PTR_ERR(handler); 3847 goto destroy_ft; 3848 } 3849 3850 mutex_unlock(&dev->flow_db->lock); 3851 atomic_inc(&fs_matcher->usecnt); 3852 handler->flow_matcher = fs_matcher; 3853 3854 kfree(dst); 3855 3856 return handler; 3857 3858 destroy_ft: 3859 put_flow_table(dev, ft_prio, false); 3860 unlock: 3861 mutex_unlock(&dev->flow_db->lock); 3862 kfree(dst); 3863 3864 return ERR_PTR(err); 3865 } 3866 3867 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3868 { 3869 u32 flags = 0; 3870 3871 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3872 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3873 3874 return flags; 3875 } 3876 3877 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3878 static struct ib_flow_action * 3879 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3880 const struct ib_flow_action_attrs_esp *attr, 3881 struct uverbs_attr_bundle *attrs) 3882 { 3883 struct mlx5_ib_dev *mdev = to_mdev(device); 3884 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3885 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3886 struct mlx5_ib_flow_action *action; 3887 u64 action_flags; 3888 u64 flags; 3889 int err = 0; 3890 3891 err = uverbs_get_flags64( 3892 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3893 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 3894 if (err) 3895 return ERR_PTR(err); 3896 3897 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3898 3899 /* We current only support a subset of the standard features. Only a 3900 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3901 * (with overlap). Full offload mode isn't supported. 3902 */ 3903 if (!attr->keymat || attr->replay || attr->encap || 3904 attr->spi || attr->seq || attr->tfc_pad || 3905 attr->hard_limit_pkts || 3906 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3907 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3908 return ERR_PTR(-EOPNOTSUPP); 3909 3910 if (attr->keymat->protocol != 3911 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3912 return ERR_PTR(-EOPNOTSUPP); 3913 3914 aes_gcm = &attr->keymat->keymat.aes_gcm; 3915 3916 if (aes_gcm->icv_len != 16 || 3917 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3918 return ERR_PTR(-EOPNOTSUPP); 3919 3920 action = kmalloc(sizeof(*action), GFP_KERNEL); 3921 if (!action) 3922 return ERR_PTR(-ENOMEM); 3923 3924 action->esp_aes_gcm.ib_flags = attr->flags; 3925 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3926 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3927 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3928 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3929 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3930 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3931 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3932 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3933 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3934 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3935 3936 accel_attrs.esn = attr->esn; 3937 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3938 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3939 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3940 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3941 3942 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3943 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3944 3945 action->esp_aes_gcm.ctx = 3946 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3947 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3948 err = PTR_ERR(action->esp_aes_gcm.ctx); 3949 goto err_parse; 3950 } 3951 3952 action->esp_aes_gcm.ib_flags = attr->flags; 3953 3954 return &action->ib_action; 3955 3956 err_parse: 3957 kfree(action); 3958 return ERR_PTR(err); 3959 } 3960 3961 static int 3962 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3963 const struct ib_flow_action_attrs_esp *attr, 3964 struct uverbs_attr_bundle *attrs) 3965 { 3966 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3967 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3968 int err = 0; 3969 3970 if (attr->keymat || attr->replay || attr->encap || 3971 attr->spi || attr->seq || attr->tfc_pad || 3972 attr->hard_limit_pkts || 3973 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3974 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3975 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3976 return -EOPNOTSUPP; 3977 3978 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3979 * be modified. 3980 */ 3981 if (!(maction->esp_aes_gcm.ib_flags & 3982 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3983 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3984 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3985 return -EINVAL; 3986 3987 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3988 sizeof(accel_attrs)); 3989 3990 accel_attrs.esn = attr->esn; 3991 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3992 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3993 else 3994 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3995 3996 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3997 &accel_attrs); 3998 if (err) 3999 return err; 4000 4001 maction->esp_aes_gcm.ib_flags &= 4002 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4003 maction->esp_aes_gcm.ib_flags |= 4004 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4005 4006 return 0; 4007 } 4008 4009 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4010 { 4011 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4012 4013 switch (action->type) { 4014 case IB_FLOW_ACTION_ESP: 4015 /* 4016 * We only support aes_gcm by now, so we implicitly know this is 4017 * the underline crypto. 4018 */ 4019 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4020 break; 4021 case IB_FLOW_ACTION_UNSPECIFIED: 4022 mlx5_ib_destroy_flow_action_raw(maction); 4023 break; 4024 default: 4025 WARN_ON(true); 4026 break; 4027 } 4028 4029 kfree(maction); 4030 return 0; 4031 } 4032 4033 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4034 { 4035 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4036 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4037 int err; 4038 u16 uid; 4039 4040 uid = ibqp->pd ? 4041 to_mpd(ibqp->pd)->uid : 0; 4042 4043 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4044 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4045 return -EOPNOTSUPP; 4046 } 4047 4048 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4049 if (err) 4050 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4051 ibqp->qp_num, gid->raw); 4052 4053 return err; 4054 } 4055 4056 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4057 { 4058 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4059 int err; 4060 u16 uid; 4061 4062 uid = ibqp->pd ? 4063 to_mpd(ibqp->pd)->uid : 0; 4064 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4065 if (err) 4066 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4067 ibqp->qp_num, gid->raw); 4068 4069 return err; 4070 } 4071 4072 static int init_node_data(struct mlx5_ib_dev *dev) 4073 { 4074 int err; 4075 4076 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4077 if (err) 4078 return err; 4079 4080 dev->mdev->rev_id = dev->mdev->pdev->revision; 4081 4082 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4083 } 4084 4085 static ssize_t fw_pages_show(struct device *device, 4086 struct device_attribute *attr, char *buf) 4087 { 4088 struct mlx5_ib_dev *dev = 4089 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4090 4091 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4092 } 4093 static DEVICE_ATTR_RO(fw_pages); 4094 4095 static ssize_t reg_pages_show(struct device *device, 4096 struct device_attribute *attr, char *buf) 4097 { 4098 struct mlx5_ib_dev *dev = 4099 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4100 4101 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4102 } 4103 static DEVICE_ATTR_RO(reg_pages); 4104 4105 static ssize_t hca_type_show(struct device *device, 4106 struct device_attribute *attr, char *buf) 4107 { 4108 struct mlx5_ib_dev *dev = 4109 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4110 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4111 } 4112 static DEVICE_ATTR_RO(hca_type); 4113 4114 static ssize_t hw_rev_show(struct device *device, 4115 struct device_attribute *attr, char *buf) 4116 { 4117 struct mlx5_ib_dev *dev = 4118 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4119 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4120 } 4121 static DEVICE_ATTR_RO(hw_rev); 4122 4123 static ssize_t board_id_show(struct device *device, 4124 struct device_attribute *attr, char *buf) 4125 { 4126 struct mlx5_ib_dev *dev = 4127 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4128 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4129 dev->mdev->board_id); 4130 } 4131 static DEVICE_ATTR_RO(board_id); 4132 4133 static struct attribute *mlx5_class_attributes[] = { 4134 &dev_attr_hw_rev.attr, 4135 &dev_attr_hca_type.attr, 4136 &dev_attr_board_id.attr, 4137 &dev_attr_fw_pages.attr, 4138 &dev_attr_reg_pages.attr, 4139 NULL, 4140 }; 4141 4142 static const struct attribute_group mlx5_attr_group = { 4143 .attrs = mlx5_class_attributes, 4144 }; 4145 4146 static void pkey_change_handler(struct work_struct *work) 4147 { 4148 struct mlx5_ib_port_resources *ports = 4149 container_of(work, struct mlx5_ib_port_resources, 4150 pkey_change_work); 4151 4152 mutex_lock(&ports->devr->mutex); 4153 mlx5_ib_gsi_pkey_change(ports->gsi); 4154 mutex_unlock(&ports->devr->mutex); 4155 } 4156 4157 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4158 { 4159 struct mlx5_ib_qp *mqp; 4160 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4161 struct mlx5_core_cq *mcq; 4162 struct list_head cq_armed_list; 4163 unsigned long flags_qp; 4164 unsigned long flags_cq; 4165 unsigned long flags; 4166 4167 INIT_LIST_HEAD(&cq_armed_list); 4168 4169 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4170 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4171 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4172 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4173 if (mqp->sq.tail != mqp->sq.head) { 4174 send_mcq = to_mcq(mqp->ibqp.send_cq); 4175 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4176 if (send_mcq->mcq.comp && 4177 mqp->ibqp.send_cq->comp_handler) { 4178 if (!send_mcq->mcq.reset_notify_added) { 4179 send_mcq->mcq.reset_notify_added = 1; 4180 list_add_tail(&send_mcq->mcq.reset_notify, 4181 &cq_armed_list); 4182 } 4183 } 4184 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4185 } 4186 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4187 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4188 /* no handling is needed for SRQ */ 4189 if (!mqp->ibqp.srq) { 4190 if (mqp->rq.tail != mqp->rq.head) { 4191 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4192 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4193 if (recv_mcq->mcq.comp && 4194 mqp->ibqp.recv_cq->comp_handler) { 4195 if (!recv_mcq->mcq.reset_notify_added) { 4196 recv_mcq->mcq.reset_notify_added = 1; 4197 list_add_tail(&recv_mcq->mcq.reset_notify, 4198 &cq_armed_list); 4199 } 4200 } 4201 spin_unlock_irqrestore(&recv_mcq->lock, 4202 flags_cq); 4203 } 4204 } 4205 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4206 } 4207 /*At that point all inflight post send were put to be executed as of we 4208 * lock/unlock above locks Now need to arm all involved CQs. 4209 */ 4210 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4211 mcq->comp(mcq); 4212 } 4213 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4214 } 4215 4216 static void delay_drop_handler(struct work_struct *work) 4217 { 4218 int err; 4219 struct mlx5_ib_delay_drop *delay_drop = 4220 container_of(work, struct mlx5_ib_delay_drop, 4221 delay_drop_work); 4222 4223 atomic_inc(&delay_drop->events_cnt); 4224 4225 mutex_lock(&delay_drop->lock); 4226 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4227 delay_drop->timeout); 4228 if (err) { 4229 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4230 delay_drop->timeout); 4231 delay_drop->activate = false; 4232 } 4233 mutex_unlock(&delay_drop->lock); 4234 } 4235 4236 static void mlx5_ib_handle_event(struct work_struct *_work) 4237 { 4238 struct mlx5_ib_event_work *work = 4239 container_of(_work, struct mlx5_ib_event_work, work); 4240 struct mlx5_ib_dev *ibdev; 4241 struct ib_event ibev; 4242 bool fatal = false; 4243 u8 port = (u8)work->param; 4244 4245 if (mlx5_core_is_mp_slave(work->dev)) { 4246 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 4247 if (!ibdev) 4248 goto out; 4249 } else { 4250 ibdev = work->context; 4251 } 4252 4253 switch (work->event) { 4254 case MLX5_DEV_EVENT_SYS_ERROR: 4255 ibev.event = IB_EVENT_DEVICE_FATAL; 4256 mlx5_ib_handle_internal_error(ibdev); 4257 fatal = true; 4258 break; 4259 4260 case MLX5_DEV_EVENT_PORT_UP: 4261 case MLX5_DEV_EVENT_PORT_DOWN: 4262 case MLX5_DEV_EVENT_PORT_INITIALIZED: 4263 /* In RoCE, port up/down events are handled in 4264 * mlx5_netdev_event(). 4265 */ 4266 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4267 IB_LINK_LAYER_ETHERNET) 4268 goto out; 4269 4270 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 4271 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4272 break; 4273 4274 case MLX5_DEV_EVENT_LID_CHANGE: 4275 ibev.event = IB_EVENT_LID_CHANGE; 4276 break; 4277 4278 case MLX5_DEV_EVENT_PKEY_CHANGE: 4279 ibev.event = IB_EVENT_PKEY_CHANGE; 4280 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4281 break; 4282 4283 case MLX5_DEV_EVENT_GUID_CHANGE: 4284 ibev.event = IB_EVENT_GID_CHANGE; 4285 break; 4286 4287 case MLX5_DEV_EVENT_CLIENT_REREG: 4288 ibev.event = IB_EVENT_CLIENT_REREGISTER; 4289 break; 4290 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 4291 schedule_work(&ibdev->delay_drop.delay_drop_work); 4292 goto out; 4293 default: 4294 goto out; 4295 } 4296 4297 ibev.device = &ibdev->ib_dev; 4298 ibev.element.port_num = port; 4299 4300 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 4301 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 4302 goto out; 4303 } 4304 4305 if (ibdev->ib_active) 4306 ib_dispatch_event(&ibev); 4307 4308 if (fatal) 4309 ibdev->ib_active = false; 4310 out: 4311 kfree(work); 4312 } 4313 4314 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 4315 enum mlx5_dev_event event, unsigned long param) 4316 { 4317 struct mlx5_ib_event_work *work; 4318 4319 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4320 if (!work) 4321 return; 4322 4323 INIT_WORK(&work->work, mlx5_ib_handle_event); 4324 work->dev = dev; 4325 work->param = param; 4326 work->context = context; 4327 work->event = event; 4328 4329 queue_work(mlx5_ib_event_wq, &work->work); 4330 } 4331 4332 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4333 { 4334 struct mlx5_hca_vport_context vport_ctx; 4335 int err; 4336 int port; 4337 4338 for (port = 1; port <= dev->num_ports; port++) { 4339 dev->mdev->port_caps[port - 1].has_smi = false; 4340 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4341 MLX5_CAP_PORT_TYPE_IB) { 4342 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4343 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4344 port, 0, 4345 &vport_ctx); 4346 if (err) { 4347 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4348 port, err); 4349 return err; 4350 } 4351 dev->mdev->port_caps[port - 1].has_smi = 4352 vport_ctx.has_smi; 4353 } else { 4354 dev->mdev->port_caps[port - 1].has_smi = true; 4355 } 4356 } 4357 } 4358 return 0; 4359 } 4360 4361 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4362 { 4363 int port; 4364 4365 for (port = 1; port <= dev->num_ports; port++) 4366 mlx5_query_ext_port_caps(dev, port); 4367 } 4368 4369 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4370 { 4371 struct ib_device_attr *dprops = NULL; 4372 struct ib_port_attr *pprops = NULL; 4373 int err = -ENOMEM; 4374 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4375 4376 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4377 if (!pprops) 4378 goto out; 4379 4380 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4381 if (!dprops) 4382 goto out; 4383 4384 err = set_has_smi_cap(dev); 4385 if (err) 4386 goto out; 4387 4388 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4389 if (err) { 4390 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4391 goto out; 4392 } 4393 4394 memset(pprops, 0, sizeof(*pprops)); 4395 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4396 if (err) { 4397 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4398 port, err); 4399 goto out; 4400 } 4401 4402 dev->mdev->port_caps[port - 1].pkey_table_len = 4403 dprops->max_pkeys; 4404 dev->mdev->port_caps[port - 1].gid_table_len = 4405 pprops->gid_tbl_len; 4406 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4407 port, dprops->max_pkeys, pprops->gid_tbl_len); 4408 4409 out: 4410 kfree(pprops); 4411 kfree(dprops); 4412 4413 return err; 4414 } 4415 4416 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4417 { 4418 int err; 4419 4420 err = mlx5_mr_cache_cleanup(dev); 4421 if (err) 4422 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4423 4424 if (dev->umrc.qp) 4425 mlx5_ib_destroy_qp(dev->umrc.qp); 4426 if (dev->umrc.cq) 4427 ib_free_cq(dev->umrc.cq); 4428 if (dev->umrc.pd) 4429 ib_dealloc_pd(dev->umrc.pd); 4430 } 4431 4432 enum { 4433 MAX_UMR_WR = 128, 4434 }; 4435 4436 static int create_umr_res(struct mlx5_ib_dev *dev) 4437 { 4438 struct ib_qp_init_attr *init_attr = NULL; 4439 struct ib_qp_attr *attr = NULL; 4440 struct ib_pd *pd; 4441 struct ib_cq *cq; 4442 struct ib_qp *qp; 4443 int ret; 4444 4445 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4446 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4447 if (!attr || !init_attr) { 4448 ret = -ENOMEM; 4449 goto error_0; 4450 } 4451 4452 pd = ib_alloc_pd(&dev->ib_dev, 0); 4453 if (IS_ERR(pd)) { 4454 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4455 ret = PTR_ERR(pd); 4456 goto error_0; 4457 } 4458 4459 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4460 if (IS_ERR(cq)) { 4461 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4462 ret = PTR_ERR(cq); 4463 goto error_2; 4464 } 4465 4466 init_attr->send_cq = cq; 4467 init_attr->recv_cq = cq; 4468 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4469 init_attr->cap.max_send_wr = MAX_UMR_WR; 4470 init_attr->cap.max_send_sge = 1; 4471 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4472 init_attr->port_num = 1; 4473 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4474 if (IS_ERR(qp)) { 4475 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4476 ret = PTR_ERR(qp); 4477 goto error_3; 4478 } 4479 qp->device = &dev->ib_dev; 4480 qp->real_qp = qp; 4481 qp->uobject = NULL; 4482 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4483 qp->send_cq = init_attr->send_cq; 4484 qp->recv_cq = init_attr->recv_cq; 4485 4486 attr->qp_state = IB_QPS_INIT; 4487 attr->port_num = 1; 4488 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4489 IB_QP_PORT, NULL); 4490 if (ret) { 4491 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4492 goto error_4; 4493 } 4494 4495 memset(attr, 0, sizeof(*attr)); 4496 attr->qp_state = IB_QPS_RTR; 4497 attr->path_mtu = IB_MTU_256; 4498 4499 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4500 if (ret) { 4501 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4502 goto error_4; 4503 } 4504 4505 memset(attr, 0, sizeof(*attr)); 4506 attr->qp_state = IB_QPS_RTS; 4507 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4508 if (ret) { 4509 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4510 goto error_4; 4511 } 4512 4513 dev->umrc.qp = qp; 4514 dev->umrc.cq = cq; 4515 dev->umrc.pd = pd; 4516 4517 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4518 ret = mlx5_mr_cache_init(dev); 4519 if (ret) { 4520 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4521 goto error_4; 4522 } 4523 4524 kfree(attr); 4525 kfree(init_attr); 4526 4527 return 0; 4528 4529 error_4: 4530 mlx5_ib_destroy_qp(qp); 4531 dev->umrc.qp = NULL; 4532 4533 error_3: 4534 ib_free_cq(cq); 4535 dev->umrc.cq = NULL; 4536 4537 error_2: 4538 ib_dealloc_pd(pd); 4539 dev->umrc.pd = NULL; 4540 4541 error_0: 4542 kfree(attr); 4543 kfree(init_attr); 4544 return ret; 4545 } 4546 4547 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4548 { 4549 switch (umr_fence_cap) { 4550 case MLX5_CAP_UMR_FENCE_NONE: 4551 return MLX5_FENCE_MODE_NONE; 4552 case MLX5_CAP_UMR_FENCE_SMALL: 4553 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4554 default: 4555 return MLX5_FENCE_MODE_STRONG_ORDERING; 4556 } 4557 } 4558 4559 static int create_dev_resources(struct mlx5_ib_resources *devr) 4560 { 4561 struct ib_srq_init_attr attr; 4562 struct mlx5_ib_dev *dev; 4563 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4564 int port; 4565 int ret = 0; 4566 4567 dev = container_of(devr, struct mlx5_ib_dev, devr); 4568 4569 mutex_init(&devr->mutex); 4570 4571 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4572 if (IS_ERR(devr->p0)) { 4573 ret = PTR_ERR(devr->p0); 4574 goto error0; 4575 } 4576 devr->p0->device = &dev->ib_dev; 4577 devr->p0->uobject = NULL; 4578 atomic_set(&devr->p0->usecnt, 0); 4579 4580 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4581 if (IS_ERR(devr->c0)) { 4582 ret = PTR_ERR(devr->c0); 4583 goto error1; 4584 } 4585 devr->c0->device = &dev->ib_dev; 4586 devr->c0->uobject = NULL; 4587 devr->c0->comp_handler = NULL; 4588 devr->c0->event_handler = NULL; 4589 devr->c0->cq_context = NULL; 4590 atomic_set(&devr->c0->usecnt, 0); 4591 4592 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4593 if (IS_ERR(devr->x0)) { 4594 ret = PTR_ERR(devr->x0); 4595 goto error2; 4596 } 4597 devr->x0->device = &dev->ib_dev; 4598 devr->x0->inode = NULL; 4599 atomic_set(&devr->x0->usecnt, 0); 4600 mutex_init(&devr->x0->tgt_qp_mutex); 4601 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4602 4603 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4604 if (IS_ERR(devr->x1)) { 4605 ret = PTR_ERR(devr->x1); 4606 goto error3; 4607 } 4608 devr->x1->device = &dev->ib_dev; 4609 devr->x1->inode = NULL; 4610 atomic_set(&devr->x1->usecnt, 0); 4611 mutex_init(&devr->x1->tgt_qp_mutex); 4612 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4613 4614 memset(&attr, 0, sizeof(attr)); 4615 attr.attr.max_sge = 1; 4616 attr.attr.max_wr = 1; 4617 attr.srq_type = IB_SRQT_XRC; 4618 attr.ext.cq = devr->c0; 4619 attr.ext.xrc.xrcd = devr->x0; 4620 4621 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4622 if (IS_ERR(devr->s0)) { 4623 ret = PTR_ERR(devr->s0); 4624 goto error4; 4625 } 4626 devr->s0->device = &dev->ib_dev; 4627 devr->s0->pd = devr->p0; 4628 devr->s0->uobject = NULL; 4629 devr->s0->event_handler = NULL; 4630 devr->s0->srq_context = NULL; 4631 devr->s0->srq_type = IB_SRQT_XRC; 4632 devr->s0->ext.xrc.xrcd = devr->x0; 4633 devr->s0->ext.cq = devr->c0; 4634 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4635 atomic_inc(&devr->s0->ext.cq->usecnt); 4636 atomic_inc(&devr->p0->usecnt); 4637 atomic_set(&devr->s0->usecnt, 0); 4638 4639 memset(&attr, 0, sizeof(attr)); 4640 attr.attr.max_sge = 1; 4641 attr.attr.max_wr = 1; 4642 attr.srq_type = IB_SRQT_BASIC; 4643 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4644 if (IS_ERR(devr->s1)) { 4645 ret = PTR_ERR(devr->s1); 4646 goto error5; 4647 } 4648 devr->s1->device = &dev->ib_dev; 4649 devr->s1->pd = devr->p0; 4650 devr->s1->uobject = NULL; 4651 devr->s1->event_handler = NULL; 4652 devr->s1->srq_context = NULL; 4653 devr->s1->srq_type = IB_SRQT_BASIC; 4654 devr->s1->ext.cq = devr->c0; 4655 atomic_inc(&devr->p0->usecnt); 4656 atomic_set(&devr->s1->usecnt, 0); 4657 4658 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4659 INIT_WORK(&devr->ports[port].pkey_change_work, 4660 pkey_change_handler); 4661 devr->ports[port].devr = devr; 4662 } 4663 4664 return 0; 4665 4666 error5: 4667 mlx5_ib_destroy_srq(devr->s0); 4668 error4: 4669 mlx5_ib_dealloc_xrcd(devr->x1); 4670 error3: 4671 mlx5_ib_dealloc_xrcd(devr->x0); 4672 error2: 4673 mlx5_ib_destroy_cq(devr->c0); 4674 error1: 4675 mlx5_ib_dealloc_pd(devr->p0); 4676 error0: 4677 return ret; 4678 } 4679 4680 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4681 { 4682 struct mlx5_ib_dev *dev = 4683 container_of(devr, struct mlx5_ib_dev, devr); 4684 int port; 4685 4686 mlx5_ib_destroy_srq(devr->s1); 4687 mlx5_ib_destroy_srq(devr->s0); 4688 mlx5_ib_dealloc_xrcd(devr->x0); 4689 mlx5_ib_dealloc_xrcd(devr->x1); 4690 mlx5_ib_destroy_cq(devr->c0); 4691 mlx5_ib_dealloc_pd(devr->p0); 4692 4693 /* Make sure no change P_Key work items are still executing */ 4694 for (port = 0; port < dev->num_ports; ++port) 4695 cancel_work_sync(&devr->ports[port].pkey_change_work); 4696 } 4697 4698 static u32 get_core_cap_flags(struct ib_device *ibdev, 4699 struct mlx5_hca_vport_context *rep) 4700 { 4701 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4702 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4703 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4704 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4705 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4706 u32 ret = 0; 4707 4708 if (rep->grh_required) 4709 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4710 4711 if (ll == IB_LINK_LAYER_INFINIBAND) 4712 return ret | RDMA_CORE_PORT_IBA_IB; 4713 4714 if (raw_support) 4715 ret |= RDMA_CORE_PORT_RAW_PACKET; 4716 4717 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4718 return ret; 4719 4720 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4721 return ret; 4722 4723 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4724 ret |= RDMA_CORE_PORT_IBA_ROCE; 4725 4726 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4727 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4728 4729 return ret; 4730 } 4731 4732 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4733 struct ib_port_immutable *immutable) 4734 { 4735 struct ib_port_attr attr; 4736 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4737 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4738 struct mlx5_hca_vport_context rep = {0}; 4739 int err; 4740 4741 err = ib_query_port(ibdev, port_num, &attr); 4742 if (err) 4743 return err; 4744 4745 if (ll == IB_LINK_LAYER_INFINIBAND) { 4746 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4747 &rep); 4748 if (err) 4749 return err; 4750 } 4751 4752 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4753 immutable->gid_tbl_len = attr.gid_tbl_len; 4754 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4755 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4756 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4757 4758 return 0; 4759 } 4760 4761 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4762 struct ib_port_immutable *immutable) 4763 { 4764 struct ib_port_attr attr; 4765 int err; 4766 4767 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4768 4769 err = ib_query_port(ibdev, port_num, &attr); 4770 if (err) 4771 return err; 4772 4773 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4774 immutable->gid_tbl_len = attr.gid_tbl_len; 4775 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4776 4777 return 0; 4778 } 4779 4780 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4781 { 4782 struct mlx5_ib_dev *dev = 4783 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4784 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4785 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4786 fw_rev_sub(dev->mdev)); 4787 } 4788 4789 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4790 { 4791 struct mlx5_core_dev *mdev = dev->mdev; 4792 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4793 MLX5_FLOW_NAMESPACE_LAG); 4794 struct mlx5_flow_table *ft; 4795 int err; 4796 4797 if (!ns || !mlx5_lag_is_active(mdev)) 4798 return 0; 4799 4800 err = mlx5_cmd_create_vport_lag(mdev); 4801 if (err) 4802 return err; 4803 4804 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4805 if (IS_ERR(ft)) { 4806 err = PTR_ERR(ft); 4807 goto err_destroy_vport_lag; 4808 } 4809 4810 dev->flow_db->lag_demux_ft = ft; 4811 return 0; 4812 4813 err_destroy_vport_lag: 4814 mlx5_cmd_destroy_vport_lag(mdev); 4815 return err; 4816 } 4817 4818 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4819 { 4820 struct mlx5_core_dev *mdev = dev->mdev; 4821 4822 if (dev->flow_db->lag_demux_ft) { 4823 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4824 dev->flow_db->lag_demux_ft = NULL; 4825 4826 mlx5_cmd_destroy_vport_lag(mdev); 4827 } 4828 } 4829 4830 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4831 { 4832 int err; 4833 4834 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4835 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4836 if (err) { 4837 dev->roce[port_num].nb.notifier_call = NULL; 4838 return err; 4839 } 4840 4841 return 0; 4842 } 4843 4844 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4845 { 4846 if (dev->roce[port_num].nb.notifier_call) { 4847 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4848 dev->roce[port_num].nb.notifier_call = NULL; 4849 } 4850 } 4851 4852 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 4853 { 4854 int err; 4855 4856 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4857 err = mlx5_nic_vport_enable_roce(dev->mdev); 4858 if (err) 4859 return err; 4860 } 4861 4862 err = mlx5_eth_lag_init(dev); 4863 if (err) 4864 goto err_disable_roce; 4865 4866 return 0; 4867 4868 err_disable_roce: 4869 if (MLX5_CAP_GEN(dev->mdev, roce)) 4870 mlx5_nic_vport_disable_roce(dev->mdev); 4871 4872 return err; 4873 } 4874 4875 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4876 { 4877 mlx5_eth_lag_cleanup(dev); 4878 if (MLX5_CAP_GEN(dev->mdev, roce)) 4879 mlx5_nic_vport_disable_roce(dev->mdev); 4880 } 4881 4882 struct mlx5_ib_counter { 4883 const char *name; 4884 size_t offset; 4885 }; 4886 4887 #define INIT_Q_COUNTER(_name) \ 4888 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4889 4890 static const struct mlx5_ib_counter basic_q_cnts[] = { 4891 INIT_Q_COUNTER(rx_write_requests), 4892 INIT_Q_COUNTER(rx_read_requests), 4893 INIT_Q_COUNTER(rx_atomic_requests), 4894 INIT_Q_COUNTER(out_of_buffer), 4895 }; 4896 4897 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4898 INIT_Q_COUNTER(out_of_sequence), 4899 }; 4900 4901 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4902 INIT_Q_COUNTER(duplicate_request), 4903 INIT_Q_COUNTER(rnr_nak_retry_err), 4904 INIT_Q_COUNTER(packet_seq_err), 4905 INIT_Q_COUNTER(implied_nak_seq_err), 4906 INIT_Q_COUNTER(local_ack_timeout_err), 4907 }; 4908 4909 #define INIT_CONG_COUNTER(_name) \ 4910 { .name = #_name, .offset = \ 4911 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4912 4913 static const struct mlx5_ib_counter cong_cnts[] = { 4914 INIT_CONG_COUNTER(rp_cnp_ignored), 4915 INIT_CONG_COUNTER(rp_cnp_handled), 4916 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4917 INIT_CONG_COUNTER(np_cnp_sent), 4918 }; 4919 4920 static const struct mlx5_ib_counter extended_err_cnts[] = { 4921 INIT_Q_COUNTER(resp_local_length_error), 4922 INIT_Q_COUNTER(resp_cqe_error), 4923 INIT_Q_COUNTER(req_cqe_error), 4924 INIT_Q_COUNTER(req_remote_invalid_request), 4925 INIT_Q_COUNTER(req_remote_access_errors), 4926 INIT_Q_COUNTER(resp_remote_access_errors), 4927 INIT_Q_COUNTER(resp_cqe_flush_error), 4928 INIT_Q_COUNTER(req_cqe_flush_error), 4929 }; 4930 4931 #define INIT_EXT_PPCNT_COUNTER(_name) \ 4932 { .name = #_name, .offset = \ 4933 MLX5_BYTE_OFF(ppcnt_reg, \ 4934 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 4935 4936 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 4937 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 4938 }; 4939 4940 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4941 { 4942 int i; 4943 4944 for (i = 0; i < dev->num_ports; i++) { 4945 if (dev->port[i].cnts.set_id_valid) 4946 mlx5_core_dealloc_q_counter(dev->mdev, 4947 dev->port[i].cnts.set_id); 4948 kfree(dev->port[i].cnts.names); 4949 kfree(dev->port[i].cnts.offsets); 4950 } 4951 } 4952 4953 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 4954 struct mlx5_ib_counters *cnts) 4955 { 4956 u32 num_counters; 4957 4958 num_counters = ARRAY_SIZE(basic_q_cnts); 4959 4960 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4961 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4962 4963 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4964 num_counters += ARRAY_SIZE(retrans_q_cnts); 4965 4966 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4967 num_counters += ARRAY_SIZE(extended_err_cnts); 4968 4969 cnts->num_q_counters = num_counters; 4970 4971 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4972 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4973 num_counters += ARRAY_SIZE(cong_cnts); 4974 } 4975 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 4976 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 4977 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 4978 } 4979 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4980 if (!cnts->names) 4981 return -ENOMEM; 4982 4983 cnts->offsets = kcalloc(num_counters, 4984 sizeof(cnts->offsets), GFP_KERNEL); 4985 if (!cnts->offsets) 4986 goto err_names; 4987 4988 return 0; 4989 4990 err_names: 4991 kfree(cnts->names); 4992 cnts->names = NULL; 4993 return -ENOMEM; 4994 } 4995 4996 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4997 const char **names, 4998 size_t *offsets) 4999 { 5000 int i; 5001 int j = 0; 5002 5003 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5004 names[j] = basic_q_cnts[i].name; 5005 offsets[j] = basic_q_cnts[i].offset; 5006 } 5007 5008 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5009 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5010 names[j] = out_of_seq_q_cnts[i].name; 5011 offsets[j] = out_of_seq_q_cnts[i].offset; 5012 } 5013 } 5014 5015 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5016 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5017 names[j] = retrans_q_cnts[i].name; 5018 offsets[j] = retrans_q_cnts[i].offset; 5019 } 5020 } 5021 5022 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5023 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5024 names[j] = extended_err_cnts[i].name; 5025 offsets[j] = extended_err_cnts[i].offset; 5026 } 5027 } 5028 5029 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5030 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5031 names[j] = cong_cnts[i].name; 5032 offsets[j] = cong_cnts[i].offset; 5033 } 5034 } 5035 5036 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5037 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5038 names[j] = ext_ppcnt_cnts[i].name; 5039 offsets[j] = ext_ppcnt_cnts[i].offset; 5040 } 5041 } 5042 } 5043 5044 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5045 { 5046 int err = 0; 5047 int i; 5048 5049 for (i = 0; i < dev->num_ports; i++) { 5050 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5051 if (err) 5052 goto err_alloc; 5053 5054 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5055 dev->port[i].cnts.offsets); 5056 5057 err = mlx5_core_alloc_q_counter(dev->mdev, 5058 &dev->port[i].cnts.set_id); 5059 if (err) { 5060 mlx5_ib_warn(dev, 5061 "couldn't allocate queue counter for port %d, err %d\n", 5062 i + 1, err); 5063 goto err_alloc; 5064 } 5065 dev->port[i].cnts.set_id_valid = true; 5066 } 5067 5068 return 0; 5069 5070 err_alloc: 5071 mlx5_ib_dealloc_counters(dev); 5072 return err; 5073 } 5074 5075 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5076 u8 port_num) 5077 { 5078 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5079 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5080 5081 /* We support only per port stats */ 5082 if (port_num == 0) 5083 return NULL; 5084 5085 return rdma_alloc_hw_stats_struct(port->cnts.names, 5086 port->cnts.num_q_counters + 5087 port->cnts.num_cong_counters + 5088 port->cnts.num_ext_ppcnt_counters, 5089 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5090 } 5091 5092 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5093 struct mlx5_ib_port *port, 5094 struct rdma_hw_stats *stats) 5095 { 5096 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5097 void *out; 5098 __be32 val; 5099 int ret, i; 5100 5101 out = kvzalloc(outlen, GFP_KERNEL); 5102 if (!out) 5103 return -ENOMEM; 5104 5105 ret = mlx5_core_query_q_counter(mdev, 5106 port->cnts.set_id, 0, 5107 out, outlen); 5108 if (ret) 5109 goto free; 5110 5111 for (i = 0; i < port->cnts.num_q_counters; i++) { 5112 val = *(__be32 *)(out + port->cnts.offsets[i]); 5113 stats->value[i] = (u64)be32_to_cpu(val); 5114 } 5115 5116 free: 5117 kvfree(out); 5118 return ret; 5119 } 5120 5121 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5122 struct mlx5_ib_port *port, 5123 struct rdma_hw_stats *stats) 5124 { 5125 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5126 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5127 int ret, i; 5128 void *out; 5129 5130 out = kvzalloc(sz, GFP_KERNEL); 5131 if (!out) 5132 return -ENOMEM; 5133 5134 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5135 if (ret) 5136 goto free; 5137 5138 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5139 stats->value[i + offset] = 5140 be64_to_cpup((__be64 *)(out + 5141 port->cnts.offsets[i + offset])); 5142 } 5143 5144 free: 5145 kvfree(out); 5146 return ret; 5147 } 5148 5149 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5150 struct rdma_hw_stats *stats, 5151 u8 port_num, int index) 5152 { 5153 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5154 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5155 struct mlx5_core_dev *mdev; 5156 int ret, num_counters; 5157 u8 mdev_port_num; 5158 5159 if (!stats) 5160 return -EINVAL; 5161 5162 num_counters = port->cnts.num_q_counters + 5163 port->cnts.num_cong_counters + 5164 port->cnts.num_ext_ppcnt_counters; 5165 5166 /* q_counters are per IB device, query the master mdev */ 5167 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5168 if (ret) 5169 return ret; 5170 5171 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5172 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5173 if (ret) 5174 return ret; 5175 } 5176 5177 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5178 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5179 &mdev_port_num); 5180 if (!mdev) { 5181 /* If port is not affiliated yet, its in down state 5182 * which doesn't have any counters yet, so it would be 5183 * zero. So no need to read from the HCA. 5184 */ 5185 goto done; 5186 } 5187 ret = mlx5_lag_query_cong_counters(dev->mdev, 5188 stats->value + 5189 port->cnts.num_q_counters, 5190 port->cnts.num_cong_counters, 5191 port->cnts.offsets + 5192 port->cnts.num_q_counters); 5193 5194 mlx5_ib_put_native_port_mdev(dev, port_num); 5195 if (ret) 5196 return ret; 5197 } 5198 5199 done: 5200 return num_counters; 5201 } 5202 5203 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5204 enum rdma_netdev_t type, 5205 struct rdma_netdev_alloc_params *params) 5206 { 5207 if (type != RDMA_NETDEV_IPOIB) 5208 return -EOPNOTSUPP; 5209 5210 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5211 } 5212 5213 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5214 { 5215 if (!dev->delay_drop.dbg) 5216 return; 5217 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5218 kfree(dev->delay_drop.dbg); 5219 dev->delay_drop.dbg = NULL; 5220 } 5221 5222 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5223 { 5224 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5225 return; 5226 5227 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5228 delay_drop_debugfs_cleanup(dev); 5229 } 5230 5231 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5232 size_t count, loff_t *pos) 5233 { 5234 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5235 char lbuf[20]; 5236 int len; 5237 5238 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5239 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5240 } 5241 5242 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5243 size_t count, loff_t *pos) 5244 { 5245 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5246 u32 timeout; 5247 u32 var; 5248 5249 if (kstrtouint_from_user(buf, count, 0, &var)) 5250 return -EFAULT; 5251 5252 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5253 1000); 5254 if (timeout != var) 5255 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5256 timeout); 5257 5258 delay_drop->timeout = timeout; 5259 5260 return count; 5261 } 5262 5263 static const struct file_operations fops_delay_drop_timeout = { 5264 .owner = THIS_MODULE, 5265 .open = simple_open, 5266 .write = delay_drop_timeout_write, 5267 .read = delay_drop_timeout_read, 5268 }; 5269 5270 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5271 { 5272 struct mlx5_ib_dbg_delay_drop *dbg; 5273 5274 if (!mlx5_debugfs_root) 5275 return 0; 5276 5277 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5278 if (!dbg) 5279 return -ENOMEM; 5280 5281 dev->delay_drop.dbg = dbg; 5282 5283 dbg->dir_debugfs = 5284 debugfs_create_dir("delay_drop", 5285 dev->mdev->priv.dbg_root); 5286 if (!dbg->dir_debugfs) 5287 goto out_debugfs; 5288 5289 dbg->events_cnt_debugfs = 5290 debugfs_create_atomic_t("num_timeout_events", 0400, 5291 dbg->dir_debugfs, 5292 &dev->delay_drop.events_cnt); 5293 if (!dbg->events_cnt_debugfs) 5294 goto out_debugfs; 5295 5296 dbg->rqs_cnt_debugfs = 5297 debugfs_create_atomic_t("num_rqs", 0400, 5298 dbg->dir_debugfs, 5299 &dev->delay_drop.rqs_cnt); 5300 if (!dbg->rqs_cnt_debugfs) 5301 goto out_debugfs; 5302 5303 dbg->timeout_debugfs = 5304 debugfs_create_file("timeout", 0600, 5305 dbg->dir_debugfs, 5306 &dev->delay_drop, 5307 &fops_delay_drop_timeout); 5308 if (!dbg->timeout_debugfs) 5309 goto out_debugfs; 5310 5311 return 0; 5312 5313 out_debugfs: 5314 delay_drop_debugfs_cleanup(dev); 5315 return -ENOMEM; 5316 } 5317 5318 static void init_delay_drop(struct mlx5_ib_dev *dev) 5319 { 5320 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5321 return; 5322 5323 mutex_init(&dev->delay_drop.lock); 5324 dev->delay_drop.dev = dev; 5325 dev->delay_drop.activate = false; 5326 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5327 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5328 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5329 atomic_set(&dev->delay_drop.events_cnt, 0); 5330 5331 if (delay_drop_debugfs_init(dev)) 5332 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5333 } 5334 5335 static const struct cpumask * 5336 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 5337 { 5338 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5339 5340 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector); 5341 } 5342 5343 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5344 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5345 struct mlx5_ib_multiport_info *mpi) 5346 { 5347 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5348 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5349 int comps; 5350 int err; 5351 int i; 5352 5353 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5354 5355 spin_lock(&port->mp.mpi_lock); 5356 if (!mpi->ibdev) { 5357 spin_unlock(&port->mp.mpi_lock); 5358 return; 5359 } 5360 mpi->ibdev = NULL; 5361 5362 spin_unlock(&port->mp.mpi_lock); 5363 mlx5_remove_netdev_notifier(ibdev, port_num); 5364 spin_lock(&port->mp.mpi_lock); 5365 5366 comps = mpi->mdev_refcnt; 5367 if (comps) { 5368 mpi->unaffiliate = true; 5369 init_completion(&mpi->unref_comp); 5370 spin_unlock(&port->mp.mpi_lock); 5371 5372 for (i = 0; i < comps; i++) 5373 wait_for_completion(&mpi->unref_comp); 5374 5375 spin_lock(&port->mp.mpi_lock); 5376 mpi->unaffiliate = false; 5377 } 5378 5379 port->mp.mpi = NULL; 5380 5381 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5382 5383 spin_unlock(&port->mp.mpi_lock); 5384 5385 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5386 5387 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5388 /* Log an error, still needed to cleanup the pointers and add 5389 * it back to the list. 5390 */ 5391 if (err) 5392 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5393 port_num + 1); 5394 5395 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5396 } 5397 5398 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5399 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5400 struct mlx5_ib_multiport_info *mpi) 5401 { 5402 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5403 int err; 5404 5405 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5406 if (ibdev->port[port_num].mp.mpi) { 5407 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5408 port_num + 1); 5409 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5410 return false; 5411 } 5412 5413 ibdev->port[port_num].mp.mpi = mpi; 5414 mpi->ibdev = ibdev; 5415 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5416 5417 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5418 if (err) 5419 goto unbind; 5420 5421 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5422 if (err) 5423 goto unbind; 5424 5425 err = mlx5_add_netdev_notifier(ibdev, port_num); 5426 if (err) { 5427 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5428 port_num + 1); 5429 goto unbind; 5430 } 5431 5432 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 5433 if (err) 5434 goto unbind; 5435 5436 return true; 5437 5438 unbind: 5439 mlx5_ib_unbind_slave_port(ibdev, mpi); 5440 return false; 5441 } 5442 5443 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5444 { 5445 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5446 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5447 port_num + 1); 5448 struct mlx5_ib_multiport_info *mpi; 5449 int err; 5450 int i; 5451 5452 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5453 return 0; 5454 5455 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5456 &dev->sys_image_guid); 5457 if (err) 5458 return err; 5459 5460 err = mlx5_nic_vport_enable_roce(dev->mdev); 5461 if (err) 5462 return err; 5463 5464 mutex_lock(&mlx5_ib_multiport_mutex); 5465 for (i = 0; i < dev->num_ports; i++) { 5466 bool bound = false; 5467 5468 /* build a stub multiport info struct for the native port. */ 5469 if (i == port_num) { 5470 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5471 if (!mpi) { 5472 mutex_unlock(&mlx5_ib_multiport_mutex); 5473 mlx5_nic_vport_disable_roce(dev->mdev); 5474 return -ENOMEM; 5475 } 5476 5477 mpi->is_master = true; 5478 mpi->mdev = dev->mdev; 5479 mpi->sys_image_guid = dev->sys_image_guid; 5480 dev->port[i].mp.mpi = mpi; 5481 mpi->ibdev = dev; 5482 mpi = NULL; 5483 continue; 5484 } 5485 5486 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5487 list) { 5488 if (dev->sys_image_guid == mpi->sys_image_guid && 5489 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5490 bound = mlx5_ib_bind_slave_port(dev, mpi); 5491 } 5492 5493 if (bound) { 5494 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5495 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5496 list_del(&mpi->list); 5497 break; 5498 } 5499 } 5500 if (!bound) { 5501 get_port_caps(dev, i + 1); 5502 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5503 i + 1); 5504 } 5505 } 5506 5507 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5508 mutex_unlock(&mlx5_ib_multiport_mutex); 5509 return err; 5510 } 5511 5512 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5513 { 5514 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5515 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5516 port_num + 1); 5517 int i; 5518 5519 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5520 return; 5521 5522 mutex_lock(&mlx5_ib_multiport_mutex); 5523 for (i = 0; i < dev->num_ports; i++) { 5524 if (dev->port[i].mp.mpi) { 5525 /* Destroy the native port stub */ 5526 if (i == port_num) { 5527 kfree(dev->port[i].mp.mpi); 5528 dev->port[i].mp.mpi = NULL; 5529 } else { 5530 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5531 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5532 } 5533 } 5534 } 5535 5536 mlx5_ib_dbg(dev, "removing from devlist\n"); 5537 list_del(&dev->ib_dev_list); 5538 mutex_unlock(&mlx5_ib_multiport_mutex); 5539 5540 mlx5_nic_vport_disable_roce(dev->mdev); 5541 } 5542 5543 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5544 mlx5_ib_dm, 5545 UVERBS_OBJECT_DM, 5546 UVERBS_METHOD_DM_ALLOC, 5547 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5548 UVERBS_ATTR_TYPE(u64), 5549 UA_MANDATORY), 5550 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5551 UVERBS_ATTR_TYPE(u16), 5552 UA_MANDATORY)); 5553 5554 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5555 mlx5_ib_flow_action, 5556 UVERBS_OBJECT_FLOW_ACTION, 5557 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5558 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5559 enum mlx5_ib_uapi_flow_action_flags)); 5560 5561 static int populate_specs_root(struct mlx5_ib_dev *dev) 5562 { 5563 const struct uverbs_object_tree_def **trees = dev->driver_trees; 5564 size_t num_trees = 0; 5565 5566 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 5567 MLX5_ACCEL_IPSEC_CAP_DEVICE) 5568 trees[num_trees++] = &mlx5_ib_flow_action; 5569 5570 if (MLX5_CAP_DEV_MEM(dev->mdev, memic)) 5571 trees[num_trees++] = &mlx5_ib_dm; 5572 5573 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 5574 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX) 5575 trees[num_trees++] = mlx5_ib_get_devx_tree(); 5576 5577 num_trees += mlx5_ib_get_flow_trees(trees + num_trees); 5578 5579 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees)); 5580 trees[num_trees] = NULL; 5581 dev->ib_dev.driver_specs = trees; 5582 5583 return 0; 5584 } 5585 5586 static int mlx5_ib_read_counters(struct ib_counters *counters, 5587 struct ib_counters_read_attr *read_attr, 5588 struct uverbs_attr_bundle *attrs) 5589 { 5590 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5591 struct mlx5_read_counters_attr mread_attr = {}; 5592 struct mlx5_ib_flow_counters_desc *desc; 5593 int ret, i; 5594 5595 mutex_lock(&mcounters->mcntrs_mutex); 5596 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5597 ret = -EINVAL; 5598 goto err_bound; 5599 } 5600 5601 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5602 GFP_KERNEL); 5603 if (!mread_attr.out) { 5604 ret = -ENOMEM; 5605 goto err_bound; 5606 } 5607 5608 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5609 mread_attr.flags = read_attr->flags; 5610 ret = mcounters->read_counters(counters->device, &mread_attr); 5611 if (ret) 5612 goto err_read; 5613 5614 /* do the pass over the counters data array to assign according to the 5615 * descriptions and indexing pairs 5616 */ 5617 desc = mcounters->counters_data; 5618 for (i = 0; i < mcounters->ncounters; i++) 5619 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5620 5621 err_read: 5622 kfree(mread_attr.out); 5623 err_bound: 5624 mutex_unlock(&mcounters->mcntrs_mutex); 5625 return ret; 5626 } 5627 5628 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5629 { 5630 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5631 5632 counters_clear_description(counters); 5633 if (mcounters->hw_cntrs_hndl) 5634 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5635 mcounters->hw_cntrs_hndl); 5636 5637 kfree(mcounters); 5638 5639 return 0; 5640 } 5641 5642 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5643 struct uverbs_attr_bundle *attrs) 5644 { 5645 struct mlx5_ib_mcounters *mcounters; 5646 5647 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5648 if (!mcounters) 5649 return ERR_PTR(-ENOMEM); 5650 5651 mutex_init(&mcounters->mcntrs_mutex); 5652 5653 return &mcounters->ibcntrs; 5654 } 5655 5656 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5657 { 5658 mlx5_ib_cleanup_multiport_master(dev); 5659 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5660 cleanup_srcu_struct(&dev->mr_srcu); 5661 #endif 5662 kfree(dev->port); 5663 } 5664 5665 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5666 { 5667 struct mlx5_core_dev *mdev = dev->mdev; 5668 int err; 5669 int i; 5670 5671 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5672 GFP_KERNEL); 5673 if (!dev->port) 5674 return -ENOMEM; 5675 5676 for (i = 0; i < dev->num_ports; i++) { 5677 spin_lock_init(&dev->port[i].mp.mpi_lock); 5678 rwlock_init(&dev->roce[i].netdev_lock); 5679 } 5680 5681 err = mlx5_ib_init_multiport_master(dev); 5682 if (err) 5683 goto err_free_port; 5684 5685 if (!mlx5_core_mp_enabled(mdev)) { 5686 for (i = 1; i <= dev->num_ports; i++) { 5687 err = get_port_caps(dev, i); 5688 if (err) 5689 break; 5690 } 5691 } else { 5692 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5693 } 5694 if (err) 5695 goto err_mp; 5696 5697 if (mlx5_use_mad_ifc(dev)) 5698 get_ext_port_caps(dev); 5699 5700 dev->ib_dev.owner = THIS_MODULE; 5701 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5702 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5703 dev->ib_dev.phys_port_cnt = dev->num_ports; 5704 dev->ib_dev.num_comp_vectors = 5705 dev->mdev->priv.eq_table.num_comp_vectors; 5706 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5707 5708 mutex_init(&dev->cap_mask_mutex); 5709 INIT_LIST_HEAD(&dev->qp_list); 5710 spin_lock_init(&dev->reset_flow_resource_lock); 5711 5712 spin_lock_init(&dev->memic.memic_lock); 5713 dev->memic.dev = mdev; 5714 5715 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5716 err = init_srcu_struct(&dev->mr_srcu); 5717 if (err) 5718 goto err_free_port; 5719 #endif 5720 5721 return 0; 5722 err_mp: 5723 mlx5_ib_cleanup_multiport_master(dev); 5724 5725 err_free_port: 5726 kfree(dev->port); 5727 5728 return -ENOMEM; 5729 } 5730 5731 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5732 { 5733 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5734 5735 if (!dev->flow_db) 5736 return -ENOMEM; 5737 5738 mutex_init(&dev->flow_db->lock); 5739 5740 return 0; 5741 } 5742 5743 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5744 { 5745 struct mlx5_ib_dev *nic_dev; 5746 5747 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5748 5749 if (!nic_dev) 5750 return -EINVAL; 5751 5752 dev->flow_db = nic_dev->flow_db; 5753 5754 return 0; 5755 } 5756 5757 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5758 { 5759 kfree(dev->flow_db); 5760 } 5761 5762 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5763 { 5764 struct mlx5_core_dev *mdev = dev->mdev; 5765 int err; 5766 5767 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5768 dev->ib_dev.uverbs_cmd_mask = 5769 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5770 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5771 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5772 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5773 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5774 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5775 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5776 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5777 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5778 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5779 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5780 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5781 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5782 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5783 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5784 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5785 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5786 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5787 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5788 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5789 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5790 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5791 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5792 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5793 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5794 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5795 dev->ib_dev.uverbs_ex_cmd_mask = 5796 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5797 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5798 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5799 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5800 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5801 5802 dev->ib_dev.query_device = mlx5_ib_query_device; 5803 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5804 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5805 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5806 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5807 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5808 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5809 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5810 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5811 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5812 dev->ib_dev.mmap = mlx5_ib_mmap; 5813 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5814 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5815 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5816 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5817 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5818 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5819 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5820 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5821 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5822 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5823 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5824 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5825 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5826 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5827 dev->ib_dev.drain_sq = mlx5_ib_drain_sq; 5828 dev->ib_dev.drain_rq = mlx5_ib_drain_rq; 5829 dev->ib_dev.post_send = mlx5_ib_post_send; 5830 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5831 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5832 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5833 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5834 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5835 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5836 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5837 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5838 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5839 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5840 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5841 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5842 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5843 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5844 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5845 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5846 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5847 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5848 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5849 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 5850 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 5851 dev->ib_dev.rdma_netdev_get_params = mlx5_ib_rn_get_params; 5852 5853 if (mlx5_core_is_pf(mdev)) { 5854 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5855 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5856 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5857 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5858 } 5859 5860 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5861 5862 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5863 5864 if (MLX5_CAP_GEN(mdev, imaicl)) { 5865 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5866 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5867 dev->ib_dev.uverbs_cmd_mask |= 5868 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5869 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5870 } 5871 5872 if (MLX5_CAP_GEN(mdev, xrc)) { 5873 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5874 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5875 dev->ib_dev.uverbs_cmd_mask |= 5876 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5877 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5878 } 5879 5880 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5881 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5882 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5883 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr; 5884 } 5885 5886 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5887 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5888 dev->ib_dev.uverbs_ex_cmd_mask |= 5889 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5890 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5891 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5892 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5893 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5894 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5895 dev->ib_dev.create_counters = mlx5_ib_create_counters; 5896 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters; 5897 dev->ib_dev.read_counters = mlx5_ib_read_counters; 5898 5899 err = init_node_data(dev); 5900 if (err) 5901 return err; 5902 5903 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5904 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5905 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5906 mutex_init(&dev->lb.mutex); 5907 5908 return 0; 5909 } 5910 5911 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5912 { 5913 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5914 dev->ib_dev.query_port = mlx5_ib_query_port; 5915 5916 return 0; 5917 } 5918 5919 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5920 { 5921 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5922 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5923 5924 return 0; 5925 } 5926 5927 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 5928 { 5929 u8 port_num; 5930 int i; 5931 5932 for (i = 0; i < dev->num_ports; i++) { 5933 dev->roce[i].dev = dev; 5934 dev->roce[i].native_port_num = i + 1; 5935 dev->roce[i].last_port_state = IB_PORT_DOWN; 5936 } 5937 5938 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5939 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5940 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5941 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 5942 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 5943 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 5944 5945 dev->ib_dev.uverbs_ex_cmd_mask |= 5946 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 5947 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 5948 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 5949 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 5950 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 5951 5952 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5953 5954 return mlx5_add_netdev_notifier(dev, port_num); 5955 } 5956 5957 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 5958 { 5959 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5960 5961 mlx5_remove_netdev_notifier(dev, port_num); 5962 } 5963 5964 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 5965 { 5966 struct mlx5_core_dev *mdev = dev->mdev; 5967 enum rdma_link_layer ll; 5968 int port_type_cap; 5969 int err = 0; 5970 5971 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5972 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5973 5974 if (ll == IB_LINK_LAYER_ETHERNET) 5975 err = mlx5_ib_stage_common_roce_init(dev); 5976 5977 return err; 5978 } 5979 5980 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 5981 { 5982 mlx5_ib_stage_common_roce_cleanup(dev); 5983 } 5984 5985 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 5986 { 5987 struct mlx5_core_dev *mdev = dev->mdev; 5988 enum rdma_link_layer ll; 5989 int port_type_cap; 5990 int err; 5991 5992 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5993 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5994 5995 if (ll == IB_LINK_LAYER_ETHERNET) { 5996 err = mlx5_ib_stage_common_roce_init(dev); 5997 if (err) 5998 return err; 5999 6000 err = mlx5_enable_eth(dev); 6001 if (err) 6002 goto cleanup; 6003 } 6004 6005 return 0; 6006 cleanup: 6007 mlx5_ib_stage_common_roce_cleanup(dev); 6008 6009 return err; 6010 } 6011 6012 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6013 { 6014 struct mlx5_core_dev *mdev = dev->mdev; 6015 enum rdma_link_layer ll; 6016 int port_type_cap; 6017 6018 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6019 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6020 6021 if (ll == IB_LINK_LAYER_ETHERNET) { 6022 mlx5_disable_eth(dev); 6023 mlx5_ib_stage_common_roce_cleanup(dev); 6024 } 6025 } 6026 6027 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6028 { 6029 return create_dev_resources(&dev->devr); 6030 } 6031 6032 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6033 { 6034 destroy_dev_resources(&dev->devr); 6035 } 6036 6037 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6038 { 6039 mlx5_ib_internal_fill_odp_caps(dev); 6040 6041 return mlx5_ib_odp_init_one(dev); 6042 } 6043 6044 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6045 { 6046 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6047 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 6048 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 6049 6050 return mlx5_ib_alloc_counters(dev); 6051 } 6052 6053 return 0; 6054 } 6055 6056 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6057 { 6058 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6059 mlx5_ib_dealloc_counters(dev); 6060 } 6061 6062 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6063 { 6064 return mlx5_ib_init_cong_debugfs(dev, 6065 mlx5_core_native_port_num(dev->mdev) - 1); 6066 } 6067 6068 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6069 { 6070 mlx5_ib_cleanup_cong_debugfs(dev, 6071 mlx5_core_native_port_num(dev->mdev) - 1); 6072 } 6073 6074 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6075 { 6076 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6077 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6078 } 6079 6080 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6081 { 6082 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6083 } 6084 6085 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6086 { 6087 int err; 6088 6089 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6090 if (err) 6091 return err; 6092 6093 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6094 if (err) 6095 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6096 6097 return err; 6098 } 6099 6100 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6101 { 6102 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6103 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6104 } 6105 6106 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 6107 { 6108 return populate_specs_root(dev); 6109 } 6110 6111 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6112 { 6113 const char *name; 6114 6115 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 6116 if (!mlx5_lag_is_active(dev->mdev)) 6117 name = "mlx5_%d"; 6118 else 6119 name = "mlx5_bond_%d"; 6120 return ib_register_device(&dev->ib_dev, name, NULL); 6121 } 6122 6123 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6124 { 6125 destroy_umrc_res(dev); 6126 } 6127 6128 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6129 { 6130 ib_unregister_device(&dev->ib_dev); 6131 } 6132 6133 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6134 { 6135 return create_umr_res(dev); 6136 } 6137 6138 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6139 { 6140 init_delay_drop(dev); 6141 6142 return 0; 6143 } 6144 6145 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6146 { 6147 cancel_delay_drop(dev); 6148 } 6149 6150 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 6151 { 6152 mlx5_ib_register_vport_reps(dev); 6153 6154 return 0; 6155 } 6156 6157 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 6158 { 6159 mlx5_ib_unregister_vport_reps(dev); 6160 } 6161 6162 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6163 const struct mlx5_ib_profile *profile, 6164 int stage) 6165 { 6166 /* Number of stages to cleanup */ 6167 while (stage) { 6168 stage--; 6169 if (profile->stage[stage].cleanup) 6170 profile->stage[stage].cleanup(dev); 6171 } 6172 6173 if (dev->devx_whitelist_uid) 6174 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 6175 ib_dealloc_device((struct ib_device *)dev); 6176 } 6177 6178 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6179 const struct mlx5_ib_profile *profile) 6180 { 6181 int err; 6182 int i; 6183 int uid; 6184 6185 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6186 if (profile->stage[i].init) { 6187 err = profile->stage[i].init(dev); 6188 if (err) 6189 goto err_out; 6190 } 6191 } 6192 6193 uid = mlx5_ib_devx_create(dev); 6194 if (uid > 0) 6195 dev->devx_whitelist_uid = uid; 6196 6197 dev->profile = profile; 6198 dev->ib_active = true; 6199 6200 return dev; 6201 6202 err_out: 6203 __mlx5_ib_remove(dev, profile, i); 6204 6205 return NULL; 6206 } 6207 6208 static const struct mlx5_ib_profile pf_profile = { 6209 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6210 mlx5_ib_stage_init_init, 6211 mlx5_ib_stage_init_cleanup), 6212 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6213 mlx5_ib_stage_flow_db_init, 6214 mlx5_ib_stage_flow_db_cleanup), 6215 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6216 mlx5_ib_stage_caps_init, 6217 NULL), 6218 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6219 mlx5_ib_stage_non_default_cb, 6220 NULL), 6221 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6222 mlx5_ib_stage_roce_init, 6223 mlx5_ib_stage_roce_cleanup), 6224 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6225 mlx5_ib_stage_dev_res_init, 6226 mlx5_ib_stage_dev_res_cleanup), 6227 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6228 mlx5_ib_stage_odp_init, 6229 NULL), 6230 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6231 mlx5_ib_stage_counters_init, 6232 mlx5_ib_stage_counters_cleanup), 6233 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6234 mlx5_ib_stage_cong_debugfs_init, 6235 mlx5_ib_stage_cong_debugfs_cleanup), 6236 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6237 mlx5_ib_stage_uar_init, 6238 mlx5_ib_stage_uar_cleanup), 6239 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6240 mlx5_ib_stage_bfrag_init, 6241 mlx5_ib_stage_bfrag_cleanup), 6242 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6243 NULL, 6244 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6245 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6246 mlx5_ib_stage_populate_specs, 6247 NULL), 6248 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6249 mlx5_ib_stage_ib_reg_init, 6250 mlx5_ib_stage_ib_reg_cleanup), 6251 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6252 mlx5_ib_stage_post_ib_reg_umr_init, 6253 NULL), 6254 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6255 mlx5_ib_stage_delay_drop_init, 6256 mlx5_ib_stage_delay_drop_cleanup), 6257 }; 6258 6259 static const struct mlx5_ib_profile nic_rep_profile = { 6260 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6261 mlx5_ib_stage_init_init, 6262 mlx5_ib_stage_init_cleanup), 6263 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6264 mlx5_ib_stage_flow_db_init, 6265 mlx5_ib_stage_flow_db_cleanup), 6266 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6267 mlx5_ib_stage_caps_init, 6268 NULL), 6269 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6270 mlx5_ib_stage_rep_non_default_cb, 6271 NULL), 6272 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6273 mlx5_ib_stage_rep_roce_init, 6274 mlx5_ib_stage_rep_roce_cleanup), 6275 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6276 mlx5_ib_stage_dev_res_init, 6277 mlx5_ib_stage_dev_res_cleanup), 6278 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6279 mlx5_ib_stage_counters_init, 6280 mlx5_ib_stage_counters_cleanup), 6281 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6282 mlx5_ib_stage_uar_init, 6283 mlx5_ib_stage_uar_cleanup), 6284 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6285 mlx5_ib_stage_bfrag_init, 6286 mlx5_ib_stage_bfrag_cleanup), 6287 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6288 NULL, 6289 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6290 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6291 mlx5_ib_stage_populate_specs, 6292 NULL), 6293 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6294 mlx5_ib_stage_ib_reg_init, 6295 mlx5_ib_stage_ib_reg_cleanup), 6296 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6297 mlx5_ib_stage_post_ib_reg_umr_init, 6298 NULL), 6299 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 6300 mlx5_ib_stage_rep_reg_init, 6301 mlx5_ib_stage_rep_reg_cleanup), 6302 }; 6303 6304 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6305 { 6306 struct mlx5_ib_multiport_info *mpi; 6307 struct mlx5_ib_dev *dev; 6308 bool bound = false; 6309 int err; 6310 6311 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6312 if (!mpi) 6313 return NULL; 6314 6315 mpi->mdev = mdev; 6316 6317 err = mlx5_query_nic_vport_system_image_guid(mdev, 6318 &mpi->sys_image_guid); 6319 if (err) { 6320 kfree(mpi); 6321 return NULL; 6322 } 6323 6324 mutex_lock(&mlx5_ib_multiport_mutex); 6325 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6326 if (dev->sys_image_guid == mpi->sys_image_guid) 6327 bound = mlx5_ib_bind_slave_port(dev, mpi); 6328 6329 if (bound) { 6330 rdma_roce_rescan_device(&dev->ib_dev); 6331 break; 6332 } 6333 } 6334 6335 if (!bound) { 6336 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6337 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6338 } 6339 mutex_unlock(&mlx5_ib_multiport_mutex); 6340 6341 return mpi; 6342 } 6343 6344 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6345 { 6346 enum rdma_link_layer ll; 6347 struct mlx5_ib_dev *dev; 6348 int port_type_cap; 6349 6350 printk_once(KERN_INFO "%s", mlx5_version); 6351 6352 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6353 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6354 6355 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6356 return mlx5_ib_add_slave_port(mdev); 6357 6358 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 6359 if (!dev) 6360 return NULL; 6361 6362 dev->mdev = mdev; 6363 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6364 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6365 6366 if (MLX5_ESWITCH_MANAGER(mdev) && 6367 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6368 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 6369 6370 return __mlx5_ib_add(dev, &nic_rep_profile); 6371 } 6372 6373 return __mlx5_ib_add(dev, &pf_profile); 6374 } 6375 6376 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6377 { 6378 struct mlx5_ib_multiport_info *mpi; 6379 struct mlx5_ib_dev *dev; 6380 6381 if (mlx5_core_is_mp_slave(mdev)) { 6382 mpi = context; 6383 mutex_lock(&mlx5_ib_multiport_mutex); 6384 if (mpi->ibdev) 6385 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6386 list_del(&mpi->list); 6387 mutex_unlock(&mlx5_ib_multiport_mutex); 6388 return; 6389 } 6390 6391 dev = context; 6392 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6393 } 6394 6395 static struct mlx5_interface mlx5_ib_interface = { 6396 .add = mlx5_ib_add, 6397 .remove = mlx5_ib_remove, 6398 .event = mlx5_ib_event, 6399 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 6400 .pfault = mlx5_ib_pfault, 6401 #endif 6402 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6403 }; 6404 6405 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6406 { 6407 mutex_lock(&xlt_emergency_page_mutex); 6408 return xlt_emergency_page; 6409 } 6410 6411 void mlx5_ib_put_xlt_emergency_page(void) 6412 { 6413 mutex_unlock(&xlt_emergency_page_mutex); 6414 } 6415 6416 static int __init mlx5_ib_init(void) 6417 { 6418 int err; 6419 6420 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6421 if (!xlt_emergency_page) 6422 return -ENOMEM; 6423 6424 mutex_init(&xlt_emergency_page_mutex); 6425 6426 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6427 if (!mlx5_ib_event_wq) { 6428 free_page(xlt_emergency_page); 6429 return -ENOMEM; 6430 } 6431 6432 mlx5_ib_odp_init(); 6433 6434 err = mlx5_register_interface(&mlx5_ib_interface); 6435 6436 return err; 6437 } 6438 6439 static void __exit mlx5_ib_cleanup(void) 6440 { 6441 mlx5_unregister_interface(&mlx5_ib_interface); 6442 destroy_workqueue(mlx5_ib_event_wq); 6443 mutex_destroy(&xlt_emergency_page_mutex); 6444 free_page(xlt_emergency_page); 6445 } 6446 6447 module_init(mlx5_ib_init); 6448 module_exit(mlx5_ib_cleanup); 6449