1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "fs.h" 38 #include "srq.h" 39 #include "qp.h" 40 #include "wr.h" 41 #include "restrack.h" 42 #include "counters.h" 43 #include <linux/mlx5/accel.h> 44 #include <rdma/uverbs_std_types.h> 45 #include <rdma/mlx5_user_ioctl_verbs.h> 46 #include <rdma/mlx5_user_ioctl_cmds.h> 47 #include <rdma/ib_umem_odp.h> 48 49 #define UVERBS_MODULE_NAME mlx5_ib 50 #include <rdma/uverbs_named_ioctl.h> 51 52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 53 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 54 MODULE_LICENSE("Dual BSD/GPL"); 55 56 struct mlx5_ib_event_work { 57 struct work_struct work; 58 union { 59 struct mlx5_ib_dev *dev; 60 struct mlx5_ib_multiport_info *mpi; 61 }; 62 bool is_slave; 63 unsigned int event; 64 void *param; 65 }; 66 67 enum { 68 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 69 }; 70 71 static struct workqueue_struct *mlx5_ib_event_wq; 72 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 73 static LIST_HEAD(mlx5_ib_dev_list); 74 /* 75 * This mutex should be held when accessing either of the above lists 76 */ 77 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 78 79 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 80 { 81 struct mlx5_ib_dev *dev; 82 83 mutex_lock(&mlx5_ib_multiport_mutex); 84 dev = mpi->ibdev; 85 mutex_unlock(&mlx5_ib_multiport_mutex); 86 return dev; 87 } 88 89 static enum rdma_link_layer 90 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 91 { 92 switch (port_type_cap) { 93 case MLX5_CAP_PORT_TYPE_IB: 94 return IB_LINK_LAYER_INFINIBAND; 95 case MLX5_CAP_PORT_TYPE_ETH: 96 return IB_LINK_LAYER_ETHERNET; 97 default: 98 return IB_LINK_LAYER_UNSPECIFIED; 99 } 100 } 101 102 static enum rdma_link_layer 103 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 104 { 105 struct mlx5_ib_dev *dev = to_mdev(device); 106 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 107 108 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 109 } 110 111 static int get_port_state(struct ib_device *ibdev, 112 u8 port_num, 113 enum ib_port_state *state) 114 { 115 struct ib_port_attr attr; 116 int ret; 117 118 memset(&attr, 0, sizeof(attr)); 119 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 120 if (!ret) 121 *state = attr.state; 122 return ret; 123 } 124 125 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 126 struct net_device *ndev, 127 u8 *port_num) 128 { 129 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 130 struct net_device *rep_ndev; 131 struct mlx5_ib_port *port; 132 int i; 133 134 for (i = 0; i < dev->num_ports; i++) { 135 port = &dev->port[i]; 136 if (!port->rep) 137 continue; 138 139 read_lock(&port->roce.netdev_lock); 140 rep_ndev = mlx5_ib_get_rep_netdev(esw, 141 port->rep->vport); 142 if (rep_ndev == ndev) { 143 read_unlock(&port->roce.netdev_lock); 144 *port_num = i + 1; 145 return &port->roce; 146 } 147 read_unlock(&port->roce.netdev_lock); 148 } 149 150 return NULL; 151 } 152 153 static int mlx5_netdev_event(struct notifier_block *this, 154 unsigned long event, void *ptr) 155 { 156 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 157 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 158 u8 port_num = roce->native_port_num; 159 struct mlx5_core_dev *mdev; 160 struct mlx5_ib_dev *ibdev; 161 162 ibdev = roce->dev; 163 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 164 if (!mdev) 165 return NOTIFY_DONE; 166 167 switch (event) { 168 case NETDEV_REGISTER: 169 /* Should already be registered during the load */ 170 if (ibdev->is_rep) 171 break; 172 write_lock(&roce->netdev_lock); 173 if (ndev->dev.parent == mdev->device) 174 roce->netdev = ndev; 175 write_unlock(&roce->netdev_lock); 176 break; 177 178 case NETDEV_UNREGISTER: 179 /* In case of reps, ib device goes away before the netdevs */ 180 write_lock(&roce->netdev_lock); 181 if (roce->netdev == ndev) 182 roce->netdev = NULL; 183 write_unlock(&roce->netdev_lock); 184 break; 185 186 case NETDEV_CHANGE: 187 case NETDEV_UP: 188 case NETDEV_DOWN: { 189 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 190 struct net_device *upper = NULL; 191 192 if (lag_ndev) { 193 upper = netdev_master_upper_dev_get(lag_ndev); 194 dev_put(lag_ndev); 195 } 196 197 if (ibdev->is_rep) 198 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 199 if (!roce) 200 return NOTIFY_DONE; 201 if ((upper == ndev || (!upper && ndev == roce->netdev)) 202 && ibdev->ib_active) { 203 struct ib_event ibev = { }; 204 enum ib_port_state port_state; 205 206 if (get_port_state(&ibdev->ib_dev, port_num, 207 &port_state)) 208 goto done; 209 210 if (roce->last_port_state == port_state) 211 goto done; 212 213 roce->last_port_state = port_state; 214 ibev.device = &ibdev->ib_dev; 215 if (port_state == IB_PORT_DOWN) 216 ibev.event = IB_EVENT_PORT_ERR; 217 else if (port_state == IB_PORT_ACTIVE) 218 ibev.event = IB_EVENT_PORT_ACTIVE; 219 else 220 goto done; 221 222 ibev.element.port_num = port_num; 223 ib_dispatch_event(&ibev); 224 } 225 break; 226 } 227 228 default: 229 break; 230 } 231 done: 232 mlx5_ib_put_native_port_mdev(ibdev, port_num); 233 return NOTIFY_DONE; 234 } 235 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 237 u8 port_num) 238 { 239 struct mlx5_ib_dev *ibdev = to_mdev(device); 240 struct net_device *ndev; 241 struct mlx5_core_dev *mdev; 242 243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 244 if (!mdev) 245 return NULL; 246 247 ndev = mlx5_lag_get_roce_netdev(mdev); 248 if (ndev) 249 goto out; 250 251 /* Ensure ndev does not disappear before we invoke dev_hold() 252 */ 253 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 254 ndev = ibdev->port[port_num - 1].roce.netdev; 255 if (ndev) 256 dev_hold(ndev); 257 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 258 259 out: 260 mlx5_ib_put_native_port_mdev(ibdev, port_num); 261 return ndev; 262 } 263 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 265 u8 ib_port_num, 266 u8 *native_port_num) 267 { 268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 269 ib_port_num); 270 struct mlx5_core_dev *mdev = NULL; 271 struct mlx5_ib_multiport_info *mpi; 272 struct mlx5_ib_port *port; 273 274 if (!mlx5_core_mp_enabled(ibdev->mdev) || 275 ll != IB_LINK_LAYER_ETHERNET) { 276 if (native_port_num) 277 *native_port_num = ib_port_num; 278 return ibdev->mdev; 279 } 280 281 if (native_port_num) 282 *native_port_num = 1; 283 284 port = &ibdev->port[ib_port_num - 1]; 285 spin_lock(&port->mp.mpi_lock); 286 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 287 if (mpi && !mpi->unaffiliate) { 288 mdev = mpi->mdev; 289 /* If it's the master no need to refcount, it'll exist 290 * as long as the ib_dev exists. 291 */ 292 if (!mpi->is_master) 293 mpi->mdev_refcnt++; 294 } 295 spin_unlock(&port->mp.mpi_lock); 296 297 return mdev; 298 } 299 300 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 301 { 302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 303 port_num); 304 struct mlx5_ib_multiport_info *mpi; 305 struct mlx5_ib_port *port; 306 307 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 308 return; 309 310 port = &ibdev->port[port_num - 1]; 311 312 spin_lock(&port->mp.mpi_lock); 313 mpi = ibdev->port[port_num - 1].mp.mpi; 314 if (mpi->is_master) 315 goto out; 316 317 mpi->mdev_refcnt--; 318 if (mpi->unaffiliate) 319 complete(&mpi->unref_comp); 320 out: 321 spin_unlock(&port->mp.mpi_lock); 322 } 323 324 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 325 u16 *active_speed, u8 *active_width) 326 { 327 switch (eth_proto_oper) { 328 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 329 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 330 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 332 *active_width = IB_WIDTH_1X; 333 *active_speed = IB_SPEED_SDR; 334 break; 335 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 336 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_QDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 346 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 348 *active_width = IB_WIDTH_1X; 349 *active_speed = IB_SPEED_EDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 352 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 355 *active_width = IB_WIDTH_4X; 356 *active_speed = IB_SPEED_QDR; 357 break; 358 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 359 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 361 *active_width = IB_WIDTH_1X; 362 *active_speed = IB_SPEED_HDR; 363 break; 364 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_FDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 369 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 372 *active_width = IB_WIDTH_4X; 373 *active_speed = IB_SPEED_EDR; 374 break; 375 default: 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 383 u8 *active_width) 384 { 385 switch (eth_proto_oper) { 386 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 392 *active_width = IB_WIDTH_1X; 393 *active_speed = IB_SPEED_DDR; 394 break; 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 400 *active_width = IB_WIDTH_4X; 401 *active_speed = IB_SPEED_QDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 408 *active_width = IB_WIDTH_2X; 409 *active_speed = IB_SPEED_EDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 412 *active_width = IB_WIDTH_1X; 413 *active_speed = IB_SPEED_HDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 416 *active_width = IB_WIDTH_4X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_HDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_NDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_HDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_NDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 436 *active_width = IB_WIDTH_4X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 447 u8 *active_width, bool ext) 448 { 449 return ext ? 450 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 451 active_width) : 452 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 453 active_width); 454 } 455 456 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 457 struct ib_port_attr *props) 458 { 459 struct mlx5_ib_dev *dev = to_mdev(device); 460 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 461 struct mlx5_core_dev *mdev; 462 struct net_device *ndev, *upper; 463 enum ib_mtu ndev_ib_mtu; 464 bool put_mdev = true; 465 u32 eth_prot_oper; 466 u8 mdev_port_num; 467 bool ext; 468 int err; 469 470 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 471 if (!mdev) { 472 /* This means the port isn't affiliated yet. Get the 473 * info for the master port instead. 474 */ 475 put_mdev = false; 476 mdev = dev->mdev; 477 mdev_port_num = 1; 478 port_num = 1; 479 } 480 481 /* Possible bad flows are checked before filling out props so in case 482 * of an error it will still be zeroed out. 483 * Use native port in case of reps 484 */ 485 if (dev->is_rep) 486 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 487 1); 488 else 489 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 490 mdev_port_num); 491 if (err) 492 goto out; 493 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 494 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 495 496 props->active_width = IB_WIDTH_4X; 497 props->active_speed = IB_SPEED_QDR; 498 499 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 500 &props->active_width, ext); 501 502 if (!dev->is_rep && mlx5_is_roce_enabled(mdev)) { 503 u16 qkey_viol_cntr; 504 505 props->port_cap_flags |= IB_PORT_CM_SUP; 506 props->ip_gids = true; 507 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 508 roce_address_table_size); 509 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 510 props->qkey_viol_cntr = qkey_viol_cntr; 511 } 512 props->max_mtu = IB_MTU_4096; 513 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 514 props->pkey_tbl_len = 1; 515 props->state = IB_PORT_DOWN; 516 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 517 518 /* If this is a stub query for an unaffiliated port stop here */ 519 if (!put_mdev) 520 goto out; 521 522 ndev = mlx5_ib_get_netdev(device, port_num); 523 if (!ndev) 524 goto out; 525 526 if (dev->lag_active) { 527 rcu_read_lock(); 528 upper = netdev_master_upper_dev_get_rcu(ndev); 529 if (upper) { 530 dev_put(ndev); 531 ndev = upper; 532 dev_hold(ndev); 533 } 534 rcu_read_unlock(); 535 } 536 537 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 538 props->state = IB_PORT_ACTIVE; 539 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 540 } 541 542 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 543 544 dev_put(ndev); 545 546 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 547 out: 548 if (put_mdev) 549 mlx5_ib_put_native_port_mdev(dev, port_num); 550 return err; 551 } 552 553 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 554 unsigned int index, const union ib_gid *gid, 555 const struct ib_gid_attr *attr) 556 { 557 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 558 u16 vlan_id = 0xffff; 559 u8 roce_version = 0; 560 u8 roce_l3_type = 0; 561 u8 mac[ETH_ALEN]; 562 int ret; 563 564 if (gid) { 565 gid_type = attr->gid_type; 566 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 567 if (ret) 568 return ret; 569 } 570 571 switch (gid_type) { 572 case IB_GID_TYPE_ROCE: 573 roce_version = MLX5_ROCE_VERSION_1; 574 break; 575 case IB_GID_TYPE_ROCE_UDP_ENCAP: 576 roce_version = MLX5_ROCE_VERSION_2; 577 if (ipv6_addr_v4mapped((void *)gid)) 578 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 579 else 580 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 581 break; 582 583 default: 584 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 585 } 586 587 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 588 roce_l3_type, gid->raw, mac, 589 vlan_id < VLAN_CFI_MASK, vlan_id, 590 port_num); 591 } 592 593 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 594 __always_unused void **context) 595 { 596 return set_roce_addr(to_mdev(attr->device), attr->port_num, 597 attr->index, &attr->gid, attr); 598 } 599 600 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 601 __always_unused void **context) 602 { 603 return set_roce_addr(to_mdev(attr->device), attr->port_num, 604 attr->index, NULL, NULL); 605 } 606 607 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 608 const struct ib_gid_attr *attr) 609 { 610 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 611 return 0; 612 613 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 614 } 615 616 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 617 { 618 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 619 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 620 return 0; 621 } 622 623 enum { 624 MLX5_VPORT_ACCESS_METHOD_MAD, 625 MLX5_VPORT_ACCESS_METHOD_HCA, 626 MLX5_VPORT_ACCESS_METHOD_NIC, 627 }; 628 629 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 630 { 631 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 632 return MLX5_VPORT_ACCESS_METHOD_MAD; 633 634 if (mlx5_ib_port_link_layer(ibdev, 1) == 635 IB_LINK_LAYER_ETHERNET) 636 return MLX5_VPORT_ACCESS_METHOD_NIC; 637 638 return MLX5_VPORT_ACCESS_METHOD_HCA; 639 } 640 641 static void get_atomic_caps(struct mlx5_ib_dev *dev, 642 u8 atomic_size_qp, 643 struct ib_device_attr *props) 644 { 645 u8 tmp; 646 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 647 u8 atomic_req_8B_endianness_mode = 648 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 649 650 /* Check if HW supports 8 bytes standard atomic operations and capable 651 * of host endianness respond 652 */ 653 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 654 if (((atomic_operations & tmp) == tmp) && 655 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 656 (atomic_req_8B_endianness_mode)) { 657 props->atomic_cap = IB_ATOMIC_HCA; 658 } else { 659 props->atomic_cap = IB_ATOMIC_NONE; 660 } 661 } 662 663 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 664 struct ib_device_attr *props) 665 { 666 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 667 668 get_atomic_caps(dev, atomic_size_qp, props); 669 } 670 671 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 672 __be64 *sys_image_guid) 673 { 674 struct mlx5_ib_dev *dev = to_mdev(ibdev); 675 struct mlx5_core_dev *mdev = dev->mdev; 676 u64 tmp; 677 int err; 678 679 switch (mlx5_get_vport_access_method(ibdev)) { 680 case MLX5_VPORT_ACCESS_METHOD_MAD: 681 return mlx5_query_mad_ifc_system_image_guid(ibdev, 682 sys_image_guid); 683 684 case MLX5_VPORT_ACCESS_METHOD_HCA: 685 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 686 break; 687 688 case MLX5_VPORT_ACCESS_METHOD_NIC: 689 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 690 break; 691 692 default: 693 return -EINVAL; 694 } 695 696 if (!err) 697 *sys_image_guid = cpu_to_be64(tmp); 698 699 return err; 700 701 } 702 703 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 704 u16 *max_pkeys) 705 { 706 struct mlx5_ib_dev *dev = to_mdev(ibdev); 707 struct mlx5_core_dev *mdev = dev->mdev; 708 709 switch (mlx5_get_vport_access_method(ibdev)) { 710 case MLX5_VPORT_ACCESS_METHOD_MAD: 711 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 712 713 case MLX5_VPORT_ACCESS_METHOD_HCA: 714 case MLX5_VPORT_ACCESS_METHOD_NIC: 715 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 716 pkey_table_size)); 717 return 0; 718 719 default: 720 return -EINVAL; 721 } 722 } 723 724 static int mlx5_query_vendor_id(struct ib_device *ibdev, 725 u32 *vendor_id) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 729 switch (mlx5_get_vport_access_method(ibdev)) { 730 case MLX5_VPORT_ACCESS_METHOD_MAD: 731 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 732 733 case MLX5_VPORT_ACCESS_METHOD_HCA: 734 case MLX5_VPORT_ACCESS_METHOD_NIC: 735 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 736 737 default: 738 return -EINVAL; 739 } 740 } 741 742 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 743 __be64 *node_guid) 744 { 745 u64 tmp; 746 int err; 747 748 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 749 case MLX5_VPORT_ACCESS_METHOD_MAD: 750 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 751 752 case MLX5_VPORT_ACCESS_METHOD_HCA: 753 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 754 break; 755 756 case MLX5_VPORT_ACCESS_METHOD_NIC: 757 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 758 break; 759 760 default: 761 return -EINVAL; 762 } 763 764 if (!err) 765 *node_guid = cpu_to_be64(tmp); 766 767 return err; 768 } 769 770 struct mlx5_reg_node_desc { 771 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 772 }; 773 774 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 775 { 776 struct mlx5_reg_node_desc in; 777 778 if (mlx5_use_mad_ifc(dev)) 779 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 780 781 memset(&in, 0, sizeof(in)); 782 783 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 784 sizeof(struct mlx5_reg_node_desc), 785 MLX5_REG_NODE_DESC, 0, 0); 786 } 787 788 static int mlx5_ib_query_device(struct ib_device *ibdev, 789 struct ib_device_attr *props, 790 struct ib_udata *uhw) 791 { 792 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 793 struct mlx5_ib_dev *dev = to_mdev(ibdev); 794 struct mlx5_core_dev *mdev = dev->mdev; 795 int err = -ENOMEM; 796 int max_sq_desc; 797 int max_rq_sg; 798 int max_sq_sg; 799 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 800 bool raw_support = !mlx5_core_mp_enabled(mdev); 801 struct mlx5_ib_query_device_resp resp = {}; 802 size_t resp_len; 803 u64 max_tso; 804 805 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 806 if (uhw_outlen && uhw_outlen < resp_len) 807 return -EINVAL; 808 809 resp.response_length = resp_len; 810 811 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 812 return -EINVAL; 813 814 memset(props, 0, sizeof(*props)); 815 err = mlx5_query_system_image_guid(ibdev, 816 &props->sys_image_guid); 817 if (err) 818 return err; 819 820 props->max_pkeys = dev->pkey_table_len; 821 822 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 823 if (err) 824 return err; 825 826 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 827 (fw_rev_min(dev->mdev) << 16) | 828 fw_rev_sub(dev->mdev); 829 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 830 IB_DEVICE_PORT_ACTIVE_EVENT | 831 IB_DEVICE_SYS_IMAGE_GUID | 832 IB_DEVICE_RC_RNR_NAK_GEN; 833 834 if (MLX5_CAP_GEN(mdev, pkv)) 835 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 836 if (MLX5_CAP_GEN(mdev, qkv)) 837 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 838 if (MLX5_CAP_GEN(mdev, apm)) 839 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 840 if (MLX5_CAP_GEN(mdev, xrc)) 841 props->device_cap_flags |= IB_DEVICE_XRC; 842 if (MLX5_CAP_GEN(mdev, imaicl)) { 843 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 844 IB_DEVICE_MEM_WINDOW_TYPE_2B; 845 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 846 /* We support 'Gappy' memory registration too */ 847 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 848 } 849 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 850 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 851 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 852 if (MLX5_CAP_GEN(mdev, sho)) { 853 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 854 /* At this stage no support for signature handover */ 855 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 856 IB_PROT_T10DIF_TYPE_2 | 857 IB_PROT_T10DIF_TYPE_3; 858 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 859 IB_GUARD_T10DIF_CSUM; 860 } 861 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 862 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 863 864 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 865 if (MLX5_CAP_ETH(mdev, csum_cap)) { 866 /* Legacy bit to support old userspace libraries */ 867 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 868 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 869 } 870 871 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 872 props->raw_packet_caps |= 873 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 874 875 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 876 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 877 if (max_tso) { 878 resp.tso_caps.max_tso = 1 << max_tso; 879 resp.tso_caps.supported_qpts |= 880 1 << IB_QPT_RAW_PACKET; 881 resp.response_length += sizeof(resp.tso_caps); 882 } 883 } 884 885 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 886 resp.rss_caps.rx_hash_function = 887 MLX5_RX_HASH_FUNC_TOEPLITZ; 888 resp.rss_caps.rx_hash_fields_mask = 889 MLX5_RX_HASH_SRC_IPV4 | 890 MLX5_RX_HASH_DST_IPV4 | 891 MLX5_RX_HASH_SRC_IPV6 | 892 MLX5_RX_HASH_DST_IPV6 | 893 MLX5_RX_HASH_SRC_PORT_TCP | 894 MLX5_RX_HASH_DST_PORT_TCP | 895 MLX5_RX_HASH_SRC_PORT_UDP | 896 MLX5_RX_HASH_DST_PORT_UDP | 897 MLX5_RX_HASH_INNER; 898 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 899 MLX5_ACCEL_IPSEC_CAP_DEVICE) 900 resp.rss_caps.rx_hash_fields_mask |= 901 MLX5_RX_HASH_IPSEC_SPI; 902 resp.response_length += sizeof(resp.rss_caps); 903 } 904 } else { 905 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 906 resp.response_length += sizeof(resp.tso_caps); 907 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 908 resp.response_length += sizeof(resp.rss_caps); 909 } 910 911 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 912 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 913 props->device_cap_flags |= IB_DEVICE_UD_TSO; 914 } 915 916 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 917 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 918 raw_support) 919 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 920 921 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 922 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 923 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 924 925 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 926 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 927 raw_support) { 928 /* Legacy bit to support old userspace libraries */ 929 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 930 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 931 } 932 933 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 934 props->max_dm_size = 935 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 936 } 937 938 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 939 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 940 941 if (MLX5_CAP_GEN(mdev, end_pad)) 942 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 943 944 props->vendor_part_id = mdev->pdev->device; 945 props->hw_ver = mdev->pdev->revision; 946 947 props->max_mr_size = ~0ull; 948 props->page_size_cap = ~(min_page_size - 1); 949 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 950 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 951 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 952 sizeof(struct mlx5_wqe_data_seg); 953 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 954 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 955 sizeof(struct mlx5_wqe_raddr_seg)) / 956 sizeof(struct mlx5_wqe_data_seg); 957 props->max_send_sge = max_sq_sg; 958 props->max_recv_sge = max_rq_sg; 959 props->max_sge_rd = MLX5_MAX_SGE_RD; 960 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 961 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 962 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 963 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 964 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 965 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 966 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 967 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 968 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 969 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 970 props->max_srq_sge = max_rq_sg - 1; 971 props->max_fast_reg_page_list_len = 972 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 973 props->max_pi_fast_reg_page_list_len = 974 props->max_fast_reg_page_list_len / 2; 975 props->max_sgl_rd = 976 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 977 get_atomic_caps_qp(dev, props); 978 props->masked_atomic_cap = IB_ATOMIC_NONE; 979 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 980 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 981 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 982 props->max_mcast_grp; 983 props->max_ah = INT_MAX; 984 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 985 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 986 987 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 988 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 989 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 990 props->odp_caps = dev->odp_caps; 991 if (!uhw) { 992 /* ODP for kernel QPs is not implemented for receive 993 * WQEs and SRQ WQEs 994 */ 995 props->odp_caps.per_transport_caps.rc_odp_caps &= 996 ~(IB_ODP_SUPPORT_READ | 997 IB_ODP_SUPPORT_SRQ_RECV); 998 props->odp_caps.per_transport_caps.uc_odp_caps &= 999 ~(IB_ODP_SUPPORT_READ | 1000 IB_ODP_SUPPORT_SRQ_RECV); 1001 props->odp_caps.per_transport_caps.ud_odp_caps &= 1002 ~(IB_ODP_SUPPORT_READ | 1003 IB_ODP_SUPPORT_SRQ_RECV); 1004 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1005 ~(IB_ODP_SUPPORT_READ | 1006 IB_ODP_SUPPORT_SRQ_RECV); 1007 } 1008 } 1009 1010 if (MLX5_CAP_GEN(mdev, cd)) 1011 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1012 1013 if (mlx5_core_is_vf(mdev)) 1014 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1015 1016 if (mlx5_ib_port_link_layer(ibdev, 1) == 1017 IB_LINK_LAYER_ETHERNET && raw_support) { 1018 props->rss_caps.max_rwq_indirection_tables = 1019 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1020 props->rss_caps.max_rwq_indirection_table_size = 1021 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1022 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1023 props->max_wq_type_rq = 1024 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1025 } 1026 1027 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1028 props->tm_caps.max_num_tags = 1029 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1030 props->tm_caps.max_ops = 1031 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1032 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1033 } 1034 1035 if (MLX5_CAP_GEN(mdev, tag_matching) && 1036 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1037 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1038 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1039 } 1040 1041 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1042 props->cq_caps.max_cq_moderation_count = 1043 MLX5_MAX_CQ_COUNT; 1044 props->cq_caps.max_cq_moderation_period = 1045 MLX5_MAX_CQ_PERIOD; 1046 } 1047 1048 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1049 resp.response_length += sizeof(resp.cqe_comp_caps); 1050 1051 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1052 resp.cqe_comp_caps.max_num = 1053 MLX5_CAP_GEN(dev->mdev, 1054 cqe_compression_max_num); 1055 1056 resp.cqe_comp_caps.supported_format = 1057 MLX5_IB_CQE_RES_FORMAT_HASH | 1058 MLX5_IB_CQE_RES_FORMAT_CSUM; 1059 1060 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1061 resp.cqe_comp_caps.supported_format |= 1062 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1063 } 1064 } 1065 1066 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1067 raw_support) { 1068 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1069 MLX5_CAP_GEN(mdev, qos)) { 1070 resp.packet_pacing_caps.qp_rate_limit_max = 1071 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1072 resp.packet_pacing_caps.qp_rate_limit_min = 1073 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1074 resp.packet_pacing_caps.supported_qpts |= 1075 1 << IB_QPT_RAW_PACKET; 1076 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1077 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1078 resp.packet_pacing_caps.cap_flags |= 1079 MLX5_IB_PP_SUPPORT_BURST; 1080 } 1081 resp.response_length += sizeof(resp.packet_pacing_caps); 1082 } 1083 1084 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1085 uhw_outlen) { 1086 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1087 resp.mlx5_ib_support_multi_pkt_send_wqes = 1088 MLX5_IB_ALLOW_MPW; 1089 1090 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1091 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1092 MLX5_IB_SUPPORT_EMPW; 1093 1094 resp.response_length += 1095 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1096 } 1097 1098 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1099 resp.response_length += sizeof(resp.flags); 1100 1101 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1102 resp.flags |= 1103 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1104 1105 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1106 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1107 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1108 resp.flags |= 1109 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1110 1111 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1112 } 1113 1114 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1115 resp.response_length += sizeof(resp.sw_parsing_caps); 1116 if (MLX5_CAP_ETH(mdev, swp)) { 1117 resp.sw_parsing_caps.sw_parsing_offloads |= 1118 MLX5_IB_SW_PARSING; 1119 1120 if (MLX5_CAP_ETH(mdev, swp_csum)) 1121 resp.sw_parsing_caps.sw_parsing_offloads |= 1122 MLX5_IB_SW_PARSING_CSUM; 1123 1124 if (MLX5_CAP_ETH(mdev, swp_lso)) 1125 resp.sw_parsing_caps.sw_parsing_offloads |= 1126 MLX5_IB_SW_PARSING_LSO; 1127 1128 if (resp.sw_parsing_caps.sw_parsing_offloads) 1129 resp.sw_parsing_caps.supported_qpts = 1130 BIT(IB_QPT_RAW_PACKET); 1131 } 1132 } 1133 1134 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1135 raw_support) { 1136 resp.response_length += sizeof(resp.striding_rq_caps); 1137 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1138 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1139 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1140 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1141 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1142 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1143 resp.striding_rq_caps 1144 .min_single_wqe_log_num_of_strides = 1145 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1146 else 1147 resp.striding_rq_caps 1148 .min_single_wqe_log_num_of_strides = 1149 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1150 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1151 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1152 resp.striding_rq_caps.supported_qpts = 1153 BIT(IB_QPT_RAW_PACKET); 1154 } 1155 } 1156 1157 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1158 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1159 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1160 resp.tunnel_offloads_caps |= 1161 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1162 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1163 resp.tunnel_offloads_caps |= 1164 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1165 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1166 resp.tunnel_offloads_caps |= 1167 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1168 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1169 resp.tunnel_offloads_caps |= 1170 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1171 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1172 resp.tunnel_offloads_caps |= 1173 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1174 } 1175 1176 if (uhw_outlen) { 1177 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1178 1179 if (err) 1180 return err; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1187 u8 *ib_width) 1188 { 1189 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1190 1191 if (active_width & MLX5_PTYS_WIDTH_1X) 1192 *ib_width = IB_WIDTH_1X; 1193 else if (active_width & MLX5_PTYS_WIDTH_2X) 1194 *ib_width = IB_WIDTH_2X; 1195 else if (active_width & MLX5_PTYS_WIDTH_4X) 1196 *ib_width = IB_WIDTH_4X; 1197 else if (active_width & MLX5_PTYS_WIDTH_8X) 1198 *ib_width = IB_WIDTH_8X; 1199 else if (active_width & MLX5_PTYS_WIDTH_12X) 1200 *ib_width = IB_WIDTH_12X; 1201 else { 1202 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1203 active_width); 1204 *ib_width = IB_WIDTH_4X; 1205 } 1206 1207 return; 1208 } 1209 1210 static int mlx5_mtu_to_ib_mtu(int mtu) 1211 { 1212 switch (mtu) { 1213 case 256: return 1; 1214 case 512: return 2; 1215 case 1024: return 3; 1216 case 2048: return 4; 1217 case 4096: return 5; 1218 default: 1219 pr_warn("invalid mtu\n"); 1220 return -1; 1221 } 1222 } 1223 1224 enum ib_max_vl_num { 1225 __IB_MAX_VL_0 = 1, 1226 __IB_MAX_VL_0_1 = 2, 1227 __IB_MAX_VL_0_3 = 3, 1228 __IB_MAX_VL_0_7 = 4, 1229 __IB_MAX_VL_0_14 = 5, 1230 }; 1231 1232 enum mlx5_vl_hw_cap { 1233 MLX5_VL_HW_0 = 1, 1234 MLX5_VL_HW_0_1 = 2, 1235 MLX5_VL_HW_0_2 = 3, 1236 MLX5_VL_HW_0_3 = 4, 1237 MLX5_VL_HW_0_4 = 5, 1238 MLX5_VL_HW_0_5 = 6, 1239 MLX5_VL_HW_0_6 = 7, 1240 MLX5_VL_HW_0_7 = 8, 1241 MLX5_VL_HW_0_14 = 15 1242 }; 1243 1244 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1245 u8 *max_vl_num) 1246 { 1247 switch (vl_hw_cap) { 1248 case MLX5_VL_HW_0: 1249 *max_vl_num = __IB_MAX_VL_0; 1250 break; 1251 case MLX5_VL_HW_0_1: 1252 *max_vl_num = __IB_MAX_VL_0_1; 1253 break; 1254 case MLX5_VL_HW_0_3: 1255 *max_vl_num = __IB_MAX_VL_0_3; 1256 break; 1257 case MLX5_VL_HW_0_7: 1258 *max_vl_num = __IB_MAX_VL_0_7; 1259 break; 1260 case MLX5_VL_HW_0_14: 1261 *max_vl_num = __IB_MAX_VL_0_14; 1262 break; 1263 1264 default: 1265 return -EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1272 struct ib_port_attr *props) 1273 { 1274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1275 struct mlx5_core_dev *mdev = dev->mdev; 1276 struct mlx5_hca_vport_context *rep; 1277 u16 max_mtu; 1278 u16 oper_mtu; 1279 int err; 1280 u16 ib_link_width_oper; 1281 u8 vl_hw_cap; 1282 1283 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1284 if (!rep) { 1285 err = -ENOMEM; 1286 goto out; 1287 } 1288 1289 /* props being zeroed by the caller, avoid zeroing it here */ 1290 1291 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1292 if (err) 1293 goto out; 1294 1295 props->lid = rep->lid; 1296 props->lmc = rep->lmc; 1297 props->sm_lid = rep->sm_lid; 1298 props->sm_sl = rep->sm_sl; 1299 props->state = rep->vport_state; 1300 props->phys_state = rep->port_physical_state; 1301 props->port_cap_flags = rep->cap_mask1; 1302 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1303 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1304 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1305 props->bad_pkey_cntr = rep->pkey_violation_counter; 1306 props->qkey_viol_cntr = rep->qkey_violation_counter; 1307 props->subnet_timeout = rep->subnet_timeout; 1308 props->init_type_reply = rep->init_type_reply; 1309 1310 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1311 props->port_cap_flags2 = rep->cap_mask2; 1312 1313 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1314 &props->active_speed, port); 1315 if (err) 1316 goto out; 1317 1318 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1319 1320 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1321 1322 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1323 1324 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1325 1326 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1327 1328 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1329 if (err) 1330 goto out; 1331 1332 err = translate_max_vl_num(ibdev, vl_hw_cap, 1333 &props->max_vl_num); 1334 out: 1335 kfree(rep); 1336 return err; 1337 } 1338 1339 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1340 struct ib_port_attr *props) 1341 { 1342 unsigned int count; 1343 int ret; 1344 1345 switch (mlx5_get_vport_access_method(ibdev)) { 1346 case MLX5_VPORT_ACCESS_METHOD_MAD: 1347 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1348 break; 1349 1350 case MLX5_VPORT_ACCESS_METHOD_HCA: 1351 ret = mlx5_query_hca_port(ibdev, port, props); 1352 break; 1353 1354 case MLX5_VPORT_ACCESS_METHOD_NIC: 1355 ret = mlx5_query_port_roce(ibdev, port, props); 1356 break; 1357 1358 default: 1359 ret = -EINVAL; 1360 } 1361 1362 if (!ret && props) { 1363 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1364 struct mlx5_core_dev *mdev; 1365 bool put_mdev = true; 1366 1367 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1368 if (!mdev) { 1369 /* If the port isn't affiliated yet query the master. 1370 * The master and slave will have the same values. 1371 */ 1372 mdev = dev->mdev; 1373 port = 1; 1374 put_mdev = false; 1375 } 1376 count = mlx5_core_reserved_gids_count(mdev); 1377 if (put_mdev) 1378 mlx5_ib_put_native_port_mdev(dev, port); 1379 props->gid_tbl_len -= count; 1380 } 1381 return ret; 1382 } 1383 1384 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1385 struct ib_port_attr *props) 1386 { 1387 return mlx5_query_port_roce(ibdev, port, props); 1388 } 1389 1390 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1391 u16 *pkey) 1392 { 1393 /* Default special Pkey for representor device port as per the 1394 * IB specification 1.3 section 10.9.1.2. 1395 */ 1396 *pkey = 0xffff; 1397 return 0; 1398 } 1399 1400 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1401 union ib_gid *gid) 1402 { 1403 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1404 struct mlx5_core_dev *mdev = dev->mdev; 1405 1406 switch (mlx5_get_vport_access_method(ibdev)) { 1407 case MLX5_VPORT_ACCESS_METHOD_MAD: 1408 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1409 1410 case MLX5_VPORT_ACCESS_METHOD_HCA: 1411 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1412 1413 default: 1414 return -EINVAL; 1415 } 1416 1417 } 1418 1419 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1420 u16 index, u16 *pkey) 1421 { 1422 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1423 struct mlx5_core_dev *mdev; 1424 bool put_mdev = true; 1425 u8 mdev_port_num; 1426 int err; 1427 1428 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1429 if (!mdev) { 1430 /* The port isn't affiliated yet, get the PKey from the master 1431 * port. For RoCE the PKey tables will be the same. 1432 */ 1433 put_mdev = false; 1434 mdev = dev->mdev; 1435 mdev_port_num = 1; 1436 } 1437 1438 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1439 index, pkey); 1440 if (put_mdev) 1441 mlx5_ib_put_native_port_mdev(dev, port); 1442 1443 return err; 1444 } 1445 1446 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1447 u16 *pkey) 1448 { 1449 switch (mlx5_get_vport_access_method(ibdev)) { 1450 case MLX5_VPORT_ACCESS_METHOD_MAD: 1451 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1452 1453 case MLX5_VPORT_ACCESS_METHOD_HCA: 1454 case MLX5_VPORT_ACCESS_METHOD_NIC: 1455 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1456 default: 1457 return -EINVAL; 1458 } 1459 } 1460 1461 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1462 struct ib_device_modify *props) 1463 { 1464 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1465 struct mlx5_reg_node_desc in; 1466 struct mlx5_reg_node_desc out; 1467 int err; 1468 1469 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1470 return -EOPNOTSUPP; 1471 1472 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1473 return 0; 1474 1475 /* 1476 * If possible, pass node desc to FW, so it can generate 1477 * a 144 trap. If cmd fails, just ignore. 1478 */ 1479 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1480 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1481 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1482 if (err) 1483 return err; 1484 1485 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1486 1487 return err; 1488 } 1489 1490 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1491 u32 value) 1492 { 1493 struct mlx5_hca_vport_context ctx = {}; 1494 struct mlx5_core_dev *mdev; 1495 u8 mdev_port_num; 1496 int err; 1497 1498 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1499 if (!mdev) 1500 return -ENODEV; 1501 1502 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1503 if (err) 1504 goto out; 1505 1506 if (~ctx.cap_mask1_perm & mask) { 1507 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1508 mask, ctx.cap_mask1_perm); 1509 err = -EINVAL; 1510 goto out; 1511 } 1512 1513 ctx.cap_mask1 = value; 1514 ctx.cap_mask1_perm = mask; 1515 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1516 0, &ctx); 1517 1518 out: 1519 mlx5_ib_put_native_port_mdev(dev, port_num); 1520 1521 return err; 1522 } 1523 1524 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1525 struct ib_port_modify *props) 1526 { 1527 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1528 struct ib_port_attr attr; 1529 u32 tmp; 1530 int err; 1531 u32 change_mask; 1532 u32 value; 1533 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1534 IB_LINK_LAYER_INFINIBAND); 1535 1536 /* CM layer calls ib_modify_port() regardless of the link layer. For 1537 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1538 */ 1539 if (!is_ib) 1540 return 0; 1541 1542 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1543 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1544 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1545 return set_port_caps_atomic(dev, port, change_mask, value); 1546 } 1547 1548 mutex_lock(&dev->cap_mask_mutex); 1549 1550 err = ib_query_port(ibdev, port, &attr); 1551 if (err) 1552 goto out; 1553 1554 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1555 ~props->clr_port_cap_mask; 1556 1557 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1558 1559 out: 1560 mutex_unlock(&dev->cap_mask_mutex); 1561 return err; 1562 } 1563 1564 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1565 { 1566 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1567 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1568 } 1569 1570 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1571 { 1572 /* Large page with non 4k uar support might limit the dynamic size */ 1573 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1574 return MLX5_MIN_DYN_BFREGS; 1575 1576 return MLX5_MAX_DYN_BFREGS; 1577 } 1578 1579 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1580 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1581 struct mlx5_bfreg_info *bfregi) 1582 { 1583 int uars_per_sys_page; 1584 int bfregs_per_sys_page; 1585 int ref_bfregs = req->total_num_bfregs; 1586 1587 if (req->total_num_bfregs == 0) 1588 return -EINVAL; 1589 1590 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1591 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1592 1593 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1594 return -ENOMEM; 1595 1596 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1597 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1598 /* This holds the required static allocation asked by the user */ 1599 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1600 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1601 return -EINVAL; 1602 1603 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1604 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1605 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1606 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1607 1608 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1609 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1610 lib_uar_4k ? "yes" : "no", ref_bfregs, 1611 req->total_num_bfregs, bfregi->total_num_bfregs, 1612 bfregi->num_sys_pages); 1613 1614 return 0; 1615 } 1616 1617 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1618 { 1619 struct mlx5_bfreg_info *bfregi; 1620 int err; 1621 int i; 1622 1623 bfregi = &context->bfregi; 1624 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1625 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1626 if (err) 1627 goto error; 1628 1629 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1630 } 1631 1632 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1633 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1634 1635 return 0; 1636 1637 error: 1638 for (--i; i >= 0; i--) 1639 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1640 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1641 1642 return err; 1643 } 1644 1645 static void deallocate_uars(struct mlx5_ib_dev *dev, 1646 struct mlx5_ib_ucontext *context) 1647 { 1648 struct mlx5_bfreg_info *bfregi; 1649 int i; 1650 1651 bfregi = &context->bfregi; 1652 for (i = 0; i < bfregi->num_sys_pages; i++) 1653 if (i < bfregi->num_static_sys_pages || 1654 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1655 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1656 } 1657 1658 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1659 { 1660 int err = 0; 1661 1662 mutex_lock(&dev->lb.mutex); 1663 if (td) 1664 dev->lb.user_td++; 1665 if (qp) 1666 dev->lb.qps++; 1667 1668 if (dev->lb.user_td == 2 || 1669 dev->lb.qps == 1) { 1670 if (!dev->lb.enabled) { 1671 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1672 dev->lb.enabled = true; 1673 } 1674 } 1675 1676 mutex_unlock(&dev->lb.mutex); 1677 1678 return err; 1679 } 1680 1681 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1682 { 1683 mutex_lock(&dev->lb.mutex); 1684 if (td) 1685 dev->lb.user_td--; 1686 if (qp) 1687 dev->lb.qps--; 1688 1689 if (dev->lb.user_td == 1 && 1690 dev->lb.qps == 0) { 1691 if (dev->lb.enabled) { 1692 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1693 dev->lb.enabled = false; 1694 } 1695 } 1696 1697 mutex_unlock(&dev->lb.mutex); 1698 } 1699 1700 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1701 u16 uid) 1702 { 1703 int err; 1704 1705 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1706 return 0; 1707 1708 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1709 if (err) 1710 return err; 1711 1712 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1713 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1714 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1715 return err; 1716 1717 return mlx5_ib_enable_lb(dev, true, false); 1718 } 1719 1720 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1721 u16 uid) 1722 { 1723 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1724 return; 1725 1726 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1727 1728 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1729 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1730 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1731 return; 1732 1733 mlx5_ib_disable_lb(dev, true, false); 1734 } 1735 1736 static int set_ucontext_resp(struct ib_ucontext *uctx, 1737 struct mlx5_ib_alloc_ucontext_resp *resp) 1738 { 1739 struct ib_device *ibdev = uctx->device; 1740 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1741 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1742 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1743 int err; 1744 1745 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1746 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1747 &resp->dump_fill_mkey); 1748 if (err) 1749 return err; 1750 resp->comp_mask |= 1751 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1752 } 1753 1754 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1755 if (dev->wc_support) 1756 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1757 log_bf_reg_size); 1758 resp->cache_line_size = cache_line_size(); 1759 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1760 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1761 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1762 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1763 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1764 resp->cqe_version = context->cqe_version; 1765 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1766 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1767 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1768 MLX5_CAP_GEN(dev->mdev, 1769 num_of_uars_per_page) : 1; 1770 1771 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1772 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1773 if (mlx5_get_flow_namespace(dev->mdev, 1774 MLX5_FLOW_NAMESPACE_EGRESS)) 1775 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1776 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1777 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1778 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1779 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1780 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1781 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1782 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1783 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1784 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1785 } 1786 1787 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1788 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1789 resp->num_ports = dev->num_ports; 1790 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1791 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1792 1793 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1794 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1795 resp->eth_min_inline++; 1796 } 1797 1798 if (dev->mdev->clock_info) 1799 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1800 1801 /* 1802 * We don't want to expose information from the PCI bar that is located 1803 * after 4096 bytes, so if the arch only supports larger pages, let's 1804 * pretend we don't support reading the HCA's core clock. This is also 1805 * forced by mmap function. 1806 */ 1807 if (PAGE_SIZE <= 4096) { 1808 resp->comp_mask |= 1809 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1810 resp->hca_core_clock_offset = 1811 offsetof(struct mlx5_init_seg, 1812 internal_timer_h) % PAGE_SIZE; 1813 } 1814 1815 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1816 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1817 1818 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1819 return 0; 1820 } 1821 1822 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1823 struct ib_udata *udata) 1824 { 1825 struct ib_device *ibdev = uctx->device; 1826 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1827 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1828 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1829 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1830 struct mlx5_bfreg_info *bfregi; 1831 int ver; 1832 int err; 1833 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1834 max_cqe_version); 1835 bool lib_uar_4k; 1836 bool lib_uar_dyn; 1837 1838 if (!dev->ib_active) 1839 return -EAGAIN; 1840 1841 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1842 ver = 0; 1843 else if (udata->inlen >= min_req_v2) 1844 ver = 2; 1845 else 1846 return -EINVAL; 1847 1848 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1849 if (err) 1850 return err; 1851 1852 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1853 return -EOPNOTSUPP; 1854 1855 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1856 return -EOPNOTSUPP; 1857 1858 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1859 MLX5_NON_FP_BFREGS_PER_UAR); 1860 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1861 return -EINVAL; 1862 1863 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1864 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1865 bfregi = &context->bfregi; 1866 1867 if (lib_uar_dyn) { 1868 bfregi->lib_uar_dyn = lib_uar_dyn; 1869 goto uar_done; 1870 } 1871 1872 /* updates req->total_num_bfregs */ 1873 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1874 if (err) 1875 goto out_ctx; 1876 1877 mutex_init(&bfregi->lock); 1878 bfregi->lib_uar_4k = lib_uar_4k; 1879 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1880 GFP_KERNEL); 1881 if (!bfregi->count) { 1882 err = -ENOMEM; 1883 goto out_ctx; 1884 } 1885 1886 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1887 sizeof(*bfregi->sys_pages), 1888 GFP_KERNEL); 1889 if (!bfregi->sys_pages) { 1890 err = -ENOMEM; 1891 goto out_count; 1892 } 1893 1894 err = allocate_uars(dev, context); 1895 if (err) 1896 goto out_sys_pages; 1897 1898 uar_done: 1899 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1900 err = mlx5_ib_devx_create(dev, true); 1901 if (err < 0) 1902 goto out_uars; 1903 context->devx_uid = err; 1904 } 1905 1906 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1907 context->devx_uid); 1908 if (err) 1909 goto out_devx; 1910 1911 INIT_LIST_HEAD(&context->db_page_list); 1912 mutex_init(&context->db_page_mutex); 1913 1914 context->cqe_version = min_t(__u8, 1915 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1916 req.max_cqe_version); 1917 1918 err = set_ucontext_resp(uctx, &resp); 1919 if (err) 1920 goto out_mdev; 1921 1922 resp.response_length = min(udata->outlen, sizeof(resp)); 1923 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1924 if (err) 1925 goto out_mdev; 1926 1927 bfregi->ver = ver; 1928 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1929 context->lib_caps = req.lib_caps; 1930 print_lib_caps(dev, context->lib_caps); 1931 1932 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1933 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1934 1935 atomic_set(&context->tx_port_affinity, 1936 atomic_add_return( 1937 1, &dev->port[port].roce.tx_port_affinity)); 1938 } 1939 1940 return 0; 1941 1942 out_mdev: 1943 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1944 out_devx: 1945 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1946 mlx5_ib_devx_destroy(dev, context->devx_uid); 1947 1948 out_uars: 1949 deallocate_uars(dev, context); 1950 1951 out_sys_pages: 1952 kfree(bfregi->sys_pages); 1953 1954 out_count: 1955 kfree(bfregi->count); 1956 1957 out_ctx: 1958 return err; 1959 } 1960 1961 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1962 struct uverbs_attr_bundle *attrs) 1963 { 1964 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1965 int ret; 1966 1967 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1968 if (ret) 1969 return ret; 1970 1971 uctx_resp.response_length = 1972 min_t(size_t, 1973 uverbs_attr_get_len(attrs, 1974 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1975 sizeof(uctx_resp)); 1976 1977 ret = uverbs_copy_to_struct_or_zero(attrs, 1978 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1979 &uctx_resp, 1980 sizeof(uctx_resp)); 1981 return ret; 1982 } 1983 1984 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1985 { 1986 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1987 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1988 struct mlx5_bfreg_info *bfregi; 1989 1990 bfregi = &context->bfregi; 1991 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1992 1993 if (context->devx_uid) 1994 mlx5_ib_devx_destroy(dev, context->devx_uid); 1995 1996 deallocate_uars(dev, context); 1997 kfree(bfregi->sys_pages); 1998 kfree(bfregi->count); 1999 } 2000 2001 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2002 int uar_idx) 2003 { 2004 int fw_uars_per_page; 2005 2006 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2007 2008 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2009 } 2010 2011 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2012 int uar_idx) 2013 { 2014 unsigned int fw_uars_per_page; 2015 2016 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2017 MLX5_UARS_IN_PAGE : 1; 2018 2019 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2020 } 2021 2022 static int get_command(unsigned long offset) 2023 { 2024 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2025 } 2026 2027 static int get_arg(unsigned long offset) 2028 { 2029 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2030 } 2031 2032 static int get_index(unsigned long offset) 2033 { 2034 return get_arg(offset); 2035 } 2036 2037 /* Index resides in an extra byte to enable larger values than 255 */ 2038 static int get_extended_index(unsigned long offset) 2039 { 2040 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2041 } 2042 2043 2044 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2045 { 2046 } 2047 2048 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2049 { 2050 switch (cmd) { 2051 case MLX5_IB_MMAP_WC_PAGE: 2052 return "WC"; 2053 case MLX5_IB_MMAP_REGULAR_PAGE: 2054 return "best effort WC"; 2055 case MLX5_IB_MMAP_NC_PAGE: 2056 return "NC"; 2057 case MLX5_IB_MMAP_DEVICE_MEM: 2058 return "Device Memory"; 2059 default: 2060 return NULL; 2061 } 2062 } 2063 2064 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2065 struct vm_area_struct *vma, 2066 struct mlx5_ib_ucontext *context) 2067 { 2068 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2069 !(vma->vm_flags & VM_SHARED)) 2070 return -EINVAL; 2071 2072 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2073 return -EOPNOTSUPP; 2074 2075 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2076 return -EPERM; 2077 vma->vm_flags &= ~VM_MAYWRITE; 2078 2079 if (!dev->mdev->clock_info) 2080 return -EOPNOTSUPP; 2081 2082 return vm_insert_page(vma, vma->vm_start, 2083 virt_to_page(dev->mdev->clock_info)); 2084 } 2085 2086 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2087 { 2088 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2089 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2090 struct mlx5_var_table *var_table = &dev->var_table; 2091 struct mlx5_ib_dm *mdm; 2092 2093 switch (mentry->mmap_flag) { 2094 case MLX5_IB_MMAP_TYPE_MEMIC: 2095 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2096 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2097 mdm->size); 2098 kfree(mdm); 2099 break; 2100 case MLX5_IB_MMAP_TYPE_VAR: 2101 mutex_lock(&var_table->bitmap_lock); 2102 clear_bit(mentry->page_idx, var_table->bitmap); 2103 mutex_unlock(&var_table->bitmap_lock); 2104 kfree(mentry); 2105 break; 2106 case MLX5_IB_MMAP_TYPE_UAR_WC: 2107 case MLX5_IB_MMAP_TYPE_UAR_NC: 2108 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2109 kfree(mentry); 2110 break; 2111 default: 2112 WARN_ON(true); 2113 } 2114 } 2115 2116 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2117 struct vm_area_struct *vma, 2118 struct mlx5_ib_ucontext *context) 2119 { 2120 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2121 int err; 2122 unsigned long idx; 2123 phys_addr_t pfn; 2124 pgprot_t prot; 2125 u32 bfreg_dyn_idx = 0; 2126 u32 uar_index; 2127 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2128 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2129 bfregi->num_static_sys_pages; 2130 2131 if (bfregi->lib_uar_dyn) 2132 return -EINVAL; 2133 2134 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2135 return -EINVAL; 2136 2137 if (dyn_uar) 2138 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2139 else 2140 idx = get_index(vma->vm_pgoff); 2141 2142 if (idx >= max_valid_idx) { 2143 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2144 idx, max_valid_idx); 2145 return -EINVAL; 2146 } 2147 2148 switch (cmd) { 2149 case MLX5_IB_MMAP_WC_PAGE: 2150 case MLX5_IB_MMAP_ALLOC_WC: 2151 case MLX5_IB_MMAP_REGULAR_PAGE: 2152 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2153 prot = pgprot_writecombine(vma->vm_page_prot); 2154 break; 2155 case MLX5_IB_MMAP_NC_PAGE: 2156 prot = pgprot_noncached(vma->vm_page_prot); 2157 break; 2158 default: 2159 return -EINVAL; 2160 } 2161 2162 if (dyn_uar) { 2163 int uars_per_page; 2164 2165 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2166 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2167 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2168 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2169 bfreg_dyn_idx, bfregi->total_num_bfregs); 2170 return -EINVAL; 2171 } 2172 2173 mutex_lock(&bfregi->lock); 2174 /* Fail if uar already allocated, first bfreg index of each 2175 * page holds its count. 2176 */ 2177 if (bfregi->count[bfreg_dyn_idx]) { 2178 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2179 mutex_unlock(&bfregi->lock); 2180 return -EINVAL; 2181 } 2182 2183 bfregi->count[bfreg_dyn_idx]++; 2184 mutex_unlock(&bfregi->lock); 2185 2186 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2187 if (err) { 2188 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2189 goto free_bfreg; 2190 } 2191 } else { 2192 uar_index = bfregi->sys_pages[idx]; 2193 } 2194 2195 pfn = uar_index2pfn(dev, uar_index); 2196 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2197 2198 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2199 prot, NULL); 2200 if (err) { 2201 mlx5_ib_err(dev, 2202 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2203 err, mmap_cmd2str(cmd)); 2204 goto err; 2205 } 2206 2207 if (dyn_uar) 2208 bfregi->sys_pages[idx] = uar_index; 2209 return 0; 2210 2211 err: 2212 if (!dyn_uar) 2213 return err; 2214 2215 mlx5_cmd_free_uar(dev->mdev, idx); 2216 2217 free_bfreg: 2218 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2219 2220 return err; 2221 } 2222 2223 static int add_dm_mmap_entry(struct ib_ucontext *context, 2224 struct mlx5_ib_dm *mdm, 2225 u64 address) 2226 { 2227 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2228 mdm->mentry.address = address; 2229 return rdma_user_mmap_entry_insert_range( 2230 context, &mdm->mentry.rdma_entry, 2231 mdm->size, 2232 MLX5_IB_MMAP_DEVICE_MEM << 16, 2233 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2234 } 2235 2236 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2237 { 2238 unsigned long idx; 2239 u8 command; 2240 2241 command = get_command(vma->vm_pgoff); 2242 idx = get_extended_index(vma->vm_pgoff); 2243 2244 return (command << 16 | idx); 2245 } 2246 2247 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2248 struct vm_area_struct *vma, 2249 struct ib_ucontext *ucontext) 2250 { 2251 struct mlx5_user_mmap_entry *mentry; 2252 struct rdma_user_mmap_entry *entry; 2253 unsigned long pgoff; 2254 pgprot_t prot; 2255 phys_addr_t pfn; 2256 int ret; 2257 2258 pgoff = mlx5_vma_to_pgoff(vma); 2259 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2260 if (!entry) 2261 return -EINVAL; 2262 2263 mentry = to_mmmap(entry); 2264 pfn = (mentry->address >> PAGE_SHIFT); 2265 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2266 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2267 prot = pgprot_noncached(vma->vm_page_prot); 2268 else 2269 prot = pgprot_writecombine(vma->vm_page_prot); 2270 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2271 entry->npages * PAGE_SIZE, 2272 prot, 2273 entry); 2274 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2275 return ret; 2276 } 2277 2278 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2279 { 2280 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2281 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2282 2283 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2284 (index & 0xFF)) << PAGE_SHIFT; 2285 } 2286 2287 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2288 { 2289 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2290 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2291 unsigned long command; 2292 phys_addr_t pfn; 2293 2294 command = get_command(vma->vm_pgoff); 2295 switch (command) { 2296 case MLX5_IB_MMAP_WC_PAGE: 2297 case MLX5_IB_MMAP_ALLOC_WC: 2298 if (!dev->wc_support) 2299 return -EPERM; 2300 fallthrough; 2301 case MLX5_IB_MMAP_NC_PAGE: 2302 case MLX5_IB_MMAP_REGULAR_PAGE: 2303 return uar_mmap(dev, command, vma, context); 2304 2305 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2306 return -ENOSYS; 2307 2308 case MLX5_IB_MMAP_CORE_CLOCK: 2309 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2310 return -EINVAL; 2311 2312 if (vma->vm_flags & VM_WRITE) 2313 return -EPERM; 2314 vma->vm_flags &= ~VM_MAYWRITE; 2315 2316 /* Don't expose to user-space information it shouldn't have */ 2317 if (PAGE_SIZE > 4096) 2318 return -EOPNOTSUPP; 2319 2320 pfn = (dev->mdev->iseg_base + 2321 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2322 PAGE_SHIFT; 2323 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2324 PAGE_SIZE, 2325 pgprot_noncached(vma->vm_page_prot), 2326 NULL); 2327 case MLX5_IB_MMAP_CLOCK_INFO: 2328 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2329 2330 default: 2331 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2332 } 2333 2334 return 0; 2335 } 2336 2337 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2338 u32 type) 2339 { 2340 switch (type) { 2341 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2342 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2343 return -EOPNOTSUPP; 2344 break; 2345 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2346 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2347 if (!capable(CAP_SYS_RAWIO) || 2348 !capable(CAP_NET_RAW)) 2349 return -EPERM; 2350 2351 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2352 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) || 2353 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) || 2354 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2))) 2355 return -EOPNOTSUPP; 2356 break; 2357 } 2358 2359 return 0; 2360 } 2361 2362 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2363 struct mlx5_ib_dm *dm, 2364 struct ib_dm_alloc_attr *attr, 2365 struct uverbs_attr_bundle *attrs) 2366 { 2367 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2368 u64 start_offset; 2369 u16 page_idx; 2370 int err; 2371 u64 address; 2372 2373 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2374 2375 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2376 dm->size, attr->alignment); 2377 if (err) 2378 return err; 2379 2380 address = dm->dev_addr & PAGE_MASK; 2381 err = add_dm_mmap_entry(ctx, dm, address); 2382 if (err) 2383 goto err_dealloc; 2384 2385 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2386 err = uverbs_copy_to(attrs, 2387 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2388 &page_idx, 2389 sizeof(page_idx)); 2390 if (err) 2391 goto err_copy; 2392 2393 start_offset = dm->dev_addr & ~PAGE_MASK; 2394 err = uverbs_copy_to(attrs, 2395 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2396 &start_offset, sizeof(start_offset)); 2397 if (err) 2398 goto err_copy; 2399 2400 return 0; 2401 2402 err_copy: 2403 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2404 err_dealloc: 2405 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2406 2407 return err; 2408 } 2409 2410 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2411 struct mlx5_ib_dm *dm, 2412 struct ib_dm_alloc_attr *attr, 2413 struct uverbs_attr_bundle *attrs, 2414 int type) 2415 { 2416 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2417 u64 act_size; 2418 int err; 2419 2420 /* Allocation size must a multiple of the basic block size 2421 * and a power of 2. 2422 */ 2423 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2424 act_size = roundup_pow_of_two(act_size); 2425 2426 dm->size = act_size; 2427 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2428 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2429 &dm->icm_dm.obj_id); 2430 if (err) 2431 return err; 2432 2433 err = uverbs_copy_to(attrs, 2434 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2435 &dm->dev_addr, sizeof(dm->dev_addr)); 2436 if (err) 2437 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2438 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2439 dm->icm_dm.obj_id); 2440 2441 return err; 2442 } 2443 2444 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2445 struct ib_ucontext *context, 2446 struct ib_dm_alloc_attr *attr, 2447 struct uverbs_attr_bundle *attrs) 2448 { 2449 struct mlx5_ib_dm *dm; 2450 enum mlx5_ib_uapi_dm_type type; 2451 int err; 2452 2453 err = uverbs_get_const_default(&type, attrs, 2454 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2455 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2456 if (err) 2457 return ERR_PTR(err); 2458 2459 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2460 type, attr->length, attr->alignment); 2461 2462 err = check_dm_type_support(to_mdev(ibdev), type); 2463 if (err) 2464 return ERR_PTR(err); 2465 2466 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2467 if (!dm) 2468 return ERR_PTR(-ENOMEM); 2469 2470 dm->type = type; 2471 2472 switch (type) { 2473 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2474 err = handle_alloc_dm_memic(context, dm, 2475 attr, 2476 attrs); 2477 break; 2478 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2479 err = handle_alloc_dm_sw_icm(context, dm, 2480 attr, attrs, 2481 MLX5_SW_ICM_TYPE_STEERING); 2482 break; 2483 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2484 err = handle_alloc_dm_sw_icm(context, dm, 2485 attr, attrs, 2486 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2487 break; 2488 default: 2489 err = -EOPNOTSUPP; 2490 } 2491 2492 if (err) 2493 goto err_free; 2494 2495 return &dm->ibdm; 2496 2497 err_free: 2498 kfree(dm); 2499 return ERR_PTR(err); 2500 } 2501 2502 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2503 { 2504 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2505 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2506 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2507 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2508 int ret; 2509 2510 switch (dm->type) { 2511 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2512 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2513 return 0; 2514 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2515 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2516 dm->size, ctx->devx_uid, dm->dev_addr, 2517 dm->icm_dm.obj_id); 2518 if (ret) 2519 return ret; 2520 break; 2521 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2522 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2523 dm->size, ctx->devx_uid, dm->dev_addr, 2524 dm->icm_dm.obj_id); 2525 if (ret) 2526 return ret; 2527 break; 2528 default: 2529 return -EOPNOTSUPP; 2530 } 2531 2532 kfree(dm); 2533 2534 return 0; 2535 } 2536 2537 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2538 { 2539 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2540 struct ib_device *ibdev = ibpd->device; 2541 struct mlx5_ib_alloc_pd_resp resp; 2542 int err; 2543 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2544 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2545 u16 uid = 0; 2546 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2547 udata, struct mlx5_ib_ucontext, ibucontext); 2548 2549 uid = context ? context->devx_uid : 0; 2550 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2551 MLX5_SET(alloc_pd_in, in, uid, uid); 2552 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2553 if (err) 2554 return err; 2555 2556 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2557 pd->uid = uid; 2558 if (udata) { 2559 resp.pdn = pd->pdn; 2560 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2561 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2562 return -EFAULT; 2563 } 2564 } 2565 2566 return 0; 2567 } 2568 2569 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2570 { 2571 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2572 struct mlx5_ib_pd *mpd = to_mpd(pd); 2573 2574 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2575 } 2576 2577 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2578 { 2579 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2580 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2581 int err; 2582 u16 uid; 2583 2584 uid = ibqp->pd ? 2585 to_mpd(ibqp->pd)->uid : 0; 2586 2587 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2588 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2589 return -EOPNOTSUPP; 2590 } 2591 2592 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2593 if (err) 2594 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2595 ibqp->qp_num, gid->raw); 2596 2597 return err; 2598 } 2599 2600 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2601 { 2602 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2603 int err; 2604 u16 uid; 2605 2606 uid = ibqp->pd ? 2607 to_mpd(ibqp->pd)->uid : 0; 2608 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2609 if (err) 2610 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2611 ibqp->qp_num, gid->raw); 2612 2613 return err; 2614 } 2615 2616 static int init_node_data(struct mlx5_ib_dev *dev) 2617 { 2618 int err; 2619 2620 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2621 if (err) 2622 return err; 2623 2624 dev->mdev->rev_id = dev->mdev->pdev->revision; 2625 2626 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2627 } 2628 2629 static ssize_t fw_pages_show(struct device *device, 2630 struct device_attribute *attr, char *buf) 2631 { 2632 struct mlx5_ib_dev *dev = 2633 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2634 2635 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2636 } 2637 static DEVICE_ATTR_RO(fw_pages); 2638 2639 static ssize_t reg_pages_show(struct device *device, 2640 struct device_attribute *attr, char *buf) 2641 { 2642 struct mlx5_ib_dev *dev = 2643 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2644 2645 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2646 } 2647 static DEVICE_ATTR_RO(reg_pages); 2648 2649 static ssize_t hca_type_show(struct device *device, 2650 struct device_attribute *attr, char *buf) 2651 { 2652 struct mlx5_ib_dev *dev = 2653 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2654 2655 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2656 } 2657 static DEVICE_ATTR_RO(hca_type); 2658 2659 static ssize_t hw_rev_show(struct device *device, 2660 struct device_attribute *attr, char *buf) 2661 { 2662 struct mlx5_ib_dev *dev = 2663 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2664 2665 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2666 } 2667 static DEVICE_ATTR_RO(hw_rev); 2668 2669 static ssize_t board_id_show(struct device *device, 2670 struct device_attribute *attr, char *buf) 2671 { 2672 struct mlx5_ib_dev *dev = 2673 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2674 2675 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2676 dev->mdev->board_id); 2677 } 2678 static DEVICE_ATTR_RO(board_id); 2679 2680 static struct attribute *mlx5_class_attributes[] = { 2681 &dev_attr_hw_rev.attr, 2682 &dev_attr_hca_type.attr, 2683 &dev_attr_board_id.attr, 2684 &dev_attr_fw_pages.attr, 2685 &dev_attr_reg_pages.attr, 2686 NULL, 2687 }; 2688 2689 static const struct attribute_group mlx5_attr_group = { 2690 .attrs = mlx5_class_attributes, 2691 }; 2692 2693 static void pkey_change_handler(struct work_struct *work) 2694 { 2695 struct mlx5_ib_port_resources *ports = 2696 container_of(work, struct mlx5_ib_port_resources, 2697 pkey_change_work); 2698 2699 mlx5_ib_gsi_pkey_change(ports->gsi); 2700 } 2701 2702 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2703 { 2704 struct mlx5_ib_qp *mqp; 2705 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2706 struct mlx5_core_cq *mcq; 2707 struct list_head cq_armed_list; 2708 unsigned long flags_qp; 2709 unsigned long flags_cq; 2710 unsigned long flags; 2711 2712 INIT_LIST_HEAD(&cq_armed_list); 2713 2714 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2715 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2716 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2717 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2718 if (mqp->sq.tail != mqp->sq.head) { 2719 send_mcq = to_mcq(mqp->ibqp.send_cq); 2720 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2721 if (send_mcq->mcq.comp && 2722 mqp->ibqp.send_cq->comp_handler) { 2723 if (!send_mcq->mcq.reset_notify_added) { 2724 send_mcq->mcq.reset_notify_added = 1; 2725 list_add_tail(&send_mcq->mcq.reset_notify, 2726 &cq_armed_list); 2727 } 2728 } 2729 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2730 } 2731 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2732 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2733 /* no handling is needed for SRQ */ 2734 if (!mqp->ibqp.srq) { 2735 if (mqp->rq.tail != mqp->rq.head) { 2736 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2737 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2738 if (recv_mcq->mcq.comp && 2739 mqp->ibqp.recv_cq->comp_handler) { 2740 if (!recv_mcq->mcq.reset_notify_added) { 2741 recv_mcq->mcq.reset_notify_added = 1; 2742 list_add_tail(&recv_mcq->mcq.reset_notify, 2743 &cq_armed_list); 2744 } 2745 } 2746 spin_unlock_irqrestore(&recv_mcq->lock, 2747 flags_cq); 2748 } 2749 } 2750 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2751 } 2752 /*At that point all inflight post send were put to be executed as of we 2753 * lock/unlock above locks Now need to arm all involved CQs. 2754 */ 2755 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2756 mcq->comp(mcq, NULL); 2757 } 2758 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2759 } 2760 2761 static void delay_drop_handler(struct work_struct *work) 2762 { 2763 int err; 2764 struct mlx5_ib_delay_drop *delay_drop = 2765 container_of(work, struct mlx5_ib_delay_drop, 2766 delay_drop_work); 2767 2768 atomic_inc(&delay_drop->events_cnt); 2769 2770 mutex_lock(&delay_drop->lock); 2771 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2772 if (err) { 2773 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2774 delay_drop->timeout); 2775 delay_drop->activate = false; 2776 } 2777 mutex_unlock(&delay_drop->lock); 2778 } 2779 2780 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2781 struct ib_event *ibev) 2782 { 2783 u8 port = (eqe->data.port.port >> 4) & 0xf; 2784 2785 switch (eqe->sub_type) { 2786 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2787 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2788 IB_LINK_LAYER_ETHERNET) 2789 schedule_work(&ibdev->delay_drop.delay_drop_work); 2790 break; 2791 default: /* do nothing */ 2792 return; 2793 } 2794 } 2795 2796 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2797 struct ib_event *ibev) 2798 { 2799 u8 port = (eqe->data.port.port >> 4) & 0xf; 2800 2801 ibev->element.port_num = port; 2802 2803 switch (eqe->sub_type) { 2804 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2805 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2806 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2807 /* In RoCE, port up/down events are handled in 2808 * mlx5_netdev_event(). 2809 */ 2810 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2811 IB_LINK_LAYER_ETHERNET) 2812 return -EINVAL; 2813 2814 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2815 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2816 break; 2817 2818 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2819 ibev->event = IB_EVENT_LID_CHANGE; 2820 break; 2821 2822 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2823 ibev->event = IB_EVENT_PKEY_CHANGE; 2824 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2825 break; 2826 2827 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2828 ibev->event = IB_EVENT_GID_CHANGE; 2829 break; 2830 2831 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2832 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2833 break; 2834 default: 2835 return -EINVAL; 2836 } 2837 2838 return 0; 2839 } 2840 2841 static void mlx5_ib_handle_event(struct work_struct *_work) 2842 { 2843 struct mlx5_ib_event_work *work = 2844 container_of(_work, struct mlx5_ib_event_work, work); 2845 struct mlx5_ib_dev *ibdev; 2846 struct ib_event ibev; 2847 bool fatal = false; 2848 2849 if (work->is_slave) { 2850 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2851 if (!ibdev) 2852 goto out; 2853 } else { 2854 ibdev = work->dev; 2855 } 2856 2857 switch (work->event) { 2858 case MLX5_DEV_EVENT_SYS_ERROR: 2859 ibev.event = IB_EVENT_DEVICE_FATAL; 2860 mlx5_ib_handle_internal_error(ibdev); 2861 ibev.element.port_num = (u8)(unsigned long)work->param; 2862 fatal = true; 2863 break; 2864 case MLX5_EVENT_TYPE_PORT_CHANGE: 2865 if (handle_port_change(ibdev, work->param, &ibev)) 2866 goto out; 2867 break; 2868 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2869 handle_general_event(ibdev, work->param, &ibev); 2870 fallthrough; 2871 default: 2872 goto out; 2873 } 2874 2875 ibev.device = &ibdev->ib_dev; 2876 2877 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2878 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2879 goto out; 2880 } 2881 2882 if (ibdev->ib_active) 2883 ib_dispatch_event(&ibev); 2884 2885 if (fatal) 2886 ibdev->ib_active = false; 2887 out: 2888 kfree(work); 2889 } 2890 2891 static int mlx5_ib_event(struct notifier_block *nb, 2892 unsigned long event, void *param) 2893 { 2894 struct mlx5_ib_event_work *work; 2895 2896 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2897 if (!work) 2898 return NOTIFY_DONE; 2899 2900 INIT_WORK(&work->work, mlx5_ib_handle_event); 2901 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2902 work->is_slave = false; 2903 work->param = param; 2904 work->event = event; 2905 2906 queue_work(mlx5_ib_event_wq, &work->work); 2907 2908 return NOTIFY_OK; 2909 } 2910 2911 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2912 unsigned long event, void *param) 2913 { 2914 struct mlx5_ib_event_work *work; 2915 2916 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2917 if (!work) 2918 return NOTIFY_DONE; 2919 2920 INIT_WORK(&work->work, mlx5_ib_handle_event); 2921 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2922 work->is_slave = true; 2923 work->param = param; 2924 work->event = event; 2925 queue_work(mlx5_ib_event_wq, &work->work); 2926 2927 return NOTIFY_OK; 2928 } 2929 2930 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2931 { 2932 struct mlx5_hca_vport_context vport_ctx; 2933 int err; 2934 int port; 2935 2936 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2937 dev->port_caps[port - 1].has_smi = false; 2938 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2939 MLX5_CAP_PORT_TYPE_IB) { 2940 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2941 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2942 port, 0, 2943 &vport_ctx); 2944 if (err) { 2945 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2946 port, err); 2947 return err; 2948 } 2949 dev->port_caps[port - 1].has_smi = 2950 vport_ctx.has_smi; 2951 } else { 2952 dev->port_caps[port - 1].has_smi = true; 2953 } 2954 } 2955 } 2956 return 0; 2957 } 2958 2959 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2960 { 2961 unsigned int port; 2962 2963 rdma_for_each_port (&dev->ib_dev, port) 2964 mlx5_query_ext_port_caps(dev, port); 2965 } 2966 2967 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2968 { 2969 switch (umr_fence_cap) { 2970 case MLX5_CAP_UMR_FENCE_NONE: 2971 return MLX5_FENCE_MODE_NONE; 2972 case MLX5_CAP_UMR_FENCE_SMALL: 2973 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2974 default: 2975 return MLX5_FENCE_MODE_STRONG_ORDERING; 2976 } 2977 } 2978 2979 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2980 { 2981 struct mlx5_ib_resources *devr = &dev->devr; 2982 struct ib_srq_init_attr attr; 2983 struct ib_device *ibdev; 2984 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2985 int port; 2986 int ret = 0; 2987 2988 ibdev = &dev->ib_dev; 2989 2990 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2991 return -EOPNOTSUPP; 2992 2993 mutex_init(&devr->mutex); 2994 2995 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2996 if (!devr->p0) 2997 return -ENOMEM; 2998 2999 devr->p0->device = ibdev; 3000 devr->p0->uobject = NULL; 3001 atomic_set(&devr->p0->usecnt, 0); 3002 3003 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3004 if (ret) 3005 goto error0; 3006 3007 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3008 if (!devr->c0) { 3009 ret = -ENOMEM; 3010 goto error1; 3011 } 3012 3013 devr->c0->device = &dev->ib_dev; 3014 atomic_set(&devr->c0->usecnt, 0); 3015 3016 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3017 if (ret) 3018 goto err_create_cq; 3019 3020 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3021 if (ret) 3022 goto error2; 3023 3024 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3025 if (ret) 3026 goto error3; 3027 3028 memset(&attr, 0, sizeof(attr)); 3029 attr.attr.max_sge = 1; 3030 attr.attr.max_wr = 1; 3031 attr.srq_type = IB_SRQT_XRC; 3032 attr.ext.cq = devr->c0; 3033 3034 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3035 if (!devr->s0) { 3036 ret = -ENOMEM; 3037 goto error4; 3038 } 3039 3040 devr->s0->device = &dev->ib_dev; 3041 devr->s0->pd = devr->p0; 3042 devr->s0->srq_type = IB_SRQT_XRC; 3043 devr->s0->ext.cq = devr->c0; 3044 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3045 if (ret) 3046 goto err_create; 3047 3048 atomic_inc(&devr->s0->ext.cq->usecnt); 3049 atomic_inc(&devr->p0->usecnt); 3050 atomic_set(&devr->s0->usecnt, 0); 3051 3052 memset(&attr, 0, sizeof(attr)); 3053 attr.attr.max_sge = 1; 3054 attr.attr.max_wr = 1; 3055 attr.srq_type = IB_SRQT_BASIC; 3056 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3057 if (!devr->s1) { 3058 ret = -ENOMEM; 3059 goto error5; 3060 } 3061 3062 devr->s1->device = &dev->ib_dev; 3063 devr->s1->pd = devr->p0; 3064 devr->s1->srq_type = IB_SRQT_BASIC; 3065 devr->s1->ext.cq = devr->c0; 3066 3067 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3068 if (ret) 3069 goto error6; 3070 3071 atomic_inc(&devr->p0->usecnt); 3072 atomic_set(&devr->s1->usecnt, 0); 3073 3074 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3075 INIT_WORK(&devr->ports[port].pkey_change_work, 3076 pkey_change_handler); 3077 3078 return 0; 3079 3080 error6: 3081 kfree(devr->s1); 3082 error5: 3083 mlx5_ib_destroy_srq(devr->s0, NULL); 3084 err_create: 3085 kfree(devr->s0); 3086 error4: 3087 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3088 error3: 3089 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3090 error2: 3091 mlx5_ib_destroy_cq(devr->c0, NULL); 3092 err_create_cq: 3093 kfree(devr->c0); 3094 error1: 3095 mlx5_ib_dealloc_pd(devr->p0, NULL); 3096 error0: 3097 kfree(devr->p0); 3098 return ret; 3099 } 3100 3101 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3102 { 3103 struct mlx5_ib_resources *devr = &dev->devr; 3104 int port; 3105 3106 mlx5_ib_destroy_srq(devr->s1, NULL); 3107 kfree(devr->s1); 3108 mlx5_ib_destroy_srq(devr->s0, NULL); 3109 kfree(devr->s0); 3110 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3111 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3112 mlx5_ib_destroy_cq(devr->c0, NULL); 3113 kfree(devr->c0); 3114 mlx5_ib_dealloc_pd(devr->p0, NULL); 3115 kfree(devr->p0); 3116 3117 /* Make sure no change P_Key work items are still executing */ 3118 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3119 cancel_work_sync(&devr->ports[port].pkey_change_work); 3120 } 3121 3122 static u32 get_core_cap_flags(struct ib_device *ibdev, 3123 struct mlx5_hca_vport_context *rep) 3124 { 3125 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3126 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3127 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3128 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3129 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3130 u32 ret = 0; 3131 3132 if (rep->grh_required) 3133 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3134 3135 if (ll == IB_LINK_LAYER_INFINIBAND) 3136 return ret | RDMA_CORE_PORT_IBA_IB; 3137 3138 if (raw_support) 3139 ret |= RDMA_CORE_PORT_RAW_PACKET; 3140 3141 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3142 return ret; 3143 3144 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3145 return ret; 3146 3147 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3148 ret |= RDMA_CORE_PORT_IBA_ROCE; 3149 3150 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3151 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3152 3153 return ret; 3154 } 3155 3156 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3157 struct ib_port_immutable *immutable) 3158 { 3159 struct ib_port_attr attr; 3160 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3161 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3162 struct mlx5_hca_vport_context rep = {0}; 3163 int err; 3164 3165 err = ib_query_port(ibdev, port_num, &attr); 3166 if (err) 3167 return err; 3168 3169 if (ll == IB_LINK_LAYER_INFINIBAND) { 3170 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3171 &rep); 3172 if (err) 3173 return err; 3174 } 3175 3176 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3177 immutable->gid_tbl_len = attr.gid_tbl_len; 3178 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3179 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3180 3181 return 0; 3182 } 3183 3184 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3185 struct ib_port_immutable *immutable) 3186 { 3187 struct ib_port_attr attr; 3188 int err; 3189 3190 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3191 3192 err = ib_query_port(ibdev, port_num, &attr); 3193 if (err) 3194 return err; 3195 3196 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3197 immutable->gid_tbl_len = attr.gid_tbl_len; 3198 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3199 3200 return 0; 3201 } 3202 3203 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3204 { 3205 struct mlx5_ib_dev *dev = 3206 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3207 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3208 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3209 fw_rev_sub(dev->mdev)); 3210 } 3211 3212 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3213 { 3214 struct mlx5_core_dev *mdev = dev->mdev; 3215 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3216 MLX5_FLOW_NAMESPACE_LAG); 3217 struct mlx5_flow_table *ft; 3218 int err; 3219 3220 if (!ns || !mlx5_lag_is_roce(mdev)) 3221 return 0; 3222 3223 err = mlx5_cmd_create_vport_lag(mdev); 3224 if (err) 3225 return err; 3226 3227 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3228 if (IS_ERR(ft)) { 3229 err = PTR_ERR(ft); 3230 goto err_destroy_vport_lag; 3231 } 3232 3233 dev->flow_db->lag_demux_ft = ft; 3234 dev->lag_active = true; 3235 return 0; 3236 3237 err_destroy_vport_lag: 3238 mlx5_cmd_destroy_vport_lag(mdev); 3239 return err; 3240 } 3241 3242 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3243 { 3244 struct mlx5_core_dev *mdev = dev->mdev; 3245 3246 if (dev->lag_active) { 3247 dev->lag_active = false; 3248 3249 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3250 dev->flow_db->lag_demux_ft = NULL; 3251 3252 mlx5_cmd_destroy_vport_lag(mdev); 3253 } 3254 } 3255 3256 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3257 { 3258 int err; 3259 3260 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3261 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3262 if (err) { 3263 dev->port[port_num].roce.nb.notifier_call = NULL; 3264 return err; 3265 } 3266 3267 return 0; 3268 } 3269 3270 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3271 { 3272 if (dev->port[port_num].roce.nb.notifier_call) { 3273 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3274 dev->port[port_num].roce.nb.notifier_call = NULL; 3275 } 3276 } 3277 3278 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3279 { 3280 int err; 3281 3282 err = mlx5_nic_vport_enable_roce(dev->mdev); 3283 if (err) 3284 return err; 3285 3286 err = mlx5_eth_lag_init(dev); 3287 if (err) 3288 goto err_disable_roce; 3289 3290 return 0; 3291 3292 err_disable_roce: 3293 mlx5_nic_vport_disable_roce(dev->mdev); 3294 3295 return err; 3296 } 3297 3298 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3299 { 3300 mlx5_eth_lag_cleanup(dev); 3301 mlx5_nic_vport_disable_roce(dev->mdev); 3302 } 3303 3304 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3305 enum rdma_netdev_t type, 3306 struct rdma_netdev_alloc_params *params) 3307 { 3308 if (type != RDMA_NETDEV_IPOIB) 3309 return -EOPNOTSUPP; 3310 3311 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3312 } 3313 3314 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3315 size_t count, loff_t *pos) 3316 { 3317 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3318 char lbuf[20]; 3319 int len; 3320 3321 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3322 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3323 } 3324 3325 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3326 size_t count, loff_t *pos) 3327 { 3328 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3329 u32 timeout; 3330 u32 var; 3331 3332 if (kstrtouint_from_user(buf, count, 0, &var)) 3333 return -EFAULT; 3334 3335 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3336 1000); 3337 if (timeout != var) 3338 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3339 timeout); 3340 3341 delay_drop->timeout = timeout; 3342 3343 return count; 3344 } 3345 3346 static const struct file_operations fops_delay_drop_timeout = { 3347 .owner = THIS_MODULE, 3348 .open = simple_open, 3349 .write = delay_drop_timeout_write, 3350 .read = delay_drop_timeout_read, 3351 }; 3352 3353 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3354 struct mlx5_ib_multiport_info *mpi) 3355 { 3356 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3357 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3358 int comps; 3359 int err; 3360 int i; 3361 3362 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3363 3364 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3365 3366 spin_lock(&port->mp.mpi_lock); 3367 if (!mpi->ibdev) { 3368 spin_unlock(&port->mp.mpi_lock); 3369 return; 3370 } 3371 3372 mpi->ibdev = NULL; 3373 3374 spin_unlock(&port->mp.mpi_lock); 3375 if (mpi->mdev_events.notifier_call) 3376 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3377 mpi->mdev_events.notifier_call = NULL; 3378 mlx5_remove_netdev_notifier(ibdev, port_num); 3379 spin_lock(&port->mp.mpi_lock); 3380 3381 comps = mpi->mdev_refcnt; 3382 if (comps) { 3383 mpi->unaffiliate = true; 3384 init_completion(&mpi->unref_comp); 3385 spin_unlock(&port->mp.mpi_lock); 3386 3387 for (i = 0; i < comps; i++) 3388 wait_for_completion(&mpi->unref_comp); 3389 3390 spin_lock(&port->mp.mpi_lock); 3391 mpi->unaffiliate = false; 3392 } 3393 3394 port->mp.mpi = NULL; 3395 3396 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3397 3398 spin_unlock(&port->mp.mpi_lock); 3399 3400 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3401 3402 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3403 /* Log an error, still needed to cleanup the pointers and add 3404 * it back to the list. 3405 */ 3406 if (err) 3407 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3408 port_num + 1); 3409 3410 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3411 } 3412 3413 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3414 struct mlx5_ib_multiport_info *mpi) 3415 { 3416 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3417 int err; 3418 3419 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3420 3421 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3422 if (ibdev->port[port_num].mp.mpi) { 3423 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3424 port_num + 1); 3425 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3426 return false; 3427 } 3428 3429 ibdev->port[port_num].mp.mpi = mpi; 3430 mpi->ibdev = ibdev; 3431 mpi->mdev_events.notifier_call = NULL; 3432 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3433 3434 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3435 if (err) 3436 goto unbind; 3437 3438 err = mlx5_add_netdev_notifier(ibdev, port_num); 3439 if (err) { 3440 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3441 port_num + 1); 3442 goto unbind; 3443 } 3444 3445 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3446 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3447 3448 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3449 3450 return true; 3451 3452 unbind: 3453 mlx5_ib_unbind_slave_port(ibdev, mpi); 3454 return false; 3455 } 3456 3457 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3458 { 3459 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3460 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3461 port_num + 1); 3462 struct mlx5_ib_multiport_info *mpi; 3463 int err; 3464 int i; 3465 3466 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3467 return 0; 3468 3469 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3470 &dev->sys_image_guid); 3471 if (err) 3472 return err; 3473 3474 err = mlx5_nic_vport_enable_roce(dev->mdev); 3475 if (err) 3476 return err; 3477 3478 mutex_lock(&mlx5_ib_multiport_mutex); 3479 for (i = 0; i < dev->num_ports; i++) { 3480 bool bound = false; 3481 3482 /* build a stub multiport info struct for the native port. */ 3483 if (i == port_num) { 3484 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3485 if (!mpi) { 3486 mutex_unlock(&mlx5_ib_multiport_mutex); 3487 mlx5_nic_vport_disable_roce(dev->mdev); 3488 return -ENOMEM; 3489 } 3490 3491 mpi->is_master = true; 3492 mpi->mdev = dev->mdev; 3493 mpi->sys_image_guid = dev->sys_image_guid; 3494 dev->port[i].mp.mpi = mpi; 3495 mpi->ibdev = dev; 3496 mpi = NULL; 3497 continue; 3498 } 3499 3500 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3501 list) { 3502 if (dev->sys_image_guid == mpi->sys_image_guid && 3503 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3504 bound = mlx5_ib_bind_slave_port(dev, mpi); 3505 } 3506 3507 if (bound) { 3508 dev_dbg(mpi->mdev->device, 3509 "removing port from unaffiliated list.\n"); 3510 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3511 list_del(&mpi->list); 3512 break; 3513 } 3514 } 3515 if (!bound) 3516 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3517 i + 1); 3518 } 3519 3520 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3521 mutex_unlock(&mlx5_ib_multiport_mutex); 3522 return err; 3523 } 3524 3525 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3526 { 3527 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3528 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3529 port_num + 1); 3530 int i; 3531 3532 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3533 return; 3534 3535 mutex_lock(&mlx5_ib_multiport_mutex); 3536 for (i = 0; i < dev->num_ports; i++) { 3537 if (dev->port[i].mp.mpi) { 3538 /* Destroy the native port stub */ 3539 if (i == port_num) { 3540 kfree(dev->port[i].mp.mpi); 3541 dev->port[i].mp.mpi = NULL; 3542 } else { 3543 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3544 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3545 } 3546 } 3547 } 3548 3549 mlx5_ib_dbg(dev, "removing from devlist\n"); 3550 list_del(&dev->ib_dev_list); 3551 mutex_unlock(&mlx5_ib_multiport_mutex); 3552 3553 mlx5_nic_vport_disable_roce(dev->mdev); 3554 } 3555 3556 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3557 enum rdma_remove_reason why, 3558 struct uverbs_attr_bundle *attrs) 3559 { 3560 struct mlx5_user_mmap_entry *obj = uobject->object; 3561 3562 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3563 return 0; 3564 } 3565 3566 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3567 struct mlx5_user_mmap_entry *entry, 3568 size_t length) 3569 { 3570 return rdma_user_mmap_entry_insert_range( 3571 &c->ibucontext, &entry->rdma_entry, length, 3572 (MLX5_IB_MMAP_OFFSET_START << 16), 3573 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3574 } 3575 3576 static struct mlx5_user_mmap_entry * 3577 alloc_var_entry(struct mlx5_ib_ucontext *c) 3578 { 3579 struct mlx5_user_mmap_entry *entry; 3580 struct mlx5_var_table *var_table; 3581 u32 page_idx; 3582 int err; 3583 3584 var_table = &to_mdev(c->ibucontext.device)->var_table; 3585 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3586 if (!entry) 3587 return ERR_PTR(-ENOMEM); 3588 3589 mutex_lock(&var_table->bitmap_lock); 3590 page_idx = find_first_zero_bit(var_table->bitmap, 3591 var_table->num_var_hw_entries); 3592 if (page_idx >= var_table->num_var_hw_entries) { 3593 err = -ENOSPC; 3594 mutex_unlock(&var_table->bitmap_lock); 3595 goto end; 3596 } 3597 3598 set_bit(page_idx, var_table->bitmap); 3599 mutex_unlock(&var_table->bitmap_lock); 3600 3601 entry->address = var_table->hw_start_addr + 3602 (page_idx * var_table->stride_size); 3603 entry->page_idx = page_idx; 3604 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3605 3606 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3607 var_table->stride_size); 3608 if (err) 3609 goto err_insert; 3610 3611 return entry; 3612 3613 err_insert: 3614 mutex_lock(&var_table->bitmap_lock); 3615 clear_bit(page_idx, var_table->bitmap); 3616 mutex_unlock(&var_table->bitmap_lock); 3617 end: 3618 kfree(entry); 3619 return ERR_PTR(err); 3620 } 3621 3622 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3623 struct uverbs_attr_bundle *attrs) 3624 { 3625 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3626 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3627 struct mlx5_ib_ucontext *c; 3628 struct mlx5_user_mmap_entry *entry; 3629 u64 mmap_offset; 3630 u32 length; 3631 int err; 3632 3633 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3634 if (IS_ERR(c)) 3635 return PTR_ERR(c); 3636 3637 entry = alloc_var_entry(c); 3638 if (IS_ERR(entry)) 3639 return PTR_ERR(entry); 3640 3641 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3642 length = entry->rdma_entry.npages * PAGE_SIZE; 3643 uobj->object = entry; 3644 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3645 3646 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3647 &mmap_offset, sizeof(mmap_offset)); 3648 if (err) 3649 return err; 3650 3651 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3652 &entry->page_idx, sizeof(entry->page_idx)); 3653 if (err) 3654 return err; 3655 3656 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3657 &length, sizeof(length)); 3658 return err; 3659 } 3660 3661 DECLARE_UVERBS_NAMED_METHOD( 3662 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3663 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3664 MLX5_IB_OBJECT_VAR, 3665 UVERBS_ACCESS_NEW, 3666 UA_MANDATORY), 3667 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3668 UVERBS_ATTR_TYPE(u32), 3669 UA_MANDATORY), 3670 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3671 UVERBS_ATTR_TYPE(u32), 3672 UA_MANDATORY), 3673 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3674 UVERBS_ATTR_TYPE(u64), 3675 UA_MANDATORY)); 3676 3677 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3678 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3679 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3680 MLX5_IB_OBJECT_VAR, 3681 UVERBS_ACCESS_DESTROY, 3682 UA_MANDATORY)); 3683 3684 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3685 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3686 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3687 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3688 3689 static bool var_is_supported(struct ib_device *device) 3690 { 3691 struct mlx5_ib_dev *dev = to_mdev(device); 3692 3693 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3694 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3695 } 3696 3697 static struct mlx5_user_mmap_entry * 3698 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3699 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3700 { 3701 struct mlx5_user_mmap_entry *entry; 3702 struct mlx5_ib_dev *dev; 3703 u32 uar_index; 3704 int err; 3705 3706 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3707 if (!entry) 3708 return ERR_PTR(-ENOMEM); 3709 3710 dev = to_mdev(c->ibucontext.device); 3711 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3712 if (err) 3713 goto end; 3714 3715 entry->page_idx = uar_index; 3716 entry->address = uar_index2paddress(dev, uar_index); 3717 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3718 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3719 else 3720 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3721 3722 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3723 if (err) 3724 goto err_insert; 3725 3726 return entry; 3727 3728 err_insert: 3729 mlx5_cmd_free_uar(dev->mdev, uar_index); 3730 end: 3731 kfree(entry); 3732 return ERR_PTR(err); 3733 } 3734 3735 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3736 struct uverbs_attr_bundle *attrs) 3737 { 3738 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3739 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3740 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3741 struct mlx5_ib_ucontext *c; 3742 struct mlx5_user_mmap_entry *entry; 3743 u64 mmap_offset; 3744 u32 length; 3745 int err; 3746 3747 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3748 if (IS_ERR(c)) 3749 return PTR_ERR(c); 3750 3751 err = uverbs_get_const(&alloc_type, attrs, 3752 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3753 if (err) 3754 return err; 3755 3756 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3757 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3758 return -EOPNOTSUPP; 3759 3760 if (!to_mdev(c->ibucontext.device)->wc_support && 3761 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3762 return -EOPNOTSUPP; 3763 3764 entry = alloc_uar_entry(c, alloc_type); 3765 if (IS_ERR(entry)) 3766 return PTR_ERR(entry); 3767 3768 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3769 length = entry->rdma_entry.npages * PAGE_SIZE; 3770 uobj->object = entry; 3771 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3772 3773 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3774 &mmap_offset, sizeof(mmap_offset)); 3775 if (err) 3776 return err; 3777 3778 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3779 &entry->page_idx, sizeof(entry->page_idx)); 3780 if (err) 3781 return err; 3782 3783 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3784 &length, sizeof(length)); 3785 return err; 3786 } 3787 3788 DECLARE_UVERBS_NAMED_METHOD( 3789 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3790 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3791 MLX5_IB_OBJECT_UAR, 3792 UVERBS_ACCESS_NEW, 3793 UA_MANDATORY), 3794 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3795 enum mlx5_ib_uapi_uar_alloc_type, 3796 UA_MANDATORY), 3797 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3798 UVERBS_ATTR_TYPE(u32), 3799 UA_MANDATORY), 3800 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3801 UVERBS_ATTR_TYPE(u32), 3802 UA_MANDATORY), 3803 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3804 UVERBS_ATTR_TYPE(u64), 3805 UA_MANDATORY)); 3806 3807 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3808 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3809 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3810 MLX5_IB_OBJECT_UAR, 3811 UVERBS_ACCESS_DESTROY, 3812 UA_MANDATORY)); 3813 3814 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3815 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3816 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3817 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3818 3819 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3820 mlx5_ib_dm, 3821 UVERBS_OBJECT_DM, 3822 UVERBS_METHOD_DM_ALLOC, 3823 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3824 UVERBS_ATTR_TYPE(u64), 3825 UA_MANDATORY), 3826 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3827 UVERBS_ATTR_TYPE(u16), 3828 UA_OPTIONAL), 3829 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3830 enum mlx5_ib_uapi_dm_type, 3831 UA_OPTIONAL)); 3832 3833 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3834 mlx5_ib_flow_action, 3835 UVERBS_OBJECT_FLOW_ACTION, 3836 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3837 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3838 enum mlx5_ib_uapi_flow_action_flags)); 3839 3840 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3841 mlx5_ib_query_context, 3842 UVERBS_OBJECT_DEVICE, 3843 UVERBS_METHOD_QUERY_CONTEXT, 3844 UVERBS_ATTR_PTR_OUT( 3845 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3846 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3847 dump_fill_mkey), 3848 UA_MANDATORY)); 3849 3850 static const struct uapi_definition mlx5_ib_defs[] = { 3851 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3852 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3853 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3854 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3855 3856 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3857 &mlx5_ib_flow_action), 3858 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3859 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3860 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3861 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3862 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3863 {} 3864 }; 3865 3866 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3867 { 3868 mlx5_ib_cleanup_multiport_master(dev); 3869 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3870 mutex_destroy(&dev->cap_mask_mutex); 3871 WARN_ON(!xa_empty(&dev->sig_mrs)); 3872 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3873 } 3874 3875 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3876 { 3877 struct mlx5_core_dev *mdev = dev->mdev; 3878 int err; 3879 int i; 3880 3881 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3882 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3883 dev->ib_dev.phys_port_cnt = dev->num_ports; 3884 dev->ib_dev.dev.parent = mdev->device; 3885 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3886 3887 for (i = 0; i < dev->num_ports; i++) { 3888 spin_lock_init(&dev->port[i].mp.mpi_lock); 3889 rwlock_init(&dev->port[i].roce.netdev_lock); 3890 dev->port[i].roce.dev = dev; 3891 dev->port[i].roce.native_port_num = i + 1; 3892 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3893 } 3894 3895 mlx5_ib_internal_fill_odp_caps(dev); 3896 3897 err = mlx5_ib_init_multiport_master(dev); 3898 if (err) 3899 return err; 3900 3901 err = set_has_smi_cap(dev); 3902 if (err) 3903 goto err_mp; 3904 3905 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3906 if (err) 3907 goto err_mp; 3908 3909 if (mlx5_use_mad_ifc(dev)) 3910 get_ext_port_caps(dev); 3911 3912 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3913 3914 mutex_init(&dev->cap_mask_mutex); 3915 INIT_LIST_HEAD(&dev->qp_list); 3916 spin_lock_init(&dev->reset_flow_resource_lock); 3917 xa_init(&dev->odp_mkeys); 3918 xa_init(&dev->sig_mrs); 3919 atomic_set(&dev->mkey_var, 0); 3920 3921 spin_lock_init(&dev->dm.lock); 3922 dev->dm.dev = mdev; 3923 return 0; 3924 3925 err_mp: 3926 mlx5_ib_cleanup_multiport_master(dev); 3927 return err; 3928 } 3929 3930 static int mlx5_ib_enable_driver(struct ib_device *dev) 3931 { 3932 struct mlx5_ib_dev *mdev = to_mdev(dev); 3933 int ret; 3934 3935 ret = mlx5_ib_test_wc(mdev); 3936 mlx5_ib_dbg(mdev, "Write-Combining %s", 3937 mdev->wc_support ? "supported" : "not supported"); 3938 3939 return ret; 3940 } 3941 3942 static const struct ib_device_ops mlx5_ib_dev_ops = { 3943 .owner = THIS_MODULE, 3944 .driver_id = RDMA_DRIVER_MLX5, 3945 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3946 3947 .add_gid = mlx5_ib_add_gid, 3948 .alloc_mr = mlx5_ib_alloc_mr, 3949 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3950 .alloc_pd = mlx5_ib_alloc_pd, 3951 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3952 .attach_mcast = mlx5_ib_mcg_attach, 3953 .check_mr_status = mlx5_ib_check_mr_status, 3954 .create_ah = mlx5_ib_create_ah, 3955 .create_cq = mlx5_ib_create_cq, 3956 .create_qp = mlx5_ib_create_qp, 3957 .create_srq = mlx5_ib_create_srq, 3958 .create_user_ah = mlx5_ib_create_ah, 3959 .dealloc_pd = mlx5_ib_dealloc_pd, 3960 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3961 .del_gid = mlx5_ib_del_gid, 3962 .dereg_mr = mlx5_ib_dereg_mr, 3963 .destroy_ah = mlx5_ib_destroy_ah, 3964 .destroy_cq = mlx5_ib_destroy_cq, 3965 .destroy_qp = mlx5_ib_destroy_qp, 3966 .destroy_srq = mlx5_ib_destroy_srq, 3967 .detach_mcast = mlx5_ib_mcg_detach, 3968 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3969 .drain_rq = mlx5_ib_drain_rq, 3970 .drain_sq = mlx5_ib_drain_sq, 3971 .enable_driver = mlx5_ib_enable_driver, 3972 .get_dev_fw_str = get_dev_fw_str, 3973 .get_dma_mr = mlx5_ib_get_dma_mr, 3974 .get_link_layer = mlx5_ib_port_link_layer, 3975 .map_mr_sg = mlx5_ib_map_mr_sg, 3976 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3977 .mmap = mlx5_ib_mmap, 3978 .mmap_free = mlx5_ib_mmap_free, 3979 .modify_cq = mlx5_ib_modify_cq, 3980 .modify_device = mlx5_ib_modify_device, 3981 .modify_port = mlx5_ib_modify_port, 3982 .modify_qp = mlx5_ib_modify_qp, 3983 .modify_srq = mlx5_ib_modify_srq, 3984 .poll_cq = mlx5_ib_poll_cq, 3985 .post_recv = mlx5_ib_post_recv_nodrain, 3986 .post_send = mlx5_ib_post_send_nodrain, 3987 .post_srq_recv = mlx5_ib_post_srq_recv, 3988 .process_mad = mlx5_ib_process_mad, 3989 .query_ah = mlx5_ib_query_ah, 3990 .query_device = mlx5_ib_query_device, 3991 .query_gid = mlx5_ib_query_gid, 3992 .query_pkey = mlx5_ib_query_pkey, 3993 .query_qp = mlx5_ib_query_qp, 3994 .query_srq = mlx5_ib_query_srq, 3995 .query_ucontext = mlx5_ib_query_ucontext, 3996 .reg_user_mr = mlx5_ib_reg_user_mr, 3997 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3998 .req_notify_cq = mlx5_ib_arm_cq, 3999 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4000 .resize_cq = mlx5_ib_resize_cq, 4001 4002 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4003 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4004 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4005 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4006 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4007 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4008 }; 4009 4010 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4011 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4012 }; 4013 4014 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4015 .get_vf_config = mlx5_ib_get_vf_config, 4016 .get_vf_guid = mlx5_ib_get_vf_guid, 4017 .get_vf_stats = mlx5_ib_get_vf_stats, 4018 .set_vf_guid = mlx5_ib_set_vf_guid, 4019 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4020 }; 4021 4022 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4023 .alloc_mw = mlx5_ib_alloc_mw, 4024 .dealloc_mw = mlx5_ib_dealloc_mw, 4025 4026 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4027 }; 4028 4029 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4030 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4031 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4032 4033 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4034 }; 4035 4036 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4037 .alloc_dm = mlx5_ib_alloc_dm, 4038 .dealloc_dm = mlx5_ib_dealloc_dm, 4039 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4040 }; 4041 4042 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4043 { 4044 struct mlx5_core_dev *mdev = dev->mdev; 4045 struct mlx5_var_table *var_table = &dev->var_table; 4046 u8 log_doorbell_bar_size; 4047 u8 log_doorbell_stride; 4048 u64 bar_size; 4049 4050 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4051 log_doorbell_bar_size); 4052 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4053 log_doorbell_stride); 4054 var_table->hw_start_addr = dev->mdev->bar_addr + 4055 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4056 doorbell_bar_offset); 4057 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4058 var_table->stride_size = 1ULL << log_doorbell_stride; 4059 var_table->num_var_hw_entries = div_u64(bar_size, 4060 var_table->stride_size); 4061 mutex_init(&var_table->bitmap_lock); 4062 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4063 GFP_KERNEL); 4064 return (var_table->bitmap) ? 0 : -ENOMEM; 4065 } 4066 4067 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4068 { 4069 bitmap_free(dev->var_table.bitmap); 4070 } 4071 4072 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4073 { 4074 struct mlx5_core_dev *mdev = dev->mdev; 4075 int err; 4076 4077 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4078 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4079 ib_set_device_ops(&dev->ib_dev, 4080 &mlx5_ib_dev_ipoib_enhanced_ops); 4081 4082 if (mlx5_core_is_pf(mdev)) 4083 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4084 4085 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4086 4087 if (MLX5_CAP_GEN(mdev, imaicl)) 4088 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4089 4090 if (MLX5_CAP_GEN(mdev, xrc)) 4091 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4092 4093 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4094 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4095 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4096 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4097 4098 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4099 4100 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4101 dev->ib_dev.driver_def = mlx5_ib_defs; 4102 4103 err = init_node_data(dev); 4104 if (err) 4105 return err; 4106 4107 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4108 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4109 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4110 mutex_init(&dev->lb.mutex); 4111 4112 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4114 err = mlx5_ib_init_var_table(dev); 4115 if (err) 4116 return err; 4117 } 4118 4119 dev->ib_dev.use_cq_dim = true; 4120 4121 return 0; 4122 } 4123 4124 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4125 .get_port_immutable = mlx5_port_immutable, 4126 .query_port = mlx5_ib_query_port, 4127 }; 4128 4129 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4130 { 4131 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4132 return 0; 4133 } 4134 4135 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4136 .get_port_immutable = mlx5_port_rep_immutable, 4137 .query_port = mlx5_ib_rep_query_port, 4138 .query_pkey = mlx5_ib_rep_query_pkey, 4139 }; 4140 4141 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4142 { 4143 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4144 return 0; 4145 } 4146 4147 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4148 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4149 .create_wq = mlx5_ib_create_wq, 4150 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4151 .destroy_wq = mlx5_ib_destroy_wq, 4152 .get_netdev = mlx5_ib_get_netdev, 4153 .modify_wq = mlx5_ib_modify_wq, 4154 4155 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4156 ib_rwq_ind_tbl), 4157 }; 4158 4159 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4160 { 4161 struct mlx5_core_dev *mdev = dev->mdev; 4162 enum rdma_link_layer ll; 4163 int port_type_cap; 4164 u8 port_num = 0; 4165 int err; 4166 4167 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4168 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4169 4170 if (ll == IB_LINK_LAYER_ETHERNET) { 4171 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4172 4173 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4174 4175 /* Register only for native ports */ 4176 err = mlx5_add_netdev_notifier(dev, port_num); 4177 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4178 /* 4179 * We don't enable ETH interface for 4180 * 1. IB representors 4181 * 2. User disabled ROCE through devlink interface 4182 */ 4183 return err; 4184 4185 err = mlx5_enable_eth(dev); 4186 if (err) 4187 goto cleanup; 4188 } 4189 4190 return 0; 4191 cleanup: 4192 mlx5_remove_netdev_notifier(dev, port_num); 4193 return err; 4194 } 4195 4196 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4197 { 4198 struct mlx5_core_dev *mdev = dev->mdev; 4199 enum rdma_link_layer ll; 4200 int port_type_cap; 4201 u8 port_num; 4202 4203 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4204 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4205 4206 if (ll == IB_LINK_LAYER_ETHERNET) { 4207 if (!dev->is_rep) 4208 mlx5_disable_eth(dev); 4209 4210 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4211 mlx5_remove_netdev_notifier(dev, port_num); 4212 } 4213 } 4214 4215 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4216 { 4217 mlx5_ib_init_cong_debugfs(dev, 4218 mlx5_core_native_port_num(dev->mdev) - 1); 4219 return 0; 4220 } 4221 4222 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4223 { 4224 mlx5_ib_cleanup_cong_debugfs(dev, 4225 mlx5_core_native_port_num(dev->mdev) - 1); 4226 } 4227 4228 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4229 { 4230 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4231 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4232 } 4233 4234 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4235 { 4236 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4237 } 4238 4239 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4240 { 4241 int err; 4242 4243 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4244 if (err) 4245 return err; 4246 4247 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4248 if (err) 4249 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4250 4251 return err; 4252 } 4253 4254 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4255 { 4256 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4257 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4258 } 4259 4260 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4261 { 4262 const char *name; 4263 4264 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4265 if (!mlx5_lag_is_roce(dev->mdev)) 4266 name = "mlx5_%d"; 4267 else 4268 name = "mlx5_bond_%d"; 4269 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4270 } 4271 4272 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4273 { 4274 int err; 4275 4276 err = mlx5_mr_cache_cleanup(dev); 4277 if (err) 4278 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4279 4280 if (dev->umrc.qp) 4281 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4282 if (dev->umrc.cq) 4283 ib_free_cq(dev->umrc.cq); 4284 if (dev->umrc.pd) 4285 ib_dealloc_pd(dev->umrc.pd); 4286 } 4287 4288 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4289 { 4290 ib_unregister_device(&dev->ib_dev); 4291 } 4292 4293 enum { 4294 MAX_UMR_WR = 128, 4295 }; 4296 4297 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4298 { 4299 struct ib_qp_init_attr *init_attr = NULL; 4300 struct ib_qp_attr *attr = NULL; 4301 struct ib_pd *pd; 4302 struct ib_cq *cq; 4303 struct ib_qp *qp; 4304 int ret; 4305 4306 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4307 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4308 if (!attr || !init_attr) { 4309 ret = -ENOMEM; 4310 goto error_0; 4311 } 4312 4313 pd = ib_alloc_pd(&dev->ib_dev, 0); 4314 if (IS_ERR(pd)) { 4315 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4316 ret = PTR_ERR(pd); 4317 goto error_0; 4318 } 4319 4320 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4321 if (IS_ERR(cq)) { 4322 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4323 ret = PTR_ERR(cq); 4324 goto error_2; 4325 } 4326 4327 init_attr->send_cq = cq; 4328 init_attr->recv_cq = cq; 4329 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4330 init_attr->cap.max_send_wr = MAX_UMR_WR; 4331 init_attr->cap.max_send_sge = 1; 4332 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4333 init_attr->port_num = 1; 4334 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4335 if (IS_ERR(qp)) { 4336 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4337 ret = PTR_ERR(qp); 4338 goto error_3; 4339 } 4340 qp->device = &dev->ib_dev; 4341 qp->real_qp = qp; 4342 qp->uobject = NULL; 4343 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4344 qp->send_cq = init_attr->send_cq; 4345 qp->recv_cq = init_attr->recv_cq; 4346 4347 attr->qp_state = IB_QPS_INIT; 4348 attr->port_num = 1; 4349 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4350 IB_QP_PORT, NULL); 4351 if (ret) { 4352 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4353 goto error_4; 4354 } 4355 4356 memset(attr, 0, sizeof(*attr)); 4357 attr->qp_state = IB_QPS_RTR; 4358 attr->path_mtu = IB_MTU_256; 4359 4360 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4361 if (ret) { 4362 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4363 goto error_4; 4364 } 4365 4366 memset(attr, 0, sizeof(*attr)); 4367 attr->qp_state = IB_QPS_RTS; 4368 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4369 if (ret) { 4370 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4371 goto error_4; 4372 } 4373 4374 dev->umrc.qp = qp; 4375 dev->umrc.cq = cq; 4376 dev->umrc.pd = pd; 4377 4378 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4379 ret = mlx5_mr_cache_init(dev); 4380 if (ret) { 4381 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4382 goto error_4; 4383 } 4384 4385 kfree(attr); 4386 kfree(init_attr); 4387 4388 return 0; 4389 4390 error_4: 4391 mlx5_ib_destroy_qp(qp, NULL); 4392 dev->umrc.qp = NULL; 4393 4394 error_3: 4395 ib_free_cq(cq); 4396 dev->umrc.cq = NULL; 4397 4398 error_2: 4399 ib_dealloc_pd(pd); 4400 dev->umrc.pd = NULL; 4401 4402 error_0: 4403 kfree(attr); 4404 kfree(init_attr); 4405 return ret; 4406 } 4407 4408 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4409 { 4410 struct dentry *root; 4411 4412 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4413 return 0; 4414 4415 mutex_init(&dev->delay_drop.lock); 4416 dev->delay_drop.dev = dev; 4417 dev->delay_drop.activate = false; 4418 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4419 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4420 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4421 atomic_set(&dev->delay_drop.events_cnt, 0); 4422 4423 if (!mlx5_debugfs_root) 4424 return 0; 4425 4426 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4427 dev->delay_drop.dir_debugfs = root; 4428 4429 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4430 &dev->delay_drop.events_cnt); 4431 debugfs_create_atomic_t("num_rqs", 0400, root, 4432 &dev->delay_drop.rqs_cnt); 4433 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4434 &fops_delay_drop_timeout); 4435 return 0; 4436 } 4437 4438 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4439 { 4440 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4441 return; 4442 4443 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4444 if (!dev->delay_drop.dir_debugfs) 4445 return; 4446 4447 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4448 dev->delay_drop.dir_debugfs = NULL; 4449 } 4450 4451 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4452 { 4453 dev->mdev_events.notifier_call = mlx5_ib_event; 4454 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4455 return 0; 4456 } 4457 4458 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4459 { 4460 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4461 } 4462 4463 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4464 const struct mlx5_ib_profile *profile, 4465 int stage) 4466 { 4467 dev->ib_active = false; 4468 4469 /* Number of stages to cleanup */ 4470 while (stage) { 4471 stage--; 4472 if (profile->stage[stage].cleanup) 4473 profile->stage[stage].cleanup(dev); 4474 } 4475 4476 kfree(dev->port); 4477 ib_dealloc_device(&dev->ib_dev); 4478 } 4479 4480 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4481 const struct mlx5_ib_profile *profile) 4482 { 4483 int err; 4484 int i; 4485 4486 dev->profile = profile; 4487 4488 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4489 if (profile->stage[i].init) { 4490 err = profile->stage[i].init(dev); 4491 if (err) 4492 goto err_out; 4493 } 4494 } 4495 4496 dev->ib_active = true; 4497 return 0; 4498 4499 err_out: 4500 /* Clean up stages which were initialized */ 4501 while (i) { 4502 i--; 4503 if (profile->stage[i].cleanup) 4504 profile->stage[i].cleanup(dev); 4505 } 4506 return -ENOMEM; 4507 } 4508 4509 static const struct mlx5_ib_profile pf_profile = { 4510 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4511 mlx5_ib_stage_init_init, 4512 mlx5_ib_stage_init_cleanup), 4513 STAGE_CREATE(MLX5_IB_STAGE_FS, 4514 mlx5_ib_fs_init, 4515 mlx5_ib_fs_cleanup), 4516 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4517 mlx5_ib_stage_caps_init, 4518 mlx5_ib_stage_caps_cleanup), 4519 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4520 mlx5_ib_stage_non_default_cb, 4521 NULL), 4522 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4523 mlx5_ib_roce_init, 4524 mlx5_ib_roce_cleanup), 4525 STAGE_CREATE(MLX5_IB_STAGE_QP, 4526 mlx5_init_qp_table, 4527 mlx5_cleanup_qp_table), 4528 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4529 mlx5_init_srq_table, 4530 mlx5_cleanup_srq_table), 4531 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4532 mlx5_ib_dev_res_init, 4533 mlx5_ib_dev_res_cleanup), 4534 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4535 mlx5_ib_stage_dev_notifier_init, 4536 mlx5_ib_stage_dev_notifier_cleanup), 4537 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4538 mlx5_ib_odp_init_one, 4539 mlx5_ib_odp_cleanup_one), 4540 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4541 mlx5_ib_counters_init, 4542 mlx5_ib_counters_cleanup), 4543 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4544 mlx5_ib_stage_cong_debugfs_init, 4545 mlx5_ib_stage_cong_debugfs_cleanup), 4546 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4547 mlx5_ib_stage_uar_init, 4548 mlx5_ib_stage_uar_cleanup), 4549 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4550 mlx5_ib_stage_bfrag_init, 4551 mlx5_ib_stage_bfrag_cleanup), 4552 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4553 NULL, 4554 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4555 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4556 mlx5_ib_devx_init, 4557 mlx5_ib_devx_cleanup), 4558 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4559 mlx5_ib_stage_ib_reg_init, 4560 mlx5_ib_stage_ib_reg_cleanup), 4561 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4562 mlx5_ib_stage_post_ib_reg_umr_init, 4563 NULL), 4564 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4565 mlx5_ib_stage_delay_drop_init, 4566 mlx5_ib_stage_delay_drop_cleanup), 4567 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4568 mlx5_ib_restrack_init, 4569 NULL), 4570 }; 4571 4572 const struct mlx5_ib_profile raw_eth_profile = { 4573 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4574 mlx5_ib_stage_init_init, 4575 mlx5_ib_stage_init_cleanup), 4576 STAGE_CREATE(MLX5_IB_STAGE_FS, 4577 mlx5_ib_fs_init, 4578 mlx5_ib_fs_cleanup), 4579 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4580 mlx5_ib_stage_caps_init, 4581 mlx5_ib_stage_caps_cleanup), 4582 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4583 mlx5_ib_stage_raw_eth_non_default_cb, 4584 NULL), 4585 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4586 mlx5_ib_roce_init, 4587 mlx5_ib_roce_cleanup), 4588 STAGE_CREATE(MLX5_IB_STAGE_QP, 4589 mlx5_init_qp_table, 4590 mlx5_cleanup_qp_table), 4591 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4592 mlx5_init_srq_table, 4593 mlx5_cleanup_srq_table), 4594 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4595 mlx5_ib_dev_res_init, 4596 mlx5_ib_dev_res_cleanup), 4597 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4598 mlx5_ib_stage_dev_notifier_init, 4599 mlx5_ib_stage_dev_notifier_cleanup), 4600 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4601 mlx5_ib_counters_init, 4602 mlx5_ib_counters_cleanup), 4603 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4604 mlx5_ib_stage_cong_debugfs_init, 4605 mlx5_ib_stage_cong_debugfs_cleanup), 4606 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4607 mlx5_ib_stage_uar_init, 4608 mlx5_ib_stage_uar_cleanup), 4609 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4610 mlx5_ib_stage_bfrag_init, 4611 mlx5_ib_stage_bfrag_cleanup), 4612 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4613 NULL, 4614 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4615 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4616 mlx5_ib_devx_init, 4617 mlx5_ib_devx_cleanup), 4618 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4619 mlx5_ib_stage_ib_reg_init, 4620 mlx5_ib_stage_ib_reg_cleanup), 4621 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4622 mlx5_ib_stage_post_ib_reg_umr_init, 4623 NULL), 4624 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4625 mlx5_ib_restrack_init, 4626 NULL), 4627 }; 4628 4629 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4630 const struct auxiliary_device_id *id) 4631 { 4632 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4633 struct mlx5_core_dev *mdev = idev->mdev; 4634 struct mlx5_ib_multiport_info *mpi; 4635 struct mlx5_ib_dev *dev; 4636 bool bound = false; 4637 int err; 4638 4639 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4640 if (!mpi) 4641 return -ENOMEM; 4642 4643 mpi->mdev = mdev; 4644 err = mlx5_query_nic_vport_system_image_guid(mdev, 4645 &mpi->sys_image_guid); 4646 if (err) { 4647 kfree(mpi); 4648 return err; 4649 } 4650 4651 mutex_lock(&mlx5_ib_multiport_mutex); 4652 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4653 if (dev->sys_image_guid == mpi->sys_image_guid) 4654 bound = mlx5_ib_bind_slave_port(dev, mpi); 4655 4656 if (bound) { 4657 rdma_roce_rescan_device(&dev->ib_dev); 4658 break; 4659 } 4660 } 4661 4662 if (!bound) { 4663 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4664 dev_dbg(mdev->device, 4665 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4666 } 4667 mutex_unlock(&mlx5_ib_multiport_mutex); 4668 4669 dev_set_drvdata(&adev->dev, mpi); 4670 return 0; 4671 } 4672 4673 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4674 { 4675 struct mlx5_ib_multiport_info *mpi; 4676 4677 mpi = dev_get_drvdata(&adev->dev); 4678 mutex_lock(&mlx5_ib_multiport_mutex); 4679 if (mpi->ibdev) 4680 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4681 list_del(&mpi->list); 4682 mutex_unlock(&mlx5_ib_multiport_mutex); 4683 kfree(mpi); 4684 } 4685 4686 static int mlx5r_probe(struct auxiliary_device *adev, 4687 const struct auxiliary_device_id *id) 4688 { 4689 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4690 struct mlx5_core_dev *mdev = idev->mdev; 4691 const struct mlx5_ib_profile *profile; 4692 int port_type_cap, num_ports, ret; 4693 enum rdma_link_layer ll; 4694 struct mlx5_ib_dev *dev; 4695 4696 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4697 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4698 4699 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4700 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4701 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4702 if (!dev) 4703 return -ENOMEM; 4704 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4705 GFP_KERNEL); 4706 if (!dev->port) { 4707 ib_dealloc_device(&dev->ib_dev); 4708 return -ENOMEM; 4709 } 4710 4711 dev->mdev = mdev; 4712 dev->num_ports = num_ports; 4713 4714 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4715 profile = &raw_eth_profile; 4716 else 4717 profile = &pf_profile; 4718 4719 ret = __mlx5_ib_add(dev, profile); 4720 if (ret) { 4721 kfree(dev->port); 4722 ib_dealloc_device(&dev->ib_dev); 4723 return ret; 4724 } 4725 4726 dev_set_drvdata(&adev->dev, dev); 4727 return 0; 4728 } 4729 4730 static void mlx5r_remove(struct auxiliary_device *adev) 4731 { 4732 struct mlx5_ib_dev *dev; 4733 4734 dev = dev_get_drvdata(&adev->dev); 4735 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4736 } 4737 4738 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4739 { .name = MLX5_ADEV_NAME ".multiport", }, 4740 {}, 4741 }; 4742 4743 static const struct auxiliary_device_id mlx5r_id_table[] = { 4744 { .name = MLX5_ADEV_NAME ".rdma", }, 4745 {}, 4746 }; 4747 4748 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4749 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4750 4751 static struct auxiliary_driver mlx5r_mp_driver = { 4752 .name = "multiport", 4753 .probe = mlx5r_mp_probe, 4754 .remove = mlx5r_mp_remove, 4755 .id_table = mlx5r_mp_id_table, 4756 }; 4757 4758 static struct auxiliary_driver mlx5r_driver = { 4759 .name = "rdma", 4760 .probe = mlx5r_probe, 4761 .remove = mlx5r_remove, 4762 .id_table = mlx5r_id_table, 4763 }; 4764 4765 static int __init mlx5_ib_init(void) 4766 { 4767 int ret; 4768 4769 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4770 if (!xlt_emergency_page) 4771 return -ENOMEM; 4772 4773 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4774 if (!mlx5_ib_event_wq) { 4775 free_page((unsigned long)xlt_emergency_page); 4776 return -ENOMEM; 4777 } 4778 4779 mlx5_ib_odp_init(); 4780 ret = mlx5r_rep_init(); 4781 if (ret) 4782 goto rep_err; 4783 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4784 if (ret) 4785 goto mp_err; 4786 ret = auxiliary_driver_register(&mlx5r_driver); 4787 if (ret) 4788 goto drv_err; 4789 return 0; 4790 4791 drv_err: 4792 auxiliary_driver_unregister(&mlx5r_mp_driver); 4793 mp_err: 4794 mlx5r_rep_cleanup(); 4795 rep_err: 4796 destroy_workqueue(mlx5_ib_event_wq); 4797 free_page((unsigned long)xlt_emergency_page); 4798 return ret; 4799 } 4800 4801 static void __exit mlx5_ib_cleanup(void) 4802 { 4803 auxiliary_driver_unregister(&mlx5r_driver); 4804 auxiliary_driver_unregister(&mlx5r_mp_driver); 4805 mlx5r_rep_cleanup(); 4806 4807 destroy_workqueue(mlx5_ib_event_wq); 4808 free_page((unsigned long)xlt_emergency_page); 4809 } 4810 4811 module_init(mlx5_ib_init); 4812 module_exit(mlx5_ib_cleanup); 4813