1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include <linux/mlx5/accel.h> 45 #include <rdma/uverbs_std_types.h> 46 #include <rdma/uverbs_ioctl.h> 47 #include <rdma/mlx5_user_ioctl_verbs.h> 48 #include <rdma/mlx5_user_ioctl_cmds.h> 49 #include <rdma/ib_umem_odp.h> 50 51 #define UVERBS_MODULE_NAME mlx5_ib 52 #include <rdma/uverbs_named_ioctl.h> 53 54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 56 MODULE_LICENSE("Dual BSD/GPL"); 57 58 struct mlx5_ib_event_work { 59 struct work_struct work; 60 union { 61 struct mlx5_ib_dev *dev; 62 struct mlx5_ib_multiport_info *mpi; 63 }; 64 bool is_slave; 65 unsigned int event; 66 void *param; 67 }; 68 69 enum { 70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 71 }; 72 73 static struct workqueue_struct *mlx5_ib_event_wq; 74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 75 static LIST_HEAD(mlx5_ib_dev_list); 76 /* 77 * This mutex should be held when accessing either of the above lists 78 */ 79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 80 81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 82 { 83 struct mlx5_ib_dev *dev; 84 85 mutex_lock(&mlx5_ib_multiport_mutex); 86 dev = mpi->ibdev; 87 mutex_unlock(&mlx5_ib_multiport_mutex); 88 return dev; 89 } 90 91 static enum rdma_link_layer 92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 93 { 94 switch (port_type_cap) { 95 case MLX5_CAP_PORT_TYPE_IB: 96 return IB_LINK_LAYER_INFINIBAND; 97 case MLX5_CAP_PORT_TYPE_ETH: 98 return IB_LINK_LAYER_ETHERNET; 99 default: 100 return IB_LINK_LAYER_UNSPECIFIED; 101 } 102 } 103 104 static enum rdma_link_layer 105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 106 { 107 struct mlx5_ib_dev *dev = to_mdev(device); 108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 109 110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 111 } 112 113 static int get_port_state(struct ib_device *ibdev, 114 u32 port_num, 115 enum ib_port_state *state) 116 { 117 struct ib_port_attr attr; 118 int ret; 119 120 memset(&attr, 0, sizeof(attr)); 121 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 122 if (!ret) 123 *state = attr.state; 124 return ret; 125 } 126 127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 128 struct net_device *ndev, 129 struct net_device *upper, 130 u32 *port_num) 131 { 132 struct net_device *rep_ndev; 133 struct mlx5_ib_port *port; 134 int i; 135 136 for (i = 0; i < dev->num_ports; i++) { 137 port = &dev->port[i]; 138 if (!port->rep) 139 continue; 140 141 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 142 *port_num = i + 1; 143 return &port->roce; 144 } 145 146 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 147 continue; 148 149 read_lock(&port->roce.netdev_lock); 150 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 151 port->rep->vport); 152 if (rep_ndev == ndev) { 153 read_unlock(&port->roce.netdev_lock); 154 *port_num = i + 1; 155 return &port->roce; 156 } 157 read_unlock(&port->roce.netdev_lock); 158 } 159 160 return NULL; 161 } 162 163 static int mlx5_netdev_event(struct notifier_block *this, 164 unsigned long event, void *ptr) 165 { 166 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 167 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 168 u32 port_num = roce->native_port_num; 169 struct mlx5_core_dev *mdev; 170 struct mlx5_ib_dev *ibdev; 171 172 ibdev = roce->dev; 173 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 174 if (!mdev) 175 return NOTIFY_DONE; 176 177 switch (event) { 178 case NETDEV_REGISTER: 179 /* Should already be registered during the load */ 180 if (ibdev->is_rep) 181 break; 182 write_lock(&roce->netdev_lock); 183 if (ndev->dev.parent == mdev->device) 184 roce->netdev = ndev; 185 write_unlock(&roce->netdev_lock); 186 break; 187 188 case NETDEV_UNREGISTER: 189 /* In case of reps, ib device goes away before the netdevs */ 190 write_lock(&roce->netdev_lock); 191 if (roce->netdev == ndev) 192 roce->netdev = NULL; 193 write_unlock(&roce->netdev_lock); 194 break; 195 196 case NETDEV_CHANGE: 197 case NETDEV_UP: 198 case NETDEV_DOWN: { 199 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 200 struct net_device *upper = NULL; 201 202 if (lag_ndev) { 203 upper = netdev_master_upper_dev_get(lag_ndev); 204 dev_put(lag_ndev); 205 } 206 207 if (ibdev->is_rep) 208 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 209 if (!roce) 210 return NOTIFY_DONE; 211 if ((upper == ndev || 212 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 213 ibdev->ib_active) { 214 struct ib_event ibev = { }; 215 enum ib_port_state port_state; 216 217 if (get_port_state(&ibdev->ib_dev, port_num, 218 &port_state)) 219 goto done; 220 221 if (roce->last_port_state == port_state) 222 goto done; 223 224 roce->last_port_state = port_state; 225 ibev.device = &ibdev->ib_dev; 226 if (port_state == IB_PORT_DOWN) 227 ibev.event = IB_EVENT_PORT_ERR; 228 else if (port_state == IB_PORT_ACTIVE) 229 ibev.event = IB_EVENT_PORT_ACTIVE; 230 else 231 goto done; 232 233 ibev.element.port_num = port_num; 234 ib_dispatch_event(&ibev); 235 } 236 break; 237 } 238 239 default: 240 break; 241 } 242 done: 243 mlx5_ib_put_native_port_mdev(ibdev, port_num); 244 return NOTIFY_DONE; 245 } 246 247 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 248 u32 port_num) 249 { 250 struct mlx5_ib_dev *ibdev = to_mdev(device); 251 struct net_device *ndev; 252 struct mlx5_core_dev *mdev; 253 254 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 255 if (!mdev) 256 return NULL; 257 258 ndev = mlx5_lag_get_roce_netdev(mdev); 259 if (ndev) 260 goto out; 261 262 /* Ensure ndev does not disappear before we invoke dev_hold() 263 */ 264 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 265 ndev = ibdev->port[port_num - 1].roce.netdev; 266 if (ndev) 267 dev_hold(ndev); 268 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 269 270 out: 271 mlx5_ib_put_native_port_mdev(ibdev, port_num); 272 return ndev; 273 } 274 275 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 276 u32 ib_port_num, 277 u32 *native_port_num) 278 { 279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 280 ib_port_num); 281 struct mlx5_core_dev *mdev = NULL; 282 struct mlx5_ib_multiport_info *mpi; 283 struct mlx5_ib_port *port; 284 285 if (!mlx5_core_mp_enabled(ibdev->mdev) || 286 ll != IB_LINK_LAYER_ETHERNET) { 287 if (native_port_num) 288 *native_port_num = ib_port_num; 289 return ibdev->mdev; 290 } 291 292 if (native_port_num) 293 *native_port_num = 1; 294 295 port = &ibdev->port[ib_port_num - 1]; 296 spin_lock(&port->mp.mpi_lock); 297 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 298 if (mpi && !mpi->unaffiliate) { 299 mdev = mpi->mdev; 300 /* If it's the master no need to refcount, it'll exist 301 * as long as the ib_dev exists. 302 */ 303 if (!mpi->is_master) 304 mpi->mdev_refcnt++; 305 } 306 spin_unlock(&port->mp.mpi_lock); 307 308 return mdev; 309 } 310 311 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 312 { 313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 314 port_num); 315 struct mlx5_ib_multiport_info *mpi; 316 struct mlx5_ib_port *port; 317 318 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 319 return; 320 321 port = &ibdev->port[port_num - 1]; 322 323 spin_lock(&port->mp.mpi_lock); 324 mpi = ibdev->port[port_num - 1].mp.mpi; 325 if (mpi->is_master) 326 goto out; 327 328 mpi->mdev_refcnt--; 329 if (mpi->unaffiliate) 330 complete(&mpi->unref_comp); 331 out: 332 spin_unlock(&port->mp.mpi_lock); 333 } 334 335 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 336 u16 *active_speed, u8 *active_width) 337 { 338 switch (eth_proto_oper) { 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 340 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 341 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 342 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 343 *active_width = IB_WIDTH_1X; 344 *active_speed = IB_SPEED_SDR; 345 break; 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 352 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 353 *active_width = IB_WIDTH_1X; 354 *active_speed = IB_SPEED_QDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 358 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 359 *active_width = IB_WIDTH_1X; 360 *active_speed = IB_SPEED_EDR; 361 break; 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 365 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 366 *active_width = IB_WIDTH_4X; 367 *active_speed = IB_SPEED_QDR; 368 break; 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 371 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 372 *active_width = IB_WIDTH_1X; 373 *active_speed = IB_SPEED_HDR; 374 break; 375 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 376 *active_width = IB_WIDTH_4X; 377 *active_speed = IB_SPEED_FDR; 378 break; 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 382 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 383 *active_width = IB_WIDTH_4X; 384 *active_speed = IB_SPEED_EDR; 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 return 0; 391 } 392 393 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 394 u8 *active_width) 395 { 396 switch (eth_proto_oper) { 397 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 398 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 399 *active_width = IB_WIDTH_1X; 400 *active_speed = IB_SPEED_SDR; 401 break; 402 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_DDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 407 *active_width = IB_WIDTH_1X; 408 *active_speed = IB_SPEED_QDR; 409 break; 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 415 *active_width = IB_WIDTH_1X; 416 *active_speed = IB_SPEED_EDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 419 *active_width = IB_WIDTH_2X; 420 *active_speed = IB_SPEED_EDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 423 *active_width = IB_WIDTH_1X; 424 *active_speed = IB_SPEED_HDR; 425 break; 426 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 431 *active_width = IB_WIDTH_2X; 432 *active_speed = IB_SPEED_HDR; 433 break; 434 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 435 *active_width = IB_WIDTH_1X; 436 *active_speed = IB_SPEED_NDR; 437 break; 438 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 439 *active_width = IB_WIDTH_4X; 440 *active_speed = IB_SPEED_HDR; 441 break; 442 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 443 *active_width = IB_WIDTH_2X; 444 *active_speed = IB_SPEED_NDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 447 *active_width = IB_WIDTH_4X; 448 *active_speed = IB_SPEED_NDR; 449 break; 450 default: 451 return -EINVAL; 452 } 453 454 return 0; 455 } 456 457 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 458 u8 *active_width, bool ext) 459 { 460 return ext ? 461 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 462 active_width) : 463 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 464 active_width); 465 } 466 467 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 468 struct ib_port_attr *props) 469 { 470 struct mlx5_ib_dev *dev = to_mdev(device); 471 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 472 struct mlx5_core_dev *mdev; 473 struct net_device *ndev, *upper; 474 enum ib_mtu ndev_ib_mtu; 475 bool put_mdev = true; 476 u32 eth_prot_oper; 477 u32 mdev_port_num; 478 bool ext; 479 int err; 480 481 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 482 if (!mdev) { 483 /* This means the port isn't affiliated yet. Get the 484 * info for the master port instead. 485 */ 486 put_mdev = false; 487 mdev = dev->mdev; 488 mdev_port_num = 1; 489 port_num = 1; 490 } 491 492 /* Possible bad flows are checked before filling out props so in case 493 * of an error it will still be zeroed out. 494 * Use native port in case of reps 495 */ 496 if (dev->is_rep) 497 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 498 1); 499 else 500 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 501 mdev_port_num); 502 if (err) 503 goto out; 504 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 505 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 506 507 props->active_width = IB_WIDTH_4X; 508 props->active_speed = IB_SPEED_QDR; 509 510 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 511 &props->active_width, ext); 512 513 if (!dev->is_rep && dev->mdev->roce.roce_en) { 514 u16 qkey_viol_cntr; 515 516 props->port_cap_flags |= IB_PORT_CM_SUP; 517 props->ip_gids = true; 518 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 519 roce_address_table_size); 520 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 521 props->qkey_viol_cntr = qkey_viol_cntr; 522 } 523 props->max_mtu = IB_MTU_4096; 524 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 525 props->pkey_tbl_len = 1; 526 props->state = IB_PORT_DOWN; 527 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 528 529 /* If this is a stub query for an unaffiliated port stop here */ 530 if (!put_mdev) 531 goto out; 532 533 ndev = mlx5_ib_get_netdev(device, port_num); 534 if (!ndev) 535 goto out; 536 537 if (dev->lag_active) { 538 rcu_read_lock(); 539 upper = netdev_master_upper_dev_get_rcu(ndev); 540 if (upper) { 541 dev_put(ndev); 542 ndev = upper; 543 dev_hold(ndev); 544 } 545 rcu_read_unlock(); 546 } 547 548 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 549 props->state = IB_PORT_ACTIVE; 550 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 551 } 552 553 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 554 555 dev_put(ndev); 556 557 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 558 out: 559 if (put_mdev) 560 mlx5_ib_put_native_port_mdev(dev, port_num); 561 return err; 562 } 563 564 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 565 unsigned int index, const union ib_gid *gid, 566 const struct ib_gid_attr *attr) 567 { 568 enum ib_gid_type gid_type; 569 u16 vlan_id = 0xffff; 570 u8 roce_version = 0; 571 u8 roce_l3_type = 0; 572 u8 mac[ETH_ALEN]; 573 int ret; 574 575 gid_type = attr->gid_type; 576 if (gid) { 577 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 578 if (ret) 579 return ret; 580 } 581 582 switch (gid_type) { 583 case IB_GID_TYPE_ROCE: 584 roce_version = MLX5_ROCE_VERSION_1; 585 break; 586 case IB_GID_TYPE_ROCE_UDP_ENCAP: 587 roce_version = MLX5_ROCE_VERSION_2; 588 if (gid && ipv6_addr_v4mapped((void *)gid)) 589 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 590 else 591 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 592 break; 593 594 default: 595 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 596 } 597 598 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 599 roce_l3_type, gid->raw, mac, 600 vlan_id < VLAN_CFI_MASK, vlan_id, 601 port_num); 602 } 603 604 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 605 __always_unused void **context) 606 { 607 return set_roce_addr(to_mdev(attr->device), attr->port_num, 608 attr->index, &attr->gid, attr); 609 } 610 611 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 612 __always_unused void **context) 613 { 614 return set_roce_addr(to_mdev(attr->device), attr->port_num, 615 attr->index, NULL, attr); 616 } 617 618 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 619 const struct ib_gid_attr *attr) 620 { 621 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 622 return 0; 623 624 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 625 } 626 627 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 628 { 629 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 630 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 631 return 0; 632 } 633 634 enum { 635 MLX5_VPORT_ACCESS_METHOD_MAD, 636 MLX5_VPORT_ACCESS_METHOD_HCA, 637 MLX5_VPORT_ACCESS_METHOD_NIC, 638 }; 639 640 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 641 { 642 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 643 return MLX5_VPORT_ACCESS_METHOD_MAD; 644 645 if (mlx5_ib_port_link_layer(ibdev, 1) == 646 IB_LINK_LAYER_ETHERNET) 647 return MLX5_VPORT_ACCESS_METHOD_NIC; 648 649 return MLX5_VPORT_ACCESS_METHOD_HCA; 650 } 651 652 static void get_atomic_caps(struct mlx5_ib_dev *dev, 653 u8 atomic_size_qp, 654 struct ib_device_attr *props) 655 { 656 u8 tmp; 657 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 658 u8 atomic_req_8B_endianness_mode = 659 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 660 661 /* Check if HW supports 8 bytes standard atomic operations and capable 662 * of host endianness respond 663 */ 664 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 665 if (((atomic_operations & tmp) == tmp) && 666 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 667 (atomic_req_8B_endianness_mode)) { 668 props->atomic_cap = IB_ATOMIC_HCA; 669 } else { 670 props->atomic_cap = IB_ATOMIC_NONE; 671 } 672 } 673 674 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 675 struct ib_device_attr *props) 676 { 677 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 678 679 get_atomic_caps(dev, atomic_size_qp, props); 680 } 681 682 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 683 __be64 *sys_image_guid) 684 { 685 struct mlx5_ib_dev *dev = to_mdev(ibdev); 686 struct mlx5_core_dev *mdev = dev->mdev; 687 u64 tmp; 688 int err; 689 690 switch (mlx5_get_vport_access_method(ibdev)) { 691 case MLX5_VPORT_ACCESS_METHOD_MAD: 692 return mlx5_query_mad_ifc_system_image_guid(ibdev, 693 sys_image_guid); 694 695 case MLX5_VPORT_ACCESS_METHOD_HCA: 696 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 697 break; 698 699 case MLX5_VPORT_ACCESS_METHOD_NIC: 700 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 701 break; 702 703 default: 704 return -EINVAL; 705 } 706 707 if (!err) 708 *sys_image_guid = cpu_to_be64(tmp); 709 710 return err; 711 712 } 713 714 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 715 u16 *max_pkeys) 716 { 717 struct mlx5_ib_dev *dev = to_mdev(ibdev); 718 struct mlx5_core_dev *mdev = dev->mdev; 719 720 switch (mlx5_get_vport_access_method(ibdev)) { 721 case MLX5_VPORT_ACCESS_METHOD_MAD: 722 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 723 724 case MLX5_VPORT_ACCESS_METHOD_HCA: 725 case MLX5_VPORT_ACCESS_METHOD_NIC: 726 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 727 pkey_table_size)); 728 return 0; 729 730 default: 731 return -EINVAL; 732 } 733 } 734 735 static int mlx5_query_vendor_id(struct ib_device *ibdev, 736 u32 *vendor_id) 737 { 738 struct mlx5_ib_dev *dev = to_mdev(ibdev); 739 740 switch (mlx5_get_vport_access_method(ibdev)) { 741 case MLX5_VPORT_ACCESS_METHOD_MAD: 742 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 743 744 case MLX5_VPORT_ACCESS_METHOD_HCA: 745 case MLX5_VPORT_ACCESS_METHOD_NIC: 746 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 747 748 default: 749 return -EINVAL; 750 } 751 } 752 753 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 754 __be64 *node_guid) 755 { 756 u64 tmp; 757 int err; 758 759 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 760 case MLX5_VPORT_ACCESS_METHOD_MAD: 761 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 762 763 case MLX5_VPORT_ACCESS_METHOD_HCA: 764 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 765 break; 766 767 case MLX5_VPORT_ACCESS_METHOD_NIC: 768 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 769 break; 770 771 default: 772 return -EINVAL; 773 } 774 775 if (!err) 776 *node_guid = cpu_to_be64(tmp); 777 778 return err; 779 } 780 781 struct mlx5_reg_node_desc { 782 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 783 }; 784 785 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 786 { 787 struct mlx5_reg_node_desc in; 788 789 if (mlx5_use_mad_ifc(dev)) 790 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 791 792 memset(&in, 0, sizeof(in)); 793 794 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 795 sizeof(struct mlx5_reg_node_desc), 796 MLX5_REG_NODE_DESC, 0, 0); 797 } 798 799 static int mlx5_ib_query_device(struct ib_device *ibdev, 800 struct ib_device_attr *props, 801 struct ib_udata *uhw) 802 { 803 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 804 struct mlx5_ib_dev *dev = to_mdev(ibdev); 805 struct mlx5_core_dev *mdev = dev->mdev; 806 int err = -ENOMEM; 807 int max_sq_desc; 808 int max_rq_sg; 809 int max_sq_sg; 810 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 811 bool raw_support = !mlx5_core_mp_enabled(mdev); 812 struct mlx5_ib_query_device_resp resp = {}; 813 size_t resp_len; 814 u64 max_tso; 815 816 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 817 if (uhw_outlen && uhw_outlen < resp_len) 818 return -EINVAL; 819 820 resp.response_length = resp_len; 821 822 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 823 return -EINVAL; 824 825 memset(props, 0, sizeof(*props)); 826 err = mlx5_query_system_image_guid(ibdev, 827 &props->sys_image_guid); 828 if (err) 829 return err; 830 831 props->max_pkeys = dev->pkey_table_len; 832 833 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 834 if (err) 835 return err; 836 837 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 838 (fw_rev_min(dev->mdev) << 16) | 839 fw_rev_sub(dev->mdev); 840 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 841 IB_DEVICE_PORT_ACTIVE_EVENT | 842 IB_DEVICE_SYS_IMAGE_GUID | 843 IB_DEVICE_RC_RNR_NAK_GEN; 844 845 if (MLX5_CAP_GEN(mdev, pkv)) 846 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 847 if (MLX5_CAP_GEN(mdev, qkv)) 848 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 849 if (MLX5_CAP_GEN(mdev, apm)) 850 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 851 if (MLX5_CAP_GEN(mdev, xrc)) 852 props->device_cap_flags |= IB_DEVICE_XRC; 853 if (MLX5_CAP_GEN(mdev, imaicl)) { 854 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 855 IB_DEVICE_MEM_WINDOW_TYPE_2B; 856 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 857 /* We support 'Gappy' memory registration too */ 858 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 859 } 860 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 861 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 862 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 863 if (MLX5_CAP_GEN(mdev, sho)) { 864 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 865 /* At this stage no support for signature handover */ 866 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 867 IB_PROT_T10DIF_TYPE_2 | 868 IB_PROT_T10DIF_TYPE_3; 869 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 870 IB_GUARD_T10DIF_CSUM; 871 } 872 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 873 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 874 875 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 876 if (MLX5_CAP_ETH(mdev, csum_cap)) { 877 /* Legacy bit to support old userspace libraries */ 878 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 879 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 880 } 881 882 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 883 props->raw_packet_caps |= 884 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 885 886 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 887 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 888 if (max_tso) { 889 resp.tso_caps.max_tso = 1 << max_tso; 890 resp.tso_caps.supported_qpts |= 891 1 << IB_QPT_RAW_PACKET; 892 resp.response_length += sizeof(resp.tso_caps); 893 } 894 } 895 896 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 897 resp.rss_caps.rx_hash_function = 898 MLX5_RX_HASH_FUNC_TOEPLITZ; 899 resp.rss_caps.rx_hash_fields_mask = 900 MLX5_RX_HASH_SRC_IPV4 | 901 MLX5_RX_HASH_DST_IPV4 | 902 MLX5_RX_HASH_SRC_IPV6 | 903 MLX5_RX_HASH_DST_IPV6 | 904 MLX5_RX_HASH_SRC_PORT_TCP | 905 MLX5_RX_HASH_DST_PORT_TCP | 906 MLX5_RX_HASH_SRC_PORT_UDP | 907 MLX5_RX_HASH_DST_PORT_UDP | 908 MLX5_RX_HASH_INNER; 909 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 910 MLX5_ACCEL_IPSEC_CAP_DEVICE) 911 resp.rss_caps.rx_hash_fields_mask |= 912 MLX5_RX_HASH_IPSEC_SPI; 913 resp.response_length += sizeof(resp.rss_caps); 914 } 915 } else { 916 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 917 resp.response_length += sizeof(resp.tso_caps); 918 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 919 resp.response_length += sizeof(resp.rss_caps); 920 } 921 922 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 923 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 924 props->device_cap_flags |= IB_DEVICE_UD_TSO; 925 } 926 927 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 928 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 929 raw_support) 930 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 931 932 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 933 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 934 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 935 936 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 937 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 938 raw_support) { 939 /* Legacy bit to support old userspace libraries */ 940 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 941 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 942 } 943 944 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 945 props->max_dm_size = 946 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 947 } 948 949 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 950 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 951 952 if (MLX5_CAP_GEN(mdev, end_pad)) 953 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 954 955 props->vendor_part_id = mdev->pdev->device; 956 props->hw_ver = mdev->pdev->revision; 957 958 props->max_mr_size = ~0ull; 959 props->page_size_cap = ~(min_page_size - 1); 960 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 961 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 962 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 963 sizeof(struct mlx5_wqe_data_seg); 964 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 965 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 966 sizeof(struct mlx5_wqe_raddr_seg)) / 967 sizeof(struct mlx5_wqe_data_seg); 968 props->max_send_sge = max_sq_sg; 969 props->max_recv_sge = max_rq_sg; 970 props->max_sge_rd = MLX5_MAX_SGE_RD; 971 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 972 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 973 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 974 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 975 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 976 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 977 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 978 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 979 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 980 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 981 props->max_srq_sge = max_rq_sg - 1; 982 props->max_fast_reg_page_list_len = 983 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 984 props->max_pi_fast_reg_page_list_len = 985 props->max_fast_reg_page_list_len / 2; 986 props->max_sgl_rd = 987 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 988 get_atomic_caps_qp(dev, props); 989 props->masked_atomic_cap = IB_ATOMIC_NONE; 990 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 991 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 992 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 993 props->max_mcast_grp; 994 props->max_ah = INT_MAX; 995 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 996 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 997 998 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 999 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1000 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1001 props->odp_caps = dev->odp_caps; 1002 if (!uhw) { 1003 /* ODP for kernel QPs is not implemented for receive 1004 * WQEs and SRQ WQEs 1005 */ 1006 props->odp_caps.per_transport_caps.rc_odp_caps &= 1007 ~(IB_ODP_SUPPORT_READ | 1008 IB_ODP_SUPPORT_SRQ_RECV); 1009 props->odp_caps.per_transport_caps.uc_odp_caps &= 1010 ~(IB_ODP_SUPPORT_READ | 1011 IB_ODP_SUPPORT_SRQ_RECV); 1012 props->odp_caps.per_transport_caps.ud_odp_caps &= 1013 ~(IB_ODP_SUPPORT_READ | 1014 IB_ODP_SUPPORT_SRQ_RECV); 1015 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1016 ~(IB_ODP_SUPPORT_READ | 1017 IB_ODP_SUPPORT_SRQ_RECV); 1018 } 1019 } 1020 1021 if (MLX5_CAP_GEN(mdev, cd)) 1022 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1023 1024 if (mlx5_core_is_vf(mdev)) 1025 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1026 1027 if (mlx5_ib_port_link_layer(ibdev, 1) == 1028 IB_LINK_LAYER_ETHERNET && raw_support) { 1029 props->rss_caps.max_rwq_indirection_tables = 1030 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1031 props->rss_caps.max_rwq_indirection_table_size = 1032 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1033 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1034 props->max_wq_type_rq = 1035 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1036 } 1037 1038 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1039 props->tm_caps.max_num_tags = 1040 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1041 props->tm_caps.max_ops = 1042 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1043 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1044 } 1045 1046 if (MLX5_CAP_GEN(mdev, tag_matching) && 1047 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1048 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1049 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1050 } 1051 1052 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1053 props->cq_caps.max_cq_moderation_count = 1054 MLX5_MAX_CQ_COUNT; 1055 props->cq_caps.max_cq_moderation_period = 1056 MLX5_MAX_CQ_PERIOD; 1057 } 1058 1059 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1060 resp.response_length += sizeof(resp.cqe_comp_caps); 1061 1062 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1063 resp.cqe_comp_caps.max_num = 1064 MLX5_CAP_GEN(dev->mdev, 1065 cqe_compression_max_num); 1066 1067 resp.cqe_comp_caps.supported_format = 1068 MLX5_IB_CQE_RES_FORMAT_HASH | 1069 MLX5_IB_CQE_RES_FORMAT_CSUM; 1070 1071 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1072 resp.cqe_comp_caps.supported_format |= 1073 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1074 } 1075 } 1076 1077 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1078 raw_support) { 1079 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1080 MLX5_CAP_GEN(mdev, qos)) { 1081 resp.packet_pacing_caps.qp_rate_limit_max = 1082 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1083 resp.packet_pacing_caps.qp_rate_limit_min = 1084 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1085 resp.packet_pacing_caps.supported_qpts |= 1086 1 << IB_QPT_RAW_PACKET; 1087 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1088 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1089 resp.packet_pacing_caps.cap_flags |= 1090 MLX5_IB_PP_SUPPORT_BURST; 1091 } 1092 resp.response_length += sizeof(resp.packet_pacing_caps); 1093 } 1094 1095 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1096 uhw_outlen) { 1097 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1098 resp.mlx5_ib_support_multi_pkt_send_wqes = 1099 MLX5_IB_ALLOW_MPW; 1100 1101 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1102 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1103 MLX5_IB_SUPPORT_EMPW; 1104 1105 resp.response_length += 1106 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1107 } 1108 1109 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1110 resp.response_length += sizeof(resp.flags); 1111 1112 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1113 resp.flags |= 1114 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1115 1116 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1117 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1118 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1119 resp.flags |= 1120 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1121 1122 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1123 } 1124 1125 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1126 resp.response_length += sizeof(resp.sw_parsing_caps); 1127 if (MLX5_CAP_ETH(mdev, swp)) { 1128 resp.sw_parsing_caps.sw_parsing_offloads |= 1129 MLX5_IB_SW_PARSING; 1130 1131 if (MLX5_CAP_ETH(mdev, swp_csum)) 1132 resp.sw_parsing_caps.sw_parsing_offloads |= 1133 MLX5_IB_SW_PARSING_CSUM; 1134 1135 if (MLX5_CAP_ETH(mdev, swp_lso)) 1136 resp.sw_parsing_caps.sw_parsing_offloads |= 1137 MLX5_IB_SW_PARSING_LSO; 1138 1139 if (resp.sw_parsing_caps.sw_parsing_offloads) 1140 resp.sw_parsing_caps.supported_qpts = 1141 BIT(IB_QPT_RAW_PACKET); 1142 } 1143 } 1144 1145 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1146 raw_support) { 1147 resp.response_length += sizeof(resp.striding_rq_caps); 1148 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1149 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1150 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1151 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1152 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1153 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1154 resp.striding_rq_caps 1155 .min_single_wqe_log_num_of_strides = 1156 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1157 else 1158 resp.striding_rq_caps 1159 .min_single_wqe_log_num_of_strides = 1160 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1161 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1162 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1163 resp.striding_rq_caps.supported_qpts = 1164 BIT(IB_QPT_RAW_PACKET); 1165 } 1166 } 1167 1168 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1169 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1171 resp.tunnel_offloads_caps |= 1172 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1173 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1174 resp.tunnel_offloads_caps |= 1175 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1177 resp.tunnel_offloads_caps |= 1178 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1179 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1180 resp.tunnel_offloads_caps |= 1181 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1182 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1183 resp.tunnel_offloads_caps |= 1184 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1185 } 1186 1187 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1188 resp.response_length += sizeof(resp.dci_streams_caps); 1189 1190 resp.dci_streams_caps.max_log_num_concurent = 1191 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1192 1193 resp.dci_streams_caps.max_log_num_errored = 1194 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1195 } 1196 1197 if (uhw_outlen) { 1198 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1199 1200 if (err) 1201 return err; 1202 } 1203 1204 return 0; 1205 } 1206 1207 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1208 u8 *ib_width) 1209 { 1210 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1211 1212 if (active_width & MLX5_PTYS_WIDTH_1X) 1213 *ib_width = IB_WIDTH_1X; 1214 else if (active_width & MLX5_PTYS_WIDTH_2X) 1215 *ib_width = IB_WIDTH_2X; 1216 else if (active_width & MLX5_PTYS_WIDTH_4X) 1217 *ib_width = IB_WIDTH_4X; 1218 else if (active_width & MLX5_PTYS_WIDTH_8X) 1219 *ib_width = IB_WIDTH_8X; 1220 else if (active_width & MLX5_PTYS_WIDTH_12X) 1221 *ib_width = IB_WIDTH_12X; 1222 else { 1223 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1224 active_width); 1225 *ib_width = IB_WIDTH_4X; 1226 } 1227 1228 return; 1229 } 1230 1231 static int mlx5_mtu_to_ib_mtu(int mtu) 1232 { 1233 switch (mtu) { 1234 case 256: return 1; 1235 case 512: return 2; 1236 case 1024: return 3; 1237 case 2048: return 4; 1238 case 4096: return 5; 1239 default: 1240 pr_warn("invalid mtu\n"); 1241 return -1; 1242 } 1243 } 1244 1245 enum ib_max_vl_num { 1246 __IB_MAX_VL_0 = 1, 1247 __IB_MAX_VL_0_1 = 2, 1248 __IB_MAX_VL_0_3 = 3, 1249 __IB_MAX_VL_0_7 = 4, 1250 __IB_MAX_VL_0_14 = 5, 1251 }; 1252 1253 enum mlx5_vl_hw_cap { 1254 MLX5_VL_HW_0 = 1, 1255 MLX5_VL_HW_0_1 = 2, 1256 MLX5_VL_HW_0_2 = 3, 1257 MLX5_VL_HW_0_3 = 4, 1258 MLX5_VL_HW_0_4 = 5, 1259 MLX5_VL_HW_0_5 = 6, 1260 MLX5_VL_HW_0_6 = 7, 1261 MLX5_VL_HW_0_7 = 8, 1262 MLX5_VL_HW_0_14 = 15 1263 }; 1264 1265 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1266 u8 *max_vl_num) 1267 { 1268 switch (vl_hw_cap) { 1269 case MLX5_VL_HW_0: 1270 *max_vl_num = __IB_MAX_VL_0; 1271 break; 1272 case MLX5_VL_HW_0_1: 1273 *max_vl_num = __IB_MAX_VL_0_1; 1274 break; 1275 case MLX5_VL_HW_0_3: 1276 *max_vl_num = __IB_MAX_VL_0_3; 1277 break; 1278 case MLX5_VL_HW_0_7: 1279 *max_vl_num = __IB_MAX_VL_0_7; 1280 break; 1281 case MLX5_VL_HW_0_14: 1282 *max_vl_num = __IB_MAX_VL_0_14; 1283 break; 1284 1285 default: 1286 return -EINVAL; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1293 struct ib_port_attr *props) 1294 { 1295 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1296 struct mlx5_core_dev *mdev = dev->mdev; 1297 struct mlx5_hca_vport_context *rep; 1298 u16 max_mtu; 1299 u16 oper_mtu; 1300 int err; 1301 u16 ib_link_width_oper; 1302 u8 vl_hw_cap; 1303 1304 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1305 if (!rep) { 1306 err = -ENOMEM; 1307 goto out; 1308 } 1309 1310 /* props being zeroed by the caller, avoid zeroing it here */ 1311 1312 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1313 if (err) 1314 goto out; 1315 1316 props->lid = rep->lid; 1317 props->lmc = rep->lmc; 1318 props->sm_lid = rep->sm_lid; 1319 props->sm_sl = rep->sm_sl; 1320 props->state = rep->vport_state; 1321 props->phys_state = rep->port_physical_state; 1322 props->port_cap_flags = rep->cap_mask1; 1323 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1324 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1325 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1326 props->bad_pkey_cntr = rep->pkey_violation_counter; 1327 props->qkey_viol_cntr = rep->qkey_violation_counter; 1328 props->subnet_timeout = rep->subnet_timeout; 1329 props->init_type_reply = rep->init_type_reply; 1330 1331 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1332 props->port_cap_flags2 = rep->cap_mask2; 1333 1334 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1335 &props->active_speed, port); 1336 if (err) 1337 goto out; 1338 1339 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1340 1341 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1342 1343 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1344 1345 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1346 1347 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1348 1349 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1350 if (err) 1351 goto out; 1352 1353 err = translate_max_vl_num(ibdev, vl_hw_cap, 1354 &props->max_vl_num); 1355 out: 1356 kfree(rep); 1357 return err; 1358 } 1359 1360 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1361 struct ib_port_attr *props) 1362 { 1363 unsigned int count; 1364 int ret; 1365 1366 switch (mlx5_get_vport_access_method(ibdev)) { 1367 case MLX5_VPORT_ACCESS_METHOD_MAD: 1368 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1369 break; 1370 1371 case MLX5_VPORT_ACCESS_METHOD_HCA: 1372 ret = mlx5_query_hca_port(ibdev, port, props); 1373 break; 1374 1375 case MLX5_VPORT_ACCESS_METHOD_NIC: 1376 ret = mlx5_query_port_roce(ibdev, port, props); 1377 break; 1378 1379 default: 1380 ret = -EINVAL; 1381 } 1382 1383 if (!ret && props) { 1384 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1385 struct mlx5_core_dev *mdev; 1386 bool put_mdev = true; 1387 1388 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1389 if (!mdev) { 1390 /* If the port isn't affiliated yet query the master. 1391 * The master and slave will have the same values. 1392 */ 1393 mdev = dev->mdev; 1394 port = 1; 1395 put_mdev = false; 1396 } 1397 count = mlx5_core_reserved_gids_count(mdev); 1398 if (put_mdev) 1399 mlx5_ib_put_native_port_mdev(dev, port); 1400 props->gid_tbl_len -= count; 1401 } 1402 return ret; 1403 } 1404 1405 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1406 struct ib_port_attr *props) 1407 { 1408 return mlx5_query_port_roce(ibdev, port, props); 1409 } 1410 1411 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1412 u16 *pkey) 1413 { 1414 /* Default special Pkey for representor device port as per the 1415 * IB specification 1.3 section 10.9.1.2. 1416 */ 1417 *pkey = 0xffff; 1418 return 0; 1419 } 1420 1421 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1422 union ib_gid *gid) 1423 { 1424 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1425 struct mlx5_core_dev *mdev = dev->mdev; 1426 1427 switch (mlx5_get_vport_access_method(ibdev)) { 1428 case MLX5_VPORT_ACCESS_METHOD_MAD: 1429 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1430 1431 case MLX5_VPORT_ACCESS_METHOD_HCA: 1432 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1433 1434 default: 1435 return -EINVAL; 1436 } 1437 1438 } 1439 1440 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1441 u16 index, u16 *pkey) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct mlx5_core_dev *mdev; 1445 bool put_mdev = true; 1446 u32 mdev_port_num; 1447 int err; 1448 1449 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1450 if (!mdev) { 1451 /* The port isn't affiliated yet, get the PKey from the master 1452 * port. For RoCE the PKey tables will be the same. 1453 */ 1454 put_mdev = false; 1455 mdev = dev->mdev; 1456 mdev_port_num = 1; 1457 } 1458 1459 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1460 index, pkey); 1461 if (put_mdev) 1462 mlx5_ib_put_native_port_mdev(dev, port); 1463 1464 return err; 1465 } 1466 1467 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1468 u16 *pkey) 1469 { 1470 switch (mlx5_get_vport_access_method(ibdev)) { 1471 case MLX5_VPORT_ACCESS_METHOD_MAD: 1472 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1473 1474 case MLX5_VPORT_ACCESS_METHOD_HCA: 1475 case MLX5_VPORT_ACCESS_METHOD_NIC: 1476 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1477 default: 1478 return -EINVAL; 1479 } 1480 } 1481 1482 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1483 struct ib_device_modify *props) 1484 { 1485 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1486 struct mlx5_reg_node_desc in; 1487 struct mlx5_reg_node_desc out; 1488 int err; 1489 1490 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1491 return -EOPNOTSUPP; 1492 1493 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1494 return 0; 1495 1496 /* 1497 * If possible, pass node desc to FW, so it can generate 1498 * a 144 trap. If cmd fails, just ignore. 1499 */ 1500 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1501 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1502 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1503 if (err) 1504 return err; 1505 1506 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1507 1508 return err; 1509 } 1510 1511 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1512 u32 value) 1513 { 1514 struct mlx5_hca_vport_context ctx = {}; 1515 struct mlx5_core_dev *mdev; 1516 u32 mdev_port_num; 1517 int err; 1518 1519 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1520 if (!mdev) 1521 return -ENODEV; 1522 1523 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1524 if (err) 1525 goto out; 1526 1527 if (~ctx.cap_mask1_perm & mask) { 1528 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1529 mask, ctx.cap_mask1_perm); 1530 err = -EINVAL; 1531 goto out; 1532 } 1533 1534 ctx.cap_mask1 = value; 1535 ctx.cap_mask1_perm = mask; 1536 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1537 0, &ctx); 1538 1539 out: 1540 mlx5_ib_put_native_port_mdev(dev, port_num); 1541 1542 return err; 1543 } 1544 1545 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1546 struct ib_port_modify *props) 1547 { 1548 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1549 struct ib_port_attr attr; 1550 u32 tmp; 1551 int err; 1552 u32 change_mask; 1553 u32 value; 1554 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1555 IB_LINK_LAYER_INFINIBAND); 1556 1557 /* CM layer calls ib_modify_port() regardless of the link layer. For 1558 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1559 */ 1560 if (!is_ib) 1561 return 0; 1562 1563 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1564 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1565 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1566 return set_port_caps_atomic(dev, port, change_mask, value); 1567 } 1568 1569 mutex_lock(&dev->cap_mask_mutex); 1570 1571 err = ib_query_port(ibdev, port, &attr); 1572 if (err) 1573 goto out; 1574 1575 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1576 ~props->clr_port_cap_mask; 1577 1578 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1579 1580 out: 1581 mutex_unlock(&dev->cap_mask_mutex); 1582 return err; 1583 } 1584 1585 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1586 { 1587 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1588 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1589 } 1590 1591 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1592 { 1593 /* Large page with non 4k uar support might limit the dynamic size */ 1594 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1595 return MLX5_MIN_DYN_BFREGS; 1596 1597 return MLX5_MAX_DYN_BFREGS; 1598 } 1599 1600 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1601 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1602 struct mlx5_bfreg_info *bfregi) 1603 { 1604 int uars_per_sys_page; 1605 int bfregs_per_sys_page; 1606 int ref_bfregs = req->total_num_bfregs; 1607 1608 if (req->total_num_bfregs == 0) 1609 return -EINVAL; 1610 1611 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1612 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1613 1614 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1615 return -ENOMEM; 1616 1617 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1618 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1619 /* This holds the required static allocation asked by the user */ 1620 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1621 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1622 return -EINVAL; 1623 1624 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1625 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1626 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1627 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1628 1629 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1630 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1631 lib_uar_4k ? "yes" : "no", ref_bfregs, 1632 req->total_num_bfregs, bfregi->total_num_bfregs, 1633 bfregi->num_sys_pages); 1634 1635 return 0; 1636 } 1637 1638 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1639 { 1640 struct mlx5_bfreg_info *bfregi; 1641 int err; 1642 int i; 1643 1644 bfregi = &context->bfregi; 1645 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1646 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1647 context->devx_uid); 1648 if (err) 1649 goto error; 1650 1651 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1652 } 1653 1654 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1655 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1656 1657 return 0; 1658 1659 error: 1660 for (--i; i >= 0; i--) 1661 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1662 context->devx_uid)) 1663 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1664 1665 return err; 1666 } 1667 1668 static void deallocate_uars(struct mlx5_ib_dev *dev, 1669 struct mlx5_ib_ucontext *context) 1670 { 1671 struct mlx5_bfreg_info *bfregi; 1672 int i; 1673 1674 bfregi = &context->bfregi; 1675 for (i = 0; i < bfregi->num_sys_pages; i++) 1676 if (i < bfregi->num_static_sys_pages || 1677 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1678 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1679 context->devx_uid); 1680 } 1681 1682 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1683 { 1684 int err = 0; 1685 1686 mutex_lock(&dev->lb.mutex); 1687 if (td) 1688 dev->lb.user_td++; 1689 if (qp) 1690 dev->lb.qps++; 1691 1692 if (dev->lb.user_td == 2 || 1693 dev->lb.qps == 1) { 1694 if (!dev->lb.enabled) { 1695 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1696 dev->lb.enabled = true; 1697 } 1698 } 1699 1700 mutex_unlock(&dev->lb.mutex); 1701 1702 return err; 1703 } 1704 1705 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1706 { 1707 mutex_lock(&dev->lb.mutex); 1708 if (td) 1709 dev->lb.user_td--; 1710 if (qp) 1711 dev->lb.qps--; 1712 1713 if (dev->lb.user_td == 1 && 1714 dev->lb.qps == 0) { 1715 if (dev->lb.enabled) { 1716 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1717 dev->lb.enabled = false; 1718 } 1719 } 1720 1721 mutex_unlock(&dev->lb.mutex); 1722 } 1723 1724 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1725 u16 uid) 1726 { 1727 int err; 1728 1729 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1730 return 0; 1731 1732 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1733 if (err) 1734 return err; 1735 1736 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1737 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1738 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1739 return err; 1740 1741 return mlx5_ib_enable_lb(dev, true, false); 1742 } 1743 1744 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1745 u16 uid) 1746 { 1747 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1748 return; 1749 1750 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1751 1752 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1753 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1754 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1755 return; 1756 1757 mlx5_ib_disable_lb(dev, true, false); 1758 } 1759 1760 static int set_ucontext_resp(struct ib_ucontext *uctx, 1761 struct mlx5_ib_alloc_ucontext_resp *resp) 1762 { 1763 struct ib_device *ibdev = uctx->device; 1764 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1765 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1766 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1767 int err; 1768 1769 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1770 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1771 &resp->dump_fill_mkey); 1772 if (err) 1773 return err; 1774 resp->comp_mask |= 1775 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1776 } 1777 1778 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1779 if (dev->wc_support) 1780 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1781 log_bf_reg_size); 1782 resp->cache_line_size = cache_line_size(); 1783 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1784 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1785 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1786 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1787 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1788 resp->cqe_version = context->cqe_version; 1789 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1790 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1791 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1792 MLX5_CAP_GEN(dev->mdev, 1793 num_of_uars_per_page) : 1; 1794 1795 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1796 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1797 if (mlx5_get_flow_namespace(dev->mdev, 1798 MLX5_FLOW_NAMESPACE_EGRESS)) 1799 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1800 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1801 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1802 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1803 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1804 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1805 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1806 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1807 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1808 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1809 } 1810 1811 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1812 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1813 resp->num_ports = dev->num_ports; 1814 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1815 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1816 1817 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1818 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1819 resp->eth_min_inline++; 1820 } 1821 1822 if (dev->mdev->clock_info) 1823 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1824 1825 /* 1826 * We don't want to expose information from the PCI bar that is located 1827 * after 4096 bytes, so if the arch only supports larger pages, let's 1828 * pretend we don't support reading the HCA's core clock. This is also 1829 * forced by mmap function. 1830 */ 1831 if (PAGE_SIZE <= 4096) { 1832 resp->comp_mask |= 1833 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1834 resp->hca_core_clock_offset = 1835 offsetof(struct mlx5_init_seg, 1836 internal_timer_h) % PAGE_SIZE; 1837 } 1838 1839 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1840 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1841 1842 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1843 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1844 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1845 resp->comp_mask |= 1846 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1847 1848 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1849 1850 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1851 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1852 1853 return 0; 1854 } 1855 1856 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1857 struct ib_udata *udata) 1858 { 1859 struct ib_device *ibdev = uctx->device; 1860 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1861 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1862 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1863 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1864 struct mlx5_bfreg_info *bfregi; 1865 int ver; 1866 int err; 1867 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1868 max_cqe_version); 1869 bool lib_uar_4k; 1870 bool lib_uar_dyn; 1871 1872 if (!dev->ib_active) 1873 return -EAGAIN; 1874 1875 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1876 ver = 0; 1877 else if (udata->inlen >= min_req_v2) 1878 ver = 2; 1879 else 1880 return -EINVAL; 1881 1882 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1883 if (err) 1884 return err; 1885 1886 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1887 return -EOPNOTSUPP; 1888 1889 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1890 return -EOPNOTSUPP; 1891 1892 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1893 MLX5_NON_FP_BFREGS_PER_UAR); 1894 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1895 return -EINVAL; 1896 1897 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1898 err = mlx5_ib_devx_create(dev, true); 1899 if (err < 0) 1900 goto out_ctx; 1901 context->devx_uid = err; 1902 } 1903 1904 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1905 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1906 bfregi = &context->bfregi; 1907 1908 if (lib_uar_dyn) { 1909 bfregi->lib_uar_dyn = lib_uar_dyn; 1910 goto uar_done; 1911 } 1912 1913 /* updates req->total_num_bfregs */ 1914 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1915 if (err) 1916 goto out_devx; 1917 1918 mutex_init(&bfregi->lock); 1919 bfregi->lib_uar_4k = lib_uar_4k; 1920 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1921 GFP_KERNEL); 1922 if (!bfregi->count) { 1923 err = -ENOMEM; 1924 goto out_devx; 1925 } 1926 1927 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1928 sizeof(*bfregi->sys_pages), 1929 GFP_KERNEL); 1930 if (!bfregi->sys_pages) { 1931 err = -ENOMEM; 1932 goto out_count; 1933 } 1934 1935 err = allocate_uars(dev, context); 1936 if (err) 1937 goto out_sys_pages; 1938 1939 uar_done: 1940 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1941 context->devx_uid); 1942 if (err) 1943 goto out_uars; 1944 1945 INIT_LIST_HEAD(&context->db_page_list); 1946 mutex_init(&context->db_page_mutex); 1947 1948 context->cqe_version = min_t(__u8, 1949 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1950 req.max_cqe_version); 1951 1952 err = set_ucontext_resp(uctx, &resp); 1953 if (err) 1954 goto out_mdev; 1955 1956 resp.response_length = min(udata->outlen, sizeof(resp)); 1957 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1958 if (err) 1959 goto out_mdev; 1960 1961 bfregi->ver = ver; 1962 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1963 context->lib_caps = req.lib_caps; 1964 print_lib_caps(dev, context->lib_caps); 1965 1966 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1967 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1968 1969 atomic_set(&context->tx_port_affinity, 1970 atomic_add_return( 1971 1, &dev->port[port].roce.tx_port_affinity)); 1972 } 1973 1974 return 0; 1975 1976 out_mdev: 1977 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1978 1979 out_uars: 1980 deallocate_uars(dev, context); 1981 1982 out_sys_pages: 1983 kfree(bfregi->sys_pages); 1984 1985 out_count: 1986 kfree(bfregi->count); 1987 1988 out_devx: 1989 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1990 mlx5_ib_devx_destroy(dev, context->devx_uid); 1991 1992 out_ctx: 1993 return err; 1994 } 1995 1996 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1997 struct uverbs_attr_bundle *attrs) 1998 { 1999 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2000 int ret; 2001 2002 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2003 if (ret) 2004 return ret; 2005 2006 uctx_resp.response_length = 2007 min_t(size_t, 2008 uverbs_attr_get_len(attrs, 2009 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2010 sizeof(uctx_resp)); 2011 2012 ret = uverbs_copy_to_struct_or_zero(attrs, 2013 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2014 &uctx_resp, 2015 sizeof(uctx_resp)); 2016 return ret; 2017 } 2018 2019 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2020 { 2021 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2022 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2023 struct mlx5_bfreg_info *bfregi; 2024 2025 bfregi = &context->bfregi; 2026 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2027 2028 deallocate_uars(dev, context); 2029 kfree(bfregi->sys_pages); 2030 kfree(bfregi->count); 2031 2032 if (context->devx_uid) 2033 mlx5_ib_devx_destroy(dev, context->devx_uid); 2034 } 2035 2036 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2037 int uar_idx) 2038 { 2039 int fw_uars_per_page; 2040 2041 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2042 2043 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2044 } 2045 2046 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2047 int uar_idx) 2048 { 2049 unsigned int fw_uars_per_page; 2050 2051 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2052 MLX5_UARS_IN_PAGE : 1; 2053 2054 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2055 } 2056 2057 static int get_command(unsigned long offset) 2058 { 2059 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2060 } 2061 2062 static int get_arg(unsigned long offset) 2063 { 2064 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2065 } 2066 2067 static int get_index(unsigned long offset) 2068 { 2069 return get_arg(offset); 2070 } 2071 2072 /* Index resides in an extra byte to enable larger values than 255 */ 2073 static int get_extended_index(unsigned long offset) 2074 { 2075 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2076 } 2077 2078 2079 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2080 { 2081 } 2082 2083 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2084 { 2085 switch (cmd) { 2086 case MLX5_IB_MMAP_WC_PAGE: 2087 return "WC"; 2088 case MLX5_IB_MMAP_REGULAR_PAGE: 2089 return "best effort WC"; 2090 case MLX5_IB_MMAP_NC_PAGE: 2091 return "NC"; 2092 case MLX5_IB_MMAP_DEVICE_MEM: 2093 return "Device Memory"; 2094 default: 2095 return NULL; 2096 } 2097 } 2098 2099 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2100 struct vm_area_struct *vma, 2101 struct mlx5_ib_ucontext *context) 2102 { 2103 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2104 !(vma->vm_flags & VM_SHARED)) 2105 return -EINVAL; 2106 2107 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2108 return -EOPNOTSUPP; 2109 2110 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2111 return -EPERM; 2112 vma->vm_flags &= ~VM_MAYWRITE; 2113 2114 if (!dev->mdev->clock_info) 2115 return -EOPNOTSUPP; 2116 2117 return vm_insert_page(vma, vma->vm_start, 2118 virt_to_page(dev->mdev->clock_info)); 2119 } 2120 2121 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2122 { 2123 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2124 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2125 struct mlx5_var_table *var_table = &dev->var_table; 2126 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2127 2128 switch (mentry->mmap_flag) { 2129 case MLX5_IB_MMAP_TYPE_MEMIC: 2130 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2131 mlx5_ib_dm_mmap_free(dev, mentry); 2132 break; 2133 case MLX5_IB_MMAP_TYPE_VAR: 2134 mutex_lock(&var_table->bitmap_lock); 2135 clear_bit(mentry->page_idx, var_table->bitmap); 2136 mutex_unlock(&var_table->bitmap_lock); 2137 kfree(mentry); 2138 break; 2139 case MLX5_IB_MMAP_TYPE_UAR_WC: 2140 case MLX5_IB_MMAP_TYPE_UAR_NC: 2141 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2142 context->devx_uid); 2143 kfree(mentry); 2144 break; 2145 default: 2146 WARN_ON(true); 2147 } 2148 } 2149 2150 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2151 struct vm_area_struct *vma, 2152 struct mlx5_ib_ucontext *context) 2153 { 2154 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2155 int err; 2156 unsigned long idx; 2157 phys_addr_t pfn; 2158 pgprot_t prot; 2159 u32 bfreg_dyn_idx = 0; 2160 u32 uar_index; 2161 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2162 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2163 bfregi->num_static_sys_pages; 2164 2165 if (bfregi->lib_uar_dyn) 2166 return -EINVAL; 2167 2168 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2169 return -EINVAL; 2170 2171 if (dyn_uar) 2172 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2173 else 2174 idx = get_index(vma->vm_pgoff); 2175 2176 if (idx >= max_valid_idx) { 2177 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2178 idx, max_valid_idx); 2179 return -EINVAL; 2180 } 2181 2182 switch (cmd) { 2183 case MLX5_IB_MMAP_WC_PAGE: 2184 case MLX5_IB_MMAP_ALLOC_WC: 2185 case MLX5_IB_MMAP_REGULAR_PAGE: 2186 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2187 prot = pgprot_writecombine(vma->vm_page_prot); 2188 break; 2189 case MLX5_IB_MMAP_NC_PAGE: 2190 prot = pgprot_noncached(vma->vm_page_prot); 2191 break; 2192 default: 2193 return -EINVAL; 2194 } 2195 2196 if (dyn_uar) { 2197 int uars_per_page; 2198 2199 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2200 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2201 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2202 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2203 bfreg_dyn_idx, bfregi->total_num_bfregs); 2204 return -EINVAL; 2205 } 2206 2207 mutex_lock(&bfregi->lock); 2208 /* Fail if uar already allocated, first bfreg index of each 2209 * page holds its count. 2210 */ 2211 if (bfregi->count[bfreg_dyn_idx]) { 2212 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2213 mutex_unlock(&bfregi->lock); 2214 return -EINVAL; 2215 } 2216 2217 bfregi->count[bfreg_dyn_idx]++; 2218 mutex_unlock(&bfregi->lock); 2219 2220 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2221 context->devx_uid); 2222 if (err) { 2223 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2224 goto free_bfreg; 2225 } 2226 } else { 2227 uar_index = bfregi->sys_pages[idx]; 2228 } 2229 2230 pfn = uar_index2pfn(dev, uar_index); 2231 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2232 2233 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2234 prot, NULL); 2235 if (err) { 2236 mlx5_ib_err(dev, 2237 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2238 err, mmap_cmd2str(cmd)); 2239 goto err; 2240 } 2241 2242 if (dyn_uar) 2243 bfregi->sys_pages[idx] = uar_index; 2244 return 0; 2245 2246 err: 2247 if (!dyn_uar) 2248 return err; 2249 2250 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2251 2252 free_bfreg: 2253 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2254 2255 return err; 2256 } 2257 2258 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2259 { 2260 unsigned long idx; 2261 u8 command; 2262 2263 command = get_command(vma->vm_pgoff); 2264 idx = get_extended_index(vma->vm_pgoff); 2265 2266 return (command << 16 | idx); 2267 } 2268 2269 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2270 struct vm_area_struct *vma, 2271 struct ib_ucontext *ucontext) 2272 { 2273 struct mlx5_user_mmap_entry *mentry; 2274 struct rdma_user_mmap_entry *entry; 2275 unsigned long pgoff; 2276 pgprot_t prot; 2277 phys_addr_t pfn; 2278 int ret; 2279 2280 pgoff = mlx5_vma_to_pgoff(vma); 2281 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2282 if (!entry) 2283 return -EINVAL; 2284 2285 mentry = to_mmmap(entry); 2286 pfn = (mentry->address >> PAGE_SHIFT); 2287 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2288 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2289 prot = pgprot_noncached(vma->vm_page_prot); 2290 else 2291 prot = pgprot_writecombine(vma->vm_page_prot); 2292 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2293 entry->npages * PAGE_SIZE, 2294 prot, 2295 entry); 2296 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2297 return ret; 2298 } 2299 2300 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2301 { 2302 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2303 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2304 2305 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2306 (index & 0xFF)) << PAGE_SHIFT; 2307 } 2308 2309 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2310 { 2311 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2312 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2313 unsigned long command; 2314 phys_addr_t pfn; 2315 2316 command = get_command(vma->vm_pgoff); 2317 switch (command) { 2318 case MLX5_IB_MMAP_WC_PAGE: 2319 case MLX5_IB_MMAP_ALLOC_WC: 2320 if (!dev->wc_support) 2321 return -EPERM; 2322 fallthrough; 2323 case MLX5_IB_MMAP_NC_PAGE: 2324 case MLX5_IB_MMAP_REGULAR_PAGE: 2325 return uar_mmap(dev, command, vma, context); 2326 2327 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2328 return -ENOSYS; 2329 2330 case MLX5_IB_MMAP_CORE_CLOCK: 2331 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2332 return -EINVAL; 2333 2334 if (vma->vm_flags & VM_WRITE) 2335 return -EPERM; 2336 vma->vm_flags &= ~VM_MAYWRITE; 2337 2338 /* Don't expose to user-space information it shouldn't have */ 2339 if (PAGE_SIZE > 4096) 2340 return -EOPNOTSUPP; 2341 2342 pfn = (dev->mdev->iseg_base + 2343 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2344 PAGE_SHIFT; 2345 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2346 PAGE_SIZE, 2347 pgprot_noncached(vma->vm_page_prot), 2348 NULL); 2349 case MLX5_IB_MMAP_CLOCK_INFO: 2350 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2351 2352 default: 2353 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2360 { 2361 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2362 struct ib_device *ibdev = ibpd->device; 2363 struct mlx5_ib_alloc_pd_resp resp; 2364 int err; 2365 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2366 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2367 u16 uid = 0; 2368 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2369 udata, struct mlx5_ib_ucontext, ibucontext); 2370 2371 uid = context ? context->devx_uid : 0; 2372 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2373 MLX5_SET(alloc_pd_in, in, uid, uid); 2374 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2375 if (err) 2376 return err; 2377 2378 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2379 pd->uid = uid; 2380 if (udata) { 2381 resp.pdn = pd->pdn; 2382 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2383 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2384 return -EFAULT; 2385 } 2386 } 2387 2388 return 0; 2389 } 2390 2391 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2392 { 2393 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2394 struct mlx5_ib_pd *mpd = to_mpd(pd); 2395 2396 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2397 } 2398 2399 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2400 { 2401 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2402 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2403 int err; 2404 u16 uid; 2405 2406 uid = ibqp->pd ? 2407 to_mpd(ibqp->pd)->uid : 0; 2408 2409 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2410 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2411 return -EOPNOTSUPP; 2412 } 2413 2414 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2415 if (err) 2416 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2417 ibqp->qp_num, gid->raw); 2418 2419 return err; 2420 } 2421 2422 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2423 { 2424 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2425 int err; 2426 u16 uid; 2427 2428 uid = ibqp->pd ? 2429 to_mpd(ibqp->pd)->uid : 0; 2430 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2431 if (err) 2432 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2433 ibqp->qp_num, gid->raw); 2434 2435 return err; 2436 } 2437 2438 static int init_node_data(struct mlx5_ib_dev *dev) 2439 { 2440 int err; 2441 2442 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2443 if (err) 2444 return err; 2445 2446 dev->mdev->rev_id = dev->mdev->pdev->revision; 2447 2448 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2449 } 2450 2451 static ssize_t fw_pages_show(struct device *device, 2452 struct device_attribute *attr, char *buf) 2453 { 2454 struct mlx5_ib_dev *dev = 2455 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2456 2457 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2458 } 2459 static DEVICE_ATTR_RO(fw_pages); 2460 2461 static ssize_t reg_pages_show(struct device *device, 2462 struct device_attribute *attr, char *buf) 2463 { 2464 struct mlx5_ib_dev *dev = 2465 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2466 2467 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2468 } 2469 static DEVICE_ATTR_RO(reg_pages); 2470 2471 static ssize_t hca_type_show(struct device *device, 2472 struct device_attribute *attr, char *buf) 2473 { 2474 struct mlx5_ib_dev *dev = 2475 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2476 2477 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2478 } 2479 static DEVICE_ATTR_RO(hca_type); 2480 2481 static ssize_t hw_rev_show(struct device *device, 2482 struct device_attribute *attr, char *buf) 2483 { 2484 struct mlx5_ib_dev *dev = 2485 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2486 2487 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2488 } 2489 static DEVICE_ATTR_RO(hw_rev); 2490 2491 static ssize_t board_id_show(struct device *device, 2492 struct device_attribute *attr, char *buf) 2493 { 2494 struct mlx5_ib_dev *dev = 2495 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2496 2497 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2498 dev->mdev->board_id); 2499 } 2500 static DEVICE_ATTR_RO(board_id); 2501 2502 static struct attribute *mlx5_class_attributes[] = { 2503 &dev_attr_hw_rev.attr, 2504 &dev_attr_hca_type.attr, 2505 &dev_attr_board_id.attr, 2506 &dev_attr_fw_pages.attr, 2507 &dev_attr_reg_pages.attr, 2508 NULL, 2509 }; 2510 2511 static const struct attribute_group mlx5_attr_group = { 2512 .attrs = mlx5_class_attributes, 2513 }; 2514 2515 static void pkey_change_handler(struct work_struct *work) 2516 { 2517 struct mlx5_ib_port_resources *ports = 2518 container_of(work, struct mlx5_ib_port_resources, 2519 pkey_change_work); 2520 2521 if (!ports->gsi) 2522 /* 2523 * We got this event before device was fully configured 2524 * and MAD registration code wasn't called/finished yet. 2525 */ 2526 return; 2527 2528 mlx5_ib_gsi_pkey_change(ports->gsi); 2529 } 2530 2531 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2532 { 2533 struct mlx5_ib_qp *mqp; 2534 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2535 struct mlx5_core_cq *mcq; 2536 struct list_head cq_armed_list; 2537 unsigned long flags_qp; 2538 unsigned long flags_cq; 2539 unsigned long flags; 2540 2541 INIT_LIST_HEAD(&cq_armed_list); 2542 2543 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2544 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2545 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2546 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2547 if (mqp->sq.tail != mqp->sq.head) { 2548 send_mcq = to_mcq(mqp->ibqp.send_cq); 2549 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2550 if (send_mcq->mcq.comp && 2551 mqp->ibqp.send_cq->comp_handler) { 2552 if (!send_mcq->mcq.reset_notify_added) { 2553 send_mcq->mcq.reset_notify_added = 1; 2554 list_add_tail(&send_mcq->mcq.reset_notify, 2555 &cq_armed_list); 2556 } 2557 } 2558 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2559 } 2560 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2561 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2562 /* no handling is needed for SRQ */ 2563 if (!mqp->ibqp.srq) { 2564 if (mqp->rq.tail != mqp->rq.head) { 2565 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2566 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2567 if (recv_mcq->mcq.comp && 2568 mqp->ibqp.recv_cq->comp_handler) { 2569 if (!recv_mcq->mcq.reset_notify_added) { 2570 recv_mcq->mcq.reset_notify_added = 1; 2571 list_add_tail(&recv_mcq->mcq.reset_notify, 2572 &cq_armed_list); 2573 } 2574 } 2575 spin_unlock_irqrestore(&recv_mcq->lock, 2576 flags_cq); 2577 } 2578 } 2579 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2580 } 2581 /*At that point all inflight post send were put to be executed as of we 2582 * lock/unlock above locks Now need to arm all involved CQs. 2583 */ 2584 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2585 mcq->comp(mcq, NULL); 2586 } 2587 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2588 } 2589 2590 static void delay_drop_handler(struct work_struct *work) 2591 { 2592 int err; 2593 struct mlx5_ib_delay_drop *delay_drop = 2594 container_of(work, struct mlx5_ib_delay_drop, 2595 delay_drop_work); 2596 2597 atomic_inc(&delay_drop->events_cnt); 2598 2599 mutex_lock(&delay_drop->lock); 2600 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2601 if (err) { 2602 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2603 delay_drop->timeout); 2604 delay_drop->activate = false; 2605 } 2606 mutex_unlock(&delay_drop->lock); 2607 } 2608 2609 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2610 struct ib_event *ibev) 2611 { 2612 u32 port = (eqe->data.port.port >> 4) & 0xf; 2613 2614 switch (eqe->sub_type) { 2615 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2616 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2617 IB_LINK_LAYER_ETHERNET) 2618 schedule_work(&ibdev->delay_drop.delay_drop_work); 2619 break; 2620 default: /* do nothing */ 2621 return; 2622 } 2623 } 2624 2625 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2626 struct ib_event *ibev) 2627 { 2628 u32 port = (eqe->data.port.port >> 4) & 0xf; 2629 2630 ibev->element.port_num = port; 2631 2632 switch (eqe->sub_type) { 2633 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2634 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2635 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2636 /* In RoCE, port up/down events are handled in 2637 * mlx5_netdev_event(). 2638 */ 2639 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2640 IB_LINK_LAYER_ETHERNET) 2641 return -EINVAL; 2642 2643 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2644 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2645 break; 2646 2647 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2648 ibev->event = IB_EVENT_LID_CHANGE; 2649 break; 2650 2651 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2652 ibev->event = IB_EVENT_PKEY_CHANGE; 2653 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2654 break; 2655 2656 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2657 ibev->event = IB_EVENT_GID_CHANGE; 2658 break; 2659 2660 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2661 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2662 break; 2663 default: 2664 return -EINVAL; 2665 } 2666 2667 return 0; 2668 } 2669 2670 static void mlx5_ib_handle_event(struct work_struct *_work) 2671 { 2672 struct mlx5_ib_event_work *work = 2673 container_of(_work, struct mlx5_ib_event_work, work); 2674 struct mlx5_ib_dev *ibdev; 2675 struct ib_event ibev; 2676 bool fatal = false; 2677 2678 if (work->is_slave) { 2679 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2680 if (!ibdev) 2681 goto out; 2682 } else { 2683 ibdev = work->dev; 2684 } 2685 2686 switch (work->event) { 2687 case MLX5_DEV_EVENT_SYS_ERROR: 2688 ibev.event = IB_EVENT_DEVICE_FATAL; 2689 mlx5_ib_handle_internal_error(ibdev); 2690 ibev.element.port_num = (u8)(unsigned long)work->param; 2691 fatal = true; 2692 break; 2693 case MLX5_EVENT_TYPE_PORT_CHANGE: 2694 if (handle_port_change(ibdev, work->param, &ibev)) 2695 goto out; 2696 break; 2697 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2698 handle_general_event(ibdev, work->param, &ibev); 2699 fallthrough; 2700 default: 2701 goto out; 2702 } 2703 2704 ibev.device = &ibdev->ib_dev; 2705 2706 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2707 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2708 goto out; 2709 } 2710 2711 if (ibdev->ib_active) 2712 ib_dispatch_event(&ibev); 2713 2714 if (fatal) 2715 ibdev->ib_active = false; 2716 out: 2717 kfree(work); 2718 } 2719 2720 static int mlx5_ib_event(struct notifier_block *nb, 2721 unsigned long event, void *param) 2722 { 2723 struct mlx5_ib_event_work *work; 2724 2725 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2726 if (!work) 2727 return NOTIFY_DONE; 2728 2729 INIT_WORK(&work->work, mlx5_ib_handle_event); 2730 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2731 work->is_slave = false; 2732 work->param = param; 2733 work->event = event; 2734 2735 queue_work(mlx5_ib_event_wq, &work->work); 2736 2737 return NOTIFY_OK; 2738 } 2739 2740 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2741 unsigned long event, void *param) 2742 { 2743 struct mlx5_ib_event_work *work; 2744 2745 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2746 if (!work) 2747 return NOTIFY_DONE; 2748 2749 INIT_WORK(&work->work, mlx5_ib_handle_event); 2750 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2751 work->is_slave = true; 2752 work->param = param; 2753 work->event = event; 2754 queue_work(mlx5_ib_event_wq, &work->work); 2755 2756 return NOTIFY_OK; 2757 } 2758 2759 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2760 { 2761 struct mlx5_hca_vport_context vport_ctx; 2762 int err; 2763 int port; 2764 2765 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2766 dev->port_caps[port - 1].has_smi = false; 2767 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2768 MLX5_CAP_PORT_TYPE_IB) { 2769 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2770 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2771 port, 0, 2772 &vport_ctx); 2773 if (err) { 2774 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2775 port, err); 2776 return err; 2777 } 2778 dev->port_caps[port - 1].has_smi = 2779 vport_ctx.has_smi; 2780 } else { 2781 dev->port_caps[port - 1].has_smi = true; 2782 } 2783 } 2784 } 2785 return 0; 2786 } 2787 2788 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2789 { 2790 unsigned int port; 2791 2792 rdma_for_each_port (&dev->ib_dev, port) 2793 mlx5_query_ext_port_caps(dev, port); 2794 } 2795 2796 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2797 { 2798 switch (umr_fence_cap) { 2799 case MLX5_CAP_UMR_FENCE_NONE: 2800 return MLX5_FENCE_MODE_NONE; 2801 case MLX5_CAP_UMR_FENCE_SMALL: 2802 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2803 default: 2804 return MLX5_FENCE_MODE_STRONG_ORDERING; 2805 } 2806 } 2807 2808 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2809 { 2810 struct mlx5_ib_resources *devr = &dev->devr; 2811 struct ib_srq_init_attr attr; 2812 struct ib_device *ibdev; 2813 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2814 int port; 2815 int ret = 0; 2816 2817 ibdev = &dev->ib_dev; 2818 2819 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2820 return -EOPNOTSUPP; 2821 2822 devr->p0 = ib_alloc_pd(ibdev, 0); 2823 if (IS_ERR(devr->p0)) 2824 return PTR_ERR(devr->p0); 2825 2826 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2827 if (IS_ERR(devr->c0)) { 2828 ret = PTR_ERR(devr->c0); 2829 goto error1; 2830 } 2831 2832 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2833 if (ret) 2834 goto error2; 2835 2836 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2837 if (ret) 2838 goto error3; 2839 2840 memset(&attr, 0, sizeof(attr)); 2841 attr.attr.max_sge = 1; 2842 attr.attr.max_wr = 1; 2843 attr.srq_type = IB_SRQT_XRC; 2844 attr.ext.cq = devr->c0; 2845 2846 devr->s0 = ib_create_srq(devr->p0, &attr); 2847 if (IS_ERR(devr->s0)) { 2848 ret = PTR_ERR(devr->s0); 2849 goto err_create; 2850 } 2851 2852 memset(&attr, 0, sizeof(attr)); 2853 attr.attr.max_sge = 1; 2854 attr.attr.max_wr = 1; 2855 attr.srq_type = IB_SRQT_BASIC; 2856 2857 devr->s1 = ib_create_srq(devr->p0, &attr); 2858 if (IS_ERR(devr->s1)) { 2859 ret = PTR_ERR(devr->s1); 2860 goto error6; 2861 } 2862 2863 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2864 INIT_WORK(&devr->ports[port].pkey_change_work, 2865 pkey_change_handler); 2866 2867 return 0; 2868 2869 error6: 2870 ib_destroy_srq(devr->s0); 2871 err_create: 2872 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2873 error3: 2874 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2875 error2: 2876 ib_destroy_cq(devr->c0); 2877 error1: 2878 ib_dealloc_pd(devr->p0); 2879 return ret; 2880 } 2881 2882 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2883 { 2884 struct mlx5_ib_resources *devr = &dev->devr; 2885 int port; 2886 2887 /* 2888 * Make sure no change P_Key work items are still executing. 2889 * 2890 * At this stage, the mlx5_ib_event should be unregistered 2891 * and it ensures that no new works are added. 2892 */ 2893 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2894 cancel_work_sync(&devr->ports[port].pkey_change_work); 2895 2896 ib_destroy_srq(devr->s1); 2897 ib_destroy_srq(devr->s0); 2898 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2899 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2900 ib_destroy_cq(devr->c0); 2901 ib_dealloc_pd(devr->p0); 2902 } 2903 2904 static u32 get_core_cap_flags(struct ib_device *ibdev, 2905 struct mlx5_hca_vport_context *rep) 2906 { 2907 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2908 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2909 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2910 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2911 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2912 u32 ret = 0; 2913 2914 if (rep->grh_required) 2915 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2916 2917 if (ll == IB_LINK_LAYER_INFINIBAND) 2918 return ret | RDMA_CORE_PORT_IBA_IB; 2919 2920 if (raw_support) 2921 ret |= RDMA_CORE_PORT_RAW_PACKET; 2922 2923 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2924 return ret; 2925 2926 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2927 return ret; 2928 2929 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2930 ret |= RDMA_CORE_PORT_IBA_ROCE; 2931 2932 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2933 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2934 2935 return ret; 2936 } 2937 2938 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2939 struct ib_port_immutable *immutable) 2940 { 2941 struct ib_port_attr attr; 2942 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2943 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2944 struct mlx5_hca_vport_context rep = {0}; 2945 int err; 2946 2947 err = ib_query_port(ibdev, port_num, &attr); 2948 if (err) 2949 return err; 2950 2951 if (ll == IB_LINK_LAYER_INFINIBAND) { 2952 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2953 &rep); 2954 if (err) 2955 return err; 2956 } 2957 2958 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2959 immutable->gid_tbl_len = attr.gid_tbl_len; 2960 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2961 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2962 2963 return 0; 2964 } 2965 2966 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2967 struct ib_port_immutable *immutable) 2968 { 2969 struct ib_port_attr attr; 2970 int err; 2971 2972 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2973 2974 err = ib_query_port(ibdev, port_num, &attr); 2975 if (err) 2976 return err; 2977 2978 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2979 immutable->gid_tbl_len = attr.gid_tbl_len; 2980 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2981 2982 return 0; 2983 } 2984 2985 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2986 { 2987 struct mlx5_ib_dev *dev = 2988 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2989 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2990 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2991 fw_rev_sub(dev->mdev)); 2992 } 2993 2994 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 2995 { 2996 struct mlx5_core_dev *mdev = dev->mdev; 2997 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2998 MLX5_FLOW_NAMESPACE_LAG); 2999 struct mlx5_flow_table *ft; 3000 int err; 3001 3002 if (!ns || !mlx5_lag_is_active(mdev)) 3003 return 0; 3004 3005 err = mlx5_cmd_create_vport_lag(mdev); 3006 if (err) 3007 return err; 3008 3009 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3010 if (IS_ERR(ft)) { 3011 err = PTR_ERR(ft); 3012 goto err_destroy_vport_lag; 3013 } 3014 3015 dev->flow_db->lag_demux_ft = ft; 3016 dev->lag_active = true; 3017 return 0; 3018 3019 err_destroy_vport_lag: 3020 mlx5_cmd_destroy_vport_lag(mdev); 3021 return err; 3022 } 3023 3024 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3025 { 3026 struct mlx5_core_dev *mdev = dev->mdev; 3027 3028 if (dev->lag_active) { 3029 dev->lag_active = false; 3030 3031 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3032 dev->flow_db->lag_demux_ft = NULL; 3033 3034 mlx5_cmd_destroy_vport_lag(mdev); 3035 } 3036 } 3037 3038 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num) 3039 { 3040 int err; 3041 3042 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3043 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3044 if (err) { 3045 dev->port[port_num].roce.nb.notifier_call = NULL; 3046 return err; 3047 } 3048 3049 return 0; 3050 } 3051 3052 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num) 3053 { 3054 if (dev->port[port_num].roce.nb.notifier_call) { 3055 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3056 dev->port[port_num].roce.nb.notifier_call = NULL; 3057 } 3058 } 3059 3060 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3061 { 3062 int err; 3063 3064 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3065 err = mlx5_nic_vport_enable_roce(dev->mdev); 3066 if (err) 3067 return err; 3068 } 3069 3070 err = mlx5_eth_lag_init(dev); 3071 if (err) 3072 goto err_disable_roce; 3073 3074 return 0; 3075 3076 err_disable_roce: 3077 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3078 mlx5_nic_vport_disable_roce(dev->mdev); 3079 3080 return err; 3081 } 3082 3083 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3084 { 3085 mlx5_eth_lag_cleanup(dev); 3086 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3087 mlx5_nic_vport_disable_roce(dev->mdev); 3088 } 3089 3090 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3091 enum rdma_netdev_t type, 3092 struct rdma_netdev_alloc_params *params) 3093 { 3094 if (type != RDMA_NETDEV_IPOIB) 3095 return -EOPNOTSUPP; 3096 3097 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3098 } 3099 3100 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3101 size_t count, loff_t *pos) 3102 { 3103 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3104 char lbuf[20]; 3105 int len; 3106 3107 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3108 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3109 } 3110 3111 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3112 size_t count, loff_t *pos) 3113 { 3114 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3115 u32 timeout; 3116 u32 var; 3117 3118 if (kstrtouint_from_user(buf, count, 0, &var)) 3119 return -EFAULT; 3120 3121 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3122 1000); 3123 if (timeout != var) 3124 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3125 timeout); 3126 3127 delay_drop->timeout = timeout; 3128 3129 return count; 3130 } 3131 3132 static const struct file_operations fops_delay_drop_timeout = { 3133 .owner = THIS_MODULE, 3134 .open = simple_open, 3135 .write = delay_drop_timeout_write, 3136 .read = delay_drop_timeout_read, 3137 }; 3138 3139 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3140 struct mlx5_ib_multiport_info *mpi) 3141 { 3142 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3143 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3144 int comps; 3145 int err; 3146 int i; 3147 3148 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3149 3150 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3151 3152 spin_lock(&port->mp.mpi_lock); 3153 if (!mpi->ibdev) { 3154 spin_unlock(&port->mp.mpi_lock); 3155 return; 3156 } 3157 3158 mpi->ibdev = NULL; 3159 3160 spin_unlock(&port->mp.mpi_lock); 3161 if (mpi->mdev_events.notifier_call) 3162 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3163 mpi->mdev_events.notifier_call = NULL; 3164 mlx5_remove_netdev_notifier(ibdev, port_num); 3165 spin_lock(&port->mp.mpi_lock); 3166 3167 comps = mpi->mdev_refcnt; 3168 if (comps) { 3169 mpi->unaffiliate = true; 3170 init_completion(&mpi->unref_comp); 3171 spin_unlock(&port->mp.mpi_lock); 3172 3173 for (i = 0; i < comps; i++) 3174 wait_for_completion(&mpi->unref_comp); 3175 3176 spin_lock(&port->mp.mpi_lock); 3177 mpi->unaffiliate = false; 3178 } 3179 3180 port->mp.mpi = NULL; 3181 3182 spin_unlock(&port->mp.mpi_lock); 3183 3184 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3185 3186 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3187 /* Log an error, still needed to cleanup the pointers and add 3188 * it back to the list. 3189 */ 3190 if (err) 3191 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3192 port_num + 1); 3193 3194 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3195 } 3196 3197 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3198 struct mlx5_ib_multiport_info *mpi) 3199 { 3200 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3201 int err; 3202 3203 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3204 3205 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3206 if (ibdev->port[port_num].mp.mpi) { 3207 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3208 port_num + 1); 3209 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3210 return false; 3211 } 3212 3213 ibdev->port[port_num].mp.mpi = mpi; 3214 mpi->ibdev = ibdev; 3215 mpi->mdev_events.notifier_call = NULL; 3216 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3217 3218 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3219 if (err) 3220 goto unbind; 3221 3222 err = mlx5_add_netdev_notifier(ibdev, port_num); 3223 if (err) { 3224 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3225 port_num + 1); 3226 goto unbind; 3227 } 3228 3229 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3230 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3231 3232 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3233 3234 return true; 3235 3236 unbind: 3237 mlx5_ib_unbind_slave_port(ibdev, mpi); 3238 return false; 3239 } 3240 3241 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3242 { 3243 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3244 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3245 port_num + 1); 3246 struct mlx5_ib_multiport_info *mpi; 3247 int err; 3248 u32 i; 3249 3250 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3251 return 0; 3252 3253 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3254 &dev->sys_image_guid); 3255 if (err) 3256 return err; 3257 3258 err = mlx5_nic_vport_enable_roce(dev->mdev); 3259 if (err) 3260 return err; 3261 3262 mutex_lock(&mlx5_ib_multiport_mutex); 3263 for (i = 0; i < dev->num_ports; i++) { 3264 bool bound = false; 3265 3266 /* build a stub multiport info struct for the native port. */ 3267 if (i == port_num) { 3268 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3269 if (!mpi) { 3270 mutex_unlock(&mlx5_ib_multiport_mutex); 3271 mlx5_nic_vport_disable_roce(dev->mdev); 3272 return -ENOMEM; 3273 } 3274 3275 mpi->is_master = true; 3276 mpi->mdev = dev->mdev; 3277 mpi->sys_image_guid = dev->sys_image_guid; 3278 dev->port[i].mp.mpi = mpi; 3279 mpi->ibdev = dev; 3280 mpi = NULL; 3281 continue; 3282 } 3283 3284 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3285 list) { 3286 if (dev->sys_image_guid == mpi->sys_image_guid && 3287 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3288 bound = mlx5_ib_bind_slave_port(dev, mpi); 3289 } 3290 3291 if (bound) { 3292 dev_dbg(mpi->mdev->device, 3293 "removing port from unaffiliated list.\n"); 3294 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3295 list_del(&mpi->list); 3296 break; 3297 } 3298 } 3299 if (!bound) 3300 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3301 i + 1); 3302 } 3303 3304 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3305 mutex_unlock(&mlx5_ib_multiport_mutex); 3306 return err; 3307 } 3308 3309 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3310 { 3311 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3312 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3313 port_num + 1); 3314 u32 i; 3315 3316 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3317 return; 3318 3319 mutex_lock(&mlx5_ib_multiport_mutex); 3320 for (i = 0; i < dev->num_ports; i++) { 3321 if (dev->port[i].mp.mpi) { 3322 /* Destroy the native port stub */ 3323 if (i == port_num) { 3324 kfree(dev->port[i].mp.mpi); 3325 dev->port[i].mp.mpi = NULL; 3326 } else { 3327 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3328 i + 1); 3329 list_add_tail(&dev->port[i].mp.mpi->list, 3330 &mlx5_ib_unaffiliated_port_list); 3331 mlx5_ib_unbind_slave_port(dev, 3332 dev->port[i].mp.mpi); 3333 } 3334 } 3335 } 3336 3337 mlx5_ib_dbg(dev, "removing from devlist\n"); 3338 list_del(&dev->ib_dev_list); 3339 mutex_unlock(&mlx5_ib_multiport_mutex); 3340 3341 mlx5_nic_vport_disable_roce(dev->mdev); 3342 } 3343 3344 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3345 enum rdma_remove_reason why, 3346 struct uverbs_attr_bundle *attrs) 3347 { 3348 struct mlx5_user_mmap_entry *obj = uobject->object; 3349 3350 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3351 return 0; 3352 } 3353 3354 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3355 struct mlx5_user_mmap_entry *entry, 3356 size_t length) 3357 { 3358 return rdma_user_mmap_entry_insert_range( 3359 &c->ibucontext, &entry->rdma_entry, length, 3360 (MLX5_IB_MMAP_OFFSET_START << 16), 3361 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3362 } 3363 3364 static struct mlx5_user_mmap_entry * 3365 alloc_var_entry(struct mlx5_ib_ucontext *c) 3366 { 3367 struct mlx5_user_mmap_entry *entry; 3368 struct mlx5_var_table *var_table; 3369 u32 page_idx; 3370 int err; 3371 3372 var_table = &to_mdev(c->ibucontext.device)->var_table; 3373 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3374 if (!entry) 3375 return ERR_PTR(-ENOMEM); 3376 3377 mutex_lock(&var_table->bitmap_lock); 3378 page_idx = find_first_zero_bit(var_table->bitmap, 3379 var_table->num_var_hw_entries); 3380 if (page_idx >= var_table->num_var_hw_entries) { 3381 err = -ENOSPC; 3382 mutex_unlock(&var_table->bitmap_lock); 3383 goto end; 3384 } 3385 3386 set_bit(page_idx, var_table->bitmap); 3387 mutex_unlock(&var_table->bitmap_lock); 3388 3389 entry->address = var_table->hw_start_addr + 3390 (page_idx * var_table->stride_size); 3391 entry->page_idx = page_idx; 3392 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3393 3394 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3395 var_table->stride_size); 3396 if (err) 3397 goto err_insert; 3398 3399 return entry; 3400 3401 err_insert: 3402 mutex_lock(&var_table->bitmap_lock); 3403 clear_bit(page_idx, var_table->bitmap); 3404 mutex_unlock(&var_table->bitmap_lock); 3405 end: 3406 kfree(entry); 3407 return ERR_PTR(err); 3408 } 3409 3410 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3411 struct uverbs_attr_bundle *attrs) 3412 { 3413 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3414 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3415 struct mlx5_ib_ucontext *c; 3416 struct mlx5_user_mmap_entry *entry; 3417 u64 mmap_offset; 3418 u32 length; 3419 int err; 3420 3421 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3422 if (IS_ERR(c)) 3423 return PTR_ERR(c); 3424 3425 entry = alloc_var_entry(c); 3426 if (IS_ERR(entry)) 3427 return PTR_ERR(entry); 3428 3429 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3430 length = entry->rdma_entry.npages * PAGE_SIZE; 3431 uobj->object = entry; 3432 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3433 3434 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3435 &mmap_offset, sizeof(mmap_offset)); 3436 if (err) 3437 return err; 3438 3439 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3440 &entry->page_idx, sizeof(entry->page_idx)); 3441 if (err) 3442 return err; 3443 3444 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3445 &length, sizeof(length)); 3446 return err; 3447 } 3448 3449 DECLARE_UVERBS_NAMED_METHOD( 3450 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3451 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3452 MLX5_IB_OBJECT_VAR, 3453 UVERBS_ACCESS_NEW, 3454 UA_MANDATORY), 3455 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3456 UVERBS_ATTR_TYPE(u32), 3457 UA_MANDATORY), 3458 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3459 UVERBS_ATTR_TYPE(u32), 3460 UA_MANDATORY), 3461 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3462 UVERBS_ATTR_TYPE(u64), 3463 UA_MANDATORY)); 3464 3465 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3466 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3467 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3468 MLX5_IB_OBJECT_VAR, 3469 UVERBS_ACCESS_DESTROY, 3470 UA_MANDATORY)); 3471 3472 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3473 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3474 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3475 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3476 3477 static bool var_is_supported(struct ib_device *device) 3478 { 3479 struct mlx5_ib_dev *dev = to_mdev(device); 3480 3481 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3482 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3483 } 3484 3485 static struct mlx5_user_mmap_entry * 3486 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3487 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3488 { 3489 struct mlx5_user_mmap_entry *entry; 3490 struct mlx5_ib_dev *dev; 3491 u32 uar_index; 3492 int err; 3493 3494 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3495 if (!entry) 3496 return ERR_PTR(-ENOMEM); 3497 3498 dev = to_mdev(c->ibucontext.device); 3499 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3500 if (err) 3501 goto end; 3502 3503 entry->page_idx = uar_index; 3504 entry->address = uar_index2paddress(dev, uar_index); 3505 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3506 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3507 else 3508 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3509 3510 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3511 if (err) 3512 goto err_insert; 3513 3514 return entry; 3515 3516 err_insert: 3517 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3518 end: 3519 kfree(entry); 3520 return ERR_PTR(err); 3521 } 3522 3523 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3524 struct uverbs_attr_bundle *attrs) 3525 { 3526 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3527 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3528 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3529 struct mlx5_ib_ucontext *c; 3530 struct mlx5_user_mmap_entry *entry; 3531 u64 mmap_offset; 3532 u32 length; 3533 int err; 3534 3535 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3536 if (IS_ERR(c)) 3537 return PTR_ERR(c); 3538 3539 err = uverbs_get_const(&alloc_type, attrs, 3540 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3541 if (err) 3542 return err; 3543 3544 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3545 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3546 return -EOPNOTSUPP; 3547 3548 if (!to_mdev(c->ibucontext.device)->wc_support && 3549 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3550 return -EOPNOTSUPP; 3551 3552 entry = alloc_uar_entry(c, alloc_type); 3553 if (IS_ERR(entry)) 3554 return PTR_ERR(entry); 3555 3556 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3557 length = entry->rdma_entry.npages * PAGE_SIZE; 3558 uobj->object = entry; 3559 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3560 3561 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3562 &mmap_offset, sizeof(mmap_offset)); 3563 if (err) 3564 return err; 3565 3566 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3567 &entry->page_idx, sizeof(entry->page_idx)); 3568 if (err) 3569 return err; 3570 3571 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3572 &length, sizeof(length)); 3573 return err; 3574 } 3575 3576 DECLARE_UVERBS_NAMED_METHOD( 3577 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3578 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3579 MLX5_IB_OBJECT_UAR, 3580 UVERBS_ACCESS_NEW, 3581 UA_MANDATORY), 3582 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3583 enum mlx5_ib_uapi_uar_alloc_type, 3584 UA_MANDATORY), 3585 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3586 UVERBS_ATTR_TYPE(u32), 3587 UA_MANDATORY), 3588 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3589 UVERBS_ATTR_TYPE(u32), 3590 UA_MANDATORY), 3591 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3592 UVERBS_ATTR_TYPE(u64), 3593 UA_MANDATORY)); 3594 3595 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3596 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3597 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3598 MLX5_IB_OBJECT_UAR, 3599 UVERBS_ACCESS_DESTROY, 3600 UA_MANDATORY)); 3601 3602 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3603 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3604 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3605 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3606 3607 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3608 mlx5_ib_flow_action, 3609 UVERBS_OBJECT_FLOW_ACTION, 3610 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3611 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3612 enum mlx5_ib_uapi_flow_action_flags)); 3613 3614 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3615 mlx5_ib_query_context, 3616 UVERBS_OBJECT_DEVICE, 3617 UVERBS_METHOD_QUERY_CONTEXT, 3618 UVERBS_ATTR_PTR_OUT( 3619 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3620 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3621 dump_fill_mkey), 3622 UA_MANDATORY)); 3623 3624 static const struct uapi_definition mlx5_ib_defs[] = { 3625 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3626 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3627 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3628 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3629 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3630 3631 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3632 &mlx5_ib_flow_action), 3633 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3634 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3635 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3636 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3637 {} 3638 }; 3639 3640 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3641 { 3642 mlx5_ib_cleanup_multiport_master(dev); 3643 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3644 mutex_destroy(&dev->cap_mask_mutex); 3645 WARN_ON(!xa_empty(&dev->sig_mrs)); 3646 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3647 } 3648 3649 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3650 { 3651 struct mlx5_core_dev *mdev = dev->mdev; 3652 int err; 3653 int i; 3654 3655 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3656 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3657 dev->ib_dev.phys_port_cnt = dev->num_ports; 3658 dev->ib_dev.dev.parent = mdev->device; 3659 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3660 3661 for (i = 0; i < dev->num_ports; i++) { 3662 spin_lock_init(&dev->port[i].mp.mpi_lock); 3663 rwlock_init(&dev->port[i].roce.netdev_lock); 3664 dev->port[i].roce.dev = dev; 3665 dev->port[i].roce.native_port_num = i + 1; 3666 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3667 } 3668 3669 err = mlx5_ib_init_multiport_master(dev); 3670 if (err) 3671 return err; 3672 3673 err = set_has_smi_cap(dev); 3674 if (err) 3675 goto err_mp; 3676 3677 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3678 if (err) 3679 goto err_mp; 3680 3681 if (mlx5_use_mad_ifc(dev)) 3682 get_ext_port_caps(dev); 3683 3684 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3685 3686 mutex_init(&dev->cap_mask_mutex); 3687 INIT_LIST_HEAD(&dev->qp_list); 3688 spin_lock_init(&dev->reset_flow_resource_lock); 3689 xa_init(&dev->odp_mkeys); 3690 xa_init(&dev->sig_mrs); 3691 atomic_set(&dev->mkey_var, 0); 3692 3693 spin_lock_init(&dev->dm.lock); 3694 dev->dm.dev = mdev; 3695 return 0; 3696 3697 err_mp: 3698 mlx5_ib_cleanup_multiport_master(dev); 3699 return err; 3700 } 3701 3702 static int mlx5_ib_enable_driver(struct ib_device *dev) 3703 { 3704 struct mlx5_ib_dev *mdev = to_mdev(dev); 3705 int ret; 3706 3707 ret = mlx5_ib_test_wc(mdev); 3708 mlx5_ib_dbg(mdev, "Write-Combining %s", 3709 mdev->wc_support ? "supported" : "not supported"); 3710 3711 return ret; 3712 } 3713 3714 static const struct ib_device_ops mlx5_ib_dev_ops = { 3715 .owner = THIS_MODULE, 3716 .driver_id = RDMA_DRIVER_MLX5, 3717 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3718 3719 .add_gid = mlx5_ib_add_gid, 3720 .alloc_mr = mlx5_ib_alloc_mr, 3721 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3722 .alloc_pd = mlx5_ib_alloc_pd, 3723 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3724 .attach_mcast = mlx5_ib_mcg_attach, 3725 .check_mr_status = mlx5_ib_check_mr_status, 3726 .create_ah = mlx5_ib_create_ah, 3727 .create_cq = mlx5_ib_create_cq, 3728 .create_qp = mlx5_ib_create_qp, 3729 .create_srq = mlx5_ib_create_srq, 3730 .create_user_ah = mlx5_ib_create_ah, 3731 .dealloc_pd = mlx5_ib_dealloc_pd, 3732 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3733 .del_gid = mlx5_ib_del_gid, 3734 .dereg_mr = mlx5_ib_dereg_mr, 3735 .destroy_ah = mlx5_ib_destroy_ah, 3736 .destroy_cq = mlx5_ib_destroy_cq, 3737 .destroy_qp = mlx5_ib_destroy_qp, 3738 .destroy_srq = mlx5_ib_destroy_srq, 3739 .detach_mcast = mlx5_ib_mcg_detach, 3740 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3741 .drain_rq = mlx5_ib_drain_rq, 3742 .drain_sq = mlx5_ib_drain_sq, 3743 .device_group = &mlx5_attr_group, 3744 .enable_driver = mlx5_ib_enable_driver, 3745 .get_dev_fw_str = get_dev_fw_str, 3746 .get_dma_mr = mlx5_ib_get_dma_mr, 3747 .get_link_layer = mlx5_ib_port_link_layer, 3748 .map_mr_sg = mlx5_ib_map_mr_sg, 3749 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3750 .mmap = mlx5_ib_mmap, 3751 .mmap_free = mlx5_ib_mmap_free, 3752 .modify_cq = mlx5_ib_modify_cq, 3753 .modify_device = mlx5_ib_modify_device, 3754 .modify_port = mlx5_ib_modify_port, 3755 .modify_qp = mlx5_ib_modify_qp, 3756 .modify_srq = mlx5_ib_modify_srq, 3757 .poll_cq = mlx5_ib_poll_cq, 3758 .post_recv = mlx5_ib_post_recv_nodrain, 3759 .post_send = mlx5_ib_post_send_nodrain, 3760 .post_srq_recv = mlx5_ib_post_srq_recv, 3761 .process_mad = mlx5_ib_process_mad, 3762 .query_ah = mlx5_ib_query_ah, 3763 .query_device = mlx5_ib_query_device, 3764 .query_gid = mlx5_ib_query_gid, 3765 .query_pkey = mlx5_ib_query_pkey, 3766 .query_qp = mlx5_ib_query_qp, 3767 .query_srq = mlx5_ib_query_srq, 3768 .query_ucontext = mlx5_ib_query_ucontext, 3769 .reg_user_mr = mlx5_ib_reg_user_mr, 3770 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3771 .req_notify_cq = mlx5_ib_arm_cq, 3772 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3773 .resize_cq = mlx5_ib_resize_cq, 3774 3775 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3776 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3777 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3778 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3779 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3780 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3781 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3782 }; 3783 3784 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3785 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3786 }; 3787 3788 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3789 .get_vf_config = mlx5_ib_get_vf_config, 3790 .get_vf_guid = mlx5_ib_get_vf_guid, 3791 .get_vf_stats = mlx5_ib_get_vf_stats, 3792 .set_vf_guid = mlx5_ib_set_vf_guid, 3793 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3794 }; 3795 3796 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3797 .alloc_mw = mlx5_ib_alloc_mw, 3798 .dealloc_mw = mlx5_ib_dealloc_mw, 3799 3800 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3801 }; 3802 3803 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3804 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3805 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3806 3807 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3808 }; 3809 3810 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3811 { 3812 struct mlx5_core_dev *mdev = dev->mdev; 3813 struct mlx5_var_table *var_table = &dev->var_table; 3814 u8 log_doorbell_bar_size; 3815 u8 log_doorbell_stride; 3816 u64 bar_size; 3817 3818 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3819 log_doorbell_bar_size); 3820 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3821 log_doorbell_stride); 3822 var_table->hw_start_addr = dev->mdev->bar_addr + 3823 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3824 doorbell_bar_offset); 3825 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3826 var_table->stride_size = 1ULL << log_doorbell_stride; 3827 var_table->num_var_hw_entries = div_u64(bar_size, 3828 var_table->stride_size); 3829 mutex_init(&var_table->bitmap_lock); 3830 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3831 GFP_KERNEL); 3832 return (var_table->bitmap) ? 0 : -ENOMEM; 3833 } 3834 3835 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3836 { 3837 bitmap_free(dev->var_table.bitmap); 3838 } 3839 3840 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3841 { 3842 struct mlx5_core_dev *mdev = dev->mdev; 3843 int err; 3844 3845 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3846 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3847 ib_set_device_ops(&dev->ib_dev, 3848 &mlx5_ib_dev_ipoib_enhanced_ops); 3849 3850 if (mlx5_core_is_pf(mdev)) 3851 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3852 3853 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3854 3855 if (MLX5_CAP_GEN(mdev, imaicl)) 3856 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3857 3858 if (MLX5_CAP_GEN(mdev, xrc)) 3859 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3860 3861 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3862 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3863 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3864 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3865 3866 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3867 3868 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3869 dev->ib_dev.driver_def = mlx5_ib_defs; 3870 3871 err = init_node_data(dev); 3872 if (err) 3873 return err; 3874 3875 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3876 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3877 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3878 mutex_init(&dev->lb.mutex); 3879 3880 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3881 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3882 err = mlx5_ib_init_var_table(dev); 3883 if (err) 3884 return err; 3885 } 3886 3887 dev->ib_dev.use_cq_dim = true; 3888 3889 return 0; 3890 } 3891 3892 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3893 .get_port_immutable = mlx5_port_immutable, 3894 .query_port = mlx5_ib_query_port, 3895 }; 3896 3897 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3898 { 3899 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3900 return 0; 3901 } 3902 3903 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3904 .get_port_immutable = mlx5_port_rep_immutable, 3905 .query_port = mlx5_ib_rep_query_port, 3906 .query_pkey = mlx5_ib_rep_query_pkey, 3907 }; 3908 3909 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3910 { 3911 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3912 return 0; 3913 } 3914 3915 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3916 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3917 .create_wq = mlx5_ib_create_wq, 3918 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3919 .destroy_wq = mlx5_ib_destroy_wq, 3920 .get_netdev = mlx5_ib_get_netdev, 3921 .modify_wq = mlx5_ib_modify_wq, 3922 3923 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3924 ib_rwq_ind_tbl), 3925 }; 3926 3927 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3928 { 3929 struct mlx5_core_dev *mdev = dev->mdev; 3930 enum rdma_link_layer ll; 3931 int port_type_cap; 3932 u32 port_num = 0; 3933 int err; 3934 3935 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3936 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3937 3938 if (ll == IB_LINK_LAYER_ETHERNET) { 3939 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3940 3941 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3942 3943 /* Register only for native ports */ 3944 err = mlx5_add_netdev_notifier(dev, port_num); 3945 if (err) 3946 return err; 3947 3948 err = mlx5_enable_eth(dev); 3949 if (err) 3950 goto cleanup; 3951 } 3952 3953 return 0; 3954 cleanup: 3955 mlx5_remove_netdev_notifier(dev, port_num); 3956 return err; 3957 } 3958 3959 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3960 { 3961 struct mlx5_core_dev *mdev = dev->mdev; 3962 enum rdma_link_layer ll; 3963 int port_type_cap; 3964 u32 port_num; 3965 3966 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3967 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3968 3969 if (ll == IB_LINK_LAYER_ETHERNET) { 3970 mlx5_disable_eth(dev); 3971 3972 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3973 mlx5_remove_netdev_notifier(dev, port_num); 3974 } 3975 } 3976 3977 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3978 { 3979 mlx5_ib_init_cong_debugfs(dev, 3980 mlx5_core_native_port_num(dev->mdev) - 1); 3981 return 0; 3982 } 3983 3984 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 3985 { 3986 mlx5_ib_cleanup_cong_debugfs(dev, 3987 mlx5_core_native_port_num(dev->mdev) - 1); 3988 } 3989 3990 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 3991 { 3992 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3993 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 3994 } 3995 3996 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 3997 { 3998 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3999 } 4000 4001 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4002 { 4003 int err; 4004 4005 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4006 if (err) 4007 return err; 4008 4009 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4010 if (err) 4011 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4012 4013 return err; 4014 } 4015 4016 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4017 { 4018 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4019 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4020 } 4021 4022 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4023 { 4024 const char *name; 4025 4026 if (!mlx5_lag_is_active(dev->mdev)) 4027 name = "mlx5_%d"; 4028 else 4029 name = "mlx5_bond_%d"; 4030 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4031 } 4032 4033 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4034 { 4035 int err; 4036 4037 err = mlx5_mr_cache_cleanup(dev); 4038 if (err) 4039 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4040 4041 if (dev->umrc.qp) 4042 ib_destroy_qp(dev->umrc.qp); 4043 if (dev->umrc.cq) 4044 ib_free_cq(dev->umrc.cq); 4045 if (dev->umrc.pd) 4046 ib_dealloc_pd(dev->umrc.pd); 4047 } 4048 4049 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4050 { 4051 ib_unregister_device(&dev->ib_dev); 4052 } 4053 4054 enum { 4055 MAX_UMR_WR = 128, 4056 }; 4057 4058 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4059 { 4060 struct ib_qp_init_attr *init_attr = NULL; 4061 struct ib_qp_attr *attr = NULL; 4062 struct ib_pd *pd; 4063 struct ib_cq *cq; 4064 struct ib_qp *qp; 4065 int ret; 4066 4067 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4068 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4069 if (!attr || !init_attr) { 4070 ret = -ENOMEM; 4071 goto error_0; 4072 } 4073 4074 pd = ib_alloc_pd(&dev->ib_dev, 0); 4075 if (IS_ERR(pd)) { 4076 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4077 ret = PTR_ERR(pd); 4078 goto error_0; 4079 } 4080 4081 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4082 if (IS_ERR(cq)) { 4083 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4084 ret = PTR_ERR(cq); 4085 goto error_2; 4086 } 4087 4088 init_attr->send_cq = cq; 4089 init_attr->recv_cq = cq; 4090 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4091 init_attr->cap.max_send_wr = MAX_UMR_WR; 4092 init_attr->cap.max_send_sge = 1; 4093 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4094 init_attr->port_num = 1; 4095 qp = ib_create_qp(pd, init_attr); 4096 if (IS_ERR(qp)) { 4097 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4098 ret = PTR_ERR(qp); 4099 goto error_3; 4100 } 4101 4102 attr->qp_state = IB_QPS_INIT; 4103 attr->port_num = 1; 4104 ret = ib_modify_qp(qp, attr, 4105 IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT); 4106 if (ret) { 4107 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4108 goto error_4; 4109 } 4110 4111 memset(attr, 0, sizeof(*attr)); 4112 attr->qp_state = IB_QPS_RTR; 4113 attr->path_mtu = IB_MTU_256; 4114 4115 ret = ib_modify_qp(qp, attr, IB_QP_STATE); 4116 if (ret) { 4117 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4118 goto error_4; 4119 } 4120 4121 memset(attr, 0, sizeof(*attr)); 4122 attr->qp_state = IB_QPS_RTS; 4123 ret = ib_modify_qp(qp, attr, IB_QP_STATE); 4124 if (ret) { 4125 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4126 goto error_4; 4127 } 4128 4129 dev->umrc.qp = qp; 4130 dev->umrc.cq = cq; 4131 dev->umrc.pd = pd; 4132 4133 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4134 ret = mlx5_mr_cache_init(dev); 4135 if (ret) { 4136 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4137 goto error_4; 4138 } 4139 4140 kfree(attr); 4141 kfree(init_attr); 4142 4143 return 0; 4144 4145 error_4: 4146 ib_destroy_qp(qp); 4147 dev->umrc.qp = NULL; 4148 4149 error_3: 4150 ib_free_cq(cq); 4151 dev->umrc.cq = NULL; 4152 4153 error_2: 4154 ib_dealloc_pd(pd); 4155 dev->umrc.pd = NULL; 4156 4157 error_0: 4158 kfree(attr); 4159 kfree(init_attr); 4160 return ret; 4161 } 4162 4163 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4164 { 4165 struct dentry *root; 4166 4167 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4168 return 0; 4169 4170 mutex_init(&dev->delay_drop.lock); 4171 dev->delay_drop.dev = dev; 4172 dev->delay_drop.activate = false; 4173 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4174 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4175 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4176 atomic_set(&dev->delay_drop.events_cnt, 0); 4177 4178 if (!mlx5_debugfs_root) 4179 return 0; 4180 4181 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4182 dev->delay_drop.dir_debugfs = root; 4183 4184 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4185 &dev->delay_drop.events_cnt); 4186 debugfs_create_atomic_t("num_rqs", 0400, root, 4187 &dev->delay_drop.rqs_cnt); 4188 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4189 &fops_delay_drop_timeout); 4190 return 0; 4191 } 4192 4193 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4194 { 4195 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4196 return; 4197 4198 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4199 if (!dev->delay_drop.dir_debugfs) 4200 return; 4201 4202 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4203 dev->delay_drop.dir_debugfs = NULL; 4204 } 4205 4206 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4207 { 4208 dev->mdev_events.notifier_call = mlx5_ib_event; 4209 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4210 return 0; 4211 } 4212 4213 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4214 { 4215 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4216 } 4217 4218 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4219 const struct mlx5_ib_profile *profile, 4220 int stage) 4221 { 4222 dev->ib_active = false; 4223 4224 /* Number of stages to cleanup */ 4225 while (stage) { 4226 stage--; 4227 if (profile->stage[stage].cleanup) 4228 profile->stage[stage].cleanup(dev); 4229 } 4230 4231 kfree(dev->port); 4232 ib_dealloc_device(&dev->ib_dev); 4233 } 4234 4235 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4236 const struct mlx5_ib_profile *profile) 4237 { 4238 int err; 4239 int i; 4240 4241 dev->profile = profile; 4242 4243 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4244 if (profile->stage[i].init) { 4245 err = profile->stage[i].init(dev); 4246 if (err) 4247 goto err_out; 4248 } 4249 } 4250 4251 dev->ib_active = true; 4252 return 0; 4253 4254 err_out: 4255 /* Clean up stages which were initialized */ 4256 while (i) { 4257 i--; 4258 if (profile->stage[i].cleanup) 4259 profile->stage[i].cleanup(dev); 4260 } 4261 return -ENOMEM; 4262 } 4263 4264 static const struct mlx5_ib_profile pf_profile = { 4265 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4266 mlx5_ib_stage_init_init, 4267 mlx5_ib_stage_init_cleanup), 4268 STAGE_CREATE(MLX5_IB_STAGE_FS, 4269 mlx5_ib_fs_init, 4270 mlx5_ib_fs_cleanup), 4271 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4272 mlx5_ib_stage_caps_init, 4273 mlx5_ib_stage_caps_cleanup), 4274 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4275 mlx5_ib_stage_non_default_cb, 4276 NULL), 4277 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4278 mlx5_ib_roce_init, 4279 mlx5_ib_roce_cleanup), 4280 STAGE_CREATE(MLX5_IB_STAGE_QP, 4281 mlx5_init_qp_table, 4282 mlx5_cleanup_qp_table), 4283 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4284 mlx5_init_srq_table, 4285 mlx5_cleanup_srq_table), 4286 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4287 mlx5_ib_dev_res_init, 4288 mlx5_ib_dev_res_cleanup), 4289 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4290 mlx5_ib_stage_dev_notifier_init, 4291 mlx5_ib_stage_dev_notifier_cleanup), 4292 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4293 mlx5_ib_odp_init_one, 4294 mlx5_ib_odp_cleanup_one), 4295 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4296 mlx5_ib_counters_init, 4297 mlx5_ib_counters_cleanup), 4298 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4299 mlx5_ib_stage_cong_debugfs_init, 4300 mlx5_ib_stage_cong_debugfs_cleanup), 4301 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4302 mlx5_ib_stage_uar_init, 4303 mlx5_ib_stage_uar_cleanup), 4304 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4305 mlx5_ib_stage_bfrag_init, 4306 mlx5_ib_stage_bfrag_cleanup), 4307 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4308 NULL, 4309 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4310 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4311 mlx5_ib_devx_init, 4312 mlx5_ib_devx_cleanup), 4313 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4314 mlx5_ib_stage_ib_reg_init, 4315 mlx5_ib_stage_ib_reg_cleanup), 4316 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4317 mlx5_ib_stage_post_ib_reg_umr_init, 4318 NULL), 4319 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4320 mlx5_ib_stage_delay_drop_init, 4321 mlx5_ib_stage_delay_drop_cleanup), 4322 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4323 mlx5_ib_restrack_init, 4324 NULL), 4325 }; 4326 4327 const struct mlx5_ib_profile raw_eth_profile = { 4328 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4329 mlx5_ib_stage_init_init, 4330 mlx5_ib_stage_init_cleanup), 4331 STAGE_CREATE(MLX5_IB_STAGE_FS, 4332 mlx5_ib_fs_init, 4333 mlx5_ib_fs_cleanup), 4334 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4335 mlx5_ib_stage_caps_init, 4336 mlx5_ib_stage_caps_cleanup), 4337 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4338 mlx5_ib_stage_raw_eth_non_default_cb, 4339 NULL), 4340 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4341 mlx5_ib_roce_init, 4342 mlx5_ib_roce_cleanup), 4343 STAGE_CREATE(MLX5_IB_STAGE_QP, 4344 mlx5_init_qp_table, 4345 mlx5_cleanup_qp_table), 4346 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4347 mlx5_init_srq_table, 4348 mlx5_cleanup_srq_table), 4349 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4350 mlx5_ib_dev_res_init, 4351 mlx5_ib_dev_res_cleanup), 4352 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4353 mlx5_ib_stage_dev_notifier_init, 4354 mlx5_ib_stage_dev_notifier_cleanup), 4355 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4356 mlx5_ib_counters_init, 4357 mlx5_ib_counters_cleanup), 4358 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4359 mlx5_ib_stage_cong_debugfs_init, 4360 mlx5_ib_stage_cong_debugfs_cleanup), 4361 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4362 mlx5_ib_stage_uar_init, 4363 mlx5_ib_stage_uar_cleanup), 4364 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4365 mlx5_ib_stage_bfrag_init, 4366 mlx5_ib_stage_bfrag_cleanup), 4367 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4368 NULL, 4369 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4370 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4371 mlx5_ib_devx_init, 4372 mlx5_ib_devx_cleanup), 4373 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4374 mlx5_ib_stage_ib_reg_init, 4375 mlx5_ib_stage_ib_reg_cleanup), 4376 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4377 mlx5_ib_stage_post_ib_reg_umr_init, 4378 NULL), 4379 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4380 mlx5_ib_restrack_init, 4381 NULL), 4382 }; 4383 4384 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4385 const struct auxiliary_device_id *id) 4386 { 4387 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4388 struct mlx5_core_dev *mdev = idev->mdev; 4389 struct mlx5_ib_multiport_info *mpi; 4390 struct mlx5_ib_dev *dev; 4391 bool bound = false; 4392 int err; 4393 4394 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4395 if (!mpi) 4396 return -ENOMEM; 4397 4398 mpi->mdev = mdev; 4399 err = mlx5_query_nic_vport_system_image_guid(mdev, 4400 &mpi->sys_image_guid); 4401 if (err) { 4402 kfree(mpi); 4403 return err; 4404 } 4405 4406 mutex_lock(&mlx5_ib_multiport_mutex); 4407 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4408 if (dev->sys_image_guid == mpi->sys_image_guid) 4409 bound = mlx5_ib_bind_slave_port(dev, mpi); 4410 4411 if (bound) { 4412 rdma_roce_rescan_device(&dev->ib_dev); 4413 mpi->ibdev->ib_active = true; 4414 break; 4415 } 4416 } 4417 4418 if (!bound) { 4419 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4420 dev_dbg(mdev->device, 4421 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4422 } 4423 mutex_unlock(&mlx5_ib_multiport_mutex); 4424 4425 auxiliary_set_drvdata(adev, mpi); 4426 return 0; 4427 } 4428 4429 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4430 { 4431 struct mlx5_ib_multiport_info *mpi; 4432 4433 mpi = auxiliary_get_drvdata(adev); 4434 mutex_lock(&mlx5_ib_multiport_mutex); 4435 if (mpi->ibdev) 4436 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4437 else 4438 list_del(&mpi->list); 4439 mutex_unlock(&mlx5_ib_multiport_mutex); 4440 kfree(mpi); 4441 } 4442 4443 static int mlx5r_probe(struct auxiliary_device *adev, 4444 const struct auxiliary_device_id *id) 4445 { 4446 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4447 struct mlx5_core_dev *mdev = idev->mdev; 4448 const struct mlx5_ib_profile *profile; 4449 int port_type_cap, num_ports, ret; 4450 enum rdma_link_layer ll; 4451 struct mlx5_ib_dev *dev; 4452 4453 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4454 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4455 4456 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4457 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4458 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4459 if (!dev) 4460 return -ENOMEM; 4461 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4462 GFP_KERNEL); 4463 if (!dev->port) { 4464 ib_dealloc_device(&dev->ib_dev); 4465 return -ENOMEM; 4466 } 4467 4468 dev->mdev = mdev; 4469 dev->num_ports = num_ports; 4470 4471 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev)) 4472 profile = &raw_eth_profile; 4473 else 4474 profile = &pf_profile; 4475 4476 ret = __mlx5_ib_add(dev, profile); 4477 if (ret) { 4478 kfree(dev->port); 4479 ib_dealloc_device(&dev->ib_dev); 4480 return ret; 4481 } 4482 4483 auxiliary_set_drvdata(adev, dev); 4484 return 0; 4485 } 4486 4487 static void mlx5r_remove(struct auxiliary_device *adev) 4488 { 4489 struct mlx5_ib_dev *dev; 4490 4491 dev = auxiliary_get_drvdata(adev); 4492 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4493 } 4494 4495 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4496 { .name = MLX5_ADEV_NAME ".multiport", }, 4497 {}, 4498 }; 4499 4500 static const struct auxiliary_device_id mlx5r_id_table[] = { 4501 { .name = MLX5_ADEV_NAME ".rdma", }, 4502 {}, 4503 }; 4504 4505 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4506 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4507 4508 static struct auxiliary_driver mlx5r_mp_driver = { 4509 .name = "multiport", 4510 .probe = mlx5r_mp_probe, 4511 .remove = mlx5r_mp_remove, 4512 .id_table = mlx5r_mp_id_table, 4513 }; 4514 4515 static struct auxiliary_driver mlx5r_driver = { 4516 .name = "rdma", 4517 .probe = mlx5r_probe, 4518 .remove = mlx5r_remove, 4519 .id_table = mlx5r_id_table, 4520 }; 4521 4522 static int __init mlx5_ib_init(void) 4523 { 4524 int ret; 4525 4526 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4527 if (!xlt_emergency_page) 4528 return -ENOMEM; 4529 4530 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4531 if (!mlx5_ib_event_wq) { 4532 free_page((unsigned long)xlt_emergency_page); 4533 return -ENOMEM; 4534 } 4535 4536 mlx5_ib_odp_init(); 4537 ret = mlx5r_rep_init(); 4538 if (ret) 4539 goto rep_err; 4540 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4541 if (ret) 4542 goto mp_err; 4543 ret = auxiliary_driver_register(&mlx5r_driver); 4544 if (ret) 4545 goto drv_err; 4546 return 0; 4547 4548 drv_err: 4549 auxiliary_driver_unregister(&mlx5r_mp_driver); 4550 mp_err: 4551 mlx5r_rep_cleanup(); 4552 rep_err: 4553 destroy_workqueue(mlx5_ib_event_wq); 4554 free_page((unsigned long)xlt_emergency_page); 4555 return ret; 4556 } 4557 4558 static void __exit mlx5_ib_cleanup(void) 4559 { 4560 auxiliary_driver_unregister(&mlx5r_driver); 4561 auxiliary_driver_unregister(&mlx5r_mp_driver); 4562 mlx5r_rep_cleanup(); 4563 4564 destroy_workqueue(mlx5_ib_event_wq); 4565 free_page((unsigned long)xlt_emergency_page); 4566 } 4567 4568 module_init(mlx5_ib_init); 4569 module_exit(mlx5_ib_cleanup); 4570