1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/sched/mm.h> 45 #include <linux/delay.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_addr.h> 48 #include <rdma/ib_cache.h> 49 #include <linux/mlx5/port.h> 50 #include <linux/mlx5/vport.h> 51 #include <linux/list.h> 52 #include <rdma/ib_smi.h> 53 #include <rdma/ib_umem.h> 54 #include <linux/in.h> 55 #include <linux/etherdevice.h> 56 #include <linux/mlx5/fs.h> 57 #include <linux/mlx5/vport.h> 58 #include "mlx5_ib.h" 59 60 #define DRIVER_NAME "mlx5_ib" 61 #define DRIVER_VERSION "2.2-1" 62 #define DRIVER_RELDATE "Feb 2014" 63 64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 66 MODULE_LICENSE("Dual BSD/GPL"); 67 MODULE_VERSION(DRIVER_VERSION); 68 69 static char mlx5_version[] = 70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 71 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 72 73 enum { 74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 75 }; 76 77 static enum rdma_link_layer 78 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 79 { 80 switch (port_type_cap) { 81 case MLX5_CAP_PORT_TYPE_IB: 82 return IB_LINK_LAYER_INFINIBAND; 83 case MLX5_CAP_PORT_TYPE_ETH: 84 return IB_LINK_LAYER_ETHERNET; 85 default: 86 return IB_LINK_LAYER_UNSPECIFIED; 87 } 88 } 89 90 static enum rdma_link_layer 91 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 92 { 93 struct mlx5_ib_dev *dev = to_mdev(device); 94 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 95 96 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 97 } 98 99 static int mlx5_netdev_event(struct notifier_block *this, 100 unsigned long event, void *ptr) 101 { 102 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 103 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 104 roce.nb); 105 106 switch (event) { 107 case NETDEV_REGISTER: 108 case NETDEV_UNREGISTER: 109 write_lock(&ibdev->roce.netdev_lock); 110 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 111 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 112 NULL : ndev; 113 write_unlock(&ibdev->roce.netdev_lock); 114 break; 115 116 case NETDEV_UP: 117 case NETDEV_DOWN: { 118 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 119 struct net_device *upper = NULL; 120 121 if (lag_ndev) { 122 upper = netdev_master_upper_dev_get(lag_ndev); 123 dev_put(lag_ndev); 124 } 125 126 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 127 && ibdev->ib_active) { 128 struct ib_event ibev = { }; 129 130 ibev.device = &ibdev->ib_dev; 131 ibev.event = (event == NETDEV_UP) ? 132 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 133 ibev.element.port_num = 1; 134 ib_dispatch_event(&ibev); 135 } 136 break; 137 } 138 139 default: 140 break; 141 } 142 143 return NOTIFY_DONE; 144 } 145 146 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 147 u8 port_num) 148 { 149 struct mlx5_ib_dev *ibdev = to_mdev(device); 150 struct net_device *ndev; 151 152 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 153 if (ndev) 154 return ndev; 155 156 /* Ensure ndev does not disappear before we invoke dev_hold() 157 */ 158 read_lock(&ibdev->roce.netdev_lock); 159 ndev = ibdev->roce.netdev; 160 if (ndev) 161 dev_hold(ndev); 162 read_unlock(&ibdev->roce.netdev_lock); 163 164 return ndev; 165 } 166 167 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 168 struct ib_port_attr *props) 169 { 170 struct mlx5_ib_dev *dev = to_mdev(device); 171 struct net_device *ndev, *upper; 172 enum ib_mtu ndev_ib_mtu; 173 u16 qkey_viol_cntr; 174 175 /* props being zeroed by the caller, avoid zeroing it here */ 176 177 props->port_cap_flags |= IB_PORT_CM_SUP; 178 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 179 180 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 181 roce_address_table_size); 182 props->max_mtu = IB_MTU_4096; 183 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 184 props->pkey_tbl_len = 1; 185 props->state = IB_PORT_DOWN; 186 props->phys_state = 3; 187 188 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 189 props->qkey_viol_cntr = qkey_viol_cntr; 190 191 ndev = mlx5_ib_get_netdev(device, port_num); 192 if (!ndev) 193 return 0; 194 195 if (mlx5_lag_is_active(dev->mdev)) { 196 rcu_read_lock(); 197 upper = netdev_master_upper_dev_get_rcu(ndev); 198 if (upper) { 199 dev_put(ndev); 200 ndev = upper; 201 dev_hold(ndev); 202 } 203 rcu_read_unlock(); 204 } 205 206 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 207 props->state = IB_PORT_ACTIVE; 208 props->phys_state = 5; 209 } 210 211 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 212 213 dev_put(ndev); 214 215 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 216 217 props->active_width = IB_WIDTH_4X; /* TODO */ 218 props->active_speed = IB_SPEED_QDR; /* TODO */ 219 220 return 0; 221 } 222 223 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 224 const struct ib_gid_attr *attr, 225 void *mlx5_addr) 226 { 227 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 228 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 229 source_l3_address); 230 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 231 source_mac_47_32); 232 233 if (!gid) 234 return; 235 236 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 237 238 if (is_vlan_dev(attr->ndev)) { 239 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 240 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 241 } 242 243 switch (attr->gid_type) { 244 case IB_GID_TYPE_IB: 245 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 246 break; 247 case IB_GID_TYPE_ROCE_UDP_ENCAP: 248 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 249 break; 250 251 default: 252 WARN_ON(true); 253 } 254 255 if (attr->gid_type != IB_GID_TYPE_IB) { 256 if (ipv6_addr_v4mapped((void *)gid)) 257 MLX5_SET_RA(mlx5_addr, roce_l3_type, 258 MLX5_ROCE_L3_TYPE_IPV4); 259 else 260 MLX5_SET_RA(mlx5_addr, roce_l3_type, 261 MLX5_ROCE_L3_TYPE_IPV6); 262 } 263 264 if ((attr->gid_type == IB_GID_TYPE_IB) || 265 !ipv6_addr_v4mapped((void *)gid)) 266 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 267 else 268 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 269 } 270 271 static int set_roce_addr(struct ib_device *device, u8 port_num, 272 unsigned int index, 273 const union ib_gid *gid, 274 const struct ib_gid_attr *attr) 275 { 276 struct mlx5_ib_dev *dev = to_mdev(device); 277 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 278 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 279 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 280 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 281 282 if (ll != IB_LINK_LAYER_ETHERNET) 283 return -EINVAL; 284 285 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 286 287 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 288 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 289 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 290 } 291 292 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 293 unsigned int index, const union ib_gid *gid, 294 const struct ib_gid_attr *attr, 295 __always_unused void **context) 296 { 297 return set_roce_addr(device, port_num, index, gid, attr); 298 } 299 300 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 301 unsigned int index, __always_unused void **context) 302 { 303 return set_roce_addr(device, port_num, index, NULL, NULL); 304 } 305 306 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 307 int index) 308 { 309 struct ib_gid_attr attr; 310 union ib_gid gid; 311 312 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 313 return 0; 314 315 if (!attr.ndev) 316 return 0; 317 318 dev_put(attr.ndev); 319 320 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 321 return 0; 322 323 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 324 } 325 326 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 327 int index, enum ib_gid_type *gid_type) 328 { 329 struct ib_gid_attr attr; 330 union ib_gid gid; 331 int ret; 332 333 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 334 if (ret) 335 return ret; 336 337 if (!attr.ndev) 338 return -ENODEV; 339 340 dev_put(attr.ndev); 341 342 *gid_type = attr.gid_type; 343 344 return 0; 345 } 346 347 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 348 { 349 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 350 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 351 return 0; 352 } 353 354 enum { 355 MLX5_VPORT_ACCESS_METHOD_MAD, 356 MLX5_VPORT_ACCESS_METHOD_HCA, 357 MLX5_VPORT_ACCESS_METHOD_NIC, 358 }; 359 360 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 361 { 362 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 363 return MLX5_VPORT_ACCESS_METHOD_MAD; 364 365 if (mlx5_ib_port_link_layer(ibdev, 1) == 366 IB_LINK_LAYER_ETHERNET) 367 return MLX5_VPORT_ACCESS_METHOD_NIC; 368 369 return MLX5_VPORT_ACCESS_METHOD_HCA; 370 } 371 372 static void get_atomic_caps(struct mlx5_ib_dev *dev, 373 struct ib_device_attr *props) 374 { 375 u8 tmp; 376 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 377 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 378 u8 atomic_req_8B_endianness_mode = 379 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 380 381 /* Check if HW supports 8 bytes standard atomic operations and capable 382 * of host endianness respond 383 */ 384 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 385 if (((atomic_operations & tmp) == tmp) && 386 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 387 (atomic_req_8B_endianness_mode)) { 388 props->atomic_cap = IB_ATOMIC_HCA; 389 } else { 390 props->atomic_cap = IB_ATOMIC_NONE; 391 } 392 } 393 394 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 395 __be64 *sys_image_guid) 396 { 397 struct mlx5_ib_dev *dev = to_mdev(ibdev); 398 struct mlx5_core_dev *mdev = dev->mdev; 399 u64 tmp; 400 int err; 401 402 switch (mlx5_get_vport_access_method(ibdev)) { 403 case MLX5_VPORT_ACCESS_METHOD_MAD: 404 return mlx5_query_mad_ifc_system_image_guid(ibdev, 405 sys_image_guid); 406 407 case MLX5_VPORT_ACCESS_METHOD_HCA: 408 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 409 break; 410 411 case MLX5_VPORT_ACCESS_METHOD_NIC: 412 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 413 break; 414 415 default: 416 return -EINVAL; 417 } 418 419 if (!err) 420 *sys_image_guid = cpu_to_be64(tmp); 421 422 return err; 423 424 } 425 426 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 427 u16 *max_pkeys) 428 { 429 struct mlx5_ib_dev *dev = to_mdev(ibdev); 430 struct mlx5_core_dev *mdev = dev->mdev; 431 432 switch (mlx5_get_vport_access_method(ibdev)) { 433 case MLX5_VPORT_ACCESS_METHOD_MAD: 434 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 435 436 case MLX5_VPORT_ACCESS_METHOD_HCA: 437 case MLX5_VPORT_ACCESS_METHOD_NIC: 438 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 439 pkey_table_size)); 440 return 0; 441 442 default: 443 return -EINVAL; 444 } 445 } 446 447 static int mlx5_query_vendor_id(struct ib_device *ibdev, 448 u32 *vendor_id) 449 { 450 struct mlx5_ib_dev *dev = to_mdev(ibdev); 451 452 switch (mlx5_get_vport_access_method(ibdev)) { 453 case MLX5_VPORT_ACCESS_METHOD_MAD: 454 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 455 456 case MLX5_VPORT_ACCESS_METHOD_HCA: 457 case MLX5_VPORT_ACCESS_METHOD_NIC: 458 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 459 460 default: 461 return -EINVAL; 462 } 463 } 464 465 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 466 __be64 *node_guid) 467 { 468 u64 tmp; 469 int err; 470 471 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 472 case MLX5_VPORT_ACCESS_METHOD_MAD: 473 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *node_guid = cpu_to_be64(tmp); 489 490 return err; 491 } 492 493 struct mlx5_reg_node_desc { 494 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 495 }; 496 497 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 498 { 499 struct mlx5_reg_node_desc in; 500 501 if (mlx5_use_mad_ifc(dev)) 502 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 503 504 memset(&in, 0, sizeof(in)); 505 506 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 507 sizeof(struct mlx5_reg_node_desc), 508 MLX5_REG_NODE_DESC, 0, 0); 509 } 510 511 static int mlx5_ib_query_device(struct ib_device *ibdev, 512 struct ib_device_attr *props, 513 struct ib_udata *uhw) 514 { 515 struct mlx5_ib_dev *dev = to_mdev(ibdev); 516 struct mlx5_core_dev *mdev = dev->mdev; 517 int err = -ENOMEM; 518 int max_sq_desc; 519 int max_rq_sg; 520 int max_sq_sg; 521 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 522 struct mlx5_ib_query_device_resp resp = {}; 523 size_t resp_len; 524 u64 max_tso; 525 526 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 527 if (uhw->outlen && uhw->outlen < resp_len) 528 return -EINVAL; 529 else 530 resp.response_length = resp_len; 531 532 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 533 return -EINVAL; 534 535 memset(props, 0, sizeof(*props)); 536 err = mlx5_query_system_image_guid(ibdev, 537 &props->sys_image_guid); 538 if (err) 539 return err; 540 541 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 542 if (err) 543 return err; 544 545 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 546 if (err) 547 return err; 548 549 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 550 (fw_rev_min(dev->mdev) << 16) | 551 fw_rev_sub(dev->mdev); 552 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 553 IB_DEVICE_PORT_ACTIVE_EVENT | 554 IB_DEVICE_SYS_IMAGE_GUID | 555 IB_DEVICE_RC_RNR_NAK_GEN; 556 557 if (MLX5_CAP_GEN(mdev, pkv)) 558 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 559 if (MLX5_CAP_GEN(mdev, qkv)) 560 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 561 if (MLX5_CAP_GEN(mdev, apm)) 562 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 563 if (MLX5_CAP_GEN(mdev, xrc)) 564 props->device_cap_flags |= IB_DEVICE_XRC; 565 if (MLX5_CAP_GEN(mdev, imaicl)) { 566 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 567 IB_DEVICE_MEM_WINDOW_TYPE_2B; 568 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 569 /* We support 'Gappy' memory registration too */ 570 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 571 } 572 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 573 if (MLX5_CAP_GEN(mdev, sho)) { 574 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 575 /* At this stage no support for signature handover */ 576 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 577 IB_PROT_T10DIF_TYPE_2 | 578 IB_PROT_T10DIF_TYPE_3; 579 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 580 IB_GUARD_T10DIF_CSUM; 581 } 582 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 583 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 584 585 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 586 if (MLX5_CAP_ETH(mdev, csum_cap)) { 587 /* Legacy bit to support old userspace libraries */ 588 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 589 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 590 } 591 592 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 593 props->raw_packet_caps |= 594 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 595 596 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 597 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 598 if (max_tso) { 599 resp.tso_caps.max_tso = 1 << max_tso; 600 resp.tso_caps.supported_qpts |= 601 1 << IB_QPT_RAW_PACKET; 602 resp.response_length += sizeof(resp.tso_caps); 603 } 604 } 605 606 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 607 resp.rss_caps.rx_hash_function = 608 MLX5_RX_HASH_FUNC_TOEPLITZ; 609 resp.rss_caps.rx_hash_fields_mask = 610 MLX5_RX_HASH_SRC_IPV4 | 611 MLX5_RX_HASH_DST_IPV4 | 612 MLX5_RX_HASH_SRC_IPV6 | 613 MLX5_RX_HASH_DST_IPV6 | 614 MLX5_RX_HASH_SRC_PORT_TCP | 615 MLX5_RX_HASH_DST_PORT_TCP | 616 MLX5_RX_HASH_SRC_PORT_UDP | 617 MLX5_RX_HASH_DST_PORT_UDP; 618 resp.response_length += sizeof(resp.rss_caps); 619 } 620 } else { 621 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 622 resp.response_length += sizeof(resp.tso_caps); 623 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 624 resp.response_length += sizeof(resp.rss_caps); 625 } 626 627 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 628 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 629 props->device_cap_flags |= IB_DEVICE_UD_TSO; 630 } 631 632 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 633 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 634 /* Legacy bit to support old userspace libraries */ 635 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 636 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 637 } 638 639 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 640 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 641 642 props->vendor_part_id = mdev->pdev->device; 643 props->hw_ver = mdev->pdev->revision; 644 645 props->max_mr_size = ~0ull; 646 props->page_size_cap = ~(min_page_size - 1); 647 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 648 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 649 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 650 sizeof(struct mlx5_wqe_data_seg); 651 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 652 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 653 sizeof(struct mlx5_wqe_raddr_seg)) / 654 sizeof(struct mlx5_wqe_data_seg); 655 props->max_sge = min(max_rq_sg, max_sq_sg); 656 props->max_sge_rd = MLX5_MAX_SGE_RD; 657 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 658 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 659 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 660 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 661 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 662 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 663 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 664 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 665 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 666 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 667 props->max_srq_sge = max_rq_sg - 1; 668 props->max_fast_reg_page_list_len = 669 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 670 get_atomic_caps(dev, props); 671 props->masked_atomic_cap = IB_ATOMIC_NONE; 672 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 673 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 674 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 675 props->max_mcast_grp; 676 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 677 props->max_ah = INT_MAX; 678 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 679 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 680 681 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 682 if (MLX5_CAP_GEN(mdev, pg)) 683 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 684 props->odp_caps = dev->odp_caps; 685 #endif 686 687 if (MLX5_CAP_GEN(mdev, cd)) 688 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 689 690 if (!mlx5_core_is_pf(mdev)) 691 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 692 693 if (mlx5_ib_port_link_layer(ibdev, 1) == 694 IB_LINK_LAYER_ETHERNET) { 695 props->rss_caps.max_rwq_indirection_tables = 696 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 697 props->rss_caps.max_rwq_indirection_table_size = 698 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 699 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 700 props->max_wq_type_rq = 701 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 702 } 703 704 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 705 resp.cqe_comp_caps.max_num = 706 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 707 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 708 resp.cqe_comp_caps.supported_format = 709 MLX5_IB_CQE_RES_FORMAT_HASH | 710 MLX5_IB_CQE_RES_FORMAT_CSUM; 711 resp.response_length += sizeof(resp.cqe_comp_caps); 712 } 713 714 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 715 if (MLX5_CAP_QOS(mdev, packet_pacing) && 716 MLX5_CAP_GEN(mdev, qos)) { 717 resp.packet_pacing_caps.qp_rate_limit_max = 718 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 719 resp.packet_pacing_caps.qp_rate_limit_min = 720 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 721 resp.packet_pacing_caps.supported_qpts |= 722 1 << IB_QPT_RAW_PACKET; 723 } 724 resp.response_length += sizeof(resp.packet_pacing_caps); 725 } 726 727 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 728 uhw->outlen)) { 729 resp.mlx5_ib_support_multi_pkt_send_wqes = 730 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 731 resp.response_length += 732 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 733 } 734 735 if (field_avail(typeof(resp), reserved, uhw->outlen)) 736 resp.response_length += sizeof(resp.reserved); 737 738 if (uhw->outlen) { 739 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 740 741 if (err) 742 return err; 743 } 744 745 return 0; 746 } 747 748 enum mlx5_ib_width { 749 MLX5_IB_WIDTH_1X = 1 << 0, 750 MLX5_IB_WIDTH_2X = 1 << 1, 751 MLX5_IB_WIDTH_4X = 1 << 2, 752 MLX5_IB_WIDTH_8X = 1 << 3, 753 MLX5_IB_WIDTH_12X = 1 << 4 754 }; 755 756 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 757 u8 *ib_width) 758 { 759 struct mlx5_ib_dev *dev = to_mdev(ibdev); 760 int err = 0; 761 762 if (active_width & MLX5_IB_WIDTH_1X) { 763 *ib_width = IB_WIDTH_1X; 764 } else if (active_width & MLX5_IB_WIDTH_2X) { 765 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 766 (int)active_width); 767 err = -EINVAL; 768 } else if (active_width & MLX5_IB_WIDTH_4X) { 769 *ib_width = IB_WIDTH_4X; 770 } else if (active_width & MLX5_IB_WIDTH_8X) { 771 *ib_width = IB_WIDTH_8X; 772 } else if (active_width & MLX5_IB_WIDTH_12X) { 773 *ib_width = IB_WIDTH_12X; 774 } else { 775 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 776 (int)active_width); 777 err = -EINVAL; 778 } 779 780 return err; 781 } 782 783 static int mlx5_mtu_to_ib_mtu(int mtu) 784 { 785 switch (mtu) { 786 case 256: return 1; 787 case 512: return 2; 788 case 1024: return 3; 789 case 2048: return 4; 790 case 4096: return 5; 791 default: 792 pr_warn("invalid mtu\n"); 793 return -1; 794 } 795 } 796 797 enum ib_max_vl_num { 798 __IB_MAX_VL_0 = 1, 799 __IB_MAX_VL_0_1 = 2, 800 __IB_MAX_VL_0_3 = 3, 801 __IB_MAX_VL_0_7 = 4, 802 __IB_MAX_VL_0_14 = 5, 803 }; 804 805 enum mlx5_vl_hw_cap { 806 MLX5_VL_HW_0 = 1, 807 MLX5_VL_HW_0_1 = 2, 808 MLX5_VL_HW_0_2 = 3, 809 MLX5_VL_HW_0_3 = 4, 810 MLX5_VL_HW_0_4 = 5, 811 MLX5_VL_HW_0_5 = 6, 812 MLX5_VL_HW_0_6 = 7, 813 MLX5_VL_HW_0_7 = 8, 814 MLX5_VL_HW_0_14 = 15 815 }; 816 817 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 818 u8 *max_vl_num) 819 { 820 switch (vl_hw_cap) { 821 case MLX5_VL_HW_0: 822 *max_vl_num = __IB_MAX_VL_0; 823 break; 824 case MLX5_VL_HW_0_1: 825 *max_vl_num = __IB_MAX_VL_0_1; 826 break; 827 case MLX5_VL_HW_0_3: 828 *max_vl_num = __IB_MAX_VL_0_3; 829 break; 830 case MLX5_VL_HW_0_7: 831 *max_vl_num = __IB_MAX_VL_0_7; 832 break; 833 case MLX5_VL_HW_0_14: 834 *max_vl_num = __IB_MAX_VL_0_14; 835 break; 836 837 default: 838 return -EINVAL; 839 } 840 841 return 0; 842 } 843 844 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 845 struct ib_port_attr *props) 846 { 847 struct mlx5_ib_dev *dev = to_mdev(ibdev); 848 struct mlx5_core_dev *mdev = dev->mdev; 849 struct mlx5_hca_vport_context *rep; 850 u16 max_mtu; 851 u16 oper_mtu; 852 int err; 853 u8 ib_link_width_oper; 854 u8 vl_hw_cap; 855 856 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 857 if (!rep) { 858 err = -ENOMEM; 859 goto out; 860 } 861 862 /* props being zeroed by the caller, avoid zeroing it here */ 863 864 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 865 if (err) 866 goto out; 867 868 props->lid = rep->lid; 869 props->lmc = rep->lmc; 870 props->sm_lid = rep->sm_lid; 871 props->sm_sl = rep->sm_sl; 872 props->state = rep->vport_state; 873 props->phys_state = rep->port_physical_state; 874 props->port_cap_flags = rep->cap_mask1; 875 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 876 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 877 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 878 props->bad_pkey_cntr = rep->pkey_violation_counter; 879 props->qkey_viol_cntr = rep->qkey_violation_counter; 880 props->subnet_timeout = rep->subnet_timeout; 881 props->init_type_reply = rep->init_type_reply; 882 props->grh_required = rep->grh_required; 883 884 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 885 if (err) 886 goto out; 887 888 err = translate_active_width(ibdev, ib_link_width_oper, 889 &props->active_width); 890 if (err) 891 goto out; 892 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 893 if (err) 894 goto out; 895 896 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 897 898 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 899 900 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 901 902 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 903 904 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 905 if (err) 906 goto out; 907 908 err = translate_max_vl_num(ibdev, vl_hw_cap, 909 &props->max_vl_num); 910 out: 911 kfree(rep); 912 return err; 913 } 914 915 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 916 struct ib_port_attr *props) 917 { 918 switch (mlx5_get_vport_access_method(ibdev)) { 919 case MLX5_VPORT_ACCESS_METHOD_MAD: 920 return mlx5_query_mad_ifc_port(ibdev, port, props); 921 922 case MLX5_VPORT_ACCESS_METHOD_HCA: 923 return mlx5_query_hca_port(ibdev, port, props); 924 925 case MLX5_VPORT_ACCESS_METHOD_NIC: 926 return mlx5_query_port_roce(ibdev, port, props); 927 928 default: 929 return -EINVAL; 930 } 931 } 932 933 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 934 union ib_gid *gid) 935 { 936 struct mlx5_ib_dev *dev = to_mdev(ibdev); 937 struct mlx5_core_dev *mdev = dev->mdev; 938 939 switch (mlx5_get_vport_access_method(ibdev)) { 940 case MLX5_VPORT_ACCESS_METHOD_MAD: 941 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 942 943 case MLX5_VPORT_ACCESS_METHOD_HCA: 944 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 945 946 default: 947 return -EINVAL; 948 } 949 950 } 951 952 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 953 u16 *pkey) 954 { 955 struct mlx5_ib_dev *dev = to_mdev(ibdev); 956 struct mlx5_core_dev *mdev = dev->mdev; 957 958 switch (mlx5_get_vport_access_method(ibdev)) { 959 case MLX5_VPORT_ACCESS_METHOD_MAD: 960 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 961 962 case MLX5_VPORT_ACCESS_METHOD_HCA: 963 case MLX5_VPORT_ACCESS_METHOD_NIC: 964 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 965 pkey); 966 default: 967 return -EINVAL; 968 } 969 } 970 971 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 972 struct ib_device_modify *props) 973 { 974 struct mlx5_ib_dev *dev = to_mdev(ibdev); 975 struct mlx5_reg_node_desc in; 976 struct mlx5_reg_node_desc out; 977 int err; 978 979 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 980 return -EOPNOTSUPP; 981 982 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 983 return 0; 984 985 /* 986 * If possible, pass node desc to FW, so it can generate 987 * a 144 trap. If cmd fails, just ignore. 988 */ 989 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 990 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 991 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 992 if (err) 993 return err; 994 995 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 996 997 return err; 998 } 999 1000 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1001 u32 value) 1002 { 1003 struct mlx5_hca_vport_context ctx = {}; 1004 int err; 1005 1006 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1007 port_num, 0, &ctx); 1008 if (err) 1009 return err; 1010 1011 if (~ctx.cap_mask1_perm & mask) { 1012 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1013 mask, ctx.cap_mask1_perm); 1014 return -EINVAL; 1015 } 1016 1017 ctx.cap_mask1 = value; 1018 ctx.cap_mask1_perm = mask; 1019 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1020 port_num, 0, &ctx); 1021 1022 return err; 1023 } 1024 1025 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1026 struct ib_port_modify *props) 1027 { 1028 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1029 struct ib_port_attr attr; 1030 u32 tmp; 1031 int err; 1032 u32 change_mask; 1033 u32 value; 1034 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1035 IB_LINK_LAYER_INFINIBAND); 1036 1037 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1038 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1039 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1040 return set_port_caps_atomic(dev, port, change_mask, value); 1041 } 1042 1043 mutex_lock(&dev->cap_mask_mutex); 1044 1045 err = ib_query_port(ibdev, port, &attr); 1046 if (err) 1047 goto out; 1048 1049 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1050 ~props->clr_port_cap_mask; 1051 1052 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1053 1054 out: 1055 mutex_unlock(&dev->cap_mask_mutex); 1056 return err; 1057 } 1058 1059 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1060 { 1061 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1062 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1063 } 1064 1065 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1066 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1067 u32 *num_sys_pages) 1068 { 1069 int uars_per_sys_page; 1070 int bfregs_per_sys_page; 1071 int ref_bfregs = req->total_num_bfregs; 1072 1073 if (req->total_num_bfregs == 0) 1074 return -EINVAL; 1075 1076 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1077 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1078 1079 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1080 return -ENOMEM; 1081 1082 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1083 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1084 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1085 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1086 1087 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1088 return -EINVAL; 1089 1090 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n", 1091 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1092 lib_uar_4k ? "yes" : "no", ref_bfregs, 1093 req->total_num_bfregs, *num_sys_pages); 1094 1095 return 0; 1096 } 1097 1098 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1099 { 1100 struct mlx5_bfreg_info *bfregi; 1101 int err; 1102 int i; 1103 1104 bfregi = &context->bfregi; 1105 for (i = 0; i < bfregi->num_sys_pages; i++) { 1106 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1107 if (err) 1108 goto error; 1109 1110 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1111 } 1112 return 0; 1113 1114 error: 1115 for (--i; i >= 0; i--) 1116 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1117 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1118 1119 return err; 1120 } 1121 1122 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1123 { 1124 struct mlx5_bfreg_info *bfregi; 1125 int err; 1126 int i; 1127 1128 bfregi = &context->bfregi; 1129 for (i = 0; i < bfregi->num_sys_pages; i++) { 1130 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1131 if (err) { 1132 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1133 return err; 1134 } 1135 } 1136 return 0; 1137 } 1138 1139 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1140 struct ib_udata *udata) 1141 { 1142 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1143 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1144 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1145 struct mlx5_ib_ucontext *context; 1146 struct mlx5_bfreg_info *bfregi; 1147 int ver; 1148 int err; 1149 size_t reqlen; 1150 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1151 max_cqe_version); 1152 bool lib_uar_4k; 1153 1154 if (!dev->ib_active) 1155 return ERR_PTR(-EAGAIN); 1156 1157 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1158 return ERR_PTR(-EINVAL); 1159 1160 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1161 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1162 ver = 0; 1163 else if (reqlen >= min_req_v2) 1164 ver = 2; 1165 else 1166 return ERR_PTR(-EINVAL); 1167 1168 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1169 if (err) 1170 return ERR_PTR(err); 1171 1172 if (req.flags) 1173 return ERR_PTR(-EINVAL); 1174 1175 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1176 return ERR_PTR(-EOPNOTSUPP); 1177 1178 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1179 MLX5_NON_FP_BFREGS_PER_UAR); 1180 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1181 return ERR_PTR(-EINVAL); 1182 1183 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1184 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1185 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1186 resp.cache_line_size = cache_line_size(); 1187 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1188 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1189 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1190 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1191 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1192 resp.cqe_version = min_t(__u8, 1193 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1194 req.max_cqe_version); 1195 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1196 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1197 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1198 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1199 resp.response_length = min(offsetof(typeof(resp), response_length) + 1200 sizeof(resp.response_length), udata->outlen); 1201 1202 context = kzalloc(sizeof(*context), GFP_KERNEL); 1203 if (!context) 1204 return ERR_PTR(-ENOMEM); 1205 1206 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1207 bfregi = &context->bfregi; 1208 1209 /* updates req->total_num_bfregs */ 1210 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1211 if (err) 1212 goto out_ctx; 1213 1214 mutex_init(&bfregi->lock); 1215 bfregi->lib_uar_4k = lib_uar_4k; 1216 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1217 GFP_KERNEL); 1218 if (!bfregi->count) { 1219 err = -ENOMEM; 1220 goto out_ctx; 1221 } 1222 1223 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1224 sizeof(*bfregi->sys_pages), 1225 GFP_KERNEL); 1226 if (!bfregi->sys_pages) { 1227 err = -ENOMEM; 1228 goto out_count; 1229 } 1230 1231 err = allocate_uars(dev, context); 1232 if (err) 1233 goto out_sys_pages; 1234 1235 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1236 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1237 #endif 1238 1239 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1240 if (!context->upd_xlt_page) { 1241 err = -ENOMEM; 1242 goto out_uars; 1243 } 1244 mutex_init(&context->upd_xlt_page_mutex); 1245 1246 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1247 err = mlx5_core_alloc_transport_domain(dev->mdev, 1248 &context->tdn); 1249 if (err) 1250 goto out_page; 1251 } 1252 1253 INIT_LIST_HEAD(&context->vma_private_list); 1254 INIT_LIST_HEAD(&context->db_page_list); 1255 mutex_init(&context->db_page_mutex); 1256 1257 resp.tot_bfregs = req.total_num_bfregs; 1258 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1259 1260 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1261 resp.response_length += sizeof(resp.cqe_version); 1262 1263 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1264 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1265 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1266 resp.response_length += sizeof(resp.cmds_supp_uhw); 1267 } 1268 1269 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1270 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1271 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1272 resp.eth_min_inline++; 1273 } 1274 resp.response_length += sizeof(resp.eth_min_inline); 1275 } 1276 1277 /* 1278 * We don't want to expose information from the PCI bar that is located 1279 * after 4096 bytes, so if the arch only supports larger pages, let's 1280 * pretend we don't support reading the HCA's core clock. This is also 1281 * forced by mmap function. 1282 */ 1283 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1284 if (PAGE_SIZE <= 4096) { 1285 resp.comp_mask |= 1286 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1287 resp.hca_core_clock_offset = 1288 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1289 } 1290 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1291 sizeof(resp.reserved2); 1292 } 1293 1294 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1295 resp.response_length += sizeof(resp.log_uar_size); 1296 1297 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1298 resp.response_length += sizeof(resp.num_uars_per_page); 1299 1300 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1301 if (err) 1302 goto out_td; 1303 1304 bfregi->ver = ver; 1305 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1306 context->cqe_version = resp.cqe_version; 1307 context->lib_caps = req.lib_caps; 1308 print_lib_caps(dev, context->lib_caps); 1309 1310 return &context->ibucontext; 1311 1312 out_td: 1313 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1314 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1315 1316 out_page: 1317 free_page(context->upd_xlt_page); 1318 1319 out_uars: 1320 deallocate_uars(dev, context); 1321 1322 out_sys_pages: 1323 kfree(bfregi->sys_pages); 1324 1325 out_count: 1326 kfree(bfregi->count); 1327 1328 out_ctx: 1329 kfree(context); 1330 1331 return ERR_PTR(err); 1332 } 1333 1334 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1335 { 1336 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1337 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1338 struct mlx5_bfreg_info *bfregi; 1339 1340 bfregi = &context->bfregi; 1341 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1342 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1343 1344 free_page(context->upd_xlt_page); 1345 deallocate_uars(dev, context); 1346 kfree(bfregi->sys_pages); 1347 kfree(bfregi->count); 1348 kfree(context); 1349 1350 return 0; 1351 } 1352 1353 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1354 struct mlx5_bfreg_info *bfregi, 1355 int idx) 1356 { 1357 int fw_uars_per_page; 1358 1359 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1360 1361 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1362 bfregi->sys_pages[idx] / fw_uars_per_page; 1363 } 1364 1365 static int get_command(unsigned long offset) 1366 { 1367 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1368 } 1369 1370 static int get_arg(unsigned long offset) 1371 { 1372 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1373 } 1374 1375 static int get_index(unsigned long offset) 1376 { 1377 return get_arg(offset); 1378 } 1379 1380 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1381 { 1382 /* vma_open is called when a new VMA is created on top of our VMA. This 1383 * is done through either mremap flow or split_vma (usually due to 1384 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1385 * as this VMA is strongly hardware related. Therefore we set the 1386 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1387 * calling us again and trying to do incorrect actions. We assume that 1388 * the original VMA size is exactly a single page, and therefore all 1389 * "splitting" operation will not happen to it. 1390 */ 1391 area->vm_ops = NULL; 1392 } 1393 1394 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1395 { 1396 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1397 1398 /* It's guaranteed that all VMAs opened on a FD are closed before the 1399 * file itself is closed, therefore no sync is needed with the regular 1400 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1401 * However need a sync with accessing the vma as part of 1402 * mlx5_ib_disassociate_ucontext. 1403 * The close operation is usually called under mm->mmap_sem except when 1404 * process is exiting. 1405 * The exiting case is handled explicitly as part of 1406 * mlx5_ib_disassociate_ucontext. 1407 */ 1408 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1409 1410 /* setting the vma context pointer to null in the mlx5_ib driver's 1411 * private data, to protect a race condition in 1412 * mlx5_ib_disassociate_ucontext(). 1413 */ 1414 mlx5_ib_vma_priv_data->vma = NULL; 1415 list_del(&mlx5_ib_vma_priv_data->list); 1416 kfree(mlx5_ib_vma_priv_data); 1417 } 1418 1419 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1420 .open = mlx5_ib_vma_open, 1421 .close = mlx5_ib_vma_close 1422 }; 1423 1424 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1425 struct mlx5_ib_ucontext *ctx) 1426 { 1427 struct mlx5_ib_vma_private_data *vma_prv; 1428 struct list_head *vma_head = &ctx->vma_private_list; 1429 1430 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1431 if (!vma_prv) 1432 return -ENOMEM; 1433 1434 vma_prv->vma = vma; 1435 vma->vm_private_data = vma_prv; 1436 vma->vm_ops = &mlx5_ib_vm_ops; 1437 1438 list_add(&vma_prv->list, vma_head); 1439 1440 return 0; 1441 } 1442 1443 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1444 { 1445 int ret; 1446 struct vm_area_struct *vma; 1447 struct mlx5_ib_vma_private_data *vma_private, *n; 1448 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1449 struct task_struct *owning_process = NULL; 1450 struct mm_struct *owning_mm = NULL; 1451 1452 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1453 if (!owning_process) 1454 return; 1455 1456 owning_mm = get_task_mm(owning_process); 1457 if (!owning_mm) { 1458 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1459 while (1) { 1460 put_task_struct(owning_process); 1461 usleep_range(1000, 2000); 1462 owning_process = get_pid_task(ibcontext->tgid, 1463 PIDTYPE_PID); 1464 if (!owning_process || 1465 owning_process->state == TASK_DEAD) { 1466 pr_info("disassociate ucontext done, task was terminated\n"); 1467 /* in case task was dead need to release the 1468 * task struct. 1469 */ 1470 if (owning_process) 1471 put_task_struct(owning_process); 1472 return; 1473 } 1474 } 1475 } 1476 1477 /* need to protect from a race on closing the vma as part of 1478 * mlx5_ib_vma_close. 1479 */ 1480 down_read(&owning_mm->mmap_sem); 1481 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1482 list) { 1483 vma = vma_private->vma; 1484 ret = zap_vma_ptes(vma, vma->vm_start, 1485 PAGE_SIZE); 1486 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1487 /* context going to be destroyed, should 1488 * not access ops any more. 1489 */ 1490 vma->vm_ops = NULL; 1491 list_del(&vma_private->list); 1492 kfree(vma_private); 1493 } 1494 up_read(&owning_mm->mmap_sem); 1495 mmput(owning_mm); 1496 put_task_struct(owning_process); 1497 } 1498 1499 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1500 { 1501 switch (cmd) { 1502 case MLX5_IB_MMAP_WC_PAGE: 1503 return "WC"; 1504 case MLX5_IB_MMAP_REGULAR_PAGE: 1505 return "best effort WC"; 1506 case MLX5_IB_MMAP_NC_PAGE: 1507 return "NC"; 1508 default: 1509 return NULL; 1510 } 1511 } 1512 1513 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1514 struct vm_area_struct *vma, 1515 struct mlx5_ib_ucontext *context) 1516 { 1517 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1518 int err; 1519 unsigned long idx; 1520 phys_addr_t pfn, pa; 1521 pgprot_t prot; 1522 int uars_per_page; 1523 1524 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1525 return -EINVAL; 1526 1527 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1528 idx = get_index(vma->vm_pgoff); 1529 if (idx % uars_per_page || 1530 idx * uars_per_page >= bfregi->num_sys_pages) { 1531 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1532 return -EINVAL; 1533 } 1534 1535 switch (cmd) { 1536 case MLX5_IB_MMAP_WC_PAGE: 1537 /* Some architectures don't support WC memory */ 1538 #if defined(CONFIG_X86) 1539 if (!pat_enabled()) 1540 return -EPERM; 1541 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1542 return -EPERM; 1543 #endif 1544 /* fall through */ 1545 case MLX5_IB_MMAP_REGULAR_PAGE: 1546 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1547 prot = pgprot_writecombine(vma->vm_page_prot); 1548 break; 1549 case MLX5_IB_MMAP_NC_PAGE: 1550 prot = pgprot_noncached(vma->vm_page_prot); 1551 break; 1552 default: 1553 return -EINVAL; 1554 } 1555 1556 pfn = uar_index2pfn(dev, bfregi, idx); 1557 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1558 1559 vma->vm_page_prot = prot; 1560 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1561 PAGE_SIZE, vma->vm_page_prot); 1562 if (err) { 1563 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1564 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1565 return -EAGAIN; 1566 } 1567 1568 pa = pfn << PAGE_SHIFT; 1569 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1570 vma->vm_start, &pa); 1571 1572 return mlx5_ib_set_vma_data(vma, context); 1573 } 1574 1575 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1576 { 1577 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1578 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1579 unsigned long command; 1580 phys_addr_t pfn; 1581 1582 command = get_command(vma->vm_pgoff); 1583 switch (command) { 1584 case MLX5_IB_MMAP_WC_PAGE: 1585 case MLX5_IB_MMAP_NC_PAGE: 1586 case MLX5_IB_MMAP_REGULAR_PAGE: 1587 return uar_mmap(dev, command, vma, context); 1588 1589 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1590 return -ENOSYS; 1591 1592 case MLX5_IB_MMAP_CORE_CLOCK: 1593 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1594 return -EINVAL; 1595 1596 if (vma->vm_flags & VM_WRITE) 1597 return -EPERM; 1598 1599 /* Don't expose to user-space information it shouldn't have */ 1600 if (PAGE_SIZE > 4096) 1601 return -EOPNOTSUPP; 1602 1603 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1604 pfn = (dev->mdev->iseg_base + 1605 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1606 PAGE_SHIFT; 1607 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1608 PAGE_SIZE, vma->vm_page_prot)) 1609 return -EAGAIN; 1610 1611 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1612 vma->vm_start, 1613 (unsigned long long)pfn << PAGE_SHIFT); 1614 break; 1615 1616 default: 1617 return -EINVAL; 1618 } 1619 1620 return 0; 1621 } 1622 1623 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1624 struct ib_ucontext *context, 1625 struct ib_udata *udata) 1626 { 1627 struct mlx5_ib_alloc_pd_resp resp; 1628 struct mlx5_ib_pd *pd; 1629 int err; 1630 1631 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1632 if (!pd) 1633 return ERR_PTR(-ENOMEM); 1634 1635 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1636 if (err) { 1637 kfree(pd); 1638 return ERR_PTR(err); 1639 } 1640 1641 if (context) { 1642 resp.pdn = pd->pdn; 1643 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1644 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1645 kfree(pd); 1646 return ERR_PTR(-EFAULT); 1647 } 1648 } 1649 1650 return &pd->ibpd; 1651 } 1652 1653 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1654 { 1655 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1656 struct mlx5_ib_pd *mpd = to_mpd(pd); 1657 1658 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1659 kfree(mpd); 1660 1661 return 0; 1662 } 1663 1664 enum { 1665 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1666 MATCH_CRITERIA_ENABLE_MISC_BIT, 1667 MATCH_CRITERIA_ENABLE_INNER_BIT 1668 }; 1669 1670 #define HEADER_IS_ZERO(match_criteria, headers) \ 1671 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1672 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1673 1674 static u8 get_match_criteria_enable(u32 *match_criteria) 1675 { 1676 u8 match_criteria_enable; 1677 1678 match_criteria_enable = 1679 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1680 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1681 match_criteria_enable |= 1682 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1683 MATCH_CRITERIA_ENABLE_MISC_BIT; 1684 match_criteria_enable |= 1685 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1686 MATCH_CRITERIA_ENABLE_INNER_BIT; 1687 1688 return match_criteria_enable; 1689 } 1690 1691 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1692 { 1693 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1694 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1695 } 1696 1697 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1698 bool inner) 1699 { 1700 if (inner) { 1701 MLX5_SET(fte_match_set_misc, 1702 misc_c, inner_ipv6_flow_label, mask); 1703 MLX5_SET(fte_match_set_misc, 1704 misc_v, inner_ipv6_flow_label, val); 1705 } else { 1706 MLX5_SET(fte_match_set_misc, 1707 misc_c, outer_ipv6_flow_label, mask); 1708 MLX5_SET(fte_match_set_misc, 1709 misc_v, outer_ipv6_flow_label, val); 1710 } 1711 } 1712 1713 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1714 { 1715 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1716 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1717 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1718 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1719 } 1720 1721 #define LAST_ETH_FIELD vlan_tag 1722 #define LAST_IB_FIELD sl 1723 #define LAST_IPV4_FIELD tos 1724 #define LAST_IPV6_FIELD traffic_class 1725 #define LAST_TCP_UDP_FIELD src_port 1726 #define LAST_TUNNEL_FIELD tunnel_id 1727 #define LAST_FLOW_TAG_FIELD tag_id 1728 1729 /* Field is the last supported field */ 1730 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1731 memchr_inv((void *)&filter.field +\ 1732 sizeof(filter.field), 0,\ 1733 sizeof(filter) -\ 1734 offsetof(typeof(filter), field) -\ 1735 sizeof(filter.field)) 1736 1737 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1738 const union ib_flow_spec *ib_spec, u32 *tag_id) 1739 { 1740 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1741 misc_parameters); 1742 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1743 misc_parameters); 1744 void *headers_c; 1745 void *headers_v; 1746 1747 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1748 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1749 inner_headers); 1750 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1751 inner_headers); 1752 } else { 1753 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1754 outer_headers); 1755 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1756 outer_headers); 1757 } 1758 1759 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1760 case IB_FLOW_SPEC_ETH: 1761 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1762 return -EOPNOTSUPP; 1763 1764 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1765 dmac_47_16), 1766 ib_spec->eth.mask.dst_mac); 1767 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1768 dmac_47_16), 1769 ib_spec->eth.val.dst_mac); 1770 1771 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1772 smac_47_16), 1773 ib_spec->eth.mask.src_mac); 1774 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1775 smac_47_16), 1776 ib_spec->eth.val.src_mac); 1777 1778 if (ib_spec->eth.mask.vlan_tag) { 1779 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1780 cvlan_tag, 1); 1781 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1782 cvlan_tag, 1); 1783 1784 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1785 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1787 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1788 1789 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1790 first_cfi, 1791 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1792 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1793 first_cfi, 1794 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1795 1796 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1797 first_prio, 1798 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1799 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1800 first_prio, 1801 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1802 } 1803 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1804 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1805 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1806 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1807 break; 1808 case IB_FLOW_SPEC_IPV4: 1809 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1810 return -EOPNOTSUPP; 1811 1812 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1813 ethertype, 0xffff); 1814 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1815 ethertype, ETH_P_IP); 1816 1817 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1818 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1819 &ib_spec->ipv4.mask.src_ip, 1820 sizeof(ib_spec->ipv4.mask.src_ip)); 1821 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1822 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1823 &ib_spec->ipv4.val.src_ip, 1824 sizeof(ib_spec->ipv4.val.src_ip)); 1825 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1826 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1827 &ib_spec->ipv4.mask.dst_ip, 1828 sizeof(ib_spec->ipv4.mask.dst_ip)); 1829 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1830 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1831 &ib_spec->ipv4.val.dst_ip, 1832 sizeof(ib_spec->ipv4.val.dst_ip)); 1833 1834 set_tos(headers_c, headers_v, 1835 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1836 1837 set_proto(headers_c, headers_v, 1838 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1839 break; 1840 case IB_FLOW_SPEC_IPV6: 1841 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1842 return -EOPNOTSUPP; 1843 1844 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1845 ethertype, 0xffff); 1846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1847 ethertype, ETH_P_IPV6); 1848 1849 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1850 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1851 &ib_spec->ipv6.mask.src_ip, 1852 sizeof(ib_spec->ipv6.mask.src_ip)); 1853 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1854 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1855 &ib_spec->ipv6.val.src_ip, 1856 sizeof(ib_spec->ipv6.val.src_ip)); 1857 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1858 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1859 &ib_spec->ipv6.mask.dst_ip, 1860 sizeof(ib_spec->ipv6.mask.dst_ip)); 1861 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1862 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1863 &ib_spec->ipv6.val.dst_ip, 1864 sizeof(ib_spec->ipv6.val.dst_ip)); 1865 1866 set_tos(headers_c, headers_v, 1867 ib_spec->ipv6.mask.traffic_class, 1868 ib_spec->ipv6.val.traffic_class); 1869 1870 set_proto(headers_c, headers_v, 1871 ib_spec->ipv6.mask.next_hdr, 1872 ib_spec->ipv6.val.next_hdr); 1873 1874 set_flow_label(misc_params_c, misc_params_v, 1875 ntohl(ib_spec->ipv6.mask.flow_label), 1876 ntohl(ib_spec->ipv6.val.flow_label), 1877 ib_spec->type & IB_FLOW_SPEC_INNER); 1878 1879 break; 1880 case IB_FLOW_SPEC_TCP: 1881 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1882 LAST_TCP_UDP_FIELD)) 1883 return -EOPNOTSUPP; 1884 1885 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1886 0xff); 1887 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1888 IPPROTO_TCP); 1889 1890 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 1891 ntohs(ib_spec->tcp_udp.mask.src_port)); 1892 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 1893 ntohs(ib_spec->tcp_udp.val.src_port)); 1894 1895 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 1896 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1897 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 1898 ntohs(ib_spec->tcp_udp.val.dst_port)); 1899 break; 1900 case IB_FLOW_SPEC_UDP: 1901 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1902 LAST_TCP_UDP_FIELD)) 1903 return -EOPNOTSUPP; 1904 1905 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1906 0xff); 1907 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1908 IPPROTO_UDP); 1909 1910 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 1911 ntohs(ib_spec->tcp_udp.mask.src_port)); 1912 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 1913 ntohs(ib_spec->tcp_udp.val.src_port)); 1914 1915 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 1916 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 1918 ntohs(ib_spec->tcp_udp.val.dst_port)); 1919 break; 1920 case IB_FLOW_SPEC_VXLAN_TUNNEL: 1921 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 1922 LAST_TUNNEL_FIELD)) 1923 return -EOPNOTSUPP; 1924 1925 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 1926 ntohl(ib_spec->tunnel.mask.tunnel_id)); 1927 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 1928 ntohl(ib_spec->tunnel.val.tunnel_id)); 1929 break; 1930 case IB_FLOW_SPEC_ACTION_TAG: 1931 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 1932 LAST_FLOW_TAG_FIELD)) 1933 return -EOPNOTSUPP; 1934 if (ib_spec->flow_tag.tag_id >= BIT(24)) 1935 return -EINVAL; 1936 1937 *tag_id = ib_spec->flow_tag.tag_id; 1938 break; 1939 default: 1940 return -EINVAL; 1941 } 1942 1943 return 0; 1944 } 1945 1946 /* If a flow could catch both multicast and unicast packets, 1947 * it won't fall into the multicast flow steering table and this rule 1948 * could steal other multicast packets. 1949 */ 1950 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1951 { 1952 struct ib_flow_spec_eth *eth_spec; 1953 1954 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1955 ib_attr->size < sizeof(struct ib_flow_attr) + 1956 sizeof(struct ib_flow_spec_eth) || 1957 ib_attr->num_of_specs < 1) 1958 return false; 1959 1960 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1961 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1962 eth_spec->size != sizeof(*eth_spec)) 1963 return false; 1964 1965 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1966 is_multicast_ether_addr(eth_spec->val.dst_mac); 1967 } 1968 1969 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1970 { 1971 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1972 bool has_ipv4_spec = false; 1973 bool eth_type_ipv4 = true; 1974 unsigned int spec_index; 1975 1976 /* Validate that ethertype is correct */ 1977 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1978 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1979 ib_spec->eth.mask.ether_type) { 1980 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1981 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1982 eth_type_ipv4 = false; 1983 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1984 has_ipv4_spec = true; 1985 } 1986 ib_spec = (void *)ib_spec + ib_spec->size; 1987 } 1988 return !has_ipv4_spec || eth_type_ipv4; 1989 } 1990 1991 static void put_flow_table(struct mlx5_ib_dev *dev, 1992 struct mlx5_ib_flow_prio *prio, bool ft_added) 1993 { 1994 prio->refcount -= !!ft_added; 1995 if (!prio->refcount) { 1996 mlx5_destroy_flow_table(prio->flow_table); 1997 prio->flow_table = NULL; 1998 } 1999 } 2000 2001 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2002 { 2003 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2004 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2005 struct mlx5_ib_flow_handler, 2006 ibflow); 2007 struct mlx5_ib_flow_handler *iter, *tmp; 2008 2009 mutex_lock(&dev->flow_db.lock); 2010 2011 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2012 mlx5_del_flow_rules(iter->rule); 2013 put_flow_table(dev, iter->prio, true); 2014 list_del(&iter->list); 2015 kfree(iter); 2016 } 2017 2018 mlx5_del_flow_rules(handler->rule); 2019 put_flow_table(dev, handler->prio, true); 2020 mutex_unlock(&dev->flow_db.lock); 2021 2022 kfree(handler); 2023 2024 return 0; 2025 } 2026 2027 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2028 { 2029 priority *= 2; 2030 if (!dont_trap) 2031 priority++; 2032 return priority; 2033 } 2034 2035 enum flow_table_type { 2036 MLX5_IB_FT_RX, 2037 MLX5_IB_FT_TX 2038 }; 2039 2040 #define MLX5_FS_MAX_TYPES 10 2041 #define MLX5_FS_MAX_ENTRIES 32000UL 2042 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2043 struct ib_flow_attr *flow_attr, 2044 enum flow_table_type ft_type) 2045 { 2046 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2047 struct mlx5_flow_namespace *ns = NULL; 2048 struct mlx5_ib_flow_prio *prio; 2049 struct mlx5_flow_table *ft; 2050 int num_entries; 2051 int num_groups; 2052 int priority; 2053 int err = 0; 2054 2055 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2056 if (flow_is_multicast_only(flow_attr) && 2057 !dont_trap) 2058 priority = MLX5_IB_FLOW_MCAST_PRIO; 2059 else 2060 priority = ib_prio_to_core_prio(flow_attr->priority, 2061 dont_trap); 2062 ns = mlx5_get_flow_namespace(dev->mdev, 2063 MLX5_FLOW_NAMESPACE_BYPASS); 2064 num_entries = MLX5_FS_MAX_ENTRIES; 2065 num_groups = MLX5_FS_MAX_TYPES; 2066 prio = &dev->flow_db.prios[priority]; 2067 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2068 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2069 ns = mlx5_get_flow_namespace(dev->mdev, 2070 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2071 build_leftovers_ft_param(&priority, 2072 &num_entries, 2073 &num_groups); 2074 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2075 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2076 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2077 allow_sniffer_and_nic_rx_shared_tir)) 2078 return ERR_PTR(-ENOTSUPP); 2079 2080 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2081 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2082 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2083 2084 prio = &dev->flow_db.sniffer[ft_type]; 2085 priority = 0; 2086 num_entries = 1; 2087 num_groups = 1; 2088 } 2089 2090 if (!ns) 2091 return ERR_PTR(-ENOTSUPP); 2092 2093 ft = prio->flow_table; 2094 if (!ft) { 2095 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2096 num_entries, 2097 num_groups, 2098 0, 0); 2099 2100 if (!IS_ERR(ft)) { 2101 prio->refcount = 0; 2102 prio->flow_table = ft; 2103 } else { 2104 err = PTR_ERR(ft); 2105 } 2106 } 2107 2108 return err ? ERR_PTR(err) : prio; 2109 } 2110 2111 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2112 struct mlx5_ib_flow_prio *ft_prio, 2113 const struct ib_flow_attr *flow_attr, 2114 struct mlx5_flow_destination *dst) 2115 { 2116 struct mlx5_flow_table *ft = ft_prio->flow_table; 2117 struct mlx5_ib_flow_handler *handler; 2118 struct mlx5_flow_act flow_act = {0}; 2119 struct mlx5_flow_spec *spec; 2120 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2121 unsigned int spec_index; 2122 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2123 int err = 0; 2124 2125 if (!is_valid_attr(flow_attr)) 2126 return ERR_PTR(-EINVAL); 2127 2128 spec = mlx5_vzalloc(sizeof(*spec)); 2129 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2130 if (!handler || !spec) { 2131 err = -ENOMEM; 2132 goto free; 2133 } 2134 2135 INIT_LIST_HEAD(&handler->list); 2136 2137 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2138 err = parse_flow_attr(spec->match_criteria, 2139 spec->match_value, ib_flow, &flow_tag); 2140 if (err < 0) 2141 goto free; 2142 2143 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2144 } 2145 2146 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2147 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2148 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2149 2150 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2151 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2152 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2153 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2154 flow_tag, flow_attr->type); 2155 err = -EINVAL; 2156 goto free; 2157 } 2158 flow_act.flow_tag = flow_tag; 2159 handler->rule = mlx5_add_flow_rules(ft, spec, 2160 &flow_act, 2161 dst, 1); 2162 2163 if (IS_ERR(handler->rule)) { 2164 err = PTR_ERR(handler->rule); 2165 goto free; 2166 } 2167 2168 ft_prio->refcount++; 2169 handler->prio = ft_prio; 2170 2171 ft_prio->flow_table = ft; 2172 free: 2173 if (err) 2174 kfree(handler); 2175 kvfree(spec); 2176 return err ? ERR_PTR(err) : handler; 2177 } 2178 2179 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2180 struct mlx5_ib_flow_prio *ft_prio, 2181 struct ib_flow_attr *flow_attr, 2182 struct mlx5_flow_destination *dst) 2183 { 2184 struct mlx5_ib_flow_handler *handler_dst = NULL; 2185 struct mlx5_ib_flow_handler *handler = NULL; 2186 2187 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2188 if (!IS_ERR(handler)) { 2189 handler_dst = create_flow_rule(dev, ft_prio, 2190 flow_attr, dst); 2191 if (IS_ERR(handler_dst)) { 2192 mlx5_del_flow_rules(handler->rule); 2193 ft_prio->refcount--; 2194 kfree(handler); 2195 handler = handler_dst; 2196 } else { 2197 list_add(&handler_dst->list, &handler->list); 2198 } 2199 } 2200 2201 return handler; 2202 } 2203 enum { 2204 LEFTOVERS_MC, 2205 LEFTOVERS_UC, 2206 }; 2207 2208 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2209 struct mlx5_ib_flow_prio *ft_prio, 2210 struct ib_flow_attr *flow_attr, 2211 struct mlx5_flow_destination *dst) 2212 { 2213 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2214 struct mlx5_ib_flow_handler *handler = NULL; 2215 2216 static struct { 2217 struct ib_flow_attr flow_attr; 2218 struct ib_flow_spec_eth eth_flow; 2219 } leftovers_specs[] = { 2220 [LEFTOVERS_MC] = { 2221 .flow_attr = { 2222 .num_of_specs = 1, 2223 .size = sizeof(leftovers_specs[0]) 2224 }, 2225 .eth_flow = { 2226 .type = IB_FLOW_SPEC_ETH, 2227 .size = sizeof(struct ib_flow_spec_eth), 2228 .mask = {.dst_mac = {0x1} }, 2229 .val = {.dst_mac = {0x1} } 2230 } 2231 }, 2232 [LEFTOVERS_UC] = { 2233 .flow_attr = { 2234 .num_of_specs = 1, 2235 .size = sizeof(leftovers_specs[0]) 2236 }, 2237 .eth_flow = { 2238 .type = IB_FLOW_SPEC_ETH, 2239 .size = sizeof(struct ib_flow_spec_eth), 2240 .mask = {.dst_mac = {0x1} }, 2241 .val = {.dst_mac = {} } 2242 } 2243 } 2244 }; 2245 2246 handler = create_flow_rule(dev, ft_prio, 2247 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2248 dst); 2249 if (!IS_ERR(handler) && 2250 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2251 handler_ucast = create_flow_rule(dev, ft_prio, 2252 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2253 dst); 2254 if (IS_ERR(handler_ucast)) { 2255 mlx5_del_flow_rules(handler->rule); 2256 ft_prio->refcount--; 2257 kfree(handler); 2258 handler = handler_ucast; 2259 } else { 2260 list_add(&handler_ucast->list, &handler->list); 2261 } 2262 } 2263 2264 return handler; 2265 } 2266 2267 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2268 struct mlx5_ib_flow_prio *ft_rx, 2269 struct mlx5_ib_flow_prio *ft_tx, 2270 struct mlx5_flow_destination *dst) 2271 { 2272 struct mlx5_ib_flow_handler *handler_rx; 2273 struct mlx5_ib_flow_handler *handler_tx; 2274 int err; 2275 static const struct ib_flow_attr flow_attr = { 2276 .num_of_specs = 0, 2277 .size = sizeof(flow_attr) 2278 }; 2279 2280 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2281 if (IS_ERR(handler_rx)) { 2282 err = PTR_ERR(handler_rx); 2283 goto err; 2284 } 2285 2286 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2287 if (IS_ERR(handler_tx)) { 2288 err = PTR_ERR(handler_tx); 2289 goto err_tx; 2290 } 2291 2292 list_add(&handler_tx->list, &handler_rx->list); 2293 2294 return handler_rx; 2295 2296 err_tx: 2297 mlx5_del_flow_rules(handler_rx->rule); 2298 ft_rx->refcount--; 2299 kfree(handler_rx); 2300 err: 2301 return ERR_PTR(err); 2302 } 2303 2304 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2305 struct ib_flow_attr *flow_attr, 2306 int domain) 2307 { 2308 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2309 struct mlx5_ib_qp *mqp = to_mqp(qp); 2310 struct mlx5_ib_flow_handler *handler = NULL; 2311 struct mlx5_flow_destination *dst = NULL; 2312 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2313 struct mlx5_ib_flow_prio *ft_prio; 2314 int err; 2315 2316 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2317 return ERR_PTR(-ENOSPC); 2318 2319 if (domain != IB_FLOW_DOMAIN_USER || 2320 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2321 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2322 return ERR_PTR(-EINVAL); 2323 2324 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2325 if (!dst) 2326 return ERR_PTR(-ENOMEM); 2327 2328 mutex_lock(&dev->flow_db.lock); 2329 2330 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2331 if (IS_ERR(ft_prio)) { 2332 err = PTR_ERR(ft_prio); 2333 goto unlock; 2334 } 2335 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2336 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2337 if (IS_ERR(ft_prio_tx)) { 2338 err = PTR_ERR(ft_prio_tx); 2339 ft_prio_tx = NULL; 2340 goto destroy_ft; 2341 } 2342 } 2343 2344 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2345 if (mqp->flags & MLX5_IB_QP_RSS) 2346 dst->tir_num = mqp->rss_qp.tirn; 2347 else 2348 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2349 2350 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2351 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2352 handler = create_dont_trap_rule(dev, ft_prio, 2353 flow_attr, dst); 2354 } else { 2355 handler = create_flow_rule(dev, ft_prio, flow_attr, 2356 dst); 2357 } 2358 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2359 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2360 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2361 dst); 2362 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2363 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2364 } else { 2365 err = -EINVAL; 2366 goto destroy_ft; 2367 } 2368 2369 if (IS_ERR(handler)) { 2370 err = PTR_ERR(handler); 2371 handler = NULL; 2372 goto destroy_ft; 2373 } 2374 2375 mutex_unlock(&dev->flow_db.lock); 2376 kfree(dst); 2377 2378 return &handler->ibflow; 2379 2380 destroy_ft: 2381 put_flow_table(dev, ft_prio, false); 2382 if (ft_prio_tx) 2383 put_flow_table(dev, ft_prio_tx, false); 2384 unlock: 2385 mutex_unlock(&dev->flow_db.lock); 2386 kfree(dst); 2387 kfree(handler); 2388 return ERR_PTR(err); 2389 } 2390 2391 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2392 { 2393 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2394 int err; 2395 2396 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2397 if (err) 2398 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2399 ibqp->qp_num, gid->raw); 2400 2401 return err; 2402 } 2403 2404 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2405 { 2406 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2407 int err; 2408 2409 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2410 if (err) 2411 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2412 ibqp->qp_num, gid->raw); 2413 2414 return err; 2415 } 2416 2417 static int init_node_data(struct mlx5_ib_dev *dev) 2418 { 2419 int err; 2420 2421 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2422 if (err) 2423 return err; 2424 2425 dev->mdev->rev_id = dev->mdev->pdev->revision; 2426 2427 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2428 } 2429 2430 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2431 char *buf) 2432 { 2433 struct mlx5_ib_dev *dev = 2434 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2435 2436 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2437 } 2438 2439 static ssize_t show_reg_pages(struct device *device, 2440 struct device_attribute *attr, char *buf) 2441 { 2442 struct mlx5_ib_dev *dev = 2443 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2444 2445 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2446 } 2447 2448 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2449 char *buf) 2450 { 2451 struct mlx5_ib_dev *dev = 2452 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2453 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2454 } 2455 2456 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2457 char *buf) 2458 { 2459 struct mlx5_ib_dev *dev = 2460 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2461 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2462 } 2463 2464 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2465 char *buf) 2466 { 2467 struct mlx5_ib_dev *dev = 2468 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2469 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2470 dev->mdev->board_id); 2471 } 2472 2473 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2474 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2475 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2476 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2477 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2478 2479 static struct device_attribute *mlx5_class_attributes[] = { 2480 &dev_attr_hw_rev, 2481 &dev_attr_hca_type, 2482 &dev_attr_board_id, 2483 &dev_attr_fw_pages, 2484 &dev_attr_reg_pages, 2485 }; 2486 2487 static void pkey_change_handler(struct work_struct *work) 2488 { 2489 struct mlx5_ib_port_resources *ports = 2490 container_of(work, struct mlx5_ib_port_resources, 2491 pkey_change_work); 2492 2493 mutex_lock(&ports->devr->mutex); 2494 mlx5_ib_gsi_pkey_change(ports->gsi); 2495 mutex_unlock(&ports->devr->mutex); 2496 } 2497 2498 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2499 { 2500 struct mlx5_ib_qp *mqp; 2501 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2502 struct mlx5_core_cq *mcq; 2503 struct list_head cq_armed_list; 2504 unsigned long flags_qp; 2505 unsigned long flags_cq; 2506 unsigned long flags; 2507 2508 INIT_LIST_HEAD(&cq_armed_list); 2509 2510 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2511 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2512 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2513 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2514 if (mqp->sq.tail != mqp->sq.head) { 2515 send_mcq = to_mcq(mqp->ibqp.send_cq); 2516 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2517 if (send_mcq->mcq.comp && 2518 mqp->ibqp.send_cq->comp_handler) { 2519 if (!send_mcq->mcq.reset_notify_added) { 2520 send_mcq->mcq.reset_notify_added = 1; 2521 list_add_tail(&send_mcq->mcq.reset_notify, 2522 &cq_armed_list); 2523 } 2524 } 2525 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2526 } 2527 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2528 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2529 /* no handling is needed for SRQ */ 2530 if (!mqp->ibqp.srq) { 2531 if (mqp->rq.tail != mqp->rq.head) { 2532 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2533 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2534 if (recv_mcq->mcq.comp && 2535 mqp->ibqp.recv_cq->comp_handler) { 2536 if (!recv_mcq->mcq.reset_notify_added) { 2537 recv_mcq->mcq.reset_notify_added = 1; 2538 list_add_tail(&recv_mcq->mcq.reset_notify, 2539 &cq_armed_list); 2540 } 2541 } 2542 spin_unlock_irqrestore(&recv_mcq->lock, 2543 flags_cq); 2544 } 2545 } 2546 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2547 } 2548 /*At that point all inflight post send were put to be executed as of we 2549 * lock/unlock above locks Now need to arm all involved CQs. 2550 */ 2551 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2552 mcq->comp(mcq); 2553 } 2554 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2555 } 2556 2557 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2558 enum mlx5_dev_event event, unsigned long param) 2559 { 2560 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2561 struct ib_event ibev; 2562 bool fatal = false; 2563 u8 port = 0; 2564 2565 switch (event) { 2566 case MLX5_DEV_EVENT_SYS_ERROR: 2567 ibev.event = IB_EVENT_DEVICE_FATAL; 2568 mlx5_ib_handle_internal_error(ibdev); 2569 fatal = true; 2570 break; 2571 2572 case MLX5_DEV_EVENT_PORT_UP: 2573 case MLX5_DEV_EVENT_PORT_DOWN: 2574 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2575 port = (u8)param; 2576 2577 /* In RoCE, port up/down events are handled in 2578 * mlx5_netdev_event(). 2579 */ 2580 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2581 IB_LINK_LAYER_ETHERNET) 2582 return; 2583 2584 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2585 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2586 break; 2587 2588 case MLX5_DEV_EVENT_LID_CHANGE: 2589 ibev.event = IB_EVENT_LID_CHANGE; 2590 port = (u8)param; 2591 break; 2592 2593 case MLX5_DEV_EVENT_PKEY_CHANGE: 2594 ibev.event = IB_EVENT_PKEY_CHANGE; 2595 port = (u8)param; 2596 2597 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2598 break; 2599 2600 case MLX5_DEV_EVENT_GUID_CHANGE: 2601 ibev.event = IB_EVENT_GID_CHANGE; 2602 port = (u8)param; 2603 break; 2604 2605 case MLX5_DEV_EVENT_CLIENT_REREG: 2606 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2607 port = (u8)param; 2608 break; 2609 default: 2610 return; 2611 } 2612 2613 ibev.device = &ibdev->ib_dev; 2614 ibev.element.port_num = port; 2615 2616 if (port < 1 || port > ibdev->num_ports) { 2617 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2618 return; 2619 } 2620 2621 if (ibdev->ib_active) 2622 ib_dispatch_event(&ibev); 2623 2624 if (fatal) 2625 ibdev->ib_active = false; 2626 } 2627 2628 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2629 { 2630 struct mlx5_hca_vport_context vport_ctx; 2631 int err; 2632 int port; 2633 2634 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2635 dev->mdev->port_caps[port - 1].has_smi = false; 2636 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2637 MLX5_CAP_PORT_TYPE_IB) { 2638 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2639 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2640 port, 0, 2641 &vport_ctx); 2642 if (err) { 2643 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2644 port, err); 2645 return err; 2646 } 2647 dev->mdev->port_caps[port - 1].has_smi = 2648 vport_ctx.has_smi; 2649 } else { 2650 dev->mdev->port_caps[port - 1].has_smi = true; 2651 } 2652 } 2653 } 2654 return 0; 2655 } 2656 2657 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2658 { 2659 int port; 2660 2661 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2662 mlx5_query_ext_port_caps(dev, port); 2663 } 2664 2665 static int get_port_caps(struct mlx5_ib_dev *dev) 2666 { 2667 struct ib_device_attr *dprops = NULL; 2668 struct ib_port_attr *pprops = NULL; 2669 int err = -ENOMEM; 2670 int port; 2671 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2672 2673 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2674 if (!pprops) 2675 goto out; 2676 2677 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2678 if (!dprops) 2679 goto out; 2680 2681 err = set_has_smi_cap(dev); 2682 if (err) 2683 goto out; 2684 2685 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2686 if (err) { 2687 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2688 goto out; 2689 } 2690 2691 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2692 memset(pprops, 0, sizeof(*pprops)); 2693 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2694 if (err) { 2695 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2696 port, err); 2697 break; 2698 } 2699 dev->mdev->port_caps[port - 1].pkey_table_len = 2700 dprops->max_pkeys; 2701 dev->mdev->port_caps[port - 1].gid_table_len = 2702 pprops->gid_tbl_len; 2703 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2704 dprops->max_pkeys, pprops->gid_tbl_len); 2705 } 2706 2707 out: 2708 kfree(pprops); 2709 kfree(dprops); 2710 2711 return err; 2712 } 2713 2714 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2715 { 2716 int err; 2717 2718 err = mlx5_mr_cache_cleanup(dev); 2719 if (err) 2720 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2721 2722 mlx5_ib_destroy_qp(dev->umrc.qp); 2723 ib_free_cq(dev->umrc.cq); 2724 ib_dealloc_pd(dev->umrc.pd); 2725 } 2726 2727 enum { 2728 MAX_UMR_WR = 128, 2729 }; 2730 2731 static int create_umr_res(struct mlx5_ib_dev *dev) 2732 { 2733 struct ib_qp_init_attr *init_attr = NULL; 2734 struct ib_qp_attr *attr = NULL; 2735 struct ib_pd *pd; 2736 struct ib_cq *cq; 2737 struct ib_qp *qp; 2738 int ret; 2739 2740 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2741 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2742 if (!attr || !init_attr) { 2743 ret = -ENOMEM; 2744 goto error_0; 2745 } 2746 2747 pd = ib_alloc_pd(&dev->ib_dev, 0); 2748 if (IS_ERR(pd)) { 2749 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2750 ret = PTR_ERR(pd); 2751 goto error_0; 2752 } 2753 2754 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2755 if (IS_ERR(cq)) { 2756 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2757 ret = PTR_ERR(cq); 2758 goto error_2; 2759 } 2760 2761 init_attr->send_cq = cq; 2762 init_attr->recv_cq = cq; 2763 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2764 init_attr->cap.max_send_wr = MAX_UMR_WR; 2765 init_attr->cap.max_send_sge = 1; 2766 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2767 init_attr->port_num = 1; 2768 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2769 if (IS_ERR(qp)) { 2770 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2771 ret = PTR_ERR(qp); 2772 goto error_3; 2773 } 2774 qp->device = &dev->ib_dev; 2775 qp->real_qp = qp; 2776 qp->uobject = NULL; 2777 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2778 2779 attr->qp_state = IB_QPS_INIT; 2780 attr->port_num = 1; 2781 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2782 IB_QP_PORT, NULL); 2783 if (ret) { 2784 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2785 goto error_4; 2786 } 2787 2788 memset(attr, 0, sizeof(*attr)); 2789 attr->qp_state = IB_QPS_RTR; 2790 attr->path_mtu = IB_MTU_256; 2791 2792 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2793 if (ret) { 2794 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2795 goto error_4; 2796 } 2797 2798 memset(attr, 0, sizeof(*attr)); 2799 attr->qp_state = IB_QPS_RTS; 2800 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2801 if (ret) { 2802 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2803 goto error_4; 2804 } 2805 2806 dev->umrc.qp = qp; 2807 dev->umrc.cq = cq; 2808 dev->umrc.pd = pd; 2809 2810 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2811 ret = mlx5_mr_cache_init(dev); 2812 if (ret) { 2813 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2814 goto error_4; 2815 } 2816 2817 kfree(attr); 2818 kfree(init_attr); 2819 2820 return 0; 2821 2822 error_4: 2823 mlx5_ib_destroy_qp(qp); 2824 2825 error_3: 2826 ib_free_cq(cq); 2827 2828 error_2: 2829 ib_dealloc_pd(pd); 2830 2831 error_0: 2832 kfree(attr); 2833 kfree(init_attr); 2834 return ret; 2835 } 2836 2837 static int create_dev_resources(struct mlx5_ib_resources *devr) 2838 { 2839 struct ib_srq_init_attr attr; 2840 struct mlx5_ib_dev *dev; 2841 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2842 int port; 2843 int ret = 0; 2844 2845 dev = container_of(devr, struct mlx5_ib_dev, devr); 2846 2847 mutex_init(&devr->mutex); 2848 2849 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2850 if (IS_ERR(devr->p0)) { 2851 ret = PTR_ERR(devr->p0); 2852 goto error0; 2853 } 2854 devr->p0->device = &dev->ib_dev; 2855 devr->p0->uobject = NULL; 2856 atomic_set(&devr->p0->usecnt, 0); 2857 2858 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2859 if (IS_ERR(devr->c0)) { 2860 ret = PTR_ERR(devr->c0); 2861 goto error1; 2862 } 2863 devr->c0->device = &dev->ib_dev; 2864 devr->c0->uobject = NULL; 2865 devr->c0->comp_handler = NULL; 2866 devr->c0->event_handler = NULL; 2867 devr->c0->cq_context = NULL; 2868 atomic_set(&devr->c0->usecnt, 0); 2869 2870 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2871 if (IS_ERR(devr->x0)) { 2872 ret = PTR_ERR(devr->x0); 2873 goto error2; 2874 } 2875 devr->x0->device = &dev->ib_dev; 2876 devr->x0->inode = NULL; 2877 atomic_set(&devr->x0->usecnt, 0); 2878 mutex_init(&devr->x0->tgt_qp_mutex); 2879 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2880 2881 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2882 if (IS_ERR(devr->x1)) { 2883 ret = PTR_ERR(devr->x1); 2884 goto error3; 2885 } 2886 devr->x1->device = &dev->ib_dev; 2887 devr->x1->inode = NULL; 2888 atomic_set(&devr->x1->usecnt, 0); 2889 mutex_init(&devr->x1->tgt_qp_mutex); 2890 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2891 2892 memset(&attr, 0, sizeof(attr)); 2893 attr.attr.max_sge = 1; 2894 attr.attr.max_wr = 1; 2895 attr.srq_type = IB_SRQT_XRC; 2896 attr.ext.xrc.cq = devr->c0; 2897 attr.ext.xrc.xrcd = devr->x0; 2898 2899 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2900 if (IS_ERR(devr->s0)) { 2901 ret = PTR_ERR(devr->s0); 2902 goto error4; 2903 } 2904 devr->s0->device = &dev->ib_dev; 2905 devr->s0->pd = devr->p0; 2906 devr->s0->uobject = NULL; 2907 devr->s0->event_handler = NULL; 2908 devr->s0->srq_context = NULL; 2909 devr->s0->srq_type = IB_SRQT_XRC; 2910 devr->s0->ext.xrc.xrcd = devr->x0; 2911 devr->s0->ext.xrc.cq = devr->c0; 2912 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2913 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2914 atomic_inc(&devr->p0->usecnt); 2915 atomic_set(&devr->s0->usecnt, 0); 2916 2917 memset(&attr, 0, sizeof(attr)); 2918 attr.attr.max_sge = 1; 2919 attr.attr.max_wr = 1; 2920 attr.srq_type = IB_SRQT_BASIC; 2921 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2922 if (IS_ERR(devr->s1)) { 2923 ret = PTR_ERR(devr->s1); 2924 goto error5; 2925 } 2926 devr->s1->device = &dev->ib_dev; 2927 devr->s1->pd = devr->p0; 2928 devr->s1->uobject = NULL; 2929 devr->s1->event_handler = NULL; 2930 devr->s1->srq_context = NULL; 2931 devr->s1->srq_type = IB_SRQT_BASIC; 2932 devr->s1->ext.xrc.cq = devr->c0; 2933 atomic_inc(&devr->p0->usecnt); 2934 atomic_set(&devr->s0->usecnt, 0); 2935 2936 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2937 INIT_WORK(&devr->ports[port].pkey_change_work, 2938 pkey_change_handler); 2939 devr->ports[port].devr = devr; 2940 } 2941 2942 return 0; 2943 2944 error5: 2945 mlx5_ib_destroy_srq(devr->s0); 2946 error4: 2947 mlx5_ib_dealloc_xrcd(devr->x1); 2948 error3: 2949 mlx5_ib_dealloc_xrcd(devr->x0); 2950 error2: 2951 mlx5_ib_destroy_cq(devr->c0); 2952 error1: 2953 mlx5_ib_dealloc_pd(devr->p0); 2954 error0: 2955 return ret; 2956 } 2957 2958 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2959 { 2960 struct mlx5_ib_dev *dev = 2961 container_of(devr, struct mlx5_ib_dev, devr); 2962 int port; 2963 2964 mlx5_ib_destroy_srq(devr->s1); 2965 mlx5_ib_destroy_srq(devr->s0); 2966 mlx5_ib_dealloc_xrcd(devr->x0); 2967 mlx5_ib_dealloc_xrcd(devr->x1); 2968 mlx5_ib_destroy_cq(devr->c0); 2969 mlx5_ib_dealloc_pd(devr->p0); 2970 2971 /* Make sure no change P_Key work items are still executing */ 2972 for (port = 0; port < dev->num_ports; ++port) 2973 cancel_work_sync(&devr->ports[port].pkey_change_work); 2974 } 2975 2976 static u32 get_core_cap_flags(struct ib_device *ibdev) 2977 { 2978 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2979 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2980 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2981 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2982 u32 ret = 0; 2983 2984 if (ll == IB_LINK_LAYER_INFINIBAND) 2985 return RDMA_CORE_PORT_IBA_IB; 2986 2987 ret = RDMA_CORE_PORT_RAW_PACKET; 2988 2989 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2990 return ret; 2991 2992 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2993 return ret; 2994 2995 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2996 ret |= RDMA_CORE_PORT_IBA_ROCE; 2997 2998 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2999 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3000 3001 return ret; 3002 } 3003 3004 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3005 struct ib_port_immutable *immutable) 3006 { 3007 struct ib_port_attr attr; 3008 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3009 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3010 int err; 3011 3012 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3013 3014 err = ib_query_port(ibdev, port_num, &attr); 3015 if (err) 3016 return err; 3017 3018 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3019 immutable->gid_tbl_len = attr.gid_tbl_len; 3020 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3021 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3022 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3023 3024 return 0; 3025 } 3026 3027 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3028 size_t str_len) 3029 { 3030 struct mlx5_ib_dev *dev = 3031 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3032 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3033 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3034 } 3035 3036 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3037 { 3038 struct mlx5_core_dev *mdev = dev->mdev; 3039 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3040 MLX5_FLOW_NAMESPACE_LAG); 3041 struct mlx5_flow_table *ft; 3042 int err; 3043 3044 if (!ns || !mlx5_lag_is_active(mdev)) 3045 return 0; 3046 3047 err = mlx5_cmd_create_vport_lag(mdev); 3048 if (err) 3049 return err; 3050 3051 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3052 if (IS_ERR(ft)) { 3053 err = PTR_ERR(ft); 3054 goto err_destroy_vport_lag; 3055 } 3056 3057 dev->flow_db.lag_demux_ft = ft; 3058 return 0; 3059 3060 err_destroy_vport_lag: 3061 mlx5_cmd_destroy_vport_lag(mdev); 3062 return err; 3063 } 3064 3065 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3066 { 3067 struct mlx5_core_dev *mdev = dev->mdev; 3068 3069 if (dev->flow_db.lag_demux_ft) { 3070 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3071 dev->flow_db.lag_demux_ft = NULL; 3072 3073 mlx5_cmd_destroy_vport_lag(mdev); 3074 } 3075 } 3076 3077 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3078 { 3079 int err; 3080 3081 dev->roce.nb.notifier_call = mlx5_netdev_event; 3082 err = register_netdevice_notifier(&dev->roce.nb); 3083 if (err) { 3084 dev->roce.nb.notifier_call = NULL; 3085 return err; 3086 } 3087 3088 return 0; 3089 } 3090 3091 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3092 { 3093 if (dev->roce.nb.notifier_call) { 3094 unregister_netdevice_notifier(&dev->roce.nb); 3095 dev->roce.nb.notifier_call = NULL; 3096 } 3097 } 3098 3099 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3100 { 3101 int err; 3102 3103 err = mlx5_add_netdev_notifier(dev); 3104 if (err) 3105 return err; 3106 3107 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3108 err = mlx5_nic_vport_enable_roce(dev->mdev); 3109 if (err) 3110 goto err_unregister_netdevice_notifier; 3111 } 3112 3113 err = mlx5_eth_lag_init(dev); 3114 if (err) 3115 goto err_disable_roce; 3116 3117 return 0; 3118 3119 err_disable_roce: 3120 if (MLX5_CAP_GEN(dev->mdev, roce)) 3121 mlx5_nic_vport_disable_roce(dev->mdev); 3122 3123 err_unregister_netdevice_notifier: 3124 mlx5_remove_netdev_notifier(dev); 3125 return err; 3126 } 3127 3128 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3129 { 3130 mlx5_eth_lag_cleanup(dev); 3131 if (MLX5_CAP_GEN(dev->mdev, roce)) 3132 mlx5_nic_vport_disable_roce(dev->mdev); 3133 } 3134 3135 struct mlx5_ib_q_counter { 3136 const char *name; 3137 size_t offset; 3138 }; 3139 3140 #define INIT_Q_COUNTER(_name) \ 3141 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3142 3143 static const struct mlx5_ib_q_counter basic_q_cnts[] = { 3144 INIT_Q_COUNTER(rx_write_requests), 3145 INIT_Q_COUNTER(rx_read_requests), 3146 INIT_Q_COUNTER(rx_atomic_requests), 3147 INIT_Q_COUNTER(out_of_buffer), 3148 }; 3149 3150 static const struct mlx5_ib_q_counter out_of_seq_q_cnts[] = { 3151 INIT_Q_COUNTER(out_of_sequence), 3152 }; 3153 3154 static const struct mlx5_ib_q_counter retrans_q_cnts[] = { 3155 INIT_Q_COUNTER(duplicate_request), 3156 INIT_Q_COUNTER(rnr_nak_retry_err), 3157 INIT_Q_COUNTER(packet_seq_err), 3158 INIT_Q_COUNTER(implied_nak_seq_err), 3159 INIT_Q_COUNTER(local_ack_timeout_err), 3160 }; 3161 3162 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 3163 { 3164 unsigned int i; 3165 3166 for (i = 0; i < dev->num_ports; i++) { 3167 mlx5_core_dealloc_q_counter(dev->mdev, 3168 dev->port[i].q_cnts.set_id); 3169 kfree(dev->port[i].q_cnts.names); 3170 kfree(dev->port[i].q_cnts.offsets); 3171 } 3172 } 3173 3174 static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev, 3175 const char ***names, 3176 size_t **offsets, 3177 u32 *num) 3178 { 3179 u32 num_counters; 3180 3181 num_counters = ARRAY_SIZE(basic_q_cnts); 3182 3183 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3184 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3185 3186 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3187 num_counters += ARRAY_SIZE(retrans_q_cnts); 3188 3189 *names = kcalloc(num_counters, sizeof(**names), GFP_KERNEL); 3190 if (!*names) 3191 return -ENOMEM; 3192 3193 *offsets = kcalloc(num_counters, sizeof(**offsets), GFP_KERNEL); 3194 if (!*offsets) 3195 goto err_names; 3196 3197 *num = num_counters; 3198 3199 return 0; 3200 3201 err_names: 3202 kfree(*names); 3203 return -ENOMEM; 3204 } 3205 3206 static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev, 3207 const char **names, 3208 size_t *offsets) 3209 { 3210 int i; 3211 int j = 0; 3212 3213 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3214 names[j] = basic_q_cnts[i].name; 3215 offsets[j] = basic_q_cnts[i].offset; 3216 } 3217 3218 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3219 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3220 names[j] = out_of_seq_q_cnts[i].name; 3221 offsets[j] = out_of_seq_q_cnts[i].offset; 3222 } 3223 } 3224 3225 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3226 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3227 names[j] = retrans_q_cnts[i].name; 3228 offsets[j] = retrans_q_cnts[i].offset; 3229 } 3230 } 3231 } 3232 3233 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 3234 { 3235 int i; 3236 int ret; 3237 3238 for (i = 0; i < dev->num_ports; i++) { 3239 struct mlx5_ib_port *port = &dev->port[i]; 3240 3241 ret = mlx5_core_alloc_q_counter(dev->mdev, 3242 &port->q_cnts.set_id); 3243 if (ret) { 3244 mlx5_ib_warn(dev, 3245 "couldn't allocate queue counter for port %d, err %d\n", 3246 i + 1, ret); 3247 goto dealloc_counters; 3248 } 3249 3250 ret = __mlx5_ib_alloc_q_counters(dev, 3251 &port->q_cnts.names, 3252 &port->q_cnts.offsets, 3253 &port->q_cnts.num_counters); 3254 if (ret) 3255 goto dealloc_counters; 3256 3257 mlx5_ib_fill_q_counters(dev, port->q_cnts.names, 3258 port->q_cnts.offsets); 3259 } 3260 3261 return 0; 3262 3263 dealloc_counters: 3264 while (--i >= 0) 3265 mlx5_core_dealloc_q_counter(dev->mdev, 3266 dev->port[i].q_cnts.set_id); 3267 3268 return ret; 3269 } 3270 3271 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3272 u8 port_num) 3273 { 3274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3275 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3276 3277 /* We support only per port stats */ 3278 if (port_num == 0) 3279 return NULL; 3280 3281 return rdma_alloc_hw_stats_struct(port->q_cnts.names, 3282 port->q_cnts.num_counters, 3283 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3284 } 3285 3286 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3287 struct rdma_hw_stats *stats, 3288 u8 port_num, int index) 3289 { 3290 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3291 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3292 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3293 void *out; 3294 __be32 val; 3295 int ret; 3296 int i; 3297 3298 if (!stats) 3299 return -ENOSYS; 3300 3301 out = mlx5_vzalloc(outlen); 3302 if (!out) 3303 return -ENOMEM; 3304 3305 ret = mlx5_core_query_q_counter(dev->mdev, 3306 port->q_cnts.set_id, 0, 3307 out, outlen); 3308 if (ret) 3309 goto free; 3310 3311 for (i = 0; i < port->q_cnts.num_counters; i++) { 3312 val = *(__be32 *)(out + port->q_cnts.offsets[i]); 3313 stats->value[i] = (u64)be32_to_cpu(val); 3314 } 3315 3316 free: 3317 kvfree(out); 3318 return port->q_cnts.num_counters; 3319 } 3320 3321 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3322 { 3323 struct mlx5_ib_dev *dev; 3324 enum rdma_link_layer ll; 3325 int port_type_cap; 3326 const char *name; 3327 int err; 3328 int i; 3329 3330 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3331 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3332 3333 printk_once(KERN_INFO "%s", mlx5_version); 3334 3335 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3336 if (!dev) 3337 return NULL; 3338 3339 dev->mdev = mdev; 3340 3341 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3342 GFP_KERNEL); 3343 if (!dev->port) 3344 goto err_dealloc; 3345 3346 rwlock_init(&dev->roce.netdev_lock); 3347 err = get_port_caps(dev); 3348 if (err) 3349 goto err_free_port; 3350 3351 if (mlx5_use_mad_ifc(dev)) 3352 get_ext_port_caps(dev); 3353 3354 if (!mlx5_lag_is_active(mdev)) 3355 name = "mlx5_%d"; 3356 else 3357 name = "mlx5_bond_%d"; 3358 3359 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3360 dev->ib_dev.owner = THIS_MODULE; 3361 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3362 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3363 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3364 dev->ib_dev.phys_port_cnt = dev->num_ports; 3365 dev->ib_dev.num_comp_vectors = 3366 dev->mdev->priv.eq_table.num_comp_vectors; 3367 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3368 3369 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3370 dev->ib_dev.uverbs_cmd_mask = 3371 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3372 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3373 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3374 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3375 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3376 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3377 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3378 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3379 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3380 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3381 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3382 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3383 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3384 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3385 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3386 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3387 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3388 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3389 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3390 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3391 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3392 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3393 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3394 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3395 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3396 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3397 dev->ib_dev.uverbs_ex_cmd_mask = 3398 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3399 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3400 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3401 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3402 3403 dev->ib_dev.query_device = mlx5_ib_query_device; 3404 dev->ib_dev.query_port = mlx5_ib_query_port; 3405 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3406 if (ll == IB_LINK_LAYER_ETHERNET) 3407 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3408 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3409 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3410 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3411 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3412 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3413 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3414 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3415 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3416 dev->ib_dev.mmap = mlx5_ib_mmap; 3417 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3418 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3419 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3420 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3421 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3422 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3423 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3424 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3425 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3426 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3427 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3428 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3429 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3430 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3431 dev->ib_dev.post_send = mlx5_ib_post_send; 3432 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3433 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3434 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3435 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3436 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3437 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3438 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3439 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3440 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3441 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3442 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3443 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3444 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3445 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3446 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3447 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3448 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3449 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3450 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3451 if (mlx5_core_is_pf(mdev)) { 3452 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3453 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3454 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3455 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3456 } 3457 3458 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3459 3460 mlx5_ib_internal_fill_odp_caps(dev); 3461 3462 if (MLX5_CAP_GEN(mdev, imaicl)) { 3463 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3464 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3465 dev->ib_dev.uverbs_cmd_mask |= 3466 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3467 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3468 } 3469 3470 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3471 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3472 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3473 } 3474 3475 if (MLX5_CAP_GEN(mdev, xrc)) { 3476 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3477 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3478 dev->ib_dev.uverbs_cmd_mask |= 3479 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3480 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3481 } 3482 3483 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3484 IB_LINK_LAYER_ETHERNET) { 3485 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3486 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3487 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3488 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3489 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3490 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3491 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3492 dev->ib_dev.uverbs_ex_cmd_mask |= 3493 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3494 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3495 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3496 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3497 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3498 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3499 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3500 } 3501 err = init_node_data(dev); 3502 if (err) 3503 goto err_free_port; 3504 3505 mutex_init(&dev->flow_db.lock); 3506 mutex_init(&dev->cap_mask_mutex); 3507 INIT_LIST_HEAD(&dev->qp_list); 3508 spin_lock_init(&dev->reset_flow_resource_lock); 3509 3510 if (ll == IB_LINK_LAYER_ETHERNET) { 3511 err = mlx5_enable_eth(dev); 3512 if (err) 3513 goto err_free_port; 3514 } 3515 3516 err = create_dev_resources(&dev->devr); 3517 if (err) 3518 goto err_disable_eth; 3519 3520 err = mlx5_ib_odp_init_one(dev); 3521 if (err) 3522 goto err_rsrc; 3523 3524 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3525 err = mlx5_ib_alloc_q_counters(dev); 3526 if (err) 3527 goto err_odp; 3528 } 3529 3530 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3531 if (!dev->mdev->priv.uar) 3532 goto err_q_cnt; 3533 3534 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3535 if (err) 3536 goto err_uar_page; 3537 3538 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3539 if (err) 3540 goto err_bfreg; 3541 3542 err = ib_register_device(&dev->ib_dev, NULL); 3543 if (err) 3544 goto err_fp_bfreg; 3545 3546 err = create_umr_res(dev); 3547 if (err) 3548 goto err_dev; 3549 3550 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3551 err = device_create_file(&dev->ib_dev.dev, 3552 mlx5_class_attributes[i]); 3553 if (err) 3554 goto err_umrc; 3555 } 3556 3557 dev->ib_active = true; 3558 3559 return dev; 3560 3561 err_umrc: 3562 destroy_umrc_res(dev); 3563 3564 err_dev: 3565 ib_unregister_device(&dev->ib_dev); 3566 3567 err_fp_bfreg: 3568 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3569 3570 err_bfreg: 3571 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3572 3573 err_uar_page: 3574 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3575 3576 err_q_cnt: 3577 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3578 mlx5_ib_dealloc_q_counters(dev); 3579 3580 err_odp: 3581 mlx5_ib_odp_remove_one(dev); 3582 3583 err_rsrc: 3584 destroy_dev_resources(&dev->devr); 3585 3586 err_disable_eth: 3587 if (ll == IB_LINK_LAYER_ETHERNET) { 3588 mlx5_disable_eth(dev); 3589 mlx5_remove_netdev_notifier(dev); 3590 } 3591 3592 err_free_port: 3593 kfree(dev->port); 3594 3595 err_dealloc: 3596 ib_dealloc_device((struct ib_device *)dev); 3597 3598 return NULL; 3599 } 3600 3601 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3602 { 3603 struct mlx5_ib_dev *dev = context; 3604 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3605 3606 mlx5_remove_netdev_notifier(dev); 3607 ib_unregister_device(&dev->ib_dev); 3608 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3609 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3610 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 3611 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3612 mlx5_ib_dealloc_q_counters(dev); 3613 destroy_umrc_res(dev); 3614 mlx5_ib_odp_remove_one(dev); 3615 destroy_dev_resources(&dev->devr); 3616 if (ll == IB_LINK_LAYER_ETHERNET) 3617 mlx5_disable_eth(dev); 3618 kfree(dev->port); 3619 ib_dealloc_device(&dev->ib_dev); 3620 } 3621 3622 static struct mlx5_interface mlx5_ib_interface = { 3623 .add = mlx5_ib_add, 3624 .remove = mlx5_ib_remove, 3625 .event = mlx5_ib_event, 3626 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3627 .pfault = mlx5_ib_pfault, 3628 #endif 3629 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3630 }; 3631 3632 static int __init mlx5_ib_init(void) 3633 { 3634 int err; 3635 3636 mlx5_ib_odp_init(); 3637 3638 err = mlx5_register_interface(&mlx5_ib_interface); 3639 3640 return err; 3641 } 3642 3643 static void __exit mlx5_ib_cleanup(void) 3644 { 3645 mlx5_unregister_interface(&mlx5_ib_interface); 3646 } 3647 3648 module_init(mlx5_ib_init); 3649 module_exit(mlx5_ib_cleanup); 3650