1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <rdma/ib_user_verbs.h> 46 #include <rdma/ib_addr.h> 47 #include <rdma/ib_cache.h> 48 #include <linux/mlx5/port.h> 49 #include <linux/mlx5/vport.h> 50 #include <rdma/ib_smi.h> 51 #include <rdma/ib_umem.h> 52 #include <linux/in.h> 53 #include <linux/etherdevice.h> 54 #include <linux/mlx5/fs.h> 55 #include "user.h" 56 #include "mlx5_ib.h" 57 58 #define DRIVER_NAME "mlx5_ib" 59 #define DRIVER_VERSION "2.2-1" 60 #define DRIVER_RELDATE "Feb 2014" 61 62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 64 MODULE_LICENSE("Dual BSD/GPL"); 65 MODULE_VERSION(DRIVER_VERSION); 66 67 static int deprecated_prof_sel = 2; 68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 109 return NOTIFY_DONE; 110 111 write_lock(&ibdev->roce.netdev_lock); 112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 114 write_unlock(&ibdev->roce.netdev_lock); 115 116 return NOTIFY_DONE; 117 } 118 119 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 120 u8 port_num) 121 { 122 struct mlx5_ib_dev *ibdev = to_mdev(device); 123 struct net_device *ndev; 124 125 /* Ensure ndev does not disappear before we invoke dev_hold() 126 */ 127 read_lock(&ibdev->roce.netdev_lock); 128 ndev = ibdev->roce.netdev; 129 if (ndev) 130 dev_hold(ndev); 131 read_unlock(&ibdev->roce.netdev_lock); 132 133 return ndev; 134 } 135 136 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 137 struct ib_port_attr *props) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 struct net_device *ndev; 141 enum ib_mtu ndev_ib_mtu; 142 u16 qkey_viol_cntr; 143 144 memset(props, 0, sizeof(*props)); 145 146 props->port_cap_flags |= IB_PORT_CM_SUP; 147 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 148 149 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 150 roce_address_table_size); 151 props->max_mtu = IB_MTU_4096; 152 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 153 props->pkey_tbl_len = 1; 154 props->state = IB_PORT_DOWN; 155 props->phys_state = 3; 156 157 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 158 props->qkey_viol_cntr = qkey_viol_cntr; 159 160 ndev = mlx5_ib_get_netdev(device, port_num); 161 if (!ndev) 162 return 0; 163 164 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 165 props->state = IB_PORT_ACTIVE; 166 props->phys_state = 5; 167 } 168 169 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 170 171 dev_put(ndev); 172 173 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 174 175 props->active_width = IB_WIDTH_4X; /* TODO */ 176 props->active_speed = IB_SPEED_QDR; /* TODO */ 177 178 return 0; 179 } 180 181 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 182 const struct ib_gid_attr *attr, 183 void *mlx5_addr) 184 { 185 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 186 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 187 source_l3_address); 188 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 189 source_mac_47_32); 190 191 if (!gid) 192 return; 193 194 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 195 196 if (is_vlan_dev(attr->ndev)) { 197 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 198 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 199 } 200 201 switch (attr->gid_type) { 202 case IB_GID_TYPE_IB: 203 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 204 break; 205 case IB_GID_TYPE_ROCE_UDP_ENCAP: 206 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 207 break; 208 209 default: 210 WARN_ON(true); 211 } 212 213 if (attr->gid_type != IB_GID_TYPE_IB) { 214 if (ipv6_addr_v4mapped((void *)gid)) 215 MLX5_SET_RA(mlx5_addr, roce_l3_type, 216 MLX5_ROCE_L3_TYPE_IPV4); 217 else 218 MLX5_SET_RA(mlx5_addr, roce_l3_type, 219 MLX5_ROCE_L3_TYPE_IPV6); 220 } 221 222 if ((attr->gid_type == IB_GID_TYPE_IB) || 223 !ipv6_addr_v4mapped((void *)gid)) 224 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 225 else 226 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 227 } 228 229 static int set_roce_addr(struct ib_device *device, u8 port_num, 230 unsigned int index, 231 const union ib_gid *gid, 232 const struct ib_gid_attr *attr) 233 { 234 struct mlx5_ib_dev *dev = to_mdev(device); 235 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; 236 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; 237 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 238 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 239 240 if (ll != IB_LINK_LAYER_ETHERNET) 241 return -EINVAL; 242 243 memset(in, 0, sizeof(in)); 244 245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 246 247 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 249 250 memset(out, 0, sizeof(out)); 251 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 252 } 253 254 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 255 unsigned int index, const union ib_gid *gid, 256 const struct ib_gid_attr *attr, 257 __always_unused void **context) 258 { 259 return set_roce_addr(device, port_num, index, gid, attr); 260 } 261 262 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 263 unsigned int index, __always_unused void **context) 264 { 265 return set_roce_addr(device, port_num, index, NULL, NULL); 266 } 267 268 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 269 int index) 270 { 271 struct ib_gid_attr attr; 272 union ib_gid gid; 273 274 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 275 return 0; 276 277 if (!attr.ndev) 278 return 0; 279 280 dev_put(attr.ndev); 281 282 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 283 return 0; 284 285 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 286 } 287 288 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 289 { 290 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 291 } 292 293 enum { 294 MLX5_VPORT_ACCESS_METHOD_MAD, 295 MLX5_VPORT_ACCESS_METHOD_HCA, 296 MLX5_VPORT_ACCESS_METHOD_NIC, 297 }; 298 299 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 300 { 301 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 302 return MLX5_VPORT_ACCESS_METHOD_MAD; 303 304 if (mlx5_ib_port_link_layer(ibdev, 1) == 305 IB_LINK_LAYER_ETHERNET) 306 return MLX5_VPORT_ACCESS_METHOD_NIC; 307 308 return MLX5_VPORT_ACCESS_METHOD_HCA; 309 } 310 311 static void get_atomic_caps(struct mlx5_ib_dev *dev, 312 struct ib_device_attr *props) 313 { 314 u8 tmp; 315 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 316 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 317 u8 atomic_req_8B_endianness_mode = 318 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 319 320 /* Check if HW supports 8 bytes standard atomic operations and capable 321 * of host endianness respond 322 */ 323 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 324 if (((atomic_operations & tmp) == tmp) && 325 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 326 (atomic_req_8B_endianness_mode)) { 327 props->atomic_cap = IB_ATOMIC_HCA; 328 } else { 329 props->atomic_cap = IB_ATOMIC_NONE; 330 } 331 } 332 333 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 334 __be64 *sys_image_guid) 335 { 336 struct mlx5_ib_dev *dev = to_mdev(ibdev); 337 struct mlx5_core_dev *mdev = dev->mdev; 338 u64 tmp; 339 int err; 340 341 switch (mlx5_get_vport_access_method(ibdev)) { 342 case MLX5_VPORT_ACCESS_METHOD_MAD: 343 return mlx5_query_mad_ifc_system_image_guid(ibdev, 344 sys_image_guid); 345 346 case MLX5_VPORT_ACCESS_METHOD_HCA: 347 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 348 break; 349 350 case MLX5_VPORT_ACCESS_METHOD_NIC: 351 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 352 break; 353 354 default: 355 return -EINVAL; 356 } 357 358 if (!err) 359 *sys_image_guid = cpu_to_be64(tmp); 360 361 return err; 362 363 } 364 365 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 366 u16 *max_pkeys) 367 { 368 struct mlx5_ib_dev *dev = to_mdev(ibdev); 369 struct mlx5_core_dev *mdev = dev->mdev; 370 371 switch (mlx5_get_vport_access_method(ibdev)) { 372 case MLX5_VPORT_ACCESS_METHOD_MAD: 373 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 374 375 case MLX5_VPORT_ACCESS_METHOD_HCA: 376 case MLX5_VPORT_ACCESS_METHOD_NIC: 377 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 378 pkey_table_size)); 379 return 0; 380 381 default: 382 return -EINVAL; 383 } 384 } 385 386 static int mlx5_query_vendor_id(struct ib_device *ibdev, 387 u32 *vendor_id) 388 { 389 struct mlx5_ib_dev *dev = to_mdev(ibdev); 390 391 switch (mlx5_get_vport_access_method(ibdev)) { 392 case MLX5_VPORT_ACCESS_METHOD_MAD: 393 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 394 395 case MLX5_VPORT_ACCESS_METHOD_HCA: 396 case MLX5_VPORT_ACCESS_METHOD_NIC: 397 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 398 399 default: 400 return -EINVAL; 401 } 402 } 403 404 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 405 __be64 *node_guid) 406 { 407 u64 tmp; 408 int err; 409 410 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 411 case MLX5_VPORT_ACCESS_METHOD_MAD: 412 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 413 414 case MLX5_VPORT_ACCESS_METHOD_HCA: 415 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 416 break; 417 418 case MLX5_VPORT_ACCESS_METHOD_NIC: 419 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 420 break; 421 422 default: 423 return -EINVAL; 424 } 425 426 if (!err) 427 *node_guid = cpu_to_be64(tmp); 428 429 return err; 430 } 431 432 struct mlx5_reg_node_desc { 433 u8 desc[64]; 434 }; 435 436 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 437 { 438 struct mlx5_reg_node_desc in; 439 440 if (mlx5_use_mad_ifc(dev)) 441 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 442 443 memset(&in, 0, sizeof(in)); 444 445 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 446 sizeof(struct mlx5_reg_node_desc), 447 MLX5_REG_NODE_DESC, 0, 0); 448 } 449 450 static int mlx5_ib_query_device(struct ib_device *ibdev, 451 struct ib_device_attr *props, 452 struct ib_udata *uhw) 453 { 454 struct mlx5_ib_dev *dev = to_mdev(ibdev); 455 struct mlx5_core_dev *mdev = dev->mdev; 456 int err = -ENOMEM; 457 int max_rq_sg; 458 int max_sq_sg; 459 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 460 461 if (uhw->inlen || uhw->outlen) 462 return -EINVAL; 463 464 memset(props, 0, sizeof(*props)); 465 err = mlx5_query_system_image_guid(ibdev, 466 &props->sys_image_guid); 467 if (err) 468 return err; 469 470 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 471 if (err) 472 return err; 473 474 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 475 if (err) 476 return err; 477 478 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 479 (fw_rev_min(dev->mdev) << 16) | 480 fw_rev_sub(dev->mdev); 481 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 482 IB_DEVICE_PORT_ACTIVE_EVENT | 483 IB_DEVICE_SYS_IMAGE_GUID | 484 IB_DEVICE_RC_RNR_NAK_GEN; 485 486 if (MLX5_CAP_GEN(mdev, pkv)) 487 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 488 if (MLX5_CAP_GEN(mdev, qkv)) 489 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 490 if (MLX5_CAP_GEN(mdev, apm)) 491 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 492 if (MLX5_CAP_GEN(mdev, xrc)) 493 props->device_cap_flags |= IB_DEVICE_XRC; 494 if (MLX5_CAP_GEN(mdev, imaicl)) { 495 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 496 IB_DEVICE_MEM_WINDOW_TYPE_2B; 497 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 498 /* We support 'Gappy' memory registration too */ 499 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 500 } 501 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 502 if (MLX5_CAP_GEN(mdev, sho)) { 503 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 504 /* At this stage no support for signature handover */ 505 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 506 IB_PROT_T10DIF_TYPE_2 | 507 IB_PROT_T10DIF_TYPE_3; 508 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 509 IB_GUARD_T10DIF_CSUM; 510 } 511 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 512 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 513 514 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 515 (MLX5_CAP_ETH(dev->mdev, csum_cap))) 516 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 517 518 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 519 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 520 props->device_cap_flags |= IB_DEVICE_UD_TSO; 521 } 522 523 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 524 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 525 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 526 527 props->vendor_part_id = mdev->pdev->device; 528 props->hw_ver = mdev->pdev->revision; 529 530 props->max_mr_size = ~0ull; 531 props->page_size_cap = ~(min_page_size - 1); 532 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 533 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 534 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 535 sizeof(struct mlx5_wqe_data_seg); 536 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 537 sizeof(struct mlx5_wqe_ctrl_seg)) / 538 sizeof(struct mlx5_wqe_data_seg); 539 props->max_sge = min(max_rq_sg, max_sq_sg); 540 props->max_sge_rd = MLX5_MAX_SGE_RD; 541 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 542 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 543 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 544 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 545 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 546 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 547 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 548 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 549 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 550 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 551 props->max_srq_sge = max_rq_sg - 1; 552 props->max_fast_reg_page_list_len = 553 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 554 get_atomic_caps(dev, props); 555 props->masked_atomic_cap = IB_ATOMIC_NONE; 556 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 557 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 558 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 559 props->max_mcast_grp; 560 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 561 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 562 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 563 564 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 565 if (MLX5_CAP_GEN(mdev, pg)) 566 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 567 props->odp_caps = dev->odp_caps; 568 #endif 569 570 if (MLX5_CAP_GEN(mdev, cd)) 571 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 572 573 if (!mlx5_core_is_pf(mdev)) 574 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 575 576 return 0; 577 } 578 579 enum mlx5_ib_width { 580 MLX5_IB_WIDTH_1X = 1 << 0, 581 MLX5_IB_WIDTH_2X = 1 << 1, 582 MLX5_IB_WIDTH_4X = 1 << 2, 583 MLX5_IB_WIDTH_8X = 1 << 3, 584 MLX5_IB_WIDTH_12X = 1 << 4 585 }; 586 587 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 588 u8 *ib_width) 589 { 590 struct mlx5_ib_dev *dev = to_mdev(ibdev); 591 int err = 0; 592 593 if (active_width & MLX5_IB_WIDTH_1X) { 594 *ib_width = IB_WIDTH_1X; 595 } else if (active_width & MLX5_IB_WIDTH_2X) { 596 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 597 (int)active_width); 598 err = -EINVAL; 599 } else if (active_width & MLX5_IB_WIDTH_4X) { 600 *ib_width = IB_WIDTH_4X; 601 } else if (active_width & MLX5_IB_WIDTH_8X) { 602 *ib_width = IB_WIDTH_8X; 603 } else if (active_width & MLX5_IB_WIDTH_12X) { 604 *ib_width = IB_WIDTH_12X; 605 } else { 606 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 607 (int)active_width); 608 err = -EINVAL; 609 } 610 611 return err; 612 } 613 614 static int mlx5_mtu_to_ib_mtu(int mtu) 615 { 616 switch (mtu) { 617 case 256: return 1; 618 case 512: return 2; 619 case 1024: return 3; 620 case 2048: return 4; 621 case 4096: return 5; 622 default: 623 pr_warn("invalid mtu\n"); 624 return -1; 625 } 626 } 627 628 enum ib_max_vl_num { 629 __IB_MAX_VL_0 = 1, 630 __IB_MAX_VL_0_1 = 2, 631 __IB_MAX_VL_0_3 = 3, 632 __IB_MAX_VL_0_7 = 4, 633 __IB_MAX_VL_0_14 = 5, 634 }; 635 636 enum mlx5_vl_hw_cap { 637 MLX5_VL_HW_0 = 1, 638 MLX5_VL_HW_0_1 = 2, 639 MLX5_VL_HW_0_2 = 3, 640 MLX5_VL_HW_0_3 = 4, 641 MLX5_VL_HW_0_4 = 5, 642 MLX5_VL_HW_0_5 = 6, 643 MLX5_VL_HW_0_6 = 7, 644 MLX5_VL_HW_0_7 = 8, 645 MLX5_VL_HW_0_14 = 15 646 }; 647 648 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 649 u8 *max_vl_num) 650 { 651 switch (vl_hw_cap) { 652 case MLX5_VL_HW_0: 653 *max_vl_num = __IB_MAX_VL_0; 654 break; 655 case MLX5_VL_HW_0_1: 656 *max_vl_num = __IB_MAX_VL_0_1; 657 break; 658 case MLX5_VL_HW_0_3: 659 *max_vl_num = __IB_MAX_VL_0_3; 660 break; 661 case MLX5_VL_HW_0_7: 662 *max_vl_num = __IB_MAX_VL_0_7; 663 break; 664 case MLX5_VL_HW_0_14: 665 *max_vl_num = __IB_MAX_VL_0_14; 666 break; 667 668 default: 669 return -EINVAL; 670 } 671 672 return 0; 673 } 674 675 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 676 struct ib_port_attr *props) 677 { 678 struct mlx5_ib_dev *dev = to_mdev(ibdev); 679 struct mlx5_core_dev *mdev = dev->mdev; 680 struct mlx5_hca_vport_context *rep; 681 u16 max_mtu; 682 u16 oper_mtu; 683 int err; 684 u8 ib_link_width_oper; 685 u8 vl_hw_cap; 686 687 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 688 if (!rep) { 689 err = -ENOMEM; 690 goto out; 691 } 692 693 memset(props, 0, sizeof(*props)); 694 695 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 696 if (err) 697 goto out; 698 699 props->lid = rep->lid; 700 props->lmc = rep->lmc; 701 props->sm_lid = rep->sm_lid; 702 props->sm_sl = rep->sm_sl; 703 props->state = rep->vport_state; 704 props->phys_state = rep->port_physical_state; 705 props->port_cap_flags = rep->cap_mask1; 706 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 707 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 708 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 709 props->bad_pkey_cntr = rep->pkey_violation_counter; 710 props->qkey_viol_cntr = rep->qkey_violation_counter; 711 props->subnet_timeout = rep->subnet_timeout; 712 props->init_type_reply = rep->init_type_reply; 713 props->grh_required = rep->grh_required; 714 715 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 716 if (err) 717 goto out; 718 719 err = translate_active_width(ibdev, ib_link_width_oper, 720 &props->active_width); 721 if (err) 722 goto out; 723 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, 724 port); 725 if (err) 726 goto out; 727 728 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 729 730 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 731 732 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 733 734 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 735 736 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 737 if (err) 738 goto out; 739 740 err = translate_max_vl_num(ibdev, vl_hw_cap, 741 &props->max_vl_num); 742 out: 743 kfree(rep); 744 return err; 745 } 746 747 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 748 struct ib_port_attr *props) 749 { 750 switch (mlx5_get_vport_access_method(ibdev)) { 751 case MLX5_VPORT_ACCESS_METHOD_MAD: 752 return mlx5_query_mad_ifc_port(ibdev, port, props); 753 754 case MLX5_VPORT_ACCESS_METHOD_HCA: 755 return mlx5_query_hca_port(ibdev, port, props); 756 757 case MLX5_VPORT_ACCESS_METHOD_NIC: 758 return mlx5_query_port_roce(ibdev, port, props); 759 760 default: 761 return -EINVAL; 762 } 763 } 764 765 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 766 union ib_gid *gid) 767 { 768 struct mlx5_ib_dev *dev = to_mdev(ibdev); 769 struct mlx5_core_dev *mdev = dev->mdev; 770 771 switch (mlx5_get_vport_access_method(ibdev)) { 772 case MLX5_VPORT_ACCESS_METHOD_MAD: 773 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 774 775 case MLX5_VPORT_ACCESS_METHOD_HCA: 776 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 777 778 default: 779 return -EINVAL; 780 } 781 782 } 783 784 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 785 u16 *pkey) 786 { 787 struct mlx5_ib_dev *dev = to_mdev(ibdev); 788 struct mlx5_core_dev *mdev = dev->mdev; 789 790 switch (mlx5_get_vport_access_method(ibdev)) { 791 case MLX5_VPORT_ACCESS_METHOD_MAD: 792 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 793 794 case MLX5_VPORT_ACCESS_METHOD_HCA: 795 case MLX5_VPORT_ACCESS_METHOD_NIC: 796 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 797 pkey); 798 default: 799 return -EINVAL; 800 } 801 } 802 803 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 804 struct ib_device_modify *props) 805 { 806 struct mlx5_ib_dev *dev = to_mdev(ibdev); 807 struct mlx5_reg_node_desc in; 808 struct mlx5_reg_node_desc out; 809 int err; 810 811 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 812 return -EOPNOTSUPP; 813 814 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 815 return 0; 816 817 /* 818 * If possible, pass node desc to FW, so it can generate 819 * a 144 trap. If cmd fails, just ignore. 820 */ 821 memcpy(&in, props->node_desc, 64); 822 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 823 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 824 if (err) 825 return err; 826 827 memcpy(ibdev->node_desc, props->node_desc, 64); 828 829 return err; 830 } 831 832 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 833 struct ib_port_modify *props) 834 { 835 struct mlx5_ib_dev *dev = to_mdev(ibdev); 836 struct ib_port_attr attr; 837 u32 tmp; 838 int err; 839 840 mutex_lock(&dev->cap_mask_mutex); 841 842 err = mlx5_ib_query_port(ibdev, port, &attr); 843 if (err) 844 goto out; 845 846 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 847 ~props->clr_port_cap_mask; 848 849 err = mlx5_set_port_caps(dev->mdev, port, tmp); 850 851 out: 852 mutex_unlock(&dev->cap_mask_mutex); 853 return err; 854 } 855 856 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 857 struct ib_udata *udata) 858 { 859 struct mlx5_ib_dev *dev = to_mdev(ibdev); 860 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 861 struct mlx5_ib_alloc_ucontext_resp resp = {}; 862 struct mlx5_ib_ucontext *context; 863 struct mlx5_uuar_info *uuari; 864 struct mlx5_uar *uars; 865 int gross_uuars; 866 int num_uars; 867 int ver; 868 int uuarn; 869 int err; 870 int i; 871 size_t reqlen; 872 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 873 max_cqe_version); 874 875 if (!dev->ib_active) 876 return ERR_PTR(-EAGAIN); 877 878 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 879 return ERR_PTR(-EINVAL); 880 881 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 882 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 883 ver = 0; 884 else if (reqlen >= min_req_v2) 885 ver = 2; 886 else 887 return ERR_PTR(-EINVAL); 888 889 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 890 if (err) 891 return ERR_PTR(err); 892 893 if (req.flags) 894 return ERR_PTR(-EINVAL); 895 896 if (req.total_num_uuars > MLX5_MAX_UUARS) 897 return ERR_PTR(-ENOMEM); 898 899 if (req.total_num_uuars == 0) 900 return ERR_PTR(-EINVAL); 901 902 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 903 return ERR_PTR(-EOPNOTSUPP); 904 905 if (reqlen > sizeof(req) && 906 !ib_is_udata_cleared(udata, sizeof(req), 907 reqlen - sizeof(req))) 908 return ERR_PTR(-EOPNOTSUPP); 909 910 req.total_num_uuars = ALIGN(req.total_num_uuars, 911 MLX5_NON_FP_BF_REGS_PER_PAGE); 912 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 913 return ERR_PTR(-EINVAL); 914 915 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 916 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 917 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 918 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 919 resp.cache_line_size = L1_CACHE_BYTES; 920 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 921 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 922 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 923 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 924 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 925 resp.cqe_version = min_t(__u8, 926 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 927 req.max_cqe_version); 928 resp.response_length = min(offsetof(typeof(resp), response_length) + 929 sizeof(resp.response_length), udata->outlen); 930 931 context = kzalloc(sizeof(*context), GFP_KERNEL); 932 if (!context) 933 return ERR_PTR(-ENOMEM); 934 935 uuari = &context->uuari; 936 mutex_init(&uuari->lock); 937 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 938 if (!uars) { 939 err = -ENOMEM; 940 goto out_ctx; 941 } 942 943 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 944 sizeof(*uuari->bitmap), 945 GFP_KERNEL); 946 if (!uuari->bitmap) { 947 err = -ENOMEM; 948 goto out_uar_ctx; 949 } 950 /* 951 * clear all fast path uuars 952 */ 953 for (i = 0; i < gross_uuars; i++) { 954 uuarn = i & 3; 955 if (uuarn == 2 || uuarn == 3) 956 set_bit(i, uuari->bitmap); 957 } 958 959 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 960 if (!uuari->count) { 961 err = -ENOMEM; 962 goto out_bitmap; 963 } 964 965 for (i = 0; i < num_uars; i++) { 966 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 967 if (err) 968 goto out_count; 969 } 970 971 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 972 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 973 #endif 974 975 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 976 err = mlx5_core_alloc_transport_domain(dev->mdev, 977 &context->tdn); 978 if (err) 979 goto out_uars; 980 } 981 982 INIT_LIST_HEAD(&context->db_page_list); 983 mutex_init(&context->db_page_mutex); 984 985 resp.tot_uuars = req.total_num_uuars; 986 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 987 988 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 989 resp.response_length += sizeof(resp.cqe_version); 990 991 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 992 resp.comp_mask |= 993 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 994 resp.hca_core_clock_offset = 995 offsetof(struct mlx5_init_seg, internal_timer_h) % 996 PAGE_SIZE; 997 resp.response_length += sizeof(resp.hca_core_clock_offset) + 998 sizeof(resp.reserved2) + 999 sizeof(resp.reserved3); 1000 } 1001 1002 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1003 if (err) 1004 goto out_td; 1005 1006 uuari->ver = ver; 1007 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1008 uuari->uars = uars; 1009 uuari->num_uars = num_uars; 1010 context->cqe_version = resp.cqe_version; 1011 1012 return &context->ibucontext; 1013 1014 out_td: 1015 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1016 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1017 1018 out_uars: 1019 for (i--; i >= 0; i--) 1020 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1021 out_count: 1022 kfree(uuari->count); 1023 1024 out_bitmap: 1025 kfree(uuari->bitmap); 1026 1027 out_uar_ctx: 1028 kfree(uars); 1029 1030 out_ctx: 1031 kfree(context); 1032 return ERR_PTR(err); 1033 } 1034 1035 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1036 { 1037 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1038 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1039 struct mlx5_uuar_info *uuari = &context->uuari; 1040 int i; 1041 1042 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1043 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1044 1045 for (i = 0; i < uuari->num_uars; i++) { 1046 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1047 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1048 } 1049 1050 kfree(uuari->count); 1051 kfree(uuari->bitmap); 1052 kfree(uuari->uars); 1053 kfree(context); 1054 1055 return 0; 1056 } 1057 1058 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1059 { 1060 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1061 } 1062 1063 static int get_command(unsigned long offset) 1064 { 1065 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1066 } 1067 1068 static int get_arg(unsigned long offset) 1069 { 1070 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1071 } 1072 1073 static int get_index(unsigned long offset) 1074 { 1075 return get_arg(offset); 1076 } 1077 1078 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1079 { 1080 switch (cmd) { 1081 case MLX5_IB_MMAP_WC_PAGE: 1082 return "WC"; 1083 case MLX5_IB_MMAP_REGULAR_PAGE: 1084 return "best effort WC"; 1085 case MLX5_IB_MMAP_NC_PAGE: 1086 return "NC"; 1087 default: 1088 return NULL; 1089 } 1090 } 1091 1092 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1093 struct vm_area_struct *vma, struct mlx5_uuar_info *uuari) 1094 { 1095 int err; 1096 unsigned long idx; 1097 phys_addr_t pfn, pa; 1098 pgprot_t prot; 1099 1100 switch (cmd) { 1101 case MLX5_IB_MMAP_WC_PAGE: 1102 /* Some architectures don't support WC memory */ 1103 #if defined(CONFIG_X86) 1104 if (!pat_enabled()) 1105 return -EPERM; 1106 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1107 return -EPERM; 1108 #endif 1109 /* fall through */ 1110 case MLX5_IB_MMAP_REGULAR_PAGE: 1111 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1112 prot = pgprot_writecombine(vma->vm_page_prot); 1113 break; 1114 case MLX5_IB_MMAP_NC_PAGE: 1115 prot = pgprot_noncached(vma->vm_page_prot); 1116 break; 1117 default: 1118 return -EINVAL; 1119 } 1120 1121 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1122 return -EINVAL; 1123 1124 idx = get_index(vma->vm_pgoff); 1125 if (idx >= uuari->num_uars) 1126 return -EINVAL; 1127 1128 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1129 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1130 1131 vma->vm_page_prot = prot; 1132 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1133 PAGE_SIZE, vma->vm_page_prot); 1134 if (err) { 1135 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1136 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1137 return -EAGAIN; 1138 } 1139 1140 pa = pfn << PAGE_SHIFT; 1141 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1142 vma->vm_start, &pa); 1143 1144 return 0; 1145 } 1146 1147 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1148 { 1149 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1150 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1151 struct mlx5_uuar_info *uuari = &context->uuari; 1152 unsigned long command; 1153 phys_addr_t pfn; 1154 1155 command = get_command(vma->vm_pgoff); 1156 switch (command) { 1157 case MLX5_IB_MMAP_WC_PAGE: 1158 case MLX5_IB_MMAP_NC_PAGE: 1159 case MLX5_IB_MMAP_REGULAR_PAGE: 1160 return uar_mmap(dev, command, vma, uuari); 1161 1162 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1163 return -ENOSYS; 1164 1165 case MLX5_IB_MMAP_CORE_CLOCK: 1166 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1167 return -EINVAL; 1168 1169 if (vma->vm_flags & VM_WRITE) 1170 return -EPERM; 1171 1172 /* Don't expose to user-space information it shouldn't have */ 1173 if (PAGE_SIZE > 4096) 1174 return -EOPNOTSUPP; 1175 1176 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1177 pfn = (dev->mdev->iseg_base + 1178 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1179 PAGE_SHIFT; 1180 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1181 PAGE_SIZE, vma->vm_page_prot)) 1182 return -EAGAIN; 1183 1184 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1185 vma->vm_start, 1186 (unsigned long long)pfn << PAGE_SHIFT); 1187 break; 1188 1189 default: 1190 return -EINVAL; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1197 struct ib_ucontext *context, 1198 struct ib_udata *udata) 1199 { 1200 struct mlx5_ib_alloc_pd_resp resp; 1201 struct mlx5_ib_pd *pd; 1202 int err; 1203 1204 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1205 if (!pd) 1206 return ERR_PTR(-ENOMEM); 1207 1208 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1209 if (err) { 1210 kfree(pd); 1211 return ERR_PTR(err); 1212 } 1213 1214 if (context) { 1215 resp.pdn = pd->pdn; 1216 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1217 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1218 kfree(pd); 1219 return ERR_PTR(-EFAULT); 1220 } 1221 } 1222 1223 return &pd->ibpd; 1224 } 1225 1226 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1227 { 1228 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1229 struct mlx5_ib_pd *mpd = to_mpd(pd); 1230 1231 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1232 kfree(mpd); 1233 1234 return 0; 1235 } 1236 1237 static bool outer_header_zero(u32 *match_criteria) 1238 { 1239 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1240 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1241 outer_headers); 1242 1243 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1244 outer_headers_c + 1, 1245 size - 1); 1246 } 1247 1248 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1249 union ib_flow_spec *ib_spec) 1250 { 1251 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1252 outer_headers); 1253 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1254 outer_headers); 1255 switch (ib_spec->type) { 1256 case IB_FLOW_SPEC_ETH: 1257 if (ib_spec->size != sizeof(ib_spec->eth)) 1258 return -EINVAL; 1259 1260 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1261 dmac_47_16), 1262 ib_spec->eth.mask.dst_mac); 1263 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1264 dmac_47_16), 1265 ib_spec->eth.val.dst_mac); 1266 1267 if (ib_spec->eth.mask.vlan_tag) { 1268 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1269 vlan_tag, 1); 1270 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1271 vlan_tag, 1); 1272 1273 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1274 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1275 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1276 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1277 1278 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1279 first_cfi, 1280 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1281 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1282 first_cfi, 1283 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1284 1285 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1286 first_prio, 1287 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1288 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1289 first_prio, 1290 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1291 } 1292 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1293 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1294 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1295 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1296 break; 1297 case IB_FLOW_SPEC_IPV4: 1298 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1299 return -EINVAL; 1300 1301 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1302 ethertype, 0xffff); 1303 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1304 ethertype, ETH_P_IP); 1305 1306 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1307 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1308 &ib_spec->ipv4.mask.src_ip, 1309 sizeof(ib_spec->ipv4.mask.src_ip)); 1310 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1311 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1312 &ib_spec->ipv4.val.src_ip, 1313 sizeof(ib_spec->ipv4.val.src_ip)); 1314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1315 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1316 &ib_spec->ipv4.mask.dst_ip, 1317 sizeof(ib_spec->ipv4.mask.dst_ip)); 1318 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1319 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1320 &ib_spec->ipv4.val.dst_ip, 1321 sizeof(ib_spec->ipv4.val.dst_ip)); 1322 break; 1323 case IB_FLOW_SPEC_TCP: 1324 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1325 return -EINVAL; 1326 1327 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1328 0xff); 1329 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1330 IPPROTO_TCP); 1331 1332 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1333 ntohs(ib_spec->tcp_udp.mask.src_port)); 1334 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1335 ntohs(ib_spec->tcp_udp.val.src_port)); 1336 1337 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1338 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1339 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1340 ntohs(ib_spec->tcp_udp.val.dst_port)); 1341 break; 1342 case IB_FLOW_SPEC_UDP: 1343 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1344 return -EINVAL; 1345 1346 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1347 0xff); 1348 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1349 IPPROTO_UDP); 1350 1351 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1352 ntohs(ib_spec->tcp_udp.mask.src_port)); 1353 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1354 ntohs(ib_spec->tcp_udp.val.src_port)); 1355 1356 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1357 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1358 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1359 ntohs(ib_spec->tcp_udp.val.dst_port)); 1360 break; 1361 default: 1362 return -EINVAL; 1363 } 1364 1365 return 0; 1366 } 1367 1368 /* If a flow could catch both multicast and unicast packets, 1369 * it won't fall into the multicast flow steering table and this rule 1370 * could steal other multicast packets. 1371 */ 1372 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1373 { 1374 struct ib_flow_spec_eth *eth_spec; 1375 1376 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1377 ib_attr->size < sizeof(struct ib_flow_attr) + 1378 sizeof(struct ib_flow_spec_eth) || 1379 ib_attr->num_of_specs < 1) 1380 return false; 1381 1382 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1383 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1384 eth_spec->size != sizeof(*eth_spec)) 1385 return false; 1386 1387 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1388 is_multicast_ether_addr(eth_spec->val.dst_mac); 1389 } 1390 1391 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1392 { 1393 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1394 bool has_ipv4_spec = false; 1395 bool eth_type_ipv4 = true; 1396 unsigned int spec_index; 1397 1398 /* Validate that ethertype is correct */ 1399 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1400 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1401 ib_spec->eth.mask.ether_type) { 1402 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1403 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1404 eth_type_ipv4 = false; 1405 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1406 has_ipv4_spec = true; 1407 } 1408 ib_spec = (void *)ib_spec + ib_spec->size; 1409 } 1410 return !has_ipv4_spec || eth_type_ipv4; 1411 } 1412 1413 static void put_flow_table(struct mlx5_ib_dev *dev, 1414 struct mlx5_ib_flow_prio *prio, bool ft_added) 1415 { 1416 prio->refcount -= !!ft_added; 1417 if (!prio->refcount) { 1418 mlx5_destroy_flow_table(prio->flow_table); 1419 prio->flow_table = NULL; 1420 } 1421 } 1422 1423 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1424 { 1425 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1426 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1427 struct mlx5_ib_flow_handler, 1428 ibflow); 1429 struct mlx5_ib_flow_handler *iter, *tmp; 1430 1431 mutex_lock(&dev->flow_db.lock); 1432 1433 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1434 mlx5_del_flow_rule(iter->rule); 1435 list_del(&iter->list); 1436 kfree(iter); 1437 } 1438 1439 mlx5_del_flow_rule(handler->rule); 1440 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1441 mutex_unlock(&dev->flow_db.lock); 1442 1443 kfree(handler); 1444 1445 return 0; 1446 } 1447 1448 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1449 { 1450 priority *= 2; 1451 if (!dont_trap) 1452 priority++; 1453 return priority; 1454 } 1455 1456 #define MLX5_FS_MAX_TYPES 10 1457 #define MLX5_FS_MAX_ENTRIES 32000UL 1458 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1459 struct ib_flow_attr *flow_attr) 1460 { 1461 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1462 struct mlx5_flow_namespace *ns = NULL; 1463 struct mlx5_ib_flow_prio *prio; 1464 struct mlx5_flow_table *ft; 1465 int num_entries; 1466 int num_groups; 1467 int priority; 1468 int err = 0; 1469 1470 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1471 if (flow_is_multicast_only(flow_attr) && 1472 !dont_trap) 1473 priority = MLX5_IB_FLOW_MCAST_PRIO; 1474 else 1475 priority = ib_prio_to_core_prio(flow_attr->priority, 1476 dont_trap); 1477 ns = mlx5_get_flow_namespace(dev->mdev, 1478 MLX5_FLOW_NAMESPACE_BYPASS); 1479 num_entries = MLX5_FS_MAX_ENTRIES; 1480 num_groups = MLX5_FS_MAX_TYPES; 1481 prio = &dev->flow_db.prios[priority]; 1482 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1483 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1484 ns = mlx5_get_flow_namespace(dev->mdev, 1485 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1486 build_leftovers_ft_param(&priority, 1487 &num_entries, 1488 &num_groups); 1489 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1490 } 1491 1492 if (!ns) 1493 return ERR_PTR(-ENOTSUPP); 1494 1495 ft = prio->flow_table; 1496 if (!ft) { 1497 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1498 num_entries, 1499 num_groups, 1500 0); 1501 1502 if (!IS_ERR(ft)) { 1503 prio->refcount = 0; 1504 prio->flow_table = ft; 1505 } else { 1506 err = PTR_ERR(ft); 1507 } 1508 } 1509 1510 return err ? ERR_PTR(err) : prio; 1511 } 1512 1513 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1514 struct mlx5_ib_flow_prio *ft_prio, 1515 struct ib_flow_attr *flow_attr, 1516 struct mlx5_flow_destination *dst) 1517 { 1518 struct mlx5_flow_table *ft = ft_prio->flow_table; 1519 struct mlx5_ib_flow_handler *handler; 1520 void *ib_flow = flow_attr + 1; 1521 u8 match_criteria_enable = 0; 1522 unsigned int spec_index; 1523 u32 *match_c; 1524 u32 *match_v; 1525 u32 action; 1526 int err = 0; 1527 1528 if (!is_valid_attr(flow_attr)) 1529 return ERR_PTR(-EINVAL); 1530 1531 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1532 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1533 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1534 if (!handler || !match_c || !match_v) { 1535 err = -ENOMEM; 1536 goto free; 1537 } 1538 1539 INIT_LIST_HEAD(&handler->list); 1540 1541 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1542 err = parse_flow_attr(match_c, match_v, ib_flow); 1543 if (err < 0) 1544 goto free; 1545 1546 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1547 } 1548 1549 /* Outer header support only */ 1550 match_criteria_enable = (!outer_header_zero(match_c)) << 0; 1551 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1552 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1553 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, 1554 match_c, match_v, 1555 action, 1556 MLX5_FS_DEFAULT_FLOW_TAG, 1557 dst); 1558 1559 if (IS_ERR(handler->rule)) { 1560 err = PTR_ERR(handler->rule); 1561 goto free; 1562 } 1563 1564 handler->prio = ft_prio - dev->flow_db.prios; 1565 1566 ft_prio->flow_table = ft; 1567 free: 1568 if (err) 1569 kfree(handler); 1570 kfree(match_c); 1571 kfree(match_v); 1572 return err ? ERR_PTR(err) : handler; 1573 } 1574 1575 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 1576 struct mlx5_ib_flow_prio *ft_prio, 1577 struct ib_flow_attr *flow_attr, 1578 struct mlx5_flow_destination *dst) 1579 { 1580 struct mlx5_ib_flow_handler *handler_dst = NULL; 1581 struct mlx5_ib_flow_handler *handler = NULL; 1582 1583 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 1584 if (!IS_ERR(handler)) { 1585 handler_dst = create_flow_rule(dev, ft_prio, 1586 flow_attr, dst); 1587 if (IS_ERR(handler_dst)) { 1588 mlx5_del_flow_rule(handler->rule); 1589 kfree(handler); 1590 handler = handler_dst; 1591 } else { 1592 list_add(&handler_dst->list, &handler->list); 1593 } 1594 } 1595 1596 return handler; 1597 } 1598 enum { 1599 LEFTOVERS_MC, 1600 LEFTOVERS_UC, 1601 }; 1602 1603 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1604 struct mlx5_ib_flow_prio *ft_prio, 1605 struct ib_flow_attr *flow_attr, 1606 struct mlx5_flow_destination *dst) 1607 { 1608 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1609 struct mlx5_ib_flow_handler *handler = NULL; 1610 1611 static struct { 1612 struct ib_flow_attr flow_attr; 1613 struct ib_flow_spec_eth eth_flow; 1614 } leftovers_specs[] = { 1615 [LEFTOVERS_MC] = { 1616 .flow_attr = { 1617 .num_of_specs = 1, 1618 .size = sizeof(leftovers_specs[0]) 1619 }, 1620 .eth_flow = { 1621 .type = IB_FLOW_SPEC_ETH, 1622 .size = sizeof(struct ib_flow_spec_eth), 1623 .mask = {.dst_mac = {0x1} }, 1624 .val = {.dst_mac = {0x1} } 1625 } 1626 }, 1627 [LEFTOVERS_UC] = { 1628 .flow_attr = { 1629 .num_of_specs = 1, 1630 .size = sizeof(leftovers_specs[0]) 1631 }, 1632 .eth_flow = { 1633 .type = IB_FLOW_SPEC_ETH, 1634 .size = sizeof(struct ib_flow_spec_eth), 1635 .mask = {.dst_mac = {0x1} }, 1636 .val = {.dst_mac = {} } 1637 } 1638 } 1639 }; 1640 1641 handler = create_flow_rule(dev, ft_prio, 1642 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1643 dst); 1644 if (!IS_ERR(handler) && 1645 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1646 handler_ucast = create_flow_rule(dev, ft_prio, 1647 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1648 dst); 1649 if (IS_ERR(handler_ucast)) { 1650 kfree(handler); 1651 handler = handler_ucast; 1652 } else { 1653 list_add(&handler_ucast->list, &handler->list); 1654 } 1655 } 1656 1657 return handler; 1658 } 1659 1660 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1661 struct ib_flow_attr *flow_attr, 1662 int domain) 1663 { 1664 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1665 struct mlx5_ib_flow_handler *handler = NULL; 1666 struct mlx5_flow_destination *dst = NULL; 1667 struct mlx5_ib_flow_prio *ft_prio; 1668 int err; 1669 1670 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1671 return ERR_PTR(-ENOSPC); 1672 1673 if (domain != IB_FLOW_DOMAIN_USER || 1674 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1675 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 1676 return ERR_PTR(-EINVAL); 1677 1678 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1679 if (!dst) 1680 return ERR_PTR(-ENOMEM); 1681 1682 mutex_lock(&dev->flow_db.lock); 1683 1684 ft_prio = get_flow_table(dev, flow_attr); 1685 if (IS_ERR(ft_prio)) { 1686 err = PTR_ERR(ft_prio); 1687 goto unlock; 1688 } 1689 1690 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1691 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; 1692 1693 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1694 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 1695 handler = create_dont_trap_rule(dev, ft_prio, 1696 flow_attr, dst); 1697 } else { 1698 handler = create_flow_rule(dev, ft_prio, flow_attr, 1699 dst); 1700 } 1701 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1702 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1703 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1704 dst); 1705 } else { 1706 err = -EINVAL; 1707 goto destroy_ft; 1708 } 1709 1710 if (IS_ERR(handler)) { 1711 err = PTR_ERR(handler); 1712 handler = NULL; 1713 goto destroy_ft; 1714 } 1715 1716 ft_prio->refcount++; 1717 mutex_unlock(&dev->flow_db.lock); 1718 kfree(dst); 1719 1720 return &handler->ibflow; 1721 1722 destroy_ft: 1723 put_flow_table(dev, ft_prio, false); 1724 unlock: 1725 mutex_unlock(&dev->flow_db.lock); 1726 kfree(dst); 1727 kfree(handler); 1728 return ERR_PTR(err); 1729 } 1730 1731 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1732 { 1733 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1734 int err; 1735 1736 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1737 if (err) 1738 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1739 ibqp->qp_num, gid->raw); 1740 1741 return err; 1742 } 1743 1744 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1745 { 1746 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1747 int err; 1748 1749 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1750 if (err) 1751 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1752 ibqp->qp_num, gid->raw); 1753 1754 return err; 1755 } 1756 1757 static int init_node_data(struct mlx5_ib_dev *dev) 1758 { 1759 int err; 1760 1761 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1762 if (err) 1763 return err; 1764 1765 dev->mdev->rev_id = dev->mdev->pdev->revision; 1766 1767 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1768 } 1769 1770 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1771 char *buf) 1772 { 1773 struct mlx5_ib_dev *dev = 1774 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1775 1776 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1777 } 1778 1779 static ssize_t show_reg_pages(struct device *device, 1780 struct device_attribute *attr, char *buf) 1781 { 1782 struct mlx5_ib_dev *dev = 1783 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1784 1785 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1786 } 1787 1788 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1789 char *buf) 1790 { 1791 struct mlx5_ib_dev *dev = 1792 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1793 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1794 } 1795 1796 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr, 1797 char *buf) 1798 { 1799 struct mlx5_ib_dev *dev = 1800 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1801 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev), 1802 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 1803 } 1804 1805 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1806 char *buf) 1807 { 1808 struct mlx5_ib_dev *dev = 1809 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1810 return sprintf(buf, "%x\n", dev->mdev->rev_id); 1811 } 1812 1813 static ssize_t show_board(struct device *device, struct device_attribute *attr, 1814 char *buf) 1815 { 1816 struct mlx5_ib_dev *dev = 1817 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1818 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 1819 dev->mdev->board_id); 1820 } 1821 1822 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 1823 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 1824 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 1825 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 1826 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 1827 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 1828 1829 static struct device_attribute *mlx5_class_attributes[] = { 1830 &dev_attr_hw_rev, 1831 &dev_attr_fw_ver, 1832 &dev_attr_hca_type, 1833 &dev_attr_board_id, 1834 &dev_attr_fw_pages, 1835 &dev_attr_reg_pages, 1836 }; 1837 1838 static void pkey_change_handler(struct work_struct *work) 1839 { 1840 struct mlx5_ib_port_resources *ports = 1841 container_of(work, struct mlx5_ib_port_resources, 1842 pkey_change_work); 1843 1844 mutex_lock(&ports->devr->mutex); 1845 mlx5_ib_gsi_pkey_change(ports->gsi); 1846 mutex_unlock(&ports->devr->mutex); 1847 } 1848 1849 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 1850 enum mlx5_dev_event event, unsigned long param) 1851 { 1852 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 1853 struct ib_event ibev; 1854 1855 u8 port = 0; 1856 1857 switch (event) { 1858 case MLX5_DEV_EVENT_SYS_ERROR: 1859 ibdev->ib_active = false; 1860 ibev.event = IB_EVENT_DEVICE_FATAL; 1861 break; 1862 1863 case MLX5_DEV_EVENT_PORT_UP: 1864 ibev.event = IB_EVENT_PORT_ACTIVE; 1865 port = (u8)param; 1866 break; 1867 1868 case MLX5_DEV_EVENT_PORT_DOWN: 1869 ibev.event = IB_EVENT_PORT_ERR; 1870 port = (u8)param; 1871 break; 1872 1873 case MLX5_DEV_EVENT_PORT_INITIALIZED: 1874 /* not used by ULPs */ 1875 return; 1876 1877 case MLX5_DEV_EVENT_LID_CHANGE: 1878 ibev.event = IB_EVENT_LID_CHANGE; 1879 port = (u8)param; 1880 break; 1881 1882 case MLX5_DEV_EVENT_PKEY_CHANGE: 1883 ibev.event = IB_EVENT_PKEY_CHANGE; 1884 port = (u8)param; 1885 1886 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 1887 break; 1888 1889 case MLX5_DEV_EVENT_GUID_CHANGE: 1890 ibev.event = IB_EVENT_GID_CHANGE; 1891 port = (u8)param; 1892 break; 1893 1894 case MLX5_DEV_EVENT_CLIENT_REREG: 1895 ibev.event = IB_EVENT_CLIENT_REREGISTER; 1896 port = (u8)param; 1897 break; 1898 } 1899 1900 ibev.device = &ibdev->ib_dev; 1901 ibev.element.port_num = port; 1902 1903 if (port < 1 || port > ibdev->num_ports) { 1904 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 1905 return; 1906 } 1907 1908 if (ibdev->ib_active) 1909 ib_dispatch_event(&ibev); 1910 } 1911 1912 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 1913 { 1914 int port; 1915 1916 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 1917 mlx5_query_ext_port_caps(dev, port); 1918 } 1919 1920 static int get_port_caps(struct mlx5_ib_dev *dev) 1921 { 1922 struct ib_device_attr *dprops = NULL; 1923 struct ib_port_attr *pprops = NULL; 1924 int err = -ENOMEM; 1925 int port; 1926 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 1927 1928 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 1929 if (!pprops) 1930 goto out; 1931 1932 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 1933 if (!dprops) 1934 goto out; 1935 1936 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 1937 if (err) { 1938 mlx5_ib_warn(dev, "query_device failed %d\n", err); 1939 goto out; 1940 } 1941 1942 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 1943 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 1944 if (err) { 1945 mlx5_ib_warn(dev, "query_port %d failed %d\n", 1946 port, err); 1947 break; 1948 } 1949 dev->mdev->port_caps[port - 1].pkey_table_len = 1950 dprops->max_pkeys; 1951 dev->mdev->port_caps[port - 1].gid_table_len = 1952 pprops->gid_tbl_len; 1953 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 1954 dprops->max_pkeys, pprops->gid_tbl_len); 1955 } 1956 1957 out: 1958 kfree(pprops); 1959 kfree(dprops); 1960 1961 return err; 1962 } 1963 1964 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 1965 { 1966 int err; 1967 1968 err = mlx5_mr_cache_cleanup(dev); 1969 if (err) 1970 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 1971 1972 mlx5_ib_destroy_qp(dev->umrc.qp); 1973 ib_free_cq(dev->umrc.cq); 1974 ib_dealloc_pd(dev->umrc.pd); 1975 } 1976 1977 enum { 1978 MAX_UMR_WR = 128, 1979 }; 1980 1981 static int create_umr_res(struct mlx5_ib_dev *dev) 1982 { 1983 struct ib_qp_init_attr *init_attr = NULL; 1984 struct ib_qp_attr *attr = NULL; 1985 struct ib_pd *pd; 1986 struct ib_cq *cq; 1987 struct ib_qp *qp; 1988 int ret; 1989 1990 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 1991 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 1992 if (!attr || !init_attr) { 1993 ret = -ENOMEM; 1994 goto error_0; 1995 } 1996 1997 pd = ib_alloc_pd(&dev->ib_dev); 1998 if (IS_ERR(pd)) { 1999 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2000 ret = PTR_ERR(pd); 2001 goto error_0; 2002 } 2003 2004 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2005 if (IS_ERR(cq)) { 2006 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2007 ret = PTR_ERR(cq); 2008 goto error_2; 2009 } 2010 2011 init_attr->send_cq = cq; 2012 init_attr->recv_cq = cq; 2013 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2014 init_attr->cap.max_send_wr = MAX_UMR_WR; 2015 init_attr->cap.max_send_sge = 1; 2016 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2017 init_attr->port_num = 1; 2018 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2019 if (IS_ERR(qp)) { 2020 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2021 ret = PTR_ERR(qp); 2022 goto error_3; 2023 } 2024 qp->device = &dev->ib_dev; 2025 qp->real_qp = qp; 2026 qp->uobject = NULL; 2027 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2028 2029 attr->qp_state = IB_QPS_INIT; 2030 attr->port_num = 1; 2031 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2032 IB_QP_PORT, NULL); 2033 if (ret) { 2034 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2035 goto error_4; 2036 } 2037 2038 memset(attr, 0, sizeof(*attr)); 2039 attr->qp_state = IB_QPS_RTR; 2040 attr->path_mtu = IB_MTU_256; 2041 2042 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2043 if (ret) { 2044 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2045 goto error_4; 2046 } 2047 2048 memset(attr, 0, sizeof(*attr)); 2049 attr->qp_state = IB_QPS_RTS; 2050 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2051 if (ret) { 2052 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2053 goto error_4; 2054 } 2055 2056 dev->umrc.qp = qp; 2057 dev->umrc.cq = cq; 2058 dev->umrc.pd = pd; 2059 2060 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2061 ret = mlx5_mr_cache_init(dev); 2062 if (ret) { 2063 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2064 goto error_4; 2065 } 2066 2067 kfree(attr); 2068 kfree(init_attr); 2069 2070 return 0; 2071 2072 error_4: 2073 mlx5_ib_destroy_qp(qp); 2074 2075 error_3: 2076 ib_free_cq(cq); 2077 2078 error_2: 2079 ib_dealloc_pd(pd); 2080 2081 error_0: 2082 kfree(attr); 2083 kfree(init_attr); 2084 return ret; 2085 } 2086 2087 static int create_dev_resources(struct mlx5_ib_resources *devr) 2088 { 2089 struct ib_srq_init_attr attr; 2090 struct mlx5_ib_dev *dev; 2091 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2092 int port; 2093 int ret = 0; 2094 2095 dev = container_of(devr, struct mlx5_ib_dev, devr); 2096 2097 mutex_init(&devr->mutex); 2098 2099 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2100 if (IS_ERR(devr->p0)) { 2101 ret = PTR_ERR(devr->p0); 2102 goto error0; 2103 } 2104 devr->p0->device = &dev->ib_dev; 2105 devr->p0->uobject = NULL; 2106 atomic_set(&devr->p0->usecnt, 0); 2107 2108 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2109 if (IS_ERR(devr->c0)) { 2110 ret = PTR_ERR(devr->c0); 2111 goto error1; 2112 } 2113 devr->c0->device = &dev->ib_dev; 2114 devr->c0->uobject = NULL; 2115 devr->c0->comp_handler = NULL; 2116 devr->c0->event_handler = NULL; 2117 devr->c0->cq_context = NULL; 2118 atomic_set(&devr->c0->usecnt, 0); 2119 2120 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2121 if (IS_ERR(devr->x0)) { 2122 ret = PTR_ERR(devr->x0); 2123 goto error2; 2124 } 2125 devr->x0->device = &dev->ib_dev; 2126 devr->x0->inode = NULL; 2127 atomic_set(&devr->x0->usecnt, 0); 2128 mutex_init(&devr->x0->tgt_qp_mutex); 2129 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2130 2131 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2132 if (IS_ERR(devr->x1)) { 2133 ret = PTR_ERR(devr->x1); 2134 goto error3; 2135 } 2136 devr->x1->device = &dev->ib_dev; 2137 devr->x1->inode = NULL; 2138 atomic_set(&devr->x1->usecnt, 0); 2139 mutex_init(&devr->x1->tgt_qp_mutex); 2140 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2141 2142 memset(&attr, 0, sizeof(attr)); 2143 attr.attr.max_sge = 1; 2144 attr.attr.max_wr = 1; 2145 attr.srq_type = IB_SRQT_XRC; 2146 attr.ext.xrc.cq = devr->c0; 2147 attr.ext.xrc.xrcd = devr->x0; 2148 2149 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2150 if (IS_ERR(devr->s0)) { 2151 ret = PTR_ERR(devr->s0); 2152 goto error4; 2153 } 2154 devr->s0->device = &dev->ib_dev; 2155 devr->s0->pd = devr->p0; 2156 devr->s0->uobject = NULL; 2157 devr->s0->event_handler = NULL; 2158 devr->s0->srq_context = NULL; 2159 devr->s0->srq_type = IB_SRQT_XRC; 2160 devr->s0->ext.xrc.xrcd = devr->x0; 2161 devr->s0->ext.xrc.cq = devr->c0; 2162 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2163 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2164 atomic_inc(&devr->p0->usecnt); 2165 atomic_set(&devr->s0->usecnt, 0); 2166 2167 memset(&attr, 0, sizeof(attr)); 2168 attr.attr.max_sge = 1; 2169 attr.attr.max_wr = 1; 2170 attr.srq_type = IB_SRQT_BASIC; 2171 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2172 if (IS_ERR(devr->s1)) { 2173 ret = PTR_ERR(devr->s1); 2174 goto error5; 2175 } 2176 devr->s1->device = &dev->ib_dev; 2177 devr->s1->pd = devr->p0; 2178 devr->s1->uobject = NULL; 2179 devr->s1->event_handler = NULL; 2180 devr->s1->srq_context = NULL; 2181 devr->s1->srq_type = IB_SRQT_BASIC; 2182 devr->s1->ext.xrc.cq = devr->c0; 2183 atomic_inc(&devr->p0->usecnt); 2184 atomic_set(&devr->s0->usecnt, 0); 2185 2186 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2187 INIT_WORK(&devr->ports[port].pkey_change_work, 2188 pkey_change_handler); 2189 devr->ports[port].devr = devr; 2190 } 2191 2192 return 0; 2193 2194 error5: 2195 mlx5_ib_destroy_srq(devr->s0); 2196 error4: 2197 mlx5_ib_dealloc_xrcd(devr->x1); 2198 error3: 2199 mlx5_ib_dealloc_xrcd(devr->x0); 2200 error2: 2201 mlx5_ib_destroy_cq(devr->c0); 2202 error1: 2203 mlx5_ib_dealloc_pd(devr->p0); 2204 error0: 2205 return ret; 2206 } 2207 2208 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2209 { 2210 struct mlx5_ib_dev *dev = 2211 container_of(devr, struct mlx5_ib_dev, devr); 2212 int port; 2213 2214 mlx5_ib_destroy_srq(devr->s1); 2215 mlx5_ib_destroy_srq(devr->s0); 2216 mlx5_ib_dealloc_xrcd(devr->x0); 2217 mlx5_ib_dealloc_xrcd(devr->x1); 2218 mlx5_ib_destroy_cq(devr->c0); 2219 mlx5_ib_dealloc_pd(devr->p0); 2220 2221 /* Make sure no change P_Key work items are still executing */ 2222 for (port = 0; port < dev->num_ports; ++port) 2223 cancel_work_sync(&devr->ports[port].pkey_change_work); 2224 } 2225 2226 static u32 get_core_cap_flags(struct ib_device *ibdev) 2227 { 2228 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2229 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2230 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2231 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2232 u32 ret = 0; 2233 2234 if (ll == IB_LINK_LAYER_INFINIBAND) 2235 return RDMA_CORE_PORT_IBA_IB; 2236 2237 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2238 return 0; 2239 2240 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2241 return 0; 2242 2243 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2244 ret |= RDMA_CORE_PORT_IBA_ROCE; 2245 2246 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2247 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2248 2249 return ret; 2250 } 2251 2252 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2253 struct ib_port_immutable *immutable) 2254 { 2255 struct ib_port_attr attr; 2256 int err; 2257 2258 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2259 if (err) 2260 return err; 2261 2262 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2263 immutable->gid_tbl_len = attr.gid_tbl_len; 2264 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2265 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2266 2267 return 0; 2268 } 2269 2270 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2271 { 2272 int err; 2273 2274 dev->roce.nb.notifier_call = mlx5_netdev_event; 2275 err = register_netdevice_notifier(&dev->roce.nb); 2276 if (err) 2277 return err; 2278 2279 err = mlx5_nic_vport_enable_roce(dev->mdev); 2280 if (err) 2281 goto err_unregister_netdevice_notifier; 2282 2283 return 0; 2284 2285 err_unregister_netdevice_notifier: 2286 unregister_netdevice_notifier(&dev->roce.nb); 2287 return err; 2288 } 2289 2290 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2291 { 2292 mlx5_nic_vport_disable_roce(dev->mdev); 2293 unregister_netdevice_notifier(&dev->roce.nb); 2294 } 2295 2296 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2297 { 2298 struct mlx5_ib_dev *dev; 2299 enum rdma_link_layer ll; 2300 int port_type_cap; 2301 int err; 2302 int i; 2303 2304 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2305 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2306 2307 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2308 return NULL; 2309 2310 printk_once(KERN_INFO "%s", mlx5_version); 2311 2312 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2313 if (!dev) 2314 return NULL; 2315 2316 dev->mdev = mdev; 2317 2318 rwlock_init(&dev->roce.netdev_lock); 2319 err = get_port_caps(dev); 2320 if (err) 2321 goto err_dealloc; 2322 2323 if (mlx5_use_mad_ifc(dev)) 2324 get_ext_port_caps(dev); 2325 2326 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2327 2328 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2329 dev->ib_dev.owner = THIS_MODULE; 2330 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2331 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2332 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2333 dev->ib_dev.phys_port_cnt = dev->num_ports; 2334 dev->ib_dev.num_comp_vectors = 2335 dev->mdev->priv.eq_table.num_comp_vectors; 2336 dev->ib_dev.dma_device = &mdev->pdev->dev; 2337 2338 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2339 dev->ib_dev.uverbs_cmd_mask = 2340 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2341 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2342 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2343 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2344 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2345 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2346 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2347 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2348 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2349 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2350 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2351 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2352 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2353 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2354 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2355 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2356 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2357 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2358 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2359 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2360 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2361 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2362 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2363 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2364 dev->ib_dev.uverbs_ex_cmd_mask = 2365 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2366 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2367 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2368 2369 dev->ib_dev.query_device = mlx5_ib_query_device; 2370 dev->ib_dev.query_port = mlx5_ib_query_port; 2371 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2372 if (ll == IB_LINK_LAYER_ETHERNET) 2373 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2374 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2375 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2376 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2377 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2378 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2379 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2380 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2381 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2382 dev->ib_dev.mmap = mlx5_ib_mmap; 2383 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2384 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2385 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2386 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2387 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2388 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2389 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2390 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2391 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2392 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2393 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2394 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2395 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2396 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2397 dev->ib_dev.post_send = mlx5_ib_post_send; 2398 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2399 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2400 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2401 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2402 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2403 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2404 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2405 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2406 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2407 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 2408 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2409 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2410 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2411 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2412 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2413 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2414 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2415 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2416 if (mlx5_core_is_pf(mdev)) { 2417 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 2418 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 2419 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 2420 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 2421 } 2422 2423 mlx5_ib_internal_fill_odp_caps(dev); 2424 2425 if (MLX5_CAP_GEN(mdev, imaicl)) { 2426 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 2427 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 2428 dev->ib_dev.uverbs_cmd_mask |= 2429 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2430 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2431 } 2432 2433 if (MLX5_CAP_GEN(mdev, xrc)) { 2434 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2435 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2436 dev->ib_dev.uverbs_cmd_mask |= 2437 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2438 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2439 } 2440 2441 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2442 IB_LINK_LAYER_ETHERNET) { 2443 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2444 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2445 dev->ib_dev.uverbs_ex_cmd_mask |= 2446 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2447 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2448 } 2449 err = init_node_data(dev); 2450 if (err) 2451 goto err_dealloc; 2452 2453 mutex_init(&dev->flow_db.lock); 2454 mutex_init(&dev->cap_mask_mutex); 2455 2456 if (ll == IB_LINK_LAYER_ETHERNET) { 2457 err = mlx5_enable_roce(dev); 2458 if (err) 2459 goto err_dealloc; 2460 } 2461 2462 err = create_dev_resources(&dev->devr); 2463 if (err) 2464 goto err_disable_roce; 2465 2466 err = mlx5_ib_odp_init_one(dev); 2467 if (err) 2468 goto err_rsrc; 2469 2470 err = ib_register_device(&dev->ib_dev, NULL); 2471 if (err) 2472 goto err_odp; 2473 2474 err = create_umr_res(dev); 2475 if (err) 2476 goto err_dev; 2477 2478 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2479 err = device_create_file(&dev->ib_dev.dev, 2480 mlx5_class_attributes[i]); 2481 if (err) 2482 goto err_umrc; 2483 } 2484 2485 dev->ib_active = true; 2486 2487 return dev; 2488 2489 err_umrc: 2490 destroy_umrc_res(dev); 2491 2492 err_dev: 2493 ib_unregister_device(&dev->ib_dev); 2494 2495 err_odp: 2496 mlx5_ib_odp_remove_one(dev); 2497 2498 err_rsrc: 2499 destroy_dev_resources(&dev->devr); 2500 2501 err_disable_roce: 2502 if (ll == IB_LINK_LAYER_ETHERNET) 2503 mlx5_disable_roce(dev); 2504 2505 err_dealloc: 2506 ib_dealloc_device((struct ib_device *)dev); 2507 2508 return NULL; 2509 } 2510 2511 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2512 { 2513 struct mlx5_ib_dev *dev = context; 2514 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2515 2516 ib_unregister_device(&dev->ib_dev); 2517 destroy_umrc_res(dev); 2518 mlx5_ib_odp_remove_one(dev); 2519 destroy_dev_resources(&dev->devr); 2520 if (ll == IB_LINK_LAYER_ETHERNET) 2521 mlx5_disable_roce(dev); 2522 ib_dealloc_device(&dev->ib_dev); 2523 } 2524 2525 static struct mlx5_interface mlx5_ib_interface = { 2526 .add = mlx5_ib_add, 2527 .remove = mlx5_ib_remove, 2528 .event = mlx5_ib_event, 2529 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2530 }; 2531 2532 static int __init mlx5_ib_init(void) 2533 { 2534 int err; 2535 2536 if (deprecated_prof_sel != 2) 2537 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2538 2539 err = mlx5_ib_odp_init(); 2540 if (err) 2541 return err; 2542 2543 err = mlx5_register_interface(&mlx5_ib_interface); 2544 if (err) 2545 goto clean_odp; 2546 2547 return err; 2548 2549 clean_odp: 2550 mlx5_ib_odp_cleanup(); 2551 return err; 2552 } 2553 2554 static void __exit mlx5_ib_cleanup(void) 2555 { 2556 mlx5_unregister_interface(&mlx5_ib_interface); 2557 mlx5_ib_odp_cleanup(); 2558 } 2559 2560 module_init(mlx5_ib_init); 2561 module_exit(mlx5_ib_cleanup); 2562