1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include "srq.h" 64 #include <linux/mlx5/fs_helpers.h> 65 #include <linux/mlx5/accel.h> 66 #include <rdma/uverbs_std_types.h> 67 #include <rdma/mlx5_user_ioctl_verbs.h> 68 #include <rdma/mlx5_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME mlx5_ib 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #define DRIVER_NAME "mlx5_ib" 74 #define DRIVER_VERSION "5.0-0" 75 76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 78 MODULE_LICENSE("Dual BSD/GPL"); 79 80 static char mlx5_version[] = 81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 82 DRIVER_VERSION "\n"; 83 84 struct mlx5_ib_event_work { 85 struct work_struct work; 86 union { 87 struct mlx5_ib_dev *dev; 88 struct mlx5_ib_multiport_info *mpi; 89 }; 90 bool is_slave; 91 unsigned int event; 92 void *param; 93 }; 94 95 enum { 96 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 97 }; 98 99 static struct workqueue_struct *mlx5_ib_event_wq; 100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 101 static LIST_HEAD(mlx5_ib_dev_list); 102 /* 103 * This mutex should be held when accessing either of the above lists 104 */ 105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 106 107 /* We can't use an array for xlt_emergency_page because dma_map_single 108 * doesn't work on kernel modules memory 109 */ 110 static unsigned long xlt_emergency_page; 111 static struct mutex xlt_emergency_page_mutex; 112 113 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 114 { 115 struct mlx5_ib_dev *dev; 116 117 mutex_lock(&mlx5_ib_multiport_mutex); 118 dev = mpi->ibdev; 119 mutex_unlock(&mlx5_ib_multiport_mutex); 120 return dev; 121 } 122 123 static enum rdma_link_layer 124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 125 { 126 switch (port_type_cap) { 127 case MLX5_CAP_PORT_TYPE_IB: 128 return IB_LINK_LAYER_INFINIBAND; 129 case MLX5_CAP_PORT_TYPE_ETH: 130 return IB_LINK_LAYER_ETHERNET; 131 default: 132 return IB_LINK_LAYER_UNSPECIFIED; 133 } 134 } 135 136 static enum rdma_link_layer 137 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 141 142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 143 } 144 145 static int get_port_state(struct ib_device *ibdev, 146 u8 port_num, 147 enum ib_port_state *state) 148 { 149 struct ib_port_attr attr; 150 int ret; 151 152 memset(&attr, 0, sizeof(attr)); 153 ret = ibdev->query_port(ibdev, port_num, &attr); 154 if (!ret) 155 *state = attr.state; 156 return ret; 157 } 158 159 static int mlx5_netdev_event(struct notifier_block *this, 160 unsigned long event, void *ptr) 161 { 162 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 163 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 164 u8 port_num = roce->native_port_num; 165 struct mlx5_core_dev *mdev; 166 struct mlx5_ib_dev *ibdev; 167 168 ibdev = roce->dev; 169 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 170 if (!mdev) 171 return NOTIFY_DONE; 172 173 switch (event) { 174 case NETDEV_REGISTER: 175 case NETDEV_UNREGISTER: 176 write_lock(&roce->netdev_lock); 177 if (ibdev->rep) { 178 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 179 struct net_device *rep_ndev; 180 181 rep_ndev = mlx5_ib_get_rep_netdev(esw, 182 ibdev->rep->vport); 183 if (rep_ndev == ndev) 184 roce->netdev = (event == NETDEV_UNREGISTER) ? 185 NULL : ndev; 186 } else if (ndev->dev.parent == &mdev->pdev->dev) { 187 roce->netdev = (event == NETDEV_UNREGISTER) ? 188 NULL : ndev; 189 } 190 write_unlock(&roce->netdev_lock); 191 break; 192 193 case NETDEV_CHANGE: 194 case NETDEV_UP: 195 case NETDEV_DOWN: { 196 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 197 struct net_device *upper = NULL; 198 199 if (lag_ndev) { 200 upper = netdev_master_upper_dev_get(lag_ndev); 201 dev_put(lag_ndev); 202 } 203 204 if ((upper == ndev || (!upper && ndev == roce->netdev)) 205 && ibdev->ib_active) { 206 struct ib_event ibev = { }; 207 enum ib_port_state port_state; 208 209 if (get_port_state(&ibdev->ib_dev, port_num, 210 &port_state)) 211 goto done; 212 213 if (roce->last_port_state == port_state) 214 goto done; 215 216 roce->last_port_state = port_state; 217 ibev.device = &ibdev->ib_dev; 218 if (port_state == IB_PORT_DOWN) 219 ibev.event = IB_EVENT_PORT_ERR; 220 else if (port_state == IB_PORT_ACTIVE) 221 ibev.event = IB_EVENT_PORT_ACTIVE; 222 else 223 goto done; 224 225 ibev.element.port_num = port_num; 226 ib_dispatch_event(&ibev); 227 } 228 break; 229 } 230 231 default: 232 break; 233 } 234 done: 235 mlx5_ib_put_native_port_mdev(ibdev, port_num); 236 return NOTIFY_DONE; 237 } 238 239 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 240 u8 port_num) 241 { 242 struct mlx5_ib_dev *ibdev = to_mdev(device); 243 struct net_device *ndev; 244 struct mlx5_core_dev *mdev; 245 246 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 247 if (!mdev) 248 return NULL; 249 250 ndev = mlx5_lag_get_roce_netdev(mdev); 251 if (ndev) 252 goto out; 253 254 /* Ensure ndev does not disappear before we invoke dev_hold() 255 */ 256 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 257 ndev = ibdev->roce[port_num - 1].netdev; 258 if (ndev) 259 dev_hold(ndev); 260 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 261 262 out: 263 mlx5_ib_put_native_port_mdev(ibdev, port_num); 264 return ndev; 265 } 266 267 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 268 u8 ib_port_num, 269 u8 *native_port_num) 270 { 271 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 272 ib_port_num); 273 struct mlx5_core_dev *mdev = NULL; 274 struct mlx5_ib_multiport_info *mpi; 275 struct mlx5_ib_port *port; 276 277 if (!mlx5_core_mp_enabled(ibdev->mdev) || 278 ll != IB_LINK_LAYER_ETHERNET) { 279 if (native_port_num) 280 *native_port_num = ib_port_num; 281 return ibdev->mdev; 282 } 283 284 if (native_port_num) 285 *native_port_num = 1; 286 287 port = &ibdev->port[ib_port_num - 1]; 288 if (!port) 289 return NULL; 290 291 spin_lock(&port->mp.mpi_lock); 292 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 293 if (mpi && !mpi->unaffiliate) { 294 mdev = mpi->mdev; 295 /* If it's the master no need to refcount, it'll exist 296 * as long as the ib_dev exists. 297 */ 298 if (!mpi->is_master) 299 mpi->mdev_refcnt++; 300 } 301 spin_unlock(&port->mp.mpi_lock); 302 303 return mdev; 304 } 305 306 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 307 { 308 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 309 port_num); 310 struct mlx5_ib_multiport_info *mpi; 311 struct mlx5_ib_port *port; 312 313 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 314 return; 315 316 port = &ibdev->port[port_num - 1]; 317 318 spin_lock(&port->mp.mpi_lock); 319 mpi = ibdev->port[port_num - 1].mp.mpi; 320 if (mpi->is_master) 321 goto out; 322 323 mpi->mdev_refcnt--; 324 if (mpi->unaffiliate) 325 complete(&mpi->unref_comp); 326 out: 327 spin_unlock(&port->mp.mpi_lock); 328 } 329 330 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 331 u8 *active_width) 332 { 333 switch (eth_proto_oper) { 334 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 335 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 336 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 337 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 338 *active_width = IB_WIDTH_1X; 339 *active_speed = IB_SPEED_SDR; 340 break; 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 344 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 348 *active_width = IB_WIDTH_1X; 349 *active_speed = IB_SPEED_QDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 352 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 353 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 354 *active_width = IB_WIDTH_1X; 355 *active_speed = IB_SPEED_EDR; 356 break; 357 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 358 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 359 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 360 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 361 *active_width = IB_WIDTH_4X; 362 *active_speed = IB_SPEED_QDR; 363 break; 364 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 365 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 366 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 367 *active_width = IB_WIDTH_1X; 368 *active_speed = IB_SPEED_HDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 371 *active_width = IB_WIDTH_4X; 372 *active_speed = IB_SPEED_FDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 375 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 376 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 377 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 378 *active_width = IB_WIDTH_4X; 379 *active_speed = IB_SPEED_EDR; 380 break; 381 default: 382 return -EINVAL; 383 } 384 385 return 0; 386 } 387 388 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 389 struct ib_port_attr *props) 390 { 391 struct mlx5_ib_dev *dev = to_mdev(device); 392 struct mlx5_core_dev *mdev; 393 struct net_device *ndev, *upper; 394 enum ib_mtu ndev_ib_mtu; 395 bool put_mdev = true; 396 u16 qkey_viol_cntr; 397 u32 eth_prot_oper; 398 u8 mdev_port_num; 399 int err; 400 401 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 402 if (!mdev) { 403 /* This means the port isn't affiliated yet. Get the 404 * info for the master port instead. 405 */ 406 put_mdev = false; 407 mdev = dev->mdev; 408 mdev_port_num = 1; 409 port_num = 1; 410 } 411 412 /* Possible bad flows are checked before filling out props so in case 413 * of an error it will still be zeroed out. 414 */ 415 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 416 mdev_port_num); 417 if (err) 418 goto out; 419 420 props->active_width = IB_WIDTH_4X; 421 props->active_speed = IB_SPEED_QDR; 422 423 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 424 &props->active_width); 425 426 props->port_cap_flags |= IB_PORT_CM_SUP; 427 props->ip_gids = true; 428 429 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 430 roce_address_table_size); 431 props->max_mtu = IB_MTU_4096; 432 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 433 props->pkey_tbl_len = 1; 434 props->state = IB_PORT_DOWN; 435 props->phys_state = 3; 436 437 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 438 props->qkey_viol_cntr = qkey_viol_cntr; 439 440 /* If this is a stub query for an unaffiliated port stop here */ 441 if (!put_mdev) 442 goto out; 443 444 ndev = mlx5_ib_get_netdev(device, port_num); 445 if (!ndev) 446 goto out; 447 448 if (dev->lag_active) { 449 rcu_read_lock(); 450 upper = netdev_master_upper_dev_get_rcu(ndev); 451 if (upper) { 452 dev_put(ndev); 453 ndev = upper; 454 dev_hold(ndev); 455 } 456 rcu_read_unlock(); 457 } 458 459 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 460 props->state = IB_PORT_ACTIVE; 461 props->phys_state = 5; 462 } 463 464 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 465 466 dev_put(ndev); 467 468 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 469 out: 470 if (put_mdev) 471 mlx5_ib_put_native_port_mdev(dev, port_num); 472 return err; 473 } 474 475 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 476 unsigned int index, const union ib_gid *gid, 477 const struct ib_gid_attr *attr) 478 { 479 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 480 u8 roce_version = 0; 481 u8 roce_l3_type = 0; 482 bool vlan = false; 483 u8 mac[ETH_ALEN]; 484 u16 vlan_id = 0; 485 486 if (gid) { 487 gid_type = attr->gid_type; 488 ether_addr_copy(mac, attr->ndev->dev_addr); 489 490 if (is_vlan_dev(attr->ndev)) { 491 vlan = true; 492 vlan_id = vlan_dev_vlan_id(attr->ndev); 493 } 494 } 495 496 switch (gid_type) { 497 case IB_GID_TYPE_IB: 498 roce_version = MLX5_ROCE_VERSION_1; 499 break; 500 case IB_GID_TYPE_ROCE_UDP_ENCAP: 501 roce_version = MLX5_ROCE_VERSION_2; 502 if (ipv6_addr_v4mapped((void *)gid)) 503 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 504 else 505 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 506 break; 507 508 default: 509 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 510 } 511 512 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 513 roce_l3_type, gid->raw, mac, vlan, 514 vlan_id, port_num); 515 } 516 517 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 518 __always_unused void **context) 519 { 520 return set_roce_addr(to_mdev(attr->device), attr->port_num, 521 attr->index, &attr->gid, attr); 522 } 523 524 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 525 __always_unused void **context) 526 { 527 return set_roce_addr(to_mdev(attr->device), attr->port_num, 528 attr->index, NULL, NULL); 529 } 530 531 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 532 const struct ib_gid_attr *attr) 533 { 534 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 535 return 0; 536 537 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 538 } 539 540 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 541 { 542 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 543 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 544 return 0; 545 } 546 547 enum { 548 MLX5_VPORT_ACCESS_METHOD_MAD, 549 MLX5_VPORT_ACCESS_METHOD_HCA, 550 MLX5_VPORT_ACCESS_METHOD_NIC, 551 }; 552 553 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 554 { 555 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 556 return MLX5_VPORT_ACCESS_METHOD_MAD; 557 558 if (mlx5_ib_port_link_layer(ibdev, 1) == 559 IB_LINK_LAYER_ETHERNET) 560 return MLX5_VPORT_ACCESS_METHOD_NIC; 561 562 return MLX5_VPORT_ACCESS_METHOD_HCA; 563 } 564 565 static void get_atomic_caps(struct mlx5_ib_dev *dev, 566 u8 atomic_size_qp, 567 struct ib_device_attr *props) 568 { 569 u8 tmp; 570 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 571 u8 atomic_req_8B_endianness_mode = 572 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 573 574 /* Check if HW supports 8 bytes standard atomic operations and capable 575 * of host endianness respond 576 */ 577 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 578 if (((atomic_operations & tmp) == tmp) && 579 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 580 (atomic_req_8B_endianness_mode)) { 581 props->atomic_cap = IB_ATOMIC_HCA; 582 } else { 583 props->atomic_cap = IB_ATOMIC_NONE; 584 } 585 } 586 587 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 588 struct ib_device_attr *props) 589 { 590 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 591 592 get_atomic_caps(dev, atomic_size_qp, props); 593 } 594 595 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 596 struct ib_device_attr *props) 597 { 598 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 599 600 get_atomic_caps(dev, atomic_size_qp, props); 601 } 602 603 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 604 { 605 struct ib_device_attr props = {}; 606 607 get_atomic_caps_dc(dev, &props); 608 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 609 } 610 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 611 __be64 *sys_image_guid) 612 { 613 struct mlx5_ib_dev *dev = to_mdev(ibdev); 614 struct mlx5_core_dev *mdev = dev->mdev; 615 u64 tmp; 616 int err; 617 618 switch (mlx5_get_vport_access_method(ibdev)) { 619 case MLX5_VPORT_ACCESS_METHOD_MAD: 620 return mlx5_query_mad_ifc_system_image_guid(ibdev, 621 sys_image_guid); 622 623 case MLX5_VPORT_ACCESS_METHOD_HCA: 624 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 case MLX5_VPORT_ACCESS_METHOD_NIC: 628 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 629 break; 630 631 default: 632 return -EINVAL; 633 } 634 635 if (!err) 636 *sys_image_guid = cpu_to_be64(tmp); 637 638 return err; 639 640 } 641 642 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 643 u16 *max_pkeys) 644 { 645 struct mlx5_ib_dev *dev = to_mdev(ibdev); 646 struct mlx5_core_dev *mdev = dev->mdev; 647 648 switch (mlx5_get_vport_access_method(ibdev)) { 649 case MLX5_VPORT_ACCESS_METHOD_MAD: 650 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 651 652 case MLX5_VPORT_ACCESS_METHOD_HCA: 653 case MLX5_VPORT_ACCESS_METHOD_NIC: 654 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 655 pkey_table_size)); 656 return 0; 657 658 default: 659 return -EINVAL; 660 } 661 } 662 663 static int mlx5_query_vendor_id(struct ib_device *ibdev, 664 u32 *vendor_id) 665 { 666 struct mlx5_ib_dev *dev = to_mdev(ibdev); 667 668 switch (mlx5_get_vport_access_method(ibdev)) { 669 case MLX5_VPORT_ACCESS_METHOD_MAD: 670 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 671 672 case MLX5_VPORT_ACCESS_METHOD_HCA: 673 case MLX5_VPORT_ACCESS_METHOD_NIC: 674 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 675 676 default: 677 return -EINVAL; 678 } 679 } 680 681 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 682 __be64 *node_guid) 683 { 684 u64 tmp; 685 int err; 686 687 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 688 case MLX5_VPORT_ACCESS_METHOD_MAD: 689 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 690 691 case MLX5_VPORT_ACCESS_METHOD_HCA: 692 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 case MLX5_VPORT_ACCESS_METHOD_NIC: 696 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 697 break; 698 699 default: 700 return -EINVAL; 701 } 702 703 if (!err) 704 *node_guid = cpu_to_be64(tmp); 705 706 return err; 707 } 708 709 struct mlx5_reg_node_desc { 710 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 711 }; 712 713 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 714 { 715 struct mlx5_reg_node_desc in; 716 717 if (mlx5_use_mad_ifc(dev)) 718 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 719 720 memset(&in, 0, sizeof(in)); 721 722 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 723 sizeof(struct mlx5_reg_node_desc), 724 MLX5_REG_NODE_DESC, 0, 0); 725 } 726 727 static int mlx5_ib_query_device(struct ib_device *ibdev, 728 struct ib_device_attr *props, 729 struct ib_udata *uhw) 730 { 731 struct mlx5_ib_dev *dev = to_mdev(ibdev); 732 struct mlx5_core_dev *mdev = dev->mdev; 733 int err = -ENOMEM; 734 int max_sq_desc; 735 int max_rq_sg; 736 int max_sq_sg; 737 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 738 bool raw_support = !mlx5_core_mp_enabled(mdev); 739 struct mlx5_ib_query_device_resp resp = {}; 740 size_t resp_len; 741 u64 max_tso; 742 743 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 744 if (uhw->outlen && uhw->outlen < resp_len) 745 return -EINVAL; 746 else 747 resp.response_length = resp_len; 748 749 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 750 return -EINVAL; 751 752 memset(props, 0, sizeof(*props)); 753 err = mlx5_query_system_image_guid(ibdev, 754 &props->sys_image_guid); 755 if (err) 756 return err; 757 758 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 759 if (err) 760 return err; 761 762 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 763 if (err) 764 return err; 765 766 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 767 (fw_rev_min(dev->mdev) << 16) | 768 fw_rev_sub(dev->mdev); 769 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 770 IB_DEVICE_PORT_ACTIVE_EVENT | 771 IB_DEVICE_SYS_IMAGE_GUID | 772 IB_DEVICE_RC_RNR_NAK_GEN; 773 774 if (MLX5_CAP_GEN(mdev, pkv)) 775 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 776 if (MLX5_CAP_GEN(mdev, qkv)) 777 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 778 if (MLX5_CAP_GEN(mdev, apm)) 779 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 780 if (MLX5_CAP_GEN(mdev, xrc)) 781 props->device_cap_flags |= IB_DEVICE_XRC; 782 if (MLX5_CAP_GEN(mdev, imaicl)) { 783 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 784 IB_DEVICE_MEM_WINDOW_TYPE_2B; 785 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 786 /* We support 'Gappy' memory registration too */ 787 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 788 } 789 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 790 if (MLX5_CAP_GEN(mdev, sho)) { 791 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 792 /* At this stage no support for signature handover */ 793 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 794 IB_PROT_T10DIF_TYPE_2 | 795 IB_PROT_T10DIF_TYPE_3; 796 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 797 IB_GUARD_T10DIF_CSUM; 798 } 799 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 800 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 801 802 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 803 if (MLX5_CAP_ETH(mdev, csum_cap)) { 804 /* Legacy bit to support old userspace libraries */ 805 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 806 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 807 } 808 809 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 810 props->raw_packet_caps |= 811 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 812 813 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 814 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 815 if (max_tso) { 816 resp.tso_caps.max_tso = 1 << max_tso; 817 resp.tso_caps.supported_qpts |= 818 1 << IB_QPT_RAW_PACKET; 819 resp.response_length += sizeof(resp.tso_caps); 820 } 821 } 822 823 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 824 resp.rss_caps.rx_hash_function = 825 MLX5_RX_HASH_FUNC_TOEPLITZ; 826 resp.rss_caps.rx_hash_fields_mask = 827 MLX5_RX_HASH_SRC_IPV4 | 828 MLX5_RX_HASH_DST_IPV4 | 829 MLX5_RX_HASH_SRC_IPV6 | 830 MLX5_RX_HASH_DST_IPV6 | 831 MLX5_RX_HASH_SRC_PORT_TCP | 832 MLX5_RX_HASH_DST_PORT_TCP | 833 MLX5_RX_HASH_SRC_PORT_UDP | 834 MLX5_RX_HASH_DST_PORT_UDP | 835 MLX5_RX_HASH_INNER; 836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 837 MLX5_ACCEL_IPSEC_CAP_DEVICE) 838 resp.rss_caps.rx_hash_fields_mask |= 839 MLX5_RX_HASH_IPSEC_SPI; 840 resp.response_length += sizeof(resp.rss_caps); 841 } 842 } else { 843 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 844 resp.response_length += sizeof(resp.tso_caps); 845 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 846 resp.response_length += sizeof(resp.rss_caps); 847 } 848 849 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 850 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 851 props->device_cap_flags |= IB_DEVICE_UD_TSO; 852 } 853 854 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 855 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 856 raw_support) 857 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 858 859 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 860 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 861 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 862 863 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 864 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 865 raw_support) { 866 /* Legacy bit to support old userspace libraries */ 867 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 868 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 869 } 870 871 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 872 props->max_dm_size = 873 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 874 } 875 876 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 877 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 878 879 if (MLX5_CAP_GEN(mdev, end_pad)) 880 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 881 882 props->vendor_part_id = mdev->pdev->device; 883 props->hw_ver = mdev->pdev->revision; 884 885 props->max_mr_size = ~0ull; 886 props->page_size_cap = ~(min_page_size - 1); 887 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 888 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 889 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 890 sizeof(struct mlx5_wqe_data_seg); 891 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 892 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 893 sizeof(struct mlx5_wqe_raddr_seg)) / 894 sizeof(struct mlx5_wqe_data_seg); 895 props->max_send_sge = max_sq_sg; 896 props->max_recv_sge = max_rq_sg; 897 props->max_sge_rd = MLX5_MAX_SGE_RD; 898 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 899 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 900 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 901 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 902 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 903 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 904 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 905 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 906 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 907 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 908 props->max_srq_sge = max_rq_sg - 1; 909 props->max_fast_reg_page_list_len = 910 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 911 get_atomic_caps_qp(dev, props); 912 props->masked_atomic_cap = IB_ATOMIC_NONE; 913 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 914 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 915 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 916 props->max_mcast_grp; 917 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 918 props->max_ah = INT_MAX; 919 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 920 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 921 922 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 923 if (MLX5_CAP_GEN(mdev, pg)) 924 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 925 props->odp_caps = dev->odp_caps; 926 #endif 927 928 if (MLX5_CAP_GEN(mdev, cd)) 929 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 930 931 if (!mlx5_core_is_pf(mdev)) 932 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 933 934 if (mlx5_ib_port_link_layer(ibdev, 1) == 935 IB_LINK_LAYER_ETHERNET && raw_support) { 936 props->rss_caps.max_rwq_indirection_tables = 937 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 938 props->rss_caps.max_rwq_indirection_table_size = 939 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 940 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 941 props->max_wq_type_rq = 942 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 943 } 944 945 if (MLX5_CAP_GEN(mdev, tag_matching)) { 946 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 947 props->tm_caps.max_num_tags = 948 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 949 props->tm_caps.flags = IB_TM_CAP_RC; 950 props->tm_caps.max_ops = 951 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 952 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 953 } 954 955 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 956 props->cq_caps.max_cq_moderation_count = 957 MLX5_MAX_CQ_COUNT; 958 props->cq_caps.max_cq_moderation_period = 959 MLX5_MAX_CQ_PERIOD; 960 } 961 962 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 963 resp.response_length += sizeof(resp.cqe_comp_caps); 964 965 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 966 resp.cqe_comp_caps.max_num = 967 MLX5_CAP_GEN(dev->mdev, 968 cqe_compression_max_num); 969 970 resp.cqe_comp_caps.supported_format = 971 MLX5_IB_CQE_RES_FORMAT_HASH | 972 MLX5_IB_CQE_RES_FORMAT_CSUM; 973 974 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 975 resp.cqe_comp_caps.supported_format |= 976 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 977 } 978 } 979 980 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 981 raw_support) { 982 if (MLX5_CAP_QOS(mdev, packet_pacing) && 983 MLX5_CAP_GEN(mdev, qos)) { 984 resp.packet_pacing_caps.qp_rate_limit_max = 985 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 986 resp.packet_pacing_caps.qp_rate_limit_min = 987 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 988 resp.packet_pacing_caps.supported_qpts |= 989 1 << IB_QPT_RAW_PACKET; 990 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 991 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 992 resp.packet_pacing_caps.cap_flags |= 993 MLX5_IB_PP_SUPPORT_BURST; 994 } 995 resp.response_length += sizeof(resp.packet_pacing_caps); 996 } 997 998 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 999 uhw->outlen)) { 1000 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1001 resp.mlx5_ib_support_multi_pkt_send_wqes = 1002 MLX5_IB_ALLOW_MPW; 1003 1004 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1005 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1006 MLX5_IB_SUPPORT_EMPW; 1007 1008 resp.response_length += 1009 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1010 } 1011 1012 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1013 resp.response_length += sizeof(resp.flags); 1014 1015 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1016 resp.flags |= 1017 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1018 1019 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1020 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1021 } 1022 1023 if (field_avail(typeof(resp), sw_parsing_caps, 1024 uhw->outlen)) { 1025 resp.response_length += sizeof(resp.sw_parsing_caps); 1026 if (MLX5_CAP_ETH(mdev, swp)) { 1027 resp.sw_parsing_caps.sw_parsing_offloads |= 1028 MLX5_IB_SW_PARSING; 1029 1030 if (MLX5_CAP_ETH(mdev, swp_csum)) 1031 resp.sw_parsing_caps.sw_parsing_offloads |= 1032 MLX5_IB_SW_PARSING_CSUM; 1033 1034 if (MLX5_CAP_ETH(mdev, swp_lso)) 1035 resp.sw_parsing_caps.sw_parsing_offloads |= 1036 MLX5_IB_SW_PARSING_LSO; 1037 1038 if (resp.sw_parsing_caps.sw_parsing_offloads) 1039 resp.sw_parsing_caps.supported_qpts = 1040 BIT(IB_QPT_RAW_PACKET); 1041 } 1042 } 1043 1044 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1045 raw_support) { 1046 resp.response_length += sizeof(resp.striding_rq_caps); 1047 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1048 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1049 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1050 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1051 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1052 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1053 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1054 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1055 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1056 resp.striding_rq_caps.supported_qpts = 1057 BIT(IB_QPT_RAW_PACKET); 1058 } 1059 } 1060 1061 if (field_avail(typeof(resp), tunnel_offloads_caps, 1062 uhw->outlen)) { 1063 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1064 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1065 resp.tunnel_offloads_caps |= 1066 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1067 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1068 resp.tunnel_offloads_caps |= 1069 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1070 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1071 resp.tunnel_offloads_caps |= 1072 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1074 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1075 resp.tunnel_offloads_caps |= 1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1077 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1078 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1079 resp.tunnel_offloads_caps |= 1080 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1081 } 1082 1083 if (uhw->outlen) { 1084 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1085 1086 if (err) 1087 return err; 1088 } 1089 1090 return 0; 1091 } 1092 1093 enum mlx5_ib_width { 1094 MLX5_IB_WIDTH_1X = 1 << 0, 1095 MLX5_IB_WIDTH_2X = 1 << 1, 1096 MLX5_IB_WIDTH_4X = 1 << 2, 1097 MLX5_IB_WIDTH_8X = 1 << 3, 1098 MLX5_IB_WIDTH_12X = 1 << 4 1099 }; 1100 1101 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1102 u8 *ib_width) 1103 { 1104 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1105 1106 if (active_width & MLX5_IB_WIDTH_1X) 1107 *ib_width = IB_WIDTH_1X; 1108 else if (active_width & MLX5_IB_WIDTH_4X) 1109 *ib_width = IB_WIDTH_4X; 1110 else if (active_width & MLX5_IB_WIDTH_8X) 1111 *ib_width = IB_WIDTH_8X; 1112 else if (active_width & MLX5_IB_WIDTH_12X) 1113 *ib_width = IB_WIDTH_12X; 1114 else { 1115 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1116 (int)active_width); 1117 *ib_width = IB_WIDTH_4X; 1118 } 1119 1120 return; 1121 } 1122 1123 static int mlx5_mtu_to_ib_mtu(int mtu) 1124 { 1125 switch (mtu) { 1126 case 256: return 1; 1127 case 512: return 2; 1128 case 1024: return 3; 1129 case 2048: return 4; 1130 case 4096: return 5; 1131 default: 1132 pr_warn("invalid mtu\n"); 1133 return -1; 1134 } 1135 } 1136 1137 enum ib_max_vl_num { 1138 __IB_MAX_VL_0 = 1, 1139 __IB_MAX_VL_0_1 = 2, 1140 __IB_MAX_VL_0_3 = 3, 1141 __IB_MAX_VL_0_7 = 4, 1142 __IB_MAX_VL_0_14 = 5, 1143 }; 1144 1145 enum mlx5_vl_hw_cap { 1146 MLX5_VL_HW_0 = 1, 1147 MLX5_VL_HW_0_1 = 2, 1148 MLX5_VL_HW_0_2 = 3, 1149 MLX5_VL_HW_0_3 = 4, 1150 MLX5_VL_HW_0_4 = 5, 1151 MLX5_VL_HW_0_5 = 6, 1152 MLX5_VL_HW_0_6 = 7, 1153 MLX5_VL_HW_0_7 = 8, 1154 MLX5_VL_HW_0_14 = 15 1155 }; 1156 1157 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1158 u8 *max_vl_num) 1159 { 1160 switch (vl_hw_cap) { 1161 case MLX5_VL_HW_0: 1162 *max_vl_num = __IB_MAX_VL_0; 1163 break; 1164 case MLX5_VL_HW_0_1: 1165 *max_vl_num = __IB_MAX_VL_0_1; 1166 break; 1167 case MLX5_VL_HW_0_3: 1168 *max_vl_num = __IB_MAX_VL_0_3; 1169 break; 1170 case MLX5_VL_HW_0_7: 1171 *max_vl_num = __IB_MAX_VL_0_7; 1172 break; 1173 case MLX5_VL_HW_0_14: 1174 *max_vl_num = __IB_MAX_VL_0_14; 1175 break; 1176 1177 default: 1178 return -EINVAL; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1185 struct ib_port_attr *props) 1186 { 1187 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1188 struct mlx5_core_dev *mdev = dev->mdev; 1189 struct mlx5_hca_vport_context *rep; 1190 u16 max_mtu; 1191 u16 oper_mtu; 1192 int err; 1193 u8 ib_link_width_oper; 1194 u8 vl_hw_cap; 1195 1196 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1197 if (!rep) { 1198 err = -ENOMEM; 1199 goto out; 1200 } 1201 1202 /* props being zeroed by the caller, avoid zeroing it here */ 1203 1204 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1205 if (err) 1206 goto out; 1207 1208 props->lid = rep->lid; 1209 props->lmc = rep->lmc; 1210 props->sm_lid = rep->sm_lid; 1211 props->sm_sl = rep->sm_sl; 1212 props->state = rep->vport_state; 1213 props->phys_state = rep->port_physical_state; 1214 props->port_cap_flags = rep->cap_mask1; 1215 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1216 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1217 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1218 props->bad_pkey_cntr = rep->pkey_violation_counter; 1219 props->qkey_viol_cntr = rep->qkey_violation_counter; 1220 props->subnet_timeout = rep->subnet_timeout; 1221 props->init_type_reply = rep->init_type_reply; 1222 1223 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1224 if (err) 1225 goto out; 1226 1227 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1228 1229 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1230 if (err) 1231 goto out; 1232 1233 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1234 1235 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1236 1237 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1238 1239 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1240 1241 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1242 if (err) 1243 goto out; 1244 1245 err = translate_max_vl_num(ibdev, vl_hw_cap, 1246 &props->max_vl_num); 1247 out: 1248 kfree(rep); 1249 return err; 1250 } 1251 1252 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1253 struct ib_port_attr *props) 1254 { 1255 unsigned int count; 1256 int ret; 1257 1258 switch (mlx5_get_vport_access_method(ibdev)) { 1259 case MLX5_VPORT_ACCESS_METHOD_MAD: 1260 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1261 break; 1262 1263 case MLX5_VPORT_ACCESS_METHOD_HCA: 1264 ret = mlx5_query_hca_port(ibdev, port, props); 1265 break; 1266 1267 case MLX5_VPORT_ACCESS_METHOD_NIC: 1268 ret = mlx5_query_port_roce(ibdev, port, props); 1269 break; 1270 1271 default: 1272 ret = -EINVAL; 1273 } 1274 1275 if (!ret && props) { 1276 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1277 struct mlx5_core_dev *mdev; 1278 bool put_mdev = true; 1279 1280 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1281 if (!mdev) { 1282 /* If the port isn't affiliated yet query the master. 1283 * The master and slave will have the same values. 1284 */ 1285 mdev = dev->mdev; 1286 port = 1; 1287 put_mdev = false; 1288 } 1289 count = mlx5_core_reserved_gids_count(mdev); 1290 if (put_mdev) 1291 mlx5_ib_put_native_port_mdev(dev, port); 1292 props->gid_tbl_len -= count; 1293 } 1294 return ret; 1295 } 1296 1297 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1298 struct ib_port_attr *props) 1299 { 1300 int ret; 1301 1302 /* Only link layer == ethernet is valid for representors */ 1303 ret = mlx5_query_port_roce(ibdev, port, props); 1304 if (ret || !props) 1305 return ret; 1306 1307 /* We don't support GIDS */ 1308 props->gid_tbl_len = 0; 1309 1310 return ret; 1311 } 1312 1313 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1314 union ib_gid *gid) 1315 { 1316 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1317 struct mlx5_core_dev *mdev = dev->mdev; 1318 1319 switch (mlx5_get_vport_access_method(ibdev)) { 1320 case MLX5_VPORT_ACCESS_METHOD_MAD: 1321 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1322 1323 case MLX5_VPORT_ACCESS_METHOD_HCA: 1324 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1325 1326 default: 1327 return -EINVAL; 1328 } 1329 1330 } 1331 1332 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1333 u16 index, u16 *pkey) 1334 { 1335 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1336 struct mlx5_core_dev *mdev; 1337 bool put_mdev = true; 1338 u8 mdev_port_num; 1339 int err; 1340 1341 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1342 if (!mdev) { 1343 /* The port isn't affiliated yet, get the PKey from the master 1344 * port. For RoCE the PKey tables will be the same. 1345 */ 1346 put_mdev = false; 1347 mdev = dev->mdev; 1348 mdev_port_num = 1; 1349 } 1350 1351 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1352 index, pkey); 1353 if (put_mdev) 1354 mlx5_ib_put_native_port_mdev(dev, port); 1355 1356 return err; 1357 } 1358 1359 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1360 u16 *pkey) 1361 { 1362 switch (mlx5_get_vport_access_method(ibdev)) { 1363 case MLX5_VPORT_ACCESS_METHOD_MAD: 1364 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1365 1366 case MLX5_VPORT_ACCESS_METHOD_HCA: 1367 case MLX5_VPORT_ACCESS_METHOD_NIC: 1368 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1369 default: 1370 return -EINVAL; 1371 } 1372 } 1373 1374 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1375 struct ib_device_modify *props) 1376 { 1377 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1378 struct mlx5_reg_node_desc in; 1379 struct mlx5_reg_node_desc out; 1380 int err; 1381 1382 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1383 return -EOPNOTSUPP; 1384 1385 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1386 return 0; 1387 1388 /* 1389 * If possible, pass node desc to FW, so it can generate 1390 * a 144 trap. If cmd fails, just ignore. 1391 */ 1392 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1393 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1394 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1395 if (err) 1396 return err; 1397 1398 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1399 1400 return err; 1401 } 1402 1403 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1404 u32 value) 1405 { 1406 struct mlx5_hca_vport_context ctx = {}; 1407 struct mlx5_core_dev *mdev; 1408 u8 mdev_port_num; 1409 int err; 1410 1411 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1412 if (!mdev) 1413 return -ENODEV; 1414 1415 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1416 if (err) 1417 goto out; 1418 1419 if (~ctx.cap_mask1_perm & mask) { 1420 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1421 mask, ctx.cap_mask1_perm); 1422 err = -EINVAL; 1423 goto out; 1424 } 1425 1426 ctx.cap_mask1 = value; 1427 ctx.cap_mask1_perm = mask; 1428 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1429 0, &ctx); 1430 1431 out: 1432 mlx5_ib_put_native_port_mdev(dev, port_num); 1433 1434 return err; 1435 } 1436 1437 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1438 struct ib_port_modify *props) 1439 { 1440 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1441 struct ib_port_attr attr; 1442 u32 tmp; 1443 int err; 1444 u32 change_mask; 1445 u32 value; 1446 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1447 IB_LINK_LAYER_INFINIBAND); 1448 1449 /* CM layer calls ib_modify_port() regardless of the link layer. For 1450 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1451 */ 1452 if (!is_ib) 1453 return 0; 1454 1455 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1456 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1457 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1458 return set_port_caps_atomic(dev, port, change_mask, value); 1459 } 1460 1461 mutex_lock(&dev->cap_mask_mutex); 1462 1463 err = ib_query_port(ibdev, port, &attr); 1464 if (err) 1465 goto out; 1466 1467 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1468 ~props->clr_port_cap_mask; 1469 1470 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1471 1472 out: 1473 mutex_unlock(&dev->cap_mask_mutex); 1474 return err; 1475 } 1476 1477 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1478 { 1479 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1480 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1481 } 1482 1483 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1484 { 1485 /* Large page with non 4k uar support might limit the dynamic size */ 1486 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1487 return MLX5_MIN_DYN_BFREGS; 1488 1489 return MLX5_MAX_DYN_BFREGS; 1490 } 1491 1492 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1493 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1494 struct mlx5_bfreg_info *bfregi) 1495 { 1496 int uars_per_sys_page; 1497 int bfregs_per_sys_page; 1498 int ref_bfregs = req->total_num_bfregs; 1499 1500 if (req->total_num_bfregs == 0) 1501 return -EINVAL; 1502 1503 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1504 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1505 1506 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1507 return -ENOMEM; 1508 1509 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1510 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1511 /* This holds the required static allocation asked by the user */ 1512 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1513 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1514 return -EINVAL; 1515 1516 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1517 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1518 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1519 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1520 1521 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1522 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1523 lib_uar_4k ? "yes" : "no", ref_bfregs, 1524 req->total_num_bfregs, bfregi->total_num_bfregs, 1525 bfregi->num_sys_pages); 1526 1527 return 0; 1528 } 1529 1530 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1531 { 1532 struct mlx5_bfreg_info *bfregi; 1533 int err; 1534 int i; 1535 1536 bfregi = &context->bfregi; 1537 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1538 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1539 if (err) 1540 goto error; 1541 1542 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1543 } 1544 1545 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1546 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1547 1548 return 0; 1549 1550 error: 1551 for (--i; i >= 0; i--) 1552 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1553 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1554 1555 return err; 1556 } 1557 1558 static void deallocate_uars(struct mlx5_ib_dev *dev, 1559 struct mlx5_ib_ucontext *context) 1560 { 1561 struct mlx5_bfreg_info *bfregi; 1562 int i; 1563 1564 bfregi = &context->bfregi; 1565 for (i = 0; i < bfregi->num_sys_pages; i++) 1566 if (i < bfregi->num_static_sys_pages || 1567 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1568 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1569 } 1570 1571 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1572 { 1573 int err = 0; 1574 1575 mutex_lock(&dev->lb.mutex); 1576 if (td) 1577 dev->lb.user_td++; 1578 if (qp) 1579 dev->lb.qps++; 1580 1581 if (dev->lb.user_td == 2 || 1582 dev->lb.qps == 1) { 1583 if (!dev->lb.enabled) { 1584 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1585 dev->lb.enabled = true; 1586 } 1587 } 1588 1589 mutex_unlock(&dev->lb.mutex); 1590 1591 return err; 1592 } 1593 1594 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1595 { 1596 mutex_lock(&dev->lb.mutex); 1597 if (td) 1598 dev->lb.user_td--; 1599 if (qp) 1600 dev->lb.qps--; 1601 1602 if (dev->lb.user_td == 1 && 1603 dev->lb.qps == 0) { 1604 if (dev->lb.enabled) { 1605 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1606 dev->lb.enabled = false; 1607 } 1608 } 1609 1610 mutex_unlock(&dev->lb.mutex); 1611 } 1612 1613 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1614 u16 uid) 1615 { 1616 int err; 1617 1618 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1619 return 0; 1620 1621 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1622 if (err) 1623 return err; 1624 1625 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1626 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1627 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1628 return err; 1629 1630 return mlx5_ib_enable_lb(dev, true, false); 1631 } 1632 1633 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1634 u16 uid) 1635 { 1636 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1637 return; 1638 1639 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1640 1641 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1642 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1643 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1644 return; 1645 1646 mlx5_ib_disable_lb(dev, true, false); 1647 } 1648 1649 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1650 struct ib_udata *udata) 1651 { 1652 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1653 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1654 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1655 struct mlx5_core_dev *mdev = dev->mdev; 1656 struct mlx5_ib_ucontext *context; 1657 struct mlx5_bfreg_info *bfregi; 1658 int ver; 1659 int err; 1660 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1661 max_cqe_version); 1662 u32 dump_fill_mkey; 1663 bool lib_uar_4k; 1664 1665 if (!dev->ib_active) 1666 return ERR_PTR(-EAGAIN); 1667 1668 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1669 ver = 0; 1670 else if (udata->inlen >= min_req_v2) 1671 ver = 2; 1672 else 1673 return ERR_PTR(-EINVAL); 1674 1675 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1676 if (err) 1677 return ERR_PTR(err); 1678 1679 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1680 return ERR_PTR(-EOPNOTSUPP); 1681 1682 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1683 return ERR_PTR(-EOPNOTSUPP); 1684 1685 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1686 MLX5_NON_FP_BFREGS_PER_UAR); 1687 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1688 return ERR_PTR(-EINVAL); 1689 1690 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1691 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1692 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1693 resp.cache_line_size = cache_line_size(); 1694 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1695 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1696 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1697 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1698 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1699 resp.cqe_version = min_t(__u8, 1700 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1701 req.max_cqe_version); 1702 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1703 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1704 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1705 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1706 resp.response_length = min(offsetof(typeof(resp), response_length) + 1707 sizeof(resp.response_length), udata->outlen); 1708 1709 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1710 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1711 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1712 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1713 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1714 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1715 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1716 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1717 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1718 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1719 } 1720 1721 context = kzalloc(sizeof(*context), GFP_KERNEL); 1722 if (!context) 1723 return ERR_PTR(-ENOMEM); 1724 1725 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1726 bfregi = &context->bfregi; 1727 1728 /* updates req->total_num_bfregs */ 1729 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1730 if (err) 1731 goto out_ctx; 1732 1733 mutex_init(&bfregi->lock); 1734 bfregi->lib_uar_4k = lib_uar_4k; 1735 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1736 GFP_KERNEL); 1737 if (!bfregi->count) { 1738 err = -ENOMEM; 1739 goto out_ctx; 1740 } 1741 1742 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1743 sizeof(*bfregi->sys_pages), 1744 GFP_KERNEL); 1745 if (!bfregi->sys_pages) { 1746 err = -ENOMEM; 1747 goto out_count; 1748 } 1749 1750 err = allocate_uars(dev, context); 1751 if (err) 1752 goto out_sys_pages; 1753 1754 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1755 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1756 #endif 1757 1758 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1759 err = mlx5_ib_devx_create(dev); 1760 if (err < 0) 1761 goto out_uars; 1762 context->devx_uid = err; 1763 } 1764 1765 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1766 context->devx_uid); 1767 if (err) 1768 goto out_devx; 1769 1770 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1771 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1772 if (err) 1773 goto out_mdev; 1774 } 1775 1776 INIT_LIST_HEAD(&context->db_page_list); 1777 mutex_init(&context->db_page_mutex); 1778 1779 resp.tot_bfregs = req.total_num_bfregs; 1780 resp.num_ports = dev->num_ports; 1781 1782 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1783 resp.response_length += sizeof(resp.cqe_version); 1784 1785 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1786 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1787 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1788 resp.response_length += sizeof(resp.cmds_supp_uhw); 1789 } 1790 1791 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1792 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1793 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1794 resp.eth_min_inline++; 1795 } 1796 resp.response_length += sizeof(resp.eth_min_inline); 1797 } 1798 1799 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1800 if (mdev->clock_info) 1801 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1802 resp.response_length += sizeof(resp.clock_info_versions); 1803 } 1804 1805 /* 1806 * We don't want to expose information from the PCI bar that is located 1807 * after 4096 bytes, so if the arch only supports larger pages, let's 1808 * pretend we don't support reading the HCA's core clock. This is also 1809 * forced by mmap function. 1810 */ 1811 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1812 if (PAGE_SIZE <= 4096) { 1813 resp.comp_mask |= 1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1815 resp.hca_core_clock_offset = 1816 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1817 } 1818 resp.response_length += sizeof(resp.hca_core_clock_offset); 1819 } 1820 1821 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1822 resp.response_length += sizeof(resp.log_uar_size); 1823 1824 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1825 resp.response_length += sizeof(resp.num_uars_per_page); 1826 1827 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1828 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1829 resp.response_length += sizeof(resp.num_dyn_bfregs); 1830 } 1831 1832 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1833 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1834 resp.dump_fill_mkey = dump_fill_mkey; 1835 resp.comp_mask |= 1836 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1837 } 1838 resp.response_length += sizeof(resp.dump_fill_mkey); 1839 } 1840 1841 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1842 if (err) 1843 goto out_mdev; 1844 1845 bfregi->ver = ver; 1846 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1847 context->cqe_version = resp.cqe_version; 1848 context->lib_caps = req.lib_caps; 1849 print_lib_caps(dev, context->lib_caps); 1850 1851 if (dev->lag_active) { 1852 u8 port = mlx5_core_native_port_num(dev->mdev); 1853 1854 atomic_set(&context->tx_port_affinity, 1855 atomic_add_return( 1856 1, &dev->roce[port].tx_port_affinity)); 1857 } 1858 1859 return &context->ibucontext; 1860 1861 out_mdev: 1862 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1863 out_devx: 1864 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1865 mlx5_ib_devx_destroy(dev, context->devx_uid); 1866 1867 out_uars: 1868 deallocate_uars(dev, context); 1869 1870 out_sys_pages: 1871 kfree(bfregi->sys_pages); 1872 1873 out_count: 1874 kfree(bfregi->count); 1875 1876 out_ctx: 1877 kfree(context); 1878 1879 return ERR_PTR(err); 1880 } 1881 1882 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1883 { 1884 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1885 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1886 struct mlx5_bfreg_info *bfregi; 1887 1888 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1889 /* All umem's must be destroyed before destroying the ucontext. */ 1890 mutex_lock(&ibcontext->per_mm_list_lock); 1891 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1892 mutex_unlock(&ibcontext->per_mm_list_lock); 1893 #endif 1894 1895 bfregi = &context->bfregi; 1896 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1897 1898 if (context->devx_uid) 1899 mlx5_ib_devx_destroy(dev, context->devx_uid); 1900 1901 deallocate_uars(dev, context); 1902 kfree(bfregi->sys_pages); 1903 kfree(bfregi->count); 1904 kfree(context); 1905 1906 return 0; 1907 } 1908 1909 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1910 int uar_idx) 1911 { 1912 int fw_uars_per_page; 1913 1914 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1915 1916 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1917 } 1918 1919 static int get_command(unsigned long offset) 1920 { 1921 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1922 } 1923 1924 static int get_arg(unsigned long offset) 1925 { 1926 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1927 } 1928 1929 static int get_index(unsigned long offset) 1930 { 1931 return get_arg(offset); 1932 } 1933 1934 /* Index resides in an extra byte to enable larger values than 255 */ 1935 static int get_extended_index(unsigned long offset) 1936 { 1937 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1938 } 1939 1940 1941 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1942 { 1943 } 1944 1945 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1946 { 1947 switch (cmd) { 1948 case MLX5_IB_MMAP_WC_PAGE: 1949 return "WC"; 1950 case MLX5_IB_MMAP_REGULAR_PAGE: 1951 return "best effort WC"; 1952 case MLX5_IB_MMAP_NC_PAGE: 1953 return "NC"; 1954 case MLX5_IB_MMAP_DEVICE_MEM: 1955 return "Device Memory"; 1956 default: 1957 return NULL; 1958 } 1959 } 1960 1961 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1962 struct vm_area_struct *vma, 1963 struct mlx5_ib_ucontext *context) 1964 { 1965 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1966 return -EINVAL; 1967 1968 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1969 return -EOPNOTSUPP; 1970 1971 if (vma->vm_flags & VM_WRITE) 1972 return -EPERM; 1973 1974 if (!dev->mdev->clock_info_page) 1975 return -EOPNOTSUPP; 1976 1977 return rdma_user_mmap_page(&context->ibucontext, vma, 1978 dev->mdev->clock_info_page, PAGE_SIZE); 1979 } 1980 1981 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1982 struct vm_area_struct *vma, 1983 struct mlx5_ib_ucontext *context) 1984 { 1985 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1986 int err; 1987 unsigned long idx; 1988 phys_addr_t pfn; 1989 pgprot_t prot; 1990 u32 bfreg_dyn_idx = 0; 1991 u32 uar_index; 1992 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1993 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1994 bfregi->num_static_sys_pages; 1995 1996 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1997 return -EINVAL; 1998 1999 if (dyn_uar) 2000 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2001 else 2002 idx = get_index(vma->vm_pgoff); 2003 2004 if (idx >= max_valid_idx) { 2005 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2006 idx, max_valid_idx); 2007 return -EINVAL; 2008 } 2009 2010 switch (cmd) { 2011 case MLX5_IB_MMAP_WC_PAGE: 2012 case MLX5_IB_MMAP_ALLOC_WC: 2013 /* Some architectures don't support WC memory */ 2014 #if defined(CONFIG_X86) 2015 if (!pat_enabled()) 2016 return -EPERM; 2017 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2018 return -EPERM; 2019 #endif 2020 /* fall through */ 2021 case MLX5_IB_MMAP_REGULAR_PAGE: 2022 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2023 prot = pgprot_writecombine(vma->vm_page_prot); 2024 break; 2025 case MLX5_IB_MMAP_NC_PAGE: 2026 prot = pgprot_noncached(vma->vm_page_prot); 2027 break; 2028 default: 2029 return -EINVAL; 2030 } 2031 2032 if (dyn_uar) { 2033 int uars_per_page; 2034 2035 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2036 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2037 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2038 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2039 bfreg_dyn_idx, bfregi->total_num_bfregs); 2040 return -EINVAL; 2041 } 2042 2043 mutex_lock(&bfregi->lock); 2044 /* Fail if uar already allocated, first bfreg index of each 2045 * page holds its count. 2046 */ 2047 if (bfregi->count[bfreg_dyn_idx]) { 2048 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2049 mutex_unlock(&bfregi->lock); 2050 return -EINVAL; 2051 } 2052 2053 bfregi->count[bfreg_dyn_idx]++; 2054 mutex_unlock(&bfregi->lock); 2055 2056 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2057 if (err) { 2058 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2059 goto free_bfreg; 2060 } 2061 } else { 2062 uar_index = bfregi->sys_pages[idx]; 2063 } 2064 2065 pfn = uar_index2pfn(dev, uar_index); 2066 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2067 2068 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2069 prot); 2070 if (err) { 2071 mlx5_ib_err(dev, 2072 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2073 err, mmap_cmd2str(cmd)); 2074 goto err; 2075 } 2076 2077 if (dyn_uar) 2078 bfregi->sys_pages[idx] = uar_index; 2079 return 0; 2080 2081 err: 2082 if (!dyn_uar) 2083 return err; 2084 2085 mlx5_cmd_free_uar(dev->mdev, idx); 2086 2087 free_bfreg: 2088 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2089 2090 return err; 2091 } 2092 2093 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2094 { 2095 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2096 struct mlx5_ib_dev *dev = to_mdev(context->device); 2097 u16 page_idx = get_extended_index(vma->vm_pgoff); 2098 size_t map_size = vma->vm_end - vma->vm_start; 2099 u32 npages = map_size >> PAGE_SHIFT; 2100 phys_addr_t pfn; 2101 2102 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2103 page_idx + npages) 2104 return -EINVAL; 2105 2106 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2107 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2108 PAGE_SHIFT) + 2109 page_idx; 2110 return rdma_user_mmap_io(context, vma, pfn, map_size, 2111 pgprot_writecombine(vma->vm_page_prot)); 2112 } 2113 2114 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2115 { 2116 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2117 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2118 unsigned long command; 2119 phys_addr_t pfn; 2120 2121 command = get_command(vma->vm_pgoff); 2122 switch (command) { 2123 case MLX5_IB_MMAP_WC_PAGE: 2124 case MLX5_IB_MMAP_NC_PAGE: 2125 case MLX5_IB_MMAP_REGULAR_PAGE: 2126 case MLX5_IB_MMAP_ALLOC_WC: 2127 return uar_mmap(dev, command, vma, context); 2128 2129 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2130 return -ENOSYS; 2131 2132 case MLX5_IB_MMAP_CORE_CLOCK: 2133 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2134 return -EINVAL; 2135 2136 if (vma->vm_flags & VM_WRITE) 2137 return -EPERM; 2138 2139 /* Don't expose to user-space information it shouldn't have */ 2140 if (PAGE_SIZE > 4096) 2141 return -EOPNOTSUPP; 2142 2143 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2144 pfn = (dev->mdev->iseg_base + 2145 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2146 PAGE_SHIFT; 2147 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2148 PAGE_SIZE, vma->vm_page_prot)) 2149 return -EAGAIN; 2150 break; 2151 case MLX5_IB_MMAP_CLOCK_INFO: 2152 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2153 2154 case MLX5_IB_MMAP_DEVICE_MEM: 2155 return dm_mmap(ibcontext, vma); 2156 2157 default: 2158 return -EINVAL; 2159 } 2160 2161 return 0; 2162 } 2163 2164 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2165 struct ib_ucontext *context, 2166 struct ib_dm_alloc_attr *attr, 2167 struct uverbs_attr_bundle *attrs) 2168 { 2169 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2170 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2171 phys_addr_t memic_addr; 2172 struct mlx5_ib_dm *dm; 2173 u64 start_offset; 2174 u32 page_idx; 2175 int err; 2176 2177 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2178 if (!dm) 2179 return ERR_PTR(-ENOMEM); 2180 2181 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2182 attr->length, act_size, attr->alignment); 2183 2184 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2185 act_size, attr->alignment); 2186 if (err) 2187 goto err_free; 2188 2189 start_offset = memic_addr & ~PAGE_MASK; 2190 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2191 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2192 PAGE_SHIFT; 2193 2194 err = uverbs_copy_to(attrs, 2195 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2196 &start_offset, sizeof(start_offset)); 2197 if (err) 2198 goto err_dealloc; 2199 2200 err = uverbs_copy_to(attrs, 2201 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2202 &page_idx, sizeof(page_idx)); 2203 if (err) 2204 goto err_dealloc; 2205 2206 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2207 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2208 2209 dm->dev_addr = memic_addr; 2210 2211 return &dm->ibdm; 2212 2213 err_dealloc: 2214 mlx5_cmd_dealloc_memic(memic, memic_addr, 2215 act_size); 2216 err_free: 2217 kfree(dm); 2218 return ERR_PTR(err); 2219 } 2220 2221 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2222 { 2223 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2224 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2225 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2226 u32 page_idx; 2227 int ret; 2228 2229 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2230 if (ret) 2231 return ret; 2232 2233 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2234 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2235 PAGE_SHIFT; 2236 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2237 page_idx, 2238 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2239 2240 kfree(dm); 2241 2242 return 0; 2243 } 2244 2245 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2246 struct ib_ucontext *context, 2247 struct ib_udata *udata) 2248 { 2249 struct mlx5_ib_alloc_pd_resp resp; 2250 struct mlx5_ib_pd *pd; 2251 int err; 2252 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2253 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2254 u16 uid = 0; 2255 2256 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2257 if (!pd) 2258 return ERR_PTR(-ENOMEM); 2259 2260 uid = context ? to_mucontext(context)->devx_uid : 0; 2261 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2262 MLX5_SET(alloc_pd_in, in, uid, uid); 2263 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in), 2264 out, sizeof(out)); 2265 if (err) { 2266 kfree(pd); 2267 return ERR_PTR(err); 2268 } 2269 2270 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2271 pd->uid = uid; 2272 if (context) { 2273 resp.pdn = pd->pdn; 2274 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2275 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2276 kfree(pd); 2277 return ERR_PTR(-EFAULT); 2278 } 2279 } 2280 2281 return &pd->ibpd; 2282 } 2283 2284 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2285 { 2286 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2287 struct mlx5_ib_pd *mpd = to_mpd(pd); 2288 2289 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2290 kfree(mpd); 2291 2292 return 0; 2293 } 2294 2295 enum { 2296 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2297 MATCH_CRITERIA_ENABLE_MISC_BIT, 2298 MATCH_CRITERIA_ENABLE_INNER_BIT, 2299 MATCH_CRITERIA_ENABLE_MISC2_BIT 2300 }; 2301 2302 #define HEADER_IS_ZERO(match_criteria, headers) \ 2303 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2304 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2305 2306 static u8 get_match_criteria_enable(u32 *match_criteria) 2307 { 2308 u8 match_criteria_enable; 2309 2310 match_criteria_enable = 2311 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2312 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2313 match_criteria_enable |= 2314 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2315 MATCH_CRITERIA_ENABLE_MISC_BIT; 2316 match_criteria_enable |= 2317 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2318 MATCH_CRITERIA_ENABLE_INNER_BIT; 2319 match_criteria_enable |= 2320 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2321 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2322 2323 return match_criteria_enable; 2324 } 2325 2326 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2327 { 2328 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2329 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2330 } 2331 2332 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2333 bool inner) 2334 { 2335 if (inner) { 2336 MLX5_SET(fte_match_set_misc, 2337 misc_c, inner_ipv6_flow_label, mask); 2338 MLX5_SET(fte_match_set_misc, 2339 misc_v, inner_ipv6_flow_label, val); 2340 } else { 2341 MLX5_SET(fte_match_set_misc, 2342 misc_c, outer_ipv6_flow_label, mask); 2343 MLX5_SET(fte_match_set_misc, 2344 misc_v, outer_ipv6_flow_label, val); 2345 } 2346 } 2347 2348 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2349 { 2350 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2351 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2352 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2353 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2354 } 2355 2356 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2357 { 2358 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2359 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2360 return -EOPNOTSUPP; 2361 2362 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2363 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2364 return -EOPNOTSUPP; 2365 2366 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2367 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2368 return -EOPNOTSUPP; 2369 2370 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2371 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2372 return -EOPNOTSUPP; 2373 2374 return 0; 2375 } 2376 2377 #define LAST_ETH_FIELD vlan_tag 2378 #define LAST_IB_FIELD sl 2379 #define LAST_IPV4_FIELD tos 2380 #define LAST_IPV6_FIELD traffic_class 2381 #define LAST_TCP_UDP_FIELD src_port 2382 #define LAST_TUNNEL_FIELD tunnel_id 2383 #define LAST_FLOW_TAG_FIELD tag_id 2384 #define LAST_DROP_FIELD size 2385 #define LAST_COUNTERS_FIELD counters 2386 2387 /* Field is the last supported field */ 2388 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2389 memchr_inv((void *)&filter.field +\ 2390 sizeof(filter.field), 0,\ 2391 sizeof(filter) -\ 2392 offsetof(typeof(filter), field) -\ 2393 sizeof(filter.field)) 2394 2395 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2396 bool is_egress, 2397 struct mlx5_flow_act *action) 2398 { 2399 2400 switch (maction->ib_action.type) { 2401 case IB_FLOW_ACTION_ESP: 2402 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2403 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2404 return -EINVAL; 2405 /* Currently only AES_GCM keymat is supported by the driver */ 2406 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2407 action->action |= is_egress ? 2408 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2409 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2410 return 0; 2411 case IB_FLOW_ACTION_UNSPECIFIED: 2412 if (maction->flow_action_raw.sub_type == 2413 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2414 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2415 return -EINVAL; 2416 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2417 action->modify_id = maction->flow_action_raw.action_id; 2418 return 0; 2419 } 2420 if (maction->flow_action_raw.sub_type == 2421 MLX5_IB_FLOW_ACTION_DECAP) { 2422 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2423 return -EINVAL; 2424 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2425 return 0; 2426 } 2427 if (maction->flow_action_raw.sub_type == 2428 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2429 if (action->action & 2430 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2431 return -EINVAL; 2432 action->action |= 2433 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2434 action->reformat_id = 2435 maction->flow_action_raw.action_id; 2436 return 0; 2437 } 2438 /* fall through */ 2439 default: 2440 return -EOPNOTSUPP; 2441 } 2442 } 2443 2444 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2445 u32 *match_v, const union ib_flow_spec *ib_spec, 2446 const struct ib_flow_attr *flow_attr, 2447 struct mlx5_flow_act *action, u32 prev_type) 2448 { 2449 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2450 misc_parameters); 2451 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2452 misc_parameters); 2453 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2454 misc_parameters_2); 2455 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2456 misc_parameters_2); 2457 void *headers_c; 2458 void *headers_v; 2459 int match_ipv; 2460 int ret; 2461 2462 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2463 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2464 inner_headers); 2465 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2466 inner_headers); 2467 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2468 ft_field_support.inner_ip_version); 2469 } else { 2470 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2471 outer_headers); 2472 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2473 outer_headers); 2474 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2475 ft_field_support.outer_ip_version); 2476 } 2477 2478 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2479 case IB_FLOW_SPEC_ETH: 2480 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2481 return -EOPNOTSUPP; 2482 2483 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2484 dmac_47_16), 2485 ib_spec->eth.mask.dst_mac); 2486 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2487 dmac_47_16), 2488 ib_spec->eth.val.dst_mac); 2489 2490 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2491 smac_47_16), 2492 ib_spec->eth.mask.src_mac); 2493 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2494 smac_47_16), 2495 ib_spec->eth.val.src_mac); 2496 2497 if (ib_spec->eth.mask.vlan_tag) { 2498 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2499 cvlan_tag, 1); 2500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2501 cvlan_tag, 1); 2502 2503 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2504 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2506 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2507 2508 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2509 first_cfi, 2510 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2512 first_cfi, 2513 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2514 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2516 first_prio, 2517 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2519 first_prio, 2520 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2521 } 2522 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2523 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2524 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2525 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2526 break; 2527 case IB_FLOW_SPEC_IPV4: 2528 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2529 return -EOPNOTSUPP; 2530 2531 if (match_ipv) { 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2533 ip_version, 0xf); 2534 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2535 ip_version, MLX5_FS_IPV4_VERSION); 2536 } else { 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2538 ethertype, 0xffff); 2539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2540 ethertype, ETH_P_IP); 2541 } 2542 2543 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2544 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2545 &ib_spec->ipv4.mask.src_ip, 2546 sizeof(ib_spec->ipv4.mask.src_ip)); 2547 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2548 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2549 &ib_spec->ipv4.val.src_ip, 2550 sizeof(ib_spec->ipv4.val.src_ip)); 2551 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2552 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2553 &ib_spec->ipv4.mask.dst_ip, 2554 sizeof(ib_spec->ipv4.mask.dst_ip)); 2555 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2556 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2557 &ib_spec->ipv4.val.dst_ip, 2558 sizeof(ib_spec->ipv4.val.dst_ip)); 2559 2560 set_tos(headers_c, headers_v, 2561 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2562 2563 set_proto(headers_c, headers_v, 2564 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2565 break; 2566 case IB_FLOW_SPEC_IPV6: 2567 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2568 return -EOPNOTSUPP; 2569 2570 if (match_ipv) { 2571 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2572 ip_version, 0xf); 2573 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2574 ip_version, MLX5_FS_IPV6_VERSION); 2575 } else { 2576 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2577 ethertype, 0xffff); 2578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2579 ethertype, ETH_P_IPV6); 2580 } 2581 2582 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2583 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2584 &ib_spec->ipv6.mask.src_ip, 2585 sizeof(ib_spec->ipv6.mask.src_ip)); 2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2587 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2588 &ib_spec->ipv6.val.src_ip, 2589 sizeof(ib_spec->ipv6.val.src_ip)); 2590 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2591 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2592 &ib_spec->ipv6.mask.dst_ip, 2593 sizeof(ib_spec->ipv6.mask.dst_ip)); 2594 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2595 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2596 &ib_spec->ipv6.val.dst_ip, 2597 sizeof(ib_spec->ipv6.val.dst_ip)); 2598 2599 set_tos(headers_c, headers_v, 2600 ib_spec->ipv6.mask.traffic_class, 2601 ib_spec->ipv6.val.traffic_class); 2602 2603 set_proto(headers_c, headers_v, 2604 ib_spec->ipv6.mask.next_hdr, 2605 ib_spec->ipv6.val.next_hdr); 2606 2607 set_flow_label(misc_params_c, misc_params_v, 2608 ntohl(ib_spec->ipv6.mask.flow_label), 2609 ntohl(ib_spec->ipv6.val.flow_label), 2610 ib_spec->type & IB_FLOW_SPEC_INNER); 2611 break; 2612 case IB_FLOW_SPEC_ESP: 2613 if (ib_spec->esp.mask.seq) 2614 return -EOPNOTSUPP; 2615 2616 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2617 ntohl(ib_spec->esp.mask.spi)); 2618 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2619 ntohl(ib_spec->esp.val.spi)); 2620 break; 2621 case IB_FLOW_SPEC_TCP: 2622 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2623 LAST_TCP_UDP_FIELD)) 2624 return -EOPNOTSUPP; 2625 2626 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2627 0xff); 2628 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2629 IPPROTO_TCP); 2630 2631 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2632 ntohs(ib_spec->tcp_udp.mask.src_port)); 2633 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2634 ntohs(ib_spec->tcp_udp.val.src_port)); 2635 2636 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2637 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2639 ntohs(ib_spec->tcp_udp.val.dst_port)); 2640 break; 2641 case IB_FLOW_SPEC_UDP: 2642 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2643 LAST_TCP_UDP_FIELD)) 2644 return -EOPNOTSUPP; 2645 2646 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2647 0xff); 2648 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2649 IPPROTO_UDP); 2650 2651 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2652 ntohs(ib_spec->tcp_udp.mask.src_port)); 2653 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2654 ntohs(ib_spec->tcp_udp.val.src_port)); 2655 2656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2657 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2659 ntohs(ib_spec->tcp_udp.val.dst_port)); 2660 break; 2661 case IB_FLOW_SPEC_GRE: 2662 if (ib_spec->gre.mask.c_ks_res0_ver) 2663 return -EOPNOTSUPP; 2664 2665 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2666 0xff); 2667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2668 IPPROTO_GRE); 2669 2670 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2671 ntohs(ib_spec->gre.mask.protocol)); 2672 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2673 ntohs(ib_spec->gre.val.protocol)); 2674 2675 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2676 gre_key.nvgre.hi), 2677 &ib_spec->gre.mask.key, 2678 sizeof(ib_spec->gre.mask.key)); 2679 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2680 gre_key.nvgre.hi), 2681 &ib_spec->gre.val.key, 2682 sizeof(ib_spec->gre.val.key)); 2683 break; 2684 case IB_FLOW_SPEC_MPLS: 2685 switch (prev_type) { 2686 case IB_FLOW_SPEC_UDP: 2687 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2688 ft_field_support.outer_first_mpls_over_udp), 2689 &ib_spec->mpls.mask.tag)) 2690 return -EOPNOTSUPP; 2691 2692 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2693 outer_first_mpls_over_udp), 2694 &ib_spec->mpls.val.tag, 2695 sizeof(ib_spec->mpls.val.tag)); 2696 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2697 outer_first_mpls_over_udp), 2698 &ib_spec->mpls.mask.tag, 2699 sizeof(ib_spec->mpls.mask.tag)); 2700 break; 2701 case IB_FLOW_SPEC_GRE: 2702 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2703 ft_field_support.outer_first_mpls_over_gre), 2704 &ib_spec->mpls.mask.tag)) 2705 return -EOPNOTSUPP; 2706 2707 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2708 outer_first_mpls_over_gre), 2709 &ib_spec->mpls.val.tag, 2710 sizeof(ib_spec->mpls.val.tag)); 2711 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2712 outer_first_mpls_over_gre), 2713 &ib_spec->mpls.mask.tag, 2714 sizeof(ib_spec->mpls.mask.tag)); 2715 break; 2716 default: 2717 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2718 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2719 ft_field_support.inner_first_mpls), 2720 &ib_spec->mpls.mask.tag)) 2721 return -EOPNOTSUPP; 2722 2723 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2724 inner_first_mpls), 2725 &ib_spec->mpls.val.tag, 2726 sizeof(ib_spec->mpls.val.tag)); 2727 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2728 inner_first_mpls), 2729 &ib_spec->mpls.mask.tag, 2730 sizeof(ib_spec->mpls.mask.tag)); 2731 } else { 2732 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2733 ft_field_support.outer_first_mpls), 2734 &ib_spec->mpls.mask.tag)) 2735 return -EOPNOTSUPP; 2736 2737 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2738 outer_first_mpls), 2739 &ib_spec->mpls.val.tag, 2740 sizeof(ib_spec->mpls.val.tag)); 2741 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2742 outer_first_mpls), 2743 &ib_spec->mpls.mask.tag, 2744 sizeof(ib_spec->mpls.mask.tag)); 2745 } 2746 } 2747 break; 2748 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2749 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2750 LAST_TUNNEL_FIELD)) 2751 return -EOPNOTSUPP; 2752 2753 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2754 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2755 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2756 ntohl(ib_spec->tunnel.val.tunnel_id)); 2757 break; 2758 case IB_FLOW_SPEC_ACTION_TAG: 2759 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2760 LAST_FLOW_TAG_FIELD)) 2761 return -EOPNOTSUPP; 2762 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2763 return -EINVAL; 2764 2765 action->flow_tag = ib_spec->flow_tag.tag_id; 2766 action->flags |= FLOW_ACT_HAS_TAG; 2767 break; 2768 case IB_FLOW_SPEC_ACTION_DROP: 2769 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2770 LAST_DROP_FIELD)) 2771 return -EOPNOTSUPP; 2772 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2773 break; 2774 case IB_FLOW_SPEC_ACTION_HANDLE: 2775 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 2776 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 2777 if (ret) 2778 return ret; 2779 break; 2780 case IB_FLOW_SPEC_ACTION_COUNT: 2781 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2782 LAST_COUNTERS_FIELD)) 2783 return -EOPNOTSUPP; 2784 2785 /* for now support only one counters spec per flow */ 2786 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2787 return -EINVAL; 2788 2789 action->counters = ib_spec->flow_count.counters; 2790 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2791 break; 2792 default: 2793 return -EINVAL; 2794 } 2795 2796 return 0; 2797 } 2798 2799 /* If a flow could catch both multicast and unicast packets, 2800 * it won't fall into the multicast flow steering table and this rule 2801 * could steal other multicast packets. 2802 */ 2803 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2804 { 2805 union ib_flow_spec *flow_spec; 2806 2807 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2808 ib_attr->num_of_specs < 1) 2809 return false; 2810 2811 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2812 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2813 struct ib_flow_spec_ipv4 *ipv4_spec; 2814 2815 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2816 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2817 return true; 2818 2819 return false; 2820 } 2821 2822 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2823 struct ib_flow_spec_eth *eth_spec; 2824 2825 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2826 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2827 is_multicast_ether_addr(eth_spec->val.dst_mac); 2828 } 2829 2830 return false; 2831 } 2832 2833 enum valid_spec { 2834 VALID_SPEC_INVALID, 2835 VALID_SPEC_VALID, 2836 VALID_SPEC_NA, 2837 }; 2838 2839 static enum valid_spec 2840 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2841 const struct mlx5_flow_spec *spec, 2842 const struct mlx5_flow_act *flow_act, 2843 bool egress) 2844 { 2845 const u32 *match_c = spec->match_criteria; 2846 bool is_crypto = 2847 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2848 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2849 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2850 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2851 2852 /* 2853 * Currently only crypto is supported in egress, when regular egress 2854 * rules would be supported, always return VALID_SPEC_NA. 2855 */ 2856 if (!is_crypto) 2857 return VALID_SPEC_NA; 2858 2859 return is_crypto && is_ipsec && 2860 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ? 2861 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2862 } 2863 2864 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2865 const struct mlx5_flow_spec *spec, 2866 const struct mlx5_flow_act *flow_act, 2867 bool egress) 2868 { 2869 /* We curretly only support ipsec egress flow */ 2870 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2871 } 2872 2873 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2874 const struct ib_flow_attr *flow_attr, 2875 bool check_inner) 2876 { 2877 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2878 int match_ipv = check_inner ? 2879 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2880 ft_field_support.inner_ip_version) : 2881 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2882 ft_field_support.outer_ip_version); 2883 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2884 bool ipv4_spec_valid, ipv6_spec_valid; 2885 unsigned int ip_spec_type = 0; 2886 bool has_ethertype = false; 2887 unsigned int spec_index; 2888 bool mask_valid = true; 2889 u16 eth_type = 0; 2890 bool type_valid; 2891 2892 /* Validate that ethertype is correct */ 2893 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2894 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2895 ib_spec->eth.mask.ether_type) { 2896 mask_valid = (ib_spec->eth.mask.ether_type == 2897 htons(0xffff)); 2898 has_ethertype = true; 2899 eth_type = ntohs(ib_spec->eth.val.ether_type); 2900 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2901 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2902 ip_spec_type = ib_spec->type; 2903 } 2904 ib_spec = (void *)ib_spec + ib_spec->size; 2905 } 2906 2907 type_valid = (!has_ethertype) || (!ip_spec_type); 2908 if (!type_valid && mask_valid) { 2909 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2910 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2911 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2912 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2913 2914 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2915 (((eth_type == ETH_P_MPLS_UC) || 2916 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2917 } 2918 2919 return type_valid; 2920 } 2921 2922 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2923 const struct ib_flow_attr *flow_attr) 2924 { 2925 return is_valid_ethertype(mdev, flow_attr, false) && 2926 is_valid_ethertype(mdev, flow_attr, true); 2927 } 2928 2929 static void put_flow_table(struct mlx5_ib_dev *dev, 2930 struct mlx5_ib_flow_prio *prio, bool ft_added) 2931 { 2932 prio->refcount -= !!ft_added; 2933 if (!prio->refcount) { 2934 mlx5_destroy_flow_table(prio->flow_table); 2935 prio->flow_table = NULL; 2936 } 2937 } 2938 2939 static void counters_clear_description(struct ib_counters *counters) 2940 { 2941 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 2942 2943 mutex_lock(&mcounters->mcntrs_mutex); 2944 kfree(mcounters->counters_data); 2945 mcounters->counters_data = NULL; 2946 mcounters->cntrs_max_index = 0; 2947 mutex_unlock(&mcounters->mcntrs_mutex); 2948 } 2949 2950 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2951 { 2952 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2953 struct mlx5_ib_flow_handler, 2954 ibflow); 2955 struct mlx5_ib_flow_handler *iter, *tmp; 2956 struct mlx5_ib_dev *dev = handler->dev; 2957 2958 mutex_lock(&dev->flow_db->lock); 2959 2960 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2961 mlx5_del_flow_rules(iter->rule); 2962 put_flow_table(dev, iter->prio, true); 2963 list_del(&iter->list); 2964 kfree(iter); 2965 } 2966 2967 mlx5_del_flow_rules(handler->rule); 2968 put_flow_table(dev, handler->prio, true); 2969 if (handler->ibcounters && 2970 atomic_read(&handler->ibcounters->usecnt) == 1) 2971 counters_clear_description(handler->ibcounters); 2972 2973 mutex_unlock(&dev->flow_db->lock); 2974 if (handler->flow_matcher) 2975 atomic_dec(&handler->flow_matcher->usecnt); 2976 kfree(handler); 2977 2978 return 0; 2979 } 2980 2981 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2982 { 2983 priority *= 2; 2984 if (!dont_trap) 2985 priority++; 2986 return priority; 2987 } 2988 2989 enum flow_table_type { 2990 MLX5_IB_FT_RX, 2991 MLX5_IB_FT_TX 2992 }; 2993 2994 #define MLX5_FS_MAX_TYPES 6 2995 #define MLX5_FS_MAX_ENTRIES BIT(16) 2996 2997 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 2998 struct mlx5_ib_flow_prio *prio, 2999 int priority, 3000 int num_entries, int num_groups, 3001 u32 flags) 3002 { 3003 struct mlx5_flow_table *ft; 3004 3005 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3006 num_entries, 3007 num_groups, 3008 0, flags); 3009 if (IS_ERR(ft)) 3010 return ERR_CAST(ft); 3011 3012 prio->flow_table = ft; 3013 prio->refcount = 0; 3014 return prio; 3015 } 3016 3017 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3018 struct ib_flow_attr *flow_attr, 3019 enum flow_table_type ft_type) 3020 { 3021 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3022 struct mlx5_flow_namespace *ns = NULL; 3023 struct mlx5_ib_flow_prio *prio; 3024 struct mlx5_flow_table *ft; 3025 int max_table_size; 3026 int num_entries; 3027 int num_groups; 3028 u32 flags = 0; 3029 int priority; 3030 3031 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3032 log_max_ft_size)); 3033 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3034 enum mlx5_flow_namespace_type fn_type; 3035 3036 if (flow_is_multicast_only(flow_attr) && 3037 !dont_trap) 3038 priority = MLX5_IB_FLOW_MCAST_PRIO; 3039 else 3040 priority = ib_prio_to_core_prio(flow_attr->priority, 3041 dont_trap); 3042 if (ft_type == MLX5_IB_FT_RX) { 3043 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3044 prio = &dev->flow_db->prios[priority]; 3045 if (!dev->rep && 3046 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3047 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3048 if (!dev->rep && 3049 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3050 reformat_l3_tunnel_to_l2)) 3051 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3052 } else { 3053 max_table_size = 3054 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3055 log_max_ft_size)); 3056 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3057 prio = &dev->flow_db->egress_prios[priority]; 3058 if (!dev->rep && 3059 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3060 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3061 } 3062 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3063 num_entries = MLX5_FS_MAX_ENTRIES; 3064 num_groups = MLX5_FS_MAX_TYPES; 3065 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3066 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3067 ns = mlx5_get_flow_namespace(dev->mdev, 3068 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3069 build_leftovers_ft_param(&priority, 3070 &num_entries, 3071 &num_groups); 3072 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3073 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3074 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3075 allow_sniffer_and_nic_rx_shared_tir)) 3076 return ERR_PTR(-ENOTSUPP); 3077 3078 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3079 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3080 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3081 3082 prio = &dev->flow_db->sniffer[ft_type]; 3083 priority = 0; 3084 num_entries = 1; 3085 num_groups = 1; 3086 } 3087 3088 if (!ns) 3089 return ERR_PTR(-ENOTSUPP); 3090 3091 if (num_entries > max_table_size) 3092 return ERR_PTR(-ENOMEM); 3093 3094 ft = prio->flow_table; 3095 if (!ft) 3096 return _get_prio(ns, prio, priority, num_entries, num_groups, 3097 flags); 3098 3099 return prio; 3100 } 3101 3102 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3103 struct mlx5_flow_spec *spec, 3104 u32 underlay_qpn) 3105 { 3106 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3107 spec->match_criteria, 3108 misc_parameters); 3109 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3110 misc_parameters); 3111 3112 if (underlay_qpn && 3113 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3114 ft_field_support.bth_dst_qp)) { 3115 MLX5_SET(fte_match_set_misc, 3116 misc_params_v, bth_dst_qp, underlay_qpn); 3117 MLX5_SET(fte_match_set_misc, 3118 misc_params_c, bth_dst_qp, 0xffffff); 3119 } 3120 } 3121 3122 static int read_flow_counters(struct ib_device *ibdev, 3123 struct mlx5_read_counters_attr *read_attr) 3124 { 3125 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3126 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3127 3128 return mlx5_fc_query(dev->mdev, fc, 3129 &read_attr->out[IB_COUNTER_PACKETS], 3130 &read_attr->out[IB_COUNTER_BYTES]); 3131 } 3132 3133 /* flow counters currently expose two counters packets and bytes */ 3134 #define FLOW_COUNTERS_NUM 2 3135 static int counters_set_description(struct ib_counters *counters, 3136 enum mlx5_ib_counters_type counters_type, 3137 struct mlx5_ib_flow_counters_desc *desc_data, 3138 u32 ncounters) 3139 { 3140 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3141 u32 cntrs_max_index = 0; 3142 int i; 3143 3144 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3145 return -EINVAL; 3146 3147 /* init the fields for the object */ 3148 mcounters->type = counters_type; 3149 mcounters->read_counters = read_flow_counters; 3150 mcounters->counters_num = FLOW_COUNTERS_NUM; 3151 mcounters->ncounters = ncounters; 3152 /* each counter entry have both description and index pair */ 3153 for (i = 0; i < ncounters; i++) { 3154 if (desc_data[i].description > IB_COUNTER_BYTES) 3155 return -EINVAL; 3156 3157 if (cntrs_max_index <= desc_data[i].index) 3158 cntrs_max_index = desc_data[i].index + 1; 3159 } 3160 3161 mutex_lock(&mcounters->mcntrs_mutex); 3162 mcounters->counters_data = desc_data; 3163 mcounters->cntrs_max_index = cntrs_max_index; 3164 mutex_unlock(&mcounters->mcntrs_mutex); 3165 3166 return 0; 3167 } 3168 3169 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3170 static int flow_counters_set_data(struct ib_counters *ibcounters, 3171 struct mlx5_ib_create_flow *ucmd) 3172 { 3173 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3174 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3175 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3176 bool hw_hndl = false; 3177 int ret = 0; 3178 3179 if (ucmd && ucmd->ncounters_data != 0) { 3180 cntrs_data = ucmd->data; 3181 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3182 return -EINVAL; 3183 3184 desc_data = kcalloc(cntrs_data->ncounters, 3185 sizeof(*desc_data), 3186 GFP_KERNEL); 3187 if (!desc_data) 3188 return -ENOMEM; 3189 3190 if (copy_from_user(desc_data, 3191 u64_to_user_ptr(cntrs_data->counters_data), 3192 sizeof(*desc_data) * cntrs_data->ncounters)) { 3193 ret = -EFAULT; 3194 goto free; 3195 } 3196 } 3197 3198 if (!mcounters->hw_cntrs_hndl) { 3199 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3200 to_mdev(ibcounters->device)->mdev, false); 3201 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3202 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3203 goto free; 3204 } 3205 hw_hndl = true; 3206 } 3207 3208 if (desc_data) { 3209 /* counters already bound to at least one flow */ 3210 if (mcounters->cntrs_max_index) { 3211 ret = -EINVAL; 3212 goto free_hndl; 3213 } 3214 3215 ret = counters_set_description(ibcounters, 3216 MLX5_IB_COUNTERS_FLOW, 3217 desc_data, 3218 cntrs_data->ncounters); 3219 if (ret) 3220 goto free_hndl; 3221 3222 } else if (!mcounters->cntrs_max_index) { 3223 /* counters not bound yet, must have udata passed */ 3224 ret = -EINVAL; 3225 goto free_hndl; 3226 } 3227 3228 return 0; 3229 3230 free_hndl: 3231 if (hw_hndl) { 3232 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3233 mcounters->hw_cntrs_hndl); 3234 mcounters->hw_cntrs_hndl = NULL; 3235 } 3236 free: 3237 kfree(desc_data); 3238 return ret; 3239 } 3240 3241 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3242 struct mlx5_ib_flow_prio *ft_prio, 3243 const struct ib_flow_attr *flow_attr, 3244 struct mlx5_flow_destination *dst, 3245 u32 underlay_qpn, 3246 struct mlx5_ib_create_flow *ucmd) 3247 { 3248 struct mlx5_flow_table *ft = ft_prio->flow_table; 3249 struct mlx5_ib_flow_handler *handler; 3250 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3251 struct mlx5_flow_spec *spec; 3252 struct mlx5_flow_destination dest_arr[2] = {}; 3253 struct mlx5_flow_destination *rule_dst = dest_arr; 3254 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3255 unsigned int spec_index; 3256 u32 prev_type = 0; 3257 int err = 0; 3258 int dest_num = 0; 3259 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3260 3261 if (!is_valid_attr(dev->mdev, flow_attr)) 3262 return ERR_PTR(-EINVAL); 3263 3264 if (dev->rep && is_egress) 3265 return ERR_PTR(-EINVAL); 3266 3267 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3268 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3269 if (!handler || !spec) { 3270 err = -ENOMEM; 3271 goto free; 3272 } 3273 3274 INIT_LIST_HEAD(&handler->list); 3275 if (dst) { 3276 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3277 dest_num++; 3278 } 3279 3280 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3281 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3282 spec->match_value, 3283 ib_flow, flow_attr, &flow_act, 3284 prev_type); 3285 if (err < 0) 3286 goto free; 3287 3288 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3289 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3290 } 3291 3292 if (!flow_is_multicast_only(flow_attr)) 3293 set_underlay_qp(dev, spec, underlay_qpn); 3294 3295 if (dev->rep) { 3296 void *misc; 3297 3298 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3299 misc_parameters); 3300 MLX5_SET(fte_match_set_misc, misc, source_port, 3301 dev->rep->vport); 3302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3303 misc_parameters); 3304 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3305 } 3306 3307 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3308 3309 if (is_egress && 3310 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3311 err = -EINVAL; 3312 goto free; 3313 } 3314 3315 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3316 struct mlx5_ib_mcounters *mcounters; 3317 3318 err = flow_counters_set_data(flow_act.counters, ucmd); 3319 if (err) 3320 goto free; 3321 3322 mcounters = to_mcounters(flow_act.counters); 3323 handler->ibcounters = flow_act.counters; 3324 dest_arr[dest_num].type = 3325 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3326 dest_arr[dest_num].counter_id = 3327 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3328 dest_num++; 3329 } 3330 3331 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3332 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3333 rule_dst = NULL; 3334 dest_num = 0; 3335 } 3336 } else { 3337 if (is_egress) 3338 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3339 else 3340 flow_act.action |= 3341 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3342 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3343 } 3344 3345 if ((flow_act.flags & FLOW_ACT_HAS_TAG) && 3346 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3347 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3348 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3349 flow_act.flow_tag, flow_attr->type); 3350 err = -EINVAL; 3351 goto free; 3352 } 3353 handler->rule = mlx5_add_flow_rules(ft, spec, 3354 &flow_act, 3355 rule_dst, dest_num); 3356 3357 if (IS_ERR(handler->rule)) { 3358 err = PTR_ERR(handler->rule); 3359 goto free; 3360 } 3361 3362 ft_prio->refcount++; 3363 handler->prio = ft_prio; 3364 handler->dev = dev; 3365 3366 ft_prio->flow_table = ft; 3367 free: 3368 if (err && handler) { 3369 if (handler->ibcounters && 3370 atomic_read(&handler->ibcounters->usecnt) == 1) 3371 counters_clear_description(handler->ibcounters); 3372 kfree(handler); 3373 } 3374 kvfree(spec); 3375 return err ? ERR_PTR(err) : handler; 3376 } 3377 3378 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3379 struct mlx5_ib_flow_prio *ft_prio, 3380 const struct ib_flow_attr *flow_attr, 3381 struct mlx5_flow_destination *dst) 3382 { 3383 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3384 } 3385 3386 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3387 struct mlx5_ib_flow_prio *ft_prio, 3388 struct ib_flow_attr *flow_attr, 3389 struct mlx5_flow_destination *dst) 3390 { 3391 struct mlx5_ib_flow_handler *handler_dst = NULL; 3392 struct mlx5_ib_flow_handler *handler = NULL; 3393 3394 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3395 if (!IS_ERR(handler)) { 3396 handler_dst = create_flow_rule(dev, ft_prio, 3397 flow_attr, dst); 3398 if (IS_ERR(handler_dst)) { 3399 mlx5_del_flow_rules(handler->rule); 3400 ft_prio->refcount--; 3401 kfree(handler); 3402 handler = handler_dst; 3403 } else { 3404 list_add(&handler_dst->list, &handler->list); 3405 } 3406 } 3407 3408 return handler; 3409 } 3410 enum { 3411 LEFTOVERS_MC, 3412 LEFTOVERS_UC, 3413 }; 3414 3415 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3416 struct mlx5_ib_flow_prio *ft_prio, 3417 struct ib_flow_attr *flow_attr, 3418 struct mlx5_flow_destination *dst) 3419 { 3420 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3421 struct mlx5_ib_flow_handler *handler = NULL; 3422 3423 static struct { 3424 struct ib_flow_attr flow_attr; 3425 struct ib_flow_spec_eth eth_flow; 3426 } leftovers_specs[] = { 3427 [LEFTOVERS_MC] = { 3428 .flow_attr = { 3429 .num_of_specs = 1, 3430 .size = sizeof(leftovers_specs[0]) 3431 }, 3432 .eth_flow = { 3433 .type = IB_FLOW_SPEC_ETH, 3434 .size = sizeof(struct ib_flow_spec_eth), 3435 .mask = {.dst_mac = {0x1} }, 3436 .val = {.dst_mac = {0x1} } 3437 } 3438 }, 3439 [LEFTOVERS_UC] = { 3440 .flow_attr = { 3441 .num_of_specs = 1, 3442 .size = sizeof(leftovers_specs[0]) 3443 }, 3444 .eth_flow = { 3445 .type = IB_FLOW_SPEC_ETH, 3446 .size = sizeof(struct ib_flow_spec_eth), 3447 .mask = {.dst_mac = {0x1} }, 3448 .val = {.dst_mac = {} } 3449 } 3450 } 3451 }; 3452 3453 handler = create_flow_rule(dev, ft_prio, 3454 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3455 dst); 3456 if (!IS_ERR(handler) && 3457 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3458 handler_ucast = create_flow_rule(dev, ft_prio, 3459 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3460 dst); 3461 if (IS_ERR(handler_ucast)) { 3462 mlx5_del_flow_rules(handler->rule); 3463 ft_prio->refcount--; 3464 kfree(handler); 3465 handler = handler_ucast; 3466 } else { 3467 list_add(&handler_ucast->list, &handler->list); 3468 } 3469 } 3470 3471 return handler; 3472 } 3473 3474 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3475 struct mlx5_ib_flow_prio *ft_rx, 3476 struct mlx5_ib_flow_prio *ft_tx, 3477 struct mlx5_flow_destination *dst) 3478 { 3479 struct mlx5_ib_flow_handler *handler_rx; 3480 struct mlx5_ib_flow_handler *handler_tx; 3481 int err; 3482 static const struct ib_flow_attr flow_attr = { 3483 .num_of_specs = 0, 3484 .size = sizeof(flow_attr) 3485 }; 3486 3487 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3488 if (IS_ERR(handler_rx)) { 3489 err = PTR_ERR(handler_rx); 3490 goto err; 3491 } 3492 3493 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3494 if (IS_ERR(handler_tx)) { 3495 err = PTR_ERR(handler_tx); 3496 goto err_tx; 3497 } 3498 3499 list_add(&handler_tx->list, &handler_rx->list); 3500 3501 return handler_rx; 3502 3503 err_tx: 3504 mlx5_del_flow_rules(handler_rx->rule); 3505 ft_rx->refcount--; 3506 kfree(handler_rx); 3507 err: 3508 return ERR_PTR(err); 3509 } 3510 3511 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3512 struct ib_flow_attr *flow_attr, 3513 int domain, 3514 struct ib_udata *udata) 3515 { 3516 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3517 struct mlx5_ib_qp *mqp = to_mqp(qp); 3518 struct mlx5_ib_flow_handler *handler = NULL; 3519 struct mlx5_flow_destination *dst = NULL; 3520 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3521 struct mlx5_ib_flow_prio *ft_prio; 3522 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3523 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3524 size_t min_ucmd_sz, required_ucmd_sz; 3525 int err; 3526 int underlay_qpn; 3527 3528 if (udata && udata->inlen) { 3529 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3530 sizeof(ucmd_hdr.reserved); 3531 if (udata->inlen < min_ucmd_sz) 3532 return ERR_PTR(-EOPNOTSUPP); 3533 3534 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3535 if (err) 3536 return ERR_PTR(err); 3537 3538 /* currently supports only one counters data */ 3539 if (ucmd_hdr.ncounters_data > 1) 3540 return ERR_PTR(-EINVAL); 3541 3542 required_ucmd_sz = min_ucmd_sz + 3543 sizeof(struct mlx5_ib_flow_counters_data) * 3544 ucmd_hdr.ncounters_data; 3545 if (udata->inlen > required_ucmd_sz && 3546 !ib_is_udata_cleared(udata, required_ucmd_sz, 3547 udata->inlen - required_ucmd_sz)) 3548 return ERR_PTR(-EOPNOTSUPP); 3549 3550 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3551 if (!ucmd) 3552 return ERR_PTR(-ENOMEM); 3553 3554 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3555 if (err) 3556 goto free_ucmd; 3557 } 3558 3559 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3560 err = -ENOMEM; 3561 goto free_ucmd; 3562 } 3563 3564 if (domain != IB_FLOW_DOMAIN_USER || 3565 flow_attr->port > dev->num_ports || 3566 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3567 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3568 err = -EINVAL; 3569 goto free_ucmd; 3570 } 3571 3572 if (is_egress && 3573 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3574 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3575 err = -EINVAL; 3576 goto free_ucmd; 3577 } 3578 3579 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3580 if (!dst) { 3581 err = -ENOMEM; 3582 goto free_ucmd; 3583 } 3584 3585 mutex_lock(&dev->flow_db->lock); 3586 3587 ft_prio = get_flow_table(dev, flow_attr, 3588 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3589 if (IS_ERR(ft_prio)) { 3590 err = PTR_ERR(ft_prio); 3591 goto unlock; 3592 } 3593 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3594 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3595 if (IS_ERR(ft_prio_tx)) { 3596 err = PTR_ERR(ft_prio_tx); 3597 ft_prio_tx = NULL; 3598 goto destroy_ft; 3599 } 3600 } 3601 3602 if (is_egress) { 3603 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3604 } else { 3605 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3606 if (mqp->flags & MLX5_IB_QP_RSS) 3607 dst->tir_num = mqp->rss_qp.tirn; 3608 else 3609 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3610 } 3611 3612 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3613 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3614 handler = create_dont_trap_rule(dev, ft_prio, 3615 flow_attr, dst); 3616 } else { 3617 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3618 mqp->underlay_qpn : 0; 3619 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3620 dst, underlay_qpn, ucmd); 3621 } 3622 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3623 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3624 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3625 dst); 3626 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3627 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3628 } else { 3629 err = -EINVAL; 3630 goto destroy_ft; 3631 } 3632 3633 if (IS_ERR(handler)) { 3634 err = PTR_ERR(handler); 3635 handler = NULL; 3636 goto destroy_ft; 3637 } 3638 3639 mutex_unlock(&dev->flow_db->lock); 3640 kfree(dst); 3641 kfree(ucmd); 3642 3643 return &handler->ibflow; 3644 3645 destroy_ft: 3646 put_flow_table(dev, ft_prio, false); 3647 if (ft_prio_tx) 3648 put_flow_table(dev, ft_prio_tx, false); 3649 unlock: 3650 mutex_unlock(&dev->flow_db->lock); 3651 kfree(dst); 3652 free_ucmd: 3653 kfree(ucmd); 3654 return ERR_PTR(err); 3655 } 3656 3657 static struct mlx5_ib_flow_prio * 3658 _get_flow_table(struct mlx5_ib_dev *dev, 3659 struct mlx5_ib_flow_matcher *fs_matcher, 3660 bool mcast) 3661 { 3662 struct mlx5_flow_namespace *ns = NULL; 3663 struct mlx5_ib_flow_prio *prio; 3664 int max_table_size; 3665 u32 flags = 0; 3666 int priority; 3667 3668 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3669 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3670 log_max_ft_size)); 3671 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3672 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3673 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3674 reformat_l3_tunnel_to_l2)) 3675 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3676 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */ 3677 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3678 log_max_ft_size)); 3679 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3680 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3681 } 3682 3683 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3684 return ERR_PTR(-ENOMEM); 3685 3686 if (mcast) 3687 priority = MLX5_IB_FLOW_MCAST_PRIO; 3688 else 3689 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3690 3691 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3692 if (!ns) 3693 return ERR_PTR(-ENOTSUPP); 3694 3695 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3696 prio = &dev->flow_db->prios[priority]; 3697 else 3698 prio = &dev->flow_db->egress_prios[priority]; 3699 3700 if (prio->flow_table) 3701 return prio; 3702 3703 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3704 MLX5_FS_MAX_TYPES, flags); 3705 } 3706 3707 static struct mlx5_ib_flow_handler * 3708 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3709 struct mlx5_ib_flow_prio *ft_prio, 3710 struct mlx5_flow_destination *dst, 3711 struct mlx5_ib_flow_matcher *fs_matcher, 3712 struct mlx5_flow_act *flow_act, 3713 void *cmd_in, int inlen) 3714 { 3715 struct mlx5_ib_flow_handler *handler; 3716 struct mlx5_flow_spec *spec; 3717 struct mlx5_flow_table *ft = ft_prio->flow_table; 3718 int err = 0; 3719 3720 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3721 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3722 if (!handler || !spec) { 3723 err = -ENOMEM; 3724 goto free; 3725 } 3726 3727 INIT_LIST_HEAD(&handler->list); 3728 3729 memcpy(spec->match_value, cmd_in, inlen); 3730 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3731 fs_matcher->mask_len); 3732 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3733 3734 handler->rule = mlx5_add_flow_rules(ft, spec, 3735 flow_act, dst, 1); 3736 3737 if (IS_ERR(handler->rule)) { 3738 err = PTR_ERR(handler->rule); 3739 goto free; 3740 } 3741 3742 ft_prio->refcount++; 3743 handler->prio = ft_prio; 3744 handler->dev = dev; 3745 ft_prio->flow_table = ft; 3746 3747 free: 3748 if (err) 3749 kfree(handler); 3750 kvfree(spec); 3751 return err ? ERR_PTR(err) : handler; 3752 } 3753 3754 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3755 void *match_v) 3756 { 3757 void *match_c; 3758 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3759 void *dmac, *dmac_mask; 3760 void *ipv4, *ipv4_mask; 3761 3762 if (!(fs_matcher->match_criteria_enable & 3763 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3764 return false; 3765 3766 match_c = fs_matcher->matcher_mask.match_params; 3767 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3768 outer_headers); 3769 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3770 outer_headers); 3771 3772 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3773 dmac_47_16); 3774 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3775 dmac_47_16); 3776 3777 if (is_multicast_ether_addr(dmac) && 3778 is_multicast_ether_addr(dmac_mask)) 3779 return true; 3780 3781 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3782 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3783 3784 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3785 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3786 3787 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3788 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3789 return true; 3790 3791 return false; 3792 } 3793 3794 struct mlx5_ib_flow_handler * 3795 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3796 struct mlx5_ib_flow_matcher *fs_matcher, 3797 struct mlx5_flow_act *flow_act, 3798 void *cmd_in, int inlen, int dest_id, 3799 int dest_type) 3800 { 3801 struct mlx5_flow_destination *dst; 3802 struct mlx5_ib_flow_prio *ft_prio; 3803 struct mlx5_ib_flow_handler *handler; 3804 bool mcast; 3805 int err; 3806 3807 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3808 return ERR_PTR(-EOPNOTSUPP); 3809 3810 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3811 return ERR_PTR(-ENOMEM); 3812 3813 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3814 if (!dst) 3815 return ERR_PTR(-ENOMEM); 3816 3817 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3818 mutex_lock(&dev->flow_db->lock); 3819 3820 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 3821 if (IS_ERR(ft_prio)) { 3822 err = PTR_ERR(ft_prio); 3823 goto unlock; 3824 } 3825 3826 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3827 dst->type = dest_type; 3828 dst->tir_num = dest_id; 3829 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3830 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 3831 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3832 dst->ft_num = dest_id; 3833 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3834 } else { 3835 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3836 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3837 } 3838 3839 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 3840 cmd_in, inlen); 3841 3842 if (IS_ERR(handler)) { 3843 err = PTR_ERR(handler); 3844 goto destroy_ft; 3845 } 3846 3847 mutex_unlock(&dev->flow_db->lock); 3848 atomic_inc(&fs_matcher->usecnt); 3849 handler->flow_matcher = fs_matcher; 3850 3851 kfree(dst); 3852 3853 return handler; 3854 3855 destroy_ft: 3856 put_flow_table(dev, ft_prio, false); 3857 unlock: 3858 mutex_unlock(&dev->flow_db->lock); 3859 kfree(dst); 3860 3861 return ERR_PTR(err); 3862 } 3863 3864 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3865 { 3866 u32 flags = 0; 3867 3868 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3869 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3870 3871 return flags; 3872 } 3873 3874 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3875 static struct ib_flow_action * 3876 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3877 const struct ib_flow_action_attrs_esp *attr, 3878 struct uverbs_attr_bundle *attrs) 3879 { 3880 struct mlx5_ib_dev *mdev = to_mdev(device); 3881 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3882 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3883 struct mlx5_ib_flow_action *action; 3884 u64 action_flags; 3885 u64 flags; 3886 int err = 0; 3887 3888 err = uverbs_get_flags64( 3889 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3890 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 3891 if (err) 3892 return ERR_PTR(err); 3893 3894 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3895 3896 /* We current only support a subset of the standard features. Only a 3897 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3898 * (with overlap). Full offload mode isn't supported. 3899 */ 3900 if (!attr->keymat || attr->replay || attr->encap || 3901 attr->spi || attr->seq || attr->tfc_pad || 3902 attr->hard_limit_pkts || 3903 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3904 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3905 return ERR_PTR(-EOPNOTSUPP); 3906 3907 if (attr->keymat->protocol != 3908 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3909 return ERR_PTR(-EOPNOTSUPP); 3910 3911 aes_gcm = &attr->keymat->keymat.aes_gcm; 3912 3913 if (aes_gcm->icv_len != 16 || 3914 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3915 return ERR_PTR(-EOPNOTSUPP); 3916 3917 action = kmalloc(sizeof(*action), GFP_KERNEL); 3918 if (!action) 3919 return ERR_PTR(-ENOMEM); 3920 3921 action->esp_aes_gcm.ib_flags = attr->flags; 3922 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3923 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3924 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3925 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3926 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3927 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3928 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3929 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3930 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3931 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3932 3933 accel_attrs.esn = attr->esn; 3934 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3935 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3936 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3937 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3938 3939 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3940 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3941 3942 action->esp_aes_gcm.ctx = 3943 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3944 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3945 err = PTR_ERR(action->esp_aes_gcm.ctx); 3946 goto err_parse; 3947 } 3948 3949 action->esp_aes_gcm.ib_flags = attr->flags; 3950 3951 return &action->ib_action; 3952 3953 err_parse: 3954 kfree(action); 3955 return ERR_PTR(err); 3956 } 3957 3958 static int 3959 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3960 const struct ib_flow_action_attrs_esp *attr, 3961 struct uverbs_attr_bundle *attrs) 3962 { 3963 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3964 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3965 int err = 0; 3966 3967 if (attr->keymat || attr->replay || attr->encap || 3968 attr->spi || attr->seq || attr->tfc_pad || 3969 attr->hard_limit_pkts || 3970 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3971 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3972 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3973 return -EOPNOTSUPP; 3974 3975 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3976 * be modified. 3977 */ 3978 if (!(maction->esp_aes_gcm.ib_flags & 3979 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3980 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3981 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3982 return -EINVAL; 3983 3984 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3985 sizeof(accel_attrs)); 3986 3987 accel_attrs.esn = attr->esn; 3988 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3989 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3990 else 3991 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3992 3993 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3994 &accel_attrs); 3995 if (err) 3996 return err; 3997 3998 maction->esp_aes_gcm.ib_flags &= 3999 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4000 maction->esp_aes_gcm.ib_flags |= 4001 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4002 4003 return 0; 4004 } 4005 4006 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4007 { 4008 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4009 4010 switch (action->type) { 4011 case IB_FLOW_ACTION_ESP: 4012 /* 4013 * We only support aes_gcm by now, so we implicitly know this is 4014 * the underline crypto. 4015 */ 4016 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4017 break; 4018 case IB_FLOW_ACTION_UNSPECIFIED: 4019 mlx5_ib_destroy_flow_action_raw(maction); 4020 break; 4021 default: 4022 WARN_ON(true); 4023 break; 4024 } 4025 4026 kfree(maction); 4027 return 0; 4028 } 4029 4030 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4031 { 4032 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4033 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4034 int err; 4035 u16 uid; 4036 4037 uid = ibqp->pd ? 4038 to_mpd(ibqp->pd)->uid : 0; 4039 4040 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4041 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4042 return -EOPNOTSUPP; 4043 } 4044 4045 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4046 if (err) 4047 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4048 ibqp->qp_num, gid->raw); 4049 4050 return err; 4051 } 4052 4053 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4054 { 4055 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4056 int err; 4057 u16 uid; 4058 4059 uid = ibqp->pd ? 4060 to_mpd(ibqp->pd)->uid : 0; 4061 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4062 if (err) 4063 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4064 ibqp->qp_num, gid->raw); 4065 4066 return err; 4067 } 4068 4069 static int init_node_data(struct mlx5_ib_dev *dev) 4070 { 4071 int err; 4072 4073 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4074 if (err) 4075 return err; 4076 4077 dev->mdev->rev_id = dev->mdev->pdev->revision; 4078 4079 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4080 } 4081 4082 static ssize_t fw_pages_show(struct device *device, 4083 struct device_attribute *attr, char *buf) 4084 { 4085 struct mlx5_ib_dev *dev = 4086 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4087 4088 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4089 } 4090 static DEVICE_ATTR_RO(fw_pages); 4091 4092 static ssize_t reg_pages_show(struct device *device, 4093 struct device_attribute *attr, char *buf) 4094 { 4095 struct mlx5_ib_dev *dev = 4096 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4097 4098 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4099 } 4100 static DEVICE_ATTR_RO(reg_pages); 4101 4102 static ssize_t hca_type_show(struct device *device, 4103 struct device_attribute *attr, char *buf) 4104 { 4105 struct mlx5_ib_dev *dev = 4106 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4107 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4108 } 4109 static DEVICE_ATTR_RO(hca_type); 4110 4111 static ssize_t hw_rev_show(struct device *device, 4112 struct device_attribute *attr, char *buf) 4113 { 4114 struct mlx5_ib_dev *dev = 4115 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4116 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4117 } 4118 static DEVICE_ATTR_RO(hw_rev); 4119 4120 static ssize_t board_id_show(struct device *device, 4121 struct device_attribute *attr, char *buf) 4122 { 4123 struct mlx5_ib_dev *dev = 4124 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4125 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4126 dev->mdev->board_id); 4127 } 4128 static DEVICE_ATTR_RO(board_id); 4129 4130 static struct attribute *mlx5_class_attributes[] = { 4131 &dev_attr_hw_rev.attr, 4132 &dev_attr_hca_type.attr, 4133 &dev_attr_board_id.attr, 4134 &dev_attr_fw_pages.attr, 4135 &dev_attr_reg_pages.attr, 4136 NULL, 4137 }; 4138 4139 static const struct attribute_group mlx5_attr_group = { 4140 .attrs = mlx5_class_attributes, 4141 }; 4142 4143 static void pkey_change_handler(struct work_struct *work) 4144 { 4145 struct mlx5_ib_port_resources *ports = 4146 container_of(work, struct mlx5_ib_port_resources, 4147 pkey_change_work); 4148 4149 mutex_lock(&ports->devr->mutex); 4150 mlx5_ib_gsi_pkey_change(ports->gsi); 4151 mutex_unlock(&ports->devr->mutex); 4152 } 4153 4154 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4155 { 4156 struct mlx5_ib_qp *mqp; 4157 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4158 struct mlx5_core_cq *mcq; 4159 struct list_head cq_armed_list; 4160 unsigned long flags_qp; 4161 unsigned long flags_cq; 4162 unsigned long flags; 4163 4164 INIT_LIST_HEAD(&cq_armed_list); 4165 4166 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4167 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4168 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4169 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4170 if (mqp->sq.tail != mqp->sq.head) { 4171 send_mcq = to_mcq(mqp->ibqp.send_cq); 4172 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4173 if (send_mcq->mcq.comp && 4174 mqp->ibqp.send_cq->comp_handler) { 4175 if (!send_mcq->mcq.reset_notify_added) { 4176 send_mcq->mcq.reset_notify_added = 1; 4177 list_add_tail(&send_mcq->mcq.reset_notify, 4178 &cq_armed_list); 4179 } 4180 } 4181 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4182 } 4183 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4184 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4185 /* no handling is needed for SRQ */ 4186 if (!mqp->ibqp.srq) { 4187 if (mqp->rq.tail != mqp->rq.head) { 4188 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4189 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4190 if (recv_mcq->mcq.comp && 4191 mqp->ibqp.recv_cq->comp_handler) { 4192 if (!recv_mcq->mcq.reset_notify_added) { 4193 recv_mcq->mcq.reset_notify_added = 1; 4194 list_add_tail(&recv_mcq->mcq.reset_notify, 4195 &cq_armed_list); 4196 } 4197 } 4198 spin_unlock_irqrestore(&recv_mcq->lock, 4199 flags_cq); 4200 } 4201 } 4202 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4203 } 4204 /*At that point all inflight post send were put to be executed as of we 4205 * lock/unlock above locks Now need to arm all involved CQs. 4206 */ 4207 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4208 mcq->comp(mcq); 4209 } 4210 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4211 } 4212 4213 static void delay_drop_handler(struct work_struct *work) 4214 { 4215 int err; 4216 struct mlx5_ib_delay_drop *delay_drop = 4217 container_of(work, struct mlx5_ib_delay_drop, 4218 delay_drop_work); 4219 4220 atomic_inc(&delay_drop->events_cnt); 4221 4222 mutex_lock(&delay_drop->lock); 4223 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4224 delay_drop->timeout); 4225 if (err) { 4226 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4227 delay_drop->timeout); 4228 delay_drop->activate = false; 4229 } 4230 mutex_unlock(&delay_drop->lock); 4231 } 4232 4233 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4234 struct ib_event *ibev) 4235 { 4236 switch (eqe->sub_type) { 4237 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 4238 schedule_work(&ibdev->delay_drop.delay_drop_work); 4239 break; 4240 default: /* do nothing */ 4241 return; 4242 } 4243 } 4244 4245 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4246 struct ib_event *ibev) 4247 { 4248 u8 port = (eqe->data.port.port >> 4) & 0xf; 4249 4250 ibev->element.port_num = port; 4251 4252 switch (eqe->sub_type) { 4253 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 4254 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 4255 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 4256 /* In RoCE, port up/down events are handled in 4257 * mlx5_netdev_event(). 4258 */ 4259 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4260 IB_LINK_LAYER_ETHERNET) 4261 return -EINVAL; 4262 4263 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 4264 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4265 break; 4266 4267 case MLX5_PORT_CHANGE_SUBTYPE_LID: 4268 ibev->event = IB_EVENT_LID_CHANGE; 4269 break; 4270 4271 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 4272 ibev->event = IB_EVENT_PKEY_CHANGE; 4273 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4274 break; 4275 4276 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 4277 ibev->event = IB_EVENT_GID_CHANGE; 4278 break; 4279 4280 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 4281 ibev->event = IB_EVENT_CLIENT_REREGISTER; 4282 break; 4283 default: 4284 return -EINVAL; 4285 } 4286 4287 return 0; 4288 } 4289 4290 static void mlx5_ib_handle_event(struct work_struct *_work) 4291 { 4292 struct mlx5_ib_event_work *work = 4293 container_of(_work, struct mlx5_ib_event_work, work); 4294 struct mlx5_ib_dev *ibdev; 4295 struct ib_event ibev; 4296 bool fatal = false; 4297 4298 if (work->is_slave) { 4299 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 4300 if (!ibdev) 4301 goto out; 4302 } else { 4303 ibdev = work->dev; 4304 } 4305 4306 switch (work->event) { 4307 case MLX5_DEV_EVENT_SYS_ERROR: 4308 ibev.event = IB_EVENT_DEVICE_FATAL; 4309 mlx5_ib_handle_internal_error(ibdev); 4310 ibev.element.port_num = (u8)(unsigned long)work->param; 4311 fatal = true; 4312 break; 4313 case MLX5_EVENT_TYPE_PORT_CHANGE: 4314 if (handle_port_change(ibdev, work->param, &ibev)) 4315 goto out; 4316 break; 4317 case MLX5_EVENT_TYPE_GENERAL_EVENT: 4318 handle_general_event(ibdev, work->param, &ibev); 4319 /* fall through */ 4320 default: 4321 goto out; 4322 } 4323 4324 ibev.device = &ibdev->ib_dev; 4325 4326 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 4327 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 4328 goto out; 4329 } 4330 4331 if (ibdev->ib_active) 4332 ib_dispatch_event(&ibev); 4333 4334 if (fatal) 4335 ibdev->ib_active = false; 4336 out: 4337 kfree(work); 4338 } 4339 4340 static int mlx5_ib_event(struct notifier_block *nb, 4341 unsigned long event, void *param) 4342 { 4343 struct mlx5_ib_event_work *work; 4344 4345 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4346 if (!work) 4347 return NOTIFY_DONE; 4348 4349 INIT_WORK(&work->work, mlx5_ib_handle_event); 4350 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 4351 work->is_slave = false; 4352 work->param = param; 4353 work->event = event; 4354 4355 queue_work(mlx5_ib_event_wq, &work->work); 4356 4357 return NOTIFY_OK; 4358 } 4359 4360 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 4361 unsigned long event, void *param) 4362 { 4363 struct mlx5_ib_event_work *work; 4364 4365 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4366 if (!work) 4367 return NOTIFY_DONE; 4368 4369 INIT_WORK(&work->work, mlx5_ib_handle_event); 4370 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 4371 work->is_slave = true; 4372 work->param = param; 4373 work->event = event; 4374 queue_work(mlx5_ib_event_wq, &work->work); 4375 4376 return NOTIFY_OK; 4377 } 4378 4379 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4380 { 4381 struct mlx5_hca_vport_context vport_ctx; 4382 int err; 4383 int port; 4384 4385 for (port = 1; port <= dev->num_ports; port++) { 4386 dev->mdev->port_caps[port - 1].has_smi = false; 4387 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4388 MLX5_CAP_PORT_TYPE_IB) { 4389 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4390 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4391 port, 0, 4392 &vport_ctx); 4393 if (err) { 4394 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4395 port, err); 4396 return err; 4397 } 4398 dev->mdev->port_caps[port - 1].has_smi = 4399 vport_ctx.has_smi; 4400 } else { 4401 dev->mdev->port_caps[port - 1].has_smi = true; 4402 } 4403 } 4404 } 4405 return 0; 4406 } 4407 4408 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4409 { 4410 int port; 4411 4412 for (port = 1; port <= dev->num_ports; port++) 4413 mlx5_query_ext_port_caps(dev, port); 4414 } 4415 4416 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4417 { 4418 struct ib_device_attr *dprops = NULL; 4419 struct ib_port_attr *pprops = NULL; 4420 int err = -ENOMEM; 4421 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4422 4423 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4424 if (!pprops) 4425 goto out; 4426 4427 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4428 if (!dprops) 4429 goto out; 4430 4431 err = set_has_smi_cap(dev); 4432 if (err) 4433 goto out; 4434 4435 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4436 if (err) { 4437 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4438 goto out; 4439 } 4440 4441 memset(pprops, 0, sizeof(*pprops)); 4442 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4443 if (err) { 4444 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4445 port, err); 4446 goto out; 4447 } 4448 4449 dev->mdev->port_caps[port - 1].pkey_table_len = 4450 dprops->max_pkeys; 4451 dev->mdev->port_caps[port - 1].gid_table_len = 4452 pprops->gid_tbl_len; 4453 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4454 port, dprops->max_pkeys, pprops->gid_tbl_len); 4455 4456 out: 4457 kfree(pprops); 4458 kfree(dprops); 4459 4460 return err; 4461 } 4462 4463 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4464 { 4465 int err; 4466 4467 err = mlx5_mr_cache_cleanup(dev); 4468 if (err) 4469 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4470 4471 if (dev->umrc.qp) 4472 mlx5_ib_destroy_qp(dev->umrc.qp); 4473 if (dev->umrc.cq) 4474 ib_free_cq(dev->umrc.cq); 4475 if (dev->umrc.pd) 4476 ib_dealloc_pd(dev->umrc.pd); 4477 } 4478 4479 enum { 4480 MAX_UMR_WR = 128, 4481 }; 4482 4483 static int create_umr_res(struct mlx5_ib_dev *dev) 4484 { 4485 struct ib_qp_init_attr *init_attr = NULL; 4486 struct ib_qp_attr *attr = NULL; 4487 struct ib_pd *pd; 4488 struct ib_cq *cq; 4489 struct ib_qp *qp; 4490 int ret; 4491 4492 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4493 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4494 if (!attr || !init_attr) { 4495 ret = -ENOMEM; 4496 goto error_0; 4497 } 4498 4499 pd = ib_alloc_pd(&dev->ib_dev, 0); 4500 if (IS_ERR(pd)) { 4501 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4502 ret = PTR_ERR(pd); 4503 goto error_0; 4504 } 4505 4506 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4507 if (IS_ERR(cq)) { 4508 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4509 ret = PTR_ERR(cq); 4510 goto error_2; 4511 } 4512 4513 init_attr->send_cq = cq; 4514 init_attr->recv_cq = cq; 4515 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4516 init_attr->cap.max_send_wr = MAX_UMR_WR; 4517 init_attr->cap.max_send_sge = 1; 4518 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4519 init_attr->port_num = 1; 4520 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4521 if (IS_ERR(qp)) { 4522 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4523 ret = PTR_ERR(qp); 4524 goto error_3; 4525 } 4526 qp->device = &dev->ib_dev; 4527 qp->real_qp = qp; 4528 qp->uobject = NULL; 4529 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4530 qp->send_cq = init_attr->send_cq; 4531 qp->recv_cq = init_attr->recv_cq; 4532 4533 attr->qp_state = IB_QPS_INIT; 4534 attr->port_num = 1; 4535 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4536 IB_QP_PORT, NULL); 4537 if (ret) { 4538 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4539 goto error_4; 4540 } 4541 4542 memset(attr, 0, sizeof(*attr)); 4543 attr->qp_state = IB_QPS_RTR; 4544 attr->path_mtu = IB_MTU_256; 4545 4546 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4547 if (ret) { 4548 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4549 goto error_4; 4550 } 4551 4552 memset(attr, 0, sizeof(*attr)); 4553 attr->qp_state = IB_QPS_RTS; 4554 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4555 if (ret) { 4556 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4557 goto error_4; 4558 } 4559 4560 dev->umrc.qp = qp; 4561 dev->umrc.cq = cq; 4562 dev->umrc.pd = pd; 4563 4564 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4565 ret = mlx5_mr_cache_init(dev); 4566 if (ret) { 4567 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4568 goto error_4; 4569 } 4570 4571 kfree(attr); 4572 kfree(init_attr); 4573 4574 return 0; 4575 4576 error_4: 4577 mlx5_ib_destroy_qp(qp); 4578 dev->umrc.qp = NULL; 4579 4580 error_3: 4581 ib_free_cq(cq); 4582 dev->umrc.cq = NULL; 4583 4584 error_2: 4585 ib_dealloc_pd(pd); 4586 dev->umrc.pd = NULL; 4587 4588 error_0: 4589 kfree(attr); 4590 kfree(init_attr); 4591 return ret; 4592 } 4593 4594 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4595 { 4596 switch (umr_fence_cap) { 4597 case MLX5_CAP_UMR_FENCE_NONE: 4598 return MLX5_FENCE_MODE_NONE; 4599 case MLX5_CAP_UMR_FENCE_SMALL: 4600 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4601 default: 4602 return MLX5_FENCE_MODE_STRONG_ORDERING; 4603 } 4604 } 4605 4606 static int create_dev_resources(struct mlx5_ib_resources *devr) 4607 { 4608 struct ib_srq_init_attr attr; 4609 struct mlx5_ib_dev *dev; 4610 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4611 int port; 4612 int ret = 0; 4613 4614 dev = container_of(devr, struct mlx5_ib_dev, devr); 4615 4616 mutex_init(&devr->mutex); 4617 4618 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4619 if (IS_ERR(devr->p0)) { 4620 ret = PTR_ERR(devr->p0); 4621 goto error0; 4622 } 4623 devr->p0->device = &dev->ib_dev; 4624 devr->p0->uobject = NULL; 4625 atomic_set(&devr->p0->usecnt, 0); 4626 4627 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4628 if (IS_ERR(devr->c0)) { 4629 ret = PTR_ERR(devr->c0); 4630 goto error1; 4631 } 4632 devr->c0->device = &dev->ib_dev; 4633 devr->c0->uobject = NULL; 4634 devr->c0->comp_handler = NULL; 4635 devr->c0->event_handler = NULL; 4636 devr->c0->cq_context = NULL; 4637 atomic_set(&devr->c0->usecnt, 0); 4638 4639 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4640 if (IS_ERR(devr->x0)) { 4641 ret = PTR_ERR(devr->x0); 4642 goto error2; 4643 } 4644 devr->x0->device = &dev->ib_dev; 4645 devr->x0->inode = NULL; 4646 atomic_set(&devr->x0->usecnt, 0); 4647 mutex_init(&devr->x0->tgt_qp_mutex); 4648 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4649 4650 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4651 if (IS_ERR(devr->x1)) { 4652 ret = PTR_ERR(devr->x1); 4653 goto error3; 4654 } 4655 devr->x1->device = &dev->ib_dev; 4656 devr->x1->inode = NULL; 4657 atomic_set(&devr->x1->usecnt, 0); 4658 mutex_init(&devr->x1->tgt_qp_mutex); 4659 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4660 4661 memset(&attr, 0, sizeof(attr)); 4662 attr.attr.max_sge = 1; 4663 attr.attr.max_wr = 1; 4664 attr.srq_type = IB_SRQT_XRC; 4665 attr.ext.cq = devr->c0; 4666 attr.ext.xrc.xrcd = devr->x0; 4667 4668 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4669 if (IS_ERR(devr->s0)) { 4670 ret = PTR_ERR(devr->s0); 4671 goto error4; 4672 } 4673 devr->s0->device = &dev->ib_dev; 4674 devr->s0->pd = devr->p0; 4675 devr->s0->uobject = NULL; 4676 devr->s0->event_handler = NULL; 4677 devr->s0->srq_context = NULL; 4678 devr->s0->srq_type = IB_SRQT_XRC; 4679 devr->s0->ext.xrc.xrcd = devr->x0; 4680 devr->s0->ext.cq = devr->c0; 4681 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4682 atomic_inc(&devr->s0->ext.cq->usecnt); 4683 atomic_inc(&devr->p0->usecnt); 4684 atomic_set(&devr->s0->usecnt, 0); 4685 4686 memset(&attr, 0, sizeof(attr)); 4687 attr.attr.max_sge = 1; 4688 attr.attr.max_wr = 1; 4689 attr.srq_type = IB_SRQT_BASIC; 4690 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4691 if (IS_ERR(devr->s1)) { 4692 ret = PTR_ERR(devr->s1); 4693 goto error5; 4694 } 4695 devr->s1->device = &dev->ib_dev; 4696 devr->s1->pd = devr->p0; 4697 devr->s1->uobject = NULL; 4698 devr->s1->event_handler = NULL; 4699 devr->s1->srq_context = NULL; 4700 devr->s1->srq_type = IB_SRQT_BASIC; 4701 devr->s1->ext.cq = devr->c0; 4702 atomic_inc(&devr->p0->usecnt); 4703 atomic_set(&devr->s1->usecnt, 0); 4704 4705 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4706 INIT_WORK(&devr->ports[port].pkey_change_work, 4707 pkey_change_handler); 4708 devr->ports[port].devr = devr; 4709 } 4710 4711 return 0; 4712 4713 error5: 4714 mlx5_ib_destroy_srq(devr->s0); 4715 error4: 4716 mlx5_ib_dealloc_xrcd(devr->x1); 4717 error3: 4718 mlx5_ib_dealloc_xrcd(devr->x0); 4719 error2: 4720 mlx5_ib_destroy_cq(devr->c0); 4721 error1: 4722 mlx5_ib_dealloc_pd(devr->p0); 4723 error0: 4724 return ret; 4725 } 4726 4727 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4728 { 4729 struct mlx5_ib_dev *dev = 4730 container_of(devr, struct mlx5_ib_dev, devr); 4731 int port; 4732 4733 mlx5_ib_destroy_srq(devr->s1); 4734 mlx5_ib_destroy_srq(devr->s0); 4735 mlx5_ib_dealloc_xrcd(devr->x0); 4736 mlx5_ib_dealloc_xrcd(devr->x1); 4737 mlx5_ib_destroy_cq(devr->c0); 4738 mlx5_ib_dealloc_pd(devr->p0); 4739 4740 /* Make sure no change P_Key work items are still executing */ 4741 for (port = 0; port < dev->num_ports; ++port) 4742 cancel_work_sync(&devr->ports[port].pkey_change_work); 4743 } 4744 4745 static u32 get_core_cap_flags(struct ib_device *ibdev, 4746 struct mlx5_hca_vport_context *rep) 4747 { 4748 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4749 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4750 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4751 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4752 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4753 u32 ret = 0; 4754 4755 if (rep->grh_required) 4756 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4757 4758 if (ll == IB_LINK_LAYER_INFINIBAND) 4759 return ret | RDMA_CORE_PORT_IBA_IB; 4760 4761 if (raw_support) 4762 ret |= RDMA_CORE_PORT_RAW_PACKET; 4763 4764 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4765 return ret; 4766 4767 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4768 return ret; 4769 4770 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4771 ret |= RDMA_CORE_PORT_IBA_ROCE; 4772 4773 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4774 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4775 4776 return ret; 4777 } 4778 4779 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4780 struct ib_port_immutable *immutable) 4781 { 4782 struct ib_port_attr attr; 4783 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4784 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4785 struct mlx5_hca_vport_context rep = {0}; 4786 int err; 4787 4788 err = ib_query_port(ibdev, port_num, &attr); 4789 if (err) 4790 return err; 4791 4792 if (ll == IB_LINK_LAYER_INFINIBAND) { 4793 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4794 &rep); 4795 if (err) 4796 return err; 4797 } 4798 4799 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4800 immutable->gid_tbl_len = attr.gid_tbl_len; 4801 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4802 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4803 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4804 4805 return 0; 4806 } 4807 4808 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4809 struct ib_port_immutable *immutable) 4810 { 4811 struct ib_port_attr attr; 4812 int err; 4813 4814 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4815 4816 err = ib_query_port(ibdev, port_num, &attr); 4817 if (err) 4818 return err; 4819 4820 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4821 immutable->gid_tbl_len = attr.gid_tbl_len; 4822 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4823 4824 return 0; 4825 } 4826 4827 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4828 { 4829 struct mlx5_ib_dev *dev = 4830 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4831 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4832 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4833 fw_rev_sub(dev->mdev)); 4834 } 4835 4836 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4837 { 4838 struct mlx5_core_dev *mdev = dev->mdev; 4839 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4840 MLX5_FLOW_NAMESPACE_LAG); 4841 struct mlx5_flow_table *ft; 4842 int err; 4843 4844 if (!ns || !mlx5_lag_is_roce(mdev)) 4845 return 0; 4846 4847 err = mlx5_cmd_create_vport_lag(mdev); 4848 if (err) 4849 return err; 4850 4851 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4852 if (IS_ERR(ft)) { 4853 err = PTR_ERR(ft); 4854 goto err_destroy_vport_lag; 4855 } 4856 4857 dev->flow_db->lag_demux_ft = ft; 4858 dev->lag_active = true; 4859 return 0; 4860 4861 err_destroy_vport_lag: 4862 mlx5_cmd_destroy_vport_lag(mdev); 4863 return err; 4864 } 4865 4866 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4867 { 4868 struct mlx5_core_dev *mdev = dev->mdev; 4869 4870 if (dev->lag_active) { 4871 dev->lag_active = false; 4872 4873 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4874 dev->flow_db->lag_demux_ft = NULL; 4875 4876 mlx5_cmd_destroy_vport_lag(mdev); 4877 } 4878 } 4879 4880 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4881 { 4882 int err; 4883 4884 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4885 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4886 if (err) { 4887 dev->roce[port_num].nb.notifier_call = NULL; 4888 return err; 4889 } 4890 4891 return 0; 4892 } 4893 4894 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4895 { 4896 if (dev->roce[port_num].nb.notifier_call) { 4897 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4898 dev->roce[port_num].nb.notifier_call = NULL; 4899 } 4900 } 4901 4902 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 4903 { 4904 int err; 4905 4906 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4907 err = mlx5_nic_vport_enable_roce(dev->mdev); 4908 if (err) 4909 return err; 4910 } 4911 4912 err = mlx5_eth_lag_init(dev); 4913 if (err) 4914 goto err_disable_roce; 4915 4916 return 0; 4917 4918 err_disable_roce: 4919 if (MLX5_CAP_GEN(dev->mdev, roce)) 4920 mlx5_nic_vport_disable_roce(dev->mdev); 4921 4922 return err; 4923 } 4924 4925 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4926 { 4927 mlx5_eth_lag_cleanup(dev); 4928 if (MLX5_CAP_GEN(dev->mdev, roce)) 4929 mlx5_nic_vport_disable_roce(dev->mdev); 4930 } 4931 4932 struct mlx5_ib_counter { 4933 const char *name; 4934 size_t offset; 4935 }; 4936 4937 #define INIT_Q_COUNTER(_name) \ 4938 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4939 4940 static const struct mlx5_ib_counter basic_q_cnts[] = { 4941 INIT_Q_COUNTER(rx_write_requests), 4942 INIT_Q_COUNTER(rx_read_requests), 4943 INIT_Q_COUNTER(rx_atomic_requests), 4944 INIT_Q_COUNTER(out_of_buffer), 4945 }; 4946 4947 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4948 INIT_Q_COUNTER(out_of_sequence), 4949 }; 4950 4951 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4952 INIT_Q_COUNTER(duplicate_request), 4953 INIT_Q_COUNTER(rnr_nak_retry_err), 4954 INIT_Q_COUNTER(packet_seq_err), 4955 INIT_Q_COUNTER(implied_nak_seq_err), 4956 INIT_Q_COUNTER(local_ack_timeout_err), 4957 }; 4958 4959 #define INIT_CONG_COUNTER(_name) \ 4960 { .name = #_name, .offset = \ 4961 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4962 4963 static const struct mlx5_ib_counter cong_cnts[] = { 4964 INIT_CONG_COUNTER(rp_cnp_ignored), 4965 INIT_CONG_COUNTER(rp_cnp_handled), 4966 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4967 INIT_CONG_COUNTER(np_cnp_sent), 4968 }; 4969 4970 static const struct mlx5_ib_counter extended_err_cnts[] = { 4971 INIT_Q_COUNTER(resp_local_length_error), 4972 INIT_Q_COUNTER(resp_cqe_error), 4973 INIT_Q_COUNTER(req_cqe_error), 4974 INIT_Q_COUNTER(req_remote_invalid_request), 4975 INIT_Q_COUNTER(req_remote_access_errors), 4976 INIT_Q_COUNTER(resp_remote_access_errors), 4977 INIT_Q_COUNTER(resp_cqe_flush_error), 4978 INIT_Q_COUNTER(req_cqe_flush_error), 4979 }; 4980 4981 #define INIT_EXT_PPCNT_COUNTER(_name) \ 4982 { .name = #_name, .offset = \ 4983 MLX5_BYTE_OFF(ppcnt_reg, \ 4984 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 4985 4986 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 4987 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 4988 }; 4989 4990 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4991 { 4992 int i; 4993 4994 for (i = 0; i < dev->num_ports; i++) { 4995 if (dev->port[i].cnts.set_id_valid) 4996 mlx5_core_dealloc_q_counter(dev->mdev, 4997 dev->port[i].cnts.set_id); 4998 kfree(dev->port[i].cnts.names); 4999 kfree(dev->port[i].cnts.offsets); 5000 } 5001 } 5002 5003 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 5004 struct mlx5_ib_counters *cnts) 5005 { 5006 u32 num_counters; 5007 5008 num_counters = ARRAY_SIZE(basic_q_cnts); 5009 5010 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 5011 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 5012 5013 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 5014 num_counters += ARRAY_SIZE(retrans_q_cnts); 5015 5016 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 5017 num_counters += ARRAY_SIZE(extended_err_cnts); 5018 5019 cnts->num_q_counters = num_counters; 5020 5021 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5022 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 5023 num_counters += ARRAY_SIZE(cong_cnts); 5024 } 5025 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5026 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 5027 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 5028 } 5029 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 5030 if (!cnts->names) 5031 return -ENOMEM; 5032 5033 cnts->offsets = kcalloc(num_counters, 5034 sizeof(cnts->offsets), GFP_KERNEL); 5035 if (!cnts->offsets) 5036 goto err_names; 5037 5038 return 0; 5039 5040 err_names: 5041 kfree(cnts->names); 5042 cnts->names = NULL; 5043 return -ENOMEM; 5044 } 5045 5046 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 5047 const char **names, 5048 size_t *offsets) 5049 { 5050 int i; 5051 int j = 0; 5052 5053 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5054 names[j] = basic_q_cnts[i].name; 5055 offsets[j] = basic_q_cnts[i].offset; 5056 } 5057 5058 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5059 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5060 names[j] = out_of_seq_q_cnts[i].name; 5061 offsets[j] = out_of_seq_q_cnts[i].offset; 5062 } 5063 } 5064 5065 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5066 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5067 names[j] = retrans_q_cnts[i].name; 5068 offsets[j] = retrans_q_cnts[i].offset; 5069 } 5070 } 5071 5072 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5073 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5074 names[j] = extended_err_cnts[i].name; 5075 offsets[j] = extended_err_cnts[i].offset; 5076 } 5077 } 5078 5079 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5080 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5081 names[j] = cong_cnts[i].name; 5082 offsets[j] = cong_cnts[i].offset; 5083 } 5084 } 5085 5086 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5087 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5088 names[j] = ext_ppcnt_cnts[i].name; 5089 offsets[j] = ext_ppcnt_cnts[i].offset; 5090 } 5091 } 5092 } 5093 5094 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5095 { 5096 int err = 0; 5097 int i; 5098 5099 for (i = 0; i < dev->num_ports; i++) { 5100 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5101 if (err) 5102 goto err_alloc; 5103 5104 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5105 dev->port[i].cnts.offsets); 5106 5107 err = mlx5_core_alloc_q_counter(dev->mdev, 5108 &dev->port[i].cnts.set_id); 5109 if (err) { 5110 mlx5_ib_warn(dev, 5111 "couldn't allocate queue counter for port %d, err %d\n", 5112 i + 1, err); 5113 goto err_alloc; 5114 } 5115 dev->port[i].cnts.set_id_valid = true; 5116 } 5117 5118 return 0; 5119 5120 err_alloc: 5121 mlx5_ib_dealloc_counters(dev); 5122 return err; 5123 } 5124 5125 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5126 u8 port_num) 5127 { 5128 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5129 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5130 5131 /* We support only per port stats */ 5132 if (port_num == 0) 5133 return NULL; 5134 5135 return rdma_alloc_hw_stats_struct(port->cnts.names, 5136 port->cnts.num_q_counters + 5137 port->cnts.num_cong_counters + 5138 port->cnts.num_ext_ppcnt_counters, 5139 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5140 } 5141 5142 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5143 struct mlx5_ib_port *port, 5144 struct rdma_hw_stats *stats) 5145 { 5146 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5147 void *out; 5148 __be32 val; 5149 int ret, i; 5150 5151 out = kvzalloc(outlen, GFP_KERNEL); 5152 if (!out) 5153 return -ENOMEM; 5154 5155 ret = mlx5_core_query_q_counter(mdev, 5156 port->cnts.set_id, 0, 5157 out, outlen); 5158 if (ret) 5159 goto free; 5160 5161 for (i = 0; i < port->cnts.num_q_counters; i++) { 5162 val = *(__be32 *)(out + port->cnts.offsets[i]); 5163 stats->value[i] = (u64)be32_to_cpu(val); 5164 } 5165 5166 free: 5167 kvfree(out); 5168 return ret; 5169 } 5170 5171 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5172 struct mlx5_ib_port *port, 5173 struct rdma_hw_stats *stats) 5174 { 5175 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5176 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5177 int ret, i; 5178 void *out; 5179 5180 out = kvzalloc(sz, GFP_KERNEL); 5181 if (!out) 5182 return -ENOMEM; 5183 5184 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5185 if (ret) 5186 goto free; 5187 5188 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5189 stats->value[i + offset] = 5190 be64_to_cpup((__be64 *)(out + 5191 port->cnts.offsets[i + offset])); 5192 } 5193 5194 free: 5195 kvfree(out); 5196 return ret; 5197 } 5198 5199 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5200 struct rdma_hw_stats *stats, 5201 u8 port_num, int index) 5202 { 5203 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5204 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5205 struct mlx5_core_dev *mdev; 5206 int ret, num_counters; 5207 u8 mdev_port_num; 5208 5209 if (!stats) 5210 return -EINVAL; 5211 5212 num_counters = port->cnts.num_q_counters + 5213 port->cnts.num_cong_counters + 5214 port->cnts.num_ext_ppcnt_counters; 5215 5216 /* q_counters are per IB device, query the master mdev */ 5217 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5218 if (ret) 5219 return ret; 5220 5221 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5222 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5223 if (ret) 5224 return ret; 5225 } 5226 5227 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5228 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5229 &mdev_port_num); 5230 if (!mdev) { 5231 /* If port is not affiliated yet, its in down state 5232 * which doesn't have any counters yet, so it would be 5233 * zero. So no need to read from the HCA. 5234 */ 5235 goto done; 5236 } 5237 ret = mlx5_lag_query_cong_counters(dev->mdev, 5238 stats->value + 5239 port->cnts.num_q_counters, 5240 port->cnts.num_cong_counters, 5241 port->cnts.offsets + 5242 port->cnts.num_q_counters); 5243 5244 mlx5_ib_put_native_port_mdev(dev, port_num); 5245 if (ret) 5246 return ret; 5247 } 5248 5249 done: 5250 return num_counters; 5251 } 5252 5253 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5254 enum rdma_netdev_t type, 5255 struct rdma_netdev_alloc_params *params) 5256 { 5257 if (type != RDMA_NETDEV_IPOIB) 5258 return -EOPNOTSUPP; 5259 5260 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5261 } 5262 5263 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5264 { 5265 if (!dev->delay_drop.dbg) 5266 return; 5267 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5268 kfree(dev->delay_drop.dbg); 5269 dev->delay_drop.dbg = NULL; 5270 } 5271 5272 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5273 { 5274 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5275 return; 5276 5277 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5278 delay_drop_debugfs_cleanup(dev); 5279 } 5280 5281 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5282 size_t count, loff_t *pos) 5283 { 5284 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5285 char lbuf[20]; 5286 int len; 5287 5288 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5289 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5290 } 5291 5292 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5293 size_t count, loff_t *pos) 5294 { 5295 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5296 u32 timeout; 5297 u32 var; 5298 5299 if (kstrtouint_from_user(buf, count, 0, &var)) 5300 return -EFAULT; 5301 5302 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5303 1000); 5304 if (timeout != var) 5305 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5306 timeout); 5307 5308 delay_drop->timeout = timeout; 5309 5310 return count; 5311 } 5312 5313 static const struct file_operations fops_delay_drop_timeout = { 5314 .owner = THIS_MODULE, 5315 .open = simple_open, 5316 .write = delay_drop_timeout_write, 5317 .read = delay_drop_timeout_read, 5318 }; 5319 5320 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5321 { 5322 struct mlx5_ib_dbg_delay_drop *dbg; 5323 5324 if (!mlx5_debugfs_root) 5325 return 0; 5326 5327 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5328 if (!dbg) 5329 return -ENOMEM; 5330 5331 dev->delay_drop.dbg = dbg; 5332 5333 dbg->dir_debugfs = 5334 debugfs_create_dir("delay_drop", 5335 dev->mdev->priv.dbg_root); 5336 if (!dbg->dir_debugfs) 5337 goto out_debugfs; 5338 5339 dbg->events_cnt_debugfs = 5340 debugfs_create_atomic_t("num_timeout_events", 0400, 5341 dbg->dir_debugfs, 5342 &dev->delay_drop.events_cnt); 5343 if (!dbg->events_cnt_debugfs) 5344 goto out_debugfs; 5345 5346 dbg->rqs_cnt_debugfs = 5347 debugfs_create_atomic_t("num_rqs", 0400, 5348 dbg->dir_debugfs, 5349 &dev->delay_drop.rqs_cnt); 5350 if (!dbg->rqs_cnt_debugfs) 5351 goto out_debugfs; 5352 5353 dbg->timeout_debugfs = 5354 debugfs_create_file("timeout", 0600, 5355 dbg->dir_debugfs, 5356 &dev->delay_drop, 5357 &fops_delay_drop_timeout); 5358 if (!dbg->timeout_debugfs) 5359 goto out_debugfs; 5360 5361 return 0; 5362 5363 out_debugfs: 5364 delay_drop_debugfs_cleanup(dev); 5365 return -ENOMEM; 5366 } 5367 5368 static void init_delay_drop(struct mlx5_ib_dev *dev) 5369 { 5370 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5371 return; 5372 5373 mutex_init(&dev->delay_drop.lock); 5374 dev->delay_drop.dev = dev; 5375 dev->delay_drop.activate = false; 5376 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5377 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5378 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5379 atomic_set(&dev->delay_drop.events_cnt, 0); 5380 5381 if (delay_drop_debugfs_init(dev)) 5382 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5383 } 5384 5385 static const struct cpumask * 5386 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 5387 { 5388 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5389 5390 return mlx5_comp_irq_get_affinity_mask(dev->mdev, comp_vector); 5391 } 5392 5393 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5394 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5395 struct mlx5_ib_multiport_info *mpi) 5396 { 5397 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5398 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5399 int comps; 5400 int err; 5401 int i; 5402 5403 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5404 5405 spin_lock(&port->mp.mpi_lock); 5406 if (!mpi->ibdev) { 5407 spin_unlock(&port->mp.mpi_lock); 5408 return; 5409 } 5410 5411 if (mpi->mdev_events.notifier_call) 5412 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 5413 mpi->mdev_events.notifier_call = NULL; 5414 5415 mpi->ibdev = NULL; 5416 5417 spin_unlock(&port->mp.mpi_lock); 5418 mlx5_remove_netdev_notifier(ibdev, port_num); 5419 spin_lock(&port->mp.mpi_lock); 5420 5421 comps = mpi->mdev_refcnt; 5422 if (comps) { 5423 mpi->unaffiliate = true; 5424 init_completion(&mpi->unref_comp); 5425 spin_unlock(&port->mp.mpi_lock); 5426 5427 for (i = 0; i < comps; i++) 5428 wait_for_completion(&mpi->unref_comp); 5429 5430 spin_lock(&port->mp.mpi_lock); 5431 mpi->unaffiliate = false; 5432 } 5433 5434 port->mp.mpi = NULL; 5435 5436 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5437 5438 spin_unlock(&port->mp.mpi_lock); 5439 5440 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5441 5442 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5443 /* Log an error, still needed to cleanup the pointers and add 5444 * it back to the list. 5445 */ 5446 if (err) 5447 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5448 port_num + 1); 5449 5450 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5451 } 5452 5453 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5454 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5455 struct mlx5_ib_multiport_info *mpi) 5456 { 5457 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5458 int err; 5459 5460 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5461 if (ibdev->port[port_num].mp.mpi) { 5462 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5463 port_num + 1); 5464 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5465 return false; 5466 } 5467 5468 ibdev->port[port_num].mp.mpi = mpi; 5469 mpi->ibdev = ibdev; 5470 mpi->mdev_events.notifier_call = NULL; 5471 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5472 5473 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5474 if (err) 5475 goto unbind; 5476 5477 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5478 if (err) 5479 goto unbind; 5480 5481 err = mlx5_add_netdev_notifier(ibdev, port_num); 5482 if (err) { 5483 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5484 port_num + 1); 5485 goto unbind; 5486 } 5487 5488 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 5489 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 5490 5491 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 5492 if (err) 5493 goto unbind; 5494 5495 return true; 5496 5497 unbind: 5498 mlx5_ib_unbind_slave_port(ibdev, mpi); 5499 return false; 5500 } 5501 5502 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5503 { 5504 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5505 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5506 port_num + 1); 5507 struct mlx5_ib_multiport_info *mpi; 5508 int err; 5509 int i; 5510 5511 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5512 return 0; 5513 5514 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5515 &dev->sys_image_guid); 5516 if (err) 5517 return err; 5518 5519 err = mlx5_nic_vport_enable_roce(dev->mdev); 5520 if (err) 5521 return err; 5522 5523 mutex_lock(&mlx5_ib_multiport_mutex); 5524 for (i = 0; i < dev->num_ports; i++) { 5525 bool bound = false; 5526 5527 /* build a stub multiport info struct for the native port. */ 5528 if (i == port_num) { 5529 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5530 if (!mpi) { 5531 mutex_unlock(&mlx5_ib_multiport_mutex); 5532 mlx5_nic_vport_disable_roce(dev->mdev); 5533 return -ENOMEM; 5534 } 5535 5536 mpi->is_master = true; 5537 mpi->mdev = dev->mdev; 5538 mpi->sys_image_guid = dev->sys_image_guid; 5539 dev->port[i].mp.mpi = mpi; 5540 mpi->ibdev = dev; 5541 mpi = NULL; 5542 continue; 5543 } 5544 5545 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5546 list) { 5547 if (dev->sys_image_guid == mpi->sys_image_guid && 5548 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5549 bound = mlx5_ib_bind_slave_port(dev, mpi); 5550 } 5551 5552 if (bound) { 5553 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5554 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5555 list_del(&mpi->list); 5556 break; 5557 } 5558 } 5559 if (!bound) { 5560 get_port_caps(dev, i + 1); 5561 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5562 i + 1); 5563 } 5564 } 5565 5566 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5567 mutex_unlock(&mlx5_ib_multiport_mutex); 5568 return err; 5569 } 5570 5571 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5572 { 5573 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5574 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5575 port_num + 1); 5576 int i; 5577 5578 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5579 return; 5580 5581 mutex_lock(&mlx5_ib_multiport_mutex); 5582 for (i = 0; i < dev->num_ports; i++) { 5583 if (dev->port[i].mp.mpi) { 5584 /* Destroy the native port stub */ 5585 if (i == port_num) { 5586 kfree(dev->port[i].mp.mpi); 5587 dev->port[i].mp.mpi = NULL; 5588 } else { 5589 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5590 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5591 } 5592 } 5593 } 5594 5595 mlx5_ib_dbg(dev, "removing from devlist\n"); 5596 list_del(&dev->ib_dev_list); 5597 mutex_unlock(&mlx5_ib_multiport_mutex); 5598 5599 mlx5_nic_vport_disable_roce(dev->mdev); 5600 } 5601 5602 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5603 mlx5_ib_dm, 5604 UVERBS_OBJECT_DM, 5605 UVERBS_METHOD_DM_ALLOC, 5606 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5607 UVERBS_ATTR_TYPE(u64), 5608 UA_MANDATORY), 5609 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5610 UVERBS_ATTR_TYPE(u16), 5611 UA_MANDATORY)); 5612 5613 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5614 mlx5_ib_flow_action, 5615 UVERBS_OBJECT_FLOW_ACTION, 5616 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5617 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5618 enum mlx5_ib_uapi_flow_action_flags)); 5619 5620 static int populate_specs_root(struct mlx5_ib_dev *dev) 5621 { 5622 const struct uverbs_object_tree_def **trees = dev->driver_trees; 5623 size_t num_trees = 0; 5624 5625 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 5626 MLX5_ACCEL_IPSEC_CAP_DEVICE) 5627 trees[num_trees++] = &mlx5_ib_flow_action; 5628 5629 if (MLX5_CAP_DEV_MEM(dev->mdev, memic)) 5630 trees[num_trees++] = &mlx5_ib_dm; 5631 5632 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 5633 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX) 5634 trees[num_trees++] = mlx5_ib_get_devx_tree(); 5635 5636 num_trees += mlx5_ib_get_flow_trees(trees + num_trees); 5637 5638 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees)); 5639 trees[num_trees] = NULL; 5640 dev->ib_dev.driver_specs = trees; 5641 5642 return 0; 5643 } 5644 5645 static int mlx5_ib_read_counters(struct ib_counters *counters, 5646 struct ib_counters_read_attr *read_attr, 5647 struct uverbs_attr_bundle *attrs) 5648 { 5649 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5650 struct mlx5_read_counters_attr mread_attr = {}; 5651 struct mlx5_ib_flow_counters_desc *desc; 5652 int ret, i; 5653 5654 mutex_lock(&mcounters->mcntrs_mutex); 5655 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5656 ret = -EINVAL; 5657 goto err_bound; 5658 } 5659 5660 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5661 GFP_KERNEL); 5662 if (!mread_attr.out) { 5663 ret = -ENOMEM; 5664 goto err_bound; 5665 } 5666 5667 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5668 mread_attr.flags = read_attr->flags; 5669 ret = mcounters->read_counters(counters->device, &mread_attr); 5670 if (ret) 5671 goto err_read; 5672 5673 /* do the pass over the counters data array to assign according to the 5674 * descriptions and indexing pairs 5675 */ 5676 desc = mcounters->counters_data; 5677 for (i = 0; i < mcounters->ncounters; i++) 5678 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5679 5680 err_read: 5681 kfree(mread_attr.out); 5682 err_bound: 5683 mutex_unlock(&mcounters->mcntrs_mutex); 5684 return ret; 5685 } 5686 5687 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5688 { 5689 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5690 5691 counters_clear_description(counters); 5692 if (mcounters->hw_cntrs_hndl) 5693 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5694 mcounters->hw_cntrs_hndl); 5695 5696 kfree(mcounters); 5697 5698 return 0; 5699 } 5700 5701 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5702 struct uverbs_attr_bundle *attrs) 5703 { 5704 struct mlx5_ib_mcounters *mcounters; 5705 5706 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5707 if (!mcounters) 5708 return ERR_PTR(-ENOMEM); 5709 5710 mutex_init(&mcounters->mcntrs_mutex); 5711 5712 return &mcounters->ibcntrs; 5713 } 5714 5715 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5716 { 5717 mlx5_ib_cleanup_multiport_master(dev); 5718 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5719 cleanup_srcu_struct(&dev->mr_srcu); 5720 #endif 5721 kfree(dev->port); 5722 } 5723 5724 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5725 { 5726 struct mlx5_core_dev *mdev = dev->mdev; 5727 int err; 5728 int i; 5729 5730 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5731 GFP_KERNEL); 5732 if (!dev->port) 5733 return -ENOMEM; 5734 5735 for (i = 0; i < dev->num_ports; i++) { 5736 spin_lock_init(&dev->port[i].mp.mpi_lock); 5737 rwlock_init(&dev->roce[i].netdev_lock); 5738 } 5739 5740 err = mlx5_ib_init_multiport_master(dev); 5741 if (err) 5742 goto err_free_port; 5743 5744 if (!mlx5_core_mp_enabled(mdev)) { 5745 for (i = 1; i <= dev->num_ports; i++) { 5746 err = get_port_caps(dev, i); 5747 if (err) 5748 break; 5749 } 5750 } else { 5751 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5752 } 5753 if (err) 5754 goto err_mp; 5755 5756 if (mlx5_use_mad_ifc(dev)) 5757 get_ext_port_caps(dev); 5758 5759 dev->ib_dev.owner = THIS_MODULE; 5760 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5761 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5762 dev->ib_dev.phys_port_cnt = dev->num_ports; 5763 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 5764 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5765 5766 mutex_init(&dev->cap_mask_mutex); 5767 INIT_LIST_HEAD(&dev->qp_list); 5768 spin_lock_init(&dev->reset_flow_resource_lock); 5769 5770 spin_lock_init(&dev->memic.memic_lock); 5771 dev->memic.dev = mdev; 5772 5773 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5774 err = init_srcu_struct(&dev->mr_srcu); 5775 if (err) 5776 goto err_free_port; 5777 #endif 5778 5779 return 0; 5780 err_mp: 5781 mlx5_ib_cleanup_multiport_master(dev); 5782 5783 err_free_port: 5784 kfree(dev->port); 5785 5786 return -ENOMEM; 5787 } 5788 5789 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5790 { 5791 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5792 5793 if (!dev->flow_db) 5794 return -ENOMEM; 5795 5796 mutex_init(&dev->flow_db->lock); 5797 5798 return 0; 5799 } 5800 5801 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5802 { 5803 struct mlx5_ib_dev *nic_dev; 5804 5805 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5806 5807 if (!nic_dev) 5808 return -EINVAL; 5809 5810 dev->flow_db = nic_dev->flow_db; 5811 5812 return 0; 5813 } 5814 5815 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5816 { 5817 kfree(dev->flow_db); 5818 } 5819 5820 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5821 { 5822 struct mlx5_core_dev *mdev = dev->mdev; 5823 int err; 5824 5825 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5826 dev->ib_dev.uverbs_cmd_mask = 5827 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5828 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5829 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5830 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5831 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5832 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5833 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5834 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5835 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5836 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5837 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5838 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5839 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5840 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5841 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5842 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5843 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5844 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5845 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5846 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5847 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5848 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5849 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5850 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5851 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5852 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5853 dev->ib_dev.uverbs_ex_cmd_mask = 5854 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5855 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5856 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5857 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5858 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5859 5860 dev->ib_dev.query_device = mlx5_ib_query_device; 5861 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5862 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5863 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5864 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5865 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5866 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5867 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5868 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5869 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5870 dev->ib_dev.mmap = mlx5_ib_mmap; 5871 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5872 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5873 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5874 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5875 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5876 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5877 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5878 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5879 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5880 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5881 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5882 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5883 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5884 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5885 dev->ib_dev.drain_sq = mlx5_ib_drain_sq; 5886 dev->ib_dev.drain_rq = mlx5_ib_drain_rq; 5887 dev->ib_dev.post_send = mlx5_ib_post_send; 5888 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5889 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5890 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5891 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5892 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5893 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5894 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5895 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5896 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5897 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5898 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5899 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5900 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5901 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5902 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5903 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5904 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5905 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5906 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5907 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 5908 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 5909 dev->ib_dev.rdma_netdev_get_params = mlx5_ib_rn_get_params; 5910 5911 if (mlx5_core_is_pf(mdev)) { 5912 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5913 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5914 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5915 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5916 } 5917 5918 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5919 5920 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5921 5922 if (MLX5_CAP_GEN(mdev, imaicl)) { 5923 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5924 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5925 dev->ib_dev.uverbs_cmd_mask |= 5926 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5927 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5928 } 5929 5930 if (MLX5_CAP_GEN(mdev, xrc)) { 5931 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5932 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5933 dev->ib_dev.uverbs_cmd_mask |= 5934 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5935 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5936 } 5937 5938 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5939 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5940 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5941 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr; 5942 } 5943 5944 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5945 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5946 dev->ib_dev.uverbs_ex_cmd_mask |= 5947 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5948 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5949 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5950 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5951 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5952 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5953 dev->ib_dev.create_counters = mlx5_ib_create_counters; 5954 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters; 5955 dev->ib_dev.read_counters = mlx5_ib_read_counters; 5956 5957 err = init_node_data(dev); 5958 if (err) 5959 return err; 5960 5961 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5962 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5963 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5964 mutex_init(&dev->lb.mutex); 5965 5966 return 0; 5967 } 5968 5969 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5970 { 5971 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5972 dev->ib_dev.query_port = mlx5_ib_query_port; 5973 5974 return 0; 5975 } 5976 5977 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5978 { 5979 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5980 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5981 5982 return 0; 5983 } 5984 5985 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 5986 { 5987 u8 port_num; 5988 int i; 5989 5990 for (i = 0; i < dev->num_ports; i++) { 5991 dev->roce[i].dev = dev; 5992 dev->roce[i].native_port_num = i + 1; 5993 dev->roce[i].last_port_state = IB_PORT_DOWN; 5994 } 5995 5996 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5997 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5998 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5999 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 6000 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 6001 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 6002 6003 dev->ib_dev.uverbs_ex_cmd_mask |= 6004 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 6005 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 6006 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 6007 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 6008 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 6009 6010 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6011 6012 return mlx5_add_netdev_notifier(dev, port_num); 6013 } 6014 6015 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 6016 { 6017 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6018 6019 mlx5_remove_netdev_notifier(dev, port_num); 6020 } 6021 6022 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 6023 { 6024 struct mlx5_core_dev *mdev = dev->mdev; 6025 enum rdma_link_layer ll; 6026 int port_type_cap; 6027 int err = 0; 6028 6029 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6030 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6031 6032 if (ll == IB_LINK_LAYER_ETHERNET) 6033 err = mlx5_ib_stage_common_roce_init(dev); 6034 6035 return err; 6036 } 6037 6038 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 6039 { 6040 mlx5_ib_stage_common_roce_cleanup(dev); 6041 } 6042 6043 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 6044 { 6045 struct mlx5_core_dev *mdev = dev->mdev; 6046 enum rdma_link_layer ll; 6047 int port_type_cap; 6048 int err; 6049 6050 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6051 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6052 6053 if (ll == IB_LINK_LAYER_ETHERNET) { 6054 err = mlx5_ib_stage_common_roce_init(dev); 6055 if (err) 6056 return err; 6057 6058 err = mlx5_enable_eth(dev); 6059 if (err) 6060 goto cleanup; 6061 } 6062 6063 return 0; 6064 cleanup: 6065 mlx5_ib_stage_common_roce_cleanup(dev); 6066 6067 return err; 6068 } 6069 6070 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6071 { 6072 struct mlx5_core_dev *mdev = dev->mdev; 6073 enum rdma_link_layer ll; 6074 int port_type_cap; 6075 6076 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6077 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6078 6079 if (ll == IB_LINK_LAYER_ETHERNET) { 6080 mlx5_disable_eth(dev); 6081 mlx5_ib_stage_common_roce_cleanup(dev); 6082 } 6083 } 6084 6085 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6086 { 6087 return create_dev_resources(&dev->devr); 6088 } 6089 6090 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6091 { 6092 destroy_dev_resources(&dev->devr); 6093 } 6094 6095 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6096 { 6097 mlx5_ib_internal_fill_odp_caps(dev); 6098 6099 return mlx5_ib_odp_init_one(dev); 6100 } 6101 6102 void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 6103 { 6104 mlx5_ib_odp_cleanup_one(dev); 6105 } 6106 6107 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6108 { 6109 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6110 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 6111 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 6112 6113 return mlx5_ib_alloc_counters(dev); 6114 } 6115 6116 return 0; 6117 } 6118 6119 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6120 { 6121 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6122 mlx5_ib_dealloc_counters(dev); 6123 } 6124 6125 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6126 { 6127 return mlx5_ib_init_cong_debugfs(dev, 6128 mlx5_core_native_port_num(dev->mdev) - 1); 6129 } 6130 6131 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6132 { 6133 mlx5_ib_cleanup_cong_debugfs(dev, 6134 mlx5_core_native_port_num(dev->mdev) - 1); 6135 } 6136 6137 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6138 { 6139 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6140 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6141 } 6142 6143 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6144 { 6145 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6146 } 6147 6148 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6149 { 6150 int err; 6151 6152 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6153 if (err) 6154 return err; 6155 6156 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6157 if (err) 6158 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6159 6160 return err; 6161 } 6162 6163 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6164 { 6165 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6166 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6167 } 6168 6169 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 6170 { 6171 return populate_specs_root(dev); 6172 } 6173 6174 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6175 { 6176 const char *name; 6177 6178 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 6179 if (!mlx5_lag_is_roce(dev->mdev)) 6180 name = "mlx5_%d"; 6181 else 6182 name = "mlx5_bond_%d"; 6183 return ib_register_device(&dev->ib_dev, name, NULL); 6184 } 6185 6186 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6187 { 6188 destroy_umrc_res(dev); 6189 } 6190 6191 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6192 { 6193 ib_unregister_device(&dev->ib_dev); 6194 } 6195 6196 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6197 { 6198 return create_umr_res(dev); 6199 } 6200 6201 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6202 { 6203 init_delay_drop(dev); 6204 6205 return 0; 6206 } 6207 6208 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6209 { 6210 cancel_delay_drop(dev); 6211 } 6212 6213 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 6214 { 6215 dev->mdev_events.notifier_call = mlx5_ib_event; 6216 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 6217 return 0; 6218 } 6219 6220 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 6221 { 6222 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 6223 } 6224 6225 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev) 6226 { 6227 int uid; 6228 6229 uid = mlx5_ib_devx_create(dev); 6230 if (uid > 0) 6231 dev->devx_whitelist_uid = uid; 6232 6233 return 0; 6234 } 6235 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev) 6236 { 6237 if (dev->devx_whitelist_uid) 6238 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 6239 } 6240 6241 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6242 const struct mlx5_ib_profile *profile, 6243 int stage) 6244 { 6245 /* Number of stages to cleanup */ 6246 while (stage) { 6247 stage--; 6248 if (profile->stage[stage].cleanup) 6249 profile->stage[stage].cleanup(dev); 6250 } 6251 } 6252 6253 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6254 const struct mlx5_ib_profile *profile) 6255 { 6256 int err; 6257 int i; 6258 6259 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6260 if (profile->stage[i].init) { 6261 err = profile->stage[i].init(dev); 6262 if (err) 6263 goto err_out; 6264 } 6265 } 6266 6267 dev->profile = profile; 6268 dev->ib_active = true; 6269 6270 return dev; 6271 6272 err_out: 6273 __mlx5_ib_remove(dev, profile, i); 6274 6275 return NULL; 6276 } 6277 6278 static const struct mlx5_ib_profile pf_profile = { 6279 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6280 mlx5_ib_stage_init_init, 6281 mlx5_ib_stage_init_cleanup), 6282 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6283 mlx5_ib_stage_flow_db_init, 6284 mlx5_ib_stage_flow_db_cleanup), 6285 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6286 mlx5_ib_stage_caps_init, 6287 NULL), 6288 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6289 mlx5_ib_stage_non_default_cb, 6290 NULL), 6291 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6292 mlx5_ib_stage_roce_init, 6293 mlx5_ib_stage_roce_cleanup), 6294 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6295 mlx5_init_srq_table, 6296 mlx5_cleanup_srq_table), 6297 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6298 mlx5_ib_stage_dev_res_init, 6299 mlx5_ib_stage_dev_res_cleanup), 6300 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6301 mlx5_ib_stage_dev_notifier_init, 6302 mlx5_ib_stage_dev_notifier_cleanup), 6303 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6304 mlx5_ib_stage_odp_init, 6305 mlx5_ib_stage_odp_cleanup), 6306 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6307 mlx5_ib_stage_counters_init, 6308 mlx5_ib_stage_counters_cleanup), 6309 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6310 mlx5_ib_stage_cong_debugfs_init, 6311 mlx5_ib_stage_cong_debugfs_cleanup), 6312 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6313 mlx5_ib_stage_uar_init, 6314 mlx5_ib_stage_uar_cleanup), 6315 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6316 mlx5_ib_stage_bfrag_init, 6317 mlx5_ib_stage_bfrag_cleanup), 6318 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6319 NULL, 6320 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6321 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6322 mlx5_ib_stage_populate_specs, 6323 NULL), 6324 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 6325 mlx5_ib_stage_devx_init, 6326 mlx5_ib_stage_devx_cleanup), 6327 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6328 mlx5_ib_stage_ib_reg_init, 6329 mlx5_ib_stage_ib_reg_cleanup), 6330 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6331 mlx5_ib_stage_post_ib_reg_umr_init, 6332 NULL), 6333 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6334 mlx5_ib_stage_delay_drop_init, 6335 mlx5_ib_stage_delay_drop_cleanup), 6336 }; 6337 6338 static const struct mlx5_ib_profile nic_rep_profile = { 6339 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6340 mlx5_ib_stage_init_init, 6341 mlx5_ib_stage_init_cleanup), 6342 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6343 mlx5_ib_stage_flow_db_init, 6344 mlx5_ib_stage_flow_db_cleanup), 6345 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6346 mlx5_ib_stage_caps_init, 6347 NULL), 6348 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6349 mlx5_ib_stage_rep_non_default_cb, 6350 NULL), 6351 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6352 mlx5_ib_stage_rep_roce_init, 6353 mlx5_ib_stage_rep_roce_cleanup), 6354 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 6355 mlx5_init_srq_table, 6356 mlx5_cleanup_srq_table), 6357 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6358 mlx5_ib_stage_dev_res_init, 6359 mlx5_ib_stage_dev_res_cleanup), 6360 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 6361 mlx5_ib_stage_dev_notifier_init, 6362 mlx5_ib_stage_dev_notifier_cleanup), 6363 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6364 mlx5_ib_stage_counters_init, 6365 mlx5_ib_stage_counters_cleanup), 6366 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6367 mlx5_ib_stage_uar_init, 6368 mlx5_ib_stage_uar_cleanup), 6369 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6370 mlx5_ib_stage_bfrag_init, 6371 mlx5_ib_stage_bfrag_cleanup), 6372 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6373 NULL, 6374 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6375 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6376 mlx5_ib_stage_populate_specs, 6377 NULL), 6378 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6379 mlx5_ib_stage_ib_reg_init, 6380 mlx5_ib_stage_ib_reg_cleanup), 6381 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6382 mlx5_ib_stage_post_ib_reg_umr_init, 6383 NULL), 6384 }; 6385 6386 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6387 { 6388 struct mlx5_ib_multiport_info *mpi; 6389 struct mlx5_ib_dev *dev; 6390 bool bound = false; 6391 int err; 6392 6393 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6394 if (!mpi) 6395 return NULL; 6396 6397 mpi->mdev = mdev; 6398 6399 err = mlx5_query_nic_vport_system_image_guid(mdev, 6400 &mpi->sys_image_guid); 6401 if (err) { 6402 kfree(mpi); 6403 return NULL; 6404 } 6405 6406 mutex_lock(&mlx5_ib_multiport_mutex); 6407 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6408 if (dev->sys_image_guid == mpi->sys_image_guid) 6409 bound = mlx5_ib_bind_slave_port(dev, mpi); 6410 6411 if (bound) { 6412 rdma_roce_rescan_device(&dev->ib_dev); 6413 break; 6414 } 6415 } 6416 6417 if (!bound) { 6418 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6419 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6420 } 6421 mutex_unlock(&mlx5_ib_multiport_mutex); 6422 6423 return mpi; 6424 } 6425 6426 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6427 { 6428 enum rdma_link_layer ll; 6429 struct mlx5_ib_dev *dev; 6430 int port_type_cap; 6431 6432 printk_once(KERN_INFO "%s", mlx5_version); 6433 6434 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6435 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6436 6437 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6438 return mlx5_ib_add_slave_port(mdev); 6439 6440 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 6441 if (!dev) 6442 return NULL; 6443 6444 dev->mdev = mdev; 6445 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6446 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6447 6448 if (MLX5_ESWITCH_MANAGER(mdev) && 6449 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6450 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 6451 dev->profile = &nic_rep_profile; 6452 mlx5_ib_register_vport_reps(dev); 6453 return dev; 6454 } 6455 6456 return __mlx5_ib_add(dev, &pf_profile); 6457 } 6458 6459 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6460 { 6461 struct mlx5_ib_multiport_info *mpi; 6462 struct mlx5_ib_dev *dev; 6463 6464 if (mlx5_core_is_mp_slave(mdev)) { 6465 mpi = context; 6466 mutex_lock(&mlx5_ib_multiport_mutex); 6467 if (mpi->ibdev) 6468 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6469 list_del(&mpi->list); 6470 mutex_unlock(&mlx5_ib_multiport_mutex); 6471 return; 6472 } 6473 6474 dev = context; 6475 if (dev->profile == &nic_rep_profile) 6476 mlx5_ib_unregister_vport_reps(dev); 6477 else 6478 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6479 6480 ib_dealloc_device((struct ib_device *)dev); 6481 } 6482 6483 static struct mlx5_interface mlx5_ib_interface = { 6484 .add = mlx5_ib_add, 6485 .remove = mlx5_ib_remove, 6486 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6487 }; 6488 6489 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6490 { 6491 mutex_lock(&xlt_emergency_page_mutex); 6492 return xlt_emergency_page; 6493 } 6494 6495 void mlx5_ib_put_xlt_emergency_page(void) 6496 { 6497 mutex_unlock(&xlt_emergency_page_mutex); 6498 } 6499 6500 static int __init mlx5_ib_init(void) 6501 { 6502 int err; 6503 6504 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6505 if (!xlt_emergency_page) 6506 return -ENOMEM; 6507 6508 mutex_init(&xlt_emergency_page_mutex); 6509 6510 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6511 if (!mlx5_ib_event_wq) { 6512 free_page(xlt_emergency_page); 6513 return -ENOMEM; 6514 } 6515 6516 mlx5_ib_odp_init(); 6517 6518 err = mlx5_register_interface(&mlx5_ib_interface); 6519 6520 return err; 6521 } 6522 6523 static void __exit mlx5_ib_cleanup(void) 6524 { 6525 mlx5_unregister_interface(&mlx5_ib_interface); 6526 destroy_workqueue(mlx5_ib_event_wq); 6527 mutex_destroy(&xlt_emergency_page_mutex); 6528 free_page(xlt_emergency_page); 6529 } 6530 6531 module_init(mlx5_ib_init); 6532 module_exit(mlx5_ib_cleanup); 6533