1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. 4 */ 5 6 #include <rdma/ib_user_verbs.h> 7 #include <rdma/ib_verbs.h> 8 #include <rdma/uverbs_types.h> 9 #include <rdma/uverbs_ioctl.h> 10 #include <rdma/mlx5_user_ioctl_cmds.h> 11 #include <rdma/mlx5_user_ioctl_verbs.h> 12 #include <rdma/ib_umem.h> 13 #include <rdma/uverbs_std_types.h> 14 #include <linux/mlx5/driver.h> 15 #include <linux/mlx5/fs.h> 16 #include "mlx5_ib.h" 17 #include "devx.h" 18 #include "qp.h" 19 #include <linux/xarray.h> 20 21 #define UVERBS_MODULE_NAME mlx5_ib 22 #include <rdma/uverbs_named_ioctl.h> 23 24 static void dispatch_event_fd(struct list_head *fd_list, const void *data); 25 26 enum devx_obj_flags { 27 DEVX_OBJ_FLAGS_INDIRECT_MKEY = 1 << 0, 28 DEVX_OBJ_FLAGS_DCT = 1 << 1, 29 DEVX_OBJ_FLAGS_CQ = 1 << 2, 30 }; 31 32 struct devx_async_data { 33 struct mlx5_ib_dev *mdev; 34 struct list_head list; 35 struct devx_async_cmd_event_file *ev_file; 36 struct mlx5_async_work cb_work; 37 u16 cmd_out_len; 38 /* must be last field in this structure */ 39 struct mlx5_ib_uapi_devx_async_cmd_hdr hdr; 40 }; 41 42 struct devx_async_event_data { 43 struct list_head list; /* headed in ev_file->event_list */ 44 struct mlx5_ib_uapi_devx_async_event_hdr hdr; 45 }; 46 47 /* first level XA value data structure */ 48 struct devx_event { 49 struct xarray object_ids; /* second XA level, Key = object id */ 50 struct list_head unaffiliated_list; 51 }; 52 53 /* second level XA value data structure */ 54 struct devx_obj_event { 55 struct rcu_head rcu; 56 struct list_head obj_sub_list; 57 }; 58 59 struct devx_event_subscription { 60 struct list_head file_list; /* headed in ev_file-> 61 * subscribed_events_list 62 */ 63 struct list_head xa_list; /* headed in devx_event->unaffiliated_list or 64 * devx_obj_event->obj_sub_list 65 */ 66 struct list_head obj_list; /* headed in devx_object */ 67 struct list_head event_list; /* headed in ev_file->event_list or in 68 * temp list via subscription 69 */ 70 71 u8 is_cleaned:1; 72 u32 xa_key_level1; 73 u32 xa_key_level2; 74 struct rcu_head rcu; 75 u64 cookie; 76 struct devx_async_event_file *ev_file; 77 struct eventfd_ctx *eventfd; 78 }; 79 80 struct devx_async_event_file { 81 struct ib_uobject uobj; 82 /* Head of events that are subscribed to this FD */ 83 struct list_head subscribed_events_list; 84 spinlock_t lock; 85 wait_queue_head_t poll_wait; 86 struct list_head event_list; 87 struct mlx5_ib_dev *dev; 88 u8 omit_data:1; 89 u8 is_overflow_err:1; 90 u8 is_destroyed:1; 91 }; 92 93 struct devx_umem { 94 struct mlx5_core_dev *mdev; 95 struct ib_umem *umem; 96 u32 dinlen; 97 u32 dinbox[MLX5_ST_SZ_DW(destroy_umem_in)]; 98 }; 99 100 struct devx_umem_reg_cmd { 101 void *in; 102 u32 inlen; 103 u32 out[MLX5_ST_SZ_DW(create_umem_out)]; 104 }; 105 106 static struct mlx5_ib_ucontext * 107 devx_ufile2uctx(const struct uverbs_attr_bundle *attrs) 108 { 109 return to_mucontext(ib_uverbs_get_ucontext(attrs)); 110 } 111 112 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user) 113 { 114 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {}; 115 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; 116 void *uctx; 117 int err; 118 u16 uid; 119 u32 cap = 0; 120 121 /* 0 means not supported */ 122 if (!MLX5_CAP_GEN(dev->mdev, log_max_uctx)) 123 return -EINVAL; 124 125 uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx); 126 if (is_user && capable(CAP_NET_RAW) && 127 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RAW_TX)) 128 cap |= MLX5_UCTX_CAP_RAW_TX; 129 if (is_user && capable(CAP_SYS_RAWIO) && 130 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 131 MLX5_UCTX_CAP_INTERNAL_DEV_RES)) 132 cap |= MLX5_UCTX_CAP_INTERNAL_DEV_RES; 133 134 MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX); 135 MLX5_SET(uctx, uctx, cap, cap); 136 137 err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 138 if (err) 139 return err; 140 141 uid = MLX5_GET(create_uctx_out, out, uid); 142 return uid; 143 } 144 145 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) 146 { 147 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; 148 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {}; 149 150 MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX); 151 MLX5_SET(destroy_uctx_in, in, uid, uid); 152 153 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 154 } 155 156 static bool is_legacy_unaffiliated_event_num(u16 event_num) 157 { 158 switch (event_num) { 159 case MLX5_EVENT_TYPE_PORT_CHANGE: 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 static bool is_legacy_obj_event_num(u16 event_num) 167 { 168 switch (event_num) { 169 case MLX5_EVENT_TYPE_PATH_MIG: 170 case MLX5_EVENT_TYPE_COMM_EST: 171 case MLX5_EVENT_TYPE_SQ_DRAINED: 172 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 173 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 174 case MLX5_EVENT_TYPE_CQ_ERROR: 175 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 176 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 177 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 178 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 179 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 180 case MLX5_EVENT_TYPE_DCT_DRAINED: 181 case MLX5_EVENT_TYPE_COMP: 182 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 183 case MLX5_EVENT_TYPE_XRQ_ERROR: 184 return true; 185 default: 186 return false; 187 } 188 } 189 190 static u16 get_legacy_obj_type(u16 opcode) 191 { 192 switch (opcode) { 193 case MLX5_CMD_OP_CREATE_RQ: 194 return MLX5_EVENT_QUEUE_TYPE_RQ; 195 case MLX5_CMD_OP_CREATE_QP: 196 return MLX5_EVENT_QUEUE_TYPE_QP; 197 case MLX5_CMD_OP_CREATE_SQ: 198 return MLX5_EVENT_QUEUE_TYPE_SQ; 199 case MLX5_CMD_OP_CREATE_DCT: 200 return MLX5_EVENT_QUEUE_TYPE_DCT; 201 default: 202 return 0; 203 } 204 } 205 206 static u16 get_dec_obj_type(struct devx_obj *obj, u16 event_num) 207 { 208 u16 opcode; 209 210 opcode = (obj->obj_id >> 32) & 0xffff; 211 212 if (is_legacy_obj_event_num(event_num)) 213 return get_legacy_obj_type(opcode); 214 215 switch (opcode) { 216 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 217 return (obj->obj_id >> 48); 218 case MLX5_CMD_OP_CREATE_RQ: 219 return MLX5_OBJ_TYPE_RQ; 220 case MLX5_CMD_OP_CREATE_QP: 221 return MLX5_OBJ_TYPE_QP; 222 case MLX5_CMD_OP_CREATE_SQ: 223 return MLX5_OBJ_TYPE_SQ; 224 case MLX5_CMD_OP_CREATE_DCT: 225 return MLX5_OBJ_TYPE_DCT; 226 case MLX5_CMD_OP_CREATE_TIR: 227 return MLX5_OBJ_TYPE_TIR; 228 case MLX5_CMD_OP_CREATE_TIS: 229 return MLX5_OBJ_TYPE_TIS; 230 case MLX5_CMD_OP_CREATE_PSV: 231 return MLX5_OBJ_TYPE_PSV; 232 case MLX5_OBJ_TYPE_MKEY: 233 return MLX5_OBJ_TYPE_MKEY; 234 case MLX5_CMD_OP_CREATE_RMP: 235 return MLX5_OBJ_TYPE_RMP; 236 case MLX5_CMD_OP_CREATE_XRC_SRQ: 237 return MLX5_OBJ_TYPE_XRC_SRQ; 238 case MLX5_CMD_OP_CREATE_XRQ: 239 return MLX5_OBJ_TYPE_XRQ; 240 case MLX5_CMD_OP_CREATE_RQT: 241 return MLX5_OBJ_TYPE_RQT; 242 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 243 return MLX5_OBJ_TYPE_FLOW_COUNTER; 244 case MLX5_CMD_OP_CREATE_CQ: 245 return MLX5_OBJ_TYPE_CQ; 246 default: 247 return 0; 248 } 249 } 250 251 static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe) 252 { 253 switch (event_type) { 254 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 255 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 256 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 257 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 258 case MLX5_EVENT_TYPE_PATH_MIG: 259 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 260 case MLX5_EVENT_TYPE_COMM_EST: 261 case MLX5_EVENT_TYPE_SQ_DRAINED: 262 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 263 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 264 return eqe->data.qp_srq.type; 265 case MLX5_EVENT_TYPE_CQ_ERROR: 266 case MLX5_EVENT_TYPE_XRQ_ERROR: 267 return 0; 268 case MLX5_EVENT_TYPE_DCT_DRAINED: 269 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 270 return MLX5_EVENT_QUEUE_TYPE_DCT; 271 default: 272 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type); 273 } 274 } 275 276 static u32 get_dec_obj_id(u64 obj_id) 277 { 278 return (obj_id & 0xffffffff); 279 } 280 281 /* 282 * As the obj_id in the firmware is not globally unique the object type 283 * must be considered upon checking for a valid object id. 284 * For that the opcode of the creator command is encoded as part of the obj_id. 285 */ 286 static u64 get_enc_obj_id(u32 opcode, u32 obj_id) 287 { 288 return ((u64)opcode << 32) | obj_id; 289 } 290 291 static u32 devx_get_created_obj_id(const void *in, const void *out, u16 opcode) 292 { 293 switch (opcode) { 294 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 295 return MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 296 case MLX5_CMD_OP_CREATE_UMEM: 297 return MLX5_GET(create_umem_out, out, umem_id); 298 case MLX5_CMD_OP_CREATE_MKEY: 299 return MLX5_GET(create_mkey_out, out, mkey_index); 300 case MLX5_CMD_OP_CREATE_CQ: 301 return MLX5_GET(create_cq_out, out, cqn); 302 case MLX5_CMD_OP_ALLOC_PD: 303 return MLX5_GET(alloc_pd_out, out, pd); 304 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 305 return MLX5_GET(alloc_transport_domain_out, out, 306 transport_domain); 307 case MLX5_CMD_OP_CREATE_RMP: 308 return MLX5_GET(create_rmp_out, out, rmpn); 309 case MLX5_CMD_OP_CREATE_SQ: 310 return MLX5_GET(create_sq_out, out, sqn); 311 case MLX5_CMD_OP_CREATE_RQ: 312 return MLX5_GET(create_rq_out, out, rqn); 313 case MLX5_CMD_OP_CREATE_RQT: 314 return MLX5_GET(create_rqt_out, out, rqtn); 315 case MLX5_CMD_OP_CREATE_TIR: 316 return MLX5_GET(create_tir_out, out, tirn); 317 case MLX5_CMD_OP_CREATE_TIS: 318 return MLX5_GET(create_tis_out, out, tisn); 319 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 320 return MLX5_GET(alloc_q_counter_out, out, counter_set_id); 321 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 322 return MLX5_GET(create_flow_table_out, out, table_id); 323 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 324 return MLX5_GET(create_flow_group_out, out, group_id); 325 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 326 return MLX5_GET(set_fte_in, in, flow_index); 327 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 328 return MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 329 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 330 return MLX5_GET(alloc_packet_reformat_context_out, out, 331 packet_reformat_id); 332 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 333 return MLX5_GET(alloc_modify_header_context_out, out, 334 modify_header_id); 335 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 336 return MLX5_GET(create_scheduling_element_out, out, 337 scheduling_element_id); 338 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 339 return MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port); 340 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 341 return MLX5_GET(set_l2_table_entry_in, in, table_index); 342 case MLX5_CMD_OP_CREATE_QP: 343 return MLX5_GET(create_qp_out, out, qpn); 344 case MLX5_CMD_OP_CREATE_SRQ: 345 return MLX5_GET(create_srq_out, out, srqn); 346 case MLX5_CMD_OP_CREATE_XRC_SRQ: 347 return MLX5_GET(create_xrc_srq_out, out, xrc_srqn); 348 case MLX5_CMD_OP_CREATE_DCT: 349 return MLX5_GET(create_dct_out, out, dctn); 350 case MLX5_CMD_OP_CREATE_XRQ: 351 return MLX5_GET(create_xrq_out, out, xrqn); 352 case MLX5_CMD_OP_ATTACH_TO_MCG: 353 return MLX5_GET(attach_to_mcg_in, in, qpn); 354 case MLX5_CMD_OP_ALLOC_XRCD: 355 return MLX5_GET(alloc_xrcd_out, out, xrcd); 356 case MLX5_CMD_OP_CREATE_PSV: 357 return MLX5_GET(create_psv_out, out, psv0_index); 358 default: 359 /* The entry must match to one of the devx_is_obj_create_cmd */ 360 WARN_ON(true); 361 return 0; 362 } 363 } 364 365 static u64 devx_get_obj_id(const void *in) 366 { 367 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 368 u64 obj_id; 369 370 switch (opcode) { 371 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT: 372 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT: 373 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_GENERAL_OBJECT | 374 MLX5_GET(general_obj_in_cmd_hdr, in, 375 obj_type) << 16, 376 MLX5_GET(general_obj_in_cmd_hdr, in, 377 obj_id)); 378 break; 379 case MLX5_CMD_OP_QUERY_MKEY: 380 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_MKEY, 381 MLX5_GET(query_mkey_in, in, 382 mkey_index)); 383 break; 384 case MLX5_CMD_OP_QUERY_CQ: 385 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 386 MLX5_GET(query_cq_in, in, cqn)); 387 break; 388 case MLX5_CMD_OP_MODIFY_CQ: 389 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 390 MLX5_GET(modify_cq_in, in, cqn)); 391 break; 392 case MLX5_CMD_OP_QUERY_SQ: 393 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 394 MLX5_GET(query_sq_in, in, sqn)); 395 break; 396 case MLX5_CMD_OP_MODIFY_SQ: 397 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 398 MLX5_GET(modify_sq_in, in, sqn)); 399 break; 400 case MLX5_CMD_OP_QUERY_RQ: 401 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 402 MLX5_GET(query_rq_in, in, rqn)); 403 break; 404 case MLX5_CMD_OP_MODIFY_RQ: 405 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 406 MLX5_GET(modify_rq_in, in, rqn)); 407 break; 408 case MLX5_CMD_OP_QUERY_RMP: 409 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 410 MLX5_GET(query_rmp_in, in, rmpn)); 411 break; 412 case MLX5_CMD_OP_MODIFY_RMP: 413 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 414 MLX5_GET(modify_rmp_in, in, rmpn)); 415 break; 416 case MLX5_CMD_OP_QUERY_RQT: 417 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 418 MLX5_GET(query_rqt_in, in, rqtn)); 419 break; 420 case MLX5_CMD_OP_MODIFY_RQT: 421 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 422 MLX5_GET(modify_rqt_in, in, rqtn)); 423 break; 424 case MLX5_CMD_OP_QUERY_TIR: 425 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 426 MLX5_GET(query_tir_in, in, tirn)); 427 break; 428 case MLX5_CMD_OP_MODIFY_TIR: 429 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 430 MLX5_GET(modify_tir_in, in, tirn)); 431 break; 432 case MLX5_CMD_OP_QUERY_TIS: 433 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 434 MLX5_GET(query_tis_in, in, tisn)); 435 break; 436 case MLX5_CMD_OP_MODIFY_TIS: 437 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 438 MLX5_GET(modify_tis_in, in, tisn)); 439 break; 440 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 441 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 442 MLX5_GET(query_flow_table_in, in, 443 table_id)); 444 break; 445 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 446 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 447 MLX5_GET(modify_flow_table_in, in, 448 table_id)); 449 break; 450 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 451 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_GROUP, 452 MLX5_GET(query_flow_group_in, in, 453 group_id)); 454 break; 455 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 456 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 457 MLX5_GET(query_fte_in, in, 458 flow_index)); 459 break; 460 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 461 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 462 MLX5_GET(set_fte_in, in, flow_index)); 463 break; 464 case MLX5_CMD_OP_QUERY_Q_COUNTER: 465 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_Q_COUNTER, 466 MLX5_GET(query_q_counter_in, in, 467 counter_set_id)); 468 break; 469 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 470 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_FLOW_COUNTER, 471 MLX5_GET(query_flow_counter_in, in, 472 flow_counter_id)); 473 break; 474 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 475 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT, 476 MLX5_GET(query_modify_header_context_in, 477 in, modify_header_id)); 478 break; 479 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 480 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 481 MLX5_GET(query_scheduling_element_in, 482 in, scheduling_element_id)); 483 break; 484 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 485 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 486 MLX5_GET(modify_scheduling_element_in, 487 in, scheduling_element_id)); 488 break; 489 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 490 obj_id = get_enc_obj_id(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT, 491 MLX5_GET(add_vxlan_udp_dport_in, in, 492 vxlan_udp_port)); 493 break; 494 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 495 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 496 MLX5_GET(query_l2_table_entry_in, in, 497 table_index)); 498 break; 499 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 500 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 501 MLX5_GET(set_l2_table_entry_in, in, 502 table_index)); 503 break; 504 case MLX5_CMD_OP_QUERY_QP: 505 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 506 MLX5_GET(query_qp_in, in, qpn)); 507 break; 508 case MLX5_CMD_OP_RST2INIT_QP: 509 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 510 MLX5_GET(rst2init_qp_in, in, qpn)); 511 break; 512 case MLX5_CMD_OP_INIT2INIT_QP: 513 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 514 MLX5_GET(init2init_qp_in, in, qpn)); 515 break; 516 case MLX5_CMD_OP_INIT2RTR_QP: 517 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 518 MLX5_GET(init2rtr_qp_in, in, qpn)); 519 break; 520 case MLX5_CMD_OP_RTR2RTS_QP: 521 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 522 MLX5_GET(rtr2rts_qp_in, in, qpn)); 523 break; 524 case MLX5_CMD_OP_RTS2RTS_QP: 525 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 526 MLX5_GET(rts2rts_qp_in, in, qpn)); 527 break; 528 case MLX5_CMD_OP_SQERR2RTS_QP: 529 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 530 MLX5_GET(sqerr2rts_qp_in, in, qpn)); 531 break; 532 case MLX5_CMD_OP_2ERR_QP: 533 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 534 MLX5_GET(qp_2err_in, in, qpn)); 535 break; 536 case MLX5_CMD_OP_2RST_QP: 537 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 538 MLX5_GET(qp_2rst_in, in, qpn)); 539 break; 540 case MLX5_CMD_OP_QUERY_DCT: 541 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 542 MLX5_GET(query_dct_in, in, dctn)); 543 break; 544 case MLX5_CMD_OP_QUERY_XRQ: 545 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 546 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 547 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 548 MLX5_GET(query_xrq_in, in, xrqn)); 549 break; 550 case MLX5_CMD_OP_QUERY_XRC_SRQ: 551 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 552 MLX5_GET(query_xrc_srq_in, in, 553 xrc_srqn)); 554 break; 555 case MLX5_CMD_OP_ARM_XRC_SRQ: 556 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 557 MLX5_GET(arm_xrc_srq_in, in, xrc_srqn)); 558 break; 559 case MLX5_CMD_OP_QUERY_SRQ: 560 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SRQ, 561 MLX5_GET(query_srq_in, in, srqn)); 562 break; 563 case MLX5_CMD_OP_ARM_RQ: 564 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 565 MLX5_GET(arm_rq_in, in, srq_number)); 566 break; 567 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 568 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 569 MLX5_GET(drain_dct_in, in, dctn)); 570 break; 571 case MLX5_CMD_OP_ARM_XRQ: 572 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 573 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 574 case MLX5_CMD_OP_MODIFY_XRQ: 575 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 576 MLX5_GET(arm_xrq_in, in, xrqn)); 577 break; 578 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 579 obj_id = get_enc_obj_id 580 (MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT, 581 MLX5_GET(query_packet_reformat_context_in, 582 in, packet_reformat_id)); 583 break; 584 default: 585 obj_id = 0; 586 } 587 588 return obj_id; 589 } 590 591 static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs, 592 struct ib_uobject *uobj, const void *in) 593 { 594 struct mlx5_ib_dev *dev = mlx5_udata_to_mdev(&attrs->driver_udata); 595 u64 obj_id = devx_get_obj_id(in); 596 597 if (!obj_id) 598 return false; 599 600 switch (uobj_get_object_id(uobj)) { 601 case UVERBS_OBJECT_CQ: 602 return get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 603 to_mcq(uobj->object)->mcq.cqn) == 604 obj_id; 605 606 case UVERBS_OBJECT_SRQ: 607 { 608 struct mlx5_core_srq *srq = &(to_msrq(uobj->object)->msrq); 609 u16 opcode; 610 611 switch (srq->common.res) { 612 case MLX5_RES_XSRQ: 613 opcode = MLX5_CMD_OP_CREATE_XRC_SRQ; 614 break; 615 case MLX5_RES_XRQ: 616 opcode = MLX5_CMD_OP_CREATE_XRQ; 617 break; 618 default: 619 if (!dev->mdev->issi) 620 opcode = MLX5_CMD_OP_CREATE_SRQ; 621 else 622 opcode = MLX5_CMD_OP_CREATE_RMP; 623 } 624 625 return get_enc_obj_id(opcode, 626 to_msrq(uobj->object)->msrq.srqn) == 627 obj_id; 628 } 629 630 case UVERBS_OBJECT_QP: 631 { 632 struct mlx5_ib_qp *qp = to_mqp(uobj->object); 633 634 if (qp->type == IB_QPT_RAW_PACKET || 635 (qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 636 struct mlx5_ib_raw_packet_qp *raw_packet_qp = 637 &qp->raw_packet_qp; 638 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 639 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 640 641 return (get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 642 rq->base.mqp.qpn) == obj_id || 643 get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 644 sq->base.mqp.qpn) == obj_id || 645 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 646 rq->tirn) == obj_id || 647 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 648 sq->tisn) == obj_id); 649 } 650 651 if (qp->type == MLX5_IB_QPT_DCT) 652 return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 653 qp->dct.mdct.mqp.qpn) == obj_id; 654 return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 655 qp->ibqp.qp_num) == obj_id; 656 } 657 658 case UVERBS_OBJECT_WQ: 659 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 660 to_mrwq(uobj->object)->core_qp.qpn) == 661 obj_id; 662 663 case UVERBS_OBJECT_RWQ_IND_TBL: 664 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 665 to_mrwq_ind_table(uobj->object)->rqtn) == 666 obj_id; 667 668 case MLX5_IB_OBJECT_DEVX_OBJ: 669 return ((struct devx_obj *)uobj->object)->obj_id == obj_id; 670 671 default: 672 return false; 673 } 674 } 675 676 static void devx_set_umem_valid(const void *in) 677 { 678 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 679 680 switch (opcode) { 681 case MLX5_CMD_OP_CREATE_MKEY: 682 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 683 break; 684 case MLX5_CMD_OP_CREATE_CQ: 685 { 686 void *cqc; 687 688 MLX5_SET(create_cq_in, in, cq_umem_valid, 1); 689 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 690 MLX5_SET(cqc, cqc, dbr_umem_valid, 1); 691 break; 692 } 693 case MLX5_CMD_OP_CREATE_QP: 694 { 695 void *qpc; 696 697 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 698 MLX5_SET(qpc, qpc, dbr_umem_valid, 1); 699 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 700 break; 701 } 702 703 case MLX5_CMD_OP_CREATE_RQ: 704 { 705 void *rqc, *wq; 706 707 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 708 wq = MLX5_ADDR_OF(rqc, rqc, wq); 709 MLX5_SET(wq, wq, dbr_umem_valid, 1); 710 MLX5_SET(wq, wq, wq_umem_valid, 1); 711 break; 712 } 713 714 case MLX5_CMD_OP_CREATE_SQ: 715 { 716 void *sqc, *wq; 717 718 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 719 wq = MLX5_ADDR_OF(sqc, sqc, wq); 720 MLX5_SET(wq, wq, dbr_umem_valid, 1); 721 MLX5_SET(wq, wq, wq_umem_valid, 1); 722 break; 723 } 724 725 case MLX5_CMD_OP_MODIFY_CQ: 726 MLX5_SET(modify_cq_in, in, cq_umem_valid, 1); 727 break; 728 729 case MLX5_CMD_OP_CREATE_RMP: 730 { 731 void *rmpc, *wq; 732 733 rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx); 734 wq = MLX5_ADDR_OF(rmpc, rmpc, wq); 735 MLX5_SET(wq, wq, dbr_umem_valid, 1); 736 MLX5_SET(wq, wq, wq_umem_valid, 1); 737 break; 738 } 739 740 case MLX5_CMD_OP_CREATE_XRQ: 741 { 742 void *xrqc, *wq; 743 744 xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context); 745 wq = MLX5_ADDR_OF(xrqc, xrqc, wq); 746 MLX5_SET(wq, wq, dbr_umem_valid, 1); 747 MLX5_SET(wq, wq, wq_umem_valid, 1); 748 break; 749 } 750 751 case MLX5_CMD_OP_CREATE_XRC_SRQ: 752 { 753 void *xrc_srqc; 754 755 MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1); 756 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in, 757 xrc_srq_context_entry); 758 MLX5_SET(xrc_srqc, xrc_srqc, dbr_umem_valid, 1); 759 break; 760 } 761 762 default: 763 return; 764 } 765 } 766 767 static bool devx_is_obj_create_cmd(const void *in, u16 *opcode) 768 { 769 *opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 770 771 switch (*opcode) { 772 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 773 case MLX5_CMD_OP_CREATE_MKEY: 774 case MLX5_CMD_OP_CREATE_CQ: 775 case MLX5_CMD_OP_ALLOC_PD: 776 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 777 case MLX5_CMD_OP_CREATE_RMP: 778 case MLX5_CMD_OP_CREATE_SQ: 779 case MLX5_CMD_OP_CREATE_RQ: 780 case MLX5_CMD_OP_CREATE_RQT: 781 case MLX5_CMD_OP_CREATE_TIR: 782 case MLX5_CMD_OP_CREATE_TIS: 783 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 784 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 785 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 786 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 787 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 788 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 789 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 790 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 791 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 792 case MLX5_CMD_OP_CREATE_QP: 793 case MLX5_CMD_OP_CREATE_SRQ: 794 case MLX5_CMD_OP_CREATE_XRC_SRQ: 795 case MLX5_CMD_OP_CREATE_DCT: 796 case MLX5_CMD_OP_CREATE_XRQ: 797 case MLX5_CMD_OP_ATTACH_TO_MCG: 798 case MLX5_CMD_OP_ALLOC_XRCD: 799 return true; 800 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 801 { 802 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 803 if (op_mod == 0) 804 return true; 805 return false; 806 } 807 case MLX5_CMD_OP_CREATE_PSV: 808 { 809 u8 num_psv = MLX5_GET(create_psv_in, in, num_psv); 810 811 if (num_psv == 1) 812 return true; 813 return false; 814 } 815 default: 816 return false; 817 } 818 } 819 820 static bool devx_is_obj_modify_cmd(const void *in) 821 { 822 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 823 824 switch (opcode) { 825 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT: 826 case MLX5_CMD_OP_MODIFY_CQ: 827 case MLX5_CMD_OP_MODIFY_RMP: 828 case MLX5_CMD_OP_MODIFY_SQ: 829 case MLX5_CMD_OP_MODIFY_RQ: 830 case MLX5_CMD_OP_MODIFY_RQT: 831 case MLX5_CMD_OP_MODIFY_TIR: 832 case MLX5_CMD_OP_MODIFY_TIS: 833 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 834 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 835 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 836 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 837 case MLX5_CMD_OP_RST2INIT_QP: 838 case MLX5_CMD_OP_INIT2RTR_QP: 839 case MLX5_CMD_OP_INIT2INIT_QP: 840 case MLX5_CMD_OP_RTR2RTS_QP: 841 case MLX5_CMD_OP_RTS2RTS_QP: 842 case MLX5_CMD_OP_SQERR2RTS_QP: 843 case MLX5_CMD_OP_2ERR_QP: 844 case MLX5_CMD_OP_2RST_QP: 845 case MLX5_CMD_OP_ARM_XRC_SRQ: 846 case MLX5_CMD_OP_ARM_RQ: 847 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 848 case MLX5_CMD_OP_ARM_XRQ: 849 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 850 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 851 case MLX5_CMD_OP_MODIFY_XRQ: 852 return true; 853 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 854 { 855 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 856 857 if (op_mod == 1) 858 return true; 859 return false; 860 } 861 default: 862 return false; 863 } 864 } 865 866 static bool devx_is_obj_query_cmd(const void *in) 867 { 868 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 869 870 switch (opcode) { 871 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT: 872 case MLX5_CMD_OP_QUERY_MKEY: 873 case MLX5_CMD_OP_QUERY_CQ: 874 case MLX5_CMD_OP_QUERY_RMP: 875 case MLX5_CMD_OP_QUERY_SQ: 876 case MLX5_CMD_OP_QUERY_RQ: 877 case MLX5_CMD_OP_QUERY_RQT: 878 case MLX5_CMD_OP_QUERY_TIR: 879 case MLX5_CMD_OP_QUERY_TIS: 880 case MLX5_CMD_OP_QUERY_Q_COUNTER: 881 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 882 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 883 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 884 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 885 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 886 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 887 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 888 case MLX5_CMD_OP_QUERY_QP: 889 case MLX5_CMD_OP_QUERY_SRQ: 890 case MLX5_CMD_OP_QUERY_XRC_SRQ: 891 case MLX5_CMD_OP_QUERY_DCT: 892 case MLX5_CMD_OP_QUERY_XRQ: 893 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 894 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 895 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 896 return true; 897 default: 898 return false; 899 } 900 } 901 902 static bool devx_is_whitelist_cmd(void *in) 903 { 904 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 905 906 switch (opcode) { 907 case MLX5_CMD_OP_QUERY_HCA_CAP: 908 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 909 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 910 return true; 911 default: 912 return false; 913 } 914 } 915 916 static int devx_get_uid(struct mlx5_ib_ucontext *c, void *cmd_in) 917 { 918 if (devx_is_whitelist_cmd(cmd_in)) { 919 struct mlx5_ib_dev *dev; 920 921 if (c->devx_uid) 922 return c->devx_uid; 923 924 dev = to_mdev(c->ibucontext.device); 925 if (dev->devx_whitelist_uid) 926 return dev->devx_whitelist_uid; 927 928 return -EOPNOTSUPP; 929 } 930 931 if (!c->devx_uid) 932 return -EINVAL; 933 934 return c->devx_uid; 935 } 936 937 static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev) 938 { 939 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 940 941 /* Pass all cmds for vhca_tunnel as general, tracking is done in FW */ 942 if ((MLX5_CAP_GEN_64(dev->mdev, vhca_tunnel_commands) && 943 MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) || 944 (opcode >= MLX5_CMD_OP_GENERAL_START && 945 opcode < MLX5_CMD_OP_GENERAL_END)) 946 return true; 947 948 switch (opcode) { 949 case MLX5_CMD_OP_QUERY_HCA_CAP: 950 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 951 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 952 case MLX5_CMD_OP_QUERY_VPORT_STATE: 953 case MLX5_CMD_OP_QUERY_ADAPTER: 954 case MLX5_CMD_OP_QUERY_ISSI: 955 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 956 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 957 case MLX5_CMD_OP_QUERY_VNIC_ENV: 958 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 959 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 960 case MLX5_CMD_OP_NOP: 961 case MLX5_CMD_OP_QUERY_CONG_STATUS: 962 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 963 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 964 case MLX5_CMD_OP_QUERY_LAG: 965 return true; 966 default: 967 return false; 968 } 969 } 970 971 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)( 972 struct uverbs_attr_bundle *attrs) 973 { 974 struct mlx5_ib_ucontext *c; 975 struct mlx5_ib_dev *dev; 976 int user_vector; 977 int dev_eqn; 978 int err; 979 980 if (uverbs_copy_from(&user_vector, attrs, 981 MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC)) 982 return -EFAULT; 983 984 c = devx_ufile2uctx(attrs); 985 if (IS_ERR(c)) 986 return PTR_ERR(c); 987 dev = to_mdev(c->ibucontext.device); 988 989 err = mlx5_vector2eqn(dev->mdev, user_vector, &dev_eqn); 990 if (err < 0) 991 return err; 992 993 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 994 &dev_eqn, sizeof(dev_eqn))) 995 return -EFAULT; 996 997 return 0; 998 } 999 1000 /* 1001 *Security note: 1002 * The hardware protection mechanism works like this: Each device object that 1003 * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in 1004 * the device specification manual) upon its creation. Then upon doorbell, 1005 * hardware fetches the object context for which the doorbell was rang, and 1006 * validates that the UAR through which the DB was rang matches the UAR ID 1007 * of the object. 1008 * If no match the doorbell is silently ignored by the hardware. Of course, 1009 * the user cannot ring a doorbell on a UAR that was not mapped to it. 1010 * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command 1011 * mailboxes (except tagging them with UID), we expose to the user its UAR 1012 * ID, so it can embed it in these objects in the expected specification 1013 * format. So the only thing the user can do is hurt itself by creating a 1014 * QP/SQ/CQ with a UAR ID other than his, and then in this case other users 1015 * may ring a doorbell on its objects. 1016 * The consequence of that will be that another user can schedule a QP/SQ 1017 * of the buggy user for execution (just insert it to the hardware schedule 1018 * queue or arm its CQ for event generation), no further harm is expected. 1019 */ 1020 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_UAR)( 1021 struct uverbs_attr_bundle *attrs) 1022 { 1023 struct mlx5_ib_ucontext *c; 1024 struct mlx5_ib_dev *dev; 1025 u32 user_idx; 1026 s32 dev_idx; 1027 1028 c = devx_ufile2uctx(attrs); 1029 if (IS_ERR(c)) 1030 return PTR_ERR(c); 1031 dev = to_mdev(c->ibucontext.device); 1032 1033 if (uverbs_copy_from(&user_idx, attrs, 1034 MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX)) 1035 return -EFAULT; 1036 1037 dev_idx = bfregn_to_uar_index(dev, &c->bfregi, user_idx, true); 1038 if (dev_idx < 0) 1039 return dev_idx; 1040 1041 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 1042 &dev_idx, sizeof(dev_idx))) 1043 return -EFAULT; 1044 1045 return 0; 1046 } 1047 1048 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OTHER)( 1049 struct uverbs_attr_bundle *attrs) 1050 { 1051 struct mlx5_ib_ucontext *c; 1052 struct mlx5_ib_dev *dev; 1053 void *cmd_in = uverbs_attr_get_alloced_ptr( 1054 attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN); 1055 int cmd_out_len = uverbs_attr_get_len(attrs, 1056 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT); 1057 void *cmd_out; 1058 int err; 1059 int uid; 1060 1061 c = devx_ufile2uctx(attrs); 1062 if (IS_ERR(c)) 1063 return PTR_ERR(c); 1064 dev = to_mdev(c->ibucontext.device); 1065 1066 uid = devx_get_uid(c, cmd_in); 1067 if (uid < 0) 1068 return uid; 1069 1070 /* Only white list of some general HCA commands are allowed for this method. */ 1071 if (!devx_is_general_cmd(cmd_in, dev)) 1072 return -EINVAL; 1073 1074 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1075 if (IS_ERR(cmd_out)) 1076 return PTR_ERR(cmd_out); 1077 1078 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1079 err = mlx5_cmd_exec(dev->mdev, cmd_in, 1080 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN), 1081 cmd_out, cmd_out_len); 1082 if (err) 1083 return err; 1084 1085 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, cmd_out, 1086 cmd_out_len); 1087 } 1088 1089 static void devx_obj_build_destroy_cmd(void *in, void *out, void *din, 1090 u32 *dinlen, 1091 u32 *obj_id) 1092 { 1093 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 1094 u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid); 1095 1096 *obj_id = devx_get_created_obj_id(in, out, opcode); 1097 *dinlen = MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr); 1098 MLX5_SET(general_obj_in_cmd_hdr, din, uid, uid); 1099 1100 switch (opcode) { 1101 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 1102 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJECT); 1103 MLX5_SET(general_obj_in_cmd_hdr, din, obj_id, *obj_id); 1104 MLX5_SET(general_obj_in_cmd_hdr, din, obj_type, 1105 MLX5_GET(general_obj_in_cmd_hdr, in, obj_type)); 1106 break; 1107 1108 case MLX5_CMD_OP_CREATE_UMEM: 1109 MLX5_SET(destroy_umem_in, din, opcode, 1110 MLX5_CMD_OP_DESTROY_UMEM); 1111 MLX5_SET(destroy_umem_in, din, umem_id, *obj_id); 1112 break; 1113 case MLX5_CMD_OP_CREATE_MKEY: 1114 MLX5_SET(destroy_mkey_in, din, opcode, 1115 MLX5_CMD_OP_DESTROY_MKEY); 1116 MLX5_SET(destroy_mkey_in, din, mkey_index, *obj_id); 1117 break; 1118 case MLX5_CMD_OP_CREATE_CQ: 1119 MLX5_SET(destroy_cq_in, din, opcode, MLX5_CMD_OP_DESTROY_CQ); 1120 MLX5_SET(destroy_cq_in, din, cqn, *obj_id); 1121 break; 1122 case MLX5_CMD_OP_ALLOC_PD: 1123 MLX5_SET(dealloc_pd_in, din, opcode, MLX5_CMD_OP_DEALLOC_PD); 1124 MLX5_SET(dealloc_pd_in, din, pd, *obj_id); 1125 break; 1126 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 1127 MLX5_SET(dealloc_transport_domain_in, din, opcode, 1128 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN); 1129 MLX5_SET(dealloc_transport_domain_in, din, transport_domain, 1130 *obj_id); 1131 break; 1132 case MLX5_CMD_OP_CREATE_RMP: 1133 MLX5_SET(destroy_rmp_in, din, opcode, MLX5_CMD_OP_DESTROY_RMP); 1134 MLX5_SET(destroy_rmp_in, din, rmpn, *obj_id); 1135 break; 1136 case MLX5_CMD_OP_CREATE_SQ: 1137 MLX5_SET(destroy_sq_in, din, opcode, MLX5_CMD_OP_DESTROY_SQ); 1138 MLX5_SET(destroy_sq_in, din, sqn, *obj_id); 1139 break; 1140 case MLX5_CMD_OP_CREATE_RQ: 1141 MLX5_SET(destroy_rq_in, din, opcode, MLX5_CMD_OP_DESTROY_RQ); 1142 MLX5_SET(destroy_rq_in, din, rqn, *obj_id); 1143 break; 1144 case MLX5_CMD_OP_CREATE_RQT: 1145 MLX5_SET(destroy_rqt_in, din, opcode, MLX5_CMD_OP_DESTROY_RQT); 1146 MLX5_SET(destroy_rqt_in, din, rqtn, *obj_id); 1147 break; 1148 case MLX5_CMD_OP_CREATE_TIR: 1149 MLX5_SET(destroy_tir_in, din, opcode, MLX5_CMD_OP_DESTROY_TIR); 1150 MLX5_SET(destroy_tir_in, din, tirn, *obj_id); 1151 break; 1152 case MLX5_CMD_OP_CREATE_TIS: 1153 MLX5_SET(destroy_tis_in, din, opcode, MLX5_CMD_OP_DESTROY_TIS); 1154 MLX5_SET(destroy_tis_in, din, tisn, *obj_id); 1155 break; 1156 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 1157 MLX5_SET(dealloc_q_counter_in, din, opcode, 1158 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 1159 MLX5_SET(dealloc_q_counter_in, din, counter_set_id, *obj_id); 1160 break; 1161 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 1162 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_table_in); 1163 MLX5_SET(destroy_flow_table_in, din, other_vport, 1164 MLX5_GET(create_flow_table_in, in, other_vport)); 1165 MLX5_SET(destroy_flow_table_in, din, vport_number, 1166 MLX5_GET(create_flow_table_in, in, vport_number)); 1167 MLX5_SET(destroy_flow_table_in, din, table_type, 1168 MLX5_GET(create_flow_table_in, in, table_type)); 1169 MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id); 1170 MLX5_SET(destroy_flow_table_in, din, opcode, 1171 MLX5_CMD_OP_DESTROY_FLOW_TABLE); 1172 break; 1173 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 1174 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_group_in); 1175 MLX5_SET(destroy_flow_group_in, din, other_vport, 1176 MLX5_GET(create_flow_group_in, in, other_vport)); 1177 MLX5_SET(destroy_flow_group_in, din, vport_number, 1178 MLX5_GET(create_flow_group_in, in, vport_number)); 1179 MLX5_SET(destroy_flow_group_in, din, table_type, 1180 MLX5_GET(create_flow_group_in, in, table_type)); 1181 MLX5_SET(destroy_flow_group_in, din, table_id, 1182 MLX5_GET(create_flow_group_in, in, table_id)); 1183 MLX5_SET(destroy_flow_group_in, din, group_id, *obj_id); 1184 MLX5_SET(destroy_flow_group_in, din, opcode, 1185 MLX5_CMD_OP_DESTROY_FLOW_GROUP); 1186 break; 1187 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 1188 *dinlen = MLX5_ST_SZ_BYTES(delete_fte_in); 1189 MLX5_SET(delete_fte_in, din, other_vport, 1190 MLX5_GET(set_fte_in, in, other_vport)); 1191 MLX5_SET(delete_fte_in, din, vport_number, 1192 MLX5_GET(set_fte_in, in, vport_number)); 1193 MLX5_SET(delete_fte_in, din, table_type, 1194 MLX5_GET(set_fte_in, in, table_type)); 1195 MLX5_SET(delete_fte_in, din, table_id, 1196 MLX5_GET(set_fte_in, in, table_id)); 1197 MLX5_SET(delete_fte_in, din, flow_index, *obj_id); 1198 MLX5_SET(delete_fte_in, din, opcode, 1199 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY); 1200 break; 1201 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 1202 MLX5_SET(dealloc_flow_counter_in, din, opcode, 1203 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER); 1204 MLX5_SET(dealloc_flow_counter_in, din, flow_counter_id, 1205 *obj_id); 1206 break; 1207 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 1208 MLX5_SET(dealloc_packet_reformat_context_in, din, opcode, 1209 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT); 1210 MLX5_SET(dealloc_packet_reformat_context_in, din, 1211 packet_reformat_id, *obj_id); 1212 break; 1213 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 1214 MLX5_SET(dealloc_modify_header_context_in, din, opcode, 1215 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT); 1216 MLX5_SET(dealloc_modify_header_context_in, din, 1217 modify_header_id, *obj_id); 1218 break; 1219 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 1220 *dinlen = MLX5_ST_SZ_BYTES(destroy_scheduling_element_in); 1221 MLX5_SET(destroy_scheduling_element_in, din, 1222 scheduling_hierarchy, 1223 MLX5_GET(create_scheduling_element_in, in, 1224 scheduling_hierarchy)); 1225 MLX5_SET(destroy_scheduling_element_in, din, 1226 scheduling_element_id, *obj_id); 1227 MLX5_SET(destroy_scheduling_element_in, din, opcode, 1228 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT); 1229 break; 1230 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 1231 *dinlen = MLX5_ST_SZ_BYTES(delete_vxlan_udp_dport_in); 1232 MLX5_SET(delete_vxlan_udp_dport_in, din, vxlan_udp_port, *obj_id); 1233 MLX5_SET(delete_vxlan_udp_dport_in, din, opcode, 1234 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT); 1235 break; 1236 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 1237 *dinlen = MLX5_ST_SZ_BYTES(delete_l2_table_entry_in); 1238 MLX5_SET(delete_l2_table_entry_in, din, table_index, *obj_id); 1239 MLX5_SET(delete_l2_table_entry_in, din, opcode, 1240 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); 1241 break; 1242 case MLX5_CMD_OP_CREATE_QP: 1243 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP); 1244 MLX5_SET(destroy_qp_in, din, qpn, *obj_id); 1245 break; 1246 case MLX5_CMD_OP_CREATE_SRQ: 1247 MLX5_SET(destroy_srq_in, din, opcode, MLX5_CMD_OP_DESTROY_SRQ); 1248 MLX5_SET(destroy_srq_in, din, srqn, *obj_id); 1249 break; 1250 case MLX5_CMD_OP_CREATE_XRC_SRQ: 1251 MLX5_SET(destroy_xrc_srq_in, din, opcode, 1252 MLX5_CMD_OP_DESTROY_XRC_SRQ); 1253 MLX5_SET(destroy_xrc_srq_in, din, xrc_srqn, *obj_id); 1254 break; 1255 case MLX5_CMD_OP_CREATE_DCT: 1256 MLX5_SET(destroy_dct_in, din, opcode, MLX5_CMD_OP_DESTROY_DCT); 1257 MLX5_SET(destroy_dct_in, din, dctn, *obj_id); 1258 break; 1259 case MLX5_CMD_OP_CREATE_XRQ: 1260 MLX5_SET(destroy_xrq_in, din, opcode, MLX5_CMD_OP_DESTROY_XRQ); 1261 MLX5_SET(destroy_xrq_in, din, xrqn, *obj_id); 1262 break; 1263 case MLX5_CMD_OP_ATTACH_TO_MCG: 1264 *dinlen = MLX5_ST_SZ_BYTES(detach_from_mcg_in); 1265 MLX5_SET(detach_from_mcg_in, din, qpn, 1266 MLX5_GET(attach_to_mcg_in, in, qpn)); 1267 memcpy(MLX5_ADDR_OF(detach_from_mcg_in, din, multicast_gid), 1268 MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid), 1269 MLX5_FLD_SZ_BYTES(attach_to_mcg_in, multicast_gid)); 1270 MLX5_SET(detach_from_mcg_in, din, opcode, 1271 MLX5_CMD_OP_DETACH_FROM_MCG); 1272 MLX5_SET(detach_from_mcg_in, din, qpn, *obj_id); 1273 break; 1274 case MLX5_CMD_OP_ALLOC_XRCD: 1275 MLX5_SET(dealloc_xrcd_in, din, opcode, 1276 MLX5_CMD_OP_DEALLOC_XRCD); 1277 MLX5_SET(dealloc_xrcd_in, din, xrcd, *obj_id); 1278 break; 1279 case MLX5_CMD_OP_CREATE_PSV: 1280 MLX5_SET(destroy_psv_in, din, opcode, 1281 MLX5_CMD_OP_DESTROY_PSV); 1282 MLX5_SET(destroy_psv_in, din, psvn, *obj_id); 1283 break; 1284 default: 1285 /* The entry must match to one of the devx_is_obj_create_cmd */ 1286 WARN_ON(true); 1287 break; 1288 } 1289 } 1290 1291 static int devx_handle_mkey_indirect(struct devx_obj *obj, 1292 struct mlx5_ib_dev *dev, 1293 void *in, void *out) 1294 { 1295 struct mlx5_ib_mkey *mkey = &obj->mkey; 1296 void *mkc; 1297 u8 key; 1298 1299 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1300 key = MLX5_GET(mkc, mkc, mkey_7_0); 1301 mkey->key = mlx5_idx_to_mkey( 1302 MLX5_GET(create_mkey_out, out, mkey_index)) | key; 1303 mkey->type = MLX5_MKEY_INDIRECT_DEVX; 1304 mkey->ndescs = MLX5_GET(mkc, mkc, translations_octword_size); 1305 init_waitqueue_head(&mkey->wait); 1306 1307 return mlx5r_store_odp_mkey(dev, mkey); 1308 } 1309 1310 static int devx_handle_mkey_create(struct mlx5_ib_dev *dev, 1311 struct devx_obj *obj, 1312 void *in, int in_len) 1313 { 1314 int min_len = MLX5_BYTE_OFF(create_mkey_in, memory_key_mkey_entry) + 1315 MLX5_FLD_SZ_BYTES(create_mkey_in, 1316 memory_key_mkey_entry); 1317 void *mkc; 1318 u8 access_mode; 1319 1320 if (in_len < min_len) 1321 return -EINVAL; 1322 1323 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1324 1325 access_mode = MLX5_GET(mkc, mkc, access_mode_1_0); 1326 access_mode |= MLX5_GET(mkc, mkc, access_mode_4_2) << 2; 1327 1328 if (access_mode == MLX5_MKC_ACCESS_MODE_KLMS || 1329 access_mode == MLX5_MKC_ACCESS_MODE_KSM) { 1330 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) 1331 obj->flags |= DEVX_OBJ_FLAGS_INDIRECT_MKEY; 1332 return 0; 1333 } 1334 1335 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 1336 return 0; 1337 } 1338 1339 static void devx_cleanup_subscription(struct mlx5_ib_dev *dev, 1340 struct devx_event_subscription *sub) 1341 { 1342 struct devx_event *event; 1343 struct devx_obj_event *xa_val_level2; 1344 1345 if (sub->is_cleaned) 1346 return; 1347 1348 sub->is_cleaned = 1; 1349 list_del_rcu(&sub->xa_list); 1350 1351 if (list_empty(&sub->obj_list)) 1352 return; 1353 1354 list_del_rcu(&sub->obj_list); 1355 /* check whether key level 1 for this obj_sub_list is empty */ 1356 event = xa_load(&dev->devx_event_table.event_xa, 1357 sub->xa_key_level1); 1358 WARN_ON(!event); 1359 1360 xa_val_level2 = xa_load(&event->object_ids, sub->xa_key_level2); 1361 if (list_empty(&xa_val_level2->obj_sub_list)) { 1362 xa_erase(&event->object_ids, 1363 sub->xa_key_level2); 1364 kfree_rcu(xa_val_level2, rcu); 1365 } 1366 } 1367 1368 static int devx_obj_cleanup(struct ib_uobject *uobject, 1369 enum rdma_remove_reason why, 1370 struct uverbs_attr_bundle *attrs) 1371 { 1372 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1373 struct mlx5_devx_event_table *devx_event_table; 1374 struct devx_obj *obj = uobject->object; 1375 struct devx_event_subscription *sub_entry, *tmp; 1376 struct mlx5_ib_dev *dev; 1377 int ret; 1378 1379 dev = mlx5_udata_to_mdev(&attrs->driver_udata); 1380 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY && 1381 xa_erase(&obj->ib_dev->odp_mkeys, 1382 mlx5_base_mkey(obj->mkey.key))) 1383 /* 1384 * The pagefault_single_data_segment() does commands against 1385 * the mmkey, we must wait for that to stop before freeing the 1386 * mkey, as another allocation could get the same mkey #. 1387 */ 1388 mlx5r_deref_wait_odp_mkey(&obj->mkey); 1389 1390 if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1391 ret = mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct); 1392 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1393 ret = mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1394 else 1395 ret = mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, 1396 obj->dinlen, out, sizeof(out)); 1397 if (ret) 1398 return ret; 1399 1400 devx_event_table = &dev->devx_event_table; 1401 1402 mutex_lock(&devx_event_table->event_xa_lock); 1403 list_for_each_entry_safe(sub_entry, tmp, &obj->event_sub, obj_list) 1404 devx_cleanup_subscription(dev, sub_entry); 1405 mutex_unlock(&devx_event_table->event_xa_lock); 1406 1407 kfree(obj); 1408 return ret; 1409 } 1410 1411 static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) 1412 { 1413 struct devx_obj *obj = container_of(mcq, struct devx_obj, core_cq); 1414 struct mlx5_devx_event_table *table; 1415 struct devx_event *event; 1416 struct devx_obj_event *obj_event; 1417 u32 obj_id = mcq->cqn; 1418 1419 table = &obj->ib_dev->devx_event_table; 1420 rcu_read_lock(); 1421 event = xa_load(&table->event_xa, MLX5_EVENT_TYPE_COMP); 1422 if (!event) 1423 goto out; 1424 1425 obj_event = xa_load(&event->object_ids, obj_id); 1426 if (!obj_event) 1427 goto out; 1428 1429 dispatch_event_fd(&obj_event->obj_sub_list, eqe); 1430 out: 1431 rcu_read_unlock(); 1432 } 1433 1434 static bool is_apu_cq(struct mlx5_ib_dev *dev, const void *in) 1435 { 1436 if (!MLX5_CAP_GEN(dev->mdev, apu) || 1437 !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq)) 1438 return false; 1439 1440 return true; 1441 } 1442 1443 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)( 1444 struct uverbs_attr_bundle *attrs) 1445 { 1446 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1447 int cmd_out_len = uverbs_attr_get_len(attrs, 1448 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT); 1449 int cmd_in_len = uverbs_attr_get_len(attrs, 1450 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1451 void *cmd_out; 1452 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1453 attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE); 1454 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1455 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1456 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1457 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1458 struct devx_obj *obj; 1459 u16 obj_type = 0; 1460 int err; 1461 int uid; 1462 u32 obj_id; 1463 u16 opcode; 1464 1465 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1466 return -EINVAL; 1467 1468 uid = devx_get_uid(c, cmd_in); 1469 if (uid < 0) 1470 return uid; 1471 1472 if (!devx_is_obj_create_cmd(cmd_in, &opcode)) 1473 return -EINVAL; 1474 1475 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1476 if (IS_ERR(cmd_out)) 1477 return PTR_ERR(cmd_out); 1478 1479 obj = kzalloc(sizeof(struct devx_obj), GFP_KERNEL); 1480 if (!obj) 1481 return -ENOMEM; 1482 1483 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1484 if (opcode == MLX5_CMD_OP_CREATE_MKEY) { 1485 err = devx_handle_mkey_create(dev, obj, cmd_in, cmd_in_len); 1486 if (err) 1487 goto obj_free; 1488 } else { 1489 devx_set_umem_valid(cmd_in); 1490 } 1491 1492 if (opcode == MLX5_CMD_OP_CREATE_DCT) { 1493 obj->flags |= DEVX_OBJ_FLAGS_DCT; 1494 err = mlx5_core_create_dct(dev, &obj->core_dct, cmd_in, 1495 cmd_in_len, cmd_out, cmd_out_len); 1496 } else if (opcode == MLX5_CMD_OP_CREATE_CQ && 1497 !is_apu_cq(dev, cmd_in)) { 1498 obj->flags |= DEVX_OBJ_FLAGS_CQ; 1499 obj->core_cq.comp = devx_cq_comp; 1500 err = mlx5_core_create_cq(dev->mdev, &obj->core_cq, 1501 cmd_in, cmd_in_len, cmd_out, 1502 cmd_out_len); 1503 } else { 1504 err = mlx5_cmd_exec(dev->mdev, cmd_in, 1505 cmd_in_len, 1506 cmd_out, cmd_out_len); 1507 } 1508 1509 if (err) 1510 goto obj_free; 1511 1512 if (opcode == MLX5_CMD_OP_ALLOC_FLOW_COUNTER) { 1513 u8 bulk = MLX5_GET(alloc_flow_counter_in, 1514 cmd_in, 1515 flow_counter_bulk); 1516 obj->flow_counter_bulk_size = 128UL * bulk; 1517 } 1518 1519 uobj->object = obj; 1520 INIT_LIST_HEAD(&obj->event_sub); 1521 obj->ib_dev = dev; 1522 devx_obj_build_destroy_cmd(cmd_in, cmd_out, obj->dinbox, &obj->dinlen, 1523 &obj_id); 1524 WARN_ON(obj->dinlen > MLX5_MAX_DESTROY_INBOX_SIZE_DW * sizeof(u32)); 1525 1526 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, cmd_out, cmd_out_len); 1527 if (err) 1528 goto obj_destroy; 1529 1530 if (opcode == MLX5_CMD_OP_CREATE_GENERAL_OBJECT) 1531 obj_type = MLX5_GET(general_obj_in_cmd_hdr, cmd_in, obj_type); 1532 obj->obj_id = get_enc_obj_id(opcode | obj_type << 16, obj_id); 1533 1534 if (obj->flags & DEVX_OBJ_FLAGS_INDIRECT_MKEY) { 1535 err = devx_handle_mkey_indirect(obj, dev, cmd_in, cmd_out); 1536 if (err) 1537 goto obj_destroy; 1538 } 1539 return 0; 1540 1541 obj_destroy: 1542 if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1543 mlx5_core_destroy_dct(obj->ib_dev, &obj->core_dct); 1544 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1545 mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1546 else 1547 mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, obj->dinlen, out, 1548 sizeof(out)); 1549 obj_free: 1550 kfree(obj); 1551 return err; 1552 } 1553 1554 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_MODIFY)( 1555 struct uverbs_attr_bundle *attrs) 1556 { 1557 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN); 1558 int cmd_out_len = uverbs_attr_get_len(attrs, 1559 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT); 1560 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1561 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE); 1562 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1563 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1564 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1565 void *cmd_out; 1566 int err; 1567 int uid; 1568 1569 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1570 return -EINVAL; 1571 1572 uid = devx_get_uid(c, cmd_in); 1573 if (uid < 0) 1574 return uid; 1575 1576 if (!devx_is_obj_modify_cmd(cmd_in)) 1577 return -EINVAL; 1578 1579 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1580 return -EINVAL; 1581 1582 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1583 if (IS_ERR(cmd_out)) 1584 return PTR_ERR(cmd_out); 1585 1586 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1587 devx_set_umem_valid(cmd_in); 1588 1589 err = mlx5_cmd_exec(mdev->mdev, cmd_in, 1590 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN), 1591 cmd_out, cmd_out_len); 1592 if (err) 1593 return err; 1594 1595 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 1596 cmd_out, cmd_out_len); 1597 } 1598 1599 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_QUERY)( 1600 struct uverbs_attr_bundle *attrs) 1601 { 1602 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN); 1603 int cmd_out_len = uverbs_attr_get_len(attrs, 1604 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT); 1605 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1606 MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE); 1607 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1608 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1609 void *cmd_out; 1610 int err; 1611 int uid; 1612 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1613 1614 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1615 return -EINVAL; 1616 1617 uid = devx_get_uid(c, cmd_in); 1618 if (uid < 0) 1619 return uid; 1620 1621 if (!devx_is_obj_query_cmd(cmd_in)) 1622 return -EINVAL; 1623 1624 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1625 return -EINVAL; 1626 1627 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1628 if (IS_ERR(cmd_out)) 1629 return PTR_ERR(cmd_out); 1630 1631 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1632 err = mlx5_cmd_exec(mdev->mdev, cmd_in, 1633 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN), 1634 cmd_out, cmd_out_len); 1635 if (err) 1636 return err; 1637 1638 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 1639 cmd_out, cmd_out_len); 1640 } 1641 1642 struct devx_async_event_queue { 1643 spinlock_t lock; 1644 wait_queue_head_t poll_wait; 1645 struct list_head event_list; 1646 atomic_t bytes_in_use; 1647 u8 is_destroyed:1; 1648 }; 1649 1650 struct devx_async_cmd_event_file { 1651 struct ib_uobject uobj; 1652 struct devx_async_event_queue ev_queue; 1653 struct mlx5_async_ctx async_ctx; 1654 }; 1655 1656 static void devx_init_event_queue(struct devx_async_event_queue *ev_queue) 1657 { 1658 spin_lock_init(&ev_queue->lock); 1659 INIT_LIST_HEAD(&ev_queue->event_list); 1660 init_waitqueue_head(&ev_queue->poll_wait); 1661 atomic_set(&ev_queue->bytes_in_use, 0); 1662 ev_queue->is_destroyed = 0; 1663 } 1664 1665 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)( 1666 struct uverbs_attr_bundle *attrs) 1667 { 1668 struct devx_async_cmd_event_file *ev_file; 1669 1670 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1671 attrs, MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE); 1672 struct mlx5_ib_dev *mdev = mlx5_udata_to_mdev(&attrs->driver_udata); 1673 1674 ev_file = container_of(uobj, struct devx_async_cmd_event_file, 1675 uobj); 1676 devx_init_event_queue(&ev_file->ev_queue); 1677 mlx5_cmd_init_async_ctx(mdev->mdev, &ev_file->async_ctx); 1678 return 0; 1679 } 1680 1681 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)( 1682 struct uverbs_attr_bundle *attrs) 1683 { 1684 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1685 attrs, MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE); 1686 struct devx_async_event_file *ev_file; 1687 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1688 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1689 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1690 u32 flags; 1691 int err; 1692 1693 err = uverbs_get_flags32(&flags, attrs, 1694 MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 1695 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA); 1696 1697 if (err) 1698 return err; 1699 1700 ev_file = container_of(uobj, struct devx_async_event_file, 1701 uobj); 1702 spin_lock_init(&ev_file->lock); 1703 INIT_LIST_HEAD(&ev_file->event_list); 1704 init_waitqueue_head(&ev_file->poll_wait); 1705 if (flags & MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA) 1706 ev_file->omit_data = 1; 1707 INIT_LIST_HEAD(&ev_file->subscribed_events_list); 1708 ev_file->dev = dev; 1709 get_device(&dev->ib_dev.dev); 1710 return 0; 1711 } 1712 1713 static void devx_query_callback(int status, struct mlx5_async_work *context) 1714 { 1715 struct devx_async_data *async_data = 1716 container_of(context, struct devx_async_data, cb_work); 1717 struct devx_async_cmd_event_file *ev_file = async_data->ev_file; 1718 struct devx_async_event_queue *ev_queue = &ev_file->ev_queue; 1719 unsigned long flags; 1720 1721 /* 1722 * Note that if the struct devx_async_cmd_event_file uobj begins to be 1723 * destroyed it will block at mlx5_cmd_cleanup_async_ctx() until this 1724 * routine returns, ensuring that it always remains valid here. 1725 */ 1726 spin_lock_irqsave(&ev_queue->lock, flags); 1727 list_add_tail(&async_data->list, &ev_queue->event_list); 1728 spin_unlock_irqrestore(&ev_queue->lock, flags); 1729 1730 wake_up_interruptible(&ev_queue->poll_wait); 1731 } 1732 1733 #define MAX_ASYNC_BYTES_IN_USE (1024 * 1024) /* 1MB */ 1734 1735 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)( 1736 struct uverbs_attr_bundle *attrs) 1737 { 1738 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, 1739 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN); 1740 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1741 attrs, 1742 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE); 1743 u16 cmd_out_len; 1744 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1745 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1746 struct ib_uobject *fd_uobj; 1747 int err; 1748 int uid; 1749 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1750 struct devx_async_cmd_event_file *ev_file; 1751 struct devx_async_data *async_data; 1752 1753 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1754 return -EINVAL; 1755 1756 uid = devx_get_uid(c, cmd_in); 1757 if (uid < 0) 1758 return uid; 1759 1760 if (!devx_is_obj_query_cmd(cmd_in)) 1761 return -EINVAL; 1762 1763 err = uverbs_get_const(&cmd_out_len, attrs, 1764 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN); 1765 if (err) 1766 return err; 1767 1768 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1769 return -EINVAL; 1770 1771 fd_uobj = uverbs_attr_get_uobject(attrs, 1772 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD); 1773 if (IS_ERR(fd_uobj)) 1774 return PTR_ERR(fd_uobj); 1775 1776 ev_file = container_of(fd_uobj, struct devx_async_cmd_event_file, 1777 uobj); 1778 1779 if (atomic_add_return(cmd_out_len, &ev_file->ev_queue.bytes_in_use) > 1780 MAX_ASYNC_BYTES_IN_USE) { 1781 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1782 return -EAGAIN; 1783 } 1784 1785 async_data = kvzalloc(struct_size(async_data, hdr.out_data, 1786 cmd_out_len), GFP_KERNEL); 1787 if (!async_data) { 1788 err = -ENOMEM; 1789 goto sub_bytes; 1790 } 1791 1792 err = uverbs_copy_from(&async_data->hdr.wr_id, attrs, 1793 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID); 1794 if (err) 1795 goto free_async; 1796 1797 async_data->cmd_out_len = cmd_out_len; 1798 async_data->mdev = mdev; 1799 async_data->ev_file = ev_file; 1800 1801 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1802 err = mlx5_cmd_exec_cb(&ev_file->async_ctx, cmd_in, 1803 uverbs_attr_get_len(attrs, 1804 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN), 1805 async_data->hdr.out_data, 1806 async_data->cmd_out_len, 1807 devx_query_callback, &async_data->cb_work); 1808 1809 if (err) 1810 goto free_async; 1811 1812 return 0; 1813 1814 free_async: 1815 kvfree(async_data); 1816 sub_bytes: 1817 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1818 return err; 1819 } 1820 1821 static void 1822 subscribe_event_xa_dealloc(struct mlx5_devx_event_table *devx_event_table, 1823 u32 key_level1, 1824 bool is_level2, 1825 u32 key_level2) 1826 { 1827 struct devx_event *event; 1828 struct devx_obj_event *xa_val_level2; 1829 1830 /* Level 1 is valid for future use, no need to free */ 1831 if (!is_level2) 1832 return; 1833 1834 event = xa_load(&devx_event_table->event_xa, key_level1); 1835 WARN_ON(!event); 1836 1837 xa_val_level2 = xa_load(&event->object_ids, 1838 key_level2); 1839 if (list_empty(&xa_val_level2->obj_sub_list)) { 1840 xa_erase(&event->object_ids, 1841 key_level2); 1842 kfree_rcu(xa_val_level2, rcu); 1843 } 1844 } 1845 1846 static int 1847 subscribe_event_xa_alloc(struct mlx5_devx_event_table *devx_event_table, 1848 u32 key_level1, 1849 bool is_level2, 1850 u32 key_level2) 1851 { 1852 struct devx_obj_event *obj_event; 1853 struct devx_event *event; 1854 int err; 1855 1856 event = xa_load(&devx_event_table->event_xa, key_level1); 1857 if (!event) { 1858 event = kzalloc(sizeof(*event), GFP_KERNEL); 1859 if (!event) 1860 return -ENOMEM; 1861 1862 INIT_LIST_HEAD(&event->unaffiliated_list); 1863 xa_init(&event->object_ids); 1864 1865 err = xa_insert(&devx_event_table->event_xa, 1866 key_level1, 1867 event, 1868 GFP_KERNEL); 1869 if (err) { 1870 kfree(event); 1871 return err; 1872 } 1873 } 1874 1875 if (!is_level2) 1876 return 0; 1877 1878 obj_event = xa_load(&event->object_ids, key_level2); 1879 if (!obj_event) { 1880 obj_event = kzalloc(sizeof(*obj_event), GFP_KERNEL); 1881 if (!obj_event) 1882 /* Level1 is valid for future use, no need to free */ 1883 return -ENOMEM; 1884 1885 err = xa_insert(&event->object_ids, 1886 key_level2, 1887 obj_event, 1888 GFP_KERNEL); 1889 if (err) 1890 return err; 1891 INIT_LIST_HEAD(&obj_event->obj_sub_list); 1892 } 1893 1894 return 0; 1895 } 1896 1897 static bool is_valid_events_legacy(int num_events, u16 *event_type_num_list, 1898 struct devx_obj *obj) 1899 { 1900 int i; 1901 1902 for (i = 0; i < num_events; i++) { 1903 if (obj) { 1904 if (!is_legacy_obj_event_num(event_type_num_list[i])) 1905 return false; 1906 } else if (!is_legacy_unaffiliated_event_num( 1907 event_type_num_list[i])) { 1908 return false; 1909 } 1910 } 1911 1912 return true; 1913 } 1914 1915 #define MAX_SUPP_EVENT_NUM 255 1916 static bool is_valid_events(struct mlx5_core_dev *dev, 1917 int num_events, u16 *event_type_num_list, 1918 struct devx_obj *obj) 1919 { 1920 __be64 *aff_events; 1921 __be64 *unaff_events; 1922 int mask_entry; 1923 int mask_bit; 1924 int i; 1925 1926 if (MLX5_CAP_GEN(dev, event_cap)) { 1927 aff_events = MLX5_CAP_DEV_EVENT(dev, 1928 user_affiliated_events); 1929 unaff_events = MLX5_CAP_DEV_EVENT(dev, 1930 user_unaffiliated_events); 1931 } else { 1932 return is_valid_events_legacy(num_events, event_type_num_list, 1933 obj); 1934 } 1935 1936 for (i = 0; i < num_events; i++) { 1937 if (event_type_num_list[i] > MAX_SUPP_EVENT_NUM) 1938 return false; 1939 1940 mask_entry = event_type_num_list[i] / 64; 1941 mask_bit = event_type_num_list[i] % 64; 1942 1943 if (obj) { 1944 /* CQ completion */ 1945 if (event_type_num_list[i] == 0) 1946 continue; 1947 1948 if (!(be64_to_cpu(aff_events[mask_entry]) & 1949 (1ull << mask_bit))) 1950 return false; 1951 1952 continue; 1953 } 1954 1955 if (!(be64_to_cpu(unaff_events[mask_entry]) & 1956 (1ull << mask_bit))) 1957 return false; 1958 } 1959 1960 return true; 1961 } 1962 1963 #define MAX_NUM_EVENTS 16 1964 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)( 1965 struct uverbs_attr_bundle *attrs) 1966 { 1967 struct ib_uobject *devx_uobj = uverbs_attr_get_uobject( 1968 attrs, 1969 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE); 1970 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1971 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1972 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1973 struct ib_uobject *fd_uobj; 1974 struct devx_obj *obj = NULL; 1975 struct devx_async_event_file *ev_file; 1976 struct mlx5_devx_event_table *devx_event_table = &dev->devx_event_table; 1977 u16 *event_type_num_list; 1978 struct devx_event_subscription *event_sub, *tmp_sub; 1979 struct list_head sub_list; 1980 int redirect_fd; 1981 bool use_eventfd = false; 1982 int num_events; 1983 int num_alloc_xa_entries = 0; 1984 u16 obj_type = 0; 1985 u64 cookie = 0; 1986 u32 obj_id = 0; 1987 int err; 1988 int i; 1989 1990 if (!c->devx_uid) 1991 return -EINVAL; 1992 1993 if (!IS_ERR(devx_uobj)) { 1994 obj = (struct devx_obj *)devx_uobj->object; 1995 if (obj) 1996 obj_id = get_dec_obj_id(obj->obj_id); 1997 } 1998 1999 fd_uobj = uverbs_attr_get_uobject(attrs, 2000 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE); 2001 if (IS_ERR(fd_uobj)) 2002 return PTR_ERR(fd_uobj); 2003 2004 ev_file = container_of(fd_uobj, struct devx_async_event_file, 2005 uobj); 2006 2007 if (uverbs_attr_is_valid(attrs, 2008 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM)) { 2009 err = uverbs_copy_from(&redirect_fd, attrs, 2010 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM); 2011 if (err) 2012 return err; 2013 2014 use_eventfd = true; 2015 } 2016 2017 if (uverbs_attr_is_valid(attrs, 2018 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE)) { 2019 if (use_eventfd) 2020 return -EINVAL; 2021 2022 err = uverbs_copy_from(&cookie, attrs, 2023 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE); 2024 if (err) 2025 return err; 2026 } 2027 2028 num_events = uverbs_attr_ptr_get_array_size( 2029 attrs, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 2030 sizeof(u16)); 2031 2032 if (num_events < 0) 2033 return num_events; 2034 2035 if (num_events > MAX_NUM_EVENTS) 2036 return -EINVAL; 2037 2038 event_type_num_list = uverbs_attr_get_alloced_ptr(attrs, 2039 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST); 2040 2041 if (!is_valid_events(dev->mdev, num_events, event_type_num_list, obj)) 2042 return -EINVAL; 2043 2044 INIT_LIST_HEAD(&sub_list); 2045 2046 /* Protect from concurrent subscriptions to same XA entries to allow 2047 * both to succeed 2048 */ 2049 mutex_lock(&devx_event_table->event_xa_lock); 2050 for (i = 0; i < num_events; i++) { 2051 u32 key_level1; 2052 2053 if (obj) 2054 obj_type = get_dec_obj_type(obj, 2055 event_type_num_list[i]); 2056 key_level1 = event_type_num_list[i] | obj_type << 16; 2057 2058 err = subscribe_event_xa_alloc(devx_event_table, 2059 key_level1, 2060 obj, 2061 obj_id); 2062 if (err) 2063 goto err; 2064 2065 num_alloc_xa_entries++; 2066 event_sub = kzalloc(sizeof(*event_sub), GFP_KERNEL); 2067 if (!event_sub) { 2068 err = -ENOMEM; 2069 goto err; 2070 } 2071 2072 list_add_tail(&event_sub->event_list, &sub_list); 2073 uverbs_uobject_get(&ev_file->uobj); 2074 if (use_eventfd) { 2075 event_sub->eventfd = 2076 eventfd_ctx_fdget(redirect_fd); 2077 2078 if (IS_ERR(event_sub->eventfd)) { 2079 err = PTR_ERR(event_sub->eventfd); 2080 event_sub->eventfd = NULL; 2081 goto err; 2082 } 2083 } 2084 2085 event_sub->cookie = cookie; 2086 event_sub->ev_file = ev_file; 2087 /* May be needed upon cleanup the devx object/subscription */ 2088 event_sub->xa_key_level1 = key_level1; 2089 event_sub->xa_key_level2 = obj_id; 2090 INIT_LIST_HEAD(&event_sub->obj_list); 2091 } 2092 2093 /* Once all the allocations and the XA data insertions were done we 2094 * can go ahead and add all the subscriptions to the relevant lists 2095 * without concern of a failure. 2096 */ 2097 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2098 struct devx_event *event; 2099 struct devx_obj_event *obj_event; 2100 2101 list_del_init(&event_sub->event_list); 2102 2103 spin_lock_irq(&ev_file->lock); 2104 list_add_tail_rcu(&event_sub->file_list, 2105 &ev_file->subscribed_events_list); 2106 spin_unlock_irq(&ev_file->lock); 2107 2108 event = xa_load(&devx_event_table->event_xa, 2109 event_sub->xa_key_level1); 2110 WARN_ON(!event); 2111 2112 if (!obj) { 2113 list_add_tail_rcu(&event_sub->xa_list, 2114 &event->unaffiliated_list); 2115 continue; 2116 } 2117 2118 obj_event = xa_load(&event->object_ids, obj_id); 2119 WARN_ON(!obj_event); 2120 list_add_tail_rcu(&event_sub->xa_list, 2121 &obj_event->obj_sub_list); 2122 list_add_tail_rcu(&event_sub->obj_list, 2123 &obj->event_sub); 2124 } 2125 2126 mutex_unlock(&devx_event_table->event_xa_lock); 2127 return 0; 2128 2129 err: 2130 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2131 list_del(&event_sub->event_list); 2132 2133 subscribe_event_xa_dealloc(devx_event_table, 2134 event_sub->xa_key_level1, 2135 obj, 2136 obj_id); 2137 2138 if (event_sub->eventfd) 2139 eventfd_ctx_put(event_sub->eventfd); 2140 uverbs_uobject_put(&event_sub->ev_file->uobj); 2141 kfree(event_sub); 2142 } 2143 2144 mutex_unlock(&devx_event_table->event_xa_lock); 2145 return err; 2146 } 2147 2148 static int devx_umem_get(struct mlx5_ib_dev *dev, struct ib_ucontext *ucontext, 2149 struct uverbs_attr_bundle *attrs, 2150 struct devx_umem *obj) 2151 { 2152 u64 addr; 2153 size_t size; 2154 u32 access; 2155 int err; 2156 2157 if (uverbs_copy_from(&addr, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR) || 2158 uverbs_copy_from(&size, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN)) 2159 return -EFAULT; 2160 2161 err = uverbs_get_flags32(&access, attrs, 2162 MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 2163 IB_ACCESS_LOCAL_WRITE | 2164 IB_ACCESS_REMOTE_WRITE | 2165 IB_ACCESS_REMOTE_READ); 2166 if (err) 2167 return err; 2168 2169 err = ib_check_mr_access(&dev->ib_dev, access); 2170 if (err) 2171 return err; 2172 2173 obj->umem = ib_umem_get(&dev->ib_dev, addr, size, access); 2174 if (IS_ERR(obj->umem)) 2175 return PTR_ERR(obj->umem); 2176 return 0; 2177 } 2178 2179 static unsigned int devx_umem_find_best_pgsize(struct ib_umem *umem, 2180 unsigned long pgsz_bitmap) 2181 { 2182 unsigned long page_size; 2183 2184 /* Don't bother checking larger page sizes as offset must be zero and 2185 * total DEVX umem length must be equal to total umem length. 2186 */ 2187 pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length), 2188 PAGE_SHIFT), 2189 MLX5_ADAPTER_PAGE_SHIFT); 2190 if (!pgsz_bitmap) 2191 return 0; 2192 2193 page_size = ib_umem_find_best_pgoff(umem, pgsz_bitmap, U64_MAX); 2194 if (!page_size) 2195 return 0; 2196 2197 /* If the page_size is less than the CPU page size then we can use the 2198 * offset and create a umem which is a subset of the page list. 2199 * For larger page sizes we can't be sure the DMA list reflects the 2200 * VA so we must ensure that the umem extent is exactly equal to the 2201 * page list. Reduce the page size until one of these cases is true. 2202 */ 2203 while ((ib_umem_dma_offset(umem, page_size) != 0 || 2204 (umem->length % page_size) != 0) && 2205 page_size > PAGE_SIZE) 2206 page_size /= 2; 2207 2208 return page_size; 2209 } 2210 2211 static int devx_umem_reg_cmd_alloc(struct mlx5_ib_dev *dev, 2212 struct uverbs_attr_bundle *attrs, 2213 struct devx_umem *obj, 2214 struct devx_umem_reg_cmd *cmd) 2215 { 2216 unsigned long pgsz_bitmap; 2217 unsigned int page_size; 2218 __be64 *mtt; 2219 void *umem; 2220 int ret; 2221 2222 /* 2223 * If the user does not pass in pgsz_bitmap then the user promises not 2224 * to use umem_offset!=0 in any commands that allocate on top of the 2225 * umem. 2226 * 2227 * If the user wants to use a umem_offset then it must pass in 2228 * pgsz_bitmap which guides the maximum page size and thus maximum 2229 * object alignment inside the umem. See the PRM. 2230 * 2231 * Users are not allowed to use IOVA here, mkeys are not supported on 2232 * umem. 2233 */ 2234 ret = uverbs_get_const_default(&pgsz_bitmap, attrs, 2235 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, 2236 GENMASK_ULL(63, 2237 min(PAGE_SHIFT, MLX5_ADAPTER_PAGE_SHIFT))); 2238 if (ret) 2239 return ret; 2240 2241 page_size = devx_umem_find_best_pgsize(obj->umem, pgsz_bitmap); 2242 if (!page_size) 2243 return -EINVAL; 2244 2245 cmd->inlen = MLX5_ST_SZ_BYTES(create_umem_in) + 2246 (MLX5_ST_SZ_BYTES(mtt) * 2247 ib_umem_num_dma_blocks(obj->umem, page_size)); 2248 cmd->in = uverbs_zalloc(attrs, cmd->inlen); 2249 if (IS_ERR(cmd->in)) 2250 return PTR_ERR(cmd->in); 2251 2252 umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem); 2253 mtt = (__be64 *)MLX5_ADDR_OF(umem, umem, mtt); 2254 2255 MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM); 2256 MLX5_SET64(umem, umem, num_of_mtt, 2257 ib_umem_num_dma_blocks(obj->umem, page_size)); 2258 MLX5_SET(umem, umem, log_page_size, 2259 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 2260 MLX5_SET(umem, umem, page_offset, 2261 ib_umem_dma_offset(obj->umem, page_size)); 2262 2263 mlx5_ib_populate_pas(obj->umem, page_size, mtt, 2264 (obj->umem->writable ? MLX5_IB_MTT_WRITE : 0) | 2265 MLX5_IB_MTT_READ); 2266 return 0; 2267 } 2268 2269 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_UMEM_REG)( 2270 struct uverbs_attr_bundle *attrs) 2271 { 2272 struct devx_umem_reg_cmd cmd; 2273 struct devx_umem *obj; 2274 struct ib_uobject *uobj = uverbs_attr_get_uobject( 2275 attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE); 2276 u32 obj_id; 2277 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 2278 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2279 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 2280 int err; 2281 2282 if (!c->devx_uid) 2283 return -EINVAL; 2284 2285 obj = kzalloc(sizeof(struct devx_umem), GFP_KERNEL); 2286 if (!obj) 2287 return -ENOMEM; 2288 2289 err = devx_umem_get(dev, &c->ibucontext, attrs, obj); 2290 if (err) 2291 goto err_obj_free; 2292 2293 err = devx_umem_reg_cmd_alloc(dev, attrs, obj, &cmd); 2294 if (err) 2295 goto err_umem_release; 2296 2297 MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid); 2298 err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out, 2299 sizeof(cmd.out)); 2300 if (err) 2301 goto err_umem_release; 2302 2303 obj->mdev = dev->mdev; 2304 uobj->object = obj; 2305 devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id); 2306 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE); 2307 2308 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, &obj_id, 2309 sizeof(obj_id)); 2310 return err; 2311 2312 err_umem_release: 2313 ib_umem_release(obj->umem); 2314 err_obj_free: 2315 kfree(obj); 2316 return err; 2317 } 2318 2319 static int devx_umem_cleanup(struct ib_uobject *uobject, 2320 enum rdma_remove_reason why, 2321 struct uverbs_attr_bundle *attrs) 2322 { 2323 struct devx_umem *obj = uobject->object; 2324 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2325 int err; 2326 2327 err = mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, out, sizeof(out)); 2328 if (err) 2329 return err; 2330 2331 ib_umem_release(obj->umem); 2332 kfree(obj); 2333 return 0; 2334 } 2335 2336 static bool is_unaffiliated_event(struct mlx5_core_dev *dev, 2337 unsigned long event_type) 2338 { 2339 __be64 *unaff_events; 2340 int mask_entry; 2341 int mask_bit; 2342 2343 if (!MLX5_CAP_GEN(dev, event_cap)) 2344 return is_legacy_unaffiliated_event_num(event_type); 2345 2346 unaff_events = MLX5_CAP_DEV_EVENT(dev, 2347 user_unaffiliated_events); 2348 WARN_ON(event_type > MAX_SUPP_EVENT_NUM); 2349 2350 mask_entry = event_type / 64; 2351 mask_bit = event_type % 64; 2352 2353 if (!(be64_to_cpu(unaff_events[mask_entry]) & (1ull << mask_bit))) 2354 return false; 2355 2356 return true; 2357 } 2358 2359 static u32 devx_get_obj_id_from_event(unsigned long event_type, void *data) 2360 { 2361 struct mlx5_eqe *eqe = data; 2362 u32 obj_id = 0; 2363 2364 switch (event_type) { 2365 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 2366 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 2367 case MLX5_EVENT_TYPE_PATH_MIG: 2368 case MLX5_EVENT_TYPE_COMM_EST: 2369 case MLX5_EVENT_TYPE_SQ_DRAINED: 2370 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 2371 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 2372 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 2373 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 2374 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 2375 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 2376 break; 2377 case MLX5_EVENT_TYPE_XRQ_ERROR: 2378 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff; 2379 break; 2380 case MLX5_EVENT_TYPE_DCT_DRAINED: 2381 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 2382 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; 2383 break; 2384 case MLX5_EVENT_TYPE_CQ_ERROR: 2385 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 2386 break; 2387 default: 2388 obj_id = MLX5_GET(affiliated_event_header, &eqe->data, obj_id); 2389 break; 2390 } 2391 2392 return obj_id; 2393 } 2394 2395 static int deliver_event(struct devx_event_subscription *event_sub, 2396 const void *data) 2397 { 2398 struct devx_async_event_file *ev_file; 2399 struct devx_async_event_data *event_data; 2400 unsigned long flags; 2401 2402 ev_file = event_sub->ev_file; 2403 2404 if (ev_file->omit_data) { 2405 spin_lock_irqsave(&ev_file->lock, flags); 2406 if (!list_empty(&event_sub->event_list) || 2407 ev_file->is_destroyed) { 2408 spin_unlock_irqrestore(&ev_file->lock, flags); 2409 return 0; 2410 } 2411 2412 list_add_tail(&event_sub->event_list, &ev_file->event_list); 2413 spin_unlock_irqrestore(&ev_file->lock, flags); 2414 wake_up_interruptible(&ev_file->poll_wait); 2415 return 0; 2416 } 2417 2418 event_data = kzalloc(sizeof(*event_data) + sizeof(struct mlx5_eqe), 2419 GFP_ATOMIC); 2420 if (!event_data) { 2421 spin_lock_irqsave(&ev_file->lock, flags); 2422 ev_file->is_overflow_err = 1; 2423 spin_unlock_irqrestore(&ev_file->lock, flags); 2424 return -ENOMEM; 2425 } 2426 2427 event_data->hdr.cookie = event_sub->cookie; 2428 memcpy(event_data->hdr.out_data, data, sizeof(struct mlx5_eqe)); 2429 2430 spin_lock_irqsave(&ev_file->lock, flags); 2431 if (!ev_file->is_destroyed) 2432 list_add_tail(&event_data->list, &ev_file->event_list); 2433 else 2434 kfree(event_data); 2435 spin_unlock_irqrestore(&ev_file->lock, flags); 2436 wake_up_interruptible(&ev_file->poll_wait); 2437 2438 return 0; 2439 } 2440 2441 static void dispatch_event_fd(struct list_head *fd_list, 2442 const void *data) 2443 { 2444 struct devx_event_subscription *item; 2445 2446 list_for_each_entry_rcu(item, fd_list, xa_list) { 2447 if (item->eventfd) 2448 eventfd_signal(item->eventfd, 1); 2449 else 2450 deliver_event(item, data); 2451 } 2452 } 2453 2454 static int devx_event_notifier(struct notifier_block *nb, 2455 unsigned long event_type, void *data) 2456 { 2457 struct mlx5_devx_event_table *table; 2458 struct mlx5_ib_dev *dev; 2459 struct devx_event *event; 2460 struct devx_obj_event *obj_event; 2461 u16 obj_type = 0; 2462 bool is_unaffiliated; 2463 u32 obj_id; 2464 2465 /* Explicit filtering to kernel events which may occur frequently */ 2466 if (event_type == MLX5_EVENT_TYPE_CMD || 2467 event_type == MLX5_EVENT_TYPE_PAGE_REQUEST) 2468 return NOTIFY_OK; 2469 2470 table = container_of(nb, struct mlx5_devx_event_table, devx_nb.nb); 2471 dev = container_of(table, struct mlx5_ib_dev, devx_event_table); 2472 is_unaffiliated = is_unaffiliated_event(dev->mdev, event_type); 2473 2474 if (!is_unaffiliated) 2475 obj_type = get_event_obj_type(event_type, data); 2476 2477 rcu_read_lock(); 2478 event = xa_load(&table->event_xa, event_type | (obj_type << 16)); 2479 if (!event) { 2480 rcu_read_unlock(); 2481 return NOTIFY_DONE; 2482 } 2483 2484 if (is_unaffiliated) { 2485 dispatch_event_fd(&event->unaffiliated_list, data); 2486 rcu_read_unlock(); 2487 return NOTIFY_OK; 2488 } 2489 2490 obj_id = devx_get_obj_id_from_event(event_type, data); 2491 obj_event = xa_load(&event->object_ids, obj_id); 2492 if (!obj_event) { 2493 rcu_read_unlock(); 2494 return NOTIFY_DONE; 2495 } 2496 2497 dispatch_event_fd(&obj_event->obj_sub_list, data); 2498 2499 rcu_read_unlock(); 2500 return NOTIFY_OK; 2501 } 2502 2503 int mlx5_ib_devx_init(struct mlx5_ib_dev *dev) 2504 { 2505 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2506 int uid; 2507 2508 uid = mlx5_ib_devx_create(dev, false); 2509 if (uid > 0) { 2510 dev->devx_whitelist_uid = uid; 2511 xa_init(&table->event_xa); 2512 mutex_init(&table->event_xa_lock); 2513 MLX5_NB_INIT(&table->devx_nb, devx_event_notifier, NOTIFY_ANY); 2514 mlx5_eq_notifier_register(dev->mdev, &table->devx_nb); 2515 } 2516 2517 return 0; 2518 } 2519 2520 void mlx5_ib_devx_cleanup(struct mlx5_ib_dev *dev) 2521 { 2522 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2523 struct devx_event_subscription *sub, *tmp; 2524 struct devx_event *event; 2525 void *entry; 2526 unsigned long id; 2527 2528 if (dev->devx_whitelist_uid) { 2529 mlx5_eq_notifier_unregister(dev->mdev, &table->devx_nb); 2530 mutex_lock(&dev->devx_event_table.event_xa_lock); 2531 xa_for_each(&table->event_xa, id, entry) { 2532 event = entry; 2533 list_for_each_entry_safe( 2534 sub, tmp, &event->unaffiliated_list, xa_list) 2535 devx_cleanup_subscription(dev, sub); 2536 kfree(entry); 2537 } 2538 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2539 xa_destroy(&table->event_xa); 2540 2541 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 2542 } 2543 } 2544 2545 static ssize_t devx_async_cmd_event_read(struct file *filp, char __user *buf, 2546 size_t count, loff_t *pos) 2547 { 2548 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2549 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2550 struct devx_async_data *event; 2551 int ret = 0; 2552 size_t eventsz; 2553 2554 spin_lock_irq(&ev_queue->lock); 2555 2556 while (list_empty(&ev_queue->event_list)) { 2557 spin_unlock_irq(&ev_queue->lock); 2558 2559 if (filp->f_flags & O_NONBLOCK) 2560 return -EAGAIN; 2561 2562 if (wait_event_interruptible( 2563 ev_queue->poll_wait, 2564 (!list_empty(&ev_queue->event_list) || 2565 ev_queue->is_destroyed))) { 2566 return -ERESTARTSYS; 2567 } 2568 2569 spin_lock_irq(&ev_queue->lock); 2570 if (ev_queue->is_destroyed) { 2571 spin_unlock_irq(&ev_queue->lock); 2572 return -EIO; 2573 } 2574 } 2575 2576 event = list_entry(ev_queue->event_list.next, 2577 struct devx_async_data, list); 2578 eventsz = event->cmd_out_len + 2579 sizeof(struct mlx5_ib_uapi_devx_async_cmd_hdr); 2580 2581 if (eventsz > count) { 2582 spin_unlock_irq(&ev_queue->lock); 2583 return -ENOSPC; 2584 } 2585 2586 list_del(ev_queue->event_list.next); 2587 spin_unlock_irq(&ev_queue->lock); 2588 2589 if (copy_to_user(buf, &event->hdr, eventsz)) 2590 ret = -EFAULT; 2591 else 2592 ret = eventsz; 2593 2594 atomic_sub(event->cmd_out_len, &ev_queue->bytes_in_use); 2595 kvfree(event); 2596 return ret; 2597 } 2598 2599 static __poll_t devx_async_cmd_event_poll(struct file *filp, 2600 struct poll_table_struct *wait) 2601 { 2602 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2603 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2604 __poll_t pollflags = 0; 2605 2606 poll_wait(filp, &ev_queue->poll_wait, wait); 2607 2608 spin_lock_irq(&ev_queue->lock); 2609 if (ev_queue->is_destroyed) 2610 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; 2611 else if (!list_empty(&ev_queue->event_list)) 2612 pollflags = EPOLLIN | EPOLLRDNORM; 2613 spin_unlock_irq(&ev_queue->lock); 2614 2615 return pollflags; 2616 } 2617 2618 static const struct file_operations devx_async_cmd_event_fops = { 2619 .owner = THIS_MODULE, 2620 .read = devx_async_cmd_event_read, 2621 .poll = devx_async_cmd_event_poll, 2622 .release = uverbs_uobject_fd_release, 2623 .llseek = no_llseek, 2624 }; 2625 2626 static ssize_t devx_async_event_read(struct file *filp, char __user *buf, 2627 size_t count, loff_t *pos) 2628 { 2629 struct devx_async_event_file *ev_file = filp->private_data; 2630 struct devx_event_subscription *event_sub; 2631 struct devx_async_event_data *event; 2632 int ret = 0; 2633 size_t eventsz; 2634 bool omit_data; 2635 void *event_data; 2636 2637 omit_data = ev_file->omit_data; 2638 2639 spin_lock_irq(&ev_file->lock); 2640 2641 if (ev_file->is_overflow_err) { 2642 ev_file->is_overflow_err = 0; 2643 spin_unlock_irq(&ev_file->lock); 2644 return -EOVERFLOW; 2645 } 2646 2647 2648 while (list_empty(&ev_file->event_list)) { 2649 spin_unlock_irq(&ev_file->lock); 2650 2651 if (filp->f_flags & O_NONBLOCK) 2652 return -EAGAIN; 2653 2654 if (wait_event_interruptible(ev_file->poll_wait, 2655 (!list_empty(&ev_file->event_list) || 2656 ev_file->is_destroyed))) { 2657 return -ERESTARTSYS; 2658 } 2659 2660 spin_lock_irq(&ev_file->lock); 2661 if (ev_file->is_destroyed) { 2662 spin_unlock_irq(&ev_file->lock); 2663 return -EIO; 2664 } 2665 } 2666 2667 if (omit_data) { 2668 event_sub = list_first_entry(&ev_file->event_list, 2669 struct devx_event_subscription, 2670 event_list); 2671 eventsz = sizeof(event_sub->cookie); 2672 event_data = &event_sub->cookie; 2673 } else { 2674 event = list_first_entry(&ev_file->event_list, 2675 struct devx_async_event_data, list); 2676 eventsz = sizeof(struct mlx5_eqe) + 2677 sizeof(struct mlx5_ib_uapi_devx_async_event_hdr); 2678 event_data = &event->hdr; 2679 } 2680 2681 if (eventsz > count) { 2682 spin_unlock_irq(&ev_file->lock); 2683 return -EINVAL; 2684 } 2685 2686 if (omit_data) 2687 list_del_init(&event_sub->event_list); 2688 else 2689 list_del(&event->list); 2690 2691 spin_unlock_irq(&ev_file->lock); 2692 2693 if (copy_to_user(buf, event_data, eventsz)) 2694 /* This points to an application issue, not a kernel concern */ 2695 ret = -EFAULT; 2696 else 2697 ret = eventsz; 2698 2699 if (!omit_data) 2700 kfree(event); 2701 return ret; 2702 } 2703 2704 static __poll_t devx_async_event_poll(struct file *filp, 2705 struct poll_table_struct *wait) 2706 { 2707 struct devx_async_event_file *ev_file = filp->private_data; 2708 __poll_t pollflags = 0; 2709 2710 poll_wait(filp, &ev_file->poll_wait, wait); 2711 2712 spin_lock_irq(&ev_file->lock); 2713 if (ev_file->is_destroyed) 2714 pollflags = EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; 2715 else if (!list_empty(&ev_file->event_list)) 2716 pollflags = EPOLLIN | EPOLLRDNORM; 2717 spin_unlock_irq(&ev_file->lock); 2718 2719 return pollflags; 2720 } 2721 2722 static void devx_free_subscription(struct rcu_head *rcu) 2723 { 2724 struct devx_event_subscription *event_sub = 2725 container_of(rcu, struct devx_event_subscription, rcu); 2726 2727 if (event_sub->eventfd) 2728 eventfd_ctx_put(event_sub->eventfd); 2729 uverbs_uobject_put(&event_sub->ev_file->uobj); 2730 kfree(event_sub); 2731 } 2732 2733 static const struct file_operations devx_async_event_fops = { 2734 .owner = THIS_MODULE, 2735 .read = devx_async_event_read, 2736 .poll = devx_async_event_poll, 2737 .release = uverbs_uobject_fd_release, 2738 .llseek = no_llseek, 2739 }; 2740 2741 static void devx_async_cmd_event_destroy_uobj(struct ib_uobject *uobj, 2742 enum rdma_remove_reason why) 2743 { 2744 struct devx_async_cmd_event_file *comp_ev_file = 2745 container_of(uobj, struct devx_async_cmd_event_file, 2746 uobj); 2747 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2748 struct devx_async_data *entry, *tmp; 2749 2750 spin_lock_irq(&ev_queue->lock); 2751 ev_queue->is_destroyed = 1; 2752 spin_unlock_irq(&ev_queue->lock); 2753 wake_up_interruptible(&ev_queue->poll_wait); 2754 2755 mlx5_cmd_cleanup_async_ctx(&comp_ev_file->async_ctx); 2756 2757 spin_lock_irq(&comp_ev_file->ev_queue.lock); 2758 list_for_each_entry_safe(entry, tmp, 2759 &comp_ev_file->ev_queue.event_list, list) { 2760 list_del(&entry->list); 2761 kvfree(entry); 2762 } 2763 spin_unlock_irq(&comp_ev_file->ev_queue.lock); 2764 }; 2765 2766 static void devx_async_event_destroy_uobj(struct ib_uobject *uobj, 2767 enum rdma_remove_reason why) 2768 { 2769 struct devx_async_event_file *ev_file = 2770 container_of(uobj, struct devx_async_event_file, 2771 uobj); 2772 struct devx_event_subscription *event_sub, *event_sub_tmp; 2773 struct mlx5_ib_dev *dev = ev_file->dev; 2774 2775 spin_lock_irq(&ev_file->lock); 2776 ev_file->is_destroyed = 1; 2777 2778 /* free the pending events allocation */ 2779 if (ev_file->omit_data) { 2780 struct devx_event_subscription *event_sub, *tmp; 2781 2782 list_for_each_entry_safe(event_sub, tmp, &ev_file->event_list, 2783 event_list) 2784 list_del_init(&event_sub->event_list); 2785 2786 } else { 2787 struct devx_async_event_data *entry, *tmp; 2788 2789 list_for_each_entry_safe(entry, tmp, &ev_file->event_list, 2790 list) { 2791 list_del(&entry->list); 2792 kfree(entry); 2793 } 2794 } 2795 2796 spin_unlock_irq(&ev_file->lock); 2797 wake_up_interruptible(&ev_file->poll_wait); 2798 2799 mutex_lock(&dev->devx_event_table.event_xa_lock); 2800 /* delete the subscriptions which are related to this FD */ 2801 list_for_each_entry_safe(event_sub, event_sub_tmp, 2802 &ev_file->subscribed_events_list, file_list) { 2803 devx_cleanup_subscription(dev, event_sub); 2804 list_del_rcu(&event_sub->file_list); 2805 /* subscription may not be used by the read API any more */ 2806 call_rcu(&event_sub->rcu, devx_free_subscription); 2807 } 2808 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2809 2810 put_device(&dev->ib_dev.dev); 2811 }; 2812 2813 DECLARE_UVERBS_NAMED_METHOD( 2814 MLX5_IB_METHOD_DEVX_UMEM_REG, 2815 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE, 2816 MLX5_IB_OBJECT_DEVX_UMEM, 2817 UVERBS_ACCESS_NEW, 2818 UA_MANDATORY), 2819 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR, 2820 UVERBS_ATTR_TYPE(u64), 2821 UA_MANDATORY), 2822 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_LEN, 2823 UVERBS_ATTR_TYPE(u64), 2824 UA_MANDATORY), 2825 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 2826 enum ib_access_flags), 2827 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, 2828 u64), 2829 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, 2830 UVERBS_ATTR_TYPE(u32), 2831 UA_MANDATORY)); 2832 2833 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 2834 MLX5_IB_METHOD_DEVX_UMEM_DEREG, 2835 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE, 2836 MLX5_IB_OBJECT_DEVX_UMEM, 2837 UVERBS_ACCESS_DESTROY, 2838 UA_MANDATORY)); 2839 2840 DECLARE_UVERBS_NAMED_METHOD( 2841 MLX5_IB_METHOD_DEVX_QUERY_EQN, 2842 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC, 2843 UVERBS_ATTR_TYPE(u32), 2844 UA_MANDATORY), 2845 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 2846 UVERBS_ATTR_TYPE(u32), 2847 UA_MANDATORY)); 2848 2849 DECLARE_UVERBS_NAMED_METHOD( 2850 MLX5_IB_METHOD_DEVX_QUERY_UAR, 2851 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX, 2852 UVERBS_ATTR_TYPE(u32), 2853 UA_MANDATORY), 2854 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 2855 UVERBS_ATTR_TYPE(u32), 2856 UA_MANDATORY)); 2857 2858 DECLARE_UVERBS_NAMED_METHOD( 2859 MLX5_IB_METHOD_DEVX_OTHER, 2860 UVERBS_ATTR_PTR_IN( 2861 MLX5_IB_ATTR_DEVX_OTHER_CMD_IN, 2862 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2863 UA_MANDATORY, 2864 UA_ALLOC_AND_COPY), 2865 UVERBS_ATTR_PTR_OUT( 2866 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, 2867 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2868 UA_MANDATORY)); 2869 2870 DECLARE_UVERBS_NAMED_METHOD( 2871 MLX5_IB_METHOD_DEVX_OBJ_CREATE, 2872 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE, 2873 MLX5_IB_OBJECT_DEVX_OBJ, 2874 UVERBS_ACCESS_NEW, 2875 UA_MANDATORY), 2876 UVERBS_ATTR_PTR_IN( 2877 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN, 2878 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2879 UA_MANDATORY, 2880 UA_ALLOC_AND_COPY), 2881 UVERBS_ATTR_PTR_OUT( 2882 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, 2883 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2884 UA_MANDATORY)); 2885 2886 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 2887 MLX5_IB_METHOD_DEVX_OBJ_DESTROY, 2888 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE, 2889 MLX5_IB_OBJECT_DEVX_OBJ, 2890 UVERBS_ACCESS_DESTROY, 2891 UA_MANDATORY)); 2892 2893 DECLARE_UVERBS_NAMED_METHOD( 2894 MLX5_IB_METHOD_DEVX_OBJ_MODIFY, 2895 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE, 2896 UVERBS_IDR_ANY_OBJECT, 2897 UVERBS_ACCESS_WRITE, 2898 UA_MANDATORY), 2899 UVERBS_ATTR_PTR_IN( 2900 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN, 2901 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2902 UA_MANDATORY, 2903 UA_ALLOC_AND_COPY), 2904 UVERBS_ATTR_PTR_OUT( 2905 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 2906 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2907 UA_MANDATORY)); 2908 2909 DECLARE_UVERBS_NAMED_METHOD( 2910 MLX5_IB_METHOD_DEVX_OBJ_QUERY, 2911 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 2912 UVERBS_IDR_ANY_OBJECT, 2913 UVERBS_ACCESS_READ, 2914 UA_MANDATORY), 2915 UVERBS_ATTR_PTR_IN( 2916 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 2917 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2918 UA_MANDATORY, 2919 UA_ALLOC_AND_COPY), 2920 UVERBS_ATTR_PTR_OUT( 2921 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 2922 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2923 UA_MANDATORY)); 2924 2925 DECLARE_UVERBS_NAMED_METHOD( 2926 MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY, 2927 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 2928 UVERBS_IDR_ANY_OBJECT, 2929 UVERBS_ACCESS_READ, 2930 UA_MANDATORY), 2931 UVERBS_ATTR_PTR_IN( 2932 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 2933 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2934 UA_MANDATORY, 2935 UA_ALLOC_AND_COPY), 2936 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN, 2937 u16, UA_MANDATORY), 2938 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD, 2939 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 2940 UVERBS_ACCESS_READ, 2941 UA_MANDATORY), 2942 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID, 2943 UVERBS_ATTR_TYPE(u64), 2944 UA_MANDATORY)); 2945 2946 DECLARE_UVERBS_NAMED_METHOD( 2947 MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT, 2948 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE, 2949 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 2950 UVERBS_ACCESS_READ, 2951 UA_MANDATORY), 2952 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE, 2953 MLX5_IB_OBJECT_DEVX_OBJ, 2954 UVERBS_ACCESS_READ, 2955 UA_OPTIONAL), 2956 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 2957 UVERBS_ATTR_MIN_SIZE(sizeof(u16)), 2958 UA_MANDATORY, 2959 UA_ALLOC_AND_COPY), 2960 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE, 2961 UVERBS_ATTR_TYPE(u64), 2962 UA_OPTIONAL), 2963 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM, 2964 UVERBS_ATTR_TYPE(u32), 2965 UA_OPTIONAL)); 2966 2967 DECLARE_UVERBS_GLOBAL_METHODS(MLX5_IB_OBJECT_DEVX, 2968 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OTHER), 2969 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_UAR), 2970 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_EQN), 2971 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)); 2972 2973 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_OBJ, 2974 UVERBS_TYPE_ALLOC_IDR(devx_obj_cleanup), 2975 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_CREATE), 2976 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_DESTROY), 2977 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_MODIFY), 2978 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_QUERY), 2979 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)); 2980 2981 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_UMEM, 2982 UVERBS_TYPE_ALLOC_IDR(devx_umem_cleanup), 2983 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_REG), 2984 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_DEREG)); 2985 2986 2987 DECLARE_UVERBS_NAMED_METHOD( 2988 MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC, 2989 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE, 2990 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 2991 UVERBS_ACCESS_NEW, 2992 UA_MANDATORY)); 2993 2994 DECLARE_UVERBS_NAMED_OBJECT( 2995 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 2996 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_cmd_event_file), 2997 devx_async_cmd_event_destroy_uobj, 2998 &devx_async_cmd_event_fops, "[devx_async_cmd]", 2999 O_RDONLY), 3000 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)); 3001 3002 DECLARE_UVERBS_NAMED_METHOD( 3003 MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC, 3004 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE, 3005 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3006 UVERBS_ACCESS_NEW, 3007 UA_MANDATORY), 3008 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 3009 enum mlx5_ib_uapi_devx_create_event_channel_flags, 3010 UA_MANDATORY)); 3011 3012 DECLARE_UVERBS_NAMED_OBJECT( 3013 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3014 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_event_file), 3015 devx_async_event_destroy_uobj, 3016 &devx_async_event_fops, "[devx_async_event]", 3017 O_RDONLY), 3018 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)); 3019 3020 static bool devx_is_supported(struct ib_device *device) 3021 { 3022 struct mlx5_ib_dev *dev = to_mdev(device); 3023 3024 return MLX5_CAP_GEN(dev->mdev, log_max_uctx); 3025 } 3026 3027 const struct uapi_definition mlx5_ib_devx_defs[] = { 3028 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3029 MLX5_IB_OBJECT_DEVX, 3030 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3031 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3032 MLX5_IB_OBJECT_DEVX_OBJ, 3033 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3034 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3035 MLX5_IB_OBJECT_DEVX_UMEM, 3036 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3037 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3038 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3039 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3040 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3041 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3042 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3043 {}, 3044 }; 3045