1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kref.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/ib_cache.h> 37 #include "mlx5_ib.h" 38 #include "srq.h" 39 #include "qp.h" 40 41 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe) 42 { 43 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 44 45 ibcq->comp_handler(ibcq, ibcq->cq_context); 46 } 47 48 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) 49 { 50 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 51 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 52 struct ib_cq *ibcq = &cq->ibcq; 53 struct ib_event event; 54 55 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 56 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 57 type, mcq->cqn); 58 return; 59 } 60 61 if (ibcq->event_handler) { 62 event.device = &dev->ib_dev; 63 event.event = IB_EVENT_CQ_ERR; 64 event.element.cq = ibcq; 65 ibcq->event_handler(&event, ibcq->cq_context); 66 } 67 } 68 69 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 70 { 71 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); 72 } 73 74 static u8 sw_ownership_bit(int n, int nent) 75 { 76 return (n & nent) ? 1 : 0; 77 } 78 79 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 80 { 81 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 82 struct mlx5_cqe64 *cqe64; 83 84 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 85 86 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && 87 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 88 return cqe; 89 } else { 90 return NULL; 91 } 92 } 93 94 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 95 { 96 return get_sw_cqe(cq, cq->mcq.cons_index); 97 } 98 99 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 100 { 101 switch (wq->wr_data[idx]) { 102 case MLX5_IB_WR_UMR: 103 return 0; 104 105 case IB_WR_LOCAL_INV: 106 return IB_WC_LOCAL_INV; 107 108 case IB_WR_REG_MR: 109 return IB_WC_REG_MR; 110 111 default: 112 pr_warn("unknown completion status\n"); 113 return 0; 114 } 115 } 116 117 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 118 struct mlx5_ib_wq *wq, int idx) 119 { 120 wc->wc_flags = 0; 121 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 122 case MLX5_OPCODE_RDMA_WRITE_IMM: 123 wc->wc_flags |= IB_WC_WITH_IMM; 124 fallthrough; 125 case MLX5_OPCODE_RDMA_WRITE: 126 wc->opcode = IB_WC_RDMA_WRITE; 127 break; 128 case MLX5_OPCODE_SEND_IMM: 129 wc->wc_flags |= IB_WC_WITH_IMM; 130 fallthrough; 131 case MLX5_OPCODE_SEND: 132 case MLX5_OPCODE_SEND_INVAL: 133 wc->opcode = IB_WC_SEND; 134 break; 135 case MLX5_OPCODE_RDMA_READ: 136 wc->opcode = IB_WC_RDMA_READ; 137 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 138 break; 139 case MLX5_OPCODE_ATOMIC_CS: 140 wc->opcode = IB_WC_COMP_SWAP; 141 wc->byte_len = 8; 142 break; 143 case MLX5_OPCODE_ATOMIC_FA: 144 wc->opcode = IB_WC_FETCH_ADD; 145 wc->byte_len = 8; 146 break; 147 case MLX5_OPCODE_ATOMIC_MASKED_CS: 148 wc->opcode = IB_WC_MASKED_COMP_SWAP; 149 wc->byte_len = 8; 150 break; 151 case MLX5_OPCODE_ATOMIC_MASKED_FA: 152 wc->opcode = IB_WC_MASKED_FETCH_ADD; 153 wc->byte_len = 8; 154 break; 155 case MLX5_OPCODE_UMR: 156 wc->opcode = get_umr_comp(wq, idx); 157 break; 158 } 159 } 160 161 enum { 162 MLX5_GRH_IN_BUFFER = 1, 163 MLX5_GRH_IN_CQE = 2, 164 }; 165 166 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 167 struct mlx5_ib_qp *qp) 168 { 169 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 170 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 171 struct mlx5_ib_srq *srq = NULL; 172 struct mlx5_ib_wq *wq; 173 u16 wqe_ctr; 174 u8 roce_packet_type; 175 bool vlan_present; 176 u8 g; 177 178 if (qp->ibqp.srq || qp->ibqp.xrcd) { 179 struct mlx5_core_srq *msrq = NULL; 180 181 if (qp->ibqp.xrcd) { 182 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn)); 183 if (msrq) 184 srq = to_mibsrq(msrq); 185 } else { 186 srq = to_msrq(qp->ibqp.srq); 187 } 188 if (srq) { 189 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 190 wc->wr_id = srq->wrid[wqe_ctr]; 191 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 192 if (msrq) 193 mlx5_core_res_put(&msrq->common); 194 } 195 } else { 196 wq = &qp->rq; 197 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 198 ++wq->tail; 199 } 200 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 201 202 switch (get_cqe_opcode(cqe)) { 203 case MLX5_CQE_RESP_WR_IMM: 204 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 205 wc->wc_flags = IB_WC_WITH_IMM; 206 wc->ex.imm_data = cqe->immediate; 207 break; 208 case MLX5_CQE_RESP_SEND: 209 wc->opcode = IB_WC_RECV; 210 wc->wc_flags = IB_WC_IP_CSUM_OK; 211 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 212 (cqe->hds_ip_ext & CQE_L4_OK)))) 213 wc->wc_flags = 0; 214 break; 215 case MLX5_CQE_RESP_SEND_IMM: 216 wc->opcode = IB_WC_RECV; 217 wc->wc_flags = IB_WC_WITH_IMM; 218 wc->ex.imm_data = cqe->immediate; 219 break; 220 case MLX5_CQE_RESP_SEND_INV: 221 wc->opcode = IB_WC_RECV; 222 wc->wc_flags = IB_WC_WITH_INVALIDATE; 223 wc->ex.invalidate_rkey = be32_to_cpu(cqe->inval_rkey); 224 break; 225 } 226 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 227 wc->dlid_path_bits = cqe->ml_path; 228 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 229 wc->wc_flags |= g ? IB_WC_GRH : 0; 230 if (is_qp1(qp->type)) { 231 u16 pkey = be32_to_cpu(cqe->pkey) & 0xffff; 232 233 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 234 &wc->pkey_index); 235 } else { 236 wc->pkey_index = 0; 237 } 238 239 if (ll != IB_LINK_LAYER_ETHERNET) { 240 wc->slid = be16_to_cpu(cqe->slid); 241 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 242 return; 243 } 244 245 wc->slid = 0; 246 vlan_present = cqe->l4_l3_hdr_type & 0x1; 247 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 248 if (vlan_present) { 249 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 250 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 251 wc->wc_flags |= IB_WC_WITH_VLAN; 252 } else { 253 wc->sl = 0; 254 } 255 256 switch (roce_packet_type) { 257 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 258 wc->network_hdr_type = RDMA_NETWORK_ROCE_V1; 259 break; 260 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 261 wc->network_hdr_type = RDMA_NETWORK_IPV6; 262 break; 263 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 264 wc->network_hdr_type = RDMA_NETWORK_IPV4; 265 break; 266 } 267 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 268 } 269 270 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 271 { 272 mlx5_ib_warn(dev, "dump error cqe\n"); 273 mlx5_dump_err_cqe(dev->mdev, cqe); 274 } 275 276 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 277 struct mlx5_err_cqe *cqe, 278 struct ib_wc *wc) 279 { 280 int dump = 1; 281 282 switch (cqe->syndrome) { 283 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 284 wc->status = IB_WC_LOC_LEN_ERR; 285 break; 286 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 287 wc->status = IB_WC_LOC_QP_OP_ERR; 288 break; 289 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 290 wc->status = IB_WC_LOC_PROT_ERR; 291 break; 292 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 293 dump = 0; 294 wc->status = IB_WC_WR_FLUSH_ERR; 295 break; 296 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 297 wc->status = IB_WC_MW_BIND_ERR; 298 break; 299 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 300 wc->status = IB_WC_BAD_RESP_ERR; 301 break; 302 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 303 wc->status = IB_WC_LOC_ACCESS_ERR; 304 break; 305 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 306 wc->status = IB_WC_REM_INV_REQ_ERR; 307 break; 308 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 309 wc->status = IB_WC_REM_ACCESS_ERR; 310 break; 311 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 312 wc->status = IB_WC_REM_OP_ERR; 313 break; 314 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 315 wc->status = IB_WC_RETRY_EXC_ERR; 316 dump = 0; 317 break; 318 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 319 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 320 dump = 0; 321 break; 322 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 323 wc->status = IB_WC_REM_ABORT_ERR; 324 break; 325 default: 326 wc->status = IB_WC_GENERAL_ERR; 327 break; 328 } 329 330 wc->vendor_err = cqe->vendor_err_synd; 331 if (dump) { 332 mlx5_ib_warn(dev, "WC error: %d, Message: %s\n", wc->status, 333 ib_wc_status_msg(wc->status)); 334 dump_cqe(dev, cqe); 335 } 336 } 337 338 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 339 u16 tail, u16 head) 340 { 341 u16 idx; 342 343 do { 344 idx = tail & (qp->sq.wqe_cnt - 1); 345 if (idx == head) 346 break; 347 348 tail = qp->sq.w_list[idx].next; 349 } while (1); 350 tail = qp->sq.w_list[idx].next; 351 qp->sq.last_poll = tail; 352 } 353 354 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 355 { 356 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf); 357 } 358 359 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 360 struct ib_sig_err *item) 361 { 362 u16 syndrome = be16_to_cpu(cqe->syndrome); 363 364 #define GUARD_ERR (1 << 13) 365 #define APPTAG_ERR (1 << 12) 366 #define REFTAG_ERR (1 << 11) 367 368 if (syndrome & GUARD_ERR) { 369 item->err_type = IB_SIG_BAD_GUARD; 370 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 371 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 372 } else 373 if (syndrome & REFTAG_ERR) { 374 item->err_type = IB_SIG_BAD_REFTAG; 375 item->expected = be32_to_cpu(cqe->expected_reftag); 376 item->actual = be32_to_cpu(cqe->actual_reftag); 377 } else 378 if (syndrome & APPTAG_ERR) { 379 item->err_type = IB_SIG_BAD_APPTAG; 380 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 381 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 382 } else { 383 pr_err("Got signature completion error with bad syndrome %04x\n", 384 syndrome); 385 } 386 387 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 388 item->key = be32_to_cpu(cqe->mkey); 389 } 390 391 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc, 392 int *npolled, bool is_send) 393 { 394 struct mlx5_ib_wq *wq; 395 unsigned int cur; 396 int np; 397 int i; 398 399 wq = (is_send) ? &qp->sq : &qp->rq; 400 cur = wq->head - wq->tail; 401 np = *npolled; 402 403 if (cur == 0) 404 return; 405 406 for (i = 0; i < cur && np < num_entries; i++) { 407 unsigned int idx; 408 409 idx = (is_send) ? wq->last_poll : wq->tail; 410 idx &= (wq->wqe_cnt - 1); 411 wc->wr_id = wq->wrid[idx]; 412 wc->status = IB_WC_WR_FLUSH_ERR; 413 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 414 wq->tail++; 415 if (is_send) 416 wq->last_poll = wq->w_list[idx].next; 417 np++; 418 wc->qp = &qp->ibqp; 419 wc++; 420 } 421 *npolled = np; 422 } 423 424 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 425 struct ib_wc *wc, int *npolled) 426 { 427 struct mlx5_ib_qp *qp; 428 429 *npolled = 0; 430 /* Find uncompleted WQEs belonging to that cq and return mmics ones */ 431 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 432 sw_comp(qp, num_entries, wc + *npolled, npolled, true); 433 if (*npolled >= num_entries) 434 return; 435 } 436 437 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 438 sw_comp(qp, num_entries, wc + *npolled, npolled, false); 439 if (*npolled >= num_entries) 440 return; 441 } 442 } 443 444 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 445 struct mlx5_ib_qp **cur_qp, 446 struct ib_wc *wc) 447 { 448 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 449 struct mlx5_err_cqe *err_cqe; 450 struct mlx5_cqe64 *cqe64; 451 struct mlx5_core_qp *mqp; 452 struct mlx5_ib_wq *wq; 453 uint8_t opcode; 454 uint32_t qpn; 455 u16 wqe_ctr; 456 void *cqe; 457 int idx; 458 459 repoll: 460 cqe = next_cqe_sw(cq); 461 if (!cqe) 462 return -EAGAIN; 463 464 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 465 466 ++cq->mcq.cons_index; 467 468 /* Make sure we read CQ entry contents after we've checked the 469 * ownership bit. 470 */ 471 rmb(); 472 473 opcode = get_cqe_opcode(cqe64); 474 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 475 if (likely(cq->resize_buf)) { 476 free_cq_buf(dev, &cq->buf); 477 cq->buf = *cq->resize_buf; 478 kfree(cq->resize_buf); 479 cq->resize_buf = NULL; 480 goto repoll; 481 } else { 482 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 483 } 484 } 485 486 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 487 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 488 /* We do not have to take the QP table lock here, 489 * because CQs will be locked while QPs are removed 490 * from the table. 491 */ 492 mqp = radix_tree_lookup(&dev->qp_table.tree, qpn); 493 *cur_qp = to_mibqp(mqp); 494 } 495 496 wc->qp = &(*cur_qp)->ibqp; 497 switch (opcode) { 498 case MLX5_CQE_REQ: 499 wq = &(*cur_qp)->sq; 500 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 501 idx = wqe_ctr & (wq->wqe_cnt - 1); 502 handle_good_req(wc, cqe64, wq, idx); 503 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx); 504 wc->wr_id = wq->wrid[idx]; 505 wq->tail = wq->wqe_head[idx] + 1; 506 wc->status = IB_WC_SUCCESS; 507 break; 508 case MLX5_CQE_RESP_WR_IMM: 509 case MLX5_CQE_RESP_SEND: 510 case MLX5_CQE_RESP_SEND_IMM: 511 case MLX5_CQE_RESP_SEND_INV: 512 handle_responder(wc, cqe64, *cur_qp); 513 wc->status = IB_WC_SUCCESS; 514 break; 515 case MLX5_CQE_RESIZE_CQ: 516 break; 517 case MLX5_CQE_REQ_ERR: 518 case MLX5_CQE_RESP_ERR: 519 err_cqe = (struct mlx5_err_cqe *)cqe64; 520 mlx5_handle_error_cqe(dev, err_cqe, wc); 521 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 522 opcode == MLX5_CQE_REQ_ERR ? 523 "Requestor" : "Responder", cq->mcq.cqn); 524 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 525 err_cqe->syndrome, err_cqe->vendor_err_synd); 526 if (opcode == MLX5_CQE_REQ_ERR) { 527 wq = &(*cur_qp)->sq; 528 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 529 idx = wqe_ctr & (wq->wqe_cnt - 1); 530 wc->wr_id = wq->wrid[idx]; 531 wq->tail = wq->wqe_head[idx] + 1; 532 } else { 533 struct mlx5_ib_srq *srq; 534 535 if ((*cur_qp)->ibqp.srq) { 536 srq = to_msrq((*cur_qp)->ibqp.srq); 537 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 538 wc->wr_id = srq->wrid[wqe_ctr]; 539 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 540 } else { 541 wq = &(*cur_qp)->rq; 542 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 543 ++wq->tail; 544 } 545 } 546 break; 547 case MLX5_CQE_SIG_ERR: { 548 struct mlx5_sig_err_cqe *sig_err_cqe = 549 (struct mlx5_sig_err_cqe *)cqe64; 550 struct mlx5_core_sig_ctx *sig; 551 552 xa_lock(&dev->sig_mrs); 553 sig = xa_load(&dev->sig_mrs, 554 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 555 get_sig_err_item(sig_err_cqe, &sig->err_item); 556 sig->sig_err_exists = true; 557 sig->sigerr_count++; 558 559 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 560 cq->mcq.cqn, sig->err_item.key, 561 sig->err_item.err_type, 562 sig->err_item.sig_err_offset, 563 sig->err_item.expected, 564 sig->err_item.actual); 565 566 xa_unlock(&dev->sig_mrs); 567 goto repoll; 568 } 569 } 570 571 return 0; 572 } 573 574 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 575 struct ib_wc *wc, bool is_fatal_err) 576 { 577 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 578 struct mlx5_ib_wc *soft_wc, *next; 579 int npolled = 0; 580 581 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 582 if (npolled >= num_entries) 583 break; 584 585 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 586 cq->mcq.cqn); 587 588 if (unlikely(is_fatal_err)) { 589 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR; 590 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 591 } 592 wc[npolled++] = soft_wc->wc; 593 list_del(&soft_wc->list); 594 kfree(soft_wc); 595 } 596 597 return npolled; 598 } 599 600 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 601 { 602 struct mlx5_ib_cq *cq = to_mcq(ibcq); 603 struct mlx5_ib_qp *cur_qp = NULL; 604 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 605 struct mlx5_core_dev *mdev = dev->mdev; 606 unsigned long flags; 607 int soft_polled = 0; 608 int npolled; 609 610 spin_lock_irqsave(&cq->lock, flags); 611 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 612 /* make sure no soft wqe's are waiting */ 613 if (unlikely(!list_empty(&cq->wc_list))) 614 soft_polled = poll_soft_wc(cq, num_entries, wc, true); 615 616 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled, 617 wc + soft_polled, &npolled); 618 goto out; 619 } 620 621 if (unlikely(!list_empty(&cq->wc_list))) 622 soft_polled = poll_soft_wc(cq, num_entries, wc, false); 623 624 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 625 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 626 break; 627 } 628 629 if (npolled) 630 mlx5_cq_set_ci(&cq->mcq); 631 out: 632 spin_unlock_irqrestore(&cq->lock, flags); 633 634 return soft_polled + npolled; 635 } 636 637 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 638 { 639 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 640 struct mlx5_ib_cq *cq = to_mcq(ibcq); 641 void __iomem *uar_page = mdev->priv.uar->map; 642 unsigned long irq_flags; 643 int ret = 0; 644 645 spin_lock_irqsave(&cq->lock, irq_flags); 646 if (cq->notify_flags != IB_CQ_NEXT_COMP) 647 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 648 649 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 650 ret = 1; 651 spin_unlock_irqrestore(&cq->lock, irq_flags); 652 653 mlx5_cq_arm(&cq->mcq, 654 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 655 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 656 uar_page, to_mcq(ibcq)->mcq.cons_index); 657 658 return ret; 659 } 660 661 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, 662 struct mlx5_ib_cq_buf *buf, 663 int nent, 664 int cqe_size) 665 { 666 struct mlx5_frag_buf *frag_buf = &buf->frag_buf; 667 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); 668 u8 log_wq_sz = ilog2(cqe_size); 669 int err; 670 671 err = mlx5_frag_buf_alloc_node(dev->mdev, 672 nent * cqe_size, 673 frag_buf, 674 dev->mdev->priv.numa_node); 675 if (err) 676 return err; 677 678 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); 679 680 buf->cqe_size = cqe_size; 681 buf->nent = nent; 682 683 return 0; 684 } 685 686 enum { 687 MLX5_CQE_RES_FORMAT_HASH = 0, 688 MLX5_CQE_RES_FORMAT_CSUM = 1, 689 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3, 690 }; 691 692 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format) 693 { 694 switch (format) { 695 case MLX5_IB_CQE_RES_FORMAT_HASH: 696 return MLX5_CQE_RES_FORMAT_HASH; 697 case MLX5_IB_CQE_RES_FORMAT_CSUM: 698 return MLX5_CQE_RES_FORMAT_CSUM; 699 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX: 700 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 701 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX; 702 return -EOPNOTSUPP; 703 default: 704 return -EINVAL; 705 } 706 } 707 708 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 709 struct mlx5_ib_cq *cq, int entries, u32 **cqb, 710 int *cqe_size, int *index, int *inlen) 711 { 712 struct mlx5_ib_create_cq ucmd = {}; 713 unsigned long page_size; 714 unsigned int page_offset_quantized; 715 size_t ucmdlen; 716 __be64 *pas; 717 int ncont; 718 void *cqc; 719 int err; 720 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 721 udata, struct mlx5_ib_ucontext, ibucontext); 722 723 ucmdlen = min(udata->inlen, sizeof(ucmd)); 724 if (ucmdlen < offsetof(struct mlx5_ib_create_cq, flags)) 725 return -EINVAL; 726 727 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 728 return -EFAULT; 729 730 if ((ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD | 731 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX | 732 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS))) 733 return -EINVAL; 734 735 if ((ucmd.cqe_size != 64 && ucmd.cqe_size != 128) || 736 ucmd.reserved0 || ucmd.reserved1) 737 return -EINVAL; 738 739 *cqe_size = ucmd.cqe_size; 740 741 cq->buf.umem = 742 ib_umem_get(&dev->ib_dev, ucmd.buf_addr, 743 entries * ucmd.cqe_size, IB_ACCESS_LOCAL_WRITE); 744 if (IS_ERR(cq->buf.umem)) { 745 err = PTR_ERR(cq->buf.umem); 746 return err; 747 } 748 749 page_size = mlx5_umem_find_best_cq_quantized_pgoff( 750 cq->buf.umem, cqc, log_page_size, MLX5_ADAPTER_PAGE_SHIFT, 751 page_offset, 64, &page_offset_quantized); 752 if (!page_size) { 753 err = -EINVAL; 754 goto err_umem; 755 } 756 757 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &cq->db); 758 if (err) 759 goto err_umem; 760 761 ncont = ib_umem_num_dma_blocks(cq->buf.umem, page_size); 762 mlx5_ib_dbg( 763 dev, 764 "addr 0x%llx, size %u, npages %zu, page_size %lu, ncont %d\n", 765 ucmd.buf_addr, entries * ucmd.cqe_size, 766 ib_umem_num_pages(cq->buf.umem), page_size, ncont); 767 768 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 769 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 770 *cqb = kvzalloc(*inlen, GFP_KERNEL); 771 if (!*cqb) { 772 err = -ENOMEM; 773 goto err_db; 774 } 775 776 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 777 mlx5_ib_populate_pas(cq->buf.umem, page_size, pas, 0); 778 779 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 780 MLX5_SET(cqc, cqc, log_page_size, 781 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 782 MLX5_SET(cqc, cqc, page_offset, page_offset_quantized); 783 784 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) { 785 *index = ucmd.uar_page_index; 786 } else if (context->bfregi.lib_uar_dyn) { 787 err = -EINVAL; 788 goto err_cqb; 789 } else { 790 *index = context->bfregi.sys_pages[0]; 791 } 792 793 if (ucmd.cqe_comp_en == 1) { 794 int mini_cqe_format; 795 796 if (!((*cqe_size == 128 && 797 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || 798 (*cqe_size == 64 && 799 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { 800 err = -EOPNOTSUPP; 801 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 802 *cqe_size); 803 goto err_cqb; 804 } 805 806 mini_cqe_format = 807 mini_cqe_res_format_to_hw(dev, 808 ucmd.cqe_comp_res_format); 809 if (mini_cqe_format < 0) { 810 err = mini_cqe_format; 811 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n", 812 ucmd.cqe_comp_res_format, err); 813 goto err_cqb; 814 } 815 816 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 817 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); 818 } 819 820 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) { 821 if (*cqe_size != 128 || 822 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { 823 err = -EOPNOTSUPP; 824 mlx5_ib_warn(dev, 825 "CQE padding is not supported for CQE size of %dB!\n", 826 *cqe_size); 827 goto err_cqb; 828 } 829 830 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD; 831 } 832 833 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS) 834 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS; 835 836 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid); 837 return 0; 838 839 err_cqb: 840 kvfree(*cqb); 841 842 err_db: 843 mlx5_ib_db_unmap_user(context, &cq->db); 844 845 err_umem: 846 ib_umem_release(cq->buf.umem); 847 return err; 848 } 849 850 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata) 851 { 852 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 853 udata, struct mlx5_ib_ucontext, ibucontext); 854 855 mlx5_ib_db_unmap_user(context, &cq->db); 856 ib_umem_release(cq->buf.umem); 857 } 858 859 static void init_cq_frag_buf(struct mlx5_ib_cq_buf *buf) 860 { 861 int i; 862 void *cqe; 863 struct mlx5_cqe64 *cqe64; 864 865 for (i = 0; i < buf->nent; i++) { 866 cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i); 867 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 868 cqe64->op_own = MLX5_CQE_INVALID << 4; 869 } 870 } 871 872 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 873 int entries, int cqe_size, 874 u32 **cqb, int *index, int *inlen) 875 { 876 __be64 *pas; 877 void *cqc; 878 int err; 879 880 err = mlx5_db_alloc(dev->mdev, &cq->db); 881 if (err) 882 return err; 883 884 cq->mcq.set_ci_db = cq->db.db; 885 cq->mcq.arm_db = cq->db.db + 1; 886 cq->mcq.cqe_sz = cqe_size; 887 888 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); 889 if (err) 890 goto err_db; 891 892 init_cq_frag_buf(&cq->buf); 893 894 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 895 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * 896 cq->buf.frag_buf.npages; 897 *cqb = kvzalloc(*inlen, GFP_KERNEL); 898 if (!*cqb) { 899 err = -ENOMEM; 900 goto err_buf; 901 } 902 903 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 904 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); 905 906 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 907 MLX5_SET(cqc, cqc, log_page_size, 908 cq->buf.frag_buf.page_shift - 909 MLX5_ADAPTER_PAGE_SHIFT); 910 911 *index = dev->mdev->priv.uar->index; 912 913 return 0; 914 915 err_buf: 916 free_cq_buf(dev, &cq->buf); 917 918 err_db: 919 mlx5_db_free(dev->mdev, &cq->db); 920 return err; 921 } 922 923 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 924 { 925 free_cq_buf(dev, &cq->buf); 926 mlx5_db_free(dev->mdev, &cq->db); 927 } 928 929 static void notify_soft_wc_handler(struct work_struct *work) 930 { 931 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 932 notify_work); 933 934 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 935 } 936 937 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 938 struct ib_udata *udata) 939 { 940 struct ib_device *ibdev = ibcq->device; 941 int entries = attr->cqe; 942 int vector = attr->comp_vector; 943 struct mlx5_ib_dev *dev = to_mdev(ibdev); 944 struct mlx5_ib_cq *cq = to_mcq(ibcq); 945 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 946 int index; 947 int inlen; 948 u32 *cqb = NULL; 949 void *cqc; 950 int cqe_size; 951 int eqn; 952 int err; 953 954 if (entries < 0 || 955 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 956 return -EINVAL; 957 958 if (check_cq_create_flags(attr->flags)) 959 return -EOPNOTSUPP; 960 961 entries = roundup_pow_of_two(entries + 1); 962 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 963 return -EINVAL; 964 965 cq->ibcq.cqe = entries - 1; 966 mutex_init(&cq->resize_mutex); 967 spin_lock_init(&cq->lock); 968 cq->resize_buf = NULL; 969 cq->resize_umem = NULL; 970 cq->create_flags = attr->flags; 971 INIT_LIST_HEAD(&cq->list_send_qp); 972 INIT_LIST_HEAD(&cq->list_recv_qp); 973 974 if (udata) { 975 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size, 976 &index, &inlen); 977 if (err) 978 return err; 979 } else { 980 cqe_size = cache_line_size() == 128 ? 128 : 64; 981 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 982 &index, &inlen); 983 if (err) 984 return err; 985 986 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 987 } 988 989 err = mlx5_vector2eqn(dev->mdev, vector, &eqn); 990 if (err) 991 goto err_cqb; 992 993 cq->cqe_size = cqe_size; 994 995 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 996 MLX5_SET(cqc, cqc, cqe_sz, 997 cqe_sz_to_mlx_sz(cqe_size, 998 cq->private_flags & 999 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1000 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1001 MLX5_SET(cqc, cqc, uar_page, index); 1002 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); 1003 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 1004 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) 1005 MLX5_SET(cqc, cqc, oi, 1); 1006 1007 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out)); 1008 if (err) 1009 goto err_cqb; 1010 1011 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 1012 if (udata) 1013 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; 1014 else 1015 cq->mcq.comp = mlx5_ib_cq_comp; 1016 cq->mcq.event = mlx5_ib_cq_event; 1017 1018 INIT_LIST_HEAD(&cq->wc_list); 1019 1020 if (udata) 1021 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 1022 err = -EFAULT; 1023 goto err_cmd; 1024 } 1025 1026 1027 kvfree(cqb); 1028 return 0; 1029 1030 err_cmd: 1031 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 1032 1033 err_cqb: 1034 kvfree(cqb); 1035 if (udata) 1036 destroy_cq_user(cq, udata); 1037 else 1038 destroy_cq_kernel(dev, cq); 1039 return err; 1040 } 1041 1042 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 1043 { 1044 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1045 struct mlx5_ib_cq *mcq = to_mcq(cq); 1046 int ret; 1047 1048 ret = mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 1049 if (ret) 1050 return ret; 1051 1052 if (udata) 1053 destroy_cq_user(mcq, udata); 1054 else 1055 destroy_cq_kernel(dev, mcq); 1056 return 0; 1057 } 1058 1059 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1060 { 1061 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1062 } 1063 1064 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1065 { 1066 struct mlx5_cqe64 *cqe64, *dest64; 1067 void *cqe, *dest; 1068 u32 prod_index; 1069 int nfreed = 0; 1070 u8 owner_bit; 1071 1072 if (!cq) 1073 return; 1074 1075 /* First we need to find the current producer index, so we 1076 * know where to start cleaning from. It doesn't matter if HW 1077 * adds new entries after this loop -- the QP we're worried 1078 * about is already in RESET, so the new entries won't come 1079 * from our QP and therefore don't need to be checked. 1080 */ 1081 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1082 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1083 break; 1084 1085 /* Now sweep backwards through the CQ, removing CQ entries 1086 * that match our QP by copying older entries on top of them. 1087 */ 1088 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1089 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1090 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1091 if (is_equal_rsn(cqe64, rsn)) { 1092 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1093 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1094 ++nfreed; 1095 } else if (nfreed) { 1096 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1097 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1098 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1099 memcpy(dest, cqe, cq->mcq.cqe_sz); 1100 dest64->op_own = owner_bit | 1101 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1102 } 1103 } 1104 1105 if (nfreed) { 1106 cq->mcq.cons_index += nfreed; 1107 /* Make sure update of buffer contents is done before 1108 * updating consumer index. 1109 */ 1110 wmb(); 1111 mlx5_cq_set_ci(&cq->mcq); 1112 } 1113 } 1114 1115 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1116 { 1117 if (!cq) 1118 return; 1119 1120 spin_lock_irq(&cq->lock); 1121 __mlx5_ib_cq_clean(cq, qpn, srq); 1122 spin_unlock_irq(&cq->lock); 1123 } 1124 1125 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1126 { 1127 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1128 struct mlx5_ib_cq *mcq = to_mcq(cq); 1129 int err; 1130 1131 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1132 return -EOPNOTSUPP; 1133 1134 if (cq_period > MLX5_MAX_CQ_PERIOD) 1135 return -EINVAL; 1136 1137 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1138 cq_period, cq_count); 1139 if (err) 1140 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1141 1142 return err; 1143 } 1144 1145 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1146 int entries, struct ib_udata *udata, 1147 int *cqe_size) 1148 { 1149 struct mlx5_ib_resize_cq ucmd; 1150 struct ib_umem *umem; 1151 int err; 1152 1153 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1154 if (err) 1155 return err; 1156 1157 if (ucmd.reserved0 || ucmd.reserved1) 1158 return -EINVAL; 1159 1160 /* check multiplication overflow */ 1161 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1162 return -EINVAL; 1163 1164 umem = ib_umem_get(&dev->ib_dev, ucmd.buf_addr, 1165 (size_t)ucmd.cqe_size * entries, 1166 IB_ACCESS_LOCAL_WRITE); 1167 if (IS_ERR(umem)) { 1168 err = PTR_ERR(umem); 1169 return err; 1170 } 1171 1172 cq->resize_umem = umem; 1173 *cqe_size = ucmd.cqe_size; 1174 1175 return 0; 1176 } 1177 1178 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1179 int entries, int cqe_size) 1180 { 1181 int err; 1182 1183 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1184 if (!cq->resize_buf) 1185 return -ENOMEM; 1186 1187 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); 1188 if (err) 1189 goto ex; 1190 1191 init_cq_frag_buf(cq->resize_buf); 1192 1193 return 0; 1194 1195 ex: 1196 kfree(cq->resize_buf); 1197 return err; 1198 } 1199 1200 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1201 { 1202 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1203 struct mlx5_cqe64 *scqe64; 1204 struct mlx5_cqe64 *dcqe64; 1205 void *start_cqe; 1206 void *scqe; 1207 void *dcqe; 1208 int ssize; 1209 int dsize; 1210 int i; 1211 u8 sw_own; 1212 1213 ssize = cq->buf.cqe_size; 1214 dsize = cq->resize_buf->cqe_size; 1215 if (ssize != dsize) { 1216 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1217 return -EINVAL; 1218 } 1219 1220 i = cq->mcq.cons_index; 1221 scqe = get_sw_cqe(cq, i); 1222 scqe64 = ssize == 64 ? scqe : scqe + 64; 1223 start_cqe = scqe; 1224 if (!scqe) { 1225 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1226 return -EINVAL; 1227 } 1228 1229 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) { 1230 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, 1231 (i + 1) & cq->resize_buf->nent); 1232 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1233 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1234 memcpy(dcqe, scqe, dsize); 1235 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1236 1237 ++i; 1238 scqe = get_sw_cqe(cq, i); 1239 scqe64 = ssize == 64 ? scqe : scqe + 64; 1240 if (!scqe) { 1241 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1242 return -EINVAL; 1243 } 1244 1245 if (scqe == start_cqe) { 1246 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1247 cq->mcq.cqn); 1248 return -ENOMEM; 1249 } 1250 } 1251 ++cq->mcq.cons_index; 1252 return 0; 1253 } 1254 1255 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1256 { 1257 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1258 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1259 void *cqc; 1260 u32 *in; 1261 int err; 1262 int npas; 1263 __be64 *pas; 1264 unsigned int page_offset_quantized = 0; 1265 unsigned int page_shift; 1266 int inlen; 1267 int cqe_size; 1268 unsigned long flags; 1269 1270 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1271 pr_info("Firmware does not support resize CQ\n"); 1272 return -ENOSYS; 1273 } 1274 1275 if (entries < 1 || 1276 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1277 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1278 entries, 1279 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1280 return -EINVAL; 1281 } 1282 1283 entries = roundup_pow_of_two(entries + 1); 1284 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1285 return -EINVAL; 1286 1287 if (entries == ibcq->cqe + 1) 1288 return 0; 1289 1290 mutex_lock(&cq->resize_mutex); 1291 if (udata) { 1292 unsigned long page_size; 1293 1294 err = resize_user(dev, cq, entries, udata, &cqe_size); 1295 if (err) 1296 goto ex; 1297 1298 page_size = mlx5_umem_find_best_cq_quantized_pgoff( 1299 cq->resize_umem, cqc, log_page_size, 1300 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1301 &page_offset_quantized); 1302 if (!page_size) { 1303 err = -EINVAL; 1304 goto ex_resize; 1305 } 1306 npas = ib_umem_num_dma_blocks(cq->resize_umem, page_size); 1307 page_shift = order_base_2(page_size); 1308 } else { 1309 struct mlx5_frag_buf *frag_buf; 1310 1311 cqe_size = 64; 1312 err = resize_kernel(dev, cq, entries, cqe_size); 1313 if (err) 1314 goto ex; 1315 frag_buf = &cq->resize_buf->frag_buf; 1316 npas = frag_buf->npages; 1317 page_shift = frag_buf->page_shift; 1318 } 1319 1320 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1321 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1322 1323 in = kvzalloc(inlen, GFP_KERNEL); 1324 if (!in) { 1325 err = -ENOMEM; 1326 goto ex_resize; 1327 } 1328 1329 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1330 if (udata) 1331 mlx5_ib_populate_pas(cq->resize_umem, 1UL << page_shift, pas, 1332 0); 1333 else 1334 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas); 1335 1336 MLX5_SET(modify_cq_in, in, 1337 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1338 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1339 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1340 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1341 1342 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1343 1344 MLX5_SET(cqc, cqc, log_page_size, 1345 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1346 MLX5_SET(cqc, cqc, page_offset, page_offset_quantized); 1347 MLX5_SET(cqc, cqc, cqe_sz, 1348 cqe_sz_to_mlx_sz(cqe_size, 1349 cq->private_flags & 1350 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1351 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1352 1353 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1354 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1355 1356 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1357 if (err) 1358 goto ex_alloc; 1359 1360 if (udata) { 1361 cq->ibcq.cqe = entries - 1; 1362 ib_umem_release(cq->buf.umem); 1363 cq->buf.umem = cq->resize_umem; 1364 cq->resize_umem = NULL; 1365 } else { 1366 struct mlx5_ib_cq_buf tbuf; 1367 int resized = 0; 1368 1369 spin_lock_irqsave(&cq->lock, flags); 1370 if (cq->resize_buf) { 1371 err = copy_resize_cqes(cq); 1372 if (!err) { 1373 tbuf = cq->buf; 1374 cq->buf = *cq->resize_buf; 1375 kfree(cq->resize_buf); 1376 cq->resize_buf = NULL; 1377 resized = 1; 1378 } 1379 } 1380 cq->ibcq.cqe = entries - 1; 1381 spin_unlock_irqrestore(&cq->lock, flags); 1382 if (resized) 1383 free_cq_buf(dev, &tbuf); 1384 } 1385 mutex_unlock(&cq->resize_mutex); 1386 1387 kvfree(in); 1388 return 0; 1389 1390 ex_alloc: 1391 kvfree(in); 1392 1393 ex_resize: 1394 ib_umem_release(cq->resize_umem); 1395 if (!udata) { 1396 free_cq_buf(dev, cq->resize_buf); 1397 cq->resize_buf = NULL; 1398 } 1399 ex: 1400 mutex_unlock(&cq->resize_mutex); 1401 return err; 1402 } 1403 1404 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq) 1405 { 1406 struct mlx5_ib_cq *cq; 1407 1408 if (!ibcq) 1409 return 128; 1410 1411 cq = to_mcq(ibcq); 1412 return cq->cqe_size; 1413 } 1414 1415 /* Called from atomic context */ 1416 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1417 { 1418 struct mlx5_ib_wc *soft_wc; 1419 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1420 unsigned long flags; 1421 1422 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1423 if (!soft_wc) 1424 return -ENOMEM; 1425 1426 soft_wc->wc = *wc; 1427 spin_lock_irqsave(&cq->lock, flags); 1428 list_add_tail(&soft_wc->list, &cq->wc_list); 1429 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1430 wc->status != IB_WC_SUCCESS) { 1431 cq->notify_flags = 0; 1432 schedule_work(&cq->notify_work); 1433 } 1434 spin_unlock_irqrestore(&cq->lock, flags); 1435 1436 return 0; 1437 } 1438