1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kref.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/ib_cache.h> 37 #include "mlx5_ib.h" 38 39 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq) 40 { 41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 42 43 ibcq->comp_handler(ibcq, ibcq->cq_context); 44 } 45 46 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) 47 { 48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 50 struct ib_cq *ibcq = &cq->ibcq; 51 struct ib_event event; 52 53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 55 type, mcq->cqn); 56 return; 57 } 58 59 if (ibcq->event_handler) { 60 event.device = &dev->ib_dev; 61 event.event = IB_EVENT_CQ_ERR; 62 event.element.cq = ibcq; 63 ibcq->event_handler(&event, ibcq->cq_context); 64 } 65 } 66 67 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 68 { 69 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); 70 } 71 72 static u8 sw_ownership_bit(int n, int nent) 73 { 74 return (n & nent) ? 1 : 0; 75 } 76 77 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 78 { 79 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 80 struct mlx5_cqe64 *cqe64; 81 82 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 83 84 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) && 85 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 86 return cqe; 87 } else { 88 return NULL; 89 } 90 } 91 92 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 93 { 94 return get_sw_cqe(cq, cq->mcq.cons_index); 95 } 96 97 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 98 { 99 switch (wq->wr_data[idx]) { 100 case MLX5_IB_WR_UMR: 101 return 0; 102 103 case IB_WR_LOCAL_INV: 104 return IB_WC_LOCAL_INV; 105 106 case IB_WR_REG_MR: 107 return IB_WC_REG_MR; 108 109 default: 110 pr_warn("unknown completion status\n"); 111 return 0; 112 } 113 } 114 115 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 116 struct mlx5_ib_wq *wq, int idx) 117 { 118 wc->wc_flags = 0; 119 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 120 case MLX5_OPCODE_RDMA_WRITE_IMM: 121 wc->wc_flags |= IB_WC_WITH_IMM; 122 /* fall through */ 123 case MLX5_OPCODE_RDMA_WRITE: 124 wc->opcode = IB_WC_RDMA_WRITE; 125 break; 126 case MLX5_OPCODE_SEND_IMM: 127 wc->wc_flags |= IB_WC_WITH_IMM; 128 /* fall through */ 129 case MLX5_OPCODE_SEND: 130 case MLX5_OPCODE_SEND_INVAL: 131 wc->opcode = IB_WC_SEND; 132 break; 133 case MLX5_OPCODE_RDMA_READ: 134 wc->opcode = IB_WC_RDMA_READ; 135 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 136 break; 137 case MLX5_OPCODE_ATOMIC_CS: 138 wc->opcode = IB_WC_COMP_SWAP; 139 wc->byte_len = 8; 140 break; 141 case MLX5_OPCODE_ATOMIC_FA: 142 wc->opcode = IB_WC_FETCH_ADD; 143 wc->byte_len = 8; 144 break; 145 case MLX5_OPCODE_ATOMIC_MASKED_CS: 146 wc->opcode = IB_WC_MASKED_COMP_SWAP; 147 wc->byte_len = 8; 148 break; 149 case MLX5_OPCODE_ATOMIC_MASKED_FA: 150 wc->opcode = IB_WC_MASKED_FETCH_ADD; 151 wc->byte_len = 8; 152 break; 153 case MLX5_OPCODE_UMR: 154 wc->opcode = get_umr_comp(wq, idx); 155 break; 156 } 157 } 158 159 enum { 160 MLX5_GRH_IN_BUFFER = 1, 161 MLX5_GRH_IN_CQE = 2, 162 }; 163 164 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 165 struct mlx5_ib_qp *qp) 166 { 167 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 168 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 169 struct mlx5_ib_srq *srq; 170 struct mlx5_ib_wq *wq; 171 u16 wqe_ctr; 172 u8 roce_packet_type; 173 bool vlan_present; 174 u8 g; 175 176 if (qp->ibqp.srq || qp->ibqp.xrcd) { 177 struct mlx5_core_srq *msrq = NULL; 178 179 if (qp->ibqp.xrcd) { 180 msrq = mlx5_core_get_srq(dev->mdev, 181 be32_to_cpu(cqe->srqn)); 182 srq = to_mibsrq(msrq); 183 } else { 184 srq = to_msrq(qp->ibqp.srq); 185 } 186 if (srq) { 187 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 188 wc->wr_id = srq->wrid[wqe_ctr]; 189 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 190 if (msrq && atomic_dec_and_test(&msrq->refcount)) 191 complete(&msrq->free); 192 } 193 } else { 194 wq = &qp->rq; 195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 196 ++wq->tail; 197 } 198 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 199 200 switch (cqe->op_own >> 4) { 201 case MLX5_CQE_RESP_WR_IMM: 202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 203 wc->wc_flags = IB_WC_WITH_IMM; 204 wc->ex.imm_data = cqe->imm_inval_pkey; 205 break; 206 case MLX5_CQE_RESP_SEND: 207 wc->opcode = IB_WC_RECV; 208 wc->wc_flags = IB_WC_IP_CSUM_OK; 209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 210 (cqe->hds_ip_ext & CQE_L4_OK)))) 211 wc->wc_flags = 0; 212 break; 213 case MLX5_CQE_RESP_SEND_IMM: 214 wc->opcode = IB_WC_RECV; 215 wc->wc_flags = IB_WC_WITH_IMM; 216 wc->ex.imm_data = cqe->imm_inval_pkey; 217 break; 218 case MLX5_CQE_RESP_SEND_INV: 219 wc->opcode = IB_WC_RECV; 220 wc->wc_flags = IB_WC_WITH_INVALIDATE; 221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey); 222 break; 223 } 224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 225 wc->dlid_path_bits = cqe->ml_path; 226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 227 wc->wc_flags |= g ? IB_WC_GRH : 0; 228 if (unlikely(is_qp1(qp->ibqp.qp_type))) { 229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff; 230 231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 232 &wc->pkey_index); 233 } else { 234 wc->pkey_index = 0; 235 } 236 237 if (ll != IB_LINK_LAYER_ETHERNET) { 238 wc->slid = be16_to_cpu(cqe->slid); 239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 240 return; 241 } 242 243 wc->slid = 0; 244 vlan_present = cqe->l4_l3_hdr_type & 0x1; 245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 246 if (vlan_present) { 247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 249 wc->wc_flags |= IB_WC_WITH_VLAN; 250 } else { 251 wc->sl = 0; 252 } 253 254 switch (roce_packet_type) { 255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 256 wc->network_hdr_type = RDMA_NETWORK_IB; 257 break; 258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 259 wc->network_hdr_type = RDMA_NETWORK_IPV6; 260 break; 261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 262 wc->network_hdr_type = RDMA_NETWORK_IPV4; 263 break; 264 } 265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 266 } 267 268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 269 { 270 mlx5_ib_warn(dev, "dump error cqe\n"); 271 mlx5_dump_err_cqe(dev->mdev, cqe); 272 } 273 274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 275 struct mlx5_err_cqe *cqe, 276 struct ib_wc *wc) 277 { 278 int dump = 1; 279 280 switch (cqe->syndrome) { 281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 282 wc->status = IB_WC_LOC_LEN_ERR; 283 break; 284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 285 wc->status = IB_WC_LOC_QP_OP_ERR; 286 break; 287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 288 wc->status = IB_WC_LOC_PROT_ERR; 289 break; 290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 291 dump = 0; 292 wc->status = IB_WC_WR_FLUSH_ERR; 293 break; 294 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 295 wc->status = IB_WC_MW_BIND_ERR; 296 break; 297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 298 wc->status = IB_WC_BAD_RESP_ERR; 299 break; 300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 301 wc->status = IB_WC_LOC_ACCESS_ERR; 302 break; 303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 304 wc->status = IB_WC_REM_INV_REQ_ERR; 305 break; 306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 307 wc->status = IB_WC_REM_ACCESS_ERR; 308 break; 309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 310 wc->status = IB_WC_REM_OP_ERR; 311 break; 312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 313 wc->status = IB_WC_RETRY_EXC_ERR; 314 dump = 0; 315 break; 316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 317 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 318 dump = 0; 319 break; 320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 321 wc->status = IB_WC_REM_ABORT_ERR; 322 break; 323 default: 324 wc->status = IB_WC_GENERAL_ERR; 325 break; 326 } 327 328 wc->vendor_err = cqe->vendor_err_synd; 329 if (dump) 330 dump_cqe(dev, cqe); 331 } 332 333 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx) 334 { 335 /* TBD: waiting decision 336 */ 337 return 0; 338 } 339 340 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx) 341 { 342 struct mlx5_wqe_data_seg *dpseg; 343 void *addr; 344 345 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) + 346 sizeof(struct mlx5_wqe_raddr_seg) + 347 sizeof(struct mlx5_wqe_atomic_seg); 348 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr); 349 return addr; 350 } 351 352 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 353 uint16_t idx) 354 { 355 void *addr; 356 int byte_count; 357 int i; 358 359 if (!is_atomic_response(qp, idx)) 360 return; 361 362 byte_count = be32_to_cpu(cqe64->byte_cnt); 363 addr = mlx5_get_atomic_laddr(qp, idx); 364 365 if (byte_count == 4) { 366 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr)); 367 } else { 368 for (i = 0; i < byte_count; i += 8) { 369 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr)); 370 addr += 8; 371 } 372 } 373 374 return; 375 } 376 377 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 378 u16 tail, u16 head) 379 { 380 u16 idx; 381 382 do { 383 idx = tail & (qp->sq.wqe_cnt - 1); 384 handle_atomic(qp, cqe64, idx); 385 if (idx == head) 386 break; 387 388 tail = qp->sq.w_list[idx].next; 389 } while (1); 390 tail = qp->sq.w_list[idx].next; 391 qp->sq.last_poll = tail; 392 } 393 394 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 395 { 396 mlx5_frag_buf_free(dev->mdev, &buf->fbc.frag_buf); 397 } 398 399 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 400 struct ib_sig_err *item) 401 { 402 u16 syndrome = be16_to_cpu(cqe->syndrome); 403 404 #define GUARD_ERR (1 << 13) 405 #define APPTAG_ERR (1 << 12) 406 #define REFTAG_ERR (1 << 11) 407 408 if (syndrome & GUARD_ERR) { 409 item->err_type = IB_SIG_BAD_GUARD; 410 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 411 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 412 } else 413 if (syndrome & REFTAG_ERR) { 414 item->err_type = IB_SIG_BAD_REFTAG; 415 item->expected = be32_to_cpu(cqe->expected_reftag); 416 item->actual = be32_to_cpu(cqe->actual_reftag); 417 } else 418 if (syndrome & APPTAG_ERR) { 419 item->err_type = IB_SIG_BAD_APPTAG; 420 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 421 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 422 } else { 423 pr_err("Got signature completion error with bad syndrome %04x\n", 424 syndrome); 425 } 426 427 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 428 item->key = be32_to_cpu(cqe->mkey); 429 } 430 431 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries, 432 struct ib_wc *wc, int *npolled) 433 { 434 struct mlx5_ib_wq *wq; 435 unsigned int cur; 436 unsigned int idx; 437 int np; 438 int i; 439 440 wq = &qp->sq; 441 cur = wq->head - wq->tail; 442 np = *npolled; 443 444 if (cur == 0) 445 return; 446 447 for (i = 0; i < cur && np < num_entries; i++) { 448 idx = wq->last_poll & (wq->wqe_cnt - 1); 449 wc->wr_id = wq->wrid[idx]; 450 wc->status = IB_WC_WR_FLUSH_ERR; 451 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 452 wq->tail++; 453 np++; 454 wc->qp = &qp->ibqp; 455 wc++; 456 wq->last_poll = wq->w_list[idx].next; 457 } 458 *npolled = np; 459 } 460 461 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries, 462 struct ib_wc *wc, int *npolled) 463 { 464 struct mlx5_ib_wq *wq; 465 unsigned int cur; 466 int np; 467 int i; 468 469 wq = &qp->rq; 470 cur = wq->head - wq->tail; 471 np = *npolled; 472 473 if (cur == 0) 474 return; 475 476 for (i = 0; i < cur && np < num_entries; i++) { 477 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 478 wc->status = IB_WC_WR_FLUSH_ERR; 479 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 480 wq->tail++; 481 np++; 482 wc->qp = &qp->ibqp; 483 wc++; 484 } 485 *npolled = np; 486 } 487 488 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 489 struct ib_wc *wc, int *npolled) 490 { 491 struct mlx5_ib_qp *qp; 492 493 *npolled = 0; 494 /* Find uncompleted WQEs belonging to that cq and return mmics ones */ 495 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 496 sw_send_comp(qp, num_entries, wc + *npolled, npolled); 497 if (*npolled >= num_entries) 498 return; 499 } 500 501 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 502 sw_recv_comp(qp, num_entries, wc + *npolled, npolled); 503 if (*npolled >= num_entries) 504 return; 505 } 506 } 507 508 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 509 struct mlx5_ib_qp **cur_qp, 510 struct ib_wc *wc) 511 { 512 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 513 struct mlx5_err_cqe *err_cqe; 514 struct mlx5_cqe64 *cqe64; 515 struct mlx5_core_qp *mqp; 516 struct mlx5_ib_wq *wq; 517 struct mlx5_sig_err_cqe *sig_err_cqe; 518 struct mlx5_core_mkey *mmkey; 519 struct mlx5_ib_mr *mr; 520 uint8_t opcode; 521 uint32_t qpn; 522 u16 wqe_ctr; 523 void *cqe; 524 int idx; 525 526 repoll: 527 cqe = next_cqe_sw(cq); 528 if (!cqe) 529 return -EAGAIN; 530 531 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 532 533 ++cq->mcq.cons_index; 534 535 /* Make sure we read CQ entry contents after we've checked the 536 * ownership bit. 537 */ 538 rmb(); 539 540 opcode = cqe64->op_own >> 4; 541 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 542 if (likely(cq->resize_buf)) { 543 free_cq_buf(dev, &cq->buf); 544 cq->buf = *cq->resize_buf; 545 kfree(cq->resize_buf); 546 cq->resize_buf = NULL; 547 goto repoll; 548 } else { 549 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 550 } 551 } 552 553 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 554 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 555 /* We do not have to take the QP table lock here, 556 * because CQs will be locked while QPs are removed 557 * from the table. 558 */ 559 mqp = __mlx5_qp_lookup(dev->mdev, qpn); 560 *cur_qp = to_mibqp(mqp); 561 } 562 563 wc->qp = &(*cur_qp)->ibqp; 564 switch (opcode) { 565 case MLX5_CQE_REQ: 566 wq = &(*cur_qp)->sq; 567 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 568 idx = wqe_ctr & (wq->wqe_cnt - 1); 569 handle_good_req(wc, cqe64, wq, idx); 570 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx); 571 wc->wr_id = wq->wrid[idx]; 572 wq->tail = wq->wqe_head[idx] + 1; 573 wc->status = IB_WC_SUCCESS; 574 break; 575 case MLX5_CQE_RESP_WR_IMM: 576 case MLX5_CQE_RESP_SEND: 577 case MLX5_CQE_RESP_SEND_IMM: 578 case MLX5_CQE_RESP_SEND_INV: 579 handle_responder(wc, cqe64, *cur_qp); 580 wc->status = IB_WC_SUCCESS; 581 break; 582 case MLX5_CQE_RESIZE_CQ: 583 break; 584 case MLX5_CQE_REQ_ERR: 585 case MLX5_CQE_RESP_ERR: 586 err_cqe = (struct mlx5_err_cqe *)cqe64; 587 mlx5_handle_error_cqe(dev, err_cqe, wc); 588 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 589 opcode == MLX5_CQE_REQ_ERR ? 590 "Requestor" : "Responder", cq->mcq.cqn); 591 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 592 err_cqe->syndrome, err_cqe->vendor_err_synd); 593 if (opcode == MLX5_CQE_REQ_ERR) { 594 wq = &(*cur_qp)->sq; 595 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 596 idx = wqe_ctr & (wq->wqe_cnt - 1); 597 wc->wr_id = wq->wrid[idx]; 598 wq->tail = wq->wqe_head[idx] + 1; 599 } else { 600 struct mlx5_ib_srq *srq; 601 602 if ((*cur_qp)->ibqp.srq) { 603 srq = to_msrq((*cur_qp)->ibqp.srq); 604 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 605 wc->wr_id = srq->wrid[wqe_ctr]; 606 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 607 } else { 608 wq = &(*cur_qp)->rq; 609 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 610 ++wq->tail; 611 } 612 } 613 break; 614 case MLX5_CQE_SIG_ERR: 615 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64; 616 617 read_lock(&dev->mdev->priv.mkey_table.lock); 618 mmkey = __mlx5_mr_lookup(dev->mdev, 619 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 620 mr = to_mibmr(mmkey); 621 get_sig_err_item(sig_err_cqe, &mr->sig->err_item); 622 mr->sig->sig_err_exists = true; 623 mr->sig->sigerr_count++; 624 625 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 626 cq->mcq.cqn, mr->sig->err_item.key, 627 mr->sig->err_item.err_type, 628 mr->sig->err_item.sig_err_offset, 629 mr->sig->err_item.expected, 630 mr->sig->err_item.actual); 631 632 read_unlock(&dev->mdev->priv.mkey_table.lock); 633 goto repoll; 634 } 635 636 return 0; 637 } 638 639 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 640 struct ib_wc *wc) 641 { 642 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 643 struct mlx5_ib_wc *soft_wc, *next; 644 int npolled = 0; 645 646 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 647 if (npolled >= num_entries) 648 break; 649 650 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 651 cq->mcq.cqn); 652 653 wc[npolled++] = soft_wc->wc; 654 list_del(&soft_wc->list); 655 kfree(soft_wc); 656 } 657 658 return npolled; 659 } 660 661 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 662 { 663 struct mlx5_ib_cq *cq = to_mcq(ibcq); 664 struct mlx5_ib_qp *cur_qp = NULL; 665 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 666 struct mlx5_core_dev *mdev = dev->mdev; 667 unsigned long flags; 668 int soft_polled = 0; 669 int npolled; 670 671 spin_lock_irqsave(&cq->lock, flags); 672 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 673 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 674 goto out; 675 } 676 677 if (unlikely(!list_empty(&cq->wc_list))) 678 soft_polled = poll_soft_wc(cq, num_entries, wc); 679 680 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 681 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 682 break; 683 } 684 685 if (npolled) 686 mlx5_cq_set_ci(&cq->mcq); 687 out: 688 spin_unlock_irqrestore(&cq->lock, flags); 689 690 return soft_polled + npolled; 691 } 692 693 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 694 { 695 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 696 struct mlx5_ib_cq *cq = to_mcq(ibcq); 697 void __iomem *uar_page = mdev->priv.uar->map; 698 unsigned long irq_flags; 699 int ret = 0; 700 701 spin_lock_irqsave(&cq->lock, irq_flags); 702 if (cq->notify_flags != IB_CQ_NEXT_COMP) 703 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 704 705 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 706 ret = 1; 707 spin_unlock_irqrestore(&cq->lock, irq_flags); 708 709 mlx5_cq_arm(&cq->mcq, 710 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 711 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 712 uar_page, to_mcq(ibcq)->mcq.cons_index); 713 714 return ret; 715 } 716 717 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, 718 struct mlx5_ib_cq_buf *buf, 719 int nent, 720 int cqe_size) 721 { 722 struct mlx5_frag_buf_ctrl *c = &buf->fbc; 723 struct mlx5_frag_buf *frag_buf = &c->frag_buf; 724 u32 cqc_buff[MLX5_ST_SZ_DW(cqc)] = {0}; 725 int err; 726 727 MLX5_SET(cqc, cqc_buff, log_cq_size, ilog2(cqe_size)); 728 MLX5_SET(cqc, cqc_buff, cqe_sz, (cqe_size == 128) ? 1 : 0); 729 730 mlx5_core_init_cq_frag_buf(&buf->fbc, cqc_buff); 731 732 err = mlx5_frag_buf_alloc_node(dev->mdev, 733 nent * cqe_size, 734 frag_buf, 735 dev->mdev->priv.numa_node); 736 if (err) 737 return err; 738 739 buf->cqe_size = cqe_size; 740 buf->nent = nent; 741 742 return 0; 743 } 744 745 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 746 struct ib_ucontext *context, struct mlx5_ib_cq *cq, 747 int entries, u32 **cqb, 748 int *cqe_size, int *index, int *inlen) 749 { 750 struct mlx5_ib_create_cq ucmd = {}; 751 size_t ucmdlen; 752 int page_shift; 753 __be64 *pas; 754 int npages; 755 int ncont; 756 void *cqc; 757 int err; 758 759 ucmdlen = udata->inlen < sizeof(ucmd) ? 760 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd); 761 762 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 763 return -EFAULT; 764 765 if (ucmdlen == sizeof(ucmd) && 766 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD))) 767 return -EINVAL; 768 769 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 770 return -EINVAL; 771 772 *cqe_size = ucmd.cqe_size; 773 774 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr, 775 entries * ucmd.cqe_size, 776 IB_ACCESS_LOCAL_WRITE, 1); 777 if (IS_ERR(cq->buf.umem)) { 778 err = PTR_ERR(cq->buf.umem); 779 return err; 780 } 781 782 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr, 783 &cq->db); 784 if (err) 785 goto err_umem; 786 787 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift, 788 &ncont, NULL); 789 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 790 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 791 792 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 793 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 794 *cqb = kvzalloc(*inlen, GFP_KERNEL); 795 if (!*cqb) { 796 err = -ENOMEM; 797 goto err_db; 798 } 799 800 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 801 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0); 802 803 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 804 MLX5_SET(cqc, cqc, log_page_size, 805 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 806 807 *index = to_mucontext(context)->bfregi.sys_pages[0]; 808 809 if (ucmd.cqe_comp_en == 1) { 810 if (!((*cqe_size == 128 && 811 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || 812 (*cqe_size == 64 && 813 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { 814 err = -EOPNOTSUPP; 815 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 816 *cqe_size); 817 goto err_cqb; 818 } 819 820 if (unlikely(!ucmd.cqe_comp_res_format || 821 !(ucmd.cqe_comp_res_format < 822 MLX5_IB_CQE_RES_RESERVED) || 823 (ucmd.cqe_comp_res_format & 824 (ucmd.cqe_comp_res_format - 1)))) { 825 err = -EOPNOTSUPP; 826 mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n", 827 ucmd.cqe_comp_res_format); 828 goto err_cqb; 829 } 830 831 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 832 MLX5_SET(cqc, cqc, mini_cqe_res_format, 833 ilog2(ucmd.cqe_comp_res_format)); 834 } 835 836 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) { 837 if (*cqe_size != 128 || 838 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { 839 err = -EOPNOTSUPP; 840 mlx5_ib_warn(dev, 841 "CQE padding is not supported for CQE size of %dB!\n", 842 *cqe_size); 843 goto err_cqb; 844 } 845 846 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD; 847 } 848 849 return 0; 850 851 err_cqb: 852 kfree(*cqb); 853 854 err_db: 855 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db); 856 857 err_umem: 858 ib_umem_release(cq->buf.umem); 859 return err; 860 } 861 862 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context) 863 { 864 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db); 865 ib_umem_release(cq->buf.umem); 866 } 867 868 static void init_cq_frag_buf(struct mlx5_ib_cq *cq, 869 struct mlx5_ib_cq_buf *buf) 870 { 871 int i; 872 void *cqe; 873 struct mlx5_cqe64 *cqe64; 874 875 for (i = 0; i < buf->nent; i++) { 876 cqe = get_cqe(cq, i); 877 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 878 cqe64->op_own = MLX5_CQE_INVALID << 4; 879 } 880 } 881 882 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 883 int entries, int cqe_size, 884 u32 **cqb, int *index, int *inlen) 885 { 886 __be64 *pas; 887 void *cqc; 888 int err; 889 890 err = mlx5_db_alloc(dev->mdev, &cq->db); 891 if (err) 892 return err; 893 894 cq->mcq.set_ci_db = cq->db.db; 895 cq->mcq.arm_db = cq->db.db + 1; 896 cq->mcq.cqe_sz = cqe_size; 897 898 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); 899 if (err) 900 goto err_db; 901 902 init_cq_frag_buf(cq, &cq->buf); 903 904 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 905 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * 906 cq->buf.fbc.frag_buf.npages; 907 *cqb = kvzalloc(*inlen, GFP_KERNEL); 908 if (!*cqb) { 909 err = -ENOMEM; 910 goto err_buf; 911 } 912 913 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 914 mlx5_fill_page_frag_array(&cq->buf.fbc.frag_buf, pas); 915 916 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 917 MLX5_SET(cqc, cqc, log_page_size, 918 cq->buf.fbc.frag_buf.page_shift - 919 MLX5_ADAPTER_PAGE_SHIFT); 920 921 *index = dev->mdev->priv.uar->index; 922 923 return 0; 924 925 err_buf: 926 free_cq_buf(dev, &cq->buf); 927 928 err_db: 929 mlx5_db_free(dev->mdev, &cq->db); 930 return err; 931 } 932 933 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 934 { 935 free_cq_buf(dev, &cq->buf); 936 mlx5_db_free(dev->mdev, &cq->db); 937 } 938 939 static void notify_soft_wc_handler(struct work_struct *work) 940 { 941 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 942 notify_work); 943 944 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 945 } 946 947 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 948 const struct ib_cq_init_attr *attr, 949 struct ib_ucontext *context, 950 struct ib_udata *udata) 951 { 952 int entries = attr->cqe; 953 int vector = attr->comp_vector; 954 struct mlx5_ib_dev *dev = to_mdev(ibdev); 955 struct mlx5_ib_cq *cq; 956 int uninitialized_var(index); 957 int uninitialized_var(inlen); 958 u32 *cqb = NULL; 959 void *cqc; 960 int cqe_size; 961 unsigned int irqn; 962 int eqn; 963 int err; 964 965 if (entries < 0 || 966 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 967 return ERR_PTR(-EINVAL); 968 969 if (check_cq_create_flags(attr->flags)) 970 return ERR_PTR(-EOPNOTSUPP); 971 972 entries = roundup_pow_of_two(entries + 1); 973 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 974 return ERR_PTR(-EINVAL); 975 976 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 977 if (!cq) 978 return ERR_PTR(-ENOMEM); 979 980 cq->ibcq.cqe = entries - 1; 981 mutex_init(&cq->resize_mutex); 982 spin_lock_init(&cq->lock); 983 cq->resize_buf = NULL; 984 cq->resize_umem = NULL; 985 cq->create_flags = attr->flags; 986 INIT_LIST_HEAD(&cq->list_send_qp); 987 INIT_LIST_HEAD(&cq->list_recv_qp); 988 989 if (context) { 990 err = create_cq_user(dev, udata, context, cq, entries, 991 &cqb, &cqe_size, &index, &inlen); 992 if (err) 993 goto err_create; 994 } else { 995 cqe_size = cache_line_size() == 128 ? 128 : 64; 996 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 997 &index, &inlen); 998 if (err) 999 goto err_create; 1000 1001 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 1002 } 1003 1004 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); 1005 if (err) 1006 goto err_cqb; 1007 1008 cq->cqe_size = cqe_size; 1009 1010 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 1011 MLX5_SET(cqc, cqc, cqe_sz, 1012 cqe_sz_to_mlx_sz(cqe_size, 1013 cq->private_flags & 1014 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1015 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1016 MLX5_SET(cqc, cqc, uar_page, index); 1017 MLX5_SET(cqc, cqc, c_eqn, eqn); 1018 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 1019 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) 1020 MLX5_SET(cqc, cqc, oi, 1); 1021 1022 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen); 1023 if (err) 1024 goto err_cqb; 1025 1026 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 1027 cq->mcq.irqn = irqn; 1028 if (context) 1029 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; 1030 else 1031 cq->mcq.comp = mlx5_ib_cq_comp; 1032 cq->mcq.event = mlx5_ib_cq_event; 1033 1034 INIT_LIST_HEAD(&cq->wc_list); 1035 1036 if (context) 1037 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 1038 err = -EFAULT; 1039 goto err_cmd; 1040 } 1041 1042 1043 kvfree(cqb); 1044 return &cq->ibcq; 1045 1046 err_cmd: 1047 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 1048 1049 err_cqb: 1050 kvfree(cqb); 1051 if (context) 1052 destroy_cq_user(cq, context); 1053 else 1054 destroy_cq_kernel(dev, cq); 1055 1056 err_create: 1057 kfree(cq); 1058 1059 return ERR_PTR(err); 1060 } 1061 1062 1063 int mlx5_ib_destroy_cq(struct ib_cq *cq) 1064 { 1065 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1066 struct mlx5_ib_cq *mcq = to_mcq(cq); 1067 struct ib_ucontext *context = NULL; 1068 1069 if (cq->uobject) 1070 context = cq->uobject->context; 1071 1072 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 1073 if (context) 1074 destroy_cq_user(mcq, context); 1075 else 1076 destroy_cq_kernel(dev, mcq); 1077 1078 kfree(mcq); 1079 1080 return 0; 1081 } 1082 1083 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1084 { 1085 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1086 } 1087 1088 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1089 { 1090 struct mlx5_cqe64 *cqe64, *dest64; 1091 void *cqe, *dest; 1092 u32 prod_index; 1093 int nfreed = 0; 1094 u8 owner_bit; 1095 1096 if (!cq) 1097 return; 1098 1099 /* First we need to find the current producer index, so we 1100 * know where to start cleaning from. It doesn't matter if HW 1101 * adds new entries after this loop -- the QP we're worried 1102 * about is already in RESET, so the new entries won't come 1103 * from our QP and therefore don't need to be checked. 1104 */ 1105 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1106 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1107 break; 1108 1109 /* Now sweep backwards through the CQ, removing CQ entries 1110 * that match our QP by copying older entries on top of them. 1111 */ 1112 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1113 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1114 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1115 if (is_equal_rsn(cqe64, rsn)) { 1116 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1117 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1118 ++nfreed; 1119 } else if (nfreed) { 1120 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1121 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1122 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1123 memcpy(dest, cqe, cq->mcq.cqe_sz); 1124 dest64->op_own = owner_bit | 1125 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1126 } 1127 } 1128 1129 if (nfreed) { 1130 cq->mcq.cons_index += nfreed; 1131 /* Make sure update of buffer contents is done before 1132 * updating consumer index. 1133 */ 1134 wmb(); 1135 mlx5_cq_set_ci(&cq->mcq); 1136 } 1137 } 1138 1139 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1140 { 1141 if (!cq) 1142 return; 1143 1144 spin_lock_irq(&cq->lock); 1145 __mlx5_ib_cq_clean(cq, qpn, srq); 1146 spin_unlock_irq(&cq->lock); 1147 } 1148 1149 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1150 { 1151 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1152 struct mlx5_ib_cq *mcq = to_mcq(cq); 1153 int err; 1154 1155 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1156 return -ENOSYS; 1157 1158 if (cq_period > MLX5_MAX_CQ_PERIOD) 1159 return -EINVAL; 1160 1161 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1162 cq_period, cq_count); 1163 if (err) 1164 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1165 1166 return err; 1167 } 1168 1169 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1170 int entries, struct ib_udata *udata, int *npas, 1171 int *page_shift, int *cqe_size) 1172 { 1173 struct mlx5_ib_resize_cq ucmd; 1174 struct ib_umem *umem; 1175 int err; 1176 int npages; 1177 struct ib_ucontext *context = cq->buf.umem->context; 1178 1179 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1180 if (err) 1181 return err; 1182 1183 if (ucmd.reserved0 || ucmd.reserved1) 1184 return -EINVAL; 1185 1186 /* check multiplication overflow */ 1187 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1188 return -EINVAL; 1189 1190 umem = ib_umem_get(context, ucmd.buf_addr, 1191 (size_t)ucmd.cqe_size * entries, 1192 IB_ACCESS_LOCAL_WRITE, 1); 1193 if (IS_ERR(umem)) { 1194 err = PTR_ERR(umem); 1195 return err; 1196 } 1197 1198 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift, 1199 npas, NULL); 1200 1201 cq->resize_umem = umem; 1202 *cqe_size = ucmd.cqe_size; 1203 1204 return 0; 1205 } 1206 1207 static void un_resize_user(struct mlx5_ib_cq *cq) 1208 { 1209 ib_umem_release(cq->resize_umem); 1210 } 1211 1212 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1213 int entries, int cqe_size) 1214 { 1215 int err; 1216 1217 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1218 if (!cq->resize_buf) 1219 return -ENOMEM; 1220 1221 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); 1222 if (err) 1223 goto ex; 1224 1225 init_cq_frag_buf(cq, cq->resize_buf); 1226 1227 return 0; 1228 1229 ex: 1230 kfree(cq->resize_buf); 1231 return err; 1232 } 1233 1234 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 1235 { 1236 free_cq_buf(dev, cq->resize_buf); 1237 cq->resize_buf = NULL; 1238 } 1239 1240 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1241 { 1242 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1243 struct mlx5_cqe64 *scqe64; 1244 struct mlx5_cqe64 *dcqe64; 1245 void *start_cqe; 1246 void *scqe; 1247 void *dcqe; 1248 int ssize; 1249 int dsize; 1250 int i; 1251 u8 sw_own; 1252 1253 ssize = cq->buf.cqe_size; 1254 dsize = cq->resize_buf->cqe_size; 1255 if (ssize != dsize) { 1256 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1257 return -EINVAL; 1258 } 1259 1260 i = cq->mcq.cons_index; 1261 scqe = get_sw_cqe(cq, i); 1262 scqe64 = ssize == 64 ? scqe : scqe + 64; 1263 start_cqe = scqe; 1264 if (!scqe) { 1265 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1266 return -EINVAL; 1267 } 1268 1269 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) { 1270 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, 1271 (i + 1) & cq->resize_buf->nent); 1272 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1273 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1274 memcpy(dcqe, scqe, dsize); 1275 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1276 1277 ++i; 1278 scqe = get_sw_cqe(cq, i); 1279 scqe64 = ssize == 64 ? scqe : scqe + 64; 1280 if (!scqe) { 1281 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1282 return -EINVAL; 1283 } 1284 1285 if (scqe == start_cqe) { 1286 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1287 cq->mcq.cqn); 1288 return -ENOMEM; 1289 } 1290 } 1291 ++cq->mcq.cons_index; 1292 return 0; 1293 } 1294 1295 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1296 { 1297 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1298 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1299 void *cqc; 1300 u32 *in; 1301 int err; 1302 int npas; 1303 __be64 *pas; 1304 int page_shift; 1305 int inlen; 1306 int uninitialized_var(cqe_size); 1307 unsigned long flags; 1308 1309 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1310 pr_info("Firmware does not support resize CQ\n"); 1311 return -ENOSYS; 1312 } 1313 1314 if (entries < 1 || 1315 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1316 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1317 entries, 1318 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1319 return -EINVAL; 1320 } 1321 1322 entries = roundup_pow_of_two(entries + 1); 1323 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1324 return -EINVAL; 1325 1326 if (entries == ibcq->cqe + 1) 1327 return 0; 1328 1329 mutex_lock(&cq->resize_mutex); 1330 if (udata) { 1331 err = resize_user(dev, cq, entries, udata, &npas, &page_shift, 1332 &cqe_size); 1333 } else { 1334 cqe_size = 64; 1335 err = resize_kernel(dev, cq, entries, cqe_size); 1336 if (!err) { 1337 struct mlx5_frag_buf_ctrl *c; 1338 1339 c = &cq->resize_buf->fbc; 1340 npas = c->frag_buf.npages; 1341 page_shift = c->frag_buf.page_shift; 1342 } 1343 } 1344 1345 if (err) 1346 goto ex; 1347 1348 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1349 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1350 1351 in = kvzalloc(inlen, GFP_KERNEL); 1352 if (!in) { 1353 err = -ENOMEM; 1354 goto ex_resize; 1355 } 1356 1357 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1358 if (udata) 1359 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, 1360 pas, 0); 1361 else 1362 mlx5_fill_page_frag_array(&cq->resize_buf->fbc.frag_buf, 1363 pas); 1364 1365 MLX5_SET(modify_cq_in, in, 1366 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1367 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1368 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1369 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1370 1371 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1372 1373 MLX5_SET(cqc, cqc, log_page_size, 1374 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1375 MLX5_SET(cqc, cqc, cqe_sz, 1376 cqe_sz_to_mlx_sz(cqe_size, 1377 cq->private_flags & 1378 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1379 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1380 1381 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1382 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1383 1384 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1385 if (err) 1386 goto ex_alloc; 1387 1388 if (udata) { 1389 cq->ibcq.cqe = entries - 1; 1390 ib_umem_release(cq->buf.umem); 1391 cq->buf.umem = cq->resize_umem; 1392 cq->resize_umem = NULL; 1393 } else { 1394 struct mlx5_ib_cq_buf tbuf; 1395 int resized = 0; 1396 1397 spin_lock_irqsave(&cq->lock, flags); 1398 if (cq->resize_buf) { 1399 err = copy_resize_cqes(cq); 1400 if (!err) { 1401 tbuf = cq->buf; 1402 cq->buf = *cq->resize_buf; 1403 kfree(cq->resize_buf); 1404 cq->resize_buf = NULL; 1405 resized = 1; 1406 } 1407 } 1408 cq->ibcq.cqe = entries - 1; 1409 spin_unlock_irqrestore(&cq->lock, flags); 1410 if (resized) 1411 free_cq_buf(dev, &tbuf); 1412 } 1413 mutex_unlock(&cq->resize_mutex); 1414 1415 kvfree(in); 1416 return 0; 1417 1418 ex_alloc: 1419 kvfree(in); 1420 1421 ex_resize: 1422 if (udata) 1423 un_resize_user(cq); 1424 else 1425 un_resize_kernel(dev, cq); 1426 ex: 1427 mutex_unlock(&cq->resize_mutex); 1428 return err; 1429 } 1430 1431 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq) 1432 { 1433 struct mlx5_ib_cq *cq; 1434 1435 if (!ibcq) 1436 return 128; 1437 1438 cq = to_mcq(ibcq); 1439 return cq->cqe_size; 1440 } 1441 1442 /* Called from atomic context */ 1443 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1444 { 1445 struct mlx5_ib_wc *soft_wc; 1446 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1447 unsigned long flags; 1448 1449 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1450 if (!soft_wc) 1451 return -ENOMEM; 1452 1453 soft_wc->wc = *wc; 1454 spin_lock_irqsave(&cq->lock, flags); 1455 list_add_tail(&soft_wc->list, &cq->wc_list); 1456 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1457 wc->status != IB_WC_SUCCESS) { 1458 cq->notify_flags = 0; 1459 schedule_work(&cq->notify_work); 1460 } 1461 spin_unlock_irqrestore(&cq->lock, flags); 1462 1463 return 0; 1464 } 1465