1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kref.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/ib_cache.h> 37 #include "mlx5_ib.h" 38 #include "srq.h" 39 40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq) 41 { 42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 43 44 ibcq->comp_handler(ibcq, ibcq->cq_context); 45 } 46 47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) 48 { 49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 51 struct ib_cq *ibcq = &cq->ibcq; 52 struct ib_event event; 53 54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 56 type, mcq->cqn); 57 return; 58 } 59 60 if (ibcq->event_handler) { 61 event.device = &dev->ib_dev; 62 event.event = IB_EVENT_CQ_ERR; 63 event.element.cq = ibcq; 64 ibcq->event_handler(&event, ibcq->cq_context); 65 } 66 } 67 68 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 69 { 70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); 71 } 72 73 static u8 sw_ownership_bit(int n, int nent) 74 { 75 return (n & nent) ? 1 : 0; 76 } 77 78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 79 { 80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 81 struct mlx5_cqe64 *cqe64; 82 83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 84 85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && 86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 87 return cqe; 88 } else { 89 return NULL; 90 } 91 } 92 93 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 94 { 95 return get_sw_cqe(cq, cq->mcq.cons_index); 96 } 97 98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 99 { 100 switch (wq->wr_data[idx]) { 101 case MLX5_IB_WR_UMR: 102 return 0; 103 104 case IB_WR_LOCAL_INV: 105 return IB_WC_LOCAL_INV; 106 107 case IB_WR_REG_MR: 108 return IB_WC_REG_MR; 109 110 default: 111 pr_warn("unknown completion status\n"); 112 return 0; 113 } 114 } 115 116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 117 struct mlx5_ib_wq *wq, int idx) 118 { 119 wc->wc_flags = 0; 120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 121 case MLX5_OPCODE_RDMA_WRITE_IMM: 122 wc->wc_flags |= IB_WC_WITH_IMM; 123 /* fall through */ 124 case MLX5_OPCODE_RDMA_WRITE: 125 wc->opcode = IB_WC_RDMA_WRITE; 126 break; 127 case MLX5_OPCODE_SEND_IMM: 128 wc->wc_flags |= IB_WC_WITH_IMM; 129 /* fall through */ 130 case MLX5_OPCODE_SEND: 131 case MLX5_OPCODE_SEND_INVAL: 132 wc->opcode = IB_WC_SEND; 133 break; 134 case MLX5_OPCODE_RDMA_READ: 135 wc->opcode = IB_WC_RDMA_READ; 136 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 137 break; 138 case MLX5_OPCODE_ATOMIC_CS: 139 wc->opcode = IB_WC_COMP_SWAP; 140 wc->byte_len = 8; 141 break; 142 case MLX5_OPCODE_ATOMIC_FA: 143 wc->opcode = IB_WC_FETCH_ADD; 144 wc->byte_len = 8; 145 break; 146 case MLX5_OPCODE_ATOMIC_MASKED_CS: 147 wc->opcode = IB_WC_MASKED_COMP_SWAP; 148 wc->byte_len = 8; 149 break; 150 case MLX5_OPCODE_ATOMIC_MASKED_FA: 151 wc->opcode = IB_WC_MASKED_FETCH_ADD; 152 wc->byte_len = 8; 153 break; 154 case MLX5_OPCODE_UMR: 155 wc->opcode = get_umr_comp(wq, idx); 156 break; 157 } 158 } 159 160 enum { 161 MLX5_GRH_IN_BUFFER = 1, 162 MLX5_GRH_IN_CQE = 2, 163 }; 164 165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 166 struct mlx5_ib_qp *qp) 167 { 168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 170 struct mlx5_ib_srq *srq; 171 struct mlx5_ib_wq *wq; 172 u16 wqe_ctr; 173 u8 roce_packet_type; 174 bool vlan_present; 175 u8 g; 176 177 if (qp->ibqp.srq || qp->ibqp.xrcd) { 178 struct mlx5_core_srq *msrq = NULL; 179 180 if (qp->ibqp.xrcd) { 181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn)); 182 srq = to_mibsrq(msrq); 183 } else { 184 srq = to_msrq(qp->ibqp.srq); 185 } 186 if (srq) { 187 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 188 wc->wr_id = srq->wrid[wqe_ctr]; 189 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 190 if (msrq) 191 mlx5_core_res_put(&msrq->common); 192 } 193 } else { 194 wq = &qp->rq; 195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 196 ++wq->tail; 197 } 198 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 199 200 switch (get_cqe_opcode(cqe)) { 201 case MLX5_CQE_RESP_WR_IMM: 202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 203 wc->wc_flags = IB_WC_WITH_IMM; 204 wc->ex.imm_data = cqe->imm_inval_pkey; 205 break; 206 case MLX5_CQE_RESP_SEND: 207 wc->opcode = IB_WC_RECV; 208 wc->wc_flags = IB_WC_IP_CSUM_OK; 209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 210 (cqe->hds_ip_ext & CQE_L4_OK)))) 211 wc->wc_flags = 0; 212 break; 213 case MLX5_CQE_RESP_SEND_IMM: 214 wc->opcode = IB_WC_RECV; 215 wc->wc_flags = IB_WC_WITH_IMM; 216 wc->ex.imm_data = cqe->imm_inval_pkey; 217 break; 218 case MLX5_CQE_RESP_SEND_INV: 219 wc->opcode = IB_WC_RECV; 220 wc->wc_flags = IB_WC_WITH_INVALIDATE; 221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey); 222 break; 223 } 224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 225 wc->dlid_path_bits = cqe->ml_path; 226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 227 wc->wc_flags |= g ? IB_WC_GRH : 0; 228 if (unlikely(is_qp1(qp->ibqp.qp_type))) { 229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff; 230 231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 232 &wc->pkey_index); 233 } else { 234 wc->pkey_index = 0; 235 } 236 237 if (ll != IB_LINK_LAYER_ETHERNET) { 238 wc->slid = be16_to_cpu(cqe->slid); 239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 240 return; 241 } 242 243 wc->slid = 0; 244 vlan_present = cqe->l4_l3_hdr_type & 0x1; 245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 246 if (vlan_present) { 247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 249 wc->wc_flags |= IB_WC_WITH_VLAN; 250 } else { 251 wc->sl = 0; 252 } 253 254 switch (roce_packet_type) { 255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 256 wc->network_hdr_type = RDMA_NETWORK_IB; 257 break; 258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 259 wc->network_hdr_type = RDMA_NETWORK_IPV6; 260 break; 261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 262 wc->network_hdr_type = RDMA_NETWORK_IPV4; 263 break; 264 } 265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 266 } 267 268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 269 { 270 mlx5_ib_warn(dev, "dump error cqe\n"); 271 mlx5_dump_err_cqe(dev->mdev, cqe); 272 } 273 274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 275 struct mlx5_err_cqe *cqe, 276 struct ib_wc *wc) 277 { 278 int dump = 1; 279 280 switch (cqe->syndrome) { 281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 282 wc->status = IB_WC_LOC_LEN_ERR; 283 break; 284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 285 wc->status = IB_WC_LOC_QP_OP_ERR; 286 break; 287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 288 wc->status = IB_WC_LOC_PROT_ERR; 289 break; 290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 291 dump = 0; 292 wc->status = IB_WC_WR_FLUSH_ERR; 293 break; 294 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 295 wc->status = IB_WC_MW_BIND_ERR; 296 break; 297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 298 wc->status = IB_WC_BAD_RESP_ERR; 299 break; 300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 301 wc->status = IB_WC_LOC_ACCESS_ERR; 302 break; 303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 304 wc->status = IB_WC_REM_INV_REQ_ERR; 305 break; 306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 307 wc->status = IB_WC_REM_ACCESS_ERR; 308 break; 309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 310 wc->status = IB_WC_REM_OP_ERR; 311 break; 312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 313 wc->status = IB_WC_RETRY_EXC_ERR; 314 dump = 0; 315 break; 316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 317 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 318 dump = 0; 319 break; 320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 321 wc->status = IB_WC_REM_ABORT_ERR; 322 break; 323 default: 324 wc->status = IB_WC_GENERAL_ERR; 325 break; 326 } 327 328 wc->vendor_err = cqe->vendor_err_synd; 329 if (dump) 330 dump_cqe(dev, cqe); 331 } 332 333 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 334 { 335 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf); 336 } 337 338 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 339 struct ib_sig_err *item) 340 { 341 u16 syndrome = be16_to_cpu(cqe->syndrome); 342 343 #define GUARD_ERR (1 << 13) 344 #define APPTAG_ERR (1 << 12) 345 #define REFTAG_ERR (1 << 11) 346 347 if (syndrome & GUARD_ERR) { 348 item->err_type = IB_SIG_BAD_GUARD; 349 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 350 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 351 } else 352 if (syndrome & REFTAG_ERR) { 353 item->err_type = IB_SIG_BAD_REFTAG; 354 item->expected = be32_to_cpu(cqe->expected_reftag); 355 item->actual = be32_to_cpu(cqe->actual_reftag); 356 } else 357 if (syndrome & APPTAG_ERR) { 358 item->err_type = IB_SIG_BAD_APPTAG; 359 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 360 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 361 } else { 362 pr_err("Got signature completion error with bad syndrome %04x\n", 363 syndrome); 364 } 365 366 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 367 item->key = be32_to_cpu(cqe->mkey); 368 } 369 370 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc, 371 int *npolled, int is_send) 372 { 373 struct mlx5_ib_wq *wq; 374 unsigned int cur; 375 int np; 376 int i; 377 378 wq = (is_send) ? &qp->sq : &qp->rq; 379 cur = wq->head - wq->tail; 380 np = *npolled; 381 382 if (cur == 0) 383 return; 384 385 for (i = 0; i < cur && np < num_entries; i++) { 386 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 387 wc->status = IB_WC_WR_FLUSH_ERR; 388 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 389 wq->tail++; 390 np++; 391 wc->qp = &qp->ibqp; 392 wc++; 393 } 394 *npolled = np; 395 } 396 397 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 398 struct ib_wc *wc, int *npolled) 399 { 400 struct mlx5_ib_qp *qp; 401 402 *npolled = 0; 403 /* Find uncompleted WQEs belonging to that cq and return mmics ones */ 404 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 405 sw_comp(qp, num_entries, wc + *npolled, npolled, true); 406 if (*npolled >= num_entries) 407 return; 408 } 409 410 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 411 sw_comp(qp, num_entries, wc + *npolled, npolled, false); 412 if (*npolled >= num_entries) 413 return; 414 } 415 } 416 417 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 418 struct mlx5_ib_qp **cur_qp, 419 struct ib_wc *wc) 420 { 421 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 422 struct mlx5_err_cqe *err_cqe; 423 struct mlx5_cqe64 *cqe64; 424 struct mlx5_core_qp *mqp; 425 struct mlx5_ib_wq *wq; 426 struct mlx5_sig_err_cqe *sig_err_cqe; 427 struct mlx5_core_mkey *mmkey; 428 struct mlx5_ib_mr *mr; 429 uint8_t opcode; 430 uint32_t qpn; 431 u16 wqe_ctr; 432 void *cqe; 433 int idx; 434 435 repoll: 436 cqe = next_cqe_sw(cq); 437 if (!cqe) 438 return -EAGAIN; 439 440 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 441 442 ++cq->mcq.cons_index; 443 444 /* Make sure we read CQ entry contents after we've checked the 445 * ownership bit. 446 */ 447 rmb(); 448 449 opcode = get_cqe_opcode(cqe64); 450 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 451 if (likely(cq->resize_buf)) { 452 free_cq_buf(dev, &cq->buf); 453 cq->buf = *cq->resize_buf; 454 kfree(cq->resize_buf); 455 cq->resize_buf = NULL; 456 goto repoll; 457 } else { 458 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 459 } 460 } 461 462 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 463 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 464 /* We do not have to take the QP table lock here, 465 * because CQs will be locked while QPs are removed 466 * from the table. 467 */ 468 mqp = __mlx5_qp_lookup(dev->mdev, qpn); 469 *cur_qp = to_mibqp(mqp); 470 } 471 472 wc->qp = &(*cur_qp)->ibqp; 473 switch (opcode) { 474 case MLX5_CQE_REQ: 475 wq = &(*cur_qp)->sq; 476 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 477 idx = wqe_ctr & (wq->wqe_cnt - 1); 478 handle_good_req(wc, cqe64, wq, idx); 479 wc->wr_id = wq->wrid[idx]; 480 wq->tail = wq->wqe_head[idx] + 1; 481 wc->status = IB_WC_SUCCESS; 482 break; 483 case MLX5_CQE_RESP_WR_IMM: 484 case MLX5_CQE_RESP_SEND: 485 case MLX5_CQE_RESP_SEND_IMM: 486 case MLX5_CQE_RESP_SEND_INV: 487 handle_responder(wc, cqe64, *cur_qp); 488 wc->status = IB_WC_SUCCESS; 489 break; 490 case MLX5_CQE_RESIZE_CQ: 491 break; 492 case MLX5_CQE_REQ_ERR: 493 case MLX5_CQE_RESP_ERR: 494 err_cqe = (struct mlx5_err_cqe *)cqe64; 495 mlx5_handle_error_cqe(dev, err_cqe, wc); 496 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 497 opcode == MLX5_CQE_REQ_ERR ? 498 "Requestor" : "Responder", cq->mcq.cqn); 499 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 500 err_cqe->syndrome, err_cqe->vendor_err_synd); 501 if (opcode == MLX5_CQE_REQ_ERR) { 502 wq = &(*cur_qp)->sq; 503 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 504 idx = wqe_ctr & (wq->wqe_cnt - 1); 505 wc->wr_id = wq->wrid[idx]; 506 wq->tail = wq->wqe_head[idx] + 1; 507 } else { 508 struct mlx5_ib_srq *srq; 509 510 if ((*cur_qp)->ibqp.srq) { 511 srq = to_msrq((*cur_qp)->ibqp.srq); 512 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 513 wc->wr_id = srq->wrid[wqe_ctr]; 514 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 515 } else { 516 wq = &(*cur_qp)->rq; 517 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 518 ++wq->tail; 519 } 520 } 521 break; 522 case MLX5_CQE_SIG_ERR: 523 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64; 524 525 read_lock(&dev->mdev->priv.mkey_table.lock); 526 mmkey = __mlx5_mr_lookup(dev->mdev, 527 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 528 mr = to_mibmr(mmkey); 529 get_sig_err_item(sig_err_cqe, &mr->sig->err_item); 530 mr->sig->sig_err_exists = true; 531 mr->sig->sigerr_count++; 532 533 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 534 cq->mcq.cqn, mr->sig->err_item.key, 535 mr->sig->err_item.err_type, 536 mr->sig->err_item.sig_err_offset, 537 mr->sig->err_item.expected, 538 mr->sig->err_item.actual); 539 540 read_unlock(&dev->mdev->priv.mkey_table.lock); 541 goto repoll; 542 } 543 544 return 0; 545 } 546 547 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 548 struct ib_wc *wc, bool is_fatal_err) 549 { 550 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 551 struct mlx5_ib_wc *soft_wc, *next; 552 int npolled = 0; 553 554 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 555 if (npolled >= num_entries) 556 break; 557 558 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 559 cq->mcq.cqn); 560 561 if (unlikely(is_fatal_err)) { 562 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR; 563 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 564 } 565 wc[npolled++] = soft_wc->wc; 566 list_del(&soft_wc->list); 567 kfree(soft_wc); 568 } 569 570 return npolled; 571 } 572 573 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 574 { 575 struct mlx5_ib_cq *cq = to_mcq(ibcq); 576 struct mlx5_ib_qp *cur_qp = NULL; 577 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 578 struct mlx5_core_dev *mdev = dev->mdev; 579 unsigned long flags; 580 int soft_polled = 0; 581 int npolled; 582 583 spin_lock_irqsave(&cq->lock, flags); 584 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 585 /* make sure no soft wqe's are waiting */ 586 if (unlikely(!list_empty(&cq->wc_list))) 587 soft_polled = poll_soft_wc(cq, num_entries, wc, true); 588 589 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled, 590 wc + soft_polled, &npolled); 591 goto out; 592 } 593 594 if (unlikely(!list_empty(&cq->wc_list))) 595 soft_polled = poll_soft_wc(cq, num_entries, wc, false); 596 597 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 598 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 599 break; 600 } 601 602 if (npolled) 603 mlx5_cq_set_ci(&cq->mcq); 604 out: 605 spin_unlock_irqrestore(&cq->lock, flags); 606 607 return soft_polled + npolled; 608 } 609 610 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 611 { 612 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 613 struct mlx5_ib_cq *cq = to_mcq(ibcq); 614 void __iomem *uar_page = mdev->priv.uar->map; 615 unsigned long irq_flags; 616 int ret = 0; 617 618 spin_lock_irqsave(&cq->lock, irq_flags); 619 if (cq->notify_flags != IB_CQ_NEXT_COMP) 620 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 621 622 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 623 ret = 1; 624 spin_unlock_irqrestore(&cq->lock, irq_flags); 625 626 mlx5_cq_arm(&cq->mcq, 627 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 628 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 629 uar_page, to_mcq(ibcq)->mcq.cons_index); 630 631 return ret; 632 } 633 634 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, 635 struct mlx5_ib_cq_buf *buf, 636 int nent, 637 int cqe_size) 638 { 639 struct mlx5_frag_buf *frag_buf = &buf->frag_buf; 640 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); 641 u8 log_wq_sz = ilog2(cqe_size); 642 int err; 643 644 err = mlx5_frag_buf_alloc_node(dev->mdev, 645 nent * cqe_size, 646 frag_buf, 647 dev->mdev->priv.numa_node); 648 if (err) 649 return err; 650 651 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); 652 653 buf->cqe_size = cqe_size; 654 buf->nent = nent; 655 656 return 0; 657 } 658 659 enum { 660 MLX5_CQE_RES_FORMAT_HASH = 0, 661 MLX5_CQE_RES_FORMAT_CSUM = 1, 662 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3, 663 }; 664 665 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format) 666 { 667 switch (format) { 668 case MLX5_IB_CQE_RES_FORMAT_HASH: 669 return MLX5_CQE_RES_FORMAT_HASH; 670 case MLX5_IB_CQE_RES_FORMAT_CSUM: 671 return MLX5_CQE_RES_FORMAT_CSUM; 672 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX: 673 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 674 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX; 675 return -EOPNOTSUPP; 676 default: 677 return -EINVAL; 678 } 679 } 680 681 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 682 struct mlx5_ib_cq *cq, int entries, u32 **cqb, 683 int *cqe_size, int *index, int *inlen) 684 { 685 struct mlx5_ib_create_cq ucmd = {}; 686 size_t ucmdlen; 687 int page_shift; 688 __be64 *pas; 689 int npages; 690 int ncont; 691 void *cqc; 692 int err; 693 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 694 udata, struct mlx5_ib_ucontext, ibucontext); 695 696 ucmdlen = udata->inlen < sizeof(ucmd) ? 697 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd); 698 699 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 700 return -EFAULT; 701 702 if (ucmdlen == sizeof(ucmd) && 703 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD))) 704 return -EINVAL; 705 706 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 707 return -EINVAL; 708 709 *cqe_size = ucmd.cqe_size; 710 711 cq->buf.umem = 712 ib_umem_get(udata, ucmd.buf_addr, entries * ucmd.cqe_size, 713 IB_ACCESS_LOCAL_WRITE, 1); 714 if (IS_ERR(cq->buf.umem)) { 715 err = PTR_ERR(cq->buf.umem); 716 return err; 717 } 718 719 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db); 720 if (err) 721 goto err_umem; 722 723 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift, 724 &ncont, NULL); 725 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 726 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 727 728 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 729 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 730 *cqb = kvzalloc(*inlen, GFP_KERNEL); 731 if (!*cqb) { 732 err = -ENOMEM; 733 goto err_db; 734 } 735 736 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 737 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0); 738 739 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 740 MLX5_SET(cqc, cqc, log_page_size, 741 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 742 743 *index = context->bfregi.sys_pages[0]; 744 745 if (ucmd.cqe_comp_en == 1) { 746 int mini_cqe_format; 747 748 if (!((*cqe_size == 128 && 749 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || 750 (*cqe_size == 64 && 751 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { 752 err = -EOPNOTSUPP; 753 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 754 *cqe_size); 755 goto err_cqb; 756 } 757 758 mini_cqe_format = 759 mini_cqe_res_format_to_hw(dev, 760 ucmd.cqe_comp_res_format); 761 if (mini_cqe_format < 0) { 762 err = mini_cqe_format; 763 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n", 764 ucmd.cqe_comp_res_format, err); 765 goto err_cqb; 766 } 767 768 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 769 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); 770 } 771 772 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) { 773 if (*cqe_size != 128 || 774 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { 775 err = -EOPNOTSUPP; 776 mlx5_ib_warn(dev, 777 "CQE padding is not supported for CQE size of %dB!\n", 778 *cqe_size); 779 goto err_cqb; 780 } 781 782 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD; 783 } 784 785 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid); 786 return 0; 787 788 err_cqb: 789 kvfree(*cqb); 790 791 err_db: 792 mlx5_ib_db_unmap_user(context, &cq->db); 793 794 err_umem: 795 ib_umem_release(cq->buf.umem); 796 return err; 797 } 798 799 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata) 800 { 801 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 804 mlx5_ib_db_unmap_user(context, &cq->db); 805 ib_umem_release(cq->buf.umem); 806 } 807 808 static void init_cq_frag_buf(struct mlx5_ib_cq *cq, 809 struct mlx5_ib_cq_buf *buf) 810 { 811 int i; 812 void *cqe; 813 struct mlx5_cqe64 *cqe64; 814 815 for (i = 0; i < buf->nent; i++) { 816 cqe = get_cqe(cq, i); 817 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 818 cqe64->op_own = MLX5_CQE_INVALID << 4; 819 } 820 } 821 822 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 823 int entries, int cqe_size, 824 u32 **cqb, int *index, int *inlen) 825 { 826 __be64 *pas; 827 void *cqc; 828 int err; 829 830 err = mlx5_db_alloc(dev->mdev, &cq->db); 831 if (err) 832 return err; 833 834 cq->mcq.set_ci_db = cq->db.db; 835 cq->mcq.arm_db = cq->db.db + 1; 836 cq->mcq.cqe_sz = cqe_size; 837 838 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); 839 if (err) 840 goto err_db; 841 842 init_cq_frag_buf(cq, &cq->buf); 843 844 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 845 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * 846 cq->buf.frag_buf.npages; 847 *cqb = kvzalloc(*inlen, GFP_KERNEL); 848 if (!*cqb) { 849 err = -ENOMEM; 850 goto err_buf; 851 } 852 853 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 854 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); 855 856 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 857 MLX5_SET(cqc, cqc, log_page_size, 858 cq->buf.frag_buf.page_shift - 859 MLX5_ADAPTER_PAGE_SHIFT); 860 861 *index = dev->mdev->priv.uar->index; 862 863 return 0; 864 865 err_buf: 866 free_cq_buf(dev, &cq->buf); 867 868 err_db: 869 mlx5_db_free(dev->mdev, &cq->db); 870 return err; 871 } 872 873 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 874 { 875 free_cq_buf(dev, &cq->buf); 876 mlx5_db_free(dev->mdev, &cq->db); 877 } 878 879 static void notify_soft_wc_handler(struct work_struct *work) 880 { 881 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 882 notify_work); 883 884 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 885 } 886 887 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 888 const struct ib_cq_init_attr *attr, 889 struct ib_udata *udata) 890 { 891 int entries = attr->cqe; 892 int vector = attr->comp_vector; 893 struct mlx5_ib_dev *dev = to_mdev(ibdev); 894 struct mlx5_ib_cq *cq; 895 int uninitialized_var(index); 896 int uninitialized_var(inlen); 897 u32 *cqb = NULL; 898 void *cqc; 899 int cqe_size; 900 unsigned int irqn; 901 int eqn; 902 int err; 903 904 if (entries < 0 || 905 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 906 return ERR_PTR(-EINVAL); 907 908 if (check_cq_create_flags(attr->flags)) 909 return ERR_PTR(-EOPNOTSUPP); 910 911 entries = roundup_pow_of_two(entries + 1); 912 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 913 return ERR_PTR(-EINVAL); 914 915 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 916 if (!cq) 917 return ERR_PTR(-ENOMEM); 918 919 cq->ibcq.cqe = entries - 1; 920 mutex_init(&cq->resize_mutex); 921 spin_lock_init(&cq->lock); 922 cq->resize_buf = NULL; 923 cq->resize_umem = NULL; 924 cq->create_flags = attr->flags; 925 INIT_LIST_HEAD(&cq->list_send_qp); 926 INIT_LIST_HEAD(&cq->list_recv_qp); 927 928 if (udata) { 929 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size, 930 &index, &inlen); 931 if (err) 932 goto err_create; 933 } else { 934 cqe_size = cache_line_size() == 128 ? 128 : 64; 935 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 936 &index, &inlen); 937 if (err) 938 goto err_create; 939 940 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 941 } 942 943 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); 944 if (err) 945 goto err_cqb; 946 947 cq->cqe_size = cqe_size; 948 949 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 950 MLX5_SET(cqc, cqc, cqe_sz, 951 cqe_sz_to_mlx_sz(cqe_size, 952 cq->private_flags & 953 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 954 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 955 MLX5_SET(cqc, cqc, uar_page, index); 956 MLX5_SET(cqc, cqc, c_eqn, eqn); 957 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 958 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) 959 MLX5_SET(cqc, cqc, oi, 1); 960 961 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen); 962 if (err) 963 goto err_cqb; 964 965 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 966 cq->mcq.irqn = irqn; 967 if (udata) 968 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; 969 else 970 cq->mcq.comp = mlx5_ib_cq_comp; 971 cq->mcq.event = mlx5_ib_cq_event; 972 973 INIT_LIST_HEAD(&cq->wc_list); 974 975 if (udata) 976 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 977 err = -EFAULT; 978 goto err_cmd; 979 } 980 981 982 kvfree(cqb); 983 return &cq->ibcq; 984 985 err_cmd: 986 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 987 988 err_cqb: 989 kvfree(cqb); 990 if (udata) 991 destroy_cq_user(cq, udata); 992 else 993 destroy_cq_kernel(dev, cq); 994 995 err_create: 996 kfree(cq); 997 998 return ERR_PTR(err); 999 } 1000 1001 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 1002 { 1003 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1004 struct mlx5_ib_cq *mcq = to_mcq(cq); 1005 1006 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 1007 if (udata) 1008 destroy_cq_user(mcq, udata); 1009 else 1010 destroy_cq_kernel(dev, mcq); 1011 1012 kfree(mcq); 1013 1014 return 0; 1015 } 1016 1017 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1018 { 1019 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1020 } 1021 1022 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1023 { 1024 struct mlx5_cqe64 *cqe64, *dest64; 1025 void *cqe, *dest; 1026 u32 prod_index; 1027 int nfreed = 0; 1028 u8 owner_bit; 1029 1030 if (!cq) 1031 return; 1032 1033 /* First we need to find the current producer index, so we 1034 * know where to start cleaning from. It doesn't matter if HW 1035 * adds new entries after this loop -- the QP we're worried 1036 * about is already in RESET, so the new entries won't come 1037 * from our QP and therefore don't need to be checked. 1038 */ 1039 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1040 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1041 break; 1042 1043 /* Now sweep backwards through the CQ, removing CQ entries 1044 * that match our QP by copying older entries on top of them. 1045 */ 1046 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1047 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1048 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1049 if (is_equal_rsn(cqe64, rsn)) { 1050 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1051 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1052 ++nfreed; 1053 } else if (nfreed) { 1054 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1055 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1056 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1057 memcpy(dest, cqe, cq->mcq.cqe_sz); 1058 dest64->op_own = owner_bit | 1059 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1060 } 1061 } 1062 1063 if (nfreed) { 1064 cq->mcq.cons_index += nfreed; 1065 /* Make sure update of buffer contents is done before 1066 * updating consumer index. 1067 */ 1068 wmb(); 1069 mlx5_cq_set_ci(&cq->mcq); 1070 } 1071 } 1072 1073 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1074 { 1075 if (!cq) 1076 return; 1077 1078 spin_lock_irq(&cq->lock); 1079 __mlx5_ib_cq_clean(cq, qpn, srq); 1080 spin_unlock_irq(&cq->lock); 1081 } 1082 1083 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1084 { 1085 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1086 struct mlx5_ib_cq *mcq = to_mcq(cq); 1087 int err; 1088 1089 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1090 return -EOPNOTSUPP; 1091 1092 if (cq_period > MLX5_MAX_CQ_PERIOD) 1093 return -EINVAL; 1094 1095 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1096 cq_period, cq_count); 1097 if (err) 1098 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1099 1100 return err; 1101 } 1102 1103 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1104 int entries, struct ib_udata *udata, int *npas, 1105 int *page_shift, int *cqe_size) 1106 { 1107 struct mlx5_ib_resize_cq ucmd; 1108 struct ib_umem *umem; 1109 int err; 1110 int npages; 1111 1112 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1113 if (err) 1114 return err; 1115 1116 if (ucmd.reserved0 || ucmd.reserved1) 1117 return -EINVAL; 1118 1119 /* check multiplication overflow */ 1120 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1121 return -EINVAL; 1122 1123 umem = ib_umem_get(udata, ucmd.buf_addr, 1124 (size_t)ucmd.cqe_size * entries, 1125 IB_ACCESS_LOCAL_WRITE, 1); 1126 if (IS_ERR(umem)) { 1127 err = PTR_ERR(umem); 1128 return err; 1129 } 1130 1131 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift, 1132 npas, NULL); 1133 1134 cq->resize_umem = umem; 1135 *cqe_size = ucmd.cqe_size; 1136 1137 return 0; 1138 } 1139 1140 static void un_resize_user(struct mlx5_ib_cq *cq) 1141 { 1142 ib_umem_release(cq->resize_umem); 1143 } 1144 1145 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1146 int entries, int cqe_size) 1147 { 1148 int err; 1149 1150 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1151 if (!cq->resize_buf) 1152 return -ENOMEM; 1153 1154 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); 1155 if (err) 1156 goto ex; 1157 1158 init_cq_frag_buf(cq, cq->resize_buf); 1159 1160 return 0; 1161 1162 ex: 1163 kfree(cq->resize_buf); 1164 return err; 1165 } 1166 1167 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 1168 { 1169 free_cq_buf(dev, cq->resize_buf); 1170 cq->resize_buf = NULL; 1171 } 1172 1173 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1174 { 1175 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1176 struct mlx5_cqe64 *scqe64; 1177 struct mlx5_cqe64 *dcqe64; 1178 void *start_cqe; 1179 void *scqe; 1180 void *dcqe; 1181 int ssize; 1182 int dsize; 1183 int i; 1184 u8 sw_own; 1185 1186 ssize = cq->buf.cqe_size; 1187 dsize = cq->resize_buf->cqe_size; 1188 if (ssize != dsize) { 1189 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1190 return -EINVAL; 1191 } 1192 1193 i = cq->mcq.cons_index; 1194 scqe = get_sw_cqe(cq, i); 1195 scqe64 = ssize == 64 ? scqe : scqe + 64; 1196 start_cqe = scqe; 1197 if (!scqe) { 1198 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1199 return -EINVAL; 1200 } 1201 1202 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) { 1203 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, 1204 (i + 1) & cq->resize_buf->nent); 1205 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1206 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1207 memcpy(dcqe, scqe, dsize); 1208 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1209 1210 ++i; 1211 scqe = get_sw_cqe(cq, i); 1212 scqe64 = ssize == 64 ? scqe : scqe + 64; 1213 if (!scqe) { 1214 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1215 return -EINVAL; 1216 } 1217 1218 if (scqe == start_cqe) { 1219 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1220 cq->mcq.cqn); 1221 return -ENOMEM; 1222 } 1223 } 1224 ++cq->mcq.cons_index; 1225 return 0; 1226 } 1227 1228 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1229 { 1230 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1231 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1232 void *cqc; 1233 u32 *in; 1234 int err; 1235 int npas; 1236 __be64 *pas; 1237 int page_shift; 1238 int inlen; 1239 int uninitialized_var(cqe_size); 1240 unsigned long flags; 1241 1242 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1243 pr_info("Firmware does not support resize CQ\n"); 1244 return -ENOSYS; 1245 } 1246 1247 if (entries < 1 || 1248 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1249 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1250 entries, 1251 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1252 return -EINVAL; 1253 } 1254 1255 entries = roundup_pow_of_two(entries + 1); 1256 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1257 return -EINVAL; 1258 1259 if (entries == ibcq->cqe + 1) 1260 return 0; 1261 1262 mutex_lock(&cq->resize_mutex); 1263 if (udata) { 1264 err = resize_user(dev, cq, entries, udata, &npas, &page_shift, 1265 &cqe_size); 1266 } else { 1267 cqe_size = 64; 1268 err = resize_kernel(dev, cq, entries, cqe_size); 1269 if (!err) { 1270 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf; 1271 1272 npas = frag_buf->npages; 1273 page_shift = frag_buf->page_shift; 1274 } 1275 } 1276 1277 if (err) 1278 goto ex; 1279 1280 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1281 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1282 1283 in = kvzalloc(inlen, GFP_KERNEL); 1284 if (!in) { 1285 err = -ENOMEM; 1286 goto ex_resize; 1287 } 1288 1289 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1290 if (udata) 1291 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, 1292 pas, 0); 1293 else 1294 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas); 1295 1296 MLX5_SET(modify_cq_in, in, 1297 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1298 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1299 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1300 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1301 1302 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1303 1304 MLX5_SET(cqc, cqc, log_page_size, 1305 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1306 MLX5_SET(cqc, cqc, cqe_sz, 1307 cqe_sz_to_mlx_sz(cqe_size, 1308 cq->private_flags & 1309 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1310 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1311 1312 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1313 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1314 1315 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1316 if (err) 1317 goto ex_alloc; 1318 1319 if (udata) { 1320 cq->ibcq.cqe = entries - 1; 1321 ib_umem_release(cq->buf.umem); 1322 cq->buf.umem = cq->resize_umem; 1323 cq->resize_umem = NULL; 1324 } else { 1325 struct mlx5_ib_cq_buf tbuf; 1326 int resized = 0; 1327 1328 spin_lock_irqsave(&cq->lock, flags); 1329 if (cq->resize_buf) { 1330 err = copy_resize_cqes(cq); 1331 if (!err) { 1332 tbuf = cq->buf; 1333 cq->buf = *cq->resize_buf; 1334 kfree(cq->resize_buf); 1335 cq->resize_buf = NULL; 1336 resized = 1; 1337 } 1338 } 1339 cq->ibcq.cqe = entries - 1; 1340 spin_unlock_irqrestore(&cq->lock, flags); 1341 if (resized) 1342 free_cq_buf(dev, &tbuf); 1343 } 1344 mutex_unlock(&cq->resize_mutex); 1345 1346 kvfree(in); 1347 return 0; 1348 1349 ex_alloc: 1350 kvfree(in); 1351 1352 ex_resize: 1353 if (udata) 1354 un_resize_user(cq); 1355 else 1356 un_resize_kernel(dev, cq); 1357 ex: 1358 mutex_unlock(&cq->resize_mutex); 1359 return err; 1360 } 1361 1362 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq) 1363 { 1364 struct mlx5_ib_cq *cq; 1365 1366 if (!ibcq) 1367 return 128; 1368 1369 cq = to_mcq(ibcq); 1370 return cq->cqe_size; 1371 } 1372 1373 /* Called from atomic context */ 1374 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1375 { 1376 struct mlx5_ib_wc *soft_wc; 1377 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1378 unsigned long flags; 1379 1380 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1381 if (!soft_wc) 1382 return -ENOMEM; 1383 1384 soft_wc->wc = *wc; 1385 spin_lock_irqsave(&cq->lock, flags); 1386 list_add_tail(&soft_wc->list, &cq->wc_list); 1387 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1388 wc->status != IB_WC_SUCCESS) { 1389 cq->notify_flags = 0; 1390 schedule_work(&cq->notify_work); 1391 } 1392 spin_unlock_irqrestore(&cq->lock, flags); 1393 1394 return 0; 1395 } 1396