1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kref.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/ib_cache.h> 37 #include "mlx5_ib.h" 38 #include "srq.h" 39 40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe) 41 { 42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 43 44 ibcq->comp_handler(ibcq, ibcq->cq_context); 45 } 46 47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) 48 { 49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 51 struct ib_cq *ibcq = &cq->ibcq; 52 struct ib_event event; 53 54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 56 type, mcq->cqn); 57 return; 58 } 59 60 if (ibcq->event_handler) { 61 event.device = &dev->ib_dev; 62 event.event = IB_EVENT_CQ_ERR; 63 event.element.cq = ibcq; 64 ibcq->event_handler(&event, ibcq->cq_context); 65 } 66 } 67 68 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 69 { 70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); 71 } 72 73 static u8 sw_ownership_bit(int n, int nent) 74 { 75 return (n & nent) ? 1 : 0; 76 } 77 78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 79 { 80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 81 struct mlx5_cqe64 *cqe64; 82 83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 84 85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && 86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 87 return cqe; 88 } else { 89 return NULL; 90 } 91 } 92 93 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 94 { 95 return get_sw_cqe(cq, cq->mcq.cons_index); 96 } 97 98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 99 { 100 switch (wq->wr_data[idx]) { 101 case MLX5_IB_WR_UMR: 102 return 0; 103 104 case IB_WR_LOCAL_INV: 105 return IB_WC_LOCAL_INV; 106 107 case IB_WR_REG_MR: 108 return IB_WC_REG_MR; 109 110 default: 111 pr_warn("unknown completion status\n"); 112 return 0; 113 } 114 } 115 116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 117 struct mlx5_ib_wq *wq, int idx) 118 { 119 wc->wc_flags = 0; 120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 121 case MLX5_OPCODE_RDMA_WRITE_IMM: 122 wc->wc_flags |= IB_WC_WITH_IMM; 123 /* fall through */ 124 case MLX5_OPCODE_RDMA_WRITE: 125 wc->opcode = IB_WC_RDMA_WRITE; 126 break; 127 case MLX5_OPCODE_SEND_IMM: 128 wc->wc_flags |= IB_WC_WITH_IMM; 129 /* fall through */ 130 case MLX5_OPCODE_SEND: 131 case MLX5_OPCODE_SEND_INVAL: 132 wc->opcode = IB_WC_SEND; 133 break; 134 case MLX5_OPCODE_RDMA_READ: 135 wc->opcode = IB_WC_RDMA_READ; 136 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 137 break; 138 case MLX5_OPCODE_ATOMIC_CS: 139 wc->opcode = IB_WC_COMP_SWAP; 140 wc->byte_len = 8; 141 break; 142 case MLX5_OPCODE_ATOMIC_FA: 143 wc->opcode = IB_WC_FETCH_ADD; 144 wc->byte_len = 8; 145 break; 146 case MLX5_OPCODE_ATOMIC_MASKED_CS: 147 wc->opcode = IB_WC_MASKED_COMP_SWAP; 148 wc->byte_len = 8; 149 break; 150 case MLX5_OPCODE_ATOMIC_MASKED_FA: 151 wc->opcode = IB_WC_MASKED_FETCH_ADD; 152 wc->byte_len = 8; 153 break; 154 case MLX5_OPCODE_UMR: 155 wc->opcode = get_umr_comp(wq, idx); 156 break; 157 } 158 } 159 160 enum { 161 MLX5_GRH_IN_BUFFER = 1, 162 MLX5_GRH_IN_CQE = 2, 163 }; 164 165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 166 struct mlx5_ib_qp *qp) 167 { 168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 170 struct mlx5_ib_srq *srq; 171 struct mlx5_ib_wq *wq; 172 u16 wqe_ctr; 173 u8 roce_packet_type; 174 bool vlan_present; 175 u8 g; 176 177 if (qp->ibqp.srq || qp->ibqp.xrcd) { 178 struct mlx5_core_srq *msrq = NULL; 179 180 if (qp->ibqp.xrcd) { 181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn)); 182 srq = to_mibsrq(msrq); 183 } else { 184 srq = to_msrq(qp->ibqp.srq); 185 } 186 if (srq) { 187 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 188 wc->wr_id = srq->wrid[wqe_ctr]; 189 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 190 if (msrq) 191 mlx5_core_res_put(&msrq->common); 192 } 193 } else { 194 wq = &qp->rq; 195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 196 ++wq->tail; 197 } 198 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 199 200 switch (get_cqe_opcode(cqe)) { 201 case MLX5_CQE_RESP_WR_IMM: 202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 203 wc->wc_flags = IB_WC_WITH_IMM; 204 wc->ex.imm_data = cqe->imm_inval_pkey; 205 break; 206 case MLX5_CQE_RESP_SEND: 207 wc->opcode = IB_WC_RECV; 208 wc->wc_flags = IB_WC_IP_CSUM_OK; 209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 210 (cqe->hds_ip_ext & CQE_L4_OK)))) 211 wc->wc_flags = 0; 212 break; 213 case MLX5_CQE_RESP_SEND_IMM: 214 wc->opcode = IB_WC_RECV; 215 wc->wc_flags = IB_WC_WITH_IMM; 216 wc->ex.imm_data = cqe->imm_inval_pkey; 217 break; 218 case MLX5_CQE_RESP_SEND_INV: 219 wc->opcode = IB_WC_RECV; 220 wc->wc_flags = IB_WC_WITH_INVALIDATE; 221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey); 222 break; 223 } 224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 225 wc->dlid_path_bits = cqe->ml_path; 226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 227 wc->wc_flags |= g ? IB_WC_GRH : 0; 228 if (unlikely(is_qp1(qp->ibqp.qp_type))) { 229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff; 230 231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 232 &wc->pkey_index); 233 } else { 234 wc->pkey_index = 0; 235 } 236 237 if (ll != IB_LINK_LAYER_ETHERNET) { 238 wc->slid = be16_to_cpu(cqe->slid); 239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 240 return; 241 } 242 243 wc->slid = 0; 244 vlan_present = cqe->l4_l3_hdr_type & 0x1; 245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 246 if (vlan_present) { 247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 249 wc->wc_flags |= IB_WC_WITH_VLAN; 250 } else { 251 wc->sl = 0; 252 } 253 254 switch (roce_packet_type) { 255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 256 wc->network_hdr_type = RDMA_NETWORK_IB; 257 break; 258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 259 wc->network_hdr_type = RDMA_NETWORK_IPV6; 260 break; 261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 262 wc->network_hdr_type = RDMA_NETWORK_IPV4; 263 break; 264 } 265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 266 } 267 268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 269 { 270 mlx5_ib_warn(dev, "dump error cqe\n"); 271 mlx5_dump_err_cqe(dev->mdev, cqe); 272 } 273 274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 275 struct mlx5_err_cqe *cqe, 276 struct ib_wc *wc) 277 { 278 int dump = 1; 279 280 switch (cqe->syndrome) { 281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 282 wc->status = IB_WC_LOC_LEN_ERR; 283 break; 284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 285 wc->status = IB_WC_LOC_QP_OP_ERR; 286 break; 287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 288 wc->status = IB_WC_LOC_PROT_ERR; 289 break; 290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 291 dump = 0; 292 wc->status = IB_WC_WR_FLUSH_ERR; 293 break; 294 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 295 wc->status = IB_WC_MW_BIND_ERR; 296 break; 297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 298 wc->status = IB_WC_BAD_RESP_ERR; 299 break; 300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 301 wc->status = IB_WC_LOC_ACCESS_ERR; 302 break; 303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 304 wc->status = IB_WC_REM_INV_REQ_ERR; 305 break; 306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 307 wc->status = IB_WC_REM_ACCESS_ERR; 308 break; 309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 310 wc->status = IB_WC_REM_OP_ERR; 311 break; 312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 313 wc->status = IB_WC_RETRY_EXC_ERR; 314 dump = 0; 315 break; 316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 317 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 318 dump = 0; 319 break; 320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 321 wc->status = IB_WC_REM_ABORT_ERR; 322 break; 323 default: 324 wc->status = IB_WC_GENERAL_ERR; 325 break; 326 } 327 328 wc->vendor_err = cqe->vendor_err_synd; 329 if (dump) 330 dump_cqe(dev, cqe); 331 } 332 333 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 334 u16 tail, u16 head) 335 { 336 u16 idx; 337 338 do { 339 idx = tail & (qp->sq.wqe_cnt - 1); 340 if (idx == head) 341 break; 342 343 tail = qp->sq.w_list[idx].next; 344 } while (1); 345 tail = qp->sq.w_list[idx].next; 346 qp->sq.last_poll = tail; 347 } 348 349 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 350 { 351 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf); 352 } 353 354 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 355 struct ib_sig_err *item) 356 { 357 u16 syndrome = be16_to_cpu(cqe->syndrome); 358 359 #define GUARD_ERR (1 << 13) 360 #define APPTAG_ERR (1 << 12) 361 #define REFTAG_ERR (1 << 11) 362 363 if (syndrome & GUARD_ERR) { 364 item->err_type = IB_SIG_BAD_GUARD; 365 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 366 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 367 } else 368 if (syndrome & REFTAG_ERR) { 369 item->err_type = IB_SIG_BAD_REFTAG; 370 item->expected = be32_to_cpu(cqe->expected_reftag); 371 item->actual = be32_to_cpu(cqe->actual_reftag); 372 } else 373 if (syndrome & APPTAG_ERR) { 374 item->err_type = IB_SIG_BAD_APPTAG; 375 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 376 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 377 } else { 378 pr_err("Got signature completion error with bad syndrome %04x\n", 379 syndrome); 380 } 381 382 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 383 item->key = be32_to_cpu(cqe->mkey); 384 } 385 386 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc, 387 int *npolled, bool is_send) 388 { 389 struct mlx5_ib_wq *wq; 390 unsigned int cur; 391 int np; 392 int i; 393 394 wq = (is_send) ? &qp->sq : &qp->rq; 395 cur = wq->head - wq->tail; 396 np = *npolled; 397 398 if (cur == 0) 399 return; 400 401 for (i = 0; i < cur && np < num_entries; i++) { 402 unsigned int idx; 403 404 idx = (is_send) ? wq->last_poll : wq->tail; 405 idx &= (wq->wqe_cnt - 1); 406 wc->wr_id = wq->wrid[idx]; 407 wc->status = IB_WC_WR_FLUSH_ERR; 408 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 409 wq->tail++; 410 if (is_send) 411 wq->last_poll = wq->w_list[idx].next; 412 np++; 413 wc->qp = &qp->ibqp; 414 wc++; 415 } 416 *npolled = np; 417 } 418 419 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 420 struct ib_wc *wc, int *npolled) 421 { 422 struct mlx5_ib_qp *qp; 423 424 *npolled = 0; 425 /* Find uncompleted WQEs belonging to that cq and return mmics ones */ 426 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 427 sw_comp(qp, num_entries, wc + *npolled, npolled, true); 428 if (*npolled >= num_entries) 429 return; 430 } 431 432 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 433 sw_comp(qp, num_entries, wc + *npolled, npolled, false); 434 if (*npolled >= num_entries) 435 return; 436 } 437 } 438 439 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 440 struct mlx5_ib_qp **cur_qp, 441 struct ib_wc *wc) 442 { 443 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 444 struct mlx5_err_cqe *err_cqe; 445 struct mlx5_cqe64 *cqe64; 446 struct mlx5_core_qp *mqp; 447 struct mlx5_ib_wq *wq; 448 uint8_t opcode; 449 uint32_t qpn; 450 u16 wqe_ctr; 451 void *cqe; 452 int idx; 453 454 repoll: 455 cqe = next_cqe_sw(cq); 456 if (!cqe) 457 return -EAGAIN; 458 459 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 460 461 ++cq->mcq.cons_index; 462 463 /* Make sure we read CQ entry contents after we've checked the 464 * ownership bit. 465 */ 466 rmb(); 467 468 opcode = get_cqe_opcode(cqe64); 469 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 470 if (likely(cq->resize_buf)) { 471 free_cq_buf(dev, &cq->buf); 472 cq->buf = *cq->resize_buf; 473 kfree(cq->resize_buf); 474 cq->resize_buf = NULL; 475 goto repoll; 476 } else { 477 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 478 } 479 } 480 481 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 482 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 483 /* We do not have to take the QP table lock here, 484 * because CQs will be locked while QPs are removed 485 * from the table. 486 */ 487 mqp = __mlx5_qp_lookup(dev->mdev, qpn); 488 *cur_qp = to_mibqp(mqp); 489 } 490 491 wc->qp = &(*cur_qp)->ibqp; 492 switch (opcode) { 493 case MLX5_CQE_REQ: 494 wq = &(*cur_qp)->sq; 495 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 496 idx = wqe_ctr & (wq->wqe_cnt - 1); 497 handle_good_req(wc, cqe64, wq, idx); 498 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx); 499 wc->wr_id = wq->wrid[idx]; 500 wq->tail = wq->wqe_head[idx] + 1; 501 wc->status = IB_WC_SUCCESS; 502 break; 503 case MLX5_CQE_RESP_WR_IMM: 504 case MLX5_CQE_RESP_SEND: 505 case MLX5_CQE_RESP_SEND_IMM: 506 case MLX5_CQE_RESP_SEND_INV: 507 handle_responder(wc, cqe64, *cur_qp); 508 wc->status = IB_WC_SUCCESS; 509 break; 510 case MLX5_CQE_RESIZE_CQ: 511 break; 512 case MLX5_CQE_REQ_ERR: 513 case MLX5_CQE_RESP_ERR: 514 err_cqe = (struct mlx5_err_cqe *)cqe64; 515 mlx5_handle_error_cqe(dev, err_cqe, wc); 516 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 517 opcode == MLX5_CQE_REQ_ERR ? 518 "Requestor" : "Responder", cq->mcq.cqn); 519 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 520 err_cqe->syndrome, err_cqe->vendor_err_synd); 521 if (opcode == MLX5_CQE_REQ_ERR) { 522 wq = &(*cur_qp)->sq; 523 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 524 idx = wqe_ctr & (wq->wqe_cnt - 1); 525 wc->wr_id = wq->wrid[idx]; 526 wq->tail = wq->wqe_head[idx] + 1; 527 } else { 528 struct mlx5_ib_srq *srq; 529 530 if ((*cur_qp)->ibqp.srq) { 531 srq = to_msrq((*cur_qp)->ibqp.srq); 532 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 533 wc->wr_id = srq->wrid[wqe_ctr]; 534 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 535 } else { 536 wq = &(*cur_qp)->rq; 537 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 538 ++wq->tail; 539 } 540 } 541 break; 542 case MLX5_CQE_SIG_ERR: { 543 struct mlx5_sig_err_cqe *sig_err_cqe = 544 (struct mlx5_sig_err_cqe *)cqe64; 545 struct mlx5_core_sig_ctx *sig; 546 547 xa_lock(&dev->sig_mrs); 548 sig = xa_load(&dev->sig_mrs, 549 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 550 get_sig_err_item(sig_err_cqe, &sig->err_item); 551 sig->sig_err_exists = true; 552 sig->sigerr_count++; 553 554 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 555 cq->mcq.cqn, sig->err_item.key, 556 sig->err_item.err_type, 557 sig->err_item.sig_err_offset, 558 sig->err_item.expected, 559 sig->err_item.actual); 560 561 xa_unlock(&dev->sig_mrs); 562 goto repoll; 563 } 564 } 565 566 return 0; 567 } 568 569 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 570 struct ib_wc *wc, bool is_fatal_err) 571 { 572 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 573 struct mlx5_ib_wc *soft_wc, *next; 574 int npolled = 0; 575 576 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 577 if (npolled >= num_entries) 578 break; 579 580 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 581 cq->mcq.cqn); 582 583 if (unlikely(is_fatal_err)) { 584 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR; 585 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 586 } 587 wc[npolled++] = soft_wc->wc; 588 list_del(&soft_wc->list); 589 kfree(soft_wc); 590 } 591 592 return npolled; 593 } 594 595 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 596 { 597 struct mlx5_ib_cq *cq = to_mcq(ibcq); 598 struct mlx5_ib_qp *cur_qp = NULL; 599 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 600 struct mlx5_core_dev *mdev = dev->mdev; 601 unsigned long flags; 602 int soft_polled = 0; 603 int npolled; 604 605 spin_lock_irqsave(&cq->lock, flags); 606 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 607 /* make sure no soft wqe's are waiting */ 608 if (unlikely(!list_empty(&cq->wc_list))) 609 soft_polled = poll_soft_wc(cq, num_entries, wc, true); 610 611 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled, 612 wc + soft_polled, &npolled); 613 goto out; 614 } 615 616 if (unlikely(!list_empty(&cq->wc_list))) 617 soft_polled = poll_soft_wc(cq, num_entries, wc, false); 618 619 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 620 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 621 break; 622 } 623 624 if (npolled) 625 mlx5_cq_set_ci(&cq->mcq); 626 out: 627 spin_unlock_irqrestore(&cq->lock, flags); 628 629 return soft_polled + npolled; 630 } 631 632 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 633 { 634 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 635 struct mlx5_ib_cq *cq = to_mcq(ibcq); 636 void __iomem *uar_page = mdev->priv.uar->map; 637 unsigned long irq_flags; 638 int ret = 0; 639 640 spin_lock_irqsave(&cq->lock, irq_flags); 641 if (cq->notify_flags != IB_CQ_NEXT_COMP) 642 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 643 644 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 645 ret = 1; 646 spin_unlock_irqrestore(&cq->lock, irq_flags); 647 648 mlx5_cq_arm(&cq->mcq, 649 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 650 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 651 uar_page, to_mcq(ibcq)->mcq.cons_index); 652 653 return ret; 654 } 655 656 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, 657 struct mlx5_ib_cq_buf *buf, 658 int nent, 659 int cqe_size) 660 { 661 struct mlx5_frag_buf *frag_buf = &buf->frag_buf; 662 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); 663 u8 log_wq_sz = ilog2(cqe_size); 664 int err; 665 666 err = mlx5_frag_buf_alloc_node(dev->mdev, 667 nent * cqe_size, 668 frag_buf, 669 dev->mdev->priv.numa_node); 670 if (err) 671 return err; 672 673 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); 674 675 buf->cqe_size = cqe_size; 676 buf->nent = nent; 677 678 return 0; 679 } 680 681 enum { 682 MLX5_CQE_RES_FORMAT_HASH = 0, 683 MLX5_CQE_RES_FORMAT_CSUM = 1, 684 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3, 685 }; 686 687 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format) 688 { 689 switch (format) { 690 case MLX5_IB_CQE_RES_FORMAT_HASH: 691 return MLX5_CQE_RES_FORMAT_HASH; 692 case MLX5_IB_CQE_RES_FORMAT_CSUM: 693 return MLX5_CQE_RES_FORMAT_CSUM; 694 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX: 695 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 696 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX; 697 return -EOPNOTSUPP; 698 default: 699 return -EINVAL; 700 } 701 } 702 703 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 704 struct mlx5_ib_cq *cq, int entries, u32 **cqb, 705 int *cqe_size, int *index, int *inlen) 706 { 707 struct mlx5_ib_create_cq ucmd = {}; 708 size_t ucmdlen; 709 int page_shift; 710 __be64 *pas; 711 int npages; 712 int ncont; 713 void *cqc; 714 int err; 715 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 716 udata, struct mlx5_ib_ucontext, ibucontext); 717 718 ucmdlen = udata->inlen < sizeof(ucmd) ? 719 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd); 720 721 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 722 return -EFAULT; 723 724 if (ucmdlen == sizeof(ucmd) && 725 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD))) 726 return -EINVAL; 727 728 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 729 return -EINVAL; 730 731 *cqe_size = ucmd.cqe_size; 732 733 cq->buf.umem = 734 ib_umem_get(&dev->ib_dev, ucmd.buf_addr, 735 entries * ucmd.cqe_size, IB_ACCESS_LOCAL_WRITE); 736 if (IS_ERR(cq->buf.umem)) { 737 err = PTR_ERR(cq->buf.umem); 738 return err; 739 } 740 741 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db); 742 if (err) 743 goto err_umem; 744 745 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift, 746 &ncont, NULL); 747 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 748 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 749 750 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 751 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 752 *cqb = kvzalloc(*inlen, GFP_KERNEL); 753 if (!*cqb) { 754 err = -ENOMEM; 755 goto err_db; 756 } 757 758 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 759 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0); 760 761 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 762 MLX5_SET(cqc, cqc, log_page_size, 763 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 764 765 *index = context->bfregi.sys_pages[0]; 766 767 if (ucmd.cqe_comp_en == 1) { 768 int mini_cqe_format; 769 770 if (!((*cqe_size == 128 && 771 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || 772 (*cqe_size == 64 && 773 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { 774 err = -EOPNOTSUPP; 775 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 776 *cqe_size); 777 goto err_cqb; 778 } 779 780 mini_cqe_format = 781 mini_cqe_res_format_to_hw(dev, 782 ucmd.cqe_comp_res_format); 783 if (mini_cqe_format < 0) { 784 err = mini_cqe_format; 785 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n", 786 ucmd.cqe_comp_res_format, err); 787 goto err_cqb; 788 } 789 790 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 791 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); 792 } 793 794 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) { 795 if (*cqe_size != 128 || 796 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { 797 err = -EOPNOTSUPP; 798 mlx5_ib_warn(dev, 799 "CQE padding is not supported for CQE size of %dB!\n", 800 *cqe_size); 801 goto err_cqb; 802 } 803 804 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD; 805 } 806 807 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid); 808 return 0; 809 810 err_cqb: 811 kvfree(*cqb); 812 813 err_db: 814 mlx5_ib_db_unmap_user(context, &cq->db); 815 816 err_umem: 817 ib_umem_release(cq->buf.umem); 818 return err; 819 } 820 821 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata) 822 { 823 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 824 udata, struct mlx5_ib_ucontext, ibucontext); 825 826 mlx5_ib_db_unmap_user(context, &cq->db); 827 ib_umem_release(cq->buf.umem); 828 } 829 830 static void init_cq_frag_buf(struct mlx5_ib_cq *cq, 831 struct mlx5_ib_cq_buf *buf) 832 { 833 int i; 834 void *cqe; 835 struct mlx5_cqe64 *cqe64; 836 837 for (i = 0; i < buf->nent; i++) { 838 cqe = get_cqe(cq, i); 839 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 840 cqe64->op_own = MLX5_CQE_INVALID << 4; 841 } 842 } 843 844 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 845 int entries, int cqe_size, 846 u32 **cqb, int *index, int *inlen) 847 { 848 __be64 *pas; 849 void *cqc; 850 int err; 851 852 err = mlx5_db_alloc(dev->mdev, &cq->db); 853 if (err) 854 return err; 855 856 cq->mcq.set_ci_db = cq->db.db; 857 cq->mcq.arm_db = cq->db.db + 1; 858 cq->mcq.cqe_sz = cqe_size; 859 860 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); 861 if (err) 862 goto err_db; 863 864 init_cq_frag_buf(cq, &cq->buf); 865 866 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 867 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * 868 cq->buf.frag_buf.npages; 869 *cqb = kvzalloc(*inlen, GFP_KERNEL); 870 if (!*cqb) { 871 err = -ENOMEM; 872 goto err_buf; 873 } 874 875 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 876 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); 877 878 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 879 MLX5_SET(cqc, cqc, log_page_size, 880 cq->buf.frag_buf.page_shift - 881 MLX5_ADAPTER_PAGE_SHIFT); 882 883 *index = dev->mdev->priv.uar->index; 884 885 return 0; 886 887 err_buf: 888 free_cq_buf(dev, &cq->buf); 889 890 err_db: 891 mlx5_db_free(dev->mdev, &cq->db); 892 return err; 893 } 894 895 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 896 { 897 free_cq_buf(dev, &cq->buf); 898 mlx5_db_free(dev->mdev, &cq->db); 899 } 900 901 static void notify_soft_wc_handler(struct work_struct *work) 902 { 903 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 904 notify_work); 905 906 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 907 } 908 909 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 910 struct ib_udata *udata) 911 { 912 struct ib_device *ibdev = ibcq->device; 913 int entries = attr->cqe; 914 int vector = attr->comp_vector; 915 struct mlx5_ib_dev *dev = to_mdev(ibdev); 916 struct mlx5_ib_cq *cq = to_mcq(ibcq); 917 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 918 int uninitialized_var(index); 919 int uninitialized_var(inlen); 920 u32 *cqb = NULL; 921 void *cqc; 922 int cqe_size; 923 unsigned int irqn; 924 int eqn; 925 int err; 926 927 if (entries < 0 || 928 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 929 return -EINVAL; 930 931 if (check_cq_create_flags(attr->flags)) 932 return -EOPNOTSUPP; 933 934 entries = roundup_pow_of_two(entries + 1); 935 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 936 return -EINVAL; 937 938 cq->ibcq.cqe = entries - 1; 939 mutex_init(&cq->resize_mutex); 940 spin_lock_init(&cq->lock); 941 cq->resize_buf = NULL; 942 cq->resize_umem = NULL; 943 cq->create_flags = attr->flags; 944 INIT_LIST_HEAD(&cq->list_send_qp); 945 INIT_LIST_HEAD(&cq->list_recv_qp); 946 947 if (udata) { 948 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size, 949 &index, &inlen); 950 if (err) 951 return err; 952 } else { 953 cqe_size = cache_line_size() == 128 ? 128 : 64; 954 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 955 &index, &inlen); 956 if (err) 957 return err; 958 959 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 960 } 961 962 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); 963 if (err) 964 goto err_cqb; 965 966 cq->cqe_size = cqe_size; 967 968 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 969 MLX5_SET(cqc, cqc, cqe_sz, 970 cqe_sz_to_mlx_sz(cqe_size, 971 cq->private_flags & 972 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 973 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 974 MLX5_SET(cqc, cqc, uar_page, index); 975 MLX5_SET(cqc, cqc, c_eqn, eqn); 976 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 977 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) 978 MLX5_SET(cqc, cqc, oi, 1); 979 980 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out)); 981 if (err) 982 goto err_cqb; 983 984 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 985 cq->mcq.irqn = irqn; 986 if (udata) 987 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; 988 else 989 cq->mcq.comp = mlx5_ib_cq_comp; 990 cq->mcq.event = mlx5_ib_cq_event; 991 992 INIT_LIST_HEAD(&cq->wc_list); 993 994 if (udata) 995 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 996 err = -EFAULT; 997 goto err_cmd; 998 } 999 1000 1001 kvfree(cqb); 1002 return 0; 1003 1004 err_cmd: 1005 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 1006 1007 err_cqb: 1008 kvfree(cqb); 1009 if (udata) 1010 destroy_cq_user(cq, udata); 1011 else 1012 destroy_cq_kernel(dev, cq); 1013 return err; 1014 } 1015 1016 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 1017 { 1018 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1019 struct mlx5_ib_cq *mcq = to_mcq(cq); 1020 1021 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 1022 if (udata) 1023 destroy_cq_user(mcq, udata); 1024 else 1025 destroy_cq_kernel(dev, mcq); 1026 } 1027 1028 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1029 { 1030 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1031 } 1032 1033 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1034 { 1035 struct mlx5_cqe64 *cqe64, *dest64; 1036 void *cqe, *dest; 1037 u32 prod_index; 1038 int nfreed = 0; 1039 u8 owner_bit; 1040 1041 if (!cq) 1042 return; 1043 1044 /* First we need to find the current producer index, so we 1045 * know where to start cleaning from. It doesn't matter if HW 1046 * adds new entries after this loop -- the QP we're worried 1047 * about is already in RESET, so the new entries won't come 1048 * from our QP and therefore don't need to be checked. 1049 */ 1050 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1051 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1052 break; 1053 1054 /* Now sweep backwards through the CQ, removing CQ entries 1055 * that match our QP by copying older entries on top of them. 1056 */ 1057 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1058 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1059 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1060 if (is_equal_rsn(cqe64, rsn)) { 1061 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1062 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1063 ++nfreed; 1064 } else if (nfreed) { 1065 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1066 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1067 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1068 memcpy(dest, cqe, cq->mcq.cqe_sz); 1069 dest64->op_own = owner_bit | 1070 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1071 } 1072 } 1073 1074 if (nfreed) { 1075 cq->mcq.cons_index += nfreed; 1076 /* Make sure update of buffer contents is done before 1077 * updating consumer index. 1078 */ 1079 wmb(); 1080 mlx5_cq_set_ci(&cq->mcq); 1081 } 1082 } 1083 1084 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1085 { 1086 if (!cq) 1087 return; 1088 1089 spin_lock_irq(&cq->lock); 1090 __mlx5_ib_cq_clean(cq, qpn, srq); 1091 spin_unlock_irq(&cq->lock); 1092 } 1093 1094 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1095 { 1096 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1097 struct mlx5_ib_cq *mcq = to_mcq(cq); 1098 int err; 1099 1100 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1101 return -EOPNOTSUPP; 1102 1103 if (cq_period > MLX5_MAX_CQ_PERIOD) 1104 return -EINVAL; 1105 1106 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1107 cq_period, cq_count); 1108 if (err) 1109 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1110 1111 return err; 1112 } 1113 1114 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1115 int entries, struct ib_udata *udata, int *npas, 1116 int *page_shift, int *cqe_size) 1117 { 1118 struct mlx5_ib_resize_cq ucmd; 1119 struct ib_umem *umem; 1120 int err; 1121 int npages; 1122 1123 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1124 if (err) 1125 return err; 1126 1127 if (ucmd.reserved0 || ucmd.reserved1) 1128 return -EINVAL; 1129 1130 /* check multiplication overflow */ 1131 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1132 return -EINVAL; 1133 1134 umem = ib_umem_get(&dev->ib_dev, ucmd.buf_addr, 1135 (size_t)ucmd.cqe_size * entries, 1136 IB_ACCESS_LOCAL_WRITE); 1137 if (IS_ERR(umem)) { 1138 err = PTR_ERR(umem); 1139 return err; 1140 } 1141 1142 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift, 1143 npas, NULL); 1144 1145 cq->resize_umem = umem; 1146 *cqe_size = ucmd.cqe_size; 1147 1148 return 0; 1149 } 1150 1151 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1152 int entries, int cqe_size) 1153 { 1154 int err; 1155 1156 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1157 if (!cq->resize_buf) 1158 return -ENOMEM; 1159 1160 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); 1161 if (err) 1162 goto ex; 1163 1164 init_cq_frag_buf(cq, cq->resize_buf); 1165 1166 return 0; 1167 1168 ex: 1169 kfree(cq->resize_buf); 1170 return err; 1171 } 1172 1173 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1174 { 1175 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1176 struct mlx5_cqe64 *scqe64; 1177 struct mlx5_cqe64 *dcqe64; 1178 void *start_cqe; 1179 void *scqe; 1180 void *dcqe; 1181 int ssize; 1182 int dsize; 1183 int i; 1184 u8 sw_own; 1185 1186 ssize = cq->buf.cqe_size; 1187 dsize = cq->resize_buf->cqe_size; 1188 if (ssize != dsize) { 1189 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1190 return -EINVAL; 1191 } 1192 1193 i = cq->mcq.cons_index; 1194 scqe = get_sw_cqe(cq, i); 1195 scqe64 = ssize == 64 ? scqe : scqe + 64; 1196 start_cqe = scqe; 1197 if (!scqe) { 1198 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1199 return -EINVAL; 1200 } 1201 1202 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) { 1203 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, 1204 (i + 1) & cq->resize_buf->nent); 1205 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1206 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1207 memcpy(dcqe, scqe, dsize); 1208 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1209 1210 ++i; 1211 scqe = get_sw_cqe(cq, i); 1212 scqe64 = ssize == 64 ? scqe : scqe + 64; 1213 if (!scqe) { 1214 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1215 return -EINVAL; 1216 } 1217 1218 if (scqe == start_cqe) { 1219 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1220 cq->mcq.cqn); 1221 return -ENOMEM; 1222 } 1223 } 1224 ++cq->mcq.cons_index; 1225 return 0; 1226 } 1227 1228 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1229 { 1230 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1231 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1232 void *cqc; 1233 u32 *in; 1234 int err; 1235 int npas; 1236 __be64 *pas; 1237 int page_shift; 1238 int inlen; 1239 int uninitialized_var(cqe_size); 1240 unsigned long flags; 1241 1242 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1243 pr_info("Firmware does not support resize CQ\n"); 1244 return -ENOSYS; 1245 } 1246 1247 if (entries < 1 || 1248 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1249 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1250 entries, 1251 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1252 return -EINVAL; 1253 } 1254 1255 entries = roundup_pow_of_two(entries + 1); 1256 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1257 return -EINVAL; 1258 1259 if (entries == ibcq->cqe + 1) 1260 return 0; 1261 1262 mutex_lock(&cq->resize_mutex); 1263 if (udata) { 1264 err = resize_user(dev, cq, entries, udata, &npas, &page_shift, 1265 &cqe_size); 1266 } else { 1267 cqe_size = 64; 1268 err = resize_kernel(dev, cq, entries, cqe_size); 1269 if (!err) { 1270 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf; 1271 1272 npas = frag_buf->npages; 1273 page_shift = frag_buf->page_shift; 1274 } 1275 } 1276 1277 if (err) 1278 goto ex; 1279 1280 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1281 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1282 1283 in = kvzalloc(inlen, GFP_KERNEL); 1284 if (!in) { 1285 err = -ENOMEM; 1286 goto ex_resize; 1287 } 1288 1289 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1290 if (udata) 1291 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, 1292 pas, 0); 1293 else 1294 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas); 1295 1296 MLX5_SET(modify_cq_in, in, 1297 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1298 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1299 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1300 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1301 1302 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1303 1304 MLX5_SET(cqc, cqc, log_page_size, 1305 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1306 MLX5_SET(cqc, cqc, cqe_sz, 1307 cqe_sz_to_mlx_sz(cqe_size, 1308 cq->private_flags & 1309 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1310 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1311 1312 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1313 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1314 1315 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1316 if (err) 1317 goto ex_alloc; 1318 1319 if (udata) { 1320 cq->ibcq.cqe = entries - 1; 1321 ib_umem_release(cq->buf.umem); 1322 cq->buf.umem = cq->resize_umem; 1323 cq->resize_umem = NULL; 1324 } else { 1325 struct mlx5_ib_cq_buf tbuf; 1326 int resized = 0; 1327 1328 spin_lock_irqsave(&cq->lock, flags); 1329 if (cq->resize_buf) { 1330 err = copy_resize_cqes(cq); 1331 if (!err) { 1332 tbuf = cq->buf; 1333 cq->buf = *cq->resize_buf; 1334 kfree(cq->resize_buf); 1335 cq->resize_buf = NULL; 1336 resized = 1; 1337 } 1338 } 1339 cq->ibcq.cqe = entries - 1; 1340 spin_unlock_irqrestore(&cq->lock, flags); 1341 if (resized) 1342 free_cq_buf(dev, &tbuf); 1343 } 1344 mutex_unlock(&cq->resize_mutex); 1345 1346 kvfree(in); 1347 return 0; 1348 1349 ex_alloc: 1350 kvfree(in); 1351 1352 ex_resize: 1353 ib_umem_release(cq->resize_umem); 1354 if (!udata) { 1355 free_cq_buf(dev, cq->resize_buf); 1356 cq->resize_buf = NULL; 1357 } 1358 ex: 1359 mutex_unlock(&cq->resize_mutex); 1360 return err; 1361 } 1362 1363 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq) 1364 { 1365 struct mlx5_ib_cq *cq; 1366 1367 if (!ibcq) 1368 return 128; 1369 1370 cq = to_mcq(ibcq); 1371 return cq->cqe_size; 1372 } 1373 1374 /* Called from atomic context */ 1375 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1376 { 1377 struct mlx5_ib_wc *soft_wc; 1378 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1379 unsigned long flags; 1380 1381 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1382 if (!soft_wc) 1383 return -ENOMEM; 1384 1385 soft_wc->wc = *wc; 1386 spin_lock_irqsave(&cq->lock, flags); 1387 list_add_tail(&soft_wc->list, &cq->wc_list); 1388 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1389 wc->status != IB_WC_SUCCESS) { 1390 cq->notify_flags = 0; 1391 schedule_work(&cq->notify_work); 1392 } 1393 spin_unlock_irqrestore(&cq->lock, flags); 1394 1395 return 0; 1396 } 1397