1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kref.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_user_verbs.h> 36 #include <rdma/ib_cache.h> 37 #include "mlx5_ib.h" 38 #include "srq.h" 39 40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe) 41 { 42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 43 44 ibcq->comp_handler(ibcq, ibcq->cq_context); 45 } 46 47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) 48 { 49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 51 struct ib_cq *ibcq = &cq->ibcq; 52 struct ib_event event; 53 54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 56 type, mcq->cqn); 57 return; 58 } 59 60 if (ibcq->event_handler) { 61 event.device = &dev->ib_dev; 62 event.event = IB_EVENT_CQ_ERR; 63 event.element.cq = ibcq; 64 ibcq->event_handler(&event, ibcq->cq_context); 65 } 66 } 67 68 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 69 { 70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); 71 } 72 73 static u8 sw_ownership_bit(int n, int nent) 74 { 75 return (n & nent) ? 1 : 0; 76 } 77 78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 79 { 80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 81 struct mlx5_cqe64 *cqe64; 82 83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 84 85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) && 86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 87 return cqe; 88 } else { 89 return NULL; 90 } 91 } 92 93 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 94 { 95 return get_sw_cqe(cq, cq->mcq.cons_index); 96 } 97 98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 99 { 100 switch (wq->wr_data[idx]) { 101 case MLX5_IB_WR_UMR: 102 return 0; 103 104 case IB_WR_LOCAL_INV: 105 return IB_WC_LOCAL_INV; 106 107 case IB_WR_REG_MR: 108 return IB_WC_REG_MR; 109 110 default: 111 pr_warn("unknown completion status\n"); 112 return 0; 113 } 114 } 115 116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 117 struct mlx5_ib_wq *wq, int idx) 118 { 119 wc->wc_flags = 0; 120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 121 case MLX5_OPCODE_RDMA_WRITE_IMM: 122 wc->wc_flags |= IB_WC_WITH_IMM; 123 /* fall through */ 124 case MLX5_OPCODE_RDMA_WRITE: 125 wc->opcode = IB_WC_RDMA_WRITE; 126 break; 127 case MLX5_OPCODE_SEND_IMM: 128 wc->wc_flags |= IB_WC_WITH_IMM; 129 /* fall through */ 130 case MLX5_OPCODE_SEND: 131 case MLX5_OPCODE_SEND_INVAL: 132 wc->opcode = IB_WC_SEND; 133 break; 134 case MLX5_OPCODE_RDMA_READ: 135 wc->opcode = IB_WC_RDMA_READ; 136 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 137 break; 138 case MLX5_OPCODE_ATOMIC_CS: 139 wc->opcode = IB_WC_COMP_SWAP; 140 wc->byte_len = 8; 141 break; 142 case MLX5_OPCODE_ATOMIC_FA: 143 wc->opcode = IB_WC_FETCH_ADD; 144 wc->byte_len = 8; 145 break; 146 case MLX5_OPCODE_ATOMIC_MASKED_CS: 147 wc->opcode = IB_WC_MASKED_COMP_SWAP; 148 wc->byte_len = 8; 149 break; 150 case MLX5_OPCODE_ATOMIC_MASKED_FA: 151 wc->opcode = IB_WC_MASKED_FETCH_ADD; 152 wc->byte_len = 8; 153 break; 154 case MLX5_OPCODE_UMR: 155 wc->opcode = get_umr_comp(wq, idx); 156 break; 157 } 158 } 159 160 enum { 161 MLX5_GRH_IN_BUFFER = 1, 162 MLX5_GRH_IN_CQE = 2, 163 }; 164 165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 166 struct mlx5_ib_qp *qp) 167 { 168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 170 struct mlx5_ib_srq *srq; 171 struct mlx5_ib_wq *wq; 172 u16 wqe_ctr; 173 u8 roce_packet_type; 174 bool vlan_present; 175 u8 g; 176 177 if (qp->ibqp.srq || qp->ibqp.xrcd) { 178 struct mlx5_core_srq *msrq = NULL; 179 180 if (qp->ibqp.xrcd) { 181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn)); 182 srq = to_mibsrq(msrq); 183 } else { 184 srq = to_msrq(qp->ibqp.srq); 185 } 186 if (srq) { 187 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 188 wc->wr_id = srq->wrid[wqe_ctr]; 189 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 190 if (msrq) 191 mlx5_core_res_put(&msrq->common); 192 } 193 } else { 194 wq = &qp->rq; 195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 196 ++wq->tail; 197 } 198 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 199 200 switch (get_cqe_opcode(cqe)) { 201 case MLX5_CQE_RESP_WR_IMM: 202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 203 wc->wc_flags = IB_WC_WITH_IMM; 204 wc->ex.imm_data = cqe->imm_inval_pkey; 205 break; 206 case MLX5_CQE_RESP_SEND: 207 wc->opcode = IB_WC_RECV; 208 wc->wc_flags = IB_WC_IP_CSUM_OK; 209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 210 (cqe->hds_ip_ext & CQE_L4_OK)))) 211 wc->wc_flags = 0; 212 break; 213 case MLX5_CQE_RESP_SEND_IMM: 214 wc->opcode = IB_WC_RECV; 215 wc->wc_flags = IB_WC_WITH_IMM; 216 wc->ex.imm_data = cqe->imm_inval_pkey; 217 break; 218 case MLX5_CQE_RESP_SEND_INV: 219 wc->opcode = IB_WC_RECV; 220 wc->wc_flags = IB_WC_WITH_INVALIDATE; 221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey); 222 break; 223 } 224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 225 wc->dlid_path_bits = cqe->ml_path; 226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 227 wc->wc_flags |= g ? IB_WC_GRH : 0; 228 if (unlikely(is_qp1(qp->ibqp.qp_type))) { 229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff; 230 231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 232 &wc->pkey_index); 233 } else { 234 wc->pkey_index = 0; 235 } 236 237 if (ll != IB_LINK_LAYER_ETHERNET) { 238 wc->slid = be16_to_cpu(cqe->slid); 239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 240 return; 241 } 242 243 wc->slid = 0; 244 vlan_present = cqe->l4_l3_hdr_type & 0x1; 245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 246 if (vlan_present) { 247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 249 wc->wc_flags |= IB_WC_WITH_VLAN; 250 } else { 251 wc->sl = 0; 252 } 253 254 switch (roce_packet_type) { 255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 256 wc->network_hdr_type = RDMA_NETWORK_IB; 257 break; 258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 259 wc->network_hdr_type = RDMA_NETWORK_IPV6; 260 break; 261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 262 wc->network_hdr_type = RDMA_NETWORK_IPV4; 263 break; 264 } 265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 266 } 267 268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 269 { 270 mlx5_ib_warn(dev, "dump error cqe\n"); 271 mlx5_dump_err_cqe(dev->mdev, cqe); 272 } 273 274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 275 struct mlx5_err_cqe *cqe, 276 struct ib_wc *wc) 277 { 278 int dump = 1; 279 280 switch (cqe->syndrome) { 281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 282 wc->status = IB_WC_LOC_LEN_ERR; 283 break; 284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 285 wc->status = IB_WC_LOC_QP_OP_ERR; 286 break; 287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 288 wc->status = IB_WC_LOC_PROT_ERR; 289 break; 290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 291 dump = 0; 292 wc->status = IB_WC_WR_FLUSH_ERR; 293 break; 294 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 295 wc->status = IB_WC_MW_BIND_ERR; 296 break; 297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 298 wc->status = IB_WC_BAD_RESP_ERR; 299 break; 300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 301 wc->status = IB_WC_LOC_ACCESS_ERR; 302 break; 303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 304 wc->status = IB_WC_REM_INV_REQ_ERR; 305 break; 306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 307 wc->status = IB_WC_REM_ACCESS_ERR; 308 break; 309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 310 wc->status = IB_WC_REM_OP_ERR; 311 break; 312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 313 wc->status = IB_WC_RETRY_EXC_ERR; 314 dump = 0; 315 break; 316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 317 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 318 dump = 0; 319 break; 320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 321 wc->status = IB_WC_REM_ABORT_ERR; 322 break; 323 default: 324 wc->status = IB_WC_GENERAL_ERR; 325 break; 326 } 327 328 wc->vendor_err = cqe->vendor_err_synd; 329 if (dump) 330 dump_cqe(dev, cqe); 331 } 332 333 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 334 { 335 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf); 336 } 337 338 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 339 struct ib_sig_err *item) 340 { 341 u16 syndrome = be16_to_cpu(cqe->syndrome); 342 343 #define GUARD_ERR (1 << 13) 344 #define APPTAG_ERR (1 << 12) 345 #define REFTAG_ERR (1 << 11) 346 347 if (syndrome & GUARD_ERR) { 348 item->err_type = IB_SIG_BAD_GUARD; 349 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 350 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 351 } else 352 if (syndrome & REFTAG_ERR) { 353 item->err_type = IB_SIG_BAD_REFTAG; 354 item->expected = be32_to_cpu(cqe->expected_reftag); 355 item->actual = be32_to_cpu(cqe->actual_reftag); 356 } else 357 if (syndrome & APPTAG_ERR) { 358 item->err_type = IB_SIG_BAD_APPTAG; 359 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 360 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 361 } else { 362 pr_err("Got signature completion error with bad syndrome %04x\n", 363 syndrome); 364 } 365 366 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 367 item->key = be32_to_cpu(cqe->mkey); 368 } 369 370 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc, 371 int *npolled, int is_send) 372 { 373 struct mlx5_ib_wq *wq; 374 unsigned int cur; 375 int np; 376 int i; 377 378 wq = (is_send) ? &qp->sq : &qp->rq; 379 cur = wq->head - wq->tail; 380 np = *npolled; 381 382 if (cur == 0) 383 return; 384 385 for (i = 0; i < cur && np < num_entries; i++) { 386 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 387 wc->status = IB_WC_WR_FLUSH_ERR; 388 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 389 wq->tail++; 390 np++; 391 wc->qp = &qp->ibqp; 392 wc++; 393 } 394 *npolled = np; 395 } 396 397 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 398 struct ib_wc *wc, int *npolled) 399 { 400 struct mlx5_ib_qp *qp; 401 402 *npolled = 0; 403 /* Find uncompleted WQEs belonging to that cq and return mmics ones */ 404 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 405 sw_comp(qp, num_entries, wc + *npolled, npolled, true); 406 if (*npolled >= num_entries) 407 return; 408 } 409 410 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 411 sw_comp(qp, num_entries, wc + *npolled, npolled, false); 412 if (*npolled >= num_entries) 413 return; 414 } 415 } 416 417 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 418 struct mlx5_ib_qp **cur_qp, 419 struct ib_wc *wc) 420 { 421 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 422 struct mlx5_err_cqe *err_cqe; 423 struct mlx5_cqe64 *cqe64; 424 struct mlx5_core_qp *mqp; 425 struct mlx5_ib_wq *wq; 426 uint8_t opcode; 427 uint32_t qpn; 428 u16 wqe_ctr; 429 void *cqe; 430 int idx; 431 432 repoll: 433 cqe = next_cqe_sw(cq); 434 if (!cqe) 435 return -EAGAIN; 436 437 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 438 439 ++cq->mcq.cons_index; 440 441 /* Make sure we read CQ entry contents after we've checked the 442 * ownership bit. 443 */ 444 rmb(); 445 446 opcode = get_cqe_opcode(cqe64); 447 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 448 if (likely(cq->resize_buf)) { 449 free_cq_buf(dev, &cq->buf); 450 cq->buf = *cq->resize_buf; 451 kfree(cq->resize_buf); 452 cq->resize_buf = NULL; 453 goto repoll; 454 } else { 455 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 456 } 457 } 458 459 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 460 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 461 /* We do not have to take the QP table lock here, 462 * because CQs will be locked while QPs are removed 463 * from the table. 464 */ 465 mqp = __mlx5_qp_lookup(dev->mdev, qpn); 466 *cur_qp = to_mibqp(mqp); 467 } 468 469 wc->qp = &(*cur_qp)->ibqp; 470 switch (opcode) { 471 case MLX5_CQE_REQ: 472 wq = &(*cur_qp)->sq; 473 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 474 idx = wqe_ctr & (wq->wqe_cnt - 1); 475 handle_good_req(wc, cqe64, wq, idx); 476 wc->wr_id = wq->wrid[idx]; 477 wq->tail = wq->wqe_head[idx] + 1; 478 wc->status = IB_WC_SUCCESS; 479 break; 480 case MLX5_CQE_RESP_WR_IMM: 481 case MLX5_CQE_RESP_SEND: 482 case MLX5_CQE_RESP_SEND_IMM: 483 case MLX5_CQE_RESP_SEND_INV: 484 handle_responder(wc, cqe64, *cur_qp); 485 wc->status = IB_WC_SUCCESS; 486 break; 487 case MLX5_CQE_RESIZE_CQ: 488 break; 489 case MLX5_CQE_REQ_ERR: 490 case MLX5_CQE_RESP_ERR: 491 err_cqe = (struct mlx5_err_cqe *)cqe64; 492 mlx5_handle_error_cqe(dev, err_cqe, wc); 493 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 494 opcode == MLX5_CQE_REQ_ERR ? 495 "Requestor" : "Responder", cq->mcq.cqn); 496 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 497 err_cqe->syndrome, err_cqe->vendor_err_synd); 498 if (opcode == MLX5_CQE_REQ_ERR) { 499 wq = &(*cur_qp)->sq; 500 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 501 idx = wqe_ctr & (wq->wqe_cnt - 1); 502 wc->wr_id = wq->wrid[idx]; 503 wq->tail = wq->wqe_head[idx] + 1; 504 } else { 505 struct mlx5_ib_srq *srq; 506 507 if ((*cur_qp)->ibqp.srq) { 508 srq = to_msrq((*cur_qp)->ibqp.srq); 509 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 510 wc->wr_id = srq->wrid[wqe_ctr]; 511 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 512 } else { 513 wq = &(*cur_qp)->rq; 514 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 515 ++wq->tail; 516 } 517 } 518 break; 519 case MLX5_CQE_SIG_ERR: { 520 struct mlx5_sig_err_cqe *sig_err_cqe = 521 (struct mlx5_sig_err_cqe *)cqe64; 522 struct mlx5_core_sig_ctx *sig; 523 524 xa_lock(&dev->sig_mrs); 525 sig = xa_load(&dev->sig_mrs, 526 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 527 get_sig_err_item(sig_err_cqe, &sig->err_item); 528 sig->sig_err_exists = true; 529 sig->sigerr_count++; 530 531 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 532 cq->mcq.cqn, sig->err_item.key, 533 sig->err_item.err_type, 534 sig->err_item.sig_err_offset, 535 sig->err_item.expected, 536 sig->err_item.actual); 537 538 xa_unlock(&dev->sig_mrs); 539 goto repoll; 540 } 541 } 542 543 return 0; 544 } 545 546 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 547 struct ib_wc *wc, bool is_fatal_err) 548 { 549 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 550 struct mlx5_ib_wc *soft_wc, *next; 551 int npolled = 0; 552 553 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 554 if (npolled >= num_entries) 555 break; 556 557 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 558 cq->mcq.cqn); 559 560 if (unlikely(is_fatal_err)) { 561 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR; 562 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 563 } 564 wc[npolled++] = soft_wc->wc; 565 list_del(&soft_wc->list); 566 kfree(soft_wc); 567 } 568 569 return npolled; 570 } 571 572 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 573 { 574 struct mlx5_ib_cq *cq = to_mcq(ibcq); 575 struct mlx5_ib_qp *cur_qp = NULL; 576 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 577 struct mlx5_core_dev *mdev = dev->mdev; 578 unsigned long flags; 579 int soft_polled = 0; 580 int npolled; 581 582 spin_lock_irqsave(&cq->lock, flags); 583 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 584 /* make sure no soft wqe's are waiting */ 585 if (unlikely(!list_empty(&cq->wc_list))) 586 soft_polled = poll_soft_wc(cq, num_entries, wc, true); 587 588 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled, 589 wc + soft_polled, &npolled); 590 goto out; 591 } 592 593 if (unlikely(!list_empty(&cq->wc_list))) 594 soft_polled = poll_soft_wc(cq, num_entries, wc, false); 595 596 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 597 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 598 break; 599 } 600 601 if (npolled) 602 mlx5_cq_set_ci(&cq->mcq); 603 out: 604 spin_unlock_irqrestore(&cq->lock, flags); 605 606 return soft_polled + npolled; 607 } 608 609 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 610 { 611 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 612 struct mlx5_ib_cq *cq = to_mcq(ibcq); 613 void __iomem *uar_page = mdev->priv.uar->map; 614 unsigned long irq_flags; 615 int ret = 0; 616 617 spin_lock_irqsave(&cq->lock, irq_flags); 618 if (cq->notify_flags != IB_CQ_NEXT_COMP) 619 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 620 621 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 622 ret = 1; 623 spin_unlock_irqrestore(&cq->lock, irq_flags); 624 625 mlx5_cq_arm(&cq->mcq, 626 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 627 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 628 uar_page, to_mcq(ibcq)->mcq.cons_index); 629 630 return ret; 631 } 632 633 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, 634 struct mlx5_ib_cq_buf *buf, 635 int nent, 636 int cqe_size) 637 { 638 struct mlx5_frag_buf *frag_buf = &buf->frag_buf; 639 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0); 640 u8 log_wq_sz = ilog2(cqe_size); 641 int err; 642 643 err = mlx5_frag_buf_alloc_node(dev->mdev, 644 nent * cqe_size, 645 frag_buf, 646 dev->mdev->priv.numa_node); 647 if (err) 648 return err; 649 650 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc); 651 652 buf->cqe_size = cqe_size; 653 buf->nent = nent; 654 655 return 0; 656 } 657 658 enum { 659 MLX5_CQE_RES_FORMAT_HASH = 0, 660 MLX5_CQE_RES_FORMAT_CSUM = 1, 661 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3, 662 }; 663 664 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format) 665 { 666 switch (format) { 667 case MLX5_IB_CQE_RES_FORMAT_HASH: 668 return MLX5_CQE_RES_FORMAT_HASH; 669 case MLX5_IB_CQE_RES_FORMAT_CSUM: 670 return MLX5_CQE_RES_FORMAT_CSUM; 671 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX: 672 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 673 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX; 674 return -EOPNOTSUPP; 675 default: 676 return -EINVAL; 677 } 678 } 679 680 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 681 struct mlx5_ib_cq *cq, int entries, u32 **cqb, 682 int *cqe_size, int *index, int *inlen) 683 { 684 struct mlx5_ib_create_cq ucmd = {}; 685 size_t ucmdlen; 686 int page_shift; 687 __be64 *pas; 688 int npages; 689 int ncont; 690 void *cqc; 691 int err; 692 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 693 udata, struct mlx5_ib_ucontext, ibucontext); 694 695 ucmdlen = udata->inlen < sizeof(ucmd) ? 696 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd); 697 698 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 699 return -EFAULT; 700 701 if (ucmdlen == sizeof(ucmd) && 702 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD))) 703 return -EINVAL; 704 705 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 706 return -EINVAL; 707 708 *cqe_size = ucmd.cqe_size; 709 710 cq->buf.umem = 711 ib_umem_get(udata, ucmd.buf_addr, entries * ucmd.cqe_size, 712 IB_ACCESS_LOCAL_WRITE); 713 if (IS_ERR(cq->buf.umem)) { 714 err = PTR_ERR(cq->buf.umem); 715 return err; 716 } 717 718 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db); 719 if (err) 720 goto err_umem; 721 722 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift, 723 &ncont, NULL); 724 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 725 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 726 727 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 728 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 729 *cqb = kvzalloc(*inlen, GFP_KERNEL); 730 if (!*cqb) { 731 err = -ENOMEM; 732 goto err_db; 733 } 734 735 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 736 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0); 737 738 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 739 MLX5_SET(cqc, cqc, log_page_size, 740 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 741 742 *index = context->bfregi.sys_pages[0]; 743 744 if (ucmd.cqe_comp_en == 1) { 745 int mini_cqe_format; 746 747 if (!((*cqe_size == 128 && 748 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) || 749 (*cqe_size == 64 && 750 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) { 751 err = -EOPNOTSUPP; 752 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 753 *cqe_size); 754 goto err_cqb; 755 } 756 757 mini_cqe_format = 758 mini_cqe_res_format_to_hw(dev, 759 ucmd.cqe_comp_res_format); 760 if (mini_cqe_format < 0) { 761 err = mini_cqe_format; 762 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n", 763 ucmd.cqe_comp_res_format, err); 764 goto err_cqb; 765 } 766 767 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 768 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); 769 } 770 771 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) { 772 if (*cqe_size != 128 || 773 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) { 774 err = -EOPNOTSUPP; 775 mlx5_ib_warn(dev, 776 "CQE padding is not supported for CQE size of %dB!\n", 777 *cqe_size); 778 goto err_cqb; 779 } 780 781 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD; 782 } 783 784 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid); 785 return 0; 786 787 err_cqb: 788 kvfree(*cqb); 789 790 err_db: 791 mlx5_ib_db_unmap_user(context, &cq->db); 792 793 err_umem: 794 ib_umem_release(cq->buf.umem); 795 return err; 796 } 797 798 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata) 799 { 800 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 801 udata, struct mlx5_ib_ucontext, ibucontext); 802 803 mlx5_ib_db_unmap_user(context, &cq->db); 804 ib_umem_release(cq->buf.umem); 805 } 806 807 static void init_cq_frag_buf(struct mlx5_ib_cq *cq, 808 struct mlx5_ib_cq_buf *buf) 809 { 810 int i; 811 void *cqe; 812 struct mlx5_cqe64 *cqe64; 813 814 for (i = 0; i < buf->nent; i++) { 815 cqe = get_cqe(cq, i); 816 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 817 cqe64->op_own = MLX5_CQE_INVALID << 4; 818 } 819 } 820 821 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 822 int entries, int cqe_size, 823 u32 **cqb, int *index, int *inlen) 824 { 825 __be64 *pas; 826 void *cqc; 827 int err; 828 829 err = mlx5_db_alloc(dev->mdev, &cq->db); 830 if (err) 831 return err; 832 833 cq->mcq.set_ci_db = cq->db.db; 834 cq->mcq.arm_db = cq->db.db + 1; 835 cq->mcq.cqe_sz = cqe_size; 836 837 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); 838 if (err) 839 goto err_db; 840 841 init_cq_frag_buf(cq, &cq->buf); 842 843 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 844 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * 845 cq->buf.frag_buf.npages; 846 *cqb = kvzalloc(*inlen, GFP_KERNEL); 847 if (!*cqb) { 848 err = -ENOMEM; 849 goto err_buf; 850 } 851 852 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 853 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas); 854 855 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 856 MLX5_SET(cqc, cqc, log_page_size, 857 cq->buf.frag_buf.page_shift - 858 MLX5_ADAPTER_PAGE_SHIFT); 859 860 *index = dev->mdev->priv.uar->index; 861 862 return 0; 863 864 err_buf: 865 free_cq_buf(dev, &cq->buf); 866 867 err_db: 868 mlx5_db_free(dev->mdev, &cq->db); 869 return err; 870 } 871 872 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 873 { 874 free_cq_buf(dev, &cq->buf); 875 mlx5_db_free(dev->mdev, &cq->db); 876 } 877 878 static void notify_soft_wc_handler(struct work_struct *work) 879 { 880 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 881 notify_work); 882 883 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 884 } 885 886 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 887 struct ib_udata *udata) 888 { 889 struct ib_device *ibdev = ibcq->device; 890 int entries = attr->cqe; 891 int vector = attr->comp_vector; 892 struct mlx5_ib_dev *dev = to_mdev(ibdev); 893 struct mlx5_ib_cq *cq = to_mcq(ibcq); 894 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 895 int uninitialized_var(index); 896 int uninitialized_var(inlen); 897 u32 *cqb = NULL; 898 void *cqc; 899 int cqe_size; 900 unsigned int irqn; 901 int eqn; 902 int err; 903 904 if (entries < 0 || 905 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 906 return -EINVAL; 907 908 if (check_cq_create_flags(attr->flags)) 909 return -EOPNOTSUPP; 910 911 entries = roundup_pow_of_two(entries + 1); 912 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 913 return -EINVAL; 914 915 cq->ibcq.cqe = entries - 1; 916 mutex_init(&cq->resize_mutex); 917 spin_lock_init(&cq->lock); 918 cq->resize_buf = NULL; 919 cq->resize_umem = NULL; 920 cq->create_flags = attr->flags; 921 INIT_LIST_HEAD(&cq->list_send_qp); 922 INIT_LIST_HEAD(&cq->list_recv_qp); 923 924 if (udata) { 925 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size, 926 &index, &inlen); 927 if (err) 928 return err; 929 } else { 930 cqe_size = cache_line_size() == 128 ? 128 : 64; 931 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 932 &index, &inlen); 933 if (err) 934 return err; 935 936 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 937 } 938 939 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); 940 if (err) 941 goto err_cqb; 942 943 cq->cqe_size = cqe_size; 944 945 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 946 MLX5_SET(cqc, cqc, cqe_sz, 947 cqe_sz_to_mlx_sz(cqe_size, 948 cq->private_flags & 949 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 950 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 951 MLX5_SET(cqc, cqc, uar_page, index); 952 MLX5_SET(cqc, cqc, c_eqn, eqn); 953 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 954 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) 955 MLX5_SET(cqc, cqc, oi, 1); 956 957 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out)); 958 if (err) 959 goto err_cqb; 960 961 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 962 cq->mcq.irqn = irqn; 963 if (udata) 964 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp; 965 else 966 cq->mcq.comp = mlx5_ib_cq_comp; 967 cq->mcq.event = mlx5_ib_cq_event; 968 969 INIT_LIST_HEAD(&cq->wc_list); 970 971 if (udata) 972 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 973 err = -EFAULT; 974 goto err_cmd; 975 } 976 977 978 kvfree(cqb); 979 return 0; 980 981 err_cmd: 982 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 983 984 err_cqb: 985 kvfree(cqb); 986 if (udata) 987 destroy_cq_user(cq, udata); 988 else 989 destroy_cq_kernel(dev, cq); 990 return err; 991 } 992 993 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 994 { 995 struct mlx5_ib_dev *dev = to_mdev(cq->device); 996 struct mlx5_ib_cq *mcq = to_mcq(cq); 997 998 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 999 if (udata) 1000 destroy_cq_user(mcq, udata); 1001 else 1002 destroy_cq_kernel(dev, mcq); 1003 } 1004 1005 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1006 { 1007 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1008 } 1009 1010 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1011 { 1012 struct mlx5_cqe64 *cqe64, *dest64; 1013 void *cqe, *dest; 1014 u32 prod_index; 1015 int nfreed = 0; 1016 u8 owner_bit; 1017 1018 if (!cq) 1019 return; 1020 1021 /* First we need to find the current producer index, so we 1022 * know where to start cleaning from. It doesn't matter if HW 1023 * adds new entries after this loop -- the QP we're worried 1024 * about is already in RESET, so the new entries won't come 1025 * from our QP and therefore don't need to be checked. 1026 */ 1027 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1028 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1029 break; 1030 1031 /* Now sweep backwards through the CQ, removing CQ entries 1032 * that match our QP by copying older entries on top of them. 1033 */ 1034 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1035 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1036 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1037 if (is_equal_rsn(cqe64, rsn)) { 1038 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1039 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1040 ++nfreed; 1041 } else if (nfreed) { 1042 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1043 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1044 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1045 memcpy(dest, cqe, cq->mcq.cqe_sz); 1046 dest64->op_own = owner_bit | 1047 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1048 } 1049 } 1050 1051 if (nfreed) { 1052 cq->mcq.cons_index += nfreed; 1053 /* Make sure update of buffer contents is done before 1054 * updating consumer index. 1055 */ 1056 wmb(); 1057 mlx5_cq_set_ci(&cq->mcq); 1058 } 1059 } 1060 1061 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1062 { 1063 if (!cq) 1064 return; 1065 1066 spin_lock_irq(&cq->lock); 1067 __mlx5_ib_cq_clean(cq, qpn, srq); 1068 spin_unlock_irq(&cq->lock); 1069 } 1070 1071 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1072 { 1073 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1074 struct mlx5_ib_cq *mcq = to_mcq(cq); 1075 int err; 1076 1077 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1078 return -EOPNOTSUPP; 1079 1080 if (cq_period > MLX5_MAX_CQ_PERIOD) 1081 return -EINVAL; 1082 1083 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1084 cq_period, cq_count); 1085 if (err) 1086 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1087 1088 return err; 1089 } 1090 1091 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1092 int entries, struct ib_udata *udata, int *npas, 1093 int *page_shift, int *cqe_size) 1094 { 1095 struct mlx5_ib_resize_cq ucmd; 1096 struct ib_umem *umem; 1097 int err; 1098 int npages; 1099 1100 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1101 if (err) 1102 return err; 1103 1104 if (ucmd.reserved0 || ucmd.reserved1) 1105 return -EINVAL; 1106 1107 /* check multiplication overflow */ 1108 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1109 return -EINVAL; 1110 1111 umem = ib_umem_get(udata, ucmd.buf_addr, 1112 (size_t)ucmd.cqe_size * entries, 1113 IB_ACCESS_LOCAL_WRITE); 1114 if (IS_ERR(umem)) { 1115 err = PTR_ERR(umem); 1116 return err; 1117 } 1118 1119 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift, 1120 npas, NULL); 1121 1122 cq->resize_umem = umem; 1123 *cqe_size = ucmd.cqe_size; 1124 1125 return 0; 1126 } 1127 1128 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1129 int entries, int cqe_size) 1130 { 1131 int err; 1132 1133 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1134 if (!cq->resize_buf) 1135 return -ENOMEM; 1136 1137 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); 1138 if (err) 1139 goto ex; 1140 1141 init_cq_frag_buf(cq, cq->resize_buf); 1142 1143 return 0; 1144 1145 ex: 1146 kfree(cq->resize_buf); 1147 return err; 1148 } 1149 1150 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1151 { 1152 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1153 struct mlx5_cqe64 *scqe64; 1154 struct mlx5_cqe64 *dcqe64; 1155 void *start_cqe; 1156 void *scqe; 1157 void *dcqe; 1158 int ssize; 1159 int dsize; 1160 int i; 1161 u8 sw_own; 1162 1163 ssize = cq->buf.cqe_size; 1164 dsize = cq->resize_buf->cqe_size; 1165 if (ssize != dsize) { 1166 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1167 return -EINVAL; 1168 } 1169 1170 i = cq->mcq.cons_index; 1171 scqe = get_sw_cqe(cq, i); 1172 scqe64 = ssize == 64 ? scqe : scqe + 64; 1173 start_cqe = scqe; 1174 if (!scqe) { 1175 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1176 return -EINVAL; 1177 } 1178 1179 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) { 1180 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, 1181 (i + 1) & cq->resize_buf->nent); 1182 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1183 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1184 memcpy(dcqe, scqe, dsize); 1185 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1186 1187 ++i; 1188 scqe = get_sw_cqe(cq, i); 1189 scqe64 = ssize == 64 ? scqe : scqe + 64; 1190 if (!scqe) { 1191 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1192 return -EINVAL; 1193 } 1194 1195 if (scqe == start_cqe) { 1196 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1197 cq->mcq.cqn); 1198 return -ENOMEM; 1199 } 1200 } 1201 ++cq->mcq.cons_index; 1202 return 0; 1203 } 1204 1205 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1206 { 1207 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1208 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1209 void *cqc; 1210 u32 *in; 1211 int err; 1212 int npas; 1213 __be64 *pas; 1214 int page_shift; 1215 int inlen; 1216 int uninitialized_var(cqe_size); 1217 unsigned long flags; 1218 1219 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1220 pr_info("Firmware does not support resize CQ\n"); 1221 return -ENOSYS; 1222 } 1223 1224 if (entries < 1 || 1225 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1226 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1227 entries, 1228 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1229 return -EINVAL; 1230 } 1231 1232 entries = roundup_pow_of_two(entries + 1); 1233 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1234 return -EINVAL; 1235 1236 if (entries == ibcq->cqe + 1) 1237 return 0; 1238 1239 mutex_lock(&cq->resize_mutex); 1240 if (udata) { 1241 err = resize_user(dev, cq, entries, udata, &npas, &page_shift, 1242 &cqe_size); 1243 } else { 1244 cqe_size = 64; 1245 err = resize_kernel(dev, cq, entries, cqe_size); 1246 if (!err) { 1247 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf; 1248 1249 npas = frag_buf->npages; 1250 page_shift = frag_buf->page_shift; 1251 } 1252 } 1253 1254 if (err) 1255 goto ex; 1256 1257 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1258 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1259 1260 in = kvzalloc(inlen, GFP_KERNEL); 1261 if (!in) { 1262 err = -ENOMEM; 1263 goto ex_resize; 1264 } 1265 1266 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1267 if (udata) 1268 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, 1269 pas, 0); 1270 else 1271 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas); 1272 1273 MLX5_SET(modify_cq_in, in, 1274 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1275 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1276 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1277 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1278 1279 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1280 1281 MLX5_SET(cqc, cqc, log_page_size, 1282 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1283 MLX5_SET(cqc, cqc, cqe_sz, 1284 cqe_sz_to_mlx_sz(cqe_size, 1285 cq->private_flags & 1286 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD)); 1287 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1288 1289 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1290 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1291 1292 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1293 if (err) 1294 goto ex_alloc; 1295 1296 if (udata) { 1297 cq->ibcq.cqe = entries - 1; 1298 ib_umem_release(cq->buf.umem); 1299 cq->buf.umem = cq->resize_umem; 1300 cq->resize_umem = NULL; 1301 } else { 1302 struct mlx5_ib_cq_buf tbuf; 1303 int resized = 0; 1304 1305 spin_lock_irqsave(&cq->lock, flags); 1306 if (cq->resize_buf) { 1307 err = copy_resize_cqes(cq); 1308 if (!err) { 1309 tbuf = cq->buf; 1310 cq->buf = *cq->resize_buf; 1311 kfree(cq->resize_buf); 1312 cq->resize_buf = NULL; 1313 resized = 1; 1314 } 1315 } 1316 cq->ibcq.cqe = entries - 1; 1317 spin_unlock_irqrestore(&cq->lock, flags); 1318 if (resized) 1319 free_cq_buf(dev, &tbuf); 1320 } 1321 mutex_unlock(&cq->resize_mutex); 1322 1323 kvfree(in); 1324 return 0; 1325 1326 ex_alloc: 1327 kvfree(in); 1328 1329 ex_resize: 1330 ib_umem_release(cq->resize_umem); 1331 if (!udata) { 1332 free_cq_buf(dev, cq->resize_buf); 1333 cq->resize_buf = NULL; 1334 } 1335 ex: 1336 mutex_unlock(&cq->resize_mutex); 1337 return err; 1338 } 1339 1340 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq) 1341 { 1342 struct mlx5_ib_cq *cq; 1343 1344 if (!ibcq) 1345 return 128; 1346 1347 cq = to_mcq(ibcq); 1348 return cq->cqe_size; 1349 } 1350 1351 /* Called from atomic context */ 1352 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1353 { 1354 struct mlx5_ib_wc *soft_wc; 1355 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1356 unsigned long flags; 1357 1358 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1359 if (!soft_wc) 1360 return -ENOMEM; 1361 1362 soft_wc->wc = *wc; 1363 spin_lock_irqsave(&cq->lock, flags); 1364 list_add_tail(&soft_wc->list, &cq->wc_list); 1365 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1366 wc->status != IB_WC_SUCCESS) { 1367 cq->notify_flags = 0; 1368 schedule_work(&cq->notify_work); 1369 } 1370 spin_unlock_irqrestore(&cq->lock, flags); 1371 1372 return 0; 1373 } 1374