1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include <rdma/mlx4-abi.h> 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 57 struct ib_udata *udata); 58 59 enum { 60 MLX4_IB_ACK_REQ_FREQ = 8, 61 }; 62 63 enum { 64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 66 MLX4_IB_LINK_TYPE_IB = 0, 67 MLX4_IB_LINK_TYPE_ETH = 1 68 }; 69 70 enum { 71 MLX4_IB_MIN_SQ_STRIDE = 6, 72 MLX4_IB_CACHE_LINE_SIZE = 64, 73 }; 74 75 enum { 76 MLX4_RAW_QP_MTU = 7, 77 MLX4_RAW_QP_MSGMAX = 31, 78 }; 79 80 #ifndef ETH_ALEN 81 #define ETH_ALEN 6 82 #endif 83 84 static const __be32 mlx4_ib_opcode[] = { 85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 98 }; 99 100 enum mlx4_ib_source_type { 101 MLX4_IB_QP_SRC = 0, 102 MLX4_IB_RWQ_SRC = 1, 103 }; 104 105 struct mlx4_ib_qp_event_work { 106 struct work_struct work; 107 struct mlx4_qp *qp; 108 enum mlx4_event type; 109 }; 110 111 static struct workqueue_struct *mlx4_ib_qp_event_wq; 112 113 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 114 { 115 if (!mlx4_is_master(dev->dev)) 116 return 0; 117 118 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 119 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 120 8 * MLX4_MFUNC_MAX; 121 } 122 123 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 124 { 125 int proxy_sqp = 0; 126 int real_sqp = 0; 127 int i; 128 /* PPF or Native -- real SQP */ 129 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 130 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 131 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 132 if (real_sqp) 133 return 1; 134 /* VF or PF -- proxy SQP */ 135 if (mlx4_is_mfunc(dev->dev)) { 136 for (i = 0; i < dev->dev->caps.num_ports; i++) { 137 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 138 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 139 proxy_sqp = 1; 140 break; 141 } 142 } 143 } 144 if (proxy_sqp) 145 return 1; 146 147 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 148 } 149 150 /* used for INIT/CLOSE port logic */ 151 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 152 { 153 int proxy_qp0 = 0; 154 int real_qp0 = 0; 155 int i; 156 /* PPF or Native -- real QP0 */ 157 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 158 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 159 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 160 if (real_qp0) 161 return 1; 162 /* VF or PF -- proxy QP0 */ 163 if (mlx4_is_mfunc(dev->dev)) { 164 for (i = 0; i < dev->dev->caps.num_ports; i++) { 165 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 166 proxy_qp0 = 1; 167 break; 168 } 169 } 170 } 171 return proxy_qp0; 172 } 173 174 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 175 { 176 return mlx4_buf_offset(&qp->buf, offset); 177 } 178 179 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 180 { 181 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 182 } 183 184 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 185 { 186 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 187 } 188 189 /* 190 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 191 * first four bytes of every 64 byte chunk with 0xffffffff, except for 192 * the very first chunk of the WQE. 193 */ 194 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 195 { 196 __be32 *wqe; 197 int i; 198 int s; 199 void *buf; 200 struct mlx4_wqe_ctrl_seg *ctrl; 201 202 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 203 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 204 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 205 for (i = 64; i < s; i += 64) { 206 wqe = buf + i; 207 *wqe = cpu_to_be32(0xffffffff); 208 } 209 } 210 211 static void mlx4_ib_handle_qp_event(struct work_struct *_work) 212 { 213 struct mlx4_ib_qp_event_work *qpe_work = 214 container_of(_work, struct mlx4_ib_qp_event_work, work); 215 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 216 struct ib_event event = {}; 217 218 event.device = ibqp->device; 219 event.element.qp = ibqp; 220 221 switch (qpe_work->type) { 222 case MLX4_EVENT_TYPE_PATH_MIG: 223 event.event = IB_EVENT_PATH_MIG; 224 break; 225 case MLX4_EVENT_TYPE_COMM_EST: 226 event.event = IB_EVENT_COMM_EST; 227 break; 228 case MLX4_EVENT_TYPE_SQ_DRAINED: 229 event.event = IB_EVENT_SQ_DRAINED; 230 break; 231 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 232 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 233 break; 234 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 235 event.event = IB_EVENT_QP_FATAL; 236 break; 237 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 238 event.event = IB_EVENT_PATH_MIG_ERR; 239 break; 240 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 event.event = IB_EVENT_QP_REQ_ERR; 242 break; 243 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 244 event.event = IB_EVENT_QP_ACCESS_ERR; 245 break; 246 default: 247 pr_warn("Unexpected event type %d on QP %06x\n", 248 qpe_work->type, qpe_work->qp->qpn); 249 goto out; 250 } 251 252 ibqp->event_handler(&event, ibqp->qp_context); 253 254 out: 255 mlx4_put_qp(qpe_work->qp); 256 kfree(qpe_work); 257 } 258 259 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 260 { 261 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 262 struct mlx4_ib_qp_event_work *qpe_work; 263 264 if (type == MLX4_EVENT_TYPE_PATH_MIG) 265 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 266 267 if (!ibqp->event_handler) 268 goto out_no_handler; 269 270 qpe_work = kzalloc(sizeof(*qpe_work), GFP_ATOMIC); 271 if (!qpe_work) 272 goto out_no_handler; 273 274 qpe_work->qp = qp; 275 qpe_work->type = type; 276 INIT_WORK(&qpe_work->work, mlx4_ib_handle_qp_event); 277 queue_work(mlx4_ib_qp_event_wq, &qpe_work->work); 278 return; 279 280 out_no_handler: 281 mlx4_put_qp(qp); 282 } 283 284 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 285 { 286 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 287 type, qp->qpn); 288 } 289 290 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 291 { 292 /* 293 * UD WQEs must have a datagram segment. 294 * RC and UC WQEs might have a remote address segment. 295 * MLX WQEs need two extra inline data segments (for the UD 296 * header and space for the ICRC). 297 */ 298 switch (type) { 299 case MLX4_IB_QPT_UD: 300 return sizeof (struct mlx4_wqe_ctrl_seg) + 301 sizeof (struct mlx4_wqe_datagram_seg) + 302 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 303 case MLX4_IB_QPT_PROXY_SMI_OWNER: 304 case MLX4_IB_QPT_PROXY_SMI: 305 case MLX4_IB_QPT_PROXY_GSI: 306 return sizeof (struct mlx4_wqe_ctrl_seg) + 307 sizeof (struct mlx4_wqe_datagram_seg) + 64; 308 case MLX4_IB_QPT_TUN_SMI_OWNER: 309 case MLX4_IB_QPT_TUN_GSI: 310 return sizeof (struct mlx4_wqe_ctrl_seg) + 311 sizeof (struct mlx4_wqe_datagram_seg); 312 313 case MLX4_IB_QPT_UC: 314 return sizeof (struct mlx4_wqe_ctrl_seg) + 315 sizeof (struct mlx4_wqe_raddr_seg); 316 case MLX4_IB_QPT_RC: 317 return sizeof (struct mlx4_wqe_ctrl_seg) + 318 sizeof (struct mlx4_wqe_masked_atomic_seg) + 319 sizeof (struct mlx4_wqe_raddr_seg); 320 case MLX4_IB_QPT_SMI: 321 case MLX4_IB_QPT_GSI: 322 return sizeof (struct mlx4_wqe_ctrl_seg) + 323 ALIGN(MLX4_IB_UD_HEADER_SIZE + 324 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 325 MLX4_INLINE_ALIGN) * 326 sizeof (struct mlx4_wqe_inline_seg), 327 sizeof (struct mlx4_wqe_data_seg)) + 328 ALIGN(4 + 329 sizeof (struct mlx4_wqe_inline_seg), 330 sizeof (struct mlx4_wqe_data_seg)); 331 default: 332 return sizeof (struct mlx4_wqe_ctrl_seg); 333 } 334 } 335 336 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 337 bool is_user, bool has_rq, struct mlx4_ib_qp *qp, 338 u32 inl_recv_sz) 339 { 340 /* Sanity check RQ size before proceeding */ 341 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 342 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 343 return -EINVAL; 344 345 if (!has_rq) { 346 if (cap->max_recv_wr || inl_recv_sz) 347 return -EINVAL; 348 349 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 350 } else { 351 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 352 sizeof(struct mlx4_wqe_data_seg); 353 u32 wqe_size; 354 355 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 356 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 357 inl_recv_sz > max_inl_recv_sz)) 358 return -EINVAL; 359 360 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 361 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 362 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 363 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 364 } 365 366 /* leave userspace return values as they were, so as not to break ABI */ 367 if (is_user) { 368 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 369 cap->max_recv_sge = qp->rq.max_gs; 370 } else { 371 cap->max_recv_wr = qp->rq.max_post = 372 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 373 cap->max_recv_sge = min(qp->rq.max_gs, 374 min(dev->dev->caps.max_sq_sg, 375 dev->dev->caps.max_rq_sg)); 376 } 377 378 return 0; 379 } 380 381 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 382 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 383 { 384 int s; 385 386 /* Sanity check SQ size before proceeding */ 387 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 388 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 389 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 390 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 391 return -EINVAL; 392 393 /* 394 * For MLX transport we need 2 extra S/G entries: 395 * one for the header and one for the checksum at the end 396 */ 397 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 398 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 399 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 400 return -EINVAL; 401 402 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 403 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 404 send_wqe_overhead(type, qp->flags); 405 406 if (s > dev->dev->caps.max_sq_desc_sz) 407 return -EINVAL; 408 409 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 410 411 /* 412 * We need to leave 2 KB + 1 WR of headroom in the SQ to 413 * allow HW to prefetch. 414 */ 415 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 416 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 417 qp->sq_spare_wqes); 418 419 qp->sq.max_gs = 420 (min(dev->dev->caps.max_sq_desc_sz, 421 (1 << qp->sq.wqe_shift)) - 422 send_wqe_overhead(type, qp->flags)) / 423 sizeof (struct mlx4_wqe_data_seg); 424 425 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 426 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 427 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 428 qp->rq.offset = 0; 429 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 430 } else { 431 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 432 qp->sq.offset = 0; 433 } 434 435 cap->max_send_wr = qp->sq.max_post = 436 qp->sq.wqe_cnt - qp->sq_spare_wqes; 437 cap->max_send_sge = min(qp->sq.max_gs, 438 min(dev->dev->caps.max_sq_sg, 439 dev->dev->caps.max_rq_sg)); 440 /* We don't support inline sends for kernel QPs (yet) */ 441 cap->max_inline_data = 0; 442 443 return 0; 444 } 445 446 static int set_user_sq_size(struct mlx4_ib_dev *dev, 447 struct mlx4_ib_qp *qp, 448 struct mlx4_ib_create_qp *ucmd) 449 { 450 /* Sanity check SQ size before proceeding */ 451 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 452 ucmd->log_sq_stride > 453 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 454 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 455 return -EINVAL; 456 457 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 458 qp->sq.wqe_shift = ucmd->log_sq_stride; 459 460 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 461 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 462 463 return 0; 464 } 465 466 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 467 { 468 int i; 469 470 qp->sqp_proxy_rcv = 471 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf), 472 GFP_KERNEL); 473 if (!qp->sqp_proxy_rcv) 474 return -ENOMEM; 475 for (i = 0; i < qp->rq.wqe_cnt; i++) { 476 qp->sqp_proxy_rcv[i].addr = 477 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 478 GFP_KERNEL); 479 if (!qp->sqp_proxy_rcv[i].addr) 480 goto err; 481 qp->sqp_proxy_rcv[i].map = 482 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 483 sizeof (struct mlx4_ib_proxy_sqp_hdr), 484 DMA_FROM_DEVICE); 485 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 486 kfree(qp->sqp_proxy_rcv[i].addr); 487 goto err; 488 } 489 } 490 return 0; 491 492 err: 493 while (i > 0) { 494 --i; 495 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 496 sizeof (struct mlx4_ib_proxy_sqp_hdr), 497 DMA_FROM_DEVICE); 498 kfree(qp->sqp_proxy_rcv[i].addr); 499 } 500 kfree(qp->sqp_proxy_rcv); 501 qp->sqp_proxy_rcv = NULL; 502 return -ENOMEM; 503 } 504 505 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 506 { 507 int i; 508 509 for (i = 0; i < qp->rq.wqe_cnt; i++) { 510 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 511 sizeof (struct mlx4_ib_proxy_sqp_hdr), 512 DMA_FROM_DEVICE); 513 kfree(qp->sqp_proxy_rcv[i].addr); 514 } 515 kfree(qp->sqp_proxy_rcv); 516 } 517 518 static bool qp_has_rq(struct ib_qp_init_attr *attr) 519 { 520 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 521 return false; 522 523 return !attr->srq; 524 } 525 526 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 527 { 528 int i; 529 for (i = 0; i < dev->caps.num_ports; i++) { 530 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 531 return !!dev->caps.spec_qps[i].qp0_qkey; 532 } 533 return 0; 534 } 535 536 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 537 struct mlx4_ib_qp *qp) 538 { 539 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 540 mlx4_counter_free(dev->dev, qp->counter_index->index); 541 list_del(&qp->counter_index->list); 542 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 543 544 kfree(qp->counter_index); 545 qp->counter_index = NULL; 546 } 547 548 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 549 struct ib_qp_init_attr *init_attr, 550 struct mlx4_ib_create_qp_rss *ucmd) 551 { 552 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 553 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 554 555 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 556 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 557 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 558 MLX4_EN_RSS_KEY_SIZE); 559 } else { 560 pr_debug("RX Hash function is not supported\n"); 561 return (-EOPNOTSUPP); 562 } 563 564 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | 565 MLX4_IB_RX_HASH_DST_IPV4 | 566 MLX4_IB_RX_HASH_SRC_IPV6 | 567 MLX4_IB_RX_HASH_DST_IPV6 | 568 MLX4_IB_RX_HASH_SRC_PORT_TCP | 569 MLX4_IB_RX_HASH_DST_PORT_TCP | 570 MLX4_IB_RX_HASH_SRC_PORT_UDP | 571 MLX4_IB_RX_HASH_DST_PORT_UDP | 572 MLX4_IB_RX_HASH_INNER)) { 573 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 574 ucmd->rx_hash_fields_mask); 575 return (-EOPNOTSUPP); 576 } 577 578 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 579 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 580 rss_ctx->flags = MLX4_RSS_IPV4; 581 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 582 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 583 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 584 return (-EOPNOTSUPP); 585 } 586 587 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 588 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 589 rss_ctx->flags |= MLX4_RSS_IPV6; 590 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 591 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 592 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 593 return (-EOPNOTSUPP); 594 } 595 596 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 597 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 598 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 599 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 600 return (-EOPNOTSUPP); 601 } 602 603 if (rss_ctx->flags & MLX4_RSS_IPV4) 604 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 605 if (rss_ctx->flags & MLX4_RSS_IPV6) 606 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 607 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 608 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 609 return (-EOPNOTSUPP); 610 } 611 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 612 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 613 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 614 return (-EOPNOTSUPP); 615 } 616 617 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 618 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 619 if (rss_ctx->flags & MLX4_RSS_IPV4) 620 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 621 if (rss_ctx->flags & MLX4_RSS_IPV6) 622 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 623 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 624 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 625 return (-EOPNOTSUPP); 626 } 627 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 628 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 629 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 630 return (-EOPNOTSUPP); 631 } 632 633 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 634 if (dev->dev->caps.tunnel_offload_mode == 635 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 636 /* 637 * Hash according to inner headers if exist, otherwise 638 * according to outer headers. 639 */ 640 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 641 } else { 642 pr_debug("RSS Hash for inner headers isn't supported\n"); 643 return (-EOPNOTSUPP); 644 } 645 } 646 647 return 0; 648 } 649 650 static int create_qp_rss(struct mlx4_ib_dev *dev, 651 struct ib_qp_init_attr *init_attr, 652 struct mlx4_ib_create_qp_rss *ucmd, 653 struct mlx4_ib_qp *qp) 654 { 655 int qpn; 656 int err; 657 658 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 659 660 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 661 if (err) 662 return err; 663 664 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 665 if (err) 666 goto err_qpn; 667 668 INIT_LIST_HEAD(&qp->gid_list); 669 INIT_LIST_HEAD(&qp->steering_rules); 670 671 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 672 qp->state = IB_QPS_RESET; 673 674 /* Set dummy send resources to be compatible with HV and PRM */ 675 qp->sq_no_prefetch = 1; 676 qp->sq.wqe_cnt = 1; 677 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 678 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 679 qp->mtt = (to_mqp( 680 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 681 682 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 683 if (!qp->rss_ctx) { 684 err = -ENOMEM; 685 goto err_qp_alloc; 686 } 687 688 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 689 if (err) 690 goto err; 691 692 return 0; 693 694 err: 695 kfree(qp->rss_ctx); 696 697 err_qp_alloc: 698 mlx4_qp_remove(dev->dev, &qp->mqp); 699 mlx4_qp_free(dev->dev, &qp->mqp); 700 701 err_qpn: 702 mlx4_qp_release_range(dev->dev, qpn, 1); 703 return err; 704 } 705 706 static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp, 707 struct ib_qp_init_attr *init_attr, 708 struct ib_udata *udata) 709 { 710 struct mlx4_ib_create_qp_rss ucmd = {}; 711 size_t required_cmd_sz; 712 int err; 713 714 if (!udata) { 715 pr_debug("RSS QP with NULL udata\n"); 716 return -EINVAL; 717 } 718 719 if (udata->outlen) 720 return -EOPNOTSUPP; 721 722 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 723 sizeof(ucmd.reserved1); 724 if (udata->inlen < required_cmd_sz) { 725 pr_debug("invalid inlen\n"); 726 return -EINVAL; 727 } 728 729 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 730 pr_debug("copy failed\n"); 731 return -EFAULT; 732 } 733 734 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 735 return -EOPNOTSUPP; 736 737 if (ucmd.comp_mask || ucmd.reserved1) 738 return -EOPNOTSUPP; 739 740 if (udata->inlen > sizeof(ucmd) && 741 !ib_is_udata_cleared(udata, sizeof(ucmd), 742 udata->inlen - sizeof(ucmd))) { 743 pr_debug("inlen is not supported\n"); 744 return -EOPNOTSUPP; 745 } 746 747 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 748 pr_debug("RSS QP with unsupported QP type %d\n", 749 init_attr->qp_type); 750 return -EOPNOTSUPP; 751 } 752 753 if (init_attr->create_flags) { 754 pr_debug("RSS QP doesn't support create flags\n"); 755 return -EOPNOTSUPP; 756 } 757 758 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 759 pr_debug("RSS QP with unsupported send attributes\n"); 760 return -EOPNOTSUPP; 761 } 762 763 qp->pri.vid = 0xFFFF; 764 qp->alt.vid = 0xFFFF; 765 766 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 767 if (err) 768 return err; 769 770 qp->ibqp.qp_num = qp->mqp.qpn; 771 return 0; 772 } 773 774 /* 775 * This function allocates a WQN from a range which is consecutive and aligned 776 * to its size. In case the range is full, then it creates a new range and 777 * allocates WQN from it. The new range will be used for following allocations. 778 */ 779 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 780 struct mlx4_ib_qp *qp, int range_size, int *wqn) 781 { 782 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 783 struct mlx4_wqn_range *range; 784 int err = 0; 785 786 mutex_lock(&context->wqn_ranges_mutex); 787 788 range = list_first_entry_or_null(&context->wqn_ranges_list, 789 struct mlx4_wqn_range, list); 790 791 if (!range || (range->refcount == range->size) || range->dirty) { 792 range = kzalloc(sizeof(*range), GFP_KERNEL); 793 if (!range) { 794 err = -ENOMEM; 795 goto out; 796 } 797 798 err = mlx4_qp_reserve_range(dev->dev, range_size, 799 range_size, &range->base_wqn, 0, 800 qp->mqp.usage); 801 if (err) { 802 kfree(range); 803 goto out; 804 } 805 806 range->size = range_size; 807 list_add(&range->list, &context->wqn_ranges_list); 808 } else if (range_size != 1) { 809 /* 810 * Requesting a new range (>1) when last range is still open, is 811 * not valid. 812 */ 813 err = -EINVAL; 814 goto out; 815 } 816 817 qp->wqn_range = range; 818 819 *wqn = range->base_wqn + range->refcount; 820 821 range->refcount++; 822 823 out: 824 mutex_unlock(&context->wqn_ranges_mutex); 825 826 return err; 827 } 828 829 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 830 struct mlx4_ib_qp *qp, bool dirty_release) 831 { 832 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 833 struct mlx4_wqn_range *range; 834 835 mutex_lock(&context->wqn_ranges_mutex); 836 837 range = qp->wqn_range; 838 839 range->refcount--; 840 if (!range->refcount) { 841 mlx4_qp_release_range(dev->dev, range->base_wqn, 842 range->size); 843 list_del(&range->list); 844 kfree(range); 845 } else if (dirty_release) { 846 /* 847 * A range which one of its WQNs is destroyed, won't be able to be 848 * reused for further WQN allocations. 849 * The next created WQ will allocate a new range. 850 */ 851 range->dirty = true; 852 } 853 854 mutex_unlock(&context->wqn_ranges_mutex); 855 } 856 857 static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 858 struct ib_udata *udata, struct mlx4_ib_qp *qp) 859 { 860 struct mlx4_ib_dev *dev = to_mdev(pd->device); 861 int qpn; 862 int err; 863 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 864 udata, struct mlx4_ib_ucontext, ibucontext); 865 struct mlx4_ib_cq *mcq; 866 unsigned long flags; 867 int range_size; 868 struct mlx4_ib_create_wq wq; 869 size_t copy_len; 870 int shift; 871 int n; 872 873 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 874 875 spin_lock_init(&qp->sq.lock); 876 spin_lock_init(&qp->rq.lock); 877 INIT_LIST_HEAD(&qp->gid_list); 878 INIT_LIST_HEAD(&qp->steering_rules); 879 880 qp->state = IB_QPS_RESET; 881 882 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 883 884 if (ib_copy_from_udata(&wq, udata, copy_len)) { 885 err = -EFAULT; 886 goto err; 887 } 888 889 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] || 890 wq.reserved[2]) { 891 pr_debug("user command isn't supported\n"); 892 err = -EOPNOTSUPP; 893 goto err; 894 } 895 896 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) { 897 pr_debug("WQN range size must be equal or smaller than %d\n", 898 dev->dev->caps.max_rss_tbl_sz); 899 err = -EOPNOTSUPP; 900 goto err; 901 } 902 range_size = 1 << wq.log_range_size; 903 904 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) 905 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 906 907 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz); 908 if (err) 909 goto err; 910 911 qp->sq_no_prefetch = 1; 912 qp->sq.wqe_cnt = 1; 913 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 914 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 915 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 916 917 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0); 918 if (IS_ERR(qp->umem)) { 919 err = PTR_ERR(qp->umem); 920 goto err; 921 } 922 923 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 924 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 925 926 if (err) 927 goto err_buf; 928 929 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 930 if (err) 931 goto err_mtt; 932 933 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db); 934 if (err) 935 goto err_mtt; 936 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 937 938 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn); 939 if (err) 940 goto err_wrid; 941 942 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 943 if (err) 944 goto err_qpn; 945 946 /* 947 * Hardware wants QPN written in big-endian order (after 948 * shifting) for send doorbell. Precompute this value to save 949 * a little bit when posting sends. 950 */ 951 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 952 953 qp->mqp.event = mlx4_ib_wq_event; 954 955 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 956 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 957 to_mcq(init_attr->recv_cq)); 958 /* Maintain device to QPs access, needed for further handling 959 * via reset flow 960 */ 961 list_add_tail(&qp->qps_list, &dev->qp_list); 962 /* Maintain CQ to QPs access, needed for further handling 963 * via reset flow 964 */ 965 mcq = to_mcq(init_attr->send_cq); 966 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 967 mcq = to_mcq(init_attr->recv_cq); 968 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 969 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 970 to_mcq(init_attr->recv_cq)); 971 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 972 return 0; 973 974 err_qpn: 975 mlx4_ib_release_wqn(context, qp, 0); 976 err_wrid: 977 mlx4_ib_db_unmap_user(context, &qp->db); 978 979 err_mtt: 980 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 981 err_buf: 982 ib_umem_release(qp->umem); 983 err: 984 return err; 985 } 986 987 static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 988 struct ib_udata *udata, int sqpn, 989 struct mlx4_ib_qp *qp) 990 { 991 struct mlx4_ib_dev *dev = to_mdev(pd->device); 992 int qpn; 993 int err; 994 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 995 udata, struct mlx4_ib_ucontext, ibucontext); 996 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 997 struct mlx4_ib_cq *mcq; 998 unsigned long flags; 999 1000 /* When tunneling special qps, we use a plain UD qp */ 1001 if (sqpn) { 1002 if (mlx4_is_mfunc(dev->dev) && 1003 (!mlx4_is_master(dev->dev) || 1004 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 1005 if (init_attr->qp_type == IB_QPT_GSI) 1006 qp_type = MLX4_IB_QPT_PROXY_GSI; 1007 else { 1008 if (mlx4_is_master(dev->dev) || 1009 qp0_enabled_vf(dev->dev, sqpn)) 1010 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 1011 else 1012 qp_type = MLX4_IB_QPT_PROXY_SMI; 1013 } 1014 } 1015 qpn = sqpn; 1016 /* add extra sg entry for tunneling */ 1017 init_attr->cap.max_recv_sge++; 1018 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 1019 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 1020 container_of(init_attr, 1021 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 1022 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 1023 tnl_init->proxy_qp_type != IB_QPT_GSI) || 1024 !mlx4_is_master(dev->dev)) 1025 return -EINVAL; 1026 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 1027 qp_type = MLX4_IB_QPT_TUN_GSI; 1028 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 1029 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 1030 tnl_init->port)) 1031 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 1032 else 1033 qp_type = MLX4_IB_QPT_TUN_SMI; 1034 /* we are definitely in the PPF here, since we are creating 1035 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 1036 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 1037 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 1038 sqpn = qpn; 1039 } 1040 1041 if (init_attr->qp_type == IB_QPT_SMI || 1042 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI || 1043 qp_type == MLX4_IB_QPT_GSI || 1044 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 1045 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 1046 qp->sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 1047 if (!qp->sqp) 1048 return -ENOMEM; 1049 } 1050 1051 qp->mlx4_ib_qp_type = qp_type; 1052 1053 spin_lock_init(&qp->sq.lock); 1054 spin_lock_init(&qp->rq.lock); 1055 INIT_LIST_HEAD(&qp->gid_list); 1056 INIT_LIST_HEAD(&qp->steering_rules); 1057 1058 qp->state = IB_QPS_RESET; 1059 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1060 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1061 1062 if (udata) { 1063 struct mlx4_ib_create_qp ucmd; 1064 size_t copy_len; 1065 int shift; 1066 int n; 1067 1068 copy_len = sizeof(struct mlx4_ib_create_qp); 1069 1070 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 1071 err = -EFAULT; 1072 goto err; 1073 } 1074 1075 qp->inl_recv_sz = ucmd.inl_recv_sz; 1076 1077 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1078 if (!(dev->dev->caps.flags & 1079 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 1080 pr_debug("scatter FCS is unsupported\n"); 1081 err = -EOPNOTSUPP; 1082 goto err; 1083 } 1084 1085 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 1086 } 1087 1088 err = set_rq_size(dev, &init_attr->cap, udata, 1089 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1090 if (err) 1091 goto err; 1092 1093 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 1094 1095 err = set_user_sq_size(dev, qp, &ucmd); 1096 if (err) 1097 goto err; 1098 1099 qp->umem = 1100 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0); 1101 if (IS_ERR(qp->umem)) { 1102 err = PTR_ERR(qp->umem); 1103 goto err; 1104 } 1105 1106 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1107 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1108 1109 if (err) 1110 goto err_buf; 1111 1112 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1113 if (err) 1114 goto err_mtt; 1115 1116 if (qp_has_rq(init_attr)) { 1117 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db); 1118 if (err) 1119 goto err_mtt; 1120 } 1121 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1122 } else { 1123 err = set_rq_size(dev, &init_attr->cap, udata, 1124 qp_has_rq(init_attr), qp, 0); 1125 if (err) 1126 goto err; 1127 1128 qp->sq_no_prefetch = 0; 1129 1130 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1131 qp->flags |= MLX4_IB_QP_LSO; 1132 1133 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1134 if (dev->steering_support == 1135 MLX4_STEERING_MODE_DEVICE_MANAGED) 1136 qp->flags |= MLX4_IB_QP_NETIF; 1137 else { 1138 err = -EINVAL; 1139 goto err; 1140 } 1141 } 1142 1143 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1144 if (err) 1145 goto err; 1146 1147 if (qp_has_rq(init_attr)) { 1148 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1149 if (err) 1150 goto err; 1151 1152 *qp->db.db = 0; 1153 } 1154 1155 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1156 &qp->buf)) { 1157 err = -ENOMEM; 1158 goto err_db; 1159 } 1160 1161 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1162 &qp->mtt); 1163 if (err) 1164 goto err_buf; 1165 1166 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1167 if (err) 1168 goto err_mtt; 1169 1170 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1171 sizeof(u64), GFP_KERNEL); 1172 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1173 sizeof(u64), GFP_KERNEL); 1174 if (!qp->sq.wrid || !qp->rq.wrid) { 1175 err = -ENOMEM; 1176 goto err_wrid; 1177 } 1178 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1179 } 1180 1181 if (sqpn) { 1182 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1183 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1184 if (alloc_proxy_bufs(pd->device, qp)) { 1185 err = -ENOMEM; 1186 goto err_wrid; 1187 } 1188 } 1189 } else { 1190 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1191 * otherwise, the WQE BlueFlame setup flow wrongly causes 1192 * VLAN insertion. */ 1193 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1194 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1195 (init_attr->cap.max_send_wr ? 1196 MLX4_RESERVE_ETH_BF_QP : 0) | 1197 (init_attr->cap.max_recv_wr ? 1198 MLX4_RESERVE_A0_QP : 0), 1199 qp->mqp.usage); 1200 else 1201 if (qp->flags & MLX4_IB_QP_NETIF) 1202 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1203 else 1204 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1205 &qpn, 0, qp->mqp.usage); 1206 if (err) 1207 goto err_proxy; 1208 } 1209 1210 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1211 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1212 1213 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1214 if (err) 1215 goto err_qpn; 1216 1217 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1218 qp->mqp.qpn |= (1 << 23); 1219 1220 /* 1221 * Hardware wants QPN written in big-endian order (after 1222 * shifting) for send doorbell. Precompute this value to save 1223 * a little bit when posting sends. 1224 */ 1225 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1226 1227 qp->mqp.event = mlx4_ib_qp_event; 1228 1229 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1230 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1231 to_mcq(init_attr->recv_cq)); 1232 /* Maintain device to QPs access, needed for further handling 1233 * via reset flow 1234 */ 1235 list_add_tail(&qp->qps_list, &dev->qp_list); 1236 /* Maintain CQ to QPs access, needed for further handling 1237 * via reset flow 1238 */ 1239 mcq = to_mcq(init_attr->send_cq); 1240 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1241 mcq = to_mcq(init_attr->recv_cq); 1242 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1243 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1244 to_mcq(init_attr->recv_cq)); 1245 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1246 return 0; 1247 1248 err_qpn: 1249 if (!sqpn) { 1250 if (qp->flags & MLX4_IB_QP_NETIF) 1251 mlx4_ib_steer_qp_free(dev, qpn, 1); 1252 else 1253 mlx4_qp_release_range(dev->dev, qpn, 1); 1254 } 1255 err_proxy: 1256 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1257 free_proxy_bufs(pd->device, qp); 1258 err_wrid: 1259 if (udata) { 1260 if (qp_has_rq(init_attr)) 1261 mlx4_ib_db_unmap_user(context, &qp->db); 1262 } else { 1263 kvfree(qp->sq.wrid); 1264 kvfree(qp->rq.wrid); 1265 } 1266 1267 err_mtt: 1268 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1269 1270 err_buf: 1271 if (!qp->umem) 1272 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1273 ib_umem_release(qp->umem); 1274 1275 err_db: 1276 if (!udata && qp_has_rq(init_attr)) 1277 mlx4_db_free(dev->dev, &qp->db); 1278 1279 err: 1280 kfree(qp->sqp); 1281 return err; 1282 } 1283 1284 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1285 { 1286 switch (state) { 1287 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1288 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1289 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1290 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1291 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1292 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1293 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1294 default: return -1; 1295 } 1296 } 1297 1298 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1299 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1300 { 1301 if (send_cq == recv_cq) { 1302 spin_lock(&send_cq->lock); 1303 __acquire(&recv_cq->lock); 1304 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1305 spin_lock(&send_cq->lock); 1306 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1307 } else { 1308 spin_lock(&recv_cq->lock); 1309 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1310 } 1311 } 1312 1313 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1314 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1315 { 1316 if (send_cq == recv_cq) { 1317 __release(&recv_cq->lock); 1318 spin_unlock(&send_cq->lock); 1319 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1320 spin_unlock(&recv_cq->lock); 1321 spin_unlock(&send_cq->lock); 1322 } else { 1323 spin_unlock(&send_cq->lock); 1324 spin_unlock(&recv_cq->lock); 1325 } 1326 } 1327 1328 static void del_gid_entries(struct mlx4_ib_qp *qp) 1329 { 1330 struct mlx4_ib_gid_entry *ge, *tmp; 1331 1332 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1333 list_del(&ge->list); 1334 kfree(ge); 1335 } 1336 } 1337 1338 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1339 { 1340 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1341 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1342 else 1343 return to_mpd(qp->ibqp.pd); 1344 } 1345 1346 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1347 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1348 { 1349 switch (qp->ibqp.qp_type) { 1350 case IB_QPT_XRC_TGT: 1351 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1352 *recv_cq = *send_cq; 1353 break; 1354 case IB_QPT_XRC_INI: 1355 *send_cq = to_mcq(qp->ibqp.send_cq); 1356 *recv_cq = *send_cq; 1357 break; 1358 default: 1359 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1360 to_mcq(qp->ibwq.cq); 1361 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1362 *recv_cq; 1363 break; 1364 } 1365 } 1366 1367 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1368 { 1369 if (qp->state != IB_QPS_RESET) { 1370 int i; 1371 1372 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1373 i++) { 1374 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1375 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1376 1377 mutex_lock(&wq->mutex); 1378 1379 wq->rss_usecnt--; 1380 1381 mutex_unlock(&wq->mutex); 1382 } 1383 1384 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1385 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1386 pr_warn("modify QP %06x to RESET failed.\n", 1387 qp->mqp.qpn); 1388 } 1389 1390 mlx4_qp_remove(dev->dev, &qp->mqp); 1391 mlx4_qp_free(dev->dev, &qp->mqp); 1392 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1393 del_gid_entries(qp); 1394 } 1395 1396 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1397 enum mlx4_ib_source_type src, 1398 struct ib_udata *udata) 1399 { 1400 struct mlx4_ib_cq *send_cq, *recv_cq; 1401 unsigned long flags; 1402 1403 if (qp->state != IB_QPS_RESET) { 1404 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1405 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1406 pr_warn("modify QP %06x to RESET failed.\n", 1407 qp->mqp.qpn); 1408 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1409 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1410 qp->pri.smac = 0; 1411 qp->pri.smac_port = 0; 1412 } 1413 if (qp->alt.smac) { 1414 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1415 qp->alt.smac = 0; 1416 } 1417 if (qp->pri.vid < 0x1000) { 1418 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1419 qp->pri.vid = 0xFFFF; 1420 qp->pri.candidate_vid = 0xFFFF; 1421 qp->pri.update_vid = 0; 1422 } 1423 if (qp->alt.vid < 0x1000) { 1424 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1425 qp->alt.vid = 0xFFFF; 1426 qp->alt.candidate_vid = 0xFFFF; 1427 qp->alt.update_vid = 0; 1428 } 1429 } 1430 1431 get_cqs(qp, src, &send_cq, &recv_cq); 1432 1433 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1434 mlx4_ib_lock_cqs(send_cq, recv_cq); 1435 1436 /* del from lists under both locks above to protect reset flow paths */ 1437 list_del(&qp->qps_list); 1438 list_del(&qp->cq_send_list); 1439 list_del(&qp->cq_recv_list); 1440 if (!udata) { 1441 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1442 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1443 if (send_cq != recv_cq) 1444 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1445 } 1446 1447 mlx4_qp_remove(dev->dev, &qp->mqp); 1448 1449 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1450 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1451 1452 mlx4_qp_free(dev->dev, &qp->mqp); 1453 1454 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1455 if (qp->flags & MLX4_IB_QP_NETIF) 1456 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1457 else if (src == MLX4_IB_RWQ_SRC) 1458 mlx4_ib_release_wqn( 1459 rdma_udata_to_drv_context( 1460 udata, 1461 struct mlx4_ib_ucontext, 1462 ibucontext), 1463 qp, 1); 1464 else 1465 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1466 } 1467 1468 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1469 1470 if (udata) { 1471 if (qp->rq.wqe_cnt) { 1472 struct mlx4_ib_ucontext *mcontext = 1473 rdma_udata_to_drv_context( 1474 udata, 1475 struct mlx4_ib_ucontext, 1476 ibucontext); 1477 1478 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1479 } 1480 } else { 1481 kvfree(qp->sq.wrid); 1482 kvfree(qp->rq.wrid); 1483 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1484 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1485 free_proxy_bufs(&dev->ib_dev, qp); 1486 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1487 if (qp->rq.wqe_cnt) 1488 mlx4_db_free(dev->dev, &qp->db); 1489 } 1490 ib_umem_release(qp->umem); 1491 1492 del_gid_entries(qp); 1493 } 1494 1495 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1496 { 1497 /* Native or PPF */ 1498 if (!mlx4_is_mfunc(dev->dev) || 1499 (mlx4_is_master(dev->dev) && 1500 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1501 return dev->dev->phys_caps.base_sqpn + 1502 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1503 attr->port_num - 1; 1504 } 1505 /* PF or VF -- creating proxies */ 1506 if (attr->qp_type == IB_QPT_SMI) 1507 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1508 else 1509 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1510 } 1511 1512 static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp, 1513 struct ib_qp_init_attr *init_attr, 1514 struct ib_udata *udata) 1515 { 1516 int err; 1517 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1518 u16 xrcdn = 0; 1519 1520 if (init_attr->rwq_ind_tbl) 1521 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata); 1522 1523 /* 1524 * We only support LSO, vendor flag1, and multicast loopback blocking, 1525 * and only for kernel UD QPs. 1526 */ 1527 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1528 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1529 MLX4_IB_SRIOV_TUNNEL_QP | 1530 MLX4_IB_SRIOV_SQP | 1531 MLX4_IB_QP_NETIF | 1532 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1533 return -EOPNOTSUPP; 1534 1535 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1536 if (init_attr->qp_type != IB_QPT_UD) 1537 return -EINVAL; 1538 } 1539 1540 if (init_attr->create_flags) { 1541 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1542 return -EINVAL; 1543 1544 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1545 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1546 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1547 init_attr->qp_type != IB_QPT_UD) || 1548 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1549 init_attr->qp_type > IB_QPT_GSI) || 1550 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1551 init_attr->qp_type != IB_QPT_GSI)) 1552 return -EINVAL; 1553 } 1554 1555 switch (init_attr->qp_type) { 1556 case IB_QPT_XRC_TGT: 1557 pd = to_mxrcd(init_attr->xrcd)->pd; 1558 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1559 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1560 fallthrough; 1561 case IB_QPT_XRC_INI: 1562 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1563 return -ENOSYS; 1564 init_attr->recv_cq = init_attr->send_cq; 1565 fallthrough; 1566 case IB_QPT_RC: 1567 case IB_QPT_UC: 1568 case IB_QPT_RAW_PACKET: 1569 case IB_QPT_UD: 1570 qp->pri.vid = 0xFFFF; 1571 qp->alt.vid = 0xFFFF; 1572 err = create_qp_common(pd, init_attr, udata, 0, qp); 1573 if (err) 1574 return err; 1575 1576 qp->ibqp.qp_num = qp->mqp.qpn; 1577 qp->xrcdn = xrcdn; 1578 break; 1579 case IB_QPT_SMI: 1580 case IB_QPT_GSI: 1581 { 1582 int sqpn; 1583 1584 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1585 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1586 1, 1, &sqpn, 0, 1587 MLX4_RES_USAGE_DRIVER); 1588 1589 if (res) 1590 return res; 1591 } else { 1592 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1593 } 1594 1595 qp->pri.vid = 0xFFFF; 1596 qp->alt.vid = 0xFFFF; 1597 err = create_qp_common(pd, init_attr, udata, sqpn, qp); 1598 if (err) 1599 return err; 1600 1601 if (init_attr->create_flags & 1602 (MLX4_IB_SRIOV_SQP | MLX4_IB_SRIOV_TUNNEL_QP)) 1603 /* Internal QP created with ib_create_qp */ 1604 rdma_restrack_no_track(&qp->ibqp.res); 1605 1606 qp->port = init_attr->port_num; 1607 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1608 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1609 break; 1610 } 1611 default: 1612 /* Don't support raw QPs */ 1613 return -EOPNOTSUPP; 1614 } 1615 return 0; 1616 } 1617 1618 int mlx4_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *init_attr, 1619 struct ib_udata *udata) 1620 { 1621 struct ib_device *device = ibqp->device; 1622 struct mlx4_ib_dev *dev = to_mdev(device); 1623 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1624 struct ib_pd *pd = ibqp->pd; 1625 int ret; 1626 1627 mutex_init(&qp->mutex); 1628 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata); 1629 if (ret) 1630 return ret; 1631 1632 if (init_attr->qp_type == IB_QPT_GSI && 1633 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1634 struct mlx4_ib_sqp *sqp = qp->sqp; 1635 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1636 1637 if (is_eth && 1638 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1639 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1640 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1641 1642 if (IS_ERR(sqp->roce_v2_gsi)) { 1643 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1644 sqp->roce_v2_gsi = NULL; 1645 } else { 1646 to_mqp(sqp->roce_v2_gsi)->flags |= 1647 MLX4_IB_ROCE_V2_GSI_QP; 1648 } 1649 1650 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1651 } 1652 } 1653 return 0; 1654 } 1655 1656 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1657 { 1658 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1659 struct mlx4_ib_qp *mqp = to_mqp(qp); 1660 1661 if (is_qp0(dev, mqp)) 1662 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1663 1664 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1665 dev->qp1_proxy[mqp->port - 1] == mqp) { 1666 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1667 dev->qp1_proxy[mqp->port - 1] = NULL; 1668 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1669 } 1670 1671 if (mqp->counter_index) 1672 mlx4_ib_free_qp_counter(dev, mqp); 1673 1674 if (qp->rwq_ind_tbl) { 1675 destroy_qp_rss(dev, mqp); 1676 } else { 1677 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata); 1678 } 1679 1680 kfree(mqp->sqp); 1681 return 0; 1682 } 1683 1684 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1685 { 1686 struct mlx4_ib_qp *mqp = to_mqp(qp); 1687 1688 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1689 struct mlx4_ib_sqp *sqp = mqp->sqp; 1690 1691 if (sqp->roce_v2_gsi) 1692 ib_destroy_qp(sqp->roce_v2_gsi); 1693 } 1694 1695 return _mlx4_ib_destroy_qp(qp, udata); 1696 } 1697 1698 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1699 { 1700 switch (type) { 1701 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1702 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1703 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1704 case MLX4_IB_QPT_XRC_INI: 1705 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1706 case MLX4_IB_QPT_SMI: 1707 case MLX4_IB_QPT_GSI: 1708 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1709 1710 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1711 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1712 MLX4_QP_ST_MLX : -1); 1713 case MLX4_IB_QPT_PROXY_SMI: 1714 case MLX4_IB_QPT_TUN_SMI: 1715 case MLX4_IB_QPT_PROXY_GSI: 1716 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1717 MLX4_QP_ST_UD : -1); 1718 default: return -1; 1719 } 1720 } 1721 1722 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1723 int attr_mask) 1724 { 1725 u8 dest_rd_atomic; 1726 u32 access_flags; 1727 u32 hw_access_flags = 0; 1728 1729 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1730 dest_rd_atomic = attr->max_dest_rd_atomic; 1731 else 1732 dest_rd_atomic = qp->resp_depth; 1733 1734 if (attr_mask & IB_QP_ACCESS_FLAGS) 1735 access_flags = attr->qp_access_flags; 1736 else 1737 access_flags = qp->atomic_rd_en; 1738 1739 if (!dest_rd_atomic) 1740 access_flags &= IB_ACCESS_REMOTE_WRITE; 1741 1742 if (access_flags & IB_ACCESS_REMOTE_READ) 1743 hw_access_flags |= MLX4_QP_BIT_RRE; 1744 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1745 hw_access_flags |= MLX4_QP_BIT_RAE; 1746 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1747 hw_access_flags |= MLX4_QP_BIT_RWE; 1748 1749 return cpu_to_be32(hw_access_flags); 1750 } 1751 1752 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1753 int attr_mask) 1754 { 1755 if (attr_mask & IB_QP_PKEY_INDEX) 1756 sqp->pkey_index = attr->pkey_index; 1757 if (attr_mask & IB_QP_QKEY) 1758 sqp->qkey = attr->qkey; 1759 if (attr_mask & IB_QP_SQ_PSN) 1760 sqp->send_psn = attr->sq_psn; 1761 } 1762 1763 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1764 { 1765 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1766 } 1767 1768 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1769 const struct rdma_ah_attr *ah, 1770 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1771 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1772 { 1773 int vidx; 1774 int smac_index; 1775 int err; 1776 1777 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1778 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1779 if (rdma_ah_get_static_rate(ah)) { 1780 path->static_rate = rdma_ah_get_static_rate(ah) + 1781 MLX4_STAT_RATE_OFFSET; 1782 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1783 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1784 --path->static_rate; 1785 } else 1786 path->static_rate = 0; 1787 1788 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1789 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1790 int real_sgid_index = 1791 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1792 1793 if (real_sgid_index < 0) 1794 return real_sgid_index; 1795 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1796 pr_err("sgid_index (%u) too large. max is %d\n", 1797 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1798 return -1; 1799 } 1800 1801 path->grh_mylmc |= 1 << 7; 1802 path->mgid_index = real_sgid_index; 1803 path->hop_limit = grh->hop_limit; 1804 path->tclass_flowlabel = 1805 cpu_to_be32((grh->traffic_class << 20) | 1806 (grh->flow_label)); 1807 memcpy(path->rgid, grh->dgid.raw, 16); 1808 } 1809 1810 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1811 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1812 return -1; 1813 1814 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1815 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1816 1817 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1818 if (vlan_tag < 0x1000) { 1819 if (smac_info->vid < 0x1000) { 1820 /* both valid vlan ids */ 1821 if (smac_info->vid != vlan_tag) { 1822 /* different VIDs. unreg old and reg new */ 1823 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1824 if (err) 1825 return err; 1826 smac_info->candidate_vid = vlan_tag; 1827 smac_info->candidate_vlan_index = vidx; 1828 smac_info->candidate_vlan_port = port; 1829 smac_info->update_vid = 1; 1830 path->vlan_index = vidx; 1831 } else { 1832 path->vlan_index = smac_info->vlan_index; 1833 } 1834 } else { 1835 /* no current vlan tag in qp */ 1836 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1837 if (err) 1838 return err; 1839 smac_info->candidate_vid = vlan_tag; 1840 smac_info->candidate_vlan_index = vidx; 1841 smac_info->candidate_vlan_port = port; 1842 smac_info->update_vid = 1; 1843 path->vlan_index = vidx; 1844 } 1845 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1846 path->fl = 1 << 6; 1847 } else { 1848 /* have current vlan tag. unregister it at modify-qp success */ 1849 if (smac_info->vid < 0x1000) { 1850 smac_info->candidate_vid = 0xFFFF; 1851 smac_info->update_vid = 1; 1852 } 1853 } 1854 1855 /* get smac_index for RoCE use. 1856 * If no smac was yet assigned, register one. 1857 * If one was already assigned, but the new mac differs, 1858 * unregister the old one and register the new one. 1859 */ 1860 if ((!smac_info->smac && !smac_info->smac_port) || 1861 smac_info->smac != smac) { 1862 /* register candidate now, unreg if needed, after success */ 1863 smac_index = mlx4_register_mac(dev->dev, port, smac); 1864 if (smac_index >= 0) { 1865 smac_info->candidate_smac_index = smac_index; 1866 smac_info->candidate_smac = smac; 1867 smac_info->candidate_smac_port = port; 1868 } else { 1869 return -EINVAL; 1870 } 1871 } else { 1872 smac_index = smac_info->smac_index; 1873 } 1874 memcpy(path->dmac, ah->roce.dmac, 6); 1875 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1876 /* put MAC table smac index for IBoE */ 1877 path->grh_mylmc = (u8) (smac_index) | 0x80; 1878 } else { 1879 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1880 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1881 } 1882 1883 return 0; 1884 } 1885 1886 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1887 enum ib_qp_attr_mask qp_attr_mask, 1888 struct mlx4_ib_qp *mqp, 1889 struct mlx4_qp_path *path, u8 port, 1890 u16 vlan_id, u8 *smac) 1891 { 1892 return _mlx4_set_path(dev, &qp->ah_attr, 1893 ether_addr_to_u64(smac), 1894 vlan_id, 1895 path, &mqp->pri, port); 1896 } 1897 1898 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1899 const struct ib_qp_attr *qp, 1900 enum ib_qp_attr_mask qp_attr_mask, 1901 struct mlx4_ib_qp *mqp, 1902 struct mlx4_qp_path *path, u8 port) 1903 { 1904 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1905 0, 1906 0xffff, 1907 path, &mqp->alt, port); 1908 } 1909 1910 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1911 { 1912 struct mlx4_ib_gid_entry *ge, *tmp; 1913 1914 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1915 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1916 ge->added = 1; 1917 ge->port = qp->port; 1918 } 1919 } 1920 } 1921 1922 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1923 struct mlx4_ib_qp *qp, 1924 struct mlx4_qp_context *context) 1925 { 1926 u64 u64_mac; 1927 int smac_index; 1928 1929 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1930 1931 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1932 if (!qp->pri.smac && !qp->pri.smac_port) { 1933 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1934 if (smac_index >= 0) { 1935 qp->pri.candidate_smac_index = smac_index; 1936 qp->pri.candidate_smac = u64_mac; 1937 qp->pri.candidate_smac_port = qp->port; 1938 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1939 } else { 1940 return -ENOENT; 1941 } 1942 } 1943 return 0; 1944 } 1945 1946 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1947 { 1948 struct counter_index *new_counter_index; 1949 int err; 1950 u32 tmp_idx; 1951 1952 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1953 IB_LINK_LAYER_ETHERNET || 1954 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1955 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1956 return 0; 1957 1958 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1959 if (err) 1960 return err; 1961 1962 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1963 if (!new_counter_index) { 1964 mlx4_counter_free(dev->dev, tmp_idx); 1965 return -ENOMEM; 1966 } 1967 1968 new_counter_index->index = tmp_idx; 1969 new_counter_index->allocated = 1; 1970 qp->counter_index = new_counter_index; 1971 1972 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1973 list_add_tail(&new_counter_index->list, 1974 &dev->counters_table[qp->port - 1].counters_list); 1975 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1976 1977 return 0; 1978 } 1979 1980 enum { 1981 MLX4_QPC_ROCE_MODE_1 = 0, 1982 MLX4_QPC_ROCE_MODE_2 = 2, 1983 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1984 }; 1985 1986 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1987 { 1988 switch (gid_type) { 1989 case IB_GID_TYPE_ROCE: 1990 return MLX4_QPC_ROCE_MODE_1; 1991 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1992 return MLX4_QPC_ROCE_MODE_2; 1993 default: 1994 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1995 } 1996 } 1997 1998 /* 1999 * Go over all RSS QP's childes (WQs) and apply their HW state according to 2000 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 2001 */ 2002 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num, 2003 struct ib_udata *udata) 2004 { 2005 int err = 0; 2006 int i; 2007 2008 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2009 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2010 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2011 2012 mutex_lock(&wq->mutex); 2013 2014 /* Mlx4_ib restrictions: 2015 * WQ's is associated to a port according to the RSS QP it is 2016 * associates to. 2017 * In case the WQ is associated to a different port by another 2018 * RSS QP, return a failure. 2019 */ 2020 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 2021 err = -EINVAL; 2022 mutex_unlock(&wq->mutex); 2023 break; 2024 } 2025 wq->port = port_num; 2026 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 2027 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata); 2028 if (err) { 2029 mutex_unlock(&wq->mutex); 2030 break; 2031 } 2032 } 2033 wq->rss_usecnt++; 2034 2035 mutex_unlock(&wq->mutex); 2036 } 2037 2038 if (i && err) { 2039 int j; 2040 2041 for (j = (i - 1); j >= 0; j--) { 2042 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 2043 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2044 2045 mutex_lock(&wq->mutex); 2046 2047 if ((wq->rss_usecnt == 1) && 2048 (ibwq->state == IB_WQS_RDY)) 2049 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, 2050 udata)) 2051 pr_warn("failed to reverse WQN=0x%06x\n", 2052 ibwq->wq_num); 2053 wq->rss_usecnt--; 2054 2055 mutex_unlock(&wq->mutex); 2056 } 2057 } 2058 2059 return err; 2060 } 2061 2062 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, 2063 struct ib_udata *udata) 2064 { 2065 int i; 2066 2067 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2068 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2069 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2070 2071 mutex_lock(&wq->mutex); 2072 2073 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2074 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata)) 2075 pr_warn("failed to reverse WQN=%x\n", 2076 ibwq->wq_num); 2077 wq->rss_usecnt--; 2078 2079 mutex_unlock(&wq->mutex); 2080 } 2081 } 2082 2083 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2084 struct mlx4_ib_qp *qp) 2085 { 2086 struct mlx4_rss_context *rss_context; 2087 2088 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2089 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2090 2091 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2092 rss_context->default_qpn = 2093 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2094 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2095 rss_context->base_qpn_udp = rss_context->default_qpn; 2096 rss_context->flags = qp->rss_ctx->flags; 2097 /* Currently support just toeplitz */ 2098 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2099 2100 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2101 MLX4_EN_RSS_KEY_SIZE); 2102 } 2103 2104 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2105 const struct ib_qp_attr *attr, int attr_mask, 2106 enum ib_qp_state cur_state, 2107 enum ib_qp_state new_state, 2108 struct ib_udata *udata) 2109 { 2110 struct ib_srq *ibsrq; 2111 const struct ib_gid_attr *gid_attr = NULL; 2112 struct ib_rwq_ind_table *rwq_ind_tbl; 2113 enum ib_qp_type qp_type; 2114 struct mlx4_ib_dev *dev; 2115 struct mlx4_ib_qp *qp; 2116 struct mlx4_ib_pd *pd; 2117 struct mlx4_ib_cq *send_cq, *recv_cq; 2118 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2119 udata, struct mlx4_ib_ucontext, ibucontext); 2120 struct mlx4_qp_context *context; 2121 enum mlx4_qp_optpar optpar = 0; 2122 int sqd_event; 2123 int steer_qp = 0; 2124 int err = -EINVAL; 2125 int counter_index; 2126 2127 if (src_type == MLX4_IB_RWQ_SRC) { 2128 struct ib_wq *ibwq; 2129 2130 ibwq = (struct ib_wq *)src; 2131 ibsrq = NULL; 2132 rwq_ind_tbl = NULL; 2133 qp_type = IB_QPT_RAW_PACKET; 2134 qp = to_mqp((struct ib_qp *)ibwq); 2135 dev = to_mdev(ibwq->device); 2136 pd = to_mpd(ibwq->pd); 2137 } else { 2138 struct ib_qp *ibqp; 2139 2140 ibqp = (struct ib_qp *)src; 2141 ibsrq = ibqp->srq; 2142 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2143 qp_type = ibqp->qp_type; 2144 qp = to_mqp(ibqp); 2145 dev = to_mdev(ibqp->device); 2146 pd = get_pd(qp); 2147 } 2148 2149 /* APM is not supported under RoCE */ 2150 if (attr_mask & IB_QP_ALT_PATH && 2151 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2152 IB_LINK_LAYER_ETHERNET) 2153 return -ENOTSUPP; 2154 2155 context = kzalloc(sizeof *context, GFP_KERNEL); 2156 if (!context) 2157 return -ENOMEM; 2158 2159 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2160 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2161 2162 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2163 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2164 else { 2165 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2166 switch (attr->path_mig_state) { 2167 case IB_MIG_MIGRATED: 2168 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2169 break; 2170 case IB_MIG_REARM: 2171 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2172 break; 2173 case IB_MIG_ARMED: 2174 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2175 break; 2176 } 2177 } 2178 2179 if (qp->inl_recv_sz) 2180 context->param3 |= cpu_to_be32(1 << 25); 2181 2182 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2183 context->param3 |= cpu_to_be32(1 << 29); 2184 2185 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2186 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2187 else if (qp_type == IB_QPT_RAW_PACKET) 2188 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2189 else if (qp_type == IB_QPT_UD) { 2190 if (qp->flags & MLX4_IB_QP_LSO) 2191 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2192 ilog2(dev->dev->caps.max_gso_sz); 2193 else 2194 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2195 } else if (attr_mask & IB_QP_PATH_MTU) { 2196 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2197 pr_err("path MTU (%u) is invalid\n", 2198 attr->path_mtu); 2199 goto out; 2200 } 2201 context->mtu_msgmax = (attr->path_mtu << 5) | 2202 ilog2(dev->dev->caps.max_msg_sz); 2203 } 2204 2205 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2206 if (qp->rq.wqe_cnt) 2207 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2208 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2209 } 2210 2211 if (qp->sq.wqe_cnt) 2212 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2213 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2214 2215 if (new_state == IB_QPS_RESET && qp->counter_index) 2216 mlx4_ib_free_qp_counter(dev, qp); 2217 2218 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2219 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2220 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2221 if (qp_type == IB_QPT_RAW_PACKET) 2222 context->param3 |= cpu_to_be32(1 << 30); 2223 } 2224 2225 if (ucontext) 2226 context->usr_page = cpu_to_be32( 2227 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 2228 else 2229 context->usr_page = cpu_to_be32( 2230 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2231 2232 if (attr_mask & IB_QP_DEST_QPN) 2233 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2234 2235 if (attr_mask & IB_QP_PORT) { 2236 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2237 !(attr_mask & IB_QP_AV)) { 2238 mlx4_set_sched(&context->pri_path, attr->port_num); 2239 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2240 } 2241 } 2242 2243 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2244 err = create_qp_lb_counter(dev, qp); 2245 if (err) 2246 goto out; 2247 2248 counter_index = 2249 dev->counters_table[qp->port - 1].default_counter; 2250 if (qp->counter_index) 2251 counter_index = qp->counter_index->index; 2252 2253 if (counter_index != -1) { 2254 context->pri_path.counter_index = counter_index; 2255 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2256 if (qp->counter_index) { 2257 context->pri_path.fl |= 2258 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2259 context->pri_path.vlan_control |= 2260 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2261 } 2262 } else 2263 context->pri_path.counter_index = 2264 MLX4_SINK_COUNTER_INDEX(dev->dev); 2265 2266 if (qp->flags & MLX4_IB_QP_NETIF) { 2267 mlx4_ib_steer_qp_reg(dev, qp, 1); 2268 steer_qp = 1; 2269 } 2270 2271 if (qp_type == IB_QPT_GSI) { 2272 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2273 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2274 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2275 2276 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2277 } 2278 } 2279 2280 if (attr_mask & IB_QP_PKEY_INDEX) { 2281 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2282 context->pri_path.disable_pkey_check = 0x40; 2283 context->pri_path.pkey_index = attr->pkey_index; 2284 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2285 } 2286 2287 if (attr_mask & IB_QP_AV) { 2288 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2289 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2290 u16 vlan = 0xffff; 2291 u8 smac[ETH_ALEN]; 2292 int is_eth = 2293 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2294 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2295 2296 if (is_eth) { 2297 gid_attr = attr->ah_attr.grh.sgid_attr; 2298 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 2299 &smac[0]); 2300 if (err) 2301 goto out; 2302 } 2303 2304 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2305 port_num, vlan, smac)) 2306 goto out; 2307 2308 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2309 MLX4_QP_OPTPAR_SCHED_QUEUE); 2310 2311 if (is_eth && 2312 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2313 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2314 2315 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2316 err = -EINVAL; 2317 goto out; 2318 } 2319 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2320 } 2321 2322 } 2323 2324 if (attr_mask & IB_QP_TIMEOUT) { 2325 context->pri_path.ackto |= attr->timeout << 3; 2326 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2327 } 2328 2329 if (attr_mask & IB_QP_ALT_PATH) { 2330 if (attr->alt_port_num == 0 || 2331 attr->alt_port_num > dev->dev->caps.num_ports) 2332 goto out; 2333 2334 if (attr->alt_pkey_index >= 2335 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2336 goto out; 2337 2338 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2339 &context->alt_path, 2340 attr->alt_port_num)) 2341 goto out; 2342 2343 context->alt_path.pkey_index = attr->alt_pkey_index; 2344 context->alt_path.ackto = attr->alt_timeout << 3; 2345 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2346 } 2347 2348 context->pd = cpu_to_be32(pd->pdn); 2349 2350 if (!rwq_ind_tbl) { 2351 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2352 get_cqs(qp, src_type, &send_cq, &recv_cq); 2353 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2354 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2355 recv_cq = send_cq; 2356 } 2357 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2358 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2359 2360 /* Set "fast registration enabled" for all kernel QPs */ 2361 if (!ucontext) 2362 context->params1 |= cpu_to_be32(1 << 11); 2363 2364 if (attr_mask & IB_QP_RNR_RETRY) { 2365 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2366 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2367 } 2368 2369 if (attr_mask & IB_QP_RETRY_CNT) { 2370 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2371 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2372 } 2373 2374 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2375 if (attr->max_rd_atomic) 2376 context->params1 |= 2377 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2378 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2379 } 2380 2381 if (attr_mask & IB_QP_SQ_PSN) 2382 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2383 2384 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2385 if (attr->max_dest_rd_atomic) 2386 context->params2 |= 2387 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2388 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2389 } 2390 2391 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2392 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2393 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2394 } 2395 2396 if (ibsrq) 2397 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2398 2399 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2400 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2401 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2402 } 2403 if (attr_mask & IB_QP_RQ_PSN) 2404 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2405 2406 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2407 if (attr_mask & IB_QP_QKEY) { 2408 if (qp->mlx4_ib_qp_type & 2409 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2410 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2411 else { 2412 if (mlx4_is_mfunc(dev->dev) && 2413 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2414 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2415 MLX4_RESERVED_QKEY_BASE) { 2416 pr_err("Cannot use reserved QKEY" 2417 " 0x%x (range 0xffff0000..0xffffffff" 2418 " is reserved)\n", attr->qkey); 2419 err = -EINVAL; 2420 goto out; 2421 } 2422 context->qkey = cpu_to_be32(attr->qkey); 2423 } 2424 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2425 } 2426 2427 if (ibsrq) 2428 context->srqn = cpu_to_be32(1 << 24 | 2429 to_msrq(ibsrq)->msrq.srqn); 2430 2431 if (qp->rq.wqe_cnt && 2432 cur_state == IB_QPS_RESET && 2433 new_state == IB_QPS_INIT) 2434 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2435 2436 if (cur_state == IB_QPS_INIT && 2437 new_state == IB_QPS_RTR && 2438 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2439 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2440 context->pri_path.sched_queue = (qp->port - 1) << 6; 2441 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2442 qp->mlx4_ib_qp_type & 2443 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2444 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2445 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2446 context->pri_path.fl = 0x80; 2447 } else { 2448 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2449 context->pri_path.fl = 0x80; 2450 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2451 } 2452 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2453 IB_LINK_LAYER_ETHERNET) { 2454 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2455 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2456 context->pri_path.feup = 1 << 7; /* don't fsm */ 2457 /* handle smac_index */ 2458 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2459 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2460 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2461 err = handle_eth_ud_smac_index(dev, qp, context); 2462 if (err) { 2463 err = -EINVAL; 2464 goto out; 2465 } 2466 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2467 dev->qp1_proxy[qp->port - 1] = qp; 2468 } 2469 } 2470 } 2471 2472 if (qp_type == IB_QPT_RAW_PACKET) { 2473 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2474 MLX4_IB_LINK_TYPE_ETH; 2475 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2476 /* set QP to receive both tunneled & non-tunneled packets */ 2477 if (!rwq_ind_tbl) 2478 context->srqn = cpu_to_be32(7 << 28); 2479 } 2480 } 2481 2482 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2483 int is_eth = rdma_port_get_link_layer( 2484 &dev->ib_dev, qp->port) == 2485 IB_LINK_LAYER_ETHERNET; 2486 if (is_eth) { 2487 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2488 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2489 } 2490 } 2491 2492 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2493 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2494 sqd_event = 1; 2495 else 2496 sqd_event = 0; 2497 2498 if (!ucontext && 2499 cur_state == IB_QPS_RESET && 2500 new_state == IB_QPS_INIT) 2501 context->rlkey_roce_mode |= (1 << 4); 2502 2503 /* 2504 * Before passing a kernel QP to the HW, make sure that the 2505 * ownership bits of the send queue are set and the SQ 2506 * headroom is stamped so that the hardware doesn't start 2507 * processing stale work requests. 2508 */ 2509 if (!ucontext && 2510 cur_state == IB_QPS_RESET && 2511 new_state == IB_QPS_INIT) { 2512 struct mlx4_wqe_ctrl_seg *ctrl; 2513 int i; 2514 2515 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2516 ctrl = get_send_wqe(qp, i); 2517 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2518 ctrl->qpn_vlan.fence_size = 2519 1 << (qp->sq.wqe_shift - 4); 2520 stamp_send_wqe(qp, i); 2521 } 2522 } 2523 2524 if (rwq_ind_tbl && 2525 cur_state == IB_QPS_RESET && 2526 new_state == IB_QPS_INIT) { 2527 fill_qp_rss_context(context, qp); 2528 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2529 } 2530 2531 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2532 to_mlx4_state(new_state), context, optpar, 2533 sqd_event, &qp->mqp); 2534 if (err) 2535 goto out; 2536 2537 qp->state = new_state; 2538 2539 if (attr_mask & IB_QP_ACCESS_FLAGS) 2540 qp->atomic_rd_en = attr->qp_access_flags; 2541 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2542 qp->resp_depth = attr->max_dest_rd_atomic; 2543 if (attr_mask & IB_QP_PORT) { 2544 qp->port = attr->port_num; 2545 update_mcg_macs(dev, qp); 2546 } 2547 if (attr_mask & IB_QP_ALT_PATH) 2548 qp->alt_port = attr->alt_port_num; 2549 2550 if (is_sqp(dev, qp)) 2551 store_sqp_attrs(qp->sqp, attr, attr_mask); 2552 2553 /* 2554 * If we moved QP0 to RTR, bring the IB link up; if we moved 2555 * QP0 to RESET or ERROR, bring the link back down. 2556 */ 2557 if (is_qp0(dev, qp)) { 2558 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2559 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2560 pr_warn("INIT_PORT failed for port %d\n", 2561 qp->port); 2562 2563 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2564 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2565 mlx4_CLOSE_PORT(dev->dev, qp->port); 2566 } 2567 2568 /* 2569 * If we moved a kernel QP to RESET, clean up all old CQ 2570 * entries and reinitialize the QP. 2571 */ 2572 if (new_state == IB_QPS_RESET) { 2573 if (!ucontext) { 2574 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2575 ibsrq ? to_msrq(ibsrq) : NULL); 2576 if (send_cq != recv_cq) 2577 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2578 2579 qp->rq.head = 0; 2580 qp->rq.tail = 0; 2581 qp->sq.head = 0; 2582 qp->sq.tail = 0; 2583 qp->sq_next_wqe = 0; 2584 if (qp->rq.wqe_cnt) 2585 *qp->db.db = 0; 2586 2587 if (qp->flags & MLX4_IB_QP_NETIF) 2588 mlx4_ib_steer_qp_reg(dev, qp, 0); 2589 } 2590 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2591 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2592 qp->pri.smac = 0; 2593 qp->pri.smac_port = 0; 2594 } 2595 if (qp->alt.smac) { 2596 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2597 qp->alt.smac = 0; 2598 } 2599 if (qp->pri.vid < 0x1000) { 2600 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2601 qp->pri.vid = 0xFFFF; 2602 qp->pri.candidate_vid = 0xFFFF; 2603 qp->pri.update_vid = 0; 2604 } 2605 2606 if (qp->alt.vid < 0x1000) { 2607 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2608 qp->alt.vid = 0xFFFF; 2609 qp->alt.candidate_vid = 0xFFFF; 2610 qp->alt.update_vid = 0; 2611 } 2612 } 2613 out: 2614 if (err && qp->counter_index) 2615 mlx4_ib_free_qp_counter(dev, qp); 2616 if (err && steer_qp) 2617 mlx4_ib_steer_qp_reg(dev, qp, 0); 2618 kfree(context); 2619 if (qp->pri.candidate_smac || 2620 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2621 if (err) { 2622 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2623 } else { 2624 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2625 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2626 qp->pri.smac = qp->pri.candidate_smac; 2627 qp->pri.smac_index = qp->pri.candidate_smac_index; 2628 qp->pri.smac_port = qp->pri.candidate_smac_port; 2629 } 2630 qp->pri.candidate_smac = 0; 2631 qp->pri.candidate_smac_index = 0; 2632 qp->pri.candidate_smac_port = 0; 2633 } 2634 if (qp->alt.candidate_smac) { 2635 if (err) { 2636 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2637 } else { 2638 if (qp->alt.smac) 2639 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2640 qp->alt.smac = qp->alt.candidate_smac; 2641 qp->alt.smac_index = qp->alt.candidate_smac_index; 2642 qp->alt.smac_port = qp->alt.candidate_smac_port; 2643 } 2644 qp->alt.candidate_smac = 0; 2645 qp->alt.candidate_smac_index = 0; 2646 qp->alt.candidate_smac_port = 0; 2647 } 2648 2649 if (qp->pri.update_vid) { 2650 if (err) { 2651 if (qp->pri.candidate_vid < 0x1000) 2652 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2653 qp->pri.candidate_vid); 2654 } else { 2655 if (qp->pri.vid < 0x1000) 2656 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2657 qp->pri.vid); 2658 qp->pri.vid = qp->pri.candidate_vid; 2659 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2660 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2661 } 2662 qp->pri.candidate_vid = 0xFFFF; 2663 qp->pri.update_vid = 0; 2664 } 2665 2666 if (qp->alt.update_vid) { 2667 if (err) { 2668 if (qp->alt.candidate_vid < 0x1000) 2669 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2670 qp->alt.candidate_vid); 2671 } else { 2672 if (qp->alt.vid < 0x1000) 2673 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2674 qp->alt.vid); 2675 qp->alt.vid = qp->alt.candidate_vid; 2676 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2677 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2678 } 2679 qp->alt.candidate_vid = 0xFFFF; 2680 qp->alt.update_vid = 0; 2681 } 2682 2683 return err; 2684 } 2685 2686 enum { 2687 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2688 IB_QP_PORT), 2689 }; 2690 2691 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2692 int attr_mask, struct ib_udata *udata) 2693 { 2694 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2695 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2696 enum ib_qp_state cur_state, new_state; 2697 int err = -EINVAL; 2698 mutex_lock(&qp->mutex); 2699 2700 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2701 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2702 2703 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2704 attr_mask)) { 2705 pr_debug("qpn 0x%x: invalid attribute mask specified " 2706 "for transition %d to %d. qp_type %d," 2707 " attr_mask 0x%x\n", 2708 ibqp->qp_num, cur_state, new_state, 2709 ibqp->qp_type, attr_mask); 2710 goto out; 2711 } 2712 2713 if (ibqp->rwq_ind_tbl) { 2714 if (!(((cur_state == IB_QPS_RESET) && 2715 (new_state == IB_QPS_INIT)) || 2716 ((cur_state == IB_QPS_INIT) && 2717 (new_state == IB_QPS_RTR)))) { 2718 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2719 ibqp->qp_num, cur_state, new_state); 2720 2721 err = -EOPNOTSUPP; 2722 goto out; 2723 } 2724 2725 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2726 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2727 ibqp->qp_num, attr_mask, cur_state, new_state); 2728 2729 err = -EOPNOTSUPP; 2730 goto out; 2731 } 2732 } 2733 2734 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2735 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2736 if ((ibqp->qp_type == IB_QPT_RC) || 2737 (ibqp->qp_type == IB_QPT_UD) || 2738 (ibqp->qp_type == IB_QPT_UC) || 2739 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2740 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2741 attr->port_num = mlx4_ib_bond_next_port(dev); 2742 } 2743 } else { 2744 /* no sense in changing port_num 2745 * when ports are bonded */ 2746 attr_mask &= ~IB_QP_PORT; 2747 } 2748 } 2749 2750 if ((attr_mask & IB_QP_PORT) && 2751 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2752 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2753 "for transition %d to %d. qp_type %d\n", 2754 ibqp->qp_num, attr->port_num, cur_state, 2755 new_state, ibqp->qp_type); 2756 goto out; 2757 } 2758 2759 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2760 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2761 IB_LINK_LAYER_ETHERNET)) 2762 goto out; 2763 2764 if (attr_mask & IB_QP_PKEY_INDEX) { 2765 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2766 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2767 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2768 "for transition %d to %d. qp_type %d\n", 2769 ibqp->qp_num, attr->pkey_index, cur_state, 2770 new_state, ibqp->qp_type); 2771 goto out; 2772 } 2773 } 2774 2775 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2776 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2777 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2778 "Transition %d to %d. qp_type %d\n", 2779 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2780 new_state, ibqp->qp_type); 2781 goto out; 2782 } 2783 2784 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2785 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2786 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2787 "Transition %d to %d. qp_type %d\n", 2788 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2789 new_state, ibqp->qp_type); 2790 goto out; 2791 } 2792 2793 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2794 err = 0; 2795 goto out; 2796 } 2797 2798 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2799 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num, 2800 udata); 2801 if (err) 2802 goto out; 2803 } 2804 2805 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2806 cur_state, new_state, udata); 2807 2808 if (ibqp->rwq_ind_tbl && err) 2809 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata); 2810 2811 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2812 attr->port_num = 1; 2813 2814 out: 2815 mutex_unlock(&qp->mutex); 2816 return err; 2817 } 2818 2819 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2820 int attr_mask, struct ib_udata *udata) 2821 { 2822 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2823 int ret; 2824 2825 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 2826 return -EOPNOTSUPP; 2827 2828 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2829 2830 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2831 struct mlx4_ib_sqp *sqp = mqp->sqp; 2832 int err = 0; 2833 2834 if (sqp->roce_v2_gsi) 2835 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2836 if (err) 2837 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2838 err); 2839 } 2840 return ret; 2841 } 2842 2843 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2844 { 2845 int i; 2846 for (i = 0; i < dev->caps.num_ports; i++) { 2847 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2848 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2849 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2850 return 0; 2851 } 2852 } 2853 return -EINVAL; 2854 } 2855 2856 static int build_sriov_qp0_header(struct mlx4_ib_qp *qp, 2857 const struct ib_ud_wr *wr, 2858 void *wqe, unsigned *mlx_seg_len) 2859 { 2860 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device); 2861 struct mlx4_ib_sqp *sqp = qp->sqp; 2862 struct ib_device *ib_dev = qp->ibqp.device; 2863 struct mlx4_wqe_mlx_seg *mlx = wqe; 2864 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2865 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2866 u16 pkey; 2867 u32 qkey; 2868 int send_size; 2869 int header_size; 2870 int spc; 2871 int err; 2872 int i; 2873 2874 if (wr->wr.opcode != IB_WR_SEND) 2875 return -EINVAL; 2876 2877 send_size = 0; 2878 2879 for (i = 0; i < wr->wr.num_sge; ++i) 2880 send_size += wr->wr.sg_list[i].length; 2881 2882 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2883 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2884 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2885 send_size += sizeof (struct mlx4_ib_tunnel_header); 2886 2887 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2888 2889 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2890 sqp->ud_header.lrh.service_level = 2891 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2892 sqp->ud_header.lrh.destination_lid = 2893 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2894 sqp->ud_header.lrh.source_lid = 2895 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2896 } 2897 2898 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2899 2900 /* force loopback */ 2901 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2902 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2903 2904 sqp->ud_header.lrh.virtual_lane = 0; 2905 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2906 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey); 2907 if (err) 2908 return err; 2909 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2910 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2911 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2912 else 2913 sqp->ud_header.bth.destination_qpn = 2914 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel); 2915 2916 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2917 if (mlx4_is_master(mdev->dev)) { 2918 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2919 return -EINVAL; 2920 } else { 2921 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2922 return -EINVAL; 2923 } 2924 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2925 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn); 2926 2927 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2928 sqp->ud_header.immediate_present = 0; 2929 2930 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2931 2932 /* 2933 * Inline data segments may not cross a 64 byte boundary. If 2934 * our UD header is bigger than the space available up to the 2935 * next 64 byte boundary in the WQE, use two inline data 2936 * segments to hold the UD header. 2937 */ 2938 spc = MLX4_INLINE_ALIGN - 2939 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2940 if (header_size <= spc) { 2941 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2942 memcpy(inl + 1, sqp->header_buf, header_size); 2943 i = 1; 2944 } else { 2945 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2946 memcpy(inl + 1, sqp->header_buf, spc); 2947 2948 inl = (void *) (inl + 1) + spc; 2949 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2950 /* 2951 * Need a barrier here to make sure all the data is 2952 * visible before the byte_count field is set. 2953 * Otherwise the HCA prefetcher could grab the 64-byte 2954 * chunk with this inline segment and get a valid (!= 2955 * 0xffffffff) byte count but stale data, and end up 2956 * generating a packet with bad headers. 2957 * 2958 * The first inline segment's byte_count field doesn't 2959 * need a barrier, because it comes after a 2960 * control/MLX segment and therefore is at an offset 2961 * of 16 mod 64. 2962 */ 2963 wmb(); 2964 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2965 i = 2; 2966 } 2967 2968 *mlx_seg_len = 2969 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2970 return 0; 2971 } 2972 2973 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2974 { 2975 union sl2vl_tbl_to_u64 tmp_vltab; 2976 u8 vl; 2977 2978 if (sl > 15) 2979 return 0xf; 2980 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2981 vl = tmp_vltab.sl8[sl >> 1]; 2982 if (sl & 1) 2983 vl &= 0x0f; 2984 else 2985 vl >>= 4; 2986 return vl; 2987 } 2988 2989 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2990 int index, union ib_gid *gid, 2991 enum ib_gid_type *gid_type) 2992 { 2993 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2994 struct mlx4_port_gid_table *port_gid_table; 2995 unsigned long flags; 2996 2997 port_gid_table = &iboe->gids[port_num - 1]; 2998 spin_lock_irqsave(&iboe->lock, flags); 2999 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 3000 *gid_type = port_gid_table->gids[index].gid_type; 3001 spin_unlock_irqrestore(&iboe->lock, flags); 3002 if (rdma_is_zero_gid(gid)) 3003 return -ENOENT; 3004 3005 return 0; 3006 } 3007 3008 #define MLX4_ROCEV2_QP1_SPORT 0xC000 3009 static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr, 3010 void *wqe, unsigned *mlx_seg_len) 3011 { 3012 struct mlx4_ib_sqp *sqp = qp->sqp; 3013 struct ib_device *ib_dev = qp->ibqp.device; 3014 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 3015 struct mlx4_wqe_mlx_seg *mlx = wqe; 3016 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 3017 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 3018 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3019 union ib_gid sgid; 3020 u16 pkey; 3021 int send_size; 3022 int header_size; 3023 int spc; 3024 int i; 3025 int err = 0; 3026 u16 vlan = 0xffff; 3027 bool is_eth; 3028 bool is_vlan = false; 3029 bool is_grh; 3030 bool is_udp = false; 3031 int ip_version = 0; 3032 3033 send_size = 0; 3034 for (i = 0; i < wr->wr.num_sge; ++i) 3035 send_size += wr->wr.sg_list[i].length; 3036 3037 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET; 3038 is_grh = mlx4_ib_ah_grh_present(ah); 3039 if (is_eth) { 3040 enum ib_gid_type gid_type; 3041 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3042 /* When multi-function is enabled, the ib_core gid 3043 * indexes don't necessarily match the hw ones, so 3044 * we must use our own cache */ 3045 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 3046 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3047 ah->av.ib.gid_index, &sgid.raw[0]); 3048 if (err) 3049 return err; 3050 } else { 3051 err = fill_gid_by_hw_index(ibdev, qp->port, 3052 ah->av.ib.gid_index, &sgid, 3053 &gid_type); 3054 if (!err) { 3055 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3056 if (is_udp) { 3057 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3058 ip_version = 4; 3059 else 3060 ip_version = 6; 3061 is_grh = false; 3062 } 3063 } else { 3064 return err; 3065 } 3066 } 3067 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3068 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3069 is_vlan = true; 3070 } 3071 } 3072 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3073 ip_version, is_udp, 0, &sqp->ud_header); 3074 if (err) 3075 return err; 3076 3077 if (!is_eth) { 3078 sqp->ud_header.lrh.service_level = 3079 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3080 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3081 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3082 } 3083 3084 if (is_grh || (ip_version == 6)) { 3085 sqp->ud_header.grh.traffic_class = 3086 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3087 sqp->ud_header.grh.flow_label = 3088 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3089 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3090 if (is_eth) { 3091 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3092 } else { 3093 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3094 /* When multi-function is enabled, the ib_core gid 3095 * indexes don't necessarily match the hw ones, so 3096 * we must use our own cache 3097 */ 3098 sqp->ud_header.grh.source_gid.global 3099 .subnet_prefix = 3100 cpu_to_be64(atomic64_read( 3101 &(to_mdev(ib_dev) 3102 ->sriov 3103 .demux[qp->port - 1] 3104 .subnet_prefix))); 3105 sqp->ud_header.grh.source_gid.global 3106 .interface_id = 3107 to_mdev(ib_dev) 3108 ->sriov.demux[qp->port - 1] 3109 .guid_cache[ah->av.ib.gid_index]; 3110 } else { 3111 sqp->ud_header.grh.source_gid = 3112 ah->ibah.sgid_attr->gid; 3113 } 3114 } 3115 memcpy(sqp->ud_header.grh.destination_gid.raw, 3116 ah->av.ib.dgid, 16); 3117 } 3118 3119 if (ip_version == 4) { 3120 sqp->ud_header.ip4.tos = 3121 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3122 sqp->ud_header.ip4.id = 0; 3123 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3124 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3125 3126 memcpy(&sqp->ud_header.ip4.saddr, 3127 sgid.raw + 12, 4); 3128 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3129 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3130 } 3131 3132 if (is_udp) { 3133 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3134 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3135 sqp->ud_header.udp.csum = 0; 3136 } 3137 3138 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3139 3140 if (!is_eth) { 3141 mlx->flags |= 3142 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3143 (sqp->ud_header.lrh.destination_lid == 3144 IB_LID_PERMISSIVE ? 3145 MLX4_WQE_MLX_SLR : 3146 0) | 3147 (sqp->ud_header.lrh.service_level << 8)); 3148 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3149 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3150 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3151 } 3152 3153 switch (wr->wr.opcode) { 3154 case IB_WR_SEND: 3155 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3156 sqp->ud_header.immediate_present = 0; 3157 break; 3158 case IB_WR_SEND_WITH_IMM: 3159 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3160 sqp->ud_header.immediate_present = 1; 3161 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3162 break; 3163 default: 3164 return -EINVAL; 3165 } 3166 3167 if (is_eth) { 3168 u16 ether_type; 3169 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3170 3171 ether_type = (!is_udp) ? ETH_P_IBOE: 3172 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3173 3174 mlx->sched_prio = cpu_to_be16(pcp); 3175 3176 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3177 ether_addr_copy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac); 3178 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3179 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3180 3181 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3182 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3183 if (!is_vlan) { 3184 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3185 } else { 3186 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3187 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3188 } 3189 } else { 3190 sqp->ud_header.lrh.virtual_lane = 3191 !qp->ibqp.qp_num ? 3192 15 : 3193 sl_to_vl(to_mdev(ib_dev), 3194 sqp->ud_header.lrh.service_level, 3195 qp->port); 3196 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3197 return -EINVAL; 3198 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3199 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3200 } 3201 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3202 if (!qp->ibqp.qp_num) 3203 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index, 3204 &pkey); 3205 else 3206 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index, 3207 &pkey); 3208 if (err) 3209 return err; 3210 3211 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3212 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3213 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3214 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3215 sqp->qkey : wr->remote_qkey); 3216 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num); 3217 3218 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3219 3220 if (0) { 3221 pr_err("built UD header of size %d:\n", header_size); 3222 for (i = 0; i < header_size / 4; ++i) { 3223 if (i % 8 == 0) 3224 pr_err(" [%02x] ", i * 4); 3225 pr_cont(" %08x", 3226 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3227 if ((i + 1) % 8 == 0) 3228 pr_cont("\n"); 3229 } 3230 pr_err("\n"); 3231 } 3232 3233 /* 3234 * Inline data segments may not cross a 64 byte boundary. If 3235 * our UD header is bigger than the space available up to the 3236 * next 64 byte boundary in the WQE, use two inline data 3237 * segments to hold the UD header. 3238 */ 3239 spc = MLX4_INLINE_ALIGN - 3240 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3241 if (header_size <= spc) { 3242 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3243 memcpy(inl + 1, sqp->header_buf, header_size); 3244 i = 1; 3245 } else { 3246 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3247 memcpy(inl + 1, sqp->header_buf, spc); 3248 3249 inl = (void *) (inl + 1) + spc; 3250 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3251 /* 3252 * Need a barrier here to make sure all the data is 3253 * visible before the byte_count field is set. 3254 * Otherwise the HCA prefetcher could grab the 64-byte 3255 * chunk with this inline segment and get a valid (!= 3256 * 0xffffffff) byte count but stale data, and end up 3257 * generating a packet with bad headers. 3258 * 3259 * The first inline segment's byte_count field doesn't 3260 * need a barrier, because it comes after a 3261 * control/MLX segment and therefore is at an offset 3262 * of 16 mod 64. 3263 */ 3264 wmb(); 3265 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3266 i = 2; 3267 } 3268 3269 *mlx_seg_len = 3270 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3271 return 0; 3272 } 3273 3274 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3275 { 3276 unsigned cur; 3277 struct mlx4_ib_cq *cq; 3278 3279 cur = wq->head - wq->tail; 3280 if (likely(cur + nreq < wq->max_post)) 3281 return 0; 3282 3283 cq = to_mcq(ib_cq); 3284 spin_lock(&cq->lock); 3285 cur = wq->head - wq->tail; 3286 spin_unlock(&cq->lock); 3287 3288 return cur + nreq >= wq->max_post; 3289 } 3290 3291 static __be32 convert_access(int acc) 3292 { 3293 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3294 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3295 (acc & IB_ACCESS_REMOTE_WRITE ? 3296 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3297 (acc & IB_ACCESS_REMOTE_READ ? 3298 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3299 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3300 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3301 } 3302 3303 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3304 const struct ib_reg_wr *wr) 3305 { 3306 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3307 3308 fseg->flags = convert_access(wr->access); 3309 fseg->mem_key = cpu_to_be32(wr->key); 3310 fseg->buf_list = cpu_to_be64(mr->page_map); 3311 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3312 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3313 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3314 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3315 fseg->reserved[0] = 0; 3316 fseg->reserved[1] = 0; 3317 } 3318 3319 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3320 { 3321 memset(iseg, 0, sizeof(*iseg)); 3322 iseg->mem_key = cpu_to_be32(rkey); 3323 } 3324 3325 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3326 u64 remote_addr, u32 rkey) 3327 { 3328 rseg->raddr = cpu_to_be64(remote_addr); 3329 rseg->rkey = cpu_to_be32(rkey); 3330 rseg->reserved = 0; 3331 } 3332 3333 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3334 const struct ib_atomic_wr *wr) 3335 { 3336 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3337 aseg->swap_add = cpu_to_be64(wr->swap); 3338 aseg->compare = cpu_to_be64(wr->compare_add); 3339 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3340 aseg->swap_add = cpu_to_be64(wr->compare_add); 3341 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3342 } else { 3343 aseg->swap_add = cpu_to_be64(wr->compare_add); 3344 aseg->compare = 0; 3345 } 3346 3347 } 3348 3349 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3350 const struct ib_atomic_wr *wr) 3351 { 3352 aseg->swap_add = cpu_to_be64(wr->swap); 3353 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3354 aseg->compare = cpu_to_be64(wr->compare_add); 3355 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3356 } 3357 3358 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3359 const struct ib_ud_wr *wr) 3360 { 3361 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3362 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3363 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3364 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3365 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3366 } 3367 3368 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3369 struct mlx4_wqe_datagram_seg *dseg, 3370 const struct ib_ud_wr *wr, 3371 enum mlx4_ib_qp_type qpt) 3372 { 3373 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3374 struct mlx4_av sqp_av = {0}; 3375 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3376 3377 /* force loopback */ 3378 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3379 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3380 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3381 cpu_to_be32(0xf0000000); 3382 3383 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3384 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3385 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3386 else 3387 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3388 /* Use QKEY from the QP context, which is set by master */ 3389 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3390 } 3391 3392 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3393 unsigned *mlx_seg_len) 3394 { 3395 struct mlx4_wqe_inline_seg *inl = wqe; 3396 struct mlx4_ib_tunnel_header hdr; 3397 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3398 int spc; 3399 int i; 3400 3401 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3402 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3403 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3404 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3405 memcpy(hdr.mac, ah->av.eth.mac, 6); 3406 hdr.vlan = ah->av.eth.vlan; 3407 3408 spc = MLX4_INLINE_ALIGN - 3409 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3410 if (sizeof (hdr) <= spc) { 3411 memcpy(inl + 1, &hdr, sizeof (hdr)); 3412 wmb(); 3413 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3414 i = 1; 3415 } else { 3416 memcpy(inl + 1, &hdr, spc); 3417 wmb(); 3418 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3419 3420 inl = (void *) (inl + 1) + spc; 3421 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3422 wmb(); 3423 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3424 i = 2; 3425 } 3426 3427 *mlx_seg_len = 3428 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3429 } 3430 3431 static void set_mlx_icrc_seg(void *dseg) 3432 { 3433 u32 *t = dseg; 3434 struct mlx4_wqe_inline_seg *iseg = dseg; 3435 3436 t[1] = 0; 3437 3438 /* 3439 * Need a barrier here before writing the byte_count field to 3440 * make sure that all the data is visible before the 3441 * byte_count field is set. Otherwise, if the segment begins 3442 * a new cacheline, the HCA prefetcher could grab the 64-byte 3443 * chunk and get a valid (!= * 0xffffffff) byte count but 3444 * stale data, and end up sending the wrong data. 3445 */ 3446 wmb(); 3447 3448 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3449 } 3450 3451 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3452 { 3453 dseg->lkey = cpu_to_be32(sg->lkey); 3454 dseg->addr = cpu_to_be64(sg->addr); 3455 3456 /* 3457 * Need a barrier here before writing the byte_count field to 3458 * make sure that all the data is visible before the 3459 * byte_count field is set. Otherwise, if the segment begins 3460 * a new cacheline, the HCA prefetcher could grab the 64-byte 3461 * chunk and get a valid (!= * 0xffffffff) byte count but 3462 * stale data, and end up sending the wrong data. 3463 */ 3464 wmb(); 3465 3466 dseg->byte_count = cpu_to_be32(sg->length); 3467 } 3468 3469 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3470 { 3471 dseg->byte_count = cpu_to_be32(sg->length); 3472 dseg->lkey = cpu_to_be32(sg->lkey); 3473 dseg->addr = cpu_to_be64(sg->addr); 3474 } 3475 3476 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3477 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3478 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3479 { 3480 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3481 3482 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3483 *blh = cpu_to_be32(1 << 6); 3484 3485 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3486 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3487 return -EINVAL; 3488 3489 memcpy(wqe->header, wr->header, wr->hlen); 3490 3491 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3492 *lso_seg_len = halign; 3493 return 0; 3494 } 3495 3496 static __be32 send_ieth(const struct ib_send_wr *wr) 3497 { 3498 switch (wr->opcode) { 3499 case IB_WR_SEND_WITH_IMM: 3500 case IB_WR_RDMA_WRITE_WITH_IMM: 3501 return wr->ex.imm_data; 3502 3503 case IB_WR_SEND_WITH_INV: 3504 return cpu_to_be32(wr->ex.invalidate_rkey); 3505 3506 default: 3507 return 0; 3508 } 3509 } 3510 3511 static void add_zero_len_inline(void *wqe) 3512 { 3513 struct mlx4_wqe_inline_seg *inl = wqe; 3514 memset(wqe, 0, 16); 3515 inl->byte_count = cpu_to_be32(1 << 31); 3516 } 3517 3518 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3519 const struct ib_send_wr **bad_wr, bool drain) 3520 { 3521 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3522 void *wqe; 3523 struct mlx4_wqe_ctrl_seg *ctrl; 3524 struct mlx4_wqe_data_seg *dseg; 3525 unsigned long flags; 3526 int nreq; 3527 int err = 0; 3528 unsigned ind; 3529 int size; 3530 unsigned seglen; 3531 __be32 dummy; 3532 __be32 *lso_wqe; 3533 __be32 lso_hdr_sz; 3534 __be32 blh; 3535 int i; 3536 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3537 3538 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3539 struct mlx4_ib_sqp *sqp = qp->sqp; 3540 3541 if (sqp->roce_v2_gsi) { 3542 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3543 enum ib_gid_type gid_type; 3544 union ib_gid gid; 3545 3546 if (!fill_gid_by_hw_index(mdev, qp->port, 3547 ah->av.ib.gid_index, 3548 &gid, &gid_type)) 3549 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3550 to_mqp(sqp->roce_v2_gsi) : qp; 3551 else 3552 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3553 ah->av.ib.gid_index); 3554 } 3555 } 3556 3557 spin_lock_irqsave(&qp->sq.lock, flags); 3558 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3559 !drain) { 3560 err = -EIO; 3561 *bad_wr = wr; 3562 nreq = 0; 3563 goto out; 3564 } 3565 3566 ind = qp->sq_next_wqe; 3567 3568 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3569 lso_wqe = &dummy; 3570 blh = 0; 3571 3572 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3573 err = -ENOMEM; 3574 *bad_wr = wr; 3575 goto out; 3576 } 3577 3578 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3579 err = -EINVAL; 3580 *bad_wr = wr; 3581 goto out; 3582 } 3583 3584 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3585 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3586 3587 ctrl->srcrb_flags = 3588 (wr->send_flags & IB_SEND_SIGNALED ? 3589 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3590 (wr->send_flags & IB_SEND_SOLICITED ? 3591 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3592 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3593 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3594 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3595 qp->sq_signal_bits; 3596 3597 ctrl->imm = send_ieth(wr); 3598 3599 wqe += sizeof *ctrl; 3600 size = sizeof *ctrl / 16; 3601 3602 switch (qp->mlx4_ib_qp_type) { 3603 case MLX4_IB_QPT_RC: 3604 case MLX4_IB_QPT_UC: 3605 switch (wr->opcode) { 3606 case IB_WR_ATOMIC_CMP_AND_SWP: 3607 case IB_WR_ATOMIC_FETCH_AND_ADD: 3608 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3609 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3610 atomic_wr(wr)->rkey); 3611 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3612 3613 set_atomic_seg(wqe, atomic_wr(wr)); 3614 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3615 3616 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3617 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3618 3619 break; 3620 3621 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3622 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3623 atomic_wr(wr)->rkey); 3624 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3625 3626 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3627 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3628 3629 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3630 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3631 3632 break; 3633 3634 case IB_WR_RDMA_READ: 3635 case IB_WR_RDMA_WRITE: 3636 case IB_WR_RDMA_WRITE_WITH_IMM: 3637 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3638 rdma_wr(wr)->rkey); 3639 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3640 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3641 break; 3642 3643 case IB_WR_LOCAL_INV: 3644 ctrl->srcrb_flags |= 3645 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3646 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3647 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3648 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3649 break; 3650 3651 case IB_WR_REG_MR: 3652 ctrl->srcrb_flags |= 3653 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3654 set_reg_seg(wqe, reg_wr(wr)); 3655 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3656 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3657 break; 3658 3659 default: 3660 /* No extra segments required for sends */ 3661 break; 3662 } 3663 break; 3664 3665 case MLX4_IB_QPT_TUN_SMI_OWNER: 3666 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3667 &seglen); 3668 if (unlikely(err)) { 3669 *bad_wr = wr; 3670 goto out; 3671 } 3672 wqe += seglen; 3673 size += seglen / 16; 3674 break; 3675 case MLX4_IB_QPT_TUN_SMI: 3676 case MLX4_IB_QPT_TUN_GSI: 3677 /* this is a UD qp used in MAD responses to slaves. */ 3678 set_datagram_seg(wqe, ud_wr(wr)); 3679 /* set the forced-loopback bit in the data seg av */ 3680 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3681 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3682 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3683 break; 3684 case MLX4_IB_QPT_UD: 3685 set_datagram_seg(wqe, ud_wr(wr)); 3686 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3687 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3688 3689 if (wr->opcode == IB_WR_LSO) { 3690 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3691 &lso_hdr_sz, &blh); 3692 if (unlikely(err)) { 3693 *bad_wr = wr; 3694 goto out; 3695 } 3696 lso_wqe = (__be32 *) wqe; 3697 wqe += seglen; 3698 size += seglen / 16; 3699 } 3700 break; 3701 3702 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3703 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3704 &seglen); 3705 if (unlikely(err)) { 3706 *bad_wr = wr; 3707 goto out; 3708 } 3709 wqe += seglen; 3710 size += seglen / 16; 3711 /* to start tunnel header on a cache-line boundary */ 3712 add_zero_len_inline(wqe); 3713 wqe += 16; 3714 size++; 3715 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3716 wqe += seglen; 3717 size += seglen / 16; 3718 break; 3719 case MLX4_IB_QPT_PROXY_SMI: 3720 case MLX4_IB_QPT_PROXY_GSI: 3721 /* If we are tunneling special qps, this is a UD qp. 3722 * In this case we first add a UD segment targeting 3723 * the tunnel qp, and then add a header with address 3724 * information */ 3725 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3726 ud_wr(wr), 3727 qp->mlx4_ib_qp_type); 3728 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3729 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3730 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3731 wqe += seglen; 3732 size += seglen / 16; 3733 break; 3734 3735 case MLX4_IB_QPT_SMI: 3736 case MLX4_IB_QPT_GSI: 3737 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen); 3738 if (unlikely(err)) { 3739 *bad_wr = wr; 3740 goto out; 3741 } 3742 wqe += seglen; 3743 size += seglen / 16; 3744 break; 3745 3746 default: 3747 break; 3748 } 3749 3750 /* 3751 * Write data segments in reverse order, so as to 3752 * overwrite cacheline stamp last within each 3753 * cacheline. This avoids issues with WQE 3754 * prefetching. 3755 */ 3756 3757 dseg = wqe; 3758 dseg += wr->num_sge - 1; 3759 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3760 3761 /* Add one more inline data segment for ICRC for MLX sends */ 3762 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3763 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3764 qp->mlx4_ib_qp_type & 3765 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3766 set_mlx_icrc_seg(dseg + 1); 3767 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3768 } 3769 3770 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3771 set_data_seg(dseg, wr->sg_list + i); 3772 3773 /* 3774 * Possibly overwrite stamping in cacheline with LSO 3775 * segment only after making sure all data segments 3776 * are written. 3777 */ 3778 wmb(); 3779 *lso_wqe = lso_hdr_sz; 3780 3781 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3782 MLX4_WQE_CTRL_FENCE : 0) | size; 3783 3784 /* 3785 * Make sure descriptor is fully written before 3786 * setting ownership bit (because HW can start 3787 * executing as soon as we do). 3788 */ 3789 wmb(); 3790 3791 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3792 *bad_wr = wr; 3793 err = -EINVAL; 3794 goto out; 3795 } 3796 3797 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3798 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3799 3800 /* 3801 * We can improve latency by not stamping the last 3802 * send queue WQE until after ringing the doorbell, so 3803 * only stamp here if there are still more WQEs to post. 3804 */ 3805 if (wr->next) 3806 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3807 ind++; 3808 } 3809 3810 out: 3811 if (likely(nreq)) { 3812 qp->sq.head += nreq; 3813 3814 /* 3815 * Make sure that descriptors are written before 3816 * doorbell record. 3817 */ 3818 wmb(); 3819 3820 writel_relaxed(qp->doorbell_qpn, 3821 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3822 3823 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3824 3825 qp->sq_next_wqe = ind; 3826 } 3827 3828 spin_unlock_irqrestore(&qp->sq.lock, flags); 3829 3830 return err; 3831 } 3832 3833 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3834 const struct ib_send_wr **bad_wr) 3835 { 3836 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3837 } 3838 3839 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3840 const struct ib_recv_wr **bad_wr, bool drain) 3841 { 3842 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3843 struct mlx4_wqe_data_seg *scat; 3844 unsigned long flags; 3845 int err = 0; 3846 int nreq; 3847 int ind; 3848 int max_gs; 3849 int i; 3850 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3851 3852 max_gs = qp->rq.max_gs; 3853 spin_lock_irqsave(&qp->rq.lock, flags); 3854 3855 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3856 !drain) { 3857 err = -EIO; 3858 *bad_wr = wr; 3859 nreq = 0; 3860 goto out; 3861 } 3862 3863 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3864 3865 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3866 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3867 err = -ENOMEM; 3868 *bad_wr = wr; 3869 goto out; 3870 } 3871 3872 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3873 err = -EINVAL; 3874 *bad_wr = wr; 3875 goto out; 3876 } 3877 3878 scat = get_recv_wqe(qp, ind); 3879 3880 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3881 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3882 ib_dma_sync_single_for_device(ibqp->device, 3883 qp->sqp_proxy_rcv[ind].map, 3884 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3885 DMA_FROM_DEVICE); 3886 scat->byte_count = 3887 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3888 /* use dma lkey from upper layer entry */ 3889 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3890 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3891 scat++; 3892 max_gs--; 3893 } 3894 3895 for (i = 0; i < wr->num_sge; ++i) 3896 __set_data_seg(scat + i, wr->sg_list + i); 3897 3898 if (i < max_gs) { 3899 scat[i].byte_count = 0; 3900 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3901 scat[i].addr = 0; 3902 } 3903 3904 qp->rq.wrid[ind] = wr->wr_id; 3905 3906 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3907 } 3908 3909 out: 3910 if (likely(nreq)) { 3911 qp->rq.head += nreq; 3912 3913 /* 3914 * Make sure that descriptors are written before 3915 * doorbell record. 3916 */ 3917 wmb(); 3918 3919 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3920 } 3921 3922 spin_unlock_irqrestore(&qp->rq.lock, flags); 3923 3924 return err; 3925 } 3926 3927 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3928 const struct ib_recv_wr **bad_wr) 3929 { 3930 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3931 } 3932 3933 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3934 { 3935 switch (mlx4_state) { 3936 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3937 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3938 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3939 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3940 case MLX4_QP_STATE_SQ_DRAINING: 3941 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3942 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3943 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3944 default: return -1; 3945 } 3946 } 3947 3948 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3949 { 3950 switch (mlx4_mig_state) { 3951 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3952 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3953 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3954 default: return -1; 3955 } 3956 } 3957 3958 static int to_ib_qp_access_flags(int mlx4_flags) 3959 { 3960 int ib_flags = 0; 3961 3962 if (mlx4_flags & MLX4_QP_BIT_RRE) 3963 ib_flags |= IB_ACCESS_REMOTE_READ; 3964 if (mlx4_flags & MLX4_QP_BIT_RWE) 3965 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3966 if (mlx4_flags & MLX4_QP_BIT_RAE) 3967 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3968 3969 return ib_flags; 3970 } 3971 3972 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3973 struct rdma_ah_attr *ah_attr, 3974 struct mlx4_qp_path *path) 3975 { 3976 struct mlx4_dev *dev = ibdev->dev; 3977 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3978 3979 memset(ah_attr, 0, sizeof(*ah_attr)); 3980 if (port_num == 0 || port_num > dev->caps.num_ports) 3981 return; 3982 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3983 3984 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3985 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3986 ((path->sched_queue & 4) << 1)); 3987 else 3988 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3989 rdma_ah_set_port_num(ah_attr, port_num); 3990 3991 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3992 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3993 rdma_ah_set_static_rate(ah_attr, 3994 path->static_rate ? path->static_rate - 5 : 0); 3995 if (path->grh_mylmc & (1 << 7)) { 3996 rdma_ah_set_grh(ah_attr, NULL, 3997 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3998 path->mgid_index, 3999 path->hop_limit, 4000 (be32_to_cpu(path->tclass_flowlabel) 4001 >> 20) & 0xff); 4002 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4003 } 4004 } 4005 4006 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 4007 struct ib_qp_init_attr *qp_init_attr) 4008 { 4009 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 4010 struct mlx4_ib_qp *qp = to_mqp(ibqp); 4011 struct mlx4_qp_context context; 4012 int mlx4_state; 4013 int err = 0; 4014 4015 if (ibqp->rwq_ind_tbl) 4016 return -EOPNOTSUPP; 4017 4018 mutex_lock(&qp->mutex); 4019 4020 if (qp->state == IB_QPS_RESET) { 4021 qp_attr->qp_state = IB_QPS_RESET; 4022 goto done; 4023 } 4024 4025 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 4026 if (err) { 4027 err = -EINVAL; 4028 goto out; 4029 } 4030 4031 mlx4_state = be32_to_cpu(context.flags) >> 28; 4032 4033 qp->state = to_ib_qp_state(mlx4_state); 4034 qp_attr->qp_state = qp->state; 4035 qp_attr->path_mtu = context.mtu_msgmax >> 5; 4036 qp_attr->path_mig_state = 4037 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 4038 qp_attr->qkey = be32_to_cpu(context.qkey); 4039 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 4040 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 4041 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 4042 qp_attr->qp_access_flags = 4043 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 4044 4045 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4046 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4047 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4048 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 4049 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 4050 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 4051 qp_attr->alt_port_num = 4052 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4053 } 4054 4055 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 4056 if (qp_attr->qp_state == IB_QPS_INIT) 4057 qp_attr->port_num = qp->port; 4058 else 4059 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 4060 4061 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4062 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 4063 4064 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 4065 4066 qp_attr->max_dest_rd_atomic = 4067 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4068 qp_attr->min_rnr_timer = 4069 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4070 qp_attr->timeout = context.pri_path.ackto >> 3; 4071 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4072 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4073 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4074 4075 done: 4076 qp_attr->cur_qp_state = qp_attr->qp_state; 4077 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4078 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4079 4080 if (!ibqp->uobject) { 4081 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4082 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4083 } else { 4084 qp_attr->cap.max_send_wr = 0; 4085 qp_attr->cap.max_send_sge = 0; 4086 } 4087 4088 /* 4089 * We don't support inline sends for kernel QPs (yet), and we 4090 * don't know what userspace's value should be. 4091 */ 4092 qp_attr->cap.max_inline_data = 0; 4093 4094 qp_init_attr->cap = qp_attr->cap; 4095 4096 qp_init_attr->create_flags = 0; 4097 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4098 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4099 4100 if (qp->flags & MLX4_IB_QP_LSO) 4101 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4102 4103 if (qp->flags & MLX4_IB_QP_NETIF) 4104 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4105 4106 qp_init_attr->sq_sig_type = 4107 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4108 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4109 4110 out: 4111 mutex_unlock(&qp->mutex); 4112 return err; 4113 } 4114 4115 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4116 struct ib_wq_init_attr *init_attr, 4117 struct ib_udata *udata) 4118 { 4119 struct mlx4_dev *dev = to_mdev(pd->device)->dev; 4120 struct ib_qp_init_attr ib_qp_init_attr = {}; 4121 struct mlx4_ib_qp *qp; 4122 struct mlx4_ib_create_wq ucmd; 4123 int err, required_cmd_sz; 4124 4125 if (!udata) 4126 return ERR_PTR(-EINVAL); 4127 4128 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4129 sizeof(ucmd.comp_mask); 4130 if (udata->inlen < required_cmd_sz) { 4131 pr_debug("invalid inlen\n"); 4132 return ERR_PTR(-EINVAL); 4133 } 4134 4135 if (udata->inlen > sizeof(ucmd) && 4136 !ib_is_udata_cleared(udata, sizeof(ucmd), 4137 udata->inlen - sizeof(ucmd))) { 4138 pr_debug("inlen is not supported\n"); 4139 return ERR_PTR(-EOPNOTSUPP); 4140 } 4141 4142 if (udata->outlen) 4143 return ERR_PTR(-EOPNOTSUPP); 4144 4145 if (init_attr->wq_type != IB_WQT_RQ) { 4146 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4147 return ERR_PTR(-EOPNOTSUPP); 4148 } 4149 4150 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS || 4151 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 4152 pr_debug("unsupported create_flags %u\n", 4153 init_attr->create_flags); 4154 return ERR_PTR(-EOPNOTSUPP); 4155 } 4156 4157 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4158 if (!qp) 4159 return ERR_PTR(-ENOMEM); 4160 4161 mutex_init(&qp->mutex); 4162 qp->pri.vid = 0xFFFF; 4163 qp->alt.vid = 0xFFFF; 4164 4165 ib_qp_init_attr.qp_context = init_attr->wq_context; 4166 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4167 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4168 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4169 ib_qp_init_attr.recv_cq = init_attr->cq; 4170 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4171 4172 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4173 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4174 4175 err = create_rq(pd, &ib_qp_init_attr, udata, qp); 4176 if (err) { 4177 kfree(qp); 4178 return ERR_PTR(err); 4179 } 4180 4181 qp->ibwq.event_handler = init_attr->event_handler; 4182 qp->ibwq.wq_num = qp->mqp.qpn; 4183 qp->ibwq.state = IB_WQS_RESET; 4184 4185 return &qp->ibwq; 4186 } 4187 4188 static int ib_wq2qp_state(enum ib_wq_state state) 4189 { 4190 switch (state) { 4191 case IB_WQS_RESET: 4192 return IB_QPS_RESET; 4193 case IB_WQS_RDY: 4194 return IB_QPS_RTR; 4195 default: 4196 return IB_QPS_ERR; 4197 } 4198 } 4199 4200 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 4201 struct ib_udata *udata) 4202 { 4203 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4204 enum ib_qp_state qp_cur_state; 4205 enum ib_qp_state qp_new_state; 4206 int attr_mask; 4207 int err; 4208 4209 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4210 * the WQ logic state. 4211 */ 4212 qp_cur_state = qp->state; 4213 qp_new_state = ib_wq2qp_state(new_state); 4214 4215 if (ib_wq2qp_state(new_state) == qp_cur_state) 4216 return 0; 4217 4218 if (new_state == IB_WQS_RDY) { 4219 struct ib_qp_attr attr = {}; 4220 4221 attr.port_num = qp->port; 4222 attr_mask = IB_QP_PORT; 4223 4224 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4225 attr_mask, IB_QPS_RESET, IB_QPS_INIT, 4226 udata); 4227 if (err) { 4228 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4229 ibwq->wq_num); 4230 return err; 4231 } 4232 4233 qp_cur_state = IB_QPS_INIT; 4234 } 4235 4236 attr_mask = 0; 4237 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4238 qp_cur_state, qp_new_state, udata); 4239 4240 if (err && (qp_cur_state == IB_QPS_INIT)) { 4241 qp_new_state = IB_QPS_RESET; 4242 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4243 attr_mask, IB_QPS_INIT, IB_QPS_RESET, 4244 udata)) { 4245 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4246 ibwq->wq_num); 4247 qp_new_state = IB_QPS_INIT; 4248 } 4249 } 4250 4251 qp->state = qp_new_state; 4252 4253 return err; 4254 } 4255 4256 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4257 u32 wq_attr_mask, struct ib_udata *udata) 4258 { 4259 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4260 struct mlx4_ib_modify_wq ucmd = {}; 4261 size_t required_cmd_sz; 4262 enum ib_wq_state cur_state, new_state; 4263 int err = 0; 4264 4265 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4266 sizeof(ucmd.reserved); 4267 if (udata->inlen < required_cmd_sz) 4268 return -EINVAL; 4269 4270 if (udata->inlen > sizeof(ucmd) && 4271 !ib_is_udata_cleared(udata, sizeof(ucmd), 4272 udata->inlen - sizeof(ucmd))) 4273 return -EOPNOTSUPP; 4274 4275 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4276 return -EFAULT; 4277 4278 if (ucmd.comp_mask || ucmd.reserved) 4279 return -EOPNOTSUPP; 4280 4281 if (wq_attr_mask & IB_WQ_FLAGS) 4282 return -EOPNOTSUPP; 4283 4284 cur_state = wq_attr->curr_wq_state; 4285 new_state = wq_attr->wq_state; 4286 4287 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4288 return -EINVAL; 4289 4290 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4291 return -EINVAL; 4292 4293 /* Need to protect against the parent RSS which also may modify WQ 4294 * state. 4295 */ 4296 mutex_lock(&qp->mutex); 4297 4298 /* Can update HW state only if a RSS QP has already associated to this 4299 * WQ, so we can apply its port on the WQ. 4300 */ 4301 if (qp->rss_usecnt) 4302 err = _mlx4_ib_modify_wq(ibwq, new_state, udata); 4303 4304 if (!err) 4305 ibwq->state = new_state; 4306 4307 mutex_unlock(&qp->mutex); 4308 4309 return err; 4310 } 4311 4312 int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata) 4313 { 4314 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4315 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4316 4317 if (qp->counter_index) 4318 mlx4_ib_free_qp_counter(dev, qp); 4319 4320 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata); 4321 4322 kfree(qp); 4323 return 0; 4324 } 4325 4326 int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table, 4327 struct ib_rwq_ind_table_init_attr *init_attr, 4328 struct ib_udata *udata) 4329 { 4330 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4331 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4332 struct ib_device *device = rwq_ind_table->device; 4333 unsigned int base_wqn; 4334 size_t min_resp_len; 4335 int i, err = 0; 4336 4337 if (udata->inlen > 0 && 4338 !ib_is_udata_cleared(udata, 0, 4339 udata->inlen)) 4340 return -EOPNOTSUPP; 4341 4342 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4343 if (udata->outlen && udata->outlen < min_resp_len) 4344 return -EINVAL; 4345 4346 if (ind_tbl_size > 4347 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4348 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4349 ind_tbl_size, 4350 device->attrs.rss_caps.max_rwq_indirection_table_size); 4351 return -EINVAL; 4352 } 4353 4354 base_wqn = init_attr->ind_tbl[0]->wq_num; 4355 4356 if (base_wqn % ind_tbl_size) { 4357 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4358 base_wqn); 4359 return -EINVAL; 4360 } 4361 4362 for (i = 1; i < ind_tbl_size; i++) { 4363 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4364 pr_debug("indirection table's WQNs aren't consecutive\n"); 4365 return -EINVAL; 4366 } 4367 } 4368 4369 if (udata->outlen) { 4370 resp.response_length = offsetof(typeof(resp), response_length) + 4371 sizeof(resp.response_length); 4372 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4373 } 4374 4375 return err; 4376 } 4377 4378 struct mlx4_ib_drain_cqe { 4379 struct ib_cqe cqe; 4380 struct completion done; 4381 }; 4382 4383 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4384 { 4385 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4386 struct mlx4_ib_drain_cqe, 4387 cqe); 4388 4389 complete(&cqe->done); 4390 } 4391 4392 /* This function returns only once the drained WR was completed */ 4393 static void handle_drain_completion(struct ib_cq *cq, 4394 struct mlx4_ib_drain_cqe *sdrain, 4395 struct mlx4_ib_dev *dev) 4396 { 4397 struct mlx4_dev *mdev = dev->dev; 4398 4399 if (cq->poll_ctx == IB_POLL_DIRECT) { 4400 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4401 ib_process_cq_direct(cq, -1); 4402 return; 4403 } 4404 4405 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4406 struct mlx4_ib_cq *mcq = to_mcq(cq); 4407 bool triggered = false; 4408 unsigned long flags; 4409 4410 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4411 /* Make sure that the CQ handler won't run if wasn't run yet */ 4412 if (!mcq->mcq.reset_notify_added) 4413 mcq->mcq.reset_notify_added = 1; 4414 else 4415 triggered = true; 4416 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4417 4418 if (triggered) { 4419 /* Wait for any scheduled/running task to be ended */ 4420 switch (cq->poll_ctx) { 4421 case IB_POLL_SOFTIRQ: 4422 irq_poll_disable(&cq->iop); 4423 irq_poll_enable(&cq->iop); 4424 break; 4425 case IB_POLL_WORKQUEUE: 4426 cancel_work_sync(&cq->work); 4427 break; 4428 default: 4429 WARN_ON_ONCE(1); 4430 } 4431 } 4432 4433 /* Run the CQ handler - this makes sure that the drain WR will 4434 * be processed if wasn't processed yet. 4435 */ 4436 mcq->mcq.comp(&mcq->mcq); 4437 } 4438 4439 wait_for_completion(&sdrain->done); 4440 } 4441 4442 void mlx4_ib_drain_sq(struct ib_qp *qp) 4443 { 4444 struct ib_cq *cq = qp->send_cq; 4445 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4446 struct mlx4_ib_drain_cqe sdrain; 4447 const struct ib_send_wr *bad_swr; 4448 struct ib_rdma_wr swr = { 4449 .wr = { 4450 .next = NULL, 4451 { .wr_cqe = &sdrain.cqe, }, 4452 .opcode = IB_WR_RDMA_WRITE, 4453 }, 4454 }; 4455 int ret; 4456 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4457 struct mlx4_dev *mdev = dev->dev; 4458 4459 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4460 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4461 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4462 return; 4463 } 4464 4465 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4466 init_completion(&sdrain.done); 4467 4468 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4469 if (ret) { 4470 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4471 return; 4472 } 4473 4474 handle_drain_completion(cq, &sdrain, dev); 4475 } 4476 4477 void mlx4_ib_drain_rq(struct ib_qp *qp) 4478 { 4479 struct ib_cq *cq = qp->recv_cq; 4480 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4481 struct mlx4_ib_drain_cqe rdrain; 4482 struct ib_recv_wr rwr = {}; 4483 const struct ib_recv_wr *bad_rwr; 4484 int ret; 4485 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4486 struct mlx4_dev *mdev = dev->dev; 4487 4488 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4489 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4490 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4491 return; 4492 } 4493 4494 rwr.wr_cqe = &rdrain.cqe; 4495 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4496 init_completion(&rdrain.done); 4497 4498 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4499 if (ret) { 4500 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4501 return; 4502 } 4503 4504 handle_drain_completion(cq, &rdrain, dev); 4505 } 4506 4507 int mlx4_ib_qp_event_init(void) 4508 { 4509 mlx4_ib_qp_event_wq = alloc_ordered_workqueue("mlx4_ib_qp_event_wq", 0); 4510 if (!mlx4_ib_qp_event_wq) 4511 return -ENOMEM; 4512 4513 return 0; 4514 } 4515 4516 void mlx4_ib_qp_event_cleanup(void) 4517 { 4518 destroy_workqueue(mlx4_ib_qp_event_wq); 4519 } 4520