1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include <rdma/mlx4-abi.h> 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 57 struct ib_udata *udata); 58 59 enum { 60 MLX4_IB_ACK_REQ_FREQ = 8, 61 }; 62 63 enum { 64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 66 MLX4_IB_LINK_TYPE_IB = 0, 67 MLX4_IB_LINK_TYPE_ETH = 1 68 }; 69 70 enum { 71 /* 72 * Largest possible UD header: send with GRH and immediate 73 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 74 * tag. (LRH would only use 8 bytes, so Ethernet is the 75 * biggest case) 76 */ 77 MLX4_IB_UD_HEADER_SIZE = 82, 78 MLX4_IB_LSO_HEADER_SPARE = 128, 79 }; 80 81 struct mlx4_ib_sqp { 82 struct mlx4_ib_qp qp; 83 int pkey_index; 84 u32 qkey; 85 u32 send_psn; 86 struct ib_ud_header ud_header; 87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 88 struct ib_qp *roce_v2_gsi; 89 }; 90 91 enum { 92 MLX4_IB_MIN_SQ_STRIDE = 6, 93 MLX4_IB_CACHE_LINE_SIZE = 64, 94 }; 95 96 enum { 97 MLX4_RAW_QP_MTU = 7, 98 MLX4_RAW_QP_MSGMAX = 31, 99 }; 100 101 #ifndef ETH_ALEN 102 #define ETH_ALEN 6 103 #endif 104 105 static const __be32 mlx4_ib_opcode[] = { 106 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 107 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 108 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 109 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 110 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 111 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 112 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 113 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 114 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 115 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 116 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 117 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 118 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 119 }; 120 121 enum mlx4_ib_source_type { 122 MLX4_IB_QP_SRC = 0, 123 MLX4_IB_RWQ_SRC = 1, 124 }; 125 126 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 127 { 128 return container_of(mqp, struct mlx4_ib_sqp, qp); 129 } 130 131 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 132 { 133 if (!mlx4_is_master(dev->dev)) 134 return 0; 135 136 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 137 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 138 8 * MLX4_MFUNC_MAX; 139 } 140 141 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 142 { 143 int proxy_sqp = 0; 144 int real_sqp = 0; 145 int i; 146 /* PPF or Native -- real SQP */ 147 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 148 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 149 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 150 if (real_sqp) 151 return 1; 152 /* VF or PF -- proxy SQP */ 153 if (mlx4_is_mfunc(dev->dev)) { 154 for (i = 0; i < dev->dev->caps.num_ports; i++) { 155 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 156 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 157 proxy_sqp = 1; 158 break; 159 } 160 } 161 } 162 if (proxy_sqp) 163 return 1; 164 165 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 166 } 167 168 /* used for INIT/CLOSE port logic */ 169 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 170 { 171 int proxy_qp0 = 0; 172 int real_qp0 = 0; 173 int i; 174 /* PPF or Native -- real QP0 */ 175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 178 if (real_qp0) 179 return 1; 180 /* VF or PF -- proxy QP0 */ 181 if (mlx4_is_mfunc(dev->dev)) { 182 for (i = 0; i < dev->dev->caps.num_ports; i++) { 183 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 184 proxy_qp0 = 1; 185 break; 186 } 187 } 188 } 189 return proxy_qp0; 190 } 191 192 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 193 { 194 return mlx4_buf_offset(&qp->buf, offset); 195 } 196 197 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 198 { 199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 200 } 201 202 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 203 { 204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 205 } 206 207 /* 208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 209 * first four bytes of every 64 byte chunk with 0xffffffff, except for 210 * the very first chunk of the WQE. 211 */ 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 213 { 214 __be32 *wqe; 215 int i; 216 int s; 217 void *buf; 218 struct mlx4_wqe_ctrl_seg *ctrl; 219 220 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 221 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 222 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 223 for (i = 64; i < s; i += 64) { 224 wqe = buf + i; 225 *wqe = cpu_to_be32(0xffffffff); 226 } 227 } 228 229 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 230 { 231 struct ib_event event; 232 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 233 234 if (type == MLX4_EVENT_TYPE_PATH_MIG) 235 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 236 237 if (ibqp->event_handler) { 238 event.device = ibqp->device; 239 event.element.qp = ibqp; 240 switch (type) { 241 case MLX4_EVENT_TYPE_PATH_MIG: 242 event.event = IB_EVENT_PATH_MIG; 243 break; 244 case MLX4_EVENT_TYPE_COMM_EST: 245 event.event = IB_EVENT_COMM_EST; 246 break; 247 case MLX4_EVENT_TYPE_SQ_DRAINED: 248 event.event = IB_EVENT_SQ_DRAINED; 249 break; 250 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 251 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 252 break; 253 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 254 event.event = IB_EVENT_QP_FATAL; 255 break; 256 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 257 event.event = IB_EVENT_PATH_MIG_ERR; 258 break; 259 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 260 event.event = IB_EVENT_QP_REQ_ERR; 261 break; 262 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 263 event.event = IB_EVENT_QP_ACCESS_ERR; 264 break; 265 default: 266 pr_warn("Unexpected event type %d " 267 "on QP %06x\n", type, qp->qpn); 268 return; 269 } 270 271 ibqp->event_handler(&event, ibqp->qp_context); 272 } 273 } 274 275 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 276 { 277 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 278 type, qp->qpn); 279 } 280 281 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 282 { 283 /* 284 * UD WQEs must have a datagram segment. 285 * RC and UC WQEs might have a remote address segment. 286 * MLX WQEs need two extra inline data segments (for the UD 287 * header and space for the ICRC). 288 */ 289 switch (type) { 290 case MLX4_IB_QPT_UD: 291 return sizeof (struct mlx4_wqe_ctrl_seg) + 292 sizeof (struct mlx4_wqe_datagram_seg) + 293 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 294 case MLX4_IB_QPT_PROXY_SMI_OWNER: 295 case MLX4_IB_QPT_PROXY_SMI: 296 case MLX4_IB_QPT_PROXY_GSI: 297 return sizeof (struct mlx4_wqe_ctrl_seg) + 298 sizeof (struct mlx4_wqe_datagram_seg) + 64; 299 case MLX4_IB_QPT_TUN_SMI_OWNER: 300 case MLX4_IB_QPT_TUN_GSI: 301 return sizeof (struct mlx4_wqe_ctrl_seg) + 302 sizeof (struct mlx4_wqe_datagram_seg); 303 304 case MLX4_IB_QPT_UC: 305 return sizeof (struct mlx4_wqe_ctrl_seg) + 306 sizeof (struct mlx4_wqe_raddr_seg); 307 case MLX4_IB_QPT_RC: 308 return sizeof (struct mlx4_wqe_ctrl_seg) + 309 sizeof (struct mlx4_wqe_masked_atomic_seg) + 310 sizeof (struct mlx4_wqe_raddr_seg); 311 case MLX4_IB_QPT_SMI: 312 case MLX4_IB_QPT_GSI: 313 return sizeof (struct mlx4_wqe_ctrl_seg) + 314 ALIGN(MLX4_IB_UD_HEADER_SIZE + 315 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 316 MLX4_INLINE_ALIGN) * 317 sizeof (struct mlx4_wqe_inline_seg), 318 sizeof (struct mlx4_wqe_data_seg)) + 319 ALIGN(4 + 320 sizeof (struct mlx4_wqe_inline_seg), 321 sizeof (struct mlx4_wqe_data_seg)); 322 default: 323 return sizeof (struct mlx4_wqe_ctrl_seg); 324 } 325 } 326 327 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 328 bool is_user, int has_rq, struct mlx4_ib_qp *qp, 329 u32 inl_recv_sz) 330 { 331 /* Sanity check RQ size before proceeding */ 332 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 333 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 334 return -EINVAL; 335 336 if (!has_rq) { 337 if (cap->max_recv_wr || inl_recv_sz) 338 return -EINVAL; 339 340 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 341 } else { 342 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 343 sizeof(struct mlx4_wqe_data_seg); 344 u32 wqe_size; 345 346 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 347 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 348 inl_recv_sz > max_inl_recv_sz)) 349 return -EINVAL; 350 351 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 352 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 353 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 354 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 355 } 356 357 /* leave userspace return values as they were, so as not to break ABI */ 358 if (is_user) { 359 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 360 cap->max_recv_sge = qp->rq.max_gs; 361 } else { 362 cap->max_recv_wr = qp->rq.max_post = 363 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 364 cap->max_recv_sge = min(qp->rq.max_gs, 365 min(dev->dev->caps.max_sq_sg, 366 dev->dev->caps.max_rq_sg)); 367 } 368 369 return 0; 370 } 371 372 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 373 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 374 { 375 int s; 376 377 /* Sanity check SQ size before proceeding */ 378 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 379 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 380 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 381 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 382 return -EINVAL; 383 384 /* 385 * For MLX transport we need 2 extra S/G entries: 386 * one for the header and one for the checksum at the end 387 */ 388 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 389 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 390 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 391 return -EINVAL; 392 393 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 394 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 395 send_wqe_overhead(type, qp->flags); 396 397 if (s > dev->dev->caps.max_sq_desc_sz) 398 return -EINVAL; 399 400 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 401 402 /* 403 * We need to leave 2 KB + 1 WR of headroom in the SQ to 404 * allow HW to prefetch. 405 */ 406 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 407 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 408 qp->sq_spare_wqes); 409 410 qp->sq.max_gs = 411 (min(dev->dev->caps.max_sq_desc_sz, 412 (1 << qp->sq.wqe_shift)) - 413 send_wqe_overhead(type, qp->flags)) / 414 sizeof (struct mlx4_wqe_data_seg); 415 416 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 417 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 418 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 419 qp->rq.offset = 0; 420 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 421 } else { 422 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 423 qp->sq.offset = 0; 424 } 425 426 cap->max_send_wr = qp->sq.max_post = 427 qp->sq.wqe_cnt - qp->sq_spare_wqes; 428 cap->max_send_sge = min(qp->sq.max_gs, 429 min(dev->dev->caps.max_sq_sg, 430 dev->dev->caps.max_rq_sg)); 431 /* We don't support inline sends for kernel QPs (yet) */ 432 cap->max_inline_data = 0; 433 434 return 0; 435 } 436 437 static int set_user_sq_size(struct mlx4_ib_dev *dev, 438 struct mlx4_ib_qp *qp, 439 struct mlx4_ib_create_qp *ucmd) 440 { 441 /* Sanity check SQ size before proceeding */ 442 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 443 ucmd->log_sq_stride > 444 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 445 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 446 return -EINVAL; 447 448 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 449 qp->sq.wqe_shift = ucmd->log_sq_stride; 450 451 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 452 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 453 454 return 0; 455 } 456 457 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 458 { 459 int i; 460 461 qp->sqp_proxy_rcv = 462 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf), 463 GFP_KERNEL); 464 if (!qp->sqp_proxy_rcv) 465 return -ENOMEM; 466 for (i = 0; i < qp->rq.wqe_cnt; i++) { 467 qp->sqp_proxy_rcv[i].addr = 468 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 469 GFP_KERNEL); 470 if (!qp->sqp_proxy_rcv[i].addr) 471 goto err; 472 qp->sqp_proxy_rcv[i].map = 473 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 474 sizeof (struct mlx4_ib_proxy_sqp_hdr), 475 DMA_FROM_DEVICE); 476 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 477 kfree(qp->sqp_proxy_rcv[i].addr); 478 goto err; 479 } 480 } 481 return 0; 482 483 err: 484 while (i > 0) { 485 --i; 486 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 487 sizeof (struct mlx4_ib_proxy_sqp_hdr), 488 DMA_FROM_DEVICE); 489 kfree(qp->sqp_proxy_rcv[i].addr); 490 } 491 kfree(qp->sqp_proxy_rcv); 492 qp->sqp_proxy_rcv = NULL; 493 return -ENOMEM; 494 } 495 496 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 497 { 498 int i; 499 500 for (i = 0; i < qp->rq.wqe_cnt; i++) { 501 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 502 sizeof (struct mlx4_ib_proxy_sqp_hdr), 503 DMA_FROM_DEVICE); 504 kfree(qp->sqp_proxy_rcv[i].addr); 505 } 506 kfree(qp->sqp_proxy_rcv); 507 } 508 509 static int qp_has_rq(struct ib_qp_init_attr *attr) 510 { 511 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 512 return 0; 513 514 return !attr->srq; 515 } 516 517 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 518 { 519 int i; 520 for (i = 0; i < dev->caps.num_ports; i++) { 521 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 522 return !!dev->caps.spec_qps[i].qp0_qkey; 523 } 524 return 0; 525 } 526 527 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 528 struct mlx4_ib_qp *qp) 529 { 530 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 531 mlx4_counter_free(dev->dev, qp->counter_index->index); 532 list_del(&qp->counter_index->list); 533 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 534 535 kfree(qp->counter_index); 536 qp->counter_index = NULL; 537 } 538 539 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 540 struct ib_qp_init_attr *init_attr, 541 struct mlx4_ib_create_qp_rss *ucmd) 542 { 543 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 544 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 545 546 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 547 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 548 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 549 MLX4_EN_RSS_KEY_SIZE); 550 } else { 551 pr_debug("RX Hash function is not supported\n"); 552 return (-EOPNOTSUPP); 553 } 554 555 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | 556 MLX4_IB_RX_HASH_DST_IPV4 | 557 MLX4_IB_RX_HASH_SRC_IPV6 | 558 MLX4_IB_RX_HASH_DST_IPV6 | 559 MLX4_IB_RX_HASH_SRC_PORT_TCP | 560 MLX4_IB_RX_HASH_DST_PORT_TCP | 561 MLX4_IB_RX_HASH_SRC_PORT_UDP | 562 MLX4_IB_RX_HASH_DST_PORT_UDP | 563 MLX4_IB_RX_HASH_INNER)) { 564 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 565 ucmd->rx_hash_fields_mask); 566 return (-EOPNOTSUPP); 567 } 568 569 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 570 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 571 rss_ctx->flags = MLX4_RSS_IPV4; 572 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 573 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 574 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 575 return (-EOPNOTSUPP); 576 } 577 578 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 579 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 580 rss_ctx->flags |= MLX4_RSS_IPV6; 581 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 582 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 583 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 584 return (-EOPNOTSUPP); 585 } 586 587 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 588 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 589 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 590 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 591 return (-EOPNOTSUPP); 592 } 593 594 if (rss_ctx->flags & MLX4_RSS_IPV4) 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 596 if (rss_ctx->flags & MLX4_RSS_IPV6) 597 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 598 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 599 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 600 return (-EOPNOTSUPP); 601 } 602 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 603 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 604 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 605 return (-EOPNOTSUPP); 606 } 607 608 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 609 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 610 if (rss_ctx->flags & MLX4_RSS_IPV4) 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 612 if (rss_ctx->flags & MLX4_RSS_IPV6) 613 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 614 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 615 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 616 return (-EOPNOTSUPP); 617 } 618 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 619 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 620 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 621 return (-EOPNOTSUPP); 622 } 623 624 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 625 if (dev->dev->caps.tunnel_offload_mode == 626 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 627 /* 628 * Hash according to inner headers if exist, otherwise 629 * according to outer headers. 630 */ 631 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 632 } else { 633 pr_debug("RSS Hash for inner headers isn't supported\n"); 634 return (-EOPNOTSUPP); 635 } 636 } 637 638 return 0; 639 } 640 641 static int create_qp_rss(struct mlx4_ib_dev *dev, 642 struct ib_qp_init_attr *init_attr, 643 struct mlx4_ib_create_qp_rss *ucmd, 644 struct mlx4_ib_qp *qp) 645 { 646 int qpn; 647 int err; 648 649 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 650 651 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 652 if (err) 653 return err; 654 655 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 656 if (err) 657 goto err_qpn; 658 659 mutex_init(&qp->mutex); 660 661 INIT_LIST_HEAD(&qp->gid_list); 662 INIT_LIST_HEAD(&qp->steering_rules); 663 664 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 665 qp->state = IB_QPS_RESET; 666 667 /* Set dummy send resources to be compatible with HV and PRM */ 668 qp->sq_no_prefetch = 1; 669 qp->sq.wqe_cnt = 1; 670 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 671 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 672 qp->mtt = (to_mqp( 673 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 674 675 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 676 if (!qp->rss_ctx) { 677 err = -ENOMEM; 678 goto err_qp_alloc; 679 } 680 681 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 682 if (err) 683 goto err; 684 685 return 0; 686 687 err: 688 kfree(qp->rss_ctx); 689 690 err_qp_alloc: 691 mlx4_qp_remove(dev->dev, &qp->mqp); 692 mlx4_qp_free(dev->dev, &qp->mqp); 693 694 err_qpn: 695 mlx4_qp_release_range(dev->dev, qpn, 1); 696 return err; 697 } 698 699 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd, 700 struct ib_qp_init_attr *init_attr, 701 struct ib_udata *udata) 702 { 703 struct mlx4_ib_qp *qp; 704 struct mlx4_ib_create_qp_rss ucmd = {}; 705 size_t required_cmd_sz; 706 int err; 707 708 if (!udata) { 709 pr_debug("RSS QP with NULL udata\n"); 710 return ERR_PTR(-EINVAL); 711 } 712 713 if (udata->outlen) 714 return ERR_PTR(-EOPNOTSUPP); 715 716 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 717 sizeof(ucmd.reserved1); 718 if (udata->inlen < required_cmd_sz) { 719 pr_debug("invalid inlen\n"); 720 return ERR_PTR(-EINVAL); 721 } 722 723 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 724 pr_debug("copy failed\n"); 725 return ERR_PTR(-EFAULT); 726 } 727 728 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 729 return ERR_PTR(-EOPNOTSUPP); 730 731 if (ucmd.comp_mask || ucmd.reserved1) 732 return ERR_PTR(-EOPNOTSUPP); 733 734 if (udata->inlen > sizeof(ucmd) && 735 !ib_is_udata_cleared(udata, sizeof(ucmd), 736 udata->inlen - sizeof(ucmd))) { 737 pr_debug("inlen is not supported\n"); 738 return ERR_PTR(-EOPNOTSUPP); 739 } 740 741 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 742 pr_debug("RSS QP with unsupported QP type %d\n", 743 init_attr->qp_type); 744 return ERR_PTR(-EOPNOTSUPP); 745 } 746 747 if (init_attr->create_flags) { 748 pr_debug("RSS QP doesn't support create flags\n"); 749 return ERR_PTR(-EOPNOTSUPP); 750 } 751 752 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 753 pr_debug("RSS QP with unsupported send attributes\n"); 754 return ERR_PTR(-EOPNOTSUPP); 755 } 756 757 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 758 if (!qp) 759 return ERR_PTR(-ENOMEM); 760 761 qp->pri.vid = 0xFFFF; 762 qp->alt.vid = 0xFFFF; 763 764 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 765 if (err) { 766 kfree(qp); 767 return ERR_PTR(err); 768 } 769 770 qp->ibqp.qp_num = qp->mqp.qpn; 771 772 return &qp->ibqp; 773 } 774 775 /* 776 * This function allocates a WQN from a range which is consecutive and aligned 777 * to its size. In case the range is full, then it creates a new range and 778 * allocates WQN from it. The new range will be used for following allocations. 779 */ 780 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 781 struct mlx4_ib_qp *qp, int range_size, int *wqn) 782 { 783 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 784 struct mlx4_wqn_range *range; 785 int err = 0; 786 787 mutex_lock(&context->wqn_ranges_mutex); 788 789 range = list_first_entry_or_null(&context->wqn_ranges_list, 790 struct mlx4_wqn_range, list); 791 792 if (!range || (range->refcount == range->size) || range->dirty) { 793 range = kzalloc(sizeof(*range), GFP_KERNEL); 794 if (!range) { 795 err = -ENOMEM; 796 goto out; 797 } 798 799 err = mlx4_qp_reserve_range(dev->dev, range_size, 800 range_size, &range->base_wqn, 0, 801 qp->mqp.usage); 802 if (err) { 803 kfree(range); 804 goto out; 805 } 806 807 range->size = range_size; 808 list_add(&range->list, &context->wqn_ranges_list); 809 } else if (range_size != 1) { 810 /* 811 * Requesting a new range (>1) when last range is still open, is 812 * not valid. 813 */ 814 err = -EINVAL; 815 goto out; 816 } 817 818 qp->wqn_range = range; 819 820 *wqn = range->base_wqn + range->refcount; 821 822 range->refcount++; 823 824 out: 825 mutex_unlock(&context->wqn_ranges_mutex); 826 827 return err; 828 } 829 830 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 831 struct mlx4_ib_qp *qp, bool dirty_release) 832 { 833 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 834 struct mlx4_wqn_range *range; 835 836 mutex_lock(&context->wqn_ranges_mutex); 837 838 range = qp->wqn_range; 839 840 range->refcount--; 841 if (!range->refcount) { 842 mlx4_qp_release_range(dev->dev, range->base_wqn, 843 range->size); 844 list_del(&range->list); 845 kfree(range); 846 } else if (dirty_release) { 847 /* 848 * A range which one of its WQNs is destroyed, won't be able to be 849 * reused for further WQN allocations. 850 * The next created WQ will allocate a new range. 851 */ 852 range->dirty = 1; 853 } 854 855 mutex_unlock(&context->wqn_ranges_mutex); 856 } 857 858 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 859 enum mlx4_ib_source_type src, 860 struct ib_qp_init_attr *init_attr, 861 struct ib_udata *udata, int sqpn, 862 struct mlx4_ib_qp **caller_qp) 863 { 864 int qpn; 865 int err; 866 struct mlx4_ib_sqp *sqp = NULL; 867 struct mlx4_ib_qp *qp; 868 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 869 udata, struct mlx4_ib_ucontext, ibucontext); 870 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 871 struct mlx4_ib_cq *mcq; 872 unsigned long flags; 873 int range_size = 0; 874 875 /* When tunneling special qps, we use a plain UD qp */ 876 if (sqpn) { 877 if (mlx4_is_mfunc(dev->dev) && 878 (!mlx4_is_master(dev->dev) || 879 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 880 if (init_attr->qp_type == IB_QPT_GSI) 881 qp_type = MLX4_IB_QPT_PROXY_GSI; 882 else { 883 if (mlx4_is_master(dev->dev) || 884 qp0_enabled_vf(dev->dev, sqpn)) 885 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 886 else 887 qp_type = MLX4_IB_QPT_PROXY_SMI; 888 } 889 } 890 qpn = sqpn; 891 /* add extra sg entry for tunneling */ 892 init_attr->cap.max_recv_sge++; 893 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 894 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 895 container_of(init_attr, 896 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 897 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 898 tnl_init->proxy_qp_type != IB_QPT_GSI) || 899 !mlx4_is_master(dev->dev)) 900 return -EINVAL; 901 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 902 qp_type = MLX4_IB_QPT_TUN_GSI; 903 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 904 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 905 tnl_init->port)) 906 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 907 else 908 qp_type = MLX4_IB_QPT_TUN_SMI; 909 /* we are definitely in the PPF here, since we are creating 910 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 911 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 912 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 913 sqpn = qpn; 914 } 915 916 if (!*caller_qp) { 917 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 918 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 919 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 920 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 921 if (!sqp) 922 return -ENOMEM; 923 qp = &sqp->qp; 924 qp->pri.vid = 0xFFFF; 925 qp->alt.vid = 0xFFFF; 926 } else { 927 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL); 928 if (!qp) 929 return -ENOMEM; 930 qp->pri.vid = 0xFFFF; 931 qp->alt.vid = 0xFFFF; 932 } 933 } else 934 qp = *caller_qp; 935 936 qp->mlx4_ib_qp_type = qp_type; 937 938 mutex_init(&qp->mutex); 939 spin_lock_init(&qp->sq.lock); 940 spin_lock_init(&qp->rq.lock); 941 INIT_LIST_HEAD(&qp->gid_list); 942 INIT_LIST_HEAD(&qp->steering_rules); 943 944 qp->state = IB_QPS_RESET; 945 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 946 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 947 948 949 if (udata) { 950 union { 951 struct mlx4_ib_create_qp qp; 952 struct mlx4_ib_create_wq wq; 953 } ucmd; 954 size_t copy_len; 955 int shift; 956 int n; 957 958 copy_len = (src == MLX4_IB_QP_SRC) ? 959 sizeof(struct mlx4_ib_create_qp) : 960 min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 961 962 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 963 err = -EFAULT; 964 goto err; 965 } 966 967 if (src == MLX4_IB_RWQ_SRC) { 968 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] || 969 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) { 970 pr_debug("user command isn't supported\n"); 971 err = -EOPNOTSUPP; 972 goto err; 973 } 974 975 if (ucmd.wq.log_range_size > 976 ilog2(dev->dev->caps.max_rss_tbl_sz)) { 977 pr_debug("WQN range size must be equal or smaller than %d\n", 978 dev->dev->caps.max_rss_tbl_sz); 979 err = -EOPNOTSUPP; 980 goto err; 981 } 982 range_size = 1 << ucmd.wq.log_range_size; 983 } else { 984 qp->inl_recv_sz = ucmd.qp.inl_recv_sz; 985 } 986 987 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 988 if (!(dev->dev->caps.flags & 989 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 990 pr_debug("scatter FCS is unsupported\n"); 991 err = -EOPNOTSUPP; 992 goto err; 993 } 994 995 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 996 } 997 998 err = set_rq_size(dev, &init_attr->cap, udata, 999 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1000 if (err) 1001 goto err; 1002 1003 if (src == MLX4_IB_QP_SRC) { 1004 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch; 1005 1006 err = set_user_sq_size(dev, qp, 1007 (struct mlx4_ib_create_qp *) 1008 &ucmd); 1009 if (err) 1010 goto err; 1011 } else { 1012 qp->sq_no_prefetch = 1; 1013 qp->sq.wqe_cnt = 1; 1014 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 1015 /* Allocated buffer expects to have at least that SQ 1016 * size. 1017 */ 1018 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 1019 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 1020 } 1021 1022 qp->umem = 1023 ib_umem_get(udata, 1024 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr : 1025 ucmd.wq.buf_addr, 1026 qp->buf_size, 0, 0); 1027 if (IS_ERR(qp->umem)) { 1028 err = PTR_ERR(qp->umem); 1029 goto err; 1030 } 1031 1032 n = ib_umem_page_count(qp->umem); 1033 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1034 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1035 1036 if (err) 1037 goto err_buf; 1038 1039 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1040 if (err) 1041 goto err_mtt; 1042 1043 if (qp_has_rq(init_attr)) { 1044 err = mlx4_ib_db_map_user(udata, 1045 (src == MLX4_IB_QP_SRC) ? 1046 ucmd.qp.db_addr : 1047 ucmd.wq.db_addr, 1048 &qp->db); 1049 if (err) 1050 goto err_mtt; 1051 } 1052 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1053 } else { 1054 err = set_rq_size(dev, &init_attr->cap, udata, 1055 qp_has_rq(init_attr), qp, 0); 1056 if (err) 1057 goto err; 1058 1059 qp->sq_no_prefetch = 0; 1060 1061 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1062 qp->flags |= MLX4_IB_QP_LSO; 1063 1064 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1065 if (dev->steering_support == 1066 MLX4_STEERING_MODE_DEVICE_MANAGED) 1067 qp->flags |= MLX4_IB_QP_NETIF; 1068 else 1069 goto err; 1070 } 1071 1072 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1073 if (err) 1074 goto err; 1075 1076 if (qp_has_rq(init_attr)) { 1077 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1078 if (err) 1079 goto err; 1080 1081 *qp->db.db = 0; 1082 } 1083 1084 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1085 &qp->buf)) { 1086 err = -ENOMEM; 1087 goto err_db; 1088 } 1089 1090 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1091 &qp->mtt); 1092 if (err) 1093 goto err_buf; 1094 1095 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1096 if (err) 1097 goto err_mtt; 1098 1099 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1100 sizeof(u64), GFP_KERNEL); 1101 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1102 sizeof(u64), GFP_KERNEL); 1103 if (!qp->sq.wrid || !qp->rq.wrid) { 1104 err = -ENOMEM; 1105 goto err_wrid; 1106 } 1107 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1108 } 1109 1110 if (sqpn) { 1111 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1112 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1113 if (alloc_proxy_bufs(pd->device, qp)) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 } 1118 } else if (src == MLX4_IB_RWQ_SRC) { 1119 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn); 1120 if (err) 1121 goto err_wrid; 1122 } else { 1123 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1124 * otherwise, the WQE BlueFlame setup flow wrongly causes 1125 * VLAN insertion. */ 1126 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1127 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1128 (init_attr->cap.max_send_wr ? 1129 MLX4_RESERVE_ETH_BF_QP : 0) | 1130 (init_attr->cap.max_recv_wr ? 1131 MLX4_RESERVE_A0_QP : 0), 1132 qp->mqp.usage); 1133 else 1134 if (qp->flags & MLX4_IB_QP_NETIF) 1135 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1136 else 1137 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1138 &qpn, 0, qp->mqp.usage); 1139 if (err) 1140 goto err_proxy; 1141 } 1142 1143 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1144 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1145 1146 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1147 if (err) 1148 goto err_qpn; 1149 1150 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1151 qp->mqp.qpn |= (1 << 23); 1152 1153 /* 1154 * Hardware wants QPN written in big-endian order (after 1155 * shifting) for send doorbell. Precompute this value to save 1156 * a little bit when posting sends. 1157 */ 1158 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1159 1160 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event : 1161 mlx4_ib_wq_event; 1162 1163 if (!*caller_qp) 1164 *caller_qp = qp; 1165 1166 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1167 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1168 to_mcq(init_attr->recv_cq)); 1169 /* Maintain device to QPs access, needed for further handling 1170 * via reset flow 1171 */ 1172 list_add_tail(&qp->qps_list, &dev->qp_list); 1173 /* Maintain CQ to QPs access, needed for further handling 1174 * via reset flow 1175 */ 1176 mcq = to_mcq(init_attr->send_cq); 1177 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1178 mcq = to_mcq(init_attr->recv_cq); 1179 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1180 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1181 to_mcq(init_attr->recv_cq)); 1182 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1183 return 0; 1184 1185 err_qpn: 1186 if (!sqpn) { 1187 if (qp->flags & MLX4_IB_QP_NETIF) 1188 mlx4_ib_steer_qp_free(dev, qpn, 1); 1189 else if (src == MLX4_IB_RWQ_SRC) 1190 mlx4_ib_release_wqn(context, qp, 0); 1191 else 1192 mlx4_qp_release_range(dev->dev, qpn, 1); 1193 } 1194 err_proxy: 1195 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1196 free_proxy_bufs(pd->device, qp); 1197 err_wrid: 1198 if (udata) { 1199 if (qp_has_rq(init_attr)) 1200 mlx4_ib_db_unmap_user(context, &qp->db); 1201 } else { 1202 kvfree(qp->sq.wrid); 1203 kvfree(qp->rq.wrid); 1204 } 1205 1206 err_mtt: 1207 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1208 1209 err_buf: 1210 if (!qp->umem) 1211 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1212 ib_umem_release(qp->umem); 1213 1214 err_db: 1215 if (!udata && qp_has_rq(init_attr)) 1216 mlx4_db_free(dev->dev, &qp->db); 1217 1218 err: 1219 if (!sqp && !*caller_qp) 1220 kfree(qp); 1221 kfree(sqp); 1222 1223 return err; 1224 } 1225 1226 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1227 { 1228 switch (state) { 1229 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1230 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1231 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1232 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1233 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1234 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1235 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1236 default: return -1; 1237 } 1238 } 1239 1240 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1241 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1242 { 1243 if (send_cq == recv_cq) { 1244 spin_lock(&send_cq->lock); 1245 __acquire(&recv_cq->lock); 1246 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1247 spin_lock(&send_cq->lock); 1248 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1249 } else { 1250 spin_lock(&recv_cq->lock); 1251 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1252 } 1253 } 1254 1255 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1256 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1257 { 1258 if (send_cq == recv_cq) { 1259 __release(&recv_cq->lock); 1260 spin_unlock(&send_cq->lock); 1261 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1262 spin_unlock(&recv_cq->lock); 1263 spin_unlock(&send_cq->lock); 1264 } else { 1265 spin_unlock(&send_cq->lock); 1266 spin_unlock(&recv_cq->lock); 1267 } 1268 } 1269 1270 static void del_gid_entries(struct mlx4_ib_qp *qp) 1271 { 1272 struct mlx4_ib_gid_entry *ge, *tmp; 1273 1274 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1275 list_del(&ge->list); 1276 kfree(ge); 1277 } 1278 } 1279 1280 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1281 { 1282 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1283 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1284 else 1285 return to_mpd(qp->ibqp.pd); 1286 } 1287 1288 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1289 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1290 { 1291 switch (qp->ibqp.qp_type) { 1292 case IB_QPT_XRC_TGT: 1293 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1294 *recv_cq = *send_cq; 1295 break; 1296 case IB_QPT_XRC_INI: 1297 *send_cq = to_mcq(qp->ibqp.send_cq); 1298 *recv_cq = *send_cq; 1299 break; 1300 default: 1301 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1302 to_mcq(qp->ibwq.cq); 1303 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1304 *recv_cq; 1305 break; 1306 } 1307 } 1308 1309 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1310 { 1311 if (qp->state != IB_QPS_RESET) { 1312 int i; 1313 1314 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1315 i++) { 1316 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1317 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1318 1319 mutex_lock(&wq->mutex); 1320 1321 wq->rss_usecnt--; 1322 1323 mutex_unlock(&wq->mutex); 1324 } 1325 1326 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1327 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1328 pr_warn("modify QP %06x to RESET failed.\n", 1329 qp->mqp.qpn); 1330 } 1331 1332 mlx4_qp_remove(dev->dev, &qp->mqp); 1333 mlx4_qp_free(dev->dev, &qp->mqp); 1334 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1335 del_gid_entries(qp); 1336 kfree(qp->rss_ctx); 1337 } 1338 1339 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1340 enum mlx4_ib_source_type src, 1341 struct ib_udata *udata) 1342 { 1343 struct mlx4_ib_cq *send_cq, *recv_cq; 1344 unsigned long flags; 1345 1346 if (qp->state != IB_QPS_RESET) { 1347 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1348 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1349 pr_warn("modify QP %06x to RESET failed.\n", 1350 qp->mqp.qpn); 1351 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1352 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1353 qp->pri.smac = 0; 1354 qp->pri.smac_port = 0; 1355 } 1356 if (qp->alt.smac) { 1357 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1358 qp->alt.smac = 0; 1359 } 1360 if (qp->pri.vid < 0x1000) { 1361 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1362 qp->pri.vid = 0xFFFF; 1363 qp->pri.candidate_vid = 0xFFFF; 1364 qp->pri.update_vid = 0; 1365 } 1366 if (qp->alt.vid < 0x1000) { 1367 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1368 qp->alt.vid = 0xFFFF; 1369 qp->alt.candidate_vid = 0xFFFF; 1370 qp->alt.update_vid = 0; 1371 } 1372 } 1373 1374 get_cqs(qp, src, &send_cq, &recv_cq); 1375 1376 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1377 mlx4_ib_lock_cqs(send_cq, recv_cq); 1378 1379 /* del from lists under both locks above to protect reset flow paths */ 1380 list_del(&qp->qps_list); 1381 list_del(&qp->cq_send_list); 1382 list_del(&qp->cq_recv_list); 1383 if (!udata) { 1384 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1385 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1386 if (send_cq != recv_cq) 1387 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1388 } 1389 1390 mlx4_qp_remove(dev->dev, &qp->mqp); 1391 1392 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1393 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1394 1395 mlx4_qp_free(dev->dev, &qp->mqp); 1396 1397 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1398 if (qp->flags & MLX4_IB_QP_NETIF) 1399 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1400 else if (src == MLX4_IB_RWQ_SRC) 1401 mlx4_ib_release_wqn( 1402 rdma_udata_to_drv_context( 1403 udata, 1404 struct mlx4_ib_ucontext, 1405 ibucontext), 1406 qp, 1); 1407 else 1408 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1409 } 1410 1411 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1412 1413 if (udata) { 1414 if (qp->rq.wqe_cnt) { 1415 struct mlx4_ib_ucontext *mcontext = 1416 rdma_udata_to_drv_context( 1417 udata, 1418 struct mlx4_ib_ucontext, 1419 ibucontext); 1420 1421 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1422 } 1423 } else { 1424 kvfree(qp->sq.wrid); 1425 kvfree(qp->rq.wrid); 1426 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1427 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1428 free_proxy_bufs(&dev->ib_dev, qp); 1429 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1430 if (qp->rq.wqe_cnt) 1431 mlx4_db_free(dev->dev, &qp->db); 1432 } 1433 ib_umem_release(qp->umem); 1434 1435 del_gid_entries(qp); 1436 } 1437 1438 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1439 { 1440 /* Native or PPF */ 1441 if (!mlx4_is_mfunc(dev->dev) || 1442 (mlx4_is_master(dev->dev) && 1443 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1444 return dev->dev->phys_caps.base_sqpn + 1445 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1446 attr->port_num - 1; 1447 } 1448 /* PF or VF -- creating proxies */ 1449 if (attr->qp_type == IB_QPT_SMI) 1450 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1451 else 1452 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1453 } 1454 1455 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1456 struct ib_qp_init_attr *init_attr, 1457 struct ib_udata *udata) 1458 { 1459 struct mlx4_ib_qp *qp = NULL; 1460 int err; 1461 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1462 u16 xrcdn = 0; 1463 1464 if (init_attr->rwq_ind_tbl) 1465 return _mlx4_ib_create_qp_rss(pd, init_attr, udata); 1466 1467 /* 1468 * We only support LSO, vendor flag1, and multicast loopback blocking, 1469 * and only for kernel UD QPs. 1470 */ 1471 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1472 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1473 MLX4_IB_SRIOV_TUNNEL_QP | 1474 MLX4_IB_SRIOV_SQP | 1475 MLX4_IB_QP_NETIF | 1476 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1477 return ERR_PTR(-EINVAL); 1478 1479 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1480 if (init_attr->qp_type != IB_QPT_UD) 1481 return ERR_PTR(-EINVAL); 1482 } 1483 1484 if (init_attr->create_flags) { 1485 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1486 return ERR_PTR(-EINVAL); 1487 1488 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1489 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1490 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1491 init_attr->qp_type != IB_QPT_UD) || 1492 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1493 init_attr->qp_type > IB_QPT_GSI) || 1494 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1495 init_attr->qp_type != IB_QPT_GSI)) 1496 return ERR_PTR(-EINVAL); 1497 } 1498 1499 switch (init_attr->qp_type) { 1500 case IB_QPT_XRC_TGT: 1501 pd = to_mxrcd(init_attr->xrcd)->pd; 1502 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1503 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1504 /* fall through */ 1505 case IB_QPT_XRC_INI: 1506 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1507 return ERR_PTR(-ENOSYS); 1508 init_attr->recv_cq = init_attr->send_cq; 1509 /* fall through */ 1510 case IB_QPT_RC: 1511 case IB_QPT_UC: 1512 case IB_QPT_RAW_PACKET: 1513 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1514 if (!qp) 1515 return ERR_PTR(-ENOMEM); 1516 qp->pri.vid = 0xFFFF; 1517 qp->alt.vid = 0xFFFF; 1518 /* fall through */ 1519 case IB_QPT_UD: 1520 { 1521 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1522 init_attr, udata, 0, &qp); 1523 if (err) { 1524 kfree(qp); 1525 return ERR_PTR(err); 1526 } 1527 1528 qp->ibqp.qp_num = qp->mqp.qpn; 1529 qp->xrcdn = xrcdn; 1530 1531 break; 1532 } 1533 case IB_QPT_SMI: 1534 case IB_QPT_GSI: 1535 { 1536 int sqpn; 1537 1538 /* Userspace is not allowed to create special QPs: */ 1539 if (udata) 1540 return ERR_PTR(-EINVAL); 1541 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1542 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1543 1, 1, &sqpn, 0, 1544 MLX4_RES_USAGE_DRIVER); 1545 1546 if (res) 1547 return ERR_PTR(res); 1548 } else { 1549 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1550 } 1551 1552 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1553 init_attr, udata, sqpn, &qp); 1554 if (err) 1555 return ERR_PTR(err); 1556 1557 qp->port = init_attr->port_num; 1558 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1559 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1560 break; 1561 } 1562 default: 1563 /* Don't support raw QPs */ 1564 return ERR_PTR(-EINVAL); 1565 } 1566 1567 return &qp->ibqp; 1568 } 1569 1570 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1571 struct ib_qp_init_attr *init_attr, 1572 struct ib_udata *udata) { 1573 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1574 struct ib_qp *ibqp; 1575 struct mlx4_ib_dev *dev = to_mdev(device); 1576 1577 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1578 1579 if (!IS_ERR(ibqp) && 1580 (init_attr->qp_type == IB_QPT_GSI) && 1581 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1582 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1583 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1584 1585 if (is_eth && 1586 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1587 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1588 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1589 1590 if (IS_ERR(sqp->roce_v2_gsi)) { 1591 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1592 sqp->roce_v2_gsi = NULL; 1593 } else { 1594 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1595 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1596 } 1597 1598 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1599 } 1600 } 1601 return ibqp; 1602 } 1603 1604 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1605 { 1606 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1607 struct mlx4_ib_qp *mqp = to_mqp(qp); 1608 1609 if (is_qp0(dev, mqp)) 1610 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1611 1612 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1613 dev->qp1_proxy[mqp->port - 1] == mqp) { 1614 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1615 dev->qp1_proxy[mqp->port - 1] = NULL; 1616 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1617 } 1618 1619 if (mqp->counter_index) 1620 mlx4_ib_free_qp_counter(dev, mqp); 1621 1622 if (qp->rwq_ind_tbl) { 1623 destroy_qp_rss(dev, mqp); 1624 } else { 1625 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata); 1626 } 1627 1628 if (is_sqp(dev, mqp)) 1629 kfree(to_msqp(mqp)); 1630 else 1631 kfree(mqp); 1632 1633 return 0; 1634 } 1635 1636 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1637 { 1638 struct mlx4_ib_qp *mqp = to_mqp(qp); 1639 1640 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1641 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1642 1643 if (sqp->roce_v2_gsi) 1644 ib_destroy_qp(sqp->roce_v2_gsi); 1645 } 1646 1647 return _mlx4_ib_destroy_qp(qp, udata); 1648 } 1649 1650 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1651 { 1652 switch (type) { 1653 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1654 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1655 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1656 case MLX4_IB_QPT_XRC_INI: 1657 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1658 case MLX4_IB_QPT_SMI: 1659 case MLX4_IB_QPT_GSI: 1660 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1661 1662 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1663 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1664 MLX4_QP_ST_MLX : -1); 1665 case MLX4_IB_QPT_PROXY_SMI: 1666 case MLX4_IB_QPT_TUN_SMI: 1667 case MLX4_IB_QPT_PROXY_GSI: 1668 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1669 MLX4_QP_ST_UD : -1); 1670 default: return -1; 1671 } 1672 } 1673 1674 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1675 int attr_mask) 1676 { 1677 u8 dest_rd_atomic; 1678 u32 access_flags; 1679 u32 hw_access_flags = 0; 1680 1681 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1682 dest_rd_atomic = attr->max_dest_rd_atomic; 1683 else 1684 dest_rd_atomic = qp->resp_depth; 1685 1686 if (attr_mask & IB_QP_ACCESS_FLAGS) 1687 access_flags = attr->qp_access_flags; 1688 else 1689 access_flags = qp->atomic_rd_en; 1690 1691 if (!dest_rd_atomic) 1692 access_flags &= IB_ACCESS_REMOTE_WRITE; 1693 1694 if (access_flags & IB_ACCESS_REMOTE_READ) 1695 hw_access_flags |= MLX4_QP_BIT_RRE; 1696 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1697 hw_access_flags |= MLX4_QP_BIT_RAE; 1698 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1699 hw_access_flags |= MLX4_QP_BIT_RWE; 1700 1701 return cpu_to_be32(hw_access_flags); 1702 } 1703 1704 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1705 int attr_mask) 1706 { 1707 if (attr_mask & IB_QP_PKEY_INDEX) 1708 sqp->pkey_index = attr->pkey_index; 1709 if (attr_mask & IB_QP_QKEY) 1710 sqp->qkey = attr->qkey; 1711 if (attr_mask & IB_QP_SQ_PSN) 1712 sqp->send_psn = attr->sq_psn; 1713 } 1714 1715 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1716 { 1717 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1718 } 1719 1720 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1721 const struct rdma_ah_attr *ah, 1722 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1723 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1724 { 1725 int vidx; 1726 int smac_index; 1727 int err; 1728 1729 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1730 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1731 if (rdma_ah_get_static_rate(ah)) { 1732 path->static_rate = rdma_ah_get_static_rate(ah) + 1733 MLX4_STAT_RATE_OFFSET; 1734 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1735 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1736 --path->static_rate; 1737 } else 1738 path->static_rate = 0; 1739 1740 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1741 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1742 int real_sgid_index = 1743 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1744 1745 if (real_sgid_index < 0) 1746 return real_sgid_index; 1747 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1748 pr_err("sgid_index (%u) too large. max is %d\n", 1749 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1750 return -1; 1751 } 1752 1753 path->grh_mylmc |= 1 << 7; 1754 path->mgid_index = real_sgid_index; 1755 path->hop_limit = grh->hop_limit; 1756 path->tclass_flowlabel = 1757 cpu_to_be32((grh->traffic_class << 20) | 1758 (grh->flow_label)); 1759 memcpy(path->rgid, grh->dgid.raw, 16); 1760 } 1761 1762 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1763 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1764 return -1; 1765 1766 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1767 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1768 1769 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1770 if (vlan_tag < 0x1000) { 1771 if (smac_info->vid < 0x1000) { 1772 /* both valid vlan ids */ 1773 if (smac_info->vid != vlan_tag) { 1774 /* different VIDs. unreg old and reg new */ 1775 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1776 if (err) 1777 return err; 1778 smac_info->candidate_vid = vlan_tag; 1779 smac_info->candidate_vlan_index = vidx; 1780 smac_info->candidate_vlan_port = port; 1781 smac_info->update_vid = 1; 1782 path->vlan_index = vidx; 1783 } else { 1784 path->vlan_index = smac_info->vlan_index; 1785 } 1786 } else { 1787 /* no current vlan tag in qp */ 1788 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1789 if (err) 1790 return err; 1791 smac_info->candidate_vid = vlan_tag; 1792 smac_info->candidate_vlan_index = vidx; 1793 smac_info->candidate_vlan_port = port; 1794 smac_info->update_vid = 1; 1795 path->vlan_index = vidx; 1796 } 1797 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1798 path->fl = 1 << 6; 1799 } else { 1800 /* have current vlan tag. unregister it at modify-qp success */ 1801 if (smac_info->vid < 0x1000) { 1802 smac_info->candidate_vid = 0xFFFF; 1803 smac_info->update_vid = 1; 1804 } 1805 } 1806 1807 /* get smac_index for RoCE use. 1808 * If no smac was yet assigned, register one. 1809 * If one was already assigned, but the new mac differs, 1810 * unregister the old one and register the new one. 1811 */ 1812 if ((!smac_info->smac && !smac_info->smac_port) || 1813 smac_info->smac != smac) { 1814 /* register candidate now, unreg if needed, after success */ 1815 smac_index = mlx4_register_mac(dev->dev, port, smac); 1816 if (smac_index >= 0) { 1817 smac_info->candidate_smac_index = smac_index; 1818 smac_info->candidate_smac = smac; 1819 smac_info->candidate_smac_port = port; 1820 } else { 1821 return -EINVAL; 1822 } 1823 } else { 1824 smac_index = smac_info->smac_index; 1825 } 1826 memcpy(path->dmac, ah->roce.dmac, 6); 1827 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1828 /* put MAC table smac index for IBoE */ 1829 path->grh_mylmc = (u8) (smac_index) | 0x80; 1830 } else { 1831 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1832 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1833 } 1834 1835 return 0; 1836 } 1837 1838 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1839 enum ib_qp_attr_mask qp_attr_mask, 1840 struct mlx4_ib_qp *mqp, 1841 struct mlx4_qp_path *path, u8 port, 1842 u16 vlan_id, u8 *smac) 1843 { 1844 return _mlx4_set_path(dev, &qp->ah_attr, 1845 mlx4_mac_to_u64(smac), 1846 vlan_id, 1847 path, &mqp->pri, port); 1848 } 1849 1850 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1851 const struct ib_qp_attr *qp, 1852 enum ib_qp_attr_mask qp_attr_mask, 1853 struct mlx4_ib_qp *mqp, 1854 struct mlx4_qp_path *path, u8 port) 1855 { 1856 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1857 0, 1858 0xffff, 1859 path, &mqp->alt, port); 1860 } 1861 1862 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1863 { 1864 struct mlx4_ib_gid_entry *ge, *tmp; 1865 1866 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1867 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1868 ge->added = 1; 1869 ge->port = qp->port; 1870 } 1871 } 1872 } 1873 1874 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1875 struct mlx4_ib_qp *qp, 1876 struct mlx4_qp_context *context) 1877 { 1878 u64 u64_mac; 1879 int smac_index; 1880 1881 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1882 1883 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1884 if (!qp->pri.smac && !qp->pri.smac_port) { 1885 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1886 if (smac_index >= 0) { 1887 qp->pri.candidate_smac_index = smac_index; 1888 qp->pri.candidate_smac = u64_mac; 1889 qp->pri.candidate_smac_port = qp->port; 1890 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1891 } else { 1892 return -ENOENT; 1893 } 1894 } 1895 return 0; 1896 } 1897 1898 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1899 { 1900 struct counter_index *new_counter_index; 1901 int err; 1902 u32 tmp_idx; 1903 1904 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1905 IB_LINK_LAYER_ETHERNET || 1906 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1907 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1908 return 0; 1909 1910 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1911 if (err) 1912 return err; 1913 1914 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1915 if (!new_counter_index) { 1916 mlx4_counter_free(dev->dev, tmp_idx); 1917 return -ENOMEM; 1918 } 1919 1920 new_counter_index->index = tmp_idx; 1921 new_counter_index->allocated = 1; 1922 qp->counter_index = new_counter_index; 1923 1924 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1925 list_add_tail(&new_counter_index->list, 1926 &dev->counters_table[qp->port - 1].counters_list); 1927 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1928 1929 return 0; 1930 } 1931 1932 enum { 1933 MLX4_QPC_ROCE_MODE_1 = 0, 1934 MLX4_QPC_ROCE_MODE_2 = 2, 1935 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1936 }; 1937 1938 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1939 { 1940 switch (gid_type) { 1941 case IB_GID_TYPE_ROCE: 1942 return MLX4_QPC_ROCE_MODE_1; 1943 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1944 return MLX4_QPC_ROCE_MODE_2; 1945 default: 1946 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1947 } 1948 } 1949 1950 /* 1951 * Go over all RSS QP's childes (WQs) and apply their HW state according to 1952 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 1953 */ 1954 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num, 1955 struct ib_udata *udata) 1956 { 1957 int err = 0; 1958 int i; 1959 1960 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 1961 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 1962 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1963 1964 mutex_lock(&wq->mutex); 1965 1966 /* Mlx4_ib restrictions: 1967 * WQ's is associated to a port according to the RSS QP it is 1968 * associates to. 1969 * In case the WQ is associated to a different port by another 1970 * RSS QP, return a failure. 1971 */ 1972 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 1973 err = -EINVAL; 1974 mutex_unlock(&wq->mutex); 1975 break; 1976 } 1977 wq->port = port_num; 1978 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 1979 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata); 1980 if (err) { 1981 mutex_unlock(&wq->mutex); 1982 break; 1983 } 1984 } 1985 wq->rss_usecnt++; 1986 1987 mutex_unlock(&wq->mutex); 1988 } 1989 1990 if (i && err) { 1991 int j; 1992 1993 for (j = (i - 1); j >= 0; j--) { 1994 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 1995 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1996 1997 mutex_lock(&wq->mutex); 1998 1999 if ((wq->rss_usecnt == 1) && 2000 (ibwq->state == IB_WQS_RDY)) 2001 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, 2002 udata)) 2003 pr_warn("failed to reverse WQN=0x%06x\n", 2004 ibwq->wq_num); 2005 wq->rss_usecnt--; 2006 2007 mutex_unlock(&wq->mutex); 2008 } 2009 } 2010 2011 return err; 2012 } 2013 2014 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, 2015 struct ib_udata *udata) 2016 { 2017 int i; 2018 2019 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2020 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2021 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2022 2023 mutex_lock(&wq->mutex); 2024 2025 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2026 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata)) 2027 pr_warn("failed to reverse WQN=%x\n", 2028 ibwq->wq_num); 2029 wq->rss_usecnt--; 2030 2031 mutex_unlock(&wq->mutex); 2032 } 2033 } 2034 2035 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2036 struct mlx4_ib_qp *qp) 2037 { 2038 struct mlx4_rss_context *rss_context; 2039 2040 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2041 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2042 2043 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2044 rss_context->default_qpn = 2045 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2046 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2047 rss_context->base_qpn_udp = rss_context->default_qpn; 2048 rss_context->flags = qp->rss_ctx->flags; 2049 /* Currently support just toeplitz */ 2050 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2051 2052 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2053 MLX4_EN_RSS_KEY_SIZE); 2054 } 2055 2056 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2057 const struct ib_qp_attr *attr, int attr_mask, 2058 enum ib_qp_state cur_state, 2059 enum ib_qp_state new_state, 2060 struct ib_udata *udata) 2061 { 2062 struct ib_srq *ibsrq; 2063 const struct ib_gid_attr *gid_attr = NULL; 2064 struct ib_rwq_ind_table *rwq_ind_tbl; 2065 enum ib_qp_type qp_type; 2066 struct mlx4_ib_dev *dev; 2067 struct mlx4_ib_qp *qp; 2068 struct mlx4_ib_pd *pd; 2069 struct mlx4_ib_cq *send_cq, *recv_cq; 2070 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2071 udata, struct mlx4_ib_ucontext, ibucontext); 2072 struct mlx4_qp_context *context; 2073 enum mlx4_qp_optpar optpar = 0; 2074 int sqd_event; 2075 int steer_qp = 0; 2076 int err = -EINVAL; 2077 int counter_index; 2078 2079 if (src_type == MLX4_IB_RWQ_SRC) { 2080 struct ib_wq *ibwq; 2081 2082 ibwq = (struct ib_wq *)src; 2083 ibsrq = NULL; 2084 rwq_ind_tbl = NULL; 2085 qp_type = IB_QPT_RAW_PACKET; 2086 qp = to_mqp((struct ib_qp *)ibwq); 2087 dev = to_mdev(ibwq->device); 2088 pd = to_mpd(ibwq->pd); 2089 } else { 2090 struct ib_qp *ibqp; 2091 2092 ibqp = (struct ib_qp *)src; 2093 ibsrq = ibqp->srq; 2094 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2095 qp_type = ibqp->qp_type; 2096 qp = to_mqp(ibqp); 2097 dev = to_mdev(ibqp->device); 2098 pd = get_pd(qp); 2099 } 2100 2101 /* APM is not supported under RoCE */ 2102 if (attr_mask & IB_QP_ALT_PATH && 2103 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2104 IB_LINK_LAYER_ETHERNET) 2105 return -ENOTSUPP; 2106 2107 context = kzalloc(sizeof *context, GFP_KERNEL); 2108 if (!context) 2109 return -ENOMEM; 2110 2111 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2112 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2113 2114 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2115 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2116 else { 2117 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2118 switch (attr->path_mig_state) { 2119 case IB_MIG_MIGRATED: 2120 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2121 break; 2122 case IB_MIG_REARM: 2123 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2124 break; 2125 case IB_MIG_ARMED: 2126 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2127 break; 2128 } 2129 } 2130 2131 if (qp->inl_recv_sz) 2132 context->param3 |= cpu_to_be32(1 << 25); 2133 2134 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2135 context->param3 |= cpu_to_be32(1 << 29); 2136 2137 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2138 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2139 else if (qp_type == IB_QPT_RAW_PACKET) 2140 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2141 else if (qp_type == IB_QPT_UD) { 2142 if (qp->flags & MLX4_IB_QP_LSO) 2143 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2144 ilog2(dev->dev->caps.max_gso_sz); 2145 else 2146 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2147 } else if (attr_mask & IB_QP_PATH_MTU) { 2148 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2149 pr_err("path MTU (%u) is invalid\n", 2150 attr->path_mtu); 2151 goto out; 2152 } 2153 context->mtu_msgmax = (attr->path_mtu << 5) | 2154 ilog2(dev->dev->caps.max_msg_sz); 2155 } 2156 2157 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2158 if (qp->rq.wqe_cnt) 2159 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2160 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2161 } 2162 2163 if (qp->sq.wqe_cnt) 2164 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2165 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2166 2167 if (new_state == IB_QPS_RESET && qp->counter_index) 2168 mlx4_ib_free_qp_counter(dev, qp); 2169 2170 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2171 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2172 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2173 if (qp_type == IB_QPT_RAW_PACKET) 2174 context->param3 |= cpu_to_be32(1 << 30); 2175 } 2176 2177 if (ucontext) 2178 context->usr_page = cpu_to_be32( 2179 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 2180 else 2181 context->usr_page = cpu_to_be32( 2182 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2183 2184 if (attr_mask & IB_QP_DEST_QPN) 2185 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2186 2187 if (attr_mask & IB_QP_PORT) { 2188 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2189 !(attr_mask & IB_QP_AV)) { 2190 mlx4_set_sched(&context->pri_path, attr->port_num); 2191 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2192 } 2193 } 2194 2195 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2196 err = create_qp_lb_counter(dev, qp); 2197 if (err) 2198 goto out; 2199 2200 counter_index = 2201 dev->counters_table[qp->port - 1].default_counter; 2202 if (qp->counter_index) 2203 counter_index = qp->counter_index->index; 2204 2205 if (counter_index != -1) { 2206 context->pri_path.counter_index = counter_index; 2207 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2208 if (qp->counter_index) { 2209 context->pri_path.fl |= 2210 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2211 context->pri_path.vlan_control |= 2212 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2213 } 2214 } else 2215 context->pri_path.counter_index = 2216 MLX4_SINK_COUNTER_INDEX(dev->dev); 2217 2218 if (qp->flags & MLX4_IB_QP_NETIF) { 2219 mlx4_ib_steer_qp_reg(dev, qp, 1); 2220 steer_qp = 1; 2221 } 2222 2223 if (qp_type == IB_QPT_GSI) { 2224 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2225 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2226 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2227 2228 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2229 } 2230 } 2231 2232 if (attr_mask & IB_QP_PKEY_INDEX) { 2233 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2234 context->pri_path.disable_pkey_check = 0x40; 2235 context->pri_path.pkey_index = attr->pkey_index; 2236 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2237 } 2238 2239 if (attr_mask & IB_QP_AV) { 2240 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2241 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2242 u16 vlan = 0xffff; 2243 u8 smac[ETH_ALEN]; 2244 int is_eth = 2245 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2246 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2247 2248 if (is_eth) { 2249 gid_attr = attr->ah_attr.grh.sgid_attr; 2250 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 2251 &smac[0]); 2252 if (err) 2253 goto out; 2254 } 2255 2256 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2257 port_num, vlan, smac)) 2258 goto out; 2259 2260 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2261 MLX4_QP_OPTPAR_SCHED_QUEUE); 2262 2263 if (is_eth && 2264 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2265 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2266 2267 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2268 err = -EINVAL; 2269 goto out; 2270 } 2271 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2272 } 2273 2274 } 2275 2276 if (attr_mask & IB_QP_TIMEOUT) { 2277 context->pri_path.ackto |= attr->timeout << 3; 2278 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2279 } 2280 2281 if (attr_mask & IB_QP_ALT_PATH) { 2282 if (attr->alt_port_num == 0 || 2283 attr->alt_port_num > dev->dev->caps.num_ports) 2284 goto out; 2285 2286 if (attr->alt_pkey_index >= 2287 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2288 goto out; 2289 2290 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2291 &context->alt_path, 2292 attr->alt_port_num)) 2293 goto out; 2294 2295 context->alt_path.pkey_index = attr->alt_pkey_index; 2296 context->alt_path.ackto = attr->alt_timeout << 3; 2297 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2298 } 2299 2300 context->pd = cpu_to_be32(pd->pdn); 2301 2302 if (!rwq_ind_tbl) { 2303 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2304 get_cqs(qp, src_type, &send_cq, &recv_cq); 2305 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2306 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2307 recv_cq = send_cq; 2308 } 2309 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2310 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2311 2312 /* Set "fast registration enabled" for all kernel QPs */ 2313 if (!ucontext) 2314 context->params1 |= cpu_to_be32(1 << 11); 2315 2316 if (attr_mask & IB_QP_RNR_RETRY) { 2317 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2318 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2319 } 2320 2321 if (attr_mask & IB_QP_RETRY_CNT) { 2322 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2323 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2324 } 2325 2326 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2327 if (attr->max_rd_atomic) 2328 context->params1 |= 2329 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2330 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2331 } 2332 2333 if (attr_mask & IB_QP_SQ_PSN) 2334 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2335 2336 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2337 if (attr->max_dest_rd_atomic) 2338 context->params2 |= 2339 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2340 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2341 } 2342 2343 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2344 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2345 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2346 } 2347 2348 if (ibsrq) 2349 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2350 2351 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2352 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2353 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2354 } 2355 if (attr_mask & IB_QP_RQ_PSN) 2356 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2357 2358 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2359 if (attr_mask & IB_QP_QKEY) { 2360 if (qp->mlx4_ib_qp_type & 2361 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2362 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2363 else { 2364 if (mlx4_is_mfunc(dev->dev) && 2365 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2366 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2367 MLX4_RESERVED_QKEY_BASE) { 2368 pr_err("Cannot use reserved QKEY" 2369 " 0x%x (range 0xffff0000..0xffffffff" 2370 " is reserved)\n", attr->qkey); 2371 err = -EINVAL; 2372 goto out; 2373 } 2374 context->qkey = cpu_to_be32(attr->qkey); 2375 } 2376 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2377 } 2378 2379 if (ibsrq) 2380 context->srqn = cpu_to_be32(1 << 24 | 2381 to_msrq(ibsrq)->msrq.srqn); 2382 2383 if (qp->rq.wqe_cnt && 2384 cur_state == IB_QPS_RESET && 2385 new_state == IB_QPS_INIT) 2386 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2387 2388 if (cur_state == IB_QPS_INIT && 2389 new_state == IB_QPS_RTR && 2390 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2391 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2392 context->pri_path.sched_queue = (qp->port - 1) << 6; 2393 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2394 qp->mlx4_ib_qp_type & 2395 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2396 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2397 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2398 context->pri_path.fl = 0x80; 2399 } else { 2400 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2401 context->pri_path.fl = 0x80; 2402 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2403 } 2404 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2405 IB_LINK_LAYER_ETHERNET) { 2406 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2407 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2408 context->pri_path.feup = 1 << 7; /* don't fsm */ 2409 /* handle smac_index */ 2410 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2411 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2412 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2413 err = handle_eth_ud_smac_index(dev, qp, context); 2414 if (err) { 2415 err = -EINVAL; 2416 goto out; 2417 } 2418 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2419 dev->qp1_proxy[qp->port - 1] = qp; 2420 } 2421 } 2422 } 2423 2424 if (qp_type == IB_QPT_RAW_PACKET) { 2425 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2426 MLX4_IB_LINK_TYPE_ETH; 2427 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2428 /* set QP to receive both tunneled & non-tunneled packets */ 2429 if (!rwq_ind_tbl) 2430 context->srqn = cpu_to_be32(7 << 28); 2431 } 2432 } 2433 2434 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2435 int is_eth = rdma_port_get_link_layer( 2436 &dev->ib_dev, qp->port) == 2437 IB_LINK_LAYER_ETHERNET; 2438 if (is_eth) { 2439 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2440 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2441 } 2442 } 2443 2444 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2445 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2446 sqd_event = 1; 2447 else 2448 sqd_event = 0; 2449 2450 if (!ucontext && 2451 cur_state == IB_QPS_RESET && 2452 new_state == IB_QPS_INIT) 2453 context->rlkey_roce_mode |= (1 << 4); 2454 2455 /* 2456 * Before passing a kernel QP to the HW, make sure that the 2457 * ownership bits of the send queue are set and the SQ 2458 * headroom is stamped so that the hardware doesn't start 2459 * processing stale work requests. 2460 */ 2461 if (!ucontext && 2462 cur_state == IB_QPS_RESET && 2463 new_state == IB_QPS_INIT) { 2464 struct mlx4_wqe_ctrl_seg *ctrl; 2465 int i; 2466 2467 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2468 ctrl = get_send_wqe(qp, i); 2469 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2470 ctrl->qpn_vlan.fence_size = 2471 1 << (qp->sq.wqe_shift - 4); 2472 stamp_send_wqe(qp, i); 2473 } 2474 } 2475 2476 if (rwq_ind_tbl && 2477 cur_state == IB_QPS_RESET && 2478 new_state == IB_QPS_INIT) { 2479 fill_qp_rss_context(context, qp); 2480 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2481 } 2482 2483 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2484 to_mlx4_state(new_state), context, optpar, 2485 sqd_event, &qp->mqp); 2486 if (err) 2487 goto out; 2488 2489 qp->state = new_state; 2490 2491 if (attr_mask & IB_QP_ACCESS_FLAGS) 2492 qp->atomic_rd_en = attr->qp_access_flags; 2493 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2494 qp->resp_depth = attr->max_dest_rd_atomic; 2495 if (attr_mask & IB_QP_PORT) { 2496 qp->port = attr->port_num; 2497 update_mcg_macs(dev, qp); 2498 } 2499 if (attr_mask & IB_QP_ALT_PATH) 2500 qp->alt_port = attr->alt_port_num; 2501 2502 if (is_sqp(dev, qp)) 2503 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2504 2505 /* 2506 * If we moved QP0 to RTR, bring the IB link up; if we moved 2507 * QP0 to RESET or ERROR, bring the link back down. 2508 */ 2509 if (is_qp0(dev, qp)) { 2510 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2511 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2512 pr_warn("INIT_PORT failed for port %d\n", 2513 qp->port); 2514 2515 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2516 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2517 mlx4_CLOSE_PORT(dev->dev, qp->port); 2518 } 2519 2520 /* 2521 * If we moved a kernel QP to RESET, clean up all old CQ 2522 * entries and reinitialize the QP. 2523 */ 2524 if (new_state == IB_QPS_RESET) { 2525 if (!ucontext) { 2526 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2527 ibsrq ? to_msrq(ibsrq) : NULL); 2528 if (send_cq != recv_cq) 2529 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2530 2531 qp->rq.head = 0; 2532 qp->rq.tail = 0; 2533 qp->sq.head = 0; 2534 qp->sq.tail = 0; 2535 qp->sq_next_wqe = 0; 2536 if (qp->rq.wqe_cnt) 2537 *qp->db.db = 0; 2538 2539 if (qp->flags & MLX4_IB_QP_NETIF) 2540 mlx4_ib_steer_qp_reg(dev, qp, 0); 2541 } 2542 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2543 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2544 qp->pri.smac = 0; 2545 qp->pri.smac_port = 0; 2546 } 2547 if (qp->alt.smac) { 2548 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2549 qp->alt.smac = 0; 2550 } 2551 if (qp->pri.vid < 0x1000) { 2552 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2553 qp->pri.vid = 0xFFFF; 2554 qp->pri.candidate_vid = 0xFFFF; 2555 qp->pri.update_vid = 0; 2556 } 2557 2558 if (qp->alt.vid < 0x1000) { 2559 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2560 qp->alt.vid = 0xFFFF; 2561 qp->alt.candidate_vid = 0xFFFF; 2562 qp->alt.update_vid = 0; 2563 } 2564 } 2565 out: 2566 if (err && qp->counter_index) 2567 mlx4_ib_free_qp_counter(dev, qp); 2568 if (err && steer_qp) 2569 mlx4_ib_steer_qp_reg(dev, qp, 0); 2570 kfree(context); 2571 if (qp->pri.candidate_smac || 2572 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2573 if (err) { 2574 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2575 } else { 2576 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2577 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2578 qp->pri.smac = qp->pri.candidate_smac; 2579 qp->pri.smac_index = qp->pri.candidate_smac_index; 2580 qp->pri.smac_port = qp->pri.candidate_smac_port; 2581 } 2582 qp->pri.candidate_smac = 0; 2583 qp->pri.candidate_smac_index = 0; 2584 qp->pri.candidate_smac_port = 0; 2585 } 2586 if (qp->alt.candidate_smac) { 2587 if (err) { 2588 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2589 } else { 2590 if (qp->alt.smac) 2591 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2592 qp->alt.smac = qp->alt.candidate_smac; 2593 qp->alt.smac_index = qp->alt.candidate_smac_index; 2594 qp->alt.smac_port = qp->alt.candidate_smac_port; 2595 } 2596 qp->alt.candidate_smac = 0; 2597 qp->alt.candidate_smac_index = 0; 2598 qp->alt.candidate_smac_port = 0; 2599 } 2600 2601 if (qp->pri.update_vid) { 2602 if (err) { 2603 if (qp->pri.candidate_vid < 0x1000) 2604 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2605 qp->pri.candidate_vid); 2606 } else { 2607 if (qp->pri.vid < 0x1000) 2608 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2609 qp->pri.vid); 2610 qp->pri.vid = qp->pri.candidate_vid; 2611 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2612 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2613 } 2614 qp->pri.candidate_vid = 0xFFFF; 2615 qp->pri.update_vid = 0; 2616 } 2617 2618 if (qp->alt.update_vid) { 2619 if (err) { 2620 if (qp->alt.candidate_vid < 0x1000) 2621 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2622 qp->alt.candidate_vid); 2623 } else { 2624 if (qp->alt.vid < 0x1000) 2625 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2626 qp->alt.vid); 2627 qp->alt.vid = qp->alt.candidate_vid; 2628 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2629 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2630 } 2631 qp->alt.candidate_vid = 0xFFFF; 2632 qp->alt.update_vid = 0; 2633 } 2634 2635 return err; 2636 } 2637 2638 enum { 2639 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2640 IB_QP_PORT), 2641 }; 2642 2643 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2644 int attr_mask, struct ib_udata *udata) 2645 { 2646 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2647 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2648 enum ib_qp_state cur_state, new_state; 2649 int err = -EINVAL; 2650 mutex_lock(&qp->mutex); 2651 2652 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2653 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2654 2655 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2656 attr_mask)) { 2657 pr_debug("qpn 0x%x: invalid attribute mask specified " 2658 "for transition %d to %d. qp_type %d," 2659 " attr_mask 0x%x\n", 2660 ibqp->qp_num, cur_state, new_state, 2661 ibqp->qp_type, attr_mask); 2662 goto out; 2663 } 2664 2665 if (ibqp->rwq_ind_tbl) { 2666 if (!(((cur_state == IB_QPS_RESET) && 2667 (new_state == IB_QPS_INIT)) || 2668 ((cur_state == IB_QPS_INIT) && 2669 (new_state == IB_QPS_RTR)))) { 2670 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2671 ibqp->qp_num, cur_state, new_state); 2672 2673 err = -EOPNOTSUPP; 2674 goto out; 2675 } 2676 2677 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2678 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2679 ibqp->qp_num, attr_mask, cur_state, new_state); 2680 2681 err = -EOPNOTSUPP; 2682 goto out; 2683 } 2684 } 2685 2686 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2687 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2688 if ((ibqp->qp_type == IB_QPT_RC) || 2689 (ibqp->qp_type == IB_QPT_UD) || 2690 (ibqp->qp_type == IB_QPT_UC) || 2691 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2692 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2693 attr->port_num = mlx4_ib_bond_next_port(dev); 2694 } 2695 } else { 2696 /* no sense in changing port_num 2697 * when ports are bonded */ 2698 attr_mask &= ~IB_QP_PORT; 2699 } 2700 } 2701 2702 if ((attr_mask & IB_QP_PORT) && 2703 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2704 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2705 "for transition %d to %d. qp_type %d\n", 2706 ibqp->qp_num, attr->port_num, cur_state, 2707 new_state, ibqp->qp_type); 2708 goto out; 2709 } 2710 2711 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2712 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2713 IB_LINK_LAYER_ETHERNET)) 2714 goto out; 2715 2716 if (attr_mask & IB_QP_PKEY_INDEX) { 2717 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2718 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2719 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2720 "for transition %d to %d. qp_type %d\n", 2721 ibqp->qp_num, attr->pkey_index, cur_state, 2722 new_state, ibqp->qp_type); 2723 goto out; 2724 } 2725 } 2726 2727 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2728 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2729 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2730 "Transition %d to %d. qp_type %d\n", 2731 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2732 new_state, ibqp->qp_type); 2733 goto out; 2734 } 2735 2736 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2737 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2738 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2739 "Transition %d to %d. qp_type %d\n", 2740 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2741 new_state, ibqp->qp_type); 2742 goto out; 2743 } 2744 2745 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2746 err = 0; 2747 goto out; 2748 } 2749 2750 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2751 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num, 2752 udata); 2753 if (err) 2754 goto out; 2755 } 2756 2757 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2758 cur_state, new_state, udata); 2759 2760 if (ibqp->rwq_ind_tbl && err) 2761 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata); 2762 2763 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2764 attr->port_num = 1; 2765 2766 out: 2767 mutex_unlock(&qp->mutex); 2768 return err; 2769 } 2770 2771 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2772 int attr_mask, struct ib_udata *udata) 2773 { 2774 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2775 int ret; 2776 2777 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2778 2779 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2780 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2781 int err = 0; 2782 2783 if (sqp->roce_v2_gsi) 2784 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2785 if (err) 2786 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2787 err); 2788 } 2789 return ret; 2790 } 2791 2792 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2793 { 2794 int i; 2795 for (i = 0; i < dev->caps.num_ports; i++) { 2796 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2797 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2798 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2799 return 0; 2800 } 2801 } 2802 return -EINVAL; 2803 } 2804 2805 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2806 const struct ib_ud_wr *wr, 2807 void *wqe, unsigned *mlx_seg_len) 2808 { 2809 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2810 struct ib_device *ib_dev = &mdev->ib_dev; 2811 struct mlx4_wqe_mlx_seg *mlx = wqe; 2812 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2813 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2814 u16 pkey; 2815 u32 qkey; 2816 int send_size; 2817 int header_size; 2818 int spc; 2819 int i; 2820 2821 if (wr->wr.opcode != IB_WR_SEND) 2822 return -EINVAL; 2823 2824 send_size = 0; 2825 2826 for (i = 0; i < wr->wr.num_sge; ++i) 2827 send_size += wr->wr.sg_list[i].length; 2828 2829 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2830 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2831 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2832 send_size += sizeof (struct mlx4_ib_tunnel_header); 2833 2834 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2835 2836 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2837 sqp->ud_header.lrh.service_level = 2838 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2839 sqp->ud_header.lrh.destination_lid = 2840 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2841 sqp->ud_header.lrh.source_lid = 2842 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2843 } 2844 2845 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2846 2847 /* force loopback */ 2848 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2849 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2850 2851 sqp->ud_header.lrh.virtual_lane = 0; 2852 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2853 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2854 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2855 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2856 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2857 else 2858 sqp->ud_header.bth.destination_qpn = 2859 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel); 2860 2861 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2862 if (mlx4_is_master(mdev->dev)) { 2863 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2864 return -EINVAL; 2865 } else { 2866 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2867 return -EINVAL; 2868 } 2869 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2870 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2871 2872 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2873 sqp->ud_header.immediate_present = 0; 2874 2875 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2876 2877 /* 2878 * Inline data segments may not cross a 64 byte boundary. If 2879 * our UD header is bigger than the space available up to the 2880 * next 64 byte boundary in the WQE, use two inline data 2881 * segments to hold the UD header. 2882 */ 2883 spc = MLX4_INLINE_ALIGN - 2884 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2885 if (header_size <= spc) { 2886 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2887 memcpy(inl + 1, sqp->header_buf, header_size); 2888 i = 1; 2889 } else { 2890 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2891 memcpy(inl + 1, sqp->header_buf, spc); 2892 2893 inl = (void *) (inl + 1) + spc; 2894 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2895 /* 2896 * Need a barrier here to make sure all the data is 2897 * visible before the byte_count field is set. 2898 * Otherwise the HCA prefetcher could grab the 64-byte 2899 * chunk with this inline segment and get a valid (!= 2900 * 0xffffffff) byte count but stale data, and end up 2901 * generating a packet with bad headers. 2902 * 2903 * The first inline segment's byte_count field doesn't 2904 * need a barrier, because it comes after a 2905 * control/MLX segment and therefore is at an offset 2906 * of 16 mod 64. 2907 */ 2908 wmb(); 2909 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2910 i = 2; 2911 } 2912 2913 *mlx_seg_len = 2914 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2915 return 0; 2916 } 2917 2918 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2919 { 2920 union sl2vl_tbl_to_u64 tmp_vltab; 2921 u8 vl; 2922 2923 if (sl > 15) 2924 return 0xf; 2925 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2926 vl = tmp_vltab.sl8[sl >> 1]; 2927 if (sl & 1) 2928 vl &= 0x0f; 2929 else 2930 vl >>= 4; 2931 return vl; 2932 } 2933 2934 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2935 int index, union ib_gid *gid, 2936 enum ib_gid_type *gid_type) 2937 { 2938 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2939 struct mlx4_port_gid_table *port_gid_table; 2940 unsigned long flags; 2941 2942 port_gid_table = &iboe->gids[port_num - 1]; 2943 spin_lock_irqsave(&iboe->lock, flags); 2944 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 2945 *gid_type = port_gid_table->gids[index].gid_type; 2946 spin_unlock_irqrestore(&iboe->lock, flags); 2947 if (rdma_is_zero_gid(gid)) 2948 return -ENOENT; 2949 2950 return 0; 2951 } 2952 2953 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2954 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr, 2955 void *wqe, unsigned *mlx_seg_len) 2956 { 2957 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2958 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 2959 struct mlx4_wqe_mlx_seg *mlx = wqe; 2960 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2961 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2962 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2963 union ib_gid sgid; 2964 u16 pkey; 2965 int send_size; 2966 int header_size; 2967 int spc; 2968 int i; 2969 int err = 0; 2970 u16 vlan = 0xffff; 2971 bool is_eth; 2972 bool is_vlan = false; 2973 bool is_grh; 2974 bool is_udp = false; 2975 int ip_version = 0; 2976 2977 send_size = 0; 2978 for (i = 0; i < wr->wr.num_sge; ++i) 2979 send_size += wr->wr.sg_list[i].length; 2980 2981 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2982 is_grh = mlx4_ib_ah_grh_present(ah); 2983 if (is_eth) { 2984 enum ib_gid_type gid_type; 2985 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2986 /* When multi-function is enabled, the ib_core gid 2987 * indexes don't necessarily match the hw ones, so 2988 * we must use our own cache */ 2989 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2990 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2991 ah->av.ib.gid_index, &sgid.raw[0]); 2992 if (err) 2993 return err; 2994 } else { 2995 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 2996 ah->av.ib.gid_index, 2997 &sgid, &gid_type); 2998 if (!err) { 2999 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3000 if (is_udp) { 3001 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3002 ip_version = 4; 3003 else 3004 ip_version = 6; 3005 is_grh = false; 3006 } 3007 } else { 3008 return err; 3009 } 3010 } 3011 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3012 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3013 is_vlan = 1; 3014 } 3015 } 3016 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3017 ip_version, is_udp, 0, &sqp->ud_header); 3018 if (err) 3019 return err; 3020 3021 if (!is_eth) { 3022 sqp->ud_header.lrh.service_level = 3023 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3024 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3025 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3026 } 3027 3028 if (is_grh || (ip_version == 6)) { 3029 sqp->ud_header.grh.traffic_class = 3030 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3031 sqp->ud_header.grh.flow_label = 3032 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3033 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3034 if (is_eth) { 3035 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3036 } else { 3037 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3038 /* When multi-function is enabled, the ib_core gid 3039 * indexes don't necessarily match the hw ones, so 3040 * we must use our own cache 3041 */ 3042 sqp->ud_header.grh.source_gid.global.subnet_prefix = 3043 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 3044 demux[sqp->qp.port - 1]. 3045 subnet_prefix))); 3046 sqp->ud_header.grh.source_gid.global.interface_id = 3047 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 3048 guid_cache[ah->av.ib.gid_index]; 3049 } else { 3050 sqp->ud_header.grh.source_gid = 3051 ah->ibah.sgid_attr->gid; 3052 } 3053 } 3054 memcpy(sqp->ud_header.grh.destination_gid.raw, 3055 ah->av.ib.dgid, 16); 3056 } 3057 3058 if (ip_version == 4) { 3059 sqp->ud_header.ip4.tos = 3060 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3061 sqp->ud_header.ip4.id = 0; 3062 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3063 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3064 3065 memcpy(&sqp->ud_header.ip4.saddr, 3066 sgid.raw + 12, 4); 3067 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3068 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3069 } 3070 3071 if (is_udp) { 3072 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3073 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3074 sqp->ud_header.udp.csum = 0; 3075 } 3076 3077 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3078 3079 if (!is_eth) { 3080 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3081 (sqp->ud_header.lrh.destination_lid == 3082 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 3083 (sqp->ud_header.lrh.service_level << 8)); 3084 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3085 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3086 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3087 } 3088 3089 switch (wr->wr.opcode) { 3090 case IB_WR_SEND: 3091 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3092 sqp->ud_header.immediate_present = 0; 3093 break; 3094 case IB_WR_SEND_WITH_IMM: 3095 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3096 sqp->ud_header.immediate_present = 1; 3097 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3098 break; 3099 default: 3100 return -EINVAL; 3101 } 3102 3103 if (is_eth) { 3104 struct in6_addr in6; 3105 u16 ether_type; 3106 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3107 3108 ether_type = (!is_udp) ? ETH_P_IBOE: 3109 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3110 3111 mlx->sched_prio = cpu_to_be16(pcp); 3112 3113 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3114 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 3115 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3116 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3117 memcpy(&in6, sgid.raw, sizeof(in6)); 3118 3119 3120 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3121 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3122 if (!is_vlan) { 3123 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3124 } else { 3125 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3126 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3127 } 3128 } else { 3129 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 3130 sl_to_vl(to_mdev(ib_dev), 3131 sqp->ud_header.lrh.service_level, 3132 sqp->qp.port); 3133 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3134 return -EINVAL; 3135 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3136 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3137 } 3138 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3139 if (!sqp->qp.ibqp.qp_num) 3140 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 3141 else 3142 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 3143 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3144 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3145 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3146 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3147 sqp->qkey : wr->remote_qkey); 3148 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 3149 3150 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3151 3152 if (0) { 3153 pr_err("built UD header of size %d:\n", header_size); 3154 for (i = 0; i < header_size / 4; ++i) { 3155 if (i % 8 == 0) 3156 pr_err(" [%02x] ", i * 4); 3157 pr_cont(" %08x", 3158 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3159 if ((i + 1) % 8 == 0) 3160 pr_cont("\n"); 3161 } 3162 pr_err("\n"); 3163 } 3164 3165 /* 3166 * Inline data segments may not cross a 64 byte boundary. If 3167 * our UD header is bigger than the space available up to the 3168 * next 64 byte boundary in the WQE, use two inline data 3169 * segments to hold the UD header. 3170 */ 3171 spc = MLX4_INLINE_ALIGN - 3172 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3173 if (header_size <= spc) { 3174 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3175 memcpy(inl + 1, sqp->header_buf, header_size); 3176 i = 1; 3177 } else { 3178 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3179 memcpy(inl + 1, sqp->header_buf, spc); 3180 3181 inl = (void *) (inl + 1) + spc; 3182 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3183 /* 3184 * Need a barrier here to make sure all the data is 3185 * visible before the byte_count field is set. 3186 * Otherwise the HCA prefetcher could grab the 64-byte 3187 * chunk with this inline segment and get a valid (!= 3188 * 0xffffffff) byte count but stale data, and end up 3189 * generating a packet with bad headers. 3190 * 3191 * The first inline segment's byte_count field doesn't 3192 * need a barrier, because it comes after a 3193 * control/MLX segment and therefore is at an offset 3194 * of 16 mod 64. 3195 */ 3196 wmb(); 3197 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3198 i = 2; 3199 } 3200 3201 *mlx_seg_len = 3202 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3203 return 0; 3204 } 3205 3206 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3207 { 3208 unsigned cur; 3209 struct mlx4_ib_cq *cq; 3210 3211 cur = wq->head - wq->tail; 3212 if (likely(cur + nreq < wq->max_post)) 3213 return 0; 3214 3215 cq = to_mcq(ib_cq); 3216 spin_lock(&cq->lock); 3217 cur = wq->head - wq->tail; 3218 spin_unlock(&cq->lock); 3219 3220 return cur + nreq >= wq->max_post; 3221 } 3222 3223 static __be32 convert_access(int acc) 3224 { 3225 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3226 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3227 (acc & IB_ACCESS_REMOTE_WRITE ? 3228 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3229 (acc & IB_ACCESS_REMOTE_READ ? 3230 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3231 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3232 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3233 } 3234 3235 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3236 const struct ib_reg_wr *wr) 3237 { 3238 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3239 3240 fseg->flags = convert_access(wr->access); 3241 fseg->mem_key = cpu_to_be32(wr->key); 3242 fseg->buf_list = cpu_to_be64(mr->page_map); 3243 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3244 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3245 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3246 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3247 fseg->reserved[0] = 0; 3248 fseg->reserved[1] = 0; 3249 } 3250 3251 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3252 { 3253 memset(iseg, 0, sizeof(*iseg)); 3254 iseg->mem_key = cpu_to_be32(rkey); 3255 } 3256 3257 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3258 u64 remote_addr, u32 rkey) 3259 { 3260 rseg->raddr = cpu_to_be64(remote_addr); 3261 rseg->rkey = cpu_to_be32(rkey); 3262 rseg->reserved = 0; 3263 } 3264 3265 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3266 const struct ib_atomic_wr *wr) 3267 { 3268 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3269 aseg->swap_add = cpu_to_be64(wr->swap); 3270 aseg->compare = cpu_to_be64(wr->compare_add); 3271 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3272 aseg->swap_add = cpu_to_be64(wr->compare_add); 3273 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3274 } else { 3275 aseg->swap_add = cpu_to_be64(wr->compare_add); 3276 aseg->compare = 0; 3277 } 3278 3279 } 3280 3281 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3282 const struct ib_atomic_wr *wr) 3283 { 3284 aseg->swap_add = cpu_to_be64(wr->swap); 3285 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3286 aseg->compare = cpu_to_be64(wr->compare_add); 3287 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3288 } 3289 3290 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3291 const struct ib_ud_wr *wr) 3292 { 3293 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3294 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3295 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3296 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3297 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3298 } 3299 3300 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3301 struct mlx4_wqe_datagram_seg *dseg, 3302 const struct ib_ud_wr *wr, 3303 enum mlx4_ib_qp_type qpt) 3304 { 3305 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3306 struct mlx4_av sqp_av = {0}; 3307 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3308 3309 /* force loopback */ 3310 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3311 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3312 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3313 cpu_to_be32(0xf0000000); 3314 3315 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3316 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3317 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3318 else 3319 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3320 /* Use QKEY from the QP context, which is set by master */ 3321 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3322 } 3323 3324 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3325 unsigned *mlx_seg_len) 3326 { 3327 struct mlx4_wqe_inline_seg *inl = wqe; 3328 struct mlx4_ib_tunnel_header hdr; 3329 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3330 int spc; 3331 int i; 3332 3333 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3334 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3335 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3336 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3337 memcpy(hdr.mac, ah->av.eth.mac, 6); 3338 hdr.vlan = ah->av.eth.vlan; 3339 3340 spc = MLX4_INLINE_ALIGN - 3341 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3342 if (sizeof (hdr) <= spc) { 3343 memcpy(inl + 1, &hdr, sizeof (hdr)); 3344 wmb(); 3345 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3346 i = 1; 3347 } else { 3348 memcpy(inl + 1, &hdr, spc); 3349 wmb(); 3350 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3351 3352 inl = (void *) (inl + 1) + spc; 3353 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3354 wmb(); 3355 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3356 i = 2; 3357 } 3358 3359 *mlx_seg_len = 3360 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3361 } 3362 3363 static void set_mlx_icrc_seg(void *dseg) 3364 { 3365 u32 *t = dseg; 3366 struct mlx4_wqe_inline_seg *iseg = dseg; 3367 3368 t[1] = 0; 3369 3370 /* 3371 * Need a barrier here before writing the byte_count field to 3372 * make sure that all the data is visible before the 3373 * byte_count field is set. Otherwise, if the segment begins 3374 * a new cacheline, the HCA prefetcher could grab the 64-byte 3375 * chunk and get a valid (!= * 0xffffffff) byte count but 3376 * stale data, and end up sending the wrong data. 3377 */ 3378 wmb(); 3379 3380 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3381 } 3382 3383 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3384 { 3385 dseg->lkey = cpu_to_be32(sg->lkey); 3386 dseg->addr = cpu_to_be64(sg->addr); 3387 3388 /* 3389 * Need a barrier here before writing the byte_count field to 3390 * make sure that all the data is visible before the 3391 * byte_count field is set. Otherwise, if the segment begins 3392 * a new cacheline, the HCA prefetcher could grab the 64-byte 3393 * chunk and get a valid (!= * 0xffffffff) byte count but 3394 * stale data, and end up sending the wrong data. 3395 */ 3396 wmb(); 3397 3398 dseg->byte_count = cpu_to_be32(sg->length); 3399 } 3400 3401 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3402 { 3403 dseg->byte_count = cpu_to_be32(sg->length); 3404 dseg->lkey = cpu_to_be32(sg->lkey); 3405 dseg->addr = cpu_to_be64(sg->addr); 3406 } 3407 3408 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3409 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3410 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3411 { 3412 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3413 3414 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3415 *blh = cpu_to_be32(1 << 6); 3416 3417 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3418 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3419 return -EINVAL; 3420 3421 memcpy(wqe->header, wr->header, wr->hlen); 3422 3423 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3424 *lso_seg_len = halign; 3425 return 0; 3426 } 3427 3428 static __be32 send_ieth(const struct ib_send_wr *wr) 3429 { 3430 switch (wr->opcode) { 3431 case IB_WR_SEND_WITH_IMM: 3432 case IB_WR_RDMA_WRITE_WITH_IMM: 3433 return wr->ex.imm_data; 3434 3435 case IB_WR_SEND_WITH_INV: 3436 return cpu_to_be32(wr->ex.invalidate_rkey); 3437 3438 default: 3439 return 0; 3440 } 3441 } 3442 3443 static void add_zero_len_inline(void *wqe) 3444 { 3445 struct mlx4_wqe_inline_seg *inl = wqe; 3446 memset(wqe, 0, 16); 3447 inl->byte_count = cpu_to_be32(1 << 31); 3448 } 3449 3450 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3451 const struct ib_send_wr **bad_wr, bool drain) 3452 { 3453 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3454 void *wqe; 3455 struct mlx4_wqe_ctrl_seg *ctrl; 3456 struct mlx4_wqe_data_seg *dseg; 3457 unsigned long flags; 3458 int nreq; 3459 int err = 0; 3460 unsigned ind; 3461 int uninitialized_var(size); 3462 unsigned uninitialized_var(seglen); 3463 __be32 dummy; 3464 __be32 *lso_wqe; 3465 __be32 uninitialized_var(lso_hdr_sz); 3466 __be32 blh; 3467 int i; 3468 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3469 3470 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3471 struct mlx4_ib_sqp *sqp = to_msqp(qp); 3472 3473 if (sqp->roce_v2_gsi) { 3474 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3475 enum ib_gid_type gid_type; 3476 union ib_gid gid; 3477 3478 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 3479 ah->av.ib.gid_index, 3480 &gid, &gid_type)) 3481 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3482 to_mqp(sqp->roce_v2_gsi) : qp; 3483 else 3484 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3485 ah->av.ib.gid_index); 3486 } 3487 } 3488 3489 spin_lock_irqsave(&qp->sq.lock, flags); 3490 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3491 !drain) { 3492 err = -EIO; 3493 *bad_wr = wr; 3494 nreq = 0; 3495 goto out; 3496 } 3497 3498 ind = qp->sq_next_wqe; 3499 3500 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3501 lso_wqe = &dummy; 3502 blh = 0; 3503 3504 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3505 err = -ENOMEM; 3506 *bad_wr = wr; 3507 goto out; 3508 } 3509 3510 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3511 err = -EINVAL; 3512 *bad_wr = wr; 3513 goto out; 3514 } 3515 3516 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3517 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3518 3519 ctrl->srcrb_flags = 3520 (wr->send_flags & IB_SEND_SIGNALED ? 3521 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3522 (wr->send_flags & IB_SEND_SOLICITED ? 3523 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3524 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3525 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3526 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3527 qp->sq_signal_bits; 3528 3529 ctrl->imm = send_ieth(wr); 3530 3531 wqe += sizeof *ctrl; 3532 size = sizeof *ctrl / 16; 3533 3534 switch (qp->mlx4_ib_qp_type) { 3535 case MLX4_IB_QPT_RC: 3536 case MLX4_IB_QPT_UC: 3537 switch (wr->opcode) { 3538 case IB_WR_ATOMIC_CMP_AND_SWP: 3539 case IB_WR_ATOMIC_FETCH_AND_ADD: 3540 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3541 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3542 atomic_wr(wr)->rkey); 3543 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3544 3545 set_atomic_seg(wqe, atomic_wr(wr)); 3546 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3547 3548 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3549 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3550 3551 break; 3552 3553 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3554 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3555 atomic_wr(wr)->rkey); 3556 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3557 3558 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3559 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3560 3561 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3562 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3563 3564 break; 3565 3566 case IB_WR_RDMA_READ: 3567 case IB_WR_RDMA_WRITE: 3568 case IB_WR_RDMA_WRITE_WITH_IMM: 3569 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3570 rdma_wr(wr)->rkey); 3571 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3572 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3573 break; 3574 3575 case IB_WR_LOCAL_INV: 3576 ctrl->srcrb_flags |= 3577 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3578 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3579 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3580 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3581 break; 3582 3583 case IB_WR_REG_MR: 3584 ctrl->srcrb_flags |= 3585 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3586 set_reg_seg(wqe, reg_wr(wr)); 3587 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3588 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3589 break; 3590 3591 default: 3592 /* No extra segments required for sends */ 3593 break; 3594 } 3595 break; 3596 3597 case MLX4_IB_QPT_TUN_SMI_OWNER: 3598 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3599 ctrl, &seglen); 3600 if (unlikely(err)) { 3601 *bad_wr = wr; 3602 goto out; 3603 } 3604 wqe += seglen; 3605 size += seglen / 16; 3606 break; 3607 case MLX4_IB_QPT_TUN_SMI: 3608 case MLX4_IB_QPT_TUN_GSI: 3609 /* this is a UD qp used in MAD responses to slaves. */ 3610 set_datagram_seg(wqe, ud_wr(wr)); 3611 /* set the forced-loopback bit in the data seg av */ 3612 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3613 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3614 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3615 break; 3616 case MLX4_IB_QPT_UD: 3617 set_datagram_seg(wqe, ud_wr(wr)); 3618 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3619 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3620 3621 if (wr->opcode == IB_WR_LSO) { 3622 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3623 &lso_hdr_sz, &blh); 3624 if (unlikely(err)) { 3625 *bad_wr = wr; 3626 goto out; 3627 } 3628 lso_wqe = (__be32 *) wqe; 3629 wqe += seglen; 3630 size += seglen / 16; 3631 } 3632 break; 3633 3634 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3635 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3636 ctrl, &seglen); 3637 if (unlikely(err)) { 3638 *bad_wr = wr; 3639 goto out; 3640 } 3641 wqe += seglen; 3642 size += seglen / 16; 3643 /* to start tunnel header on a cache-line boundary */ 3644 add_zero_len_inline(wqe); 3645 wqe += 16; 3646 size++; 3647 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3648 wqe += seglen; 3649 size += seglen / 16; 3650 break; 3651 case MLX4_IB_QPT_PROXY_SMI: 3652 case MLX4_IB_QPT_PROXY_GSI: 3653 /* If we are tunneling special qps, this is a UD qp. 3654 * In this case we first add a UD segment targeting 3655 * the tunnel qp, and then add a header with address 3656 * information */ 3657 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3658 ud_wr(wr), 3659 qp->mlx4_ib_qp_type); 3660 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3661 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3662 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3663 wqe += seglen; 3664 size += seglen / 16; 3665 break; 3666 3667 case MLX4_IB_QPT_SMI: 3668 case MLX4_IB_QPT_GSI: 3669 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3670 &seglen); 3671 if (unlikely(err)) { 3672 *bad_wr = wr; 3673 goto out; 3674 } 3675 wqe += seglen; 3676 size += seglen / 16; 3677 break; 3678 3679 default: 3680 break; 3681 } 3682 3683 /* 3684 * Write data segments in reverse order, so as to 3685 * overwrite cacheline stamp last within each 3686 * cacheline. This avoids issues with WQE 3687 * prefetching. 3688 */ 3689 3690 dseg = wqe; 3691 dseg += wr->num_sge - 1; 3692 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3693 3694 /* Add one more inline data segment for ICRC for MLX sends */ 3695 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3696 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3697 qp->mlx4_ib_qp_type & 3698 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3699 set_mlx_icrc_seg(dseg + 1); 3700 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3701 } 3702 3703 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3704 set_data_seg(dseg, wr->sg_list + i); 3705 3706 /* 3707 * Possibly overwrite stamping in cacheline with LSO 3708 * segment only after making sure all data segments 3709 * are written. 3710 */ 3711 wmb(); 3712 *lso_wqe = lso_hdr_sz; 3713 3714 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3715 MLX4_WQE_CTRL_FENCE : 0) | size; 3716 3717 /* 3718 * Make sure descriptor is fully written before 3719 * setting ownership bit (because HW can start 3720 * executing as soon as we do). 3721 */ 3722 wmb(); 3723 3724 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3725 *bad_wr = wr; 3726 err = -EINVAL; 3727 goto out; 3728 } 3729 3730 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3731 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3732 3733 /* 3734 * We can improve latency by not stamping the last 3735 * send queue WQE until after ringing the doorbell, so 3736 * only stamp here if there are still more WQEs to post. 3737 */ 3738 if (wr->next) 3739 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3740 ind++; 3741 } 3742 3743 out: 3744 if (likely(nreq)) { 3745 qp->sq.head += nreq; 3746 3747 /* 3748 * Make sure that descriptors are written before 3749 * doorbell record. 3750 */ 3751 wmb(); 3752 3753 writel_relaxed(qp->doorbell_qpn, 3754 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3755 3756 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3757 3758 qp->sq_next_wqe = ind; 3759 } 3760 3761 spin_unlock_irqrestore(&qp->sq.lock, flags); 3762 3763 return err; 3764 } 3765 3766 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3767 const struct ib_send_wr **bad_wr) 3768 { 3769 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3770 } 3771 3772 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3773 const struct ib_recv_wr **bad_wr, bool drain) 3774 { 3775 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3776 struct mlx4_wqe_data_seg *scat; 3777 unsigned long flags; 3778 int err = 0; 3779 int nreq; 3780 int ind; 3781 int max_gs; 3782 int i; 3783 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3784 3785 max_gs = qp->rq.max_gs; 3786 spin_lock_irqsave(&qp->rq.lock, flags); 3787 3788 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3789 !drain) { 3790 err = -EIO; 3791 *bad_wr = wr; 3792 nreq = 0; 3793 goto out; 3794 } 3795 3796 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3797 3798 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3799 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3800 err = -ENOMEM; 3801 *bad_wr = wr; 3802 goto out; 3803 } 3804 3805 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3806 err = -EINVAL; 3807 *bad_wr = wr; 3808 goto out; 3809 } 3810 3811 scat = get_recv_wqe(qp, ind); 3812 3813 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3814 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3815 ib_dma_sync_single_for_device(ibqp->device, 3816 qp->sqp_proxy_rcv[ind].map, 3817 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3818 DMA_FROM_DEVICE); 3819 scat->byte_count = 3820 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3821 /* use dma lkey from upper layer entry */ 3822 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3823 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3824 scat++; 3825 max_gs--; 3826 } 3827 3828 for (i = 0; i < wr->num_sge; ++i) 3829 __set_data_seg(scat + i, wr->sg_list + i); 3830 3831 if (i < max_gs) { 3832 scat[i].byte_count = 0; 3833 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3834 scat[i].addr = 0; 3835 } 3836 3837 qp->rq.wrid[ind] = wr->wr_id; 3838 3839 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3840 } 3841 3842 out: 3843 if (likely(nreq)) { 3844 qp->rq.head += nreq; 3845 3846 /* 3847 * Make sure that descriptors are written before 3848 * doorbell record. 3849 */ 3850 wmb(); 3851 3852 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3853 } 3854 3855 spin_unlock_irqrestore(&qp->rq.lock, flags); 3856 3857 return err; 3858 } 3859 3860 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3861 const struct ib_recv_wr **bad_wr) 3862 { 3863 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3864 } 3865 3866 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3867 { 3868 switch (mlx4_state) { 3869 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3870 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3871 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3872 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3873 case MLX4_QP_STATE_SQ_DRAINING: 3874 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3875 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3876 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3877 default: return -1; 3878 } 3879 } 3880 3881 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3882 { 3883 switch (mlx4_mig_state) { 3884 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3885 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3886 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3887 default: return -1; 3888 } 3889 } 3890 3891 static int to_ib_qp_access_flags(int mlx4_flags) 3892 { 3893 int ib_flags = 0; 3894 3895 if (mlx4_flags & MLX4_QP_BIT_RRE) 3896 ib_flags |= IB_ACCESS_REMOTE_READ; 3897 if (mlx4_flags & MLX4_QP_BIT_RWE) 3898 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3899 if (mlx4_flags & MLX4_QP_BIT_RAE) 3900 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3901 3902 return ib_flags; 3903 } 3904 3905 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3906 struct rdma_ah_attr *ah_attr, 3907 struct mlx4_qp_path *path) 3908 { 3909 struct mlx4_dev *dev = ibdev->dev; 3910 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3911 3912 memset(ah_attr, 0, sizeof(*ah_attr)); 3913 if (port_num == 0 || port_num > dev->caps.num_ports) 3914 return; 3915 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3916 3917 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3918 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3919 ((path->sched_queue & 4) << 1)); 3920 else 3921 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3922 rdma_ah_set_port_num(ah_attr, port_num); 3923 3924 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3925 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3926 rdma_ah_set_static_rate(ah_attr, 3927 path->static_rate ? path->static_rate - 5 : 0); 3928 if (path->grh_mylmc & (1 << 7)) { 3929 rdma_ah_set_grh(ah_attr, NULL, 3930 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3931 path->mgid_index, 3932 path->hop_limit, 3933 (be32_to_cpu(path->tclass_flowlabel) 3934 >> 20) & 0xff); 3935 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 3936 } 3937 } 3938 3939 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3940 struct ib_qp_init_attr *qp_init_attr) 3941 { 3942 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3943 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3944 struct mlx4_qp_context context; 3945 int mlx4_state; 3946 int err = 0; 3947 3948 if (ibqp->rwq_ind_tbl) 3949 return -EOPNOTSUPP; 3950 3951 mutex_lock(&qp->mutex); 3952 3953 if (qp->state == IB_QPS_RESET) { 3954 qp_attr->qp_state = IB_QPS_RESET; 3955 goto done; 3956 } 3957 3958 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3959 if (err) { 3960 err = -EINVAL; 3961 goto out; 3962 } 3963 3964 mlx4_state = be32_to_cpu(context.flags) >> 28; 3965 3966 qp->state = to_ib_qp_state(mlx4_state); 3967 qp_attr->qp_state = qp->state; 3968 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3969 qp_attr->path_mig_state = 3970 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3971 qp_attr->qkey = be32_to_cpu(context.qkey); 3972 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3973 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3974 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3975 qp_attr->qp_access_flags = 3976 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3977 3978 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3979 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3980 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3981 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3982 qp_attr->alt_port_num = 3983 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 3984 } 3985 3986 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3987 if (qp_attr->qp_state == IB_QPS_INIT) 3988 qp_attr->port_num = qp->port; 3989 else 3990 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3991 3992 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3993 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3994 3995 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3996 3997 qp_attr->max_dest_rd_atomic = 3998 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3999 qp_attr->min_rnr_timer = 4000 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4001 qp_attr->timeout = context.pri_path.ackto >> 3; 4002 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4003 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4004 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4005 4006 done: 4007 qp_attr->cur_qp_state = qp_attr->qp_state; 4008 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4009 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4010 4011 if (!ibqp->uobject) { 4012 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4013 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4014 } else { 4015 qp_attr->cap.max_send_wr = 0; 4016 qp_attr->cap.max_send_sge = 0; 4017 } 4018 4019 /* 4020 * We don't support inline sends for kernel QPs (yet), and we 4021 * don't know what userspace's value should be. 4022 */ 4023 qp_attr->cap.max_inline_data = 0; 4024 4025 qp_init_attr->cap = qp_attr->cap; 4026 4027 qp_init_attr->create_flags = 0; 4028 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4029 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4030 4031 if (qp->flags & MLX4_IB_QP_LSO) 4032 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4033 4034 if (qp->flags & MLX4_IB_QP_NETIF) 4035 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4036 4037 qp_init_attr->sq_sig_type = 4038 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4039 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4040 4041 out: 4042 mutex_unlock(&qp->mutex); 4043 return err; 4044 } 4045 4046 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4047 struct ib_wq_init_attr *init_attr, 4048 struct ib_udata *udata) 4049 { 4050 struct mlx4_ib_dev *dev; 4051 struct ib_qp_init_attr ib_qp_init_attr; 4052 struct mlx4_ib_qp *qp; 4053 struct mlx4_ib_create_wq ucmd; 4054 int err, required_cmd_sz; 4055 4056 if (!udata) 4057 return ERR_PTR(-EINVAL); 4058 4059 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4060 sizeof(ucmd.comp_mask); 4061 if (udata->inlen < required_cmd_sz) { 4062 pr_debug("invalid inlen\n"); 4063 return ERR_PTR(-EINVAL); 4064 } 4065 4066 if (udata->inlen > sizeof(ucmd) && 4067 !ib_is_udata_cleared(udata, sizeof(ucmd), 4068 udata->inlen - sizeof(ucmd))) { 4069 pr_debug("inlen is not supported\n"); 4070 return ERR_PTR(-EOPNOTSUPP); 4071 } 4072 4073 if (udata->outlen) 4074 return ERR_PTR(-EOPNOTSUPP); 4075 4076 dev = to_mdev(pd->device); 4077 4078 if (init_attr->wq_type != IB_WQT_RQ) { 4079 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4080 return ERR_PTR(-EOPNOTSUPP); 4081 } 4082 4083 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) { 4084 pr_debug("unsupported create_flags %u\n", 4085 init_attr->create_flags); 4086 return ERR_PTR(-EOPNOTSUPP); 4087 } 4088 4089 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4090 if (!qp) 4091 return ERR_PTR(-ENOMEM); 4092 4093 qp->pri.vid = 0xFFFF; 4094 qp->alt.vid = 0xFFFF; 4095 4096 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr)); 4097 ib_qp_init_attr.qp_context = init_attr->wq_context; 4098 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4099 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4100 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4101 ib_qp_init_attr.recv_cq = init_attr->cq; 4102 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4103 4104 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4105 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4106 4107 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr, 4108 udata, 0, &qp); 4109 if (err) { 4110 kfree(qp); 4111 return ERR_PTR(err); 4112 } 4113 4114 qp->ibwq.event_handler = init_attr->event_handler; 4115 qp->ibwq.wq_num = qp->mqp.qpn; 4116 qp->ibwq.state = IB_WQS_RESET; 4117 4118 return &qp->ibwq; 4119 } 4120 4121 static int ib_wq2qp_state(enum ib_wq_state state) 4122 { 4123 switch (state) { 4124 case IB_WQS_RESET: 4125 return IB_QPS_RESET; 4126 case IB_WQS_RDY: 4127 return IB_QPS_RTR; 4128 default: 4129 return IB_QPS_ERR; 4130 } 4131 } 4132 4133 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 4134 struct ib_udata *udata) 4135 { 4136 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4137 enum ib_qp_state qp_cur_state; 4138 enum ib_qp_state qp_new_state; 4139 int attr_mask; 4140 int err; 4141 4142 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4143 * the WQ logic state. 4144 */ 4145 qp_cur_state = qp->state; 4146 qp_new_state = ib_wq2qp_state(new_state); 4147 4148 if (ib_wq2qp_state(new_state) == qp_cur_state) 4149 return 0; 4150 4151 if (new_state == IB_WQS_RDY) { 4152 struct ib_qp_attr attr = {}; 4153 4154 attr.port_num = qp->port; 4155 attr_mask = IB_QP_PORT; 4156 4157 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4158 attr_mask, IB_QPS_RESET, IB_QPS_INIT, 4159 udata); 4160 if (err) { 4161 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4162 ibwq->wq_num); 4163 return err; 4164 } 4165 4166 qp_cur_state = IB_QPS_INIT; 4167 } 4168 4169 attr_mask = 0; 4170 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4171 qp_cur_state, qp_new_state, udata); 4172 4173 if (err && (qp_cur_state == IB_QPS_INIT)) { 4174 qp_new_state = IB_QPS_RESET; 4175 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4176 attr_mask, IB_QPS_INIT, IB_QPS_RESET, 4177 udata)) { 4178 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4179 ibwq->wq_num); 4180 qp_new_state = IB_QPS_INIT; 4181 } 4182 } 4183 4184 qp->state = qp_new_state; 4185 4186 return err; 4187 } 4188 4189 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4190 u32 wq_attr_mask, struct ib_udata *udata) 4191 { 4192 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4193 struct mlx4_ib_modify_wq ucmd = {}; 4194 size_t required_cmd_sz; 4195 enum ib_wq_state cur_state, new_state; 4196 int err = 0; 4197 4198 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4199 sizeof(ucmd.reserved); 4200 if (udata->inlen < required_cmd_sz) 4201 return -EINVAL; 4202 4203 if (udata->inlen > sizeof(ucmd) && 4204 !ib_is_udata_cleared(udata, sizeof(ucmd), 4205 udata->inlen - sizeof(ucmd))) 4206 return -EOPNOTSUPP; 4207 4208 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4209 return -EFAULT; 4210 4211 if (ucmd.comp_mask || ucmd.reserved) 4212 return -EOPNOTSUPP; 4213 4214 if (wq_attr_mask & IB_WQ_FLAGS) 4215 return -EOPNOTSUPP; 4216 4217 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state : 4218 ibwq->state; 4219 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state; 4220 4221 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR || 4222 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR) 4223 return -EINVAL; 4224 4225 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4226 return -EINVAL; 4227 4228 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4229 return -EINVAL; 4230 4231 /* Need to protect against the parent RSS which also may modify WQ 4232 * state. 4233 */ 4234 mutex_lock(&qp->mutex); 4235 4236 /* Can update HW state only if a RSS QP has already associated to this 4237 * WQ, so we can apply its port on the WQ. 4238 */ 4239 if (qp->rss_usecnt) 4240 err = _mlx4_ib_modify_wq(ibwq, new_state, udata); 4241 4242 if (!err) 4243 ibwq->state = new_state; 4244 4245 mutex_unlock(&qp->mutex); 4246 4247 return err; 4248 } 4249 4250 void mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata) 4251 { 4252 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4253 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4254 4255 if (qp->counter_index) 4256 mlx4_ib_free_qp_counter(dev, qp); 4257 4258 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata); 4259 4260 kfree(qp); 4261 } 4262 4263 struct ib_rwq_ind_table 4264 *mlx4_ib_create_rwq_ind_table(struct ib_device *device, 4265 struct ib_rwq_ind_table_init_attr *init_attr, 4266 struct ib_udata *udata) 4267 { 4268 struct ib_rwq_ind_table *rwq_ind_table; 4269 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4270 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4271 unsigned int base_wqn; 4272 size_t min_resp_len; 4273 int i; 4274 int err; 4275 4276 if (udata->inlen > 0 && 4277 !ib_is_udata_cleared(udata, 0, 4278 udata->inlen)) 4279 return ERR_PTR(-EOPNOTSUPP); 4280 4281 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4282 if (udata->outlen && udata->outlen < min_resp_len) 4283 return ERR_PTR(-EINVAL); 4284 4285 if (ind_tbl_size > 4286 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4287 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4288 ind_tbl_size, 4289 device->attrs.rss_caps.max_rwq_indirection_table_size); 4290 return ERR_PTR(-EINVAL); 4291 } 4292 4293 base_wqn = init_attr->ind_tbl[0]->wq_num; 4294 4295 if (base_wqn % ind_tbl_size) { 4296 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4297 base_wqn); 4298 return ERR_PTR(-EINVAL); 4299 } 4300 4301 for (i = 1; i < ind_tbl_size; i++) { 4302 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4303 pr_debug("indirection table's WQNs aren't consecutive\n"); 4304 return ERR_PTR(-EINVAL); 4305 } 4306 } 4307 4308 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL); 4309 if (!rwq_ind_table) 4310 return ERR_PTR(-ENOMEM); 4311 4312 if (udata->outlen) { 4313 resp.response_length = offsetof(typeof(resp), response_length) + 4314 sizeof(resp.response_length); 4315 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4316 if (err) 4317 goto err; 4318 } 4319 4320 return rwq_ind_table; 4321 4322 err: 4323 kfree(rwq_ind_table); 4324 return ERR_PTR(err); 4325 } 4326 4327 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4328 { 4329 kfree(ib_rwq_ind_tbl); 4330 return 0; 4331 } 4332 4333 struct mlx4_ib_drain_cqe { 4334 struct ib_cqe cqe; 4335 struct completion done; 4336 }; 4337 4338 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4339 { 4340 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4341 struct mlx4_ib_drain_cqe, 4342 cqe); 4343 4344 complete(&cqe->done); 4345 } 4346 4347 /* This function returns only once the drained WR was completed */ 4348 static void handle_drain_completion(struct ib_cq *cq, 4349 struct mlx4_ib_drain_cqe *sdrain, 4350 struct mlx4_ib_dev *dev) 4351 { 4352 struct mlx4_dev *mdev = dev->dev; 4353 4354 if (cq->poll_ctx == IB_POLL_DIRECT) { 4355 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4356 ib_process_cq_direct(cq, -1); 4357 return; 4358 } 4359 4360 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4361 struct mlx4_ib_cq *mcq = to_mcq(cq); 4362 bool triggered = false; 4363 unsigned long flags; 4364 4365 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4366 /* Make sure that the CQ handler won't run if wasn't run yet */ 4367 if (!mcq->mcq.reset_notify_added) 4368 mcq->mcq.reset_notify_added = 1; 4369 else 4370 triggered = true; 4371 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4372 4373 if (triggered) { 4374 /* Wait for any scheduled/running task to be ended */ 4375 switch (cq->poll_ctx) { 4376 case IB_POLL_SOFTIRQ: 4377 irq_poll_disable(&cq->iop); 4378 irq_poll_enable(&cq->iop); 4379 break; 4380 case IB_POLL_WORKQUEUE: 4381 cancel_work_sync(&cq->work); 4382 break; 4383 default: 4384 WARN_ON_ONCE(1); 4385 } 4386 } 4387 4388 /* Run the CQ handler - this makes sure that the drain WR will 4389 * be processed if wasn't processed yet. 4390 */ 4391 mcq->mcq.comp(&mcq->mcq); 4392 } 4393 4394 wait_for_completion(&sdrain->done); 4395 } 4396 4397 void mlx4_ib_drain_sq(struct ib_qp *qp) 4398 { 4399 struct ib_cq *cq = qp->send_cq; 4400 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4401 struct mlx4_ib_drain_cqe sdrain; 4402 const struct ib_send_wr *bad_swr; 4403 struct ib_rdma_wr swr = { 4404 .wr = { 4405 .next = NULL, 4406 { .wr_cqe = &sdrain.cqe, }, 4407 .opcode = IB_WR_RDMA_WRITE, 4408 }, 4409 }; 4410 int ret; 4411 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4412 struct mlx4_dev *mdev = dev->dev; 4413 4414 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4415 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4416 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4417 return; 4418 } 4419 4420 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4421 init_completion(&sdrain.done); 4422 4423 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4424 if (ret) { 4425 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4426 return; 4427 } 4428 4429 handle_drain_completion(cq, &sdrain, dev); 4430 } 4431 4432 void mlx4_ib_drain_rq(struct ib_qp *qp) 4433 { 4434 struct ib_cq *cq = qp->recv_cq; 4435 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4436 struct mlx4_ib_drain_cqe rdrain; 4437 struct ib_recv_wr rwr = {}; 4438 const struct ib_recv_wr *bad_rwr; 4439 int ret; 4440 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4441 struct mlx4_dev *mdev = dev->dev; 4442 4443 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4444 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4445 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4446 return; 4447 } 4448 4449 rwr.wr_cqe = &rdrain.cqe; 4450 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4451 init_completion(&rdrain.done); 4452 4453 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4454 if (ret) { 4455 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4456 return; 4457 } 4458 4459 handle_drain_completion(cq, &rdrain, dev); 4460 } 4461