xref: /openbmc/linux/drivers/infiniband/hw/mlx4/qp.c (revision abfbd895)
1 /*
2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 
34 #include <linux/log2.h>
35 #include <linux/slab.h>
36 #include <linux/netdevice.h>
37 #include <linux/vmalloc.h>
38 
39 #include <rdma/ib_cache.h>
40 #include <rdma/ib_pack.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_mad.h>
43 
44 #include <linux/mlx4/driver.h>
45 #include <linux/mlx4/qp.h>
46 
47 #include "mlx4_ib.h"
48 #include "user.h"
49 
50 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
51 			     struct mlx4_ib_cq *recv_cq);
52 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
53 			       struct mlx4_ib_cq *recv_cq);
54 
55 enum {
56 	MLX4_IB_ACK_REQ_FREQ	= 8,
57 };
58 
59 enum {
60 	MLX4_IB_DEFAULT_SCHED_QUEUE	= 0x83,
61 	MLX4_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
62 	MLX4_IB_LINK_TYPE_IB		= 0,
63 	MLX4_IB_LINK_TYPE_ETH		= 1
64 };
65 
66 enum {
67 	/*
68 	 * Largest possible UD header: send with GRH and immediate
69 	 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
70 	 * tag.  (LRH would only use 8 bytes, so Ethernet is the
71 	 * biggest case)
72 	 */
73 	MLX4_IB_UD_HEADER_SIZE		= 82,
74 	MLX4_IB_LSO_HEADER_SPARE	= 128,
75 };
76 
77 enum {
78 	MLX4_IB_IBOE_ETHERTYPE		= 0x8915
79 };
80 
81 struct mlx4_ib_sqp {
82 	struct mlx4_ib_qp	qp;
83 	int			pkey_index;
84 	u32			qkey;
85 	u32			send_psn;
86 	struct ib_ud_header	ud_header;
87 	u8			header_buf[MLX4_IB_UD_HEADER_SIZE];
88 };
89 
90 enum {
91 	MLX4_IB_MIN_SQ_STRIDE	= 6,
92 	MLX4_IB_CACHE_LINE_SIZE	= 64,
93 };
94 
95 enum {
96 	MLX4_RAW_QP_MTU		= 7,
97 	MLX4_RAW_QP_MSGMAX	= 31,
98 };
99 
100 #ifndef ETH_ALEN
101 #define ETH_ALEN        6
102 #endif
103 
104 static const __be32 mlx4_ib_opcode[] = {
105 	[IB_WR_SEND]				= cpu_to_be32(MLX4_OPCODE_SEND),
106 	[IB_WR_LSO]				= cpu_to_be32(MLX4_OPCODE_LSO),
107 	[IB_WR_SEND_WITH_IMM]			= cpu_to_be32(MLX4_OPCODE_SEND_IMM),
108 	[IB_WR_RDMA_WRITE]			= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
109 	[IB_WR_RDMA_WRITE_WITH_IMM]		= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
110 	[IB_WR_RDMA_READ]			= cpu_to_be32(MLX4_OPCODE_RDMA_READ),
111 	[IB_WR_ATOMIC_CMP_AND_SWP]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
112 	[IB_WR_ATOMIC_FETCH_AND_ADD]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
113 	[IB_WR_SEND_WITH_INV]			= cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
114 	[IB_WR_LOCAL_INV]			= cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
115 	[IB_WR_REG_MR]				= cpu_to_be32(MLX4_OPCODE_FMR),
116 	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
117 	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
118 	[IB_WR_BIND_MW]				= cpu_to_be32(MLX4_OPCODE_BIND_MW),
119 };
120 
121 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
122 {
123 	return container_of(mqp, struct mlx4_ib_sqp, qp);
124 }
125 
126 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
127 {
128 	if (!mlx4_is_master(dev->dev))
129 		return 0;
130 
131 	return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
132 	       qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
133 		8 * MLX4_MFUNC_MAX;
134 }
135 
136 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
137 {
138 	int proxy_sqp = 0;
139 	int real_sqp = 0;
140 	int i;
141 	/* PPF or Native -- real SQP */
142 	real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
143 		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
144 		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
145 	if (real_sqp)
146 		return 1;
147 	/* VF or PF -- proxy SQP */
148 	if (mlx4_is_mfunc(dev->dev)) {
149 		for (i = 0; i < dev->dev->caps.num_ports; i++) {
150 			if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
151 			    qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
152 				proxy_sqp = 1;
153 				break;
154 			}
155 		}
156 	}
157 	return proxy_sqp;
158 }
159 
160 /* used for INIT/CLOSE port logic */
161 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
162 {
163 	int proxy_qp0 = 0;
164 	int real_qp0 = 0;
165 	int i;
166 	/* PPF or Native -- real QP0 */
167 	real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
168 		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
169 		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
170 	if (real_qp0)
171 		return 1;
172 	/* VF or PF -- proxy QP0 */
173 	if (mlx4_is_mfunc(dev->dev)) {
174 		for (i = 0; i < dev->dev->caps.num_ports; i++) {
175 			if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
176 				proxy_qp0 = 1;
177 				break;
178 			}
179 		}
180 	}
181 	return proxy_qp0;
182 }
183 
184 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
185 {
186 	return mlx4_buf_offset(&qp->buf, offset);
187 }
188 
189 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
190 {
191 	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
192 }
193 
194 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
195 {
196 	return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
197 }
198 
199 /*
200  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
201  * first four bytes of every 64 byte chunk with
202  *     0x7FFFFFF | (invalid_ownership_value << 31).
203  *
204  * When the max work request size is less than or equal to the WQE
205  * basic block size, as an optimization, we can stamp all WQEs with
206  * 0xffffffff, and skip the very first chunk of each WQE.
207  */
208 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
209 {
210 	__be32 *wqe;
211 	int i;
212 	int s;
213 	int ind;
214 	void *buf;
215 	__be32 stamp;
216 	struct mlx4_wqe_ctrl_seg *ctrl;
217 
218 	if (qp->sq_max_wqes_per_wr > 1) {
219 		s = roundup(size, 1U << qp->sq.wqe_shift);
220 		for (i = 0; i < s; i += 64) {
221 			ind = (i >> qp->sq.wqe_shift) + n;
222 			stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
223 						       cpu_to_be32(0xffffffff);
224 			buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
225 			wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
226 			*wqe = stamp;
227 		}
228 	} else {
229 		ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
230 		s = (ctrl->fence_size & 0x3f) << 4;
231 		for (i = 64; i < s; i += 64) {
232 			wqe = buf + i;
233 			*wqe = cpu_to_be32(0xffffffff);
234 		}
235 	}
236 }
237 
238 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
239 {
240 	struct mlx4_wqe_ctrl_seg *ctrl;
241 	struct mlx4_wqe_inline_seg *inl;
242 	void *wqe;
243 	int s;
244 
245 	ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
246 	s = sizeof(struct mlx4_wqe_ctrl_seg);
247 
248 	if (qp->ibqp.qp_type == IB_QPT_UD) {
249 		struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
250 		struct mlx4_av *av = (struct mlx4_av *)dgram->av;
251 		memset(dgram, 0, sizeof *dgram);
252 		av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
253 		s += sizeof(struct mlx4_wqe_datagram_seg);
254 	}
255 
256 	/* Pad the remainder of the WQE with an inline data segment. */
257 	if (size > s) {
258 		inl = wqe + s;
259 		inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
260 	}
261 	ctrl->srcrb_flags = 0;
262 	ctrl->fence_size = size / 16;
263 	/*
264 	 * Make sure descriptor is fully written before setting ownership bit
265 	 * (because HW can start executing as soon as we do).
266 	 */
267 	wmb();
268 
269 	ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
270 		(n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
271 
272 	stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
273 }
274 
275 /* Post NOP WQE to prevent wrap-around in the middle of WR */
276 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
277 {
278 	unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
279 	if (unlikely(s < qp->sq_max_wqes_per_wr)) {
280 		post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
281 		ind += s;
282 	}
283 	return ind;
284 }
285 
286 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
287 {
288 	struct ib_event event;
289 	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
290 
291 	if (type == MLX4_EVENT_TYPE_PATH_MIG)
292 		to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
293 
294 	if (ibqp->event_handler) {
295 		event.device     = ibqp->device;
296 		event.element.qp = ibqp;
297 		switch (type) {
298 		case MLX4_EVENT_TYPE_PATH_MIG:
299 			event.event = IB_EVENT_PATH_MIG;
300 			break;
301 		case MLX4_EVENT_TYPE_COMM_EST:
302 			event.event = IB_EVENT_COMM_EST;
303 			break;
304 		case MLX4_EVENT_TYPE_SQ_DRAINED:
305 			event.event = IB_EVENT_SQ_DRAINED;
306 			break;
307 		case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
308 			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
309 			break;
310 		case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
311 			event.event = IB_EVENT_QP_FATAL;
312 			break;
313 		case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
314 			event.event = IB_EVENT_PATH_MIG_ERR;
315 			break;
316 		case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
317 			event.event = IB_EVENT_QP_REQ_ERR;
318 			break;
319 		case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
320 			event.event = IB_EVENT_QP_ACCESS_ERR;
321 			break;
322 		default:
323 			pr_warn("Unexpected event type %d "
324 			       "on QP %06x\n", type, qp->qpn);
325 			return;
326 		}
327 
328 		ibqp->event_handler(&event, ibqp->qp_context);
329 	}
330 }
331 
332 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
333 {
334 	/*
335 	 * UD WQEs must have a datagram segment.
336 	 * RC and UC WQEs might have a remote address segment.
337 	 * MLX WQEs need two extra inline data segments (for the UD
338 	 * header and space for the ICRC).
339 	 */
340 	switch (type) {
341 	case MLX4_IB_QPT_UD:
342 		return sizeof (struct mlx4_wqe_ctrl_seg) +
343 			sizeof (struct mlx4_wqe_datagram_seg) +
344 			((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
345 	case MLX4_IB_QPT_PROXY_SMI_OWNER:
346 	case MLX4_IB_QPT_PROXY_SMI:
347 	case MLX4_IB_QPT_PROXY_GSI:
348 		return sizeof (struct mlx4_wqe_ctrl_seg) +
349 			sizeof (struct mlx4_wqe_datagram_seg) + 64;
350 	case MLX4_IB_QPT_TUN_SMI_OWNER:
351 	case MLX4_IB_QPT_TUN_GSI:
352 		return sizeof (struct mlx4_wqe_ctrl_seg) +
353 			sizeof (struct mlx4_wqe_datagram_seg);
354 
355 	case MLX4_IB_QPT_UC:
356 		return sizeof (struct mlx4_wqe_ctrl_seg) +
357 			sizeof (struct mlx4_wqe_raddr_seg);
358 	case MLX4_IB_QPT_RC:
359 		return sizeof (struct mlx4_wqe_ctrl_seg) +
360 			sizeof (struct mlx4_wqe_atomic_seg) +
361 			sizeof (struct mlx4_wqe_raddr_seg);
362 	case MLX4_IB_QPT_SMI:
363 	case MLX4_IB_QPT_GSI:
364 		return sizeof (struct mlx4_wqe_ctrl_seg) +
365 			ALIGN(MLX4_IB_UD_HEADER_SIZE +
366 			      DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
367 					   MLX4_INLINE_ALIGN) *
368 			      sizeof (struct mlx4_wqe_inline_seg),
369 			      sizeof (struct mlx4_wqe_data_seg)) +
370 			ALIGN(4 +
371 			      sizeof (struct mlx4_wqe_inline_seg),
372 			      sizeof (struct mlx4_wqe_data_seg));
373 	default:
374 		return sizeof (struct mlx4_wqe_ctrl_seg);
375 	}
376 }
377 
378 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
379 		       int is_user, int has_rq, struct mlx4_ib_qp *qp)
380 {
381 	/* Sanity check RQ size before proceeding */
382 	if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
383 	    cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
384 		return -EINVAL;
385 
386 	if (!has_rq) {
387 		if (cap->max_recv_wr)
388 			return -EINVAL;
389 
390 		qp->rq.wqe_cnt = qp->rq.max_gs = 0;
391 	} else {
392 		/* HW requires >= 1 RQ entry with >= 1 gather entry */
393 		if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
394 			return -EINVAL;
395 
396 		qp->rq.wqe_cnt	 = roundup_pow_of_two(max(1U, cap->max_recv_wr));
397 		qp->rq.max_gs	 = roundup_pow_of_two(max(1U, cap->max_recv_sge));
398 		qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
399 	}
400 
401 	/* leave userspace return values as they were, so as not to break ABI */
402 	if (is_user) {
403 		cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
404 		cap->max_recv_sge = qp->rq.max_gs;
405 	} else {
406 		cap->max_recv_wr  = qp->rq.max_post =
407 			min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
408 		cap->max_recv_sge = min(qp->rq.max_gs,
409 					min(dev->dev->caps.max_sq_sg,
410 					    dev->dev->caps.max_rq_sg));
411 	}
412 
413 	return 0;
414 }
415 
416 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
417 			      enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
418 {
419 	int s;
420 
421 	/* Sanity check SQ size before proceeding */
422 	if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
423 	    cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
424 	    cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
425 	    sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
426 		return -EINVAL;
427 
428 	/*
429 	 * For MLX transport we need 2 extra S/G entries:
430 	 * one for the header and one for the checksum at the end
431 	 */
432 	if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
433 	     type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
434 	    cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
435 		return -EINVAL;
436 
437 	s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
438 		cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
439 		send_wqe_overhead(type, qp->flags);
440 
441 	if (s > dev->dev->caps.max_sq_desc_sz)
442 		return -EINVAL;
443 
444 	/*
445 	 * Hermon supports shrinking WQEs, such that a single work
446 	 * request can include multiple units of 1 << wqe_shift.  This
447 	 * way, work requests can differ in size, and do not have to
448 	 * be a power of 2 in size, saving memory and speeding up send
449 	 * WR posting.  Unfortunately, if we do this then the
450 	 * wqe_index field in CQEs can't be used to look up the WR ID
451 	 * anymore, so we do this only if selective signaling is off.
452 	 *
453 	 * Further, on 32-bit platforms, we can't use vmap() to make
454 	 * the QP buffer virtually contiguous.  Thus we have to use
455 	 * constant-sized WRs to make sure a WR is always fully within
456 	 * a single page-sized chunk.
457 	 *
458 	 * Finally, we use NOP work requests to pad the end of the
459 	 * work queue, to avoid wrap-around in the middle of WR.  We
460 	 * set NEC bit to avoid getting completions with error for
461 	 * these NOP WRs, but since NEC is only supported starting
462 	 * with firmware 2.2.232, we use constant-sized WRs for older
463 	 * firmware.
464 	 *
465 	 * And, since MLX QPs only support SEND, we use constant-sized
466 	 * WRs in this case.
467 	 *
468 	 * We look for the smallest value of wqe_shift such that the
469 	 * resulting number of wqes does not exceed device
470 	 * capabilities.
471 	 *
472 	 * We set WQE size to at least 64 bytes, this way stamping
473 	 * invalidates each WQE.
474 	 */
475 	if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
476 	    qp->sq_signal_bits && BITS_PER_LONG == 64 &&
477 	    type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
478 	    !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
479 		      MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
480 		qp->sq.wqe_shift = ilog2(64);
481 	else
482 		qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
483 
484 	for (;;) {
485 		qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
486 
487 		/*
488 		 * We need to leave 2 KB + 1 WR of headroom in the SQ to
489 		 * allow HW to prefetch.
490 		 */
491 		qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
492 		qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
493 						    qp->sq_max_wqes_per_wr +
494 						    qp->sq_spare_wqes);
495 
496 		if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
497 			break;
498 
499 		if (qp->sq_max_wqes_per_wr <= 1)
500 			return -EINVAL;
501 
502 		++qp->sq.wqe_shift;
503 	}
504 
505 	qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
506 			     (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
507 			 send_wqe_overhead(type, qp->flags)) /
508 		sizeof (struct mlx4_wqe_data_seg);
509 
510 	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
511 		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
512 	if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
513 		qp->rq.offset = 0;
514 		qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
515 	} else {
516 		qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
517 		qp->sq.offset = 0;
518 	}
519 
520 	cap->max_send_wr  = qp->sq.max_post =
521 		(qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
522 	cap->max_send_sge = min(qp->sq.max_gs,
523 				min(dev->dev->caps.max_sq_sg,
524 				    dev->dev->caps.max_rq_sg));
525 	/* We don't support inline sends for kernel QPs (yet) */
526 	cap->max_inline_data = 0;
527 
528 	return 0;
529 }
530 
531 static int set_user_sq_size(struct mlx4_ib_dev *dev,
532 			    struct mlx4_ib_qp *qp,
533 			    struct mlx4_ib_create_qp *ucmd)
534 {
535 	/* Sanity check SQ size before proceeding */
536 	if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes	 ||
537 	    ucmd->log_sq_stride >
538 		ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
539 	    ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
540 		return -EINVAL;
541 
542 	qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
543 	qp->sq.wqe_shift = ucmd->log_sq_stride;
544 
545 	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
546 		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
547 
548 	return 0;
549 }
550 
551 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
552 {
553 	int i;
554 
555 	qp->sqp_proxy_rcv =
556 		kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
557 			GFP_KERNEL);
558 	if (!qp->sqp_proxy_rcv)
559 		return -ENOMEM;
560 	for (i = 0; i < qp->rq.wqe_cnt; i++) {
561 		qp->sqp_proxy_rcv[i].addr =
562 			kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
563 				GFP_KERNEL);
564 		if (!qp->sqp_proxy_rcv[i].addr)
565 			goto err;
566 		qp->sqp_proxy_rcv[i].map =
567 			ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
568 					  sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 					  DMA_FROM_DEVICE);
570 		if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
571 			kfree(qp->sqp_proxy_rcv[i].addr);
572 			goto err;
573 		}
574 	}
575 	return 0;
576 
577 err:
578 	while (i > 0) {
579 		--i;
580 		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
581 				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
582 				    DMA_FROM_DEVICE);
583 		kfree(qp->sqp_proxy_rcv[i].addr);
584 	}
585 	kfree(qp->sqp_proxy_rcv);
586 	qp->sqp_proxy_rcv = NULL;
587 	return -ENOMEM;
588 }
589 
590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
591 {
592 	int i;
593 
594 	for (i = 0; i < qp->rq.wqe_cnt; i++) {
595 		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
596 				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
597 				    DMA_FROM_DEVICE);
598 		kfree(qp->sqp_proxy_rcv[i].addr);
599 	}
600 	kfree(qp->sqp_proxy_rcv);
601 }
602 
603 static int qp_has_rq(struct ib_qp_init_attr *attr)
604 {
605 	if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
606 		return 0;
607 
608 	return !attr->srq;
609 }
610 
611 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
612 {
613 	int i;
614 	for (i = 0; i < dev->caps.num_ports; i++) {
615 		if (qpn == dev->caps.qp0_proxy[i])
616 			return !!dev->caps.qp0_qkey[i];
617 	}
618 	return 0;
619 }
620 
621 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
622 				    struct mlx4_ib_qp *qp)
623 {
624 	mutex_lock(&dev->counters_table[qp->port - 1].mutex);
625 	mlx4_counter_free(dev->dev, qp->counter_index->index);
626 	list_del(&qp->counter_index->list);
627 	mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
628 
629 	kfree(qp->counter_index);
630 	qp->counter_index = NULL;
631 }
632 
633 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
634 			    struct ib_qp_init_attr *init_attr,
635 			    struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
636 			    gfp_t gfp)
637 {
638 	int qpn;
639 	int err;
640 	struct mlx4_ib_sqp *sqp;
641 	struct mlx4_ib_qp *qp;
642 	enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
643 	struct mlx4_ib_cq *mcq;
644 	unsigned long flags;
645 
646 	/* When tunneling special qps, we use a plain UD qp */
647 	if (sqpn) {
648 		if (mlx4_is_mfunc(dev->dev) &&
649 		    (!mlx4_is_master(dev->dev) ||
650 		     !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
651 			if (init_attr->qp_type == IB_QPT_GSI)
652 				qp_type = MLX4_IB_QPT_PROXY_GSI;
653 			else {
654 				if (mlx4_is_master(dev->dev) ||
655 				    qp0_enabled_vf(dev->dev, sqpn))
656 					qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
657 				else
658 					qp_type = MLX4_IB_QPT_PROXY_SMI;
659 			}
660 		}
661 		qpn = sqpn;
662 		/* add extra sg entry for tunneling */
663 		init_attr->cap.max_recv_sge++;
664 	} else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
665 		struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
666 			container_of(init_attr,
667 				     struct mlx4_ib_qp_tunnel_init_attr, init_attr);
668 		if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
669 		     tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
670 		    !mlx4_is_master(dev->dev))
671 			return -EINVAL;
672 		if (tnl_init->proxy_qp_type == IB_QPT_GSI)
673 			qp_type = MLX4_IB_QPT_TUN_GSI;
674 		else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
675 			 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
676 					     tnl_init->port))
677 			qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
678 		else
679 			qp_type = MLX4_IB_QPT_TUN_SMI;
680 		/* we are definitely in the PPF here, since we are creating
681 		 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
682 		qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
683 			+ tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
684 		sqpn = qpn;
685 	}
686 
687 	if (!*caller_qp) {
688 		if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
689 		    (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
690 				MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
691 			sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
692 			if (!sqp)
693 				return -ENOMEM;
694 			qp = &sqp->qp;
695 			qp->pri.vid = 0xFFFF;
696 			qp->alt.vid = 0xFFFF;
697 		} else {
698 			qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
699 			if (!qp)
700 				return -ENOMEM;
701 			qp->pri.vid = 0xFFFF;
702 			qp->alt.vid = 0xFFFF;
703 		}
704 	} else
705 		qp = *caller_qp;
706 
707 	qp->mlx4_ib_qp_type = qp_type;
708 
709 	mutex_init(&qp->mutex);
710 	spin_lock_init(&qp->sq.lock);
711 	spin_lock_init(&qp->rq.lock);
712 	INIT_LIST_HEAD(&qp->gid_list);
713 	INIT_LIST_HEAD(&qp->steering_rules);
714 
715 	qp->state	 = IB_QPS_RESET;
716 	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
717 		qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
718 
719 	err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
720 	if (err)
721 		goto err;
722 
723 	if (pd->uobject) {
724 		struct mlx4_ib_create_qp ucmd;
725 
726 		if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
727 			err = -EFAULT;
728 			goto err;
729 		}
730 
731 		qp->sq_no_prefetch = ucmd.sq_no_prefetch;
732 
733 		err = set_user_sq_size(dev, qp, &ucmd);
734 		if (err)
735 			goto err;
736 
737 		qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
738 				       qp->buf_size, 0, 0);
739 		if (IS_ERR(qp->umem)) {
740 			err = PTR_ERR(qp->umem);
741 			goto err;
742 		}
743 
744 		err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
745 				    ilog2(qp->umem->page_size), &qp->mtt);
746 		if (err)
747 			goto err_buf;
748 
749 		err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
750 		if (err)
751 			goto err_mtt;
752 
753 		if (qp_has_rq(init_attr)) {
754 			err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
755 						  ucmd.db_addr, &qp->db);
756 			if (err)
757 				goto err_mtt;
758 		}
759 	} else {
760 		qp->sq_no_prefetch = 0;
761 
762 		if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
763 			qp->flags |= MLX4_IB_QP_LSO;
764 
765 		if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
766 			if (dev->steering_support ==
767 			    MLX4_STEERING_MODE_DEVICE_MANAGED)
768 				qp->flags |= MLX4_IB_QP_NETIF;
769 			else
770 				goto err;
771 		}
772 
773 		err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
774 		if (err)
775 			goto err;
776 
777 		if (qp_has_rq(init_attr)) {
778 			err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
779 			if (err)
780 				goto err;
781 
782 			*qp->db.db = 0;
783 		}
784 
785 		if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
786 			err = -ENOMEM;
787 			goto err_db;
788 		}
789 
790 		err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
791 				    &qp->mtt);
792 		if (err)
793 			goto err_buf;
794 
795 		err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
796 		if (err)
797 			goto err_mtt;
798 
799 		qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(u64), gfp);
800 		if (!qp->sq.wrid)
801 			qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
802 						gfp, PAGE_KERNEL);
803 		qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(u64), gfp);
804 		if (!qp->rq.wrid)
805 			qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
806 						gfp, PAGE_KERNEL);
807 		if (!qp->sq.wrid || !qp->rq.wrid) {
808 			err = -ENOMEM;
809 			goto err_wrid;
810 		}
811 	}
812 
813 	if (sqpn) {
814 		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
815 		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
816 			if (alloc_proxy_bufs(pd->device, qp)) {
817 				err = -ENOMEM;
818 				goto err_wrid;
819 			}
820 		}
821 	} else {
822 		/* Raw packet QPNs may not have bits 6,7 set in their qp_num;
823 		 * otherwise, the WQE BlueFlame setup flow wrongly causes
824 		 * VLAN insertion. */
825 		if (init_attr->qp_type == IB_QPT_RAW_PACKET)
826 			err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
827 						    (init_attr->cap.max_send_wr ?
828 						     MLX4_RESERVE_ETH_BF_QP : 0) |
829 						    (init_attr->cap.max_recv_wr ?
830 						     MLX4_RESERVE_A0_QP : 0));
831 		else
832 			if (qp->flags & MLX4_IB_QP_NETIF)
833 				err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
834 			else
835 				err = mlx4_qp_reserve_range(dev->dev, 1, 1,
836 							    &qpn, 0);
837 		if (err)
838 			goto err_proxy;
839 	}
840 
841 	if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
842 		qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
843 
844 	err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
845 	if (err)
846 		goto err_qpn;
847 
848 	if (init_attr->qp_type == IB_QPT_XRC_TGT)
849 		qp->mqp.qpn |= (1 << 23);
850 
851 	/*
852 	 * Hardware wants QPN written in big-endian order (after
853 	 * shifting) for send doorbell.  Precompute this value to save
854 	 * a little bit when posting sends.
855 	 */
856 	qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
857 
858 	qp->mqp.event = mlx4_ib_qp_event;
859 	if (!*caller_qp)
860 		*caller_qp = qp;
861 
862 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
863 	mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
864 			 to_mcq(init_attr->recv_cq));
865 	/* Maintain device to QPs access, needed for further handling
866 	 * via reset flow
867 	 */
868 	list_add_tail(&qp->qps_list, &dev->qp_list);
869 	/* Maintain CQ to QPs access, needed for further handling
870 	 * via reset flow
871 	 */
872 	mcq = to_mcq(init_attr->send_cq);
873 	list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
874 	mcq = to_mcq(init_attr->recv_cq);
875 	list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
876 	mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
877 			   to_mcq(init_attr->recv_cq));
878 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
879 	return 0;
880 
881 err_qpn:
882 	if (!sqpn) {
883 		if (qp->flags & MLX4_IB_QP_NETIF)
884 			mlx4_ib_steer_qp_free(dev, qpn, 1);
885 		else
886 			mlx4_qp_release_range(dev->dev, qpn, 1);
887 	}
888 err_proxy:
889 	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
890 		free_proxy_bufs(pd->device, qp);
891 err_wrid:
892 	if (pd->uobject) {
893 		if (qp_has_rq(init_attr))
894 			mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
895 	} else {
896 		kvfree(qp->sq.wrid);
897 		kvfree(qp->rq.wrid);
898 	}
899 
900 err_mtt:
901 	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
902 
903 err_buf:
904 	if (pd->uobject)
905 		ib_umem_release(qp->umem);
906 	else
907 		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
908 
909 err_db:
910 	if (!pd->uobject && qp_has_rq(init_attr))
911 		mlx4_db_free(dev->dev, &qp->db);
912 
913 err:
914 	if (!*caller_qp)
915 		kfree(qp);
916 	return err;
917 }
918 
919 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
920 {
921 	switch (state) {
922 	case IB_QPS_RESET:	return MLX4_QP_STATE_RST;
923 	case IB_QPS_INIT:	return MLX4_QP_STATE_INIT;
924 	case IB_QPS_RTR:	return MLX4_QP_STATE_RTR;
925 	case IB_QPS_RTS:	return MLX4_QP_STATE_RTS;
926 	case IB_QPS_SQD:	return MLX4_QP_STATE_SQD;
927 	case IB_QPS_SQE:	return MLX4_QP_STATE_SQER;
928 	case IB_QPS_ERR:	return MLX4_QP_STATE_ERR;
929 	default:		return -1;
930 	}
931 }
932 
933 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
934 	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
935 {
936 	if (send_cq == recv_cq) {
937 		spin_lock(&send_cq->lock);
938 		__acquire(&recv_cq->lock);
939 	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
940 		spin_lock(&send_cq->lock);
941 		spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
942 	} else {
943 		spin_lock(&recv_cq->lock);
944 		spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
945 	}
946 }
947 
948 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
949 	__releases(&send_cq->lock) __releases(&recv_cq->lock)
950 {
951 	if (send_cq == recv_cq) {
952 		__release(&recv_cq->lock);
953 		spin_unlock(&send_cq->lock);
954 	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
955 		spin_unlock(&recv_cq->lock);
956 		spin_unlock(&send_cq->lock);
957 	} else {
958 		spin_unlock(&send_cq->lock);
959 		spin_unlock(&recv_cq->lock);
960 	}
961 }
962 
963 static void del_gid_entries(struct mlx4_ib_qp *qp)
964 {
965 	struct mlx4_ib_gid_entry *ge, *tmp;
966 
967 	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
968 		list_del(&ge->list);
969 		kfree(ge);
970 	}
971 }
972 
973 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
974 {
975 	if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
976 		return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
977 	else
978 		return to_mpd(qp->ibqp.pd);
979 }
980 
981 static void get_cqs(struct mlx4_ib_qp *qp,
982 		    struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
983 {
984 	switch (qp->ibqp.qp_type) {
985 	case IB_QPT_XRC_TGT:
986 		*send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
987 		*recv_cq = *send_cq;
988 		break;
989 	case IB_QPT_XRC_INI:
990 		*send_cq = to_mcq(qp->ibqp.send_cq);
991 		*recv_cq = *send_cq;
992 		break;
993 	default:
994 		*send_cq = to_mcq(qp->ibqp.send_cq);
995 		*recv_cq = to_mcq(qp->ibqp.recv_cq);
996 		break;
997 	}
998 }
999 
1000 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1001 			      int is_user)
1002 {
1003 	struct mlx4_ib_cq *send_cq, *recv_cq;
1004 	unsigned long flags;
1005 
1006 	if (qp->state != IB_QPS_RESET) {
1007 		if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1008 				   MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1009 			pr_warn("modify QP %06x to RESET failed.\n",
1010 			       qp->mqp.qpn);
1011 		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1012 			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1013 			qp->pri.smac = 0;
1014 			qp->pri.smac_port = 0;
1015 		}
1016 		if (qp->alt.smac) {
1017 			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1018 			qp->alt.smac = 0;
1019 		}
1020 		if (qp->pri.vid < 0x1000) {
1021 			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1022 			qp->pri.vid = 0xFFFF;
1023 			qp->pri.candidate_vid = 0xFFFF;
1024 			qp->pri.update_vid = 0;
1025 		}
1026 		if (qp->alt.vid < 0x1000) {
1027 			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1028 			qp->alt.vid = 0xFFFF;
1029 			qp->alt.candidate_vid = 0xFFFF;
1030 			qp->alt.update_vid = 0;
1031 		}
1032 	}
1033 
1034 	get_cqs(qp, &send_cq, &recv_cq);
1035 
1036 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1037 	mlx4_ib_lock_cqs(send_cq, recv_cq);
1038 
1039 	/* del from lists under both locks above to protect reset flow paths */
1040 	list_del(&qp->qps_list);
1041 	list_del(&qp->cq_send_list);
1042 	list_del(&qp->cq_recv_list);
1043 	if (!is_user) {
1044 		__mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1045 				 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1046 		if (send_cq != recv_cq)
1047 			__mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1048 	}
1049 
1050 	mlx4_qp_remove(dev->dev, &qp->mqp);
1051 
1052 	mlx4_ib_unlock_cqs(send_cq, recv_cq);
1053 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1054 
1055 	mlx4_qp_free(dev->dev, &qp->mqp);
1056 
1057 	if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1058 		if (qp->flags & MLX4_IB_QP_NETIF)
1059 			mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1060 		else
1061 			mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1062 	}
1063 
1064 	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1065 
1066 	if (is_user) {
1067 		if (qp->rq.wqe_cnt)
1068 			mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1069 					      &qp->db);
1070 		ib_umem_release(qp->umem);
1071 	} else {
1072 		kvfree(qp->sq.wrid);
1073 		kvfree(qp->rq.wrid);
1074 		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1075 		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1076 			free_proxy_bufs(&dev->ib_dev, qp);
1077 		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1078 		if (qp->rq.wqe_cnt)
1079 			mlx4_db_free(dev->dev, &qp->db);
1080 	}
1081 
1082 	del_gid_entries(qp);
1083 }
1084 
1085 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1086 {
1087 	/* Native or PPF */
1088 	if (!mlx4_is_mfunc(dev->dev) ||
1089 	    (mlx4_is_master(dev->dev) &&
1090 	     attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1091 		return  dev->dev->phys_caps.base_sqpn +
1092 			(attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1093 			attr->port_num - 1;
1094 	}
1095 	/* PF or VF -- creating proxies */
1096 	if (attr->qp_type == IB_QPT_SMI)
1097 		return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1098 	else
1099 		return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1100 }
1101 
1102 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1103 				struct ib_qp_init_attr *init_attr,
1104 				struct ib_udata *udata)
1105 {
1106 	struct mlx4_ib_qp *qp = NULL;
1107 	int err;
1108 	int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1109 	u16 xrcdn = 0;
1110 	gfp_t gfp;
1111 
1112 	gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1113 		GFP_NOIO : GFP_KERNEL;
1114 	/*
1115 	 * We only support LSO, vendor flag1, and multicast loopback blocking,
1116 	 * and only for kernel UD QPs.
1117 	 */
1118 	if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1119 					MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1120 					MLX4_IB_SRIOV_TUNNEL_QP |
1121 					MLX4_IB_SRIOV_SQP |
1122 					MLX4_IB_QP_NETIF |
1123 					MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1124 		return ERR_PTR(-EINVAL);
1125 
1126 	if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1127 		if (init_attr->qp_type != IB_QPT_UD)
1128 			return ERR_PTR(-EINVAL);
1129 	}
1130 
1131 	if (init_attr->create_flags &&
1132 	    ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1133 	     ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1134 					   MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1135 					   MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1136 	      init_attr->qp_type != IB_QPT_UD) ||
1137 	     ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1138 	      init_attr->qp_type > IB_QPT_GSI)))
1139 		return ERR_PTR(-EINVAL);
1140 
1141 	switch (init_attr->qp_type) {
1142 	case IB_QPT_XRC_TGT:
1143 		pd = to_mxrcd(init_attr->xrcd)->pd;
1144 		xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1145 		init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1146 		/* fall through */
1147 	case IB_QPT_XRC_INI:
1148 		if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1149 			return ERR_PTR(-ENOSYS);
1150 		init_attr->recv_cq = init_attr->send_cq;
1151 		/* fall through */
1152 	case IB_QPT_RC:
1153 	case IB_QPT_UC:
1154 	case IB_QPT_RAW_PACKET:
1155 		qp = kzalloc(sizeof *qp, gfp);
1156 		if (!qp)
1157 			return ERR_PTR(-ENOMEM);
1158 		qp->pri.vid = 0xFFFF;
1159 		qp->alt.vid = 0xFFFF;
1160 		/* fall through */
1161 	case IB_QPT_UD:
1162 	{
1163 		err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1164 				       udata, 0, &qp, gfp);
1165 		if (err)
1166 			return ERR_PTR(err);
1167 
1168 		qp->ibqp.qp_num = qp->mqp.qpn;
1169 		qp->xrcdn = xrcdn;
1170 
1171 		break;
1172 	}
1173 	case IB_QPT_SMI:
1174 	case IB_QPT_GSI:
1175 	{
1176 		/* Userspace is not allowed to create special QPs: */
1177 		if (udata)
1178 			return ERR_PTR(-EINVAL);
1179 
1180 		err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1181 				       get_sqp_num(to_mdev(pd->device), init_attr),
1182 				       &qp, gfp);
1183 		if (err)
1184 			return ERR_PTR(err);
1185 
1186 		qp->port	= init_attr->port_num;
1187 		qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1188 
1189 		break;
1190 	}
1191 	default:
1192 		/* Don't support raw QPs */
1193 		return ERR_PTR(-EINVAL);
1194 	}
1195 
1196 	return &qp->ibqp;
1197 }
1198 
1199 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1200 {
1201 	struct mlx4_ib_dev *dev = to_mdev(qp->device);
1202 	struct mlx4_ib_qp *mqp = to_mqp(qp);
1203 	struct mlx4_ib_pd *pd;
1204 
1205 	if (is_qp0(dev, mqp))
1206 		mlx4_CLOSE_PORT(dev->dev, mqp->port);
1207 
1208 	if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1209 		mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1210 		dev->qp1_proxy[mqp->port - 1] = NULL;
1211 		mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1212 	}
1213 
1214 	if (mqp->counter_index)
1215 		mlx4_ib_free_qp_counter(dev, mqp);
1216 
1217 	pd = get_pd(mqp);
1218 	destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1219 
1220 	if (is_sqp(dev, mqp))
1221 		kfree(to_msqp(mqp));
1222 	else
1223 		kfree(mqp);
1224 
1225 	return 0;
1226 }
1227 
1228 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1229 {
1230 	switch (type) {
1231 	case MLX4_IB_QPT_RC:		return MLX4_QP_ST_RC;
1232 	case MLX4_IB_QPT_UC:		return MLX4_QP_ST_UC;
1233 	case MLX4_IB_QPT_UD:		return MLX4_QP_ST_UD;
1234 	case MLX4_IB_QPT_XRC_INI:
1235 	case MLX4_IB_QPT_XRC_TGT:	return MLX4_QP_ST_XRC;
1236 	case MLX4_IB_QPT_SMI:
1237 	case MLX4_IB_QPT_GSI:
1238 	case MLX4_IB_QPT_RAW_PACKET:	return MLX4_QP_ST_MLX;
1239 
1240 	case MLX4_IB_QPT_PROXY_SMI_OWNER:
1241 	case MLX4_IB_QPT_TUN_SMI_OWNER:	return (mlx4_is_mfunc(dev->dev) ?
1242 						MLX4_QP_ST_MLX : -1);
1243 	case MLX4_IB_QPT_PROXY_SMI:
1244 	case MLX4_IB_QPT_TUN_SMI:
1245 	case MLX4_IB_QPT_PROXY_GSI:
1246 	case MLX4_IB_QPT_TUN_GSI:	return (mlx4_is_mfunc(dev->dev) ?
1247 						MLX4_QP_ST_UD : -1);
1248 	default:			return -1;
1249 	}
1250 }
1251 
1252 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1253 				   int attr_mask)
1254 {
1255 	u8 dest_rd_atomic;
1256 	u32 access_flags;
1257 	u32 hw_access_flags = 0;
1258 
1259 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1260 		dest_rd_atomic = attr->max_dest_rd_atomic;
1261 	else
1262 		dest_rd_atomic = qp->resp_depth;
1263 
1264 	if (attr_mask & IB_QP_ACCESS_FLAGS)
1265 		access_flags = attr->qp_access_flags;
1266 	else
1267 		access_flags = qp->atomic_rd_en;
1268 
1269 	if (!dest_rd_atomic)
1270 		access_flags &= IB_ACCESS_REMOTE_WRITE;
1271 
1272 	if (access_flags & IB_ACCESS_REMOTE_READ)
1273 		hw_access_flags |= MLX4_QP_BIT_RRE;
1274 	if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1275 		hw_access_flags |= MLX4_QP_BIT_RAE;
1276 	if (access_flags & IB_ACCESS_REMOTE_WRITE)
1277 		hw_access_flags |= MLX4_QP_BIT_RWE;
1278 
1279 	return cpu_to_be32(hw_access_flags);
1280 }
1281 
1282 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1283 			    int attr_mask)
1284 {
1285 	if (attr_mask & IB_QP_PKEY_INDEX)
1286 		sqp->pkey_index = attr->pkey_index;
1287 	if (attr_mask & IB_QP_QKEY)
1288 		sqp->qkey = attr->qkey;
1289 	if (attr_mask & IB_QP_SQ_PSN)
1290 		sqp->send_psn = attr->sq_psn;
1291 }
1292 
1293 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1294 {
1295 	path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1296 }
1297 
1298 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1299 			  u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1300 			  struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1301 {
1302 	int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1303 		IB_LINK_LAYER_ETHERNET;
1304 	int vidx;
1305 	int smac_index;
1306 	int err;
1307 
1308 
1309 	path->grh_mylmc     = ah->src_path_bits & 0x7f;
1310 	path->rlid	    = cpu_to_be16(ah->dlid);
1311 	if (ah->static_rate) {
1312 		path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1313 		while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1314 		       !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1315 			--path->static_rate;
1316 	} else
1317 		path->static_rate = 0;
1318 
1319 	if (ah->ah_flags & IB_AH_GRH) {
1320 		int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1321 								      port,
1322 								      ah->grh.sgid_index);
1323 
1324 		if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1325 			pr_err("sgid_index (%u) too large. max is %d\n",
1326 			       real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1327 			return -1;
1328 		}
1329 
1330 		path->grh_mylmc |= 1 << 7;
1331 		path->mgid_index = real_sgid_index;
1332 		path->hop_limit  = ah->grh.hop_limit;
1333 		path->tclass_flowlabel =
1334 			cpu_to_be32((ah->grh.traffic_class << 20) |
1335 				    (ah->grh.flow_label));
1336 		memcpy(path->rgid, ah->grh.dgid.raw, 16);
1337 	}
1338 
1339 	if (is_eth) {
1340 		if (!(ah->ah_flags & IB_AH_GRH))
1341 			return -1;
1342 
1343 		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1344 			((port - 1) << 6) | ((ah->sl & 7) << 3);
1345 
1346 		path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1347 		if (vlan_tag < 0x1000) {
1348 			if (smac_info->vid < 0x1000) {
1349 				/* both valid vlan ids */
1350 				if (smac_info->vid != vlan_tag) {
1351 					/* different VIDs.  unreg old and reg new */
1352 					err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1353 					if (err)
1354 						return err;
1355 					smac_info->candidate_vid = vlan_tag;
1356 					smac_info->candidate_vlan_index = vidx;
1357 					smac_info->candidate_vlan_port = port;
1358 					smac_info->update_vid = 1;
1359 					path->vlan_index = vidx;
1360 				} else {
1361 					path->vlan_index = smac_info->vlan_index;
1362 				}
1363 			} else {
1364 				/* no current vlan tag in qp */
1365 				err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1366 				if (err)
1367 					return err;
1368 				smac_info->candidate_vid = vlan_tag;
1369 				smac_info->candidate_vlan_index = vidx;
1370 				smac_info->candidate_vlan_port = port;
1371 				smac_info->update_vid = 1;
1372 				path->vlan_index = vidx;
1373 			}
1374 			path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1375 			path->fl = 1 << 6;
1376 		} else {
1377 			/* have current vlan tag. unregister it at modify-qp success */
1378 			if (smac_info->vid < 0x1000) {
1379 				smac_info->candidate_vid = 0xFFFF;
1380 				smac_info->update_vid = 1;
1381 			}
1382 		}
1383 
1384 		/* get smac_index for RoCE use.
1385 		 * If no smac was yet assigned, register one.
1386 		 * If one was already assigned, but the new mac differs,
1387 		 * unregister the old one and register the new one.
1388 		*/
1389 		if ((!smac_info->smac && !smac_info->smac_port) ||
1390 		    smac_info->smac != smac) {
1391 			/* register candidate now, unreg if needed, after success */
1392 			smac_index = mlx4_register_mac(dev->dev, port, smac);
1393 			if (smac_index >= 0) {
1394 				smac_info->candidate_smac_index = smac_index;
1395 				smac_info->candidate_smac = smac;
1396 				smac_info->candidate_smac_port = port;
1397 			} else {
1398 				return -EINVAL;
1399 			}
1400 		} else {
1401 			smac_index = smac_info->smac_index;
1402 		}
1403 
1404 		memcpy(path->dmac, ah->dmac, 6);
1405 		path->ackto = MLX4_IB_LINK_TYPE_ETH;
1406 		/* put MAC table smac index for IBoE */
1407 		path->grh_mylmc = (u8) (smac_index) | 0x80;
1408 	} else {
1409 		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1410 			((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1411 	}
1412 
1413 	return 0;
1414 }
1415 
1416 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1417 			 enum ib_qp_attr_mask qp_attr_mask,
1418 			 struct mlx4_ib_qp *mqp,
1419 			 struct mlx4_qp_path *path, u8 port,
1420 			 u16 vlan_id, u8 *smac)
1421 {
1422 	return _mlx4_set_path(dev, &qp->ah_attr,
1423 			      mlx4_mac_to_u64(smac),
1424 			      vlan_id,
1425 			      path, &mqp->pri, port);
1426 }
1427 
1428 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1429 			     const struct ib_qp_attr *qp,
1430 			     enum ib_qp_attr_mask qp_attr_mask,
1431 			     struct mlx4_ib_qp *mqp,
1432 			     struct mlx4_qp_path *path, u8 port)
1433 {
1434 	return _mlx4_set_path(dev, &qp->alt_ah_attr,
1435 			      0,
1436 			      0xffff,
1437 			      path, &mqp->alt, port);
1438 }
1439 
1440 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1441 {
1442 	struct mlx4_ib_gid_entry *ge, *tmp;
1443 
1444 	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1445 		if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1446 			ge->added = 1;
1447 			ge->port = qp->port;
1448 		}
1449 	}
1450 }
1451 
1452 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1453 				    struct mlx4_ib_qp *qp,
1454 				    struct mlx4_qp_context *context)
1455 {
1456 	u64 u64_mac;
1457 	int smac_index;
1458 
1459 	u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1460 
1461 	context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1462 	if (!qp->pri.smac && !qp->pri.smac_port) {
1463 		smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1464 		if (smac_index >= 0) {
1465 			qp->pri.candidate_smac_index = smac_index;
1466 			qp->pri.candidate_smac = u64_mac;
1467 			qp->pri.candidate_smac_port = qp->port;
1468 			context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1469 		} else {
1470 			return -ENOENT;
1471 		}
1472 	}
1473 	return 0;
1474 }
1475 
1476 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1477 {
1478 	struct counter_index *new_counter_index;
1479 	int err;
1480 	u32 tmp_idx;
1481 
1482 	if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1483 	    IB_LINK_LAYER_ETHERNET ||
1484 	    !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1485 	    !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1486 		return 0;
1487 
1488 	err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1489 	if (err)
1490 		return err;
1491 
1492 	new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1493 	if (!new_counter_index) {
1494 		mlx4_counter_free(dev->dev, tmp_idx);
1495 		return -ENOMEM;
1496 	}
1497 
1498 	new_counter_index->index = tmp_idx;
1499 	new_counter_index->allocated = 1;
1500 	qp->counter_index = new_counter_index;
1501 
1502 	mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1503 	list_add_tail(&new_counter_index->list,
1504 		      &dev->counters_table[qp->port - 1].counters_list);
1505 	mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1506 
1507 	return 0;
1508 }
1509 
1510 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1511 			       const struct ib_qp_attr *attr, int attr_mask,
1512 			       enum ib_qp_state cur_state, enum ib_qp_state new_state)
1513 {
1514 	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1515 	struct mlx4_ib_qp *qp = to_mqp(ibqp);
1516 	struct mlx4_ib_pd *pd;
1517 	struct mlx4_ib_cq *send_cq, *recv_cq;
1518 	struct mlx4_qp_context *context;
1519 	enum mlx4_qp_optpar optpar = 0;
1520 	int sqd_event;
1521 	int steer_qp = 0;
1522 	int err = -EINVAL;
1523 	int counter_index;
1524 
1525 	/* APM is not supported under RoCE */
1526 	if (attr_mask & IB_QP_ALT_PATH &&
1527 	    rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1528 	    IB_LINK_LAYER_ETHERNET)
1529 		return -ENOTSUPP;
1530 
1531 	context = kzalloc(sizeof *context, GFP_KERNEL);
1532 	if (!context)
1533 		return -ENOMEM;
1534 
1535 	context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1536 				     (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1537 
1538 	if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1539 		context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1540 	else {
1541 		optpar |= MLX4_QP_OPTPAR_PM_STATE;
1542 		switch (attr->path_mig_state) {
1543 		case IB_MIG_MIGRATED:
1544 			context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1545 			break;
1546 		case IB_MIG_REARM:
1547 			context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1548 			break;
1549 		case IB_MIG_ARMED:
1550 			context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1551 			break;
1552 		}
1553 	}
1554 
1555 	if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1556 		context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1557 	else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1558 		context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1559 	else if (ibqp->qp_type == IB_QPT_UD) {
1560 		if (qp->flags & MLX4_IB_QP_LSO)
1561 			context->mtu_msgmax = (IB_MTU_4096 << 5) |
1562 					      ilog2(dev->dev->caps.max_gso_sz);
1563 		else
1564 			context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1565 	} else if (attr_mask & IB_QP_PATH_MTU) {
1566 		if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1567 			pr_err("path MTU (%u) is invalid\n",
1568 			       attr->path_mtu);
1569 			goto out;
1570 		}
1571 		context->mtu_msgmax = (attr->path_mtu << 5) |
1572 			ilog2(dev->dev->caps.max_msg_sz);
1573 	}
1574 
1575 	if (qp->rq.wqe_cnt)
1576 		context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1577 	context->rq_size_stride |= qp->rq.wqe_shift - 4;
1578 
1579 	if (qp->sq.wqe_cnt)
1580 		context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1581 	context->sq_size_stride |= qp->sq.wqe_shift - 4;
1582 
1583 	if (new_state == IB_QPS_RESET && qp->counter_index)
1584 		mlx4_ib_free_qp_counter(dev, qp);
1585 
1586 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1587 		context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1588 		context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1589 		if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1590 			context->param3 |= cpu_to_be32(1 << 30);
1591 	}
1592 
1593 	if (qp->ibqp.uobject)
1594 		context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1595 	else
1596 		context->usr_page = cpu_to_be32(dev->priv_uar.index);
1597 
1598 	if (attr_mask & IB_QP_DEST_QPN)
1599 		context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1600 
1601 	if (attr_mask & IB_QP_PORT) {
1602 		if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1603 		    !(attr_mask & IB_QP_AV)) {
1604 			mlx4_set_sched(&context->pri_path, attr->port_num);
1605 			optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1606 		}
1607 	}
1608 
1609 	if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1610 		err = create_qp_lb_counter(dev, qp);
1611 		if (err)
1612 			goto out;
1613 
1614 		counter_index =
1615 			dev->counters_table[qp->port - 1].default_counter;
1616 		if (qp->counter_index)
1617 			counter_index = qp->counter_index->index;
1618 
1619 		if (counter_index != -1) {
1620 			context->pri_path.counter_index = counter_index;
1621 			optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1622 			if (qp->counter_index) {
1623 				context->pri_path.fl |=
1624 					MLX4_FL_ETH_SRC_CHECK_MC_LB;
1625 				context->pri_path.vlan_control |=
1626 					MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1627 			}
1628 		} else
1629 			context->pri_path.counter_index =
1630 				MLX4_SINK_COUNTER_INDEX(dev->dev);
1631 
1632 		if (qp->flags & MLX4_IB_QP_NETIF) {
1633 			mlx4_ib_steer_qp_reg(dev, qp, 1);
1634 			steer_qp = 1;
1635 		}
1636 	}
1637 
1638 	if (attr_mask & IB_QP_PKEY_INDEX) {
1639 		if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1640 			context->pri_path.disable_pkey_check = 0x40;
1641 		context->pri_path.pkey_index = attr->pkey_index;
1642 		optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1643 	}
1644 
1645 	if (attr_mask & IB_QP_AV) {
1646 		u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1647 			attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1648 		union ib_gid gid;
1649 		struct ib_gid_attr gid_attr;
1650 		u16 vlan = 0xffff;
1651 		u8 smac[ETH_ALEN];
1652 		int status = 0;
1653 
1654 		if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1655 		    attr->ah_attr.ah_flags & IB_AH_GRH) {
1656 			int index = attr->ah_attr.grh.sgid_index;
1657 
1658 			status = ib_get_cached_gid(ibqp->device, port_num,
1659 						   index, &gid, &gid_attr);
1660 			if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1661 				status = -ENOENT;
1662 			if (!status && gid_attr.ndev) {
1663 				vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1664 				memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1665 				dev_put(gid_attr.ndev);
1666 			}
1667 		}
1668 		if (status)
1669 			goto out;
1670 
1671 		if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1672 				  port_num, vlan, smac))
1673 			goto out;
1674 
1675 		optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1676 			   MLX4_QP_OPTPAR_SCHED_QUEUE);
1677 	}
1678 
1679 	if (attr_mask & IB_QP_TIMEOUT) {
1680 		context->pri_path.ackto |= attr->timeout << 3;
1681 		optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1682 	}
1683 
1684 	if (attr_mask & IB_QP_ALT_PATH) {
1685 		if (attr->alt_port_num == 0 ||
1686 		    attr->alt_port_num > dev->dev->caps.num_ports)
1687 			goto out;
1688 
1689 		if (attr->alt_pkey_index >=
1690 		    dev->dev->caps.pkey_table_len[attr->alt_port_num])
1691 			goto out;
1692 
1693 		if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1694 				      &context->alt_path,
1695 				      attr->alt_port_num))
1696 			goto out;
1697 
1698 		context->alt_path.pkey_index = attr->alt_pkey_index;
1699 		context->alt_path.ackto = attr->alt_timeout << 3;
1700 		optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1701 	}
1702 
1703 	pd = get_pd(qp);
1704 	get_cqs(qp, &send_cq, &recv_cq);
1705 	context->pd       = cpu_to_be32(pd->pdn);
1706 	context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1707 	context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1708 	context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1709 
1710 	/* Set "fast registration enabled" for all kernel QPs */
1711 	if (!qp->ibqp.uobject)
1712 		context->params1 |= cpu_to_be32(1 << 11);
1713 
1714 	if (attr_mask & IB_QP_RNR_RETRY) {
1715 		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1716 		optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1717 	}
1718 
1719 	if (attr_mask & IB_QP_RETRY_CNT) {
1720 		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1721 		optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1722 	}
1723 
1724 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1725 		if (attr->max_rd_atomic)
1726 			context->params1 |=
1727 				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1728 		optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1729 	}
1730 
1731 	if (attr_mask & IB_QP_SQ_PSN)
1732 		context->next_send_psn = cpu_to_be32(attr->sq_psn);
1733 
1734 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1735 		if (attr->max_dest_rd_atomic)
1736 			context->params2 |=
1737 				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1738 		optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1739 	}
1740 
1741 	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1742 		context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1743 		optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1744 	}
1745 
1746 	if (ibqp->srq)
1747 		context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1748 
1749 	if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1750 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1751 		optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1752 	}
1753 	if (attr_mask & IB_QP_RQ_PSN)
1754 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1755 
1756 	/* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1757 	if (attr_mask & IB_QP_QKEY) {
1758 		if (qp->mlx4_ib_qp_type &
1759 		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1760 			context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1761 		else {
1762 			if (mlx4_is_mfunc(dev->dev) &&
1763 			    !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1764 			    (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1765 			    MLX4_RESERVED_QKEY_BASE) {
1766 				pr_err("Cannot use reserved QKEY"
1767 				       " 0x%x (range 0xffff0000..0xffffffff"
1768 				       " is reserved)\n", attr->qkey);
1769 				err = -EINVAL;
1770 				goto out;
1771 			}
1772 			context->qkey = cpu_to_be32(attr->qkey);
1773 		}
1774 		optpar |= MLX4_QP_OPTPAR_Q_KEY;
1775 	}
1776 
1777 	if (ibqp->srq)
1778 		context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1779 
1780 	if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1781 		context->db_rec_addr = cpu_to_be64(qp->db.dma);
1782 
1783 	if (cur_state == IB_QPS_INIT &&
1784 	    new_state == IB_QPS_RTR  &&
1785 	    (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1786 	     ibqp->qp_type == IB_QPT_UD ||
1787 	     ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1788 		context->pri_path.sched_queue = (qp->port - 1) << 6;
1789 		if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1790 		    qp->mlx4_ib_qp_type &
1791 		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1792 			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1793 			if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1794 				context->pri_path.fl = 0x80;
1795 		} else {
1796 			if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1797 				context->pri_path.fl = 0x80;
1798 			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1799 		}
1800 		if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1801 		    IB_LINK_LAYER_ETHERNET) {
1802 			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1803 			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1804 				context->pri_path.feup = 1 << 7; /* don't fsm */
1805 			/* handle smac_index */
1806 			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1807 			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1808 			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1809 				err = handle_eth_ud_smac_index(dev, qp, context);
1810 				if (err) {
1811 					err = -EINVAL;
1812 					goto out;
1813 				}
1814 				if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1815 					dev->qp1_proxy[qp->port - 1] = qp;
1816 			}
1817 		}
1818 	}
1819 
1820 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1821 		context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1822 					MLX4_IB_LINK_TYPE_ETH;
1823 		if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1824 			/* set QP to receive both tunneled & non-tunneled packets */
1825 			if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1826 				context->srqn = cpu_to_be32(7 << 28);
1827 		}
1828 	}
1829 
1830 	if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1831 		int is_eth = rdma_port_get_link_layer(
1832 				&dev->ib_dev, qp->port) ==
1833 				IB_LINK_LAYER_ETHERNET;
1834 		if (is_eth) {
1835 			context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1836 			optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1837 		}
1838 	}
1839 
1840 
1841 	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
1842 	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1843 		sqd_event = 1;
1844 	else
1845 		sqd_event = 0;
1846 
1847 	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1848 		context->rlkey |= (1 << 4);
1849 
1850 	/*
1851 	 * Before passing a kernel QP to the HW, make sure that the
1852 	 * ownership bits of the send queue are set and the SQ
1853 	 * headroom is stamped so that the hardware doesn't start
1854 	 * processing stale work requests.
1855 	 */
1856 	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1857 		struct mlx4_wqe_ctrl_seg *ctrl;
1858 		int i;
1859 
1860 		for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1861 			ctrl = get_send_wqe(qp, i);
1862 			ctrl->owner_opcode = cpu_to_be32(1 << 31);
1863 			if (qp->sq_max_wqes_per_wr == 1)
1864 				ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1865 
1866 			stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1867 		}
1868 	}
1869 
1870 	err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1871 			     to_mlx4_state(new_state), context, optpar,
1872 			     sqd_event, &qp->mqp);
1873 	if (err)
1874 		goto out;
1875 
1876 	qp->state = new_state;
1877 
1878 	if (attr_mask & IB_QP_ACCESS_FLAGS)
1879 		qp->atomic_rd_en = attr->qp_access_flags;
1880 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1881 		qp->resp_depth = attr->max_dest_rd_atomic;
1882 	if (attr_mask & IB_QP_PORT) {
1883 		qp->port = attr->port_num;
1884 		update_mcg_macs(dev, qp);
1885 	}
1886 	if (attr_mask & IB_QP_ALT_PATH)
1887 		qp->alt_port = attr->alt_port_num;
1888 
1889 	if (is_sqp(dev, qp))
1890 		store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1891 
1892 	/*
1893 	 * If we moved QP0 to RTR, bring the IB link up; if we moved
1894 	 * QP0 to RESET or ERROR, bring the link back down.
1895 	 */
1896 	if (is_qp0(dev, qp)) {
1897 		if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1898 			if (mlx4_INIT_PORT(dev->dev, qp->port))
1899 				pr_warn("INIT_PORT failed for port %d\n",
1900 				       qp->port);
1901 
1902 		if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1903 		    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1904 			mlx4_CLOSE_PORT(dev->dev, qp->port);
1905 	}
1906 
1907 	/*
1908 	 * If we moved a kernel QP to RESET, clean up all old CQ
1909 	 * entries and reinitialize the QP.
1910 	 */
1911 	if (new_state == IB_QPS_RESET) {
1912 		if (!ibqp->uobject) {
1913 			mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1914 					 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1915 			if (send_cq != recv_cq)
1916 				mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1917 
1918 			qp->rq.head = 0;
1919 			qp->rq.tail = 0;
1920 			qp->sq.head = 0;
1921 			qp->sq.tail = 0;
1922 			qp->sq_next_wqe = 0;
1923 			if (qp->rq.wqe_cnt)
1924 				*qp->db.db  = 0;
1925 
1926 			if (qp->flags & MLX4_IB_QP_NETIF)
1927 				mlx4_ib_steer_qp_reg(dev, qp, 0);
1928 		}
1929 		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1930 			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1931 			qp->pri.smac = 0;
1932 			qp->pri.smac_port = 0;
1933 		}
1934 		if (qp->alt.smac) {
1935 			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1936 			qp->alt.smac = 0;
1937 		}
1938 		if (qp->pri.vid < 0x1000) {
1939 			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1940 			qp->pri.vid = 0xFFFF;
1941 			qp->pri.candidate_vid = 0xFFFF;
1942 			qp->pri.update_vid = 0;
1943 		}
1944 
1945 		if (qp->alt.vid < 0x1000) {
1946 			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1947 			qp->alt.vid = 0xFFFF;
1948 			qp->alt.candidate_vid = 0xFFFF;
1949 			qp->alt.update_vid = 0;
1950 		}
1951 	}
1952 out:
1953 	if (err && qp->counter_index)
1954 		mlx4_ib_free_qp_counter(dev, qp);
1955 	if (err && steer_qp)
1956 		mlx4_ib_steer_qp_reg(dev, qp, 0);
1957 	kfree(context);
1958 	if (qp->pri.candidate_smac ||
1959 	    (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1960 		if (err) {
1961 			mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1962 		} else {
1963 			if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1964 				mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1965 			qp->pri.smac = qp->pri.candidate_smac;
1966 			qp->pri.smac_index = qp->pri.candidate_smac_index;
1967 			qp->pri.smac_port = qp->pri.candidate_smac_port;
1968 		}
1969 		qp->pri.candidate_smac = 0;
1970 		qp->pri.candidate_smac_index = 0;
1971 		qp->pri.candidate_smac_port = 0;
1972 	}
1973 	if (qp->alt.candidate_smac) {
1974 		if (err) {
1975 			mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1976 		} else {
1977 			if (qp->alt.smac)
1978 				mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1979 			qp->alt.smac = qp->alt.candidate_smac;
1980 			qp->alt.smac_index = qp->alt.candidate_smac_index;
1981 			qp->alt.smac_port = qp->alt.candidate_smac_port;
1982 		}
1983 		qp->alt.candidate_smac = 0;
1984 		qp->alt.candidate_smac_index = 0;
1985 		qp->alt.candidate_smac_port = 0;
1986 	}
1987 
1988 	if (qp->pri.update_vid) {
1989 		if (err) {
1990 			if (qp->pri.candidate_vid < 0x1000)
1991 				mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1992 						     qp->pri.candidate_vid);
1993 		} else {
1994 			if (qp->pri.vid < 0x1000)
1995 				mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1996 						     qp->pri.vid);
1997 			qp->pri.vid = qp->pri.candidate_vid;
1998 			qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1999 			qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2000 		}
2001 		qp->pri.candidate_vid = 0xFFFF;
2002 		qp->pri.update_vid = 0;
2003 	}
2004 
2005 	if (qp->alt.update_vid) {
2006 		if (err) {
2007 			if (qp->alt.candidate_vid < 0x1000)
2008 				mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2009 						     qp->alt.candidate_vid);
2010 		} else {
2011 			if (qp->alt.vid < 0x1000)
2012 				mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2013 						     qp->alt.vid);
2014 			qp->alt.vid = qp->alt.candidate_vid;
2015 			qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2016 			qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2017 		}
2018 		qp->alt.candidate_vid = 0xFFFF;
2019 		qp->alt.update_vid = 0;
2020 	}
2021 
2022 	return err;
2023 }
2024 
2025 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2026 		      int attr_mask, struct ib_udata *udata)
2027 {
2028 	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2029 	struct mlx4_ib_qp *qp = to_mqp(ibqp);
2030 	enum ib_qp_state cur_state, new_state;
2031 	int err = -EINVAL;
2032 	int ll;
2033 	mutex_lock(&qp->mutex);
2034 
2035 	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2036 	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2037 
2038 	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2039 		ll = IB_LINK_LAYER_UNSPECIFIED;
2040 	} else {
2041 		int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2042 		ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2043 	}
2044 
2045 	if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2046 				attr_mask, ll)) {
2047 		pr_debug("qpn 0x%x: invalid attribute mask specified "
2048 			 "for transition %d to %d. qp_type %d,"
2049 			 " attr_mask 0x%x\n",
2050 			 ibqp->qp_num, cur_state, new_state,
2051 			 ibqp->qp_type, attr_mask);
2052 		goto out;
2053 	}
2054 
2055 	if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2056 		if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2057 			if ((ibqp->qp_type == IB_QPT_RC) ||
2058 			    (ibqp->qp_type == IB_QPT_UD) ||
2059 			    (ibqp->qp_type == IB_QPT_UC) ||
2060 			    (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2061 			    (ibqp->qp_type == IB_QPT_XRC_INI)) {
2062 				attr->port_num = mlx4_ib_bond_next_port(dev);
2063 			}
2064 		} else {
2065 			/* no sense in changing port_num
2066 			 * when ports are bonded */
2067 			attr_mask &= ~IB_QP_PORT;
2068 		}
2069 	}
2070 
2071 	if ((attr_mask & IB_QP_PORT) &&
2072 	    (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2073 		pr_debug("qpn 0x%x: invalid port number (%d) specified "
2074 			 "for transition %d to %d. qp_type %d\n",
2075 			 ibqp->qp_num, attr->port_num, cur_state,
2076 			 new_state, ibqp->qp_type);
2077 		goto out;
2078 	}
2079 
2080 	if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2081 	    (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2082 	     IB_LINK_LAYER_ETHERNET))
2083 		goto out;
2084 
2085 	if (attr_mask & IB_QP_PKEY_INDEX) {
2086 		int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2087 		if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2088 			pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2089 				 "for transition %d to %d. qp_type %d\n",
2090 				 ibqp->qp_num, attr->pkey_index, cur_state,
2091 				 new_state, ibqp->qp_type);
2092 			goto out;
2093 		}
2094 	}
2095 
2096 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2097 	    attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2098 		pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2099 			 "Transition %d to %d. qp_type %d\n",
2100 			 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2101 			 new_state, ibqp->qp_type);
2102 		goto out;
2103 	}
2104 
2105 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2106 	    attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2107 		pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2108 			 "Transition %d to %d. qp_type %d\n",
2109 			 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2110 			 new_state, ibqp->qp_type);
2111 		goto out;
2112 	}
2113 
2114 	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2115 		err = 0;
2116 		goto out;
2117 	}
2118 
2119 	err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2120 
2121 	if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2122 		attr->port_num = 1;
2123 
2124 out:
2125 	mutex_unlock(&qp->mutex);
2126 	return err;
2127 }
2128 
2129 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2130 {
2131 	int i;
2132 	for (i = 0; i < dev->caps.num_ports; i++) {
2133 		if (qpn == dev->caps.qp0_proxy[i] ||
2134 		    qpn == dev->caps.qp0_tunnel[i]) {
2135 			*qkey = dev->caps.qp0_qkey[i];
2136 			return 0;
2137 		}
2138 	}
2139 	return -EINVAL;
2140 }
2141 
2142 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2143 				  struct ib_ud_wr *wr,
2144 				  void *wqe, unsigned *mlx_seg_len)
2145 {
2146 	struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2147 	struct ib_device *ib_dev = &mdev->ib_dev;
2148 	struct mlx4_wqe_mlx_seg *mlx = wqe;
2149 	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2150 	struct mlx4_ib_ah *ah = to_mah(wr->ah);
2151 	u16 pkey;
2152 	u32 qkey;
2153 	int send_size;
2154 	int header_size;
2155 	int spc;
2156 	int i;
2157 
2158 	if (wr->wr.opcode != IB_WR_SEND)
2159 		return -EINVAL;
2160 
2161 	send_size = 0;
2162 
2163 	for (i = 0; i < wr->wr.num_sge; ++i)
2164 		send_size += wr->wr.sg_list[i].length;
2165 
2166 	/* for proxy-qp0 sends, need to add in size of tunnel header */
2167 	/* for tunnel-qp0 sends, tunnel header is already in s/g list */
2168 	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2169 		send_size += sizeof (struct mlx4_ib_tunnel_header);
2170 
2171 	ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2172 
2173 	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2174 		sqp->ud_header.lrh.service_level =
2175 			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2176 		sqp->ud_header.lrh.destination_lid =
2177 			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2178 		sqp->ud_header.lrh.source_lid =
2179 			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2180 	}
2181 
2182 	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2183 
2184 	/* force loopback */
2185 	mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2186 	mlx->rlid = sqp->ud_header.lrh.destination_lid;
2187 
2188 	sqp->ud_header.lrh.virtual_lane    = 0;
2189 	sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2190 	ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2191 	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2192 	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2193 		sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2194 	else
2195 		sqp->ud_header.bth.destination_qpn =
2196 			cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2197 
2198 	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2199 	if (mlx4_is_master(mdev->dev)) {
2200 		if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2201 			return -EINVAL;
2202 	} else {
2203 		if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2204 			return -EINVAL;
2205 	}
2206 	sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2207 	sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2208 
2209 	sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2210 	sqp->ud_header.immediate_present = 0;
2211 
2212 	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2213 
2214 	/*
2215 	 * Inline data segments may not cross a 64 byte boundary.  If
2216 	 * our UD header is bigger than the space available up to the
2217 	 * next 64 byte boundary in the WQE, use two inline data
2218 	 * segments to hold the UD header.
2219 	 */
2220 	spc = MLX4_INLINE_ALIGN -
2221 	      ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2222 	if (header_size <= spc) {
2223 		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2224 		memcpy(inl + 1, sqp->header_buf, header_size);
2225 		i = 1;
2226 	} else {
2227 		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2228 		memcpy(inl + 1, sqp->header_buf, spc);
2229 
2230 		inl = (void *) (inl + 1) + spc;
2231 		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2232 		/*
2233 		 * Need a barrier here to make sure all the data is
2234 		 * visible before the byte_count field is set.
2235 		 * Otherwise the HCA prefetcher could grab the 64-byte
2236 		 * chunk with this inline segment and get a valid (!=
2237 		 * 0xffffffff) byte count but stale data, and end up
2238 		 * generating a packet with bad headers.
2239 		 *
2240 		 * The first inline segment's byte_count field doesn't
2241 		 * need a barrier, because it comes after a
2242 		 * control/MLX segment and therefore is at an offset
2243 		 * of 16 mod 64.
2244 		 */
2245 		wmb();
2246 		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2247 		i = 2;
2248 	}
2249 
2250 	*mlx_seg_len =
2251 	ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2252 	return 0;
2253 }
2254 
2255 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2256 {
2257 	int i;
2258 
2259 	for (i = ETH_ALEN; i; i--) {
2260 		dst_mac[i - 1] = src_mac & 0xff;
2261 		src_mac >>= 8;
2262 	}
2263 }
2264 
2265 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2266 			    void *wqe, unsigned *mlx_seg_len)
2267 {
2268 	struct ib_device *ib_dev = sqp->qp.ibqp.device;
2269 	struct mlx4_wqe_mlx_seg *mlx = wqe;
2270 	struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2271 	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2272 	struct mlx4_ib_ah *ah = to_mah(wr->ah);
2273 	union ib_gid sgid;
2274 	u16 pkey;
2275 	int send_size;
2276 	int header_size;
2277 	int spc;
2278 	int i;
2279 	int err = 0;
2280 	u16 vlan = 0xffff;
2281 	bool is_eth;
2282 	bool is_vlan = false;
2283 	bool is_grh;
2284 
2285 	send_size = 0;
2286 	for (i = 0; i < wr->wr.num_sge; ++i)
2287 		send_size += wr->wr.sg_list[i].length;
2288 
2289 	is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2290 	is_grh = mlx4_ib_ah_grh_present(ah);
2291 	if (is_eth) {
2292 		if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2293 			/* When multi-function is enabled, the ib_core gid
2294 			 * indexes don't necessarily match the hw ones, so
2295 			 * we must use our own cache */
2296 			err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2297 							   be32_to_cpu(ah->av.ib.port_pd) >> 24,
2298 							   ah->av.ib.gid_index, &sgid.raw[0]);
2299 			if (err)
2300 				return err;
2301 		} else  {
2302 			err = ib_get_cached_gid(ib_dev,
2303 						be32_to_cpu(ah->av.ib.port_pd) >> 24,
2304 						ah->av.ib.gid_index, &sgid,
2305 						NULL);
2306 			if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2307 				err = -ENOENT;
2308 			if (err)
2309 				return err;
2310 		}
2311 
2312 		if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2313 			vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2314 			is_vlan = 1;
2315 		}
2316 	}
2317 	ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2318 
2319 	if (!is_eth) {
2320 		sqp->ud_header.lrh.service_level =
2321 			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2322 		sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2323 		sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2324 	}
2325 
2326 	if (is_grh) {
2327 		sqp->ud_header.grh.traffic_class =
2328 			(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2329 		sqp->ud_header.grh.flow_label    =
2330 			ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2331 		sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2332 		if (is_eth)
2333 			memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2334 		else {
2335 		if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2336 			/* When multi-function is enabled, the ib_core gid
2337 			 * indexes don't necessarily match the hw ones, so
2338 			 * we must use our own cache */
2339 			sqp->ud_header.grh.source_gid.global.subnet_prefix =
2340 				to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2341 						       subnet_prefix;
2342 			sqp->ud_header.grh.source_gid.global.interface_id =
2343 				to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2344 					       guid_cache[ah->av.ib.gid_index];
2345 		} else
2346 			ib_get_cached_gid(ib_dev,
2347 					  be32_to_cpu(ah->av.ib.port_pd) >> 24,
2348 					  ah->av.ib.gid_index,
2349 					  &sqp->ud_header.grh.source_gid, NULL);
2350 		}
2351 		memcpy(sqp->ud_header.grh.destination_gid.raw,
2352 		       ah->av.ib.dgid, 16);
2353 	}
2354 
2355 	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2356 
2357 	if (!is_eth) {
2358 		mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2359 					  (sqp->ud_header.lrh.destination_lid ==
2360 					   IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2361 					  (sqp->ud_header.lrh.service_level << 8));
2362 		if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2363 			mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2364 		mlx->rlid = sqp->ud_header.lrh.destination_lid;
2365 	}
2366 
2367 	switch (wr->wr.opcode) {
2368 	case IB_WR_SEND:
2369 		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY;
2370 		sqp->ud_header.immediate_present = 0;
2371 		break;
2372 	case IB_WR_SEND_WITH_IMM:
2373 		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2374 		sqp->ud_header.immediate_present = 1;
2375 		sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
2376 		break;
2377 	default:
2378 		return -EINVAL;
2379 	}
2380 
2381 	if (is_eth) {
2382 		struct in6_addr in6;
2383 
2384 		u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2385 
2386 		mlx->sched_prio = cpu_to_be16(pcp);
2387 
2388 		memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2389 		/* FIXME: cache smac value? */
2390 		memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2391 		memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2392 		memcpy(&in6, sgid.raw, sizeof(in6));
2393 
2394 		if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2395 			u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2396 			u8 smac[ETH_ALEN];
2397 
2398 			mlx4_u64_to_smac(smac, mac);
2399 			memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2400 		} else {
2401 			/* use the src mac of the tunnel */
2402 			memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2403 		}
2404 
2405 		if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2406 			mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2407 		if (!is_vlan) {
2408 			sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2409 		} else {
2410 			sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2411 			sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2412 		}
2413 	} else {
2414 		sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2415 		if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2416 			sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2417 	}
2418 	sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2419 	if (!sqp->qp.ibqp.qp_num)
2420 		ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2421 	else
2422 		ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
2423 	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2424 	sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2425 	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2426 	sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2427 					       sqp->qkey : wr->remote_qkey);
2428 	sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2429 
2430 	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2431 
2432 	if (0) {
2433 		pr_err("built UD header of size %d:\n", header_size);
2434 		for (i = 0; i < header_size / 4; ++i) {
2435 			if (i % 8 == 0)
2436 				pr_err("  [%02x] ", i * 4);
2437 			pr_cont(" %08x",
2438 				be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2439 			if ((i + 1) % 8 == 0)
2440 				pr_cont("\n");
2441 		}
2442 		pr_err("\n");
2443 	}
2444 
2445 	/*
2446 	 * Inline data segments may not cross a 64 byte boundary.  If
2447 	 * our UD header is bigger than the space available up to the
2448 	 * next 64 byte boundary in the WQE, use two inline data
2449 	 * segments to hold the UD header.
2450 	 */
2451 	spc = MLX4_INLINE_ALIGN -
2452 		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2453 	if (header_size <= spc) {
2454 		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2455 		memcpy(inl + 1, sqp->header_buf, header_size);
2456 		i = 1;
2457 	} else {
2458 		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2459 		memcpy(inl + 1, sqp->header_buf, spc);
2460 
2461 		inl = (void *) (inl + 1) + spc;
2462 		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2463 		/*
2464 		 * Need a barrier here to make sure all the data is
2465 		 * visible before the byte_count field is set.
2466 		 * Otherwise the HCA prefetcher could grab the 64-byte
2467 		 * chunk with this inline segment and get a valid (!=
2468 		 * 0xffffffff) byte count but stale data, and end up
2469 		 * generating a packet with bad headers.
2470 		 *
2471 		 * The first inline segment's byte_count field doesn't
2472 		 * need a barrier, because it comes after a
2473 		 * control/MLX segment and therefore is at an offset
2474 		 * of 16 mod 64.
2475 		 */
2476 		wmb();
2477 		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2478 		i = 2;
2479 	}
2480 
2481 	*mlx_seg_len =
2482 		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2483 	return 0;
2484 }
2485 
2486 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2487 {
2488 	unsigned cur;
2489 	struct mlx4_ib_cq *cq;
2490 
2491 	cur = wq->head - wq->tail;
2492 	if (likely(cur + nreq < wq->max_post))
2493 		return 0;
2494 
2495 	cq = to_mcq(ib_cq);
2496 	spin_lock(&cq->lock);
2497 	cur = wq->head - wq->tail;
2498 	spin_unlock(&cq->lock);
2499 
2500 	return cur + nreq >= wq->max_post;
2501 }
2502 
2503 static __be32 convert_access(int acc)
2504 {
2505 	return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2506 		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2507 	       (acc & IB_ACCESS_REMOTE_WRITE  ?
2508 		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2509 	       (acc & IB_ACCESS_REMOTE_READ   ?
2510 		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2511 	       (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2512 		cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2513 }
2514 
2515 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2516 			struct ib_reg_wr *wr)
2517 {
2518 	struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2519 
2520 	fseg->flags		= convert_access(wr->access);
2521 	fseg->mem_key		= cpu_to_be32(wr->key);
2522 	fseg->buf_list		= cpu_to_be64(mr->page_map);
2523 	fseg->start_addr	= cpu_to_be64(mr->ibmr.iova);
2524 	fseg->reg_len		= cpu_to_be64(mr->ibmr.length);
2525 	fseg->offset		= 0; /* XXX -- is this just for ZBVA? */
2526 	fseg->page_size		= cpu_to_be32(ilog2(mr->ibmr.page_size));
2527 	fseg->reserved[0]	= 0;
2528 	fseg->reserved[1]	= 0;
2529 }
2530 
2531 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg,
2532 		struct ib_bind_mw_wr *wr)
2533 {
2534 	bseg->flags1 =
2535 		convert_access(wr->bind_info.mw_access_flags) &
2536 		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2537 			    MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2538 			    MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2539 	bseg->flags2 = 0;
2540 	if (wr->mw->type == IB_MW_TYPE_2)
2541 		bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2542 	if (wr->bind_info.mw_access_flags & IB_ZERO_BASED)
2543 		bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2544 	bseg->new_rkey = cpu_to_be32(wr->rkey);
2545 	bseg->lkey = cpu_to_be32(wr->bind_info.mr->lkey);
2546 	bseg->addr = cpu_to_be64(wr->bind_info.addr);
2547 	bseg->length = cpu_to_be64(wr->bind_info.length);
2548 }
2549 
2550 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2551 {
2552 	memset(iseg, 0, sizeof(*iseg));
2553 	iseg->mem_key = cpu_to_be32(rkey);
2554 }
2555 
2556 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2557 					  u64 remote_addr, u32 rkey)
2558 {
2559 	rseg->raddr    = cpu_to_be64(remote_addr);
2560 	rseg->rkey     = cpu_to_be32(rkey);
2561 	rseg->reserved = 0;
2562 }
2563 
2564 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2565 		struct ib_atomic_wr *wr)
2566 {
2567 	if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2568 		aseg->swap_add = cpu_to_be64(wr->swap);
2569 		aseg->compare  = cpu_to_be64(wr->compare_add);
2570 	} else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2571 		aseg->swap_add = cpu_to_be64(wr->compare_add);
2572 		aseg->compare  = cpu_to_be64(wr->compare_add_mask);
2573 	} else {
2574 		aseg->swap_add = cpu_to_be64(wr->compare_add);
2575 		aseg->compare  = 0;
2576 	}
2577 
2578 }
2579 
2580 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2581 				  struct ib_atomic_wr *wr)
2582 {
2583 	aseg->swap_add		= cpu_to_be64(wr->swap);
2584 	aseg->swap_add_mask	= cpu_to_be64(wr->swap_mask);
2585 	aseg->compare		= cpu_to_be64(wr->compare_add);
2586 	aseg->compare_mask	= cpu_to_be64(wr->compare_add_mask);
2587 }
2588 
2589 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2590 			     struct ib_ud_wr *wr)
2591 {
2592 	memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2593 	dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2594 	dseg->qkey = cpu_to_be32(wr->remote_qkey);
2595 	dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2596 	memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2597 }
2598 
2599 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2600 				    struct mlx4_wqe_datagram_seg *dseg,
2601 				    struct ib_ud_wr *wr,
2602 				    enum mlx4_ib_qp_type qpt)
2603 {
2604 	union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2605 	struct mlx4_av sqp_av = {0};
2606 	int port = *((u8 *) &av->ib.port_pd) & 0x3;
2607 
2608 	/* force loopback */
2609 	sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2610 	sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2611 	sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2612 			cpu_to_be32(0xf0000000);
2613 
2614 	memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2615 	if (qpt == MLX4_IB_QPT_PROXY_GSI)
2616 		dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2617 	else
2618 		dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2619 	/* Use QKEY from the QP context, which is set by master */
2620 	dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2621 }
2622 
2623 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2624 {
2625 	struct mlx4_wqe_inline_seg *inl = wqe;
2626 	struct mlx4_ib_tunnel_header hdr;
2627 	struct mlx4_ib_ah *ah = to_mah(wr->ah);
2628 	int spc;
2629 	int i;
2630 
2631 	memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2632 	hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2633 	hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2634 	hdr.qkey = cpu_to_be32(wr->remote_qkey);
2635 	memcpy(hdr.mac, ah->av.eth.mac, 6);
2636 	hdr.vlan = ah->av.eth.vlan;
2637 
2638 	spc = MLX4_INLINE_ALIGN -
2639 		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2640 	if (sizeof (hdr) <= spc) {
2641 		memcpy(inl + 1, &hdr, sizeof (hdr));
2642 		wmb();
2643 		inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2644 		i = 1;
2645 	} else {
2646 		memcpy(inl + 1, &hdr, spc);
2647 		wmb();
2648 		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2649 
2650 		inl = (void *) (inl + 1) + spc;
2651 		memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2652 		wmb();
2653 		inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2654 		i = 2;
2655 	}
2656 
2657 	*mlx_seg_len =
2658 		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2659 }
2660 
2661 static void set_mlx_icrc_seg(void *dseg)
2662 {
2663 	u32 *t = dseg;
2664 	struct mlx4_wqe_inline_seg *iseg = dseg;
2665 
2666 	t[1] = 0;
2667 
2668 	/*
2669 	 * Need a barrier here before writing the byte_count field to
2670 	 * make sure that all the data is visible before the
2671 	 * byte_count field is set.  Otherwise, if the segment begins
2672 	 * a new cacheline, the HCA prefetcher could grab the 64-byte
2673 	 * chunk and get a valid (!= * 0xffffffff) byte count but
2674 	 * stale data, and end up sending the wrong data.
2675 	 */
2676 	wmb();
2677 
2678 	iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2679 }
2680 
2681 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2682 {
2683 	dseg->lkey       = cpu_to_be32(sg->lkey);
2684 	dseg->addr       = cpu_to_be64(sg->addr);
2685 
2686 	/*
2687 	 * Need a barrier here before writing the byte_count field to
2688 	 * make sure that all the data is visible before the
2689 	 * byte_count field is set.  Otherwise, if the segment begins
2690 	 * a new cacheline, the HCA prefetcher could grab the 64-byte
2691 	 * chunk and get a valid (!= * 0xffffffff) byte count but
2692 	 * stale data, and end up sending the wrong data.
2693 	 */
2694 	wmb();
2695 
2696 	dseg->byte_count = cpu_to_be32(sg->length);
2697 }
2698 
2699 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2700 {
2701 	dseg->byte_count = cpu_to_be32(sg->length);
2702 	dseg->lkey       = cpu_to_be32(sg->lkey);
2703 	dseg->addr       = cpu_to_be64(sg->addr);
2704 }
2705 
2706 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2707 			 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2708 			 __be32 *lso_hdr_sz, __be32 *blh)
2709 {
2710 	unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2711 
2712 	if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2713 		*blh = cpu_to_be32(1 << 6);
2714 
2715 	if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2716 		     wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2717 		return -EINVAL;
2718 
2719 	memcpy(wqe->header, wr->header, wr->hlen);
2720 
2721 	*lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
2722 	*lso_seg_len = halign;
2723 	return 0;
2724 }
2725 
2726 static __be32 send_ieth(struct ib_send_wr *wr)
2727 {
2728 	switch (wr->opcode) {
2729 	case IB_WR_SEND_WITH_IMM:
2730 	case IB_WR_RDMA_WRITE_WITH_IMM:
2731 		return wr->ex.imm_data;
2732 
2733 	case IB_WR_SEND_WITH_INV:
2734 		return cpu_to_be32(wr->ex.invalidate_rkey);
2735 
2736 	default:
2737 		return 0;
2738 	}
2739 }
2740 
2741 static void add_zero_len_inline(void *wqe)
2742 {
2743 	struct mlx4_wqe_inline_seg *inl = wqe;
2744 	memset(wqe, 0, 16);
2745 	inl->byte_count = cpu_to_be32(1 << 31);
2746 }
2747 
2748 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2749 		      struct ib_send_wr **bad_wr)
2750 {
2751 	struct mlx4_ib_qp *qp = to_mqp(ibqp);
2752 	void *wqe;
2753 	struct mlx4_wqe_ctrl_seg *ctrl;
2754 	struct mlx4_wqe_data_seg *dseg;
2755 	unsigned long flags;
2756 	int nreq;
2757 	int err = 0;
2758 	unsigned ind;
2759 	int uninitialized_var(stamp);
2760 	int uninitialized_var(size);
2761 	unsigned uninitialized_var(seglen);
2762 	__be32 dummy;
2763 	__be32 *lso_wqe;
2764 	__be32 uninitialized_var(lso_hdr_sz);
2765 	__be32 blh;
2766 	int i;
2767 	struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2768 
2769 	spin_lock_irqsave(&qp->sq.lock, flags);
2770 	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2771 		err = -EIO;
2772 		*bad_wr = wr;
2773 		nreq = 0;
2774 		goto out;
2775 	}
2776 
2777 	ind = qp->sq_next_wqe;
2778 
2779 	for (nreq = 0; wr; ++nreq, wr = wr->next) {
2780 		lso_wqe = &dummy;
2781 		blh = 0;
2782 
2783 		if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2784 			err = -ENOMEM;
2785 			*bad_wr = wr;
2786 			goto out;
2787 		}
2788 
2789 		if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2790 			err = -EINVAL;
2791 			*bad_wr = wr;
2792 			goto out;
2793 		}
2794 
2795 		ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2796 		qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2797 
2798 		ctrl->srcrb_flags =
2799 			(wr->send_flags & IB_SEND_SIGNALED ?
2800 			 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2801 			(wr->send_flags & IB_SEND_SOLICITED ?
2802 			 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2803 			((wr->send_flags & IB_SEND_IP_CSUM) ?
2804 			 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2805 				     MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2806 			qp->sq_signal_bits;
2807 
2808 		ctrl->imm = send_ieth(wr);
2809 
2810 		wqe += sizeof *ctrl;
2811 		size = sizeof *ctrl / 16;
2812 
2813 		switch (qp->mlx4_ib_qp_type) {
2814 		case MLX4_IB_QPT_RC:
2815 		case MLX4_IB_QPT_UC:
2816 			switch (wr->opcode) {
2817 			case IB_WR_ATOMIC_CMP_AND_SWP:
2818 			case IB_WR_ATOMIC_FETCH_AND_ADD:
2819 			case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2820 				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2821 					      atomic_wr(wr)->rkey);
2822 				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2823 
2824 				set_atomic_seg(wqe, atomic_wr(wr));
2825 				wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2826 
2827 				size += (sizeof (struct mlx4_wqe_raddr_seg) +
2828 					 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2829 
2830 				break;
2831 
2832 			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2833 				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2834 					      atomic_wr(wr)->rkey);
2835 				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2836 
2837 				set_masked_atomic_seg(wqe, atomic_wr(wr));
2838 				wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2839 
2840 				size += (sizeof (struct mlx4_wqe_raddr_seg) +
2841 					 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2842 
2843 				break;
2844 
2845 			case IB_WR_RDMA_READ:
2846 			case IB_WR_RDMA_WRITE:
2847 			case IB_WR_RDMA_WRITE_WITH_IMM:
2848 				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2849 					      rdma_wr(wr)->rkey);
2850 				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2851 				size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2852 				break;
2853 
2854 			case IB_WR_LOCAL_INV:
2855 				ctrl->srcrb_flags |=
2856 					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2857 				set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2858 				wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2859 				size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2860 				break;
2861 
2862 			case IB_WR_REG_MR:
2863 				ctrl->srcrb_flags |=
2864 					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2865 				set_reg_seg(wqe, reg_wr(wr));
2866 				wqe  += sizeof(struct mlx4_wqe_fmr_seg);
2867 				size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2868 				break;
2869 
2870 			case IB_WR_BIND_MW:
2871 				ctrl->srcrb_flags |=
2872 					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2873 				set_bind_seg(wqe, bind_mw_wr(wr));
2874 				wqe  += sizeof(struct mlx4_wqe_bind_seg);
2875 				size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2876 				break;
2877 			default:
2878 				/* No extra segments required for sends */
2879 				break;
2880 			}
2881 			break;
2882 
2883 		case MLX4_IB_QPT_TUN_SMI_OWNER:
2884 			err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2885 					ctrl, &seglen);
2886 			if (unlikely(err)) {
2887 				*bad_wr = wr;
2888 				goto out;
2889 			}
2890 			wqe  += seglen;
2891 			size += seglen / 16;
2892 			break;
2893 		case MLX4_IB_QPT_TUN_SMI:
2894 		case MLX4_IB_QPT_TUN_GSI:
2895 			/* this is a UD qp used in MAD responses to slaves. */
2896 			set_datagram_seg(wqe, ud_wr(wr));
2897 			/* set the forced-loopback bit in the data seg av */
2898 			*(__be32 *) wqe |= cpu_to_be32(0x80000000);
2899 			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2900 			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2901 			break;
2902 		case MLX4_IB_QPT_UD:
2903 			set_datagram_seg(wqe, ud_wr(wr));
2904 			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2905 			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2906 
2907 			if (wr->opcode == IB_WR_LSO) {
2908 				err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2909 						&lso_hdr_sz, &blh);
2910 				if (unlikely(err)) {
2911 					*bad_wr = wr;
2912 					goto out;
2913 				}
2914 				lso_wqe = (__be32 *) wqe;
2915 				wqe  += seglen;
2916 				size += seglen / 16;
2917 			}
2918 			break;
2919 
2920 		case MLX4_IB_QPT_PROXY_SMI_OWNER:
2921 			err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2922 					ctrl, &seglen);
2923 			if (unlikely(err)) {
2924 				*bad_wr = wr;
2925 				goto out;
2926 			}
2927 			wqe  += seglen;
2928 			size += seglen / 16;
2929 			/* to start tunnel header on a cache-line boundary */
2930 			add_zero_len_inline(wqe);
2931 			wqe += 16;
2932 			size++;
2933 			build_tunnel_header(ud_wr(wr), wqe, &seglen);
2934 			wqe  += seglen;
2935 			size += seglen / 16;
2936 			break;
2937 		case MLX4_IB_QPT_PROXY_SMI:
2938 		case MLX4_IB_QPT_PROXY_GSI:
2939 			/* If we are tunneling special qps, this is a UD qp.
2940 			 * In this case we first add a UD segment targeting
2941 			 * the tunnel qp, and then add a header with address
2942 			 * information */
2943 			set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2944 						ud_wr(wr),
2945 						qp->mlx4_ib_qp_type);
2946 			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2947 			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2948 			build_tunnel_header(ud_wr(wr), wqe, &seglen);
2949 			wqe  += seglen;
2950 			size += seglen / 16;
2951 			break;
2952 
2953 		case MLX4_IB_QPT_SMI:
2954 		case MLX4_IB_QPT_GSI:
2955 			err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2956 					&seglen);
2957 			if (unlikely(err)) {
2958 				*bad_wr = wr;
2959 				goto out;
2960 			}
2961 			wqe  += seglen;
2962 			size += seglen / 16;
2963 			break;
2964 
2965 		default:
2966 			break;
2967 		}
2968 
2969 		/*
2970 		 * Write data segments in reverse order, so as to
2971 		 * overwrite cacheline stamp last within each
2972 		 * cacheline.  This avoids issues with WQE
2973 		 * prefetching.
2974 		 */
2975 
2976 		dseg = wqe;
2977 		dseg += wr->num_sge - 1;
2978 		size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2979 
2980 		/* Add one more inline data segment for ICRC for MLX sends */
2981 		if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2982 			     qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2983 			     qp->mlx4_ib_qp_type &
2984 			     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2985 			set_mlx_icrc_seg(dseg + 1);
2986 			size += sizeof (struct mlx4_wqe_data_seg) / 16;
2987 		}
2988 
2989 		for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2990 			set_data_seg(dseg, wr->sg_list + i);
2991 
2992 		/*
2993 		 * Possibly overwrite stamping in cacheline with LSO
2994 		 * segment only after making sure all data segments
2995 		 * are written.
2996 		 */
2997 		wmb();
2998 		*lso_wqe = lso_hdr_sz;
2999 
3000 		ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
3001 				    MLX4_WQE_CTRL_FENCE : 0) | size;
3002 
3003 		/*
3004 		 * Make sure descriptor is fully written before
3005 		 * setting ownership bit (because HW can start
3006 		 * executing as soon as we do).
3007 		 */
3008 		wmb();
3009 
3010 		if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3011 			*bad_wr = wr;
3012 			err = -EINVAL;
3013 			goto out;
3014 		}
3015 
3016 		ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3017 			(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3018 
3019 		stamp = ind + qp->sq_spare_wqes;
3020 		ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3021 
3022 		/*
3023 		 * We can improve latency by not stamping the last
3024 		 * send queue WQE until after ringing the doorbell, so
3025 		 * only stamp here if there are still more WQEs to post.
3026 		 *
3027 		 * Same optimization applies to padding with NOP wqe
3028 		 * in case of WQE shrinking (used to prevent wrap-around
3029 		 * in the middle of WR).
3030 		 */
3031 		if (wr->next) {
3032 			stamp_send_wqe(qp, stamp, size * 16);
3033 			ind = pad_wraparound(qp, ind);
3034 		}
3035 	}
3036 
3037 out:
3038 	if (likely(nreq)) {
3039 		qp->sq.head += nreq;
3040 
3041 		/*
3042 		 * Make sure that descriptors are written before
3043 		 * doorbell record.
3044 		 */
3045 		wmb();
3046 
3047 		writel(qp->doorbell_qpn,
3048 		       to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3049 
3050 		/*
3051 		 * Make sure doorbells don't leak out of SQ spinlock
3052 		 * and reach the HCA out of order.
3053 		 */
3054 		mmiowb();
3055 
3056 		stamp_send_wqe(qp, stamp, size * 16);
3057 
3058 		ind = pad_wraparound(qp, ind);
3059 		qp->sq_next_wqe = ind;
3060 	}
3061 
3062 	spin_unlock_irqrestore(&qp->sq.lock, flags);
3063 
3064 	return err;
3065 }
3066 
3067 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3068 		      struct ib_recv_wr **bad_wr)
3069 {
3070 	struct mlx4_ib_qp *qp = to_mqp(ibqp);
3071 	struct mlx4_wqe_data_seg *scat;
3072 	unsigned long flags;
3073 	int err = 0;
3074 	int nreq;
3075 	int ind;
3076 	int max_gs;
3077 	int i;
3078 	struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3079 
3080 	max_gs = qp->rq.max_gs;
3081 	spin_lock_irqsave(&qp->rq.lock, flags);
3082 
3083 	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3084 		err = -EIO;
3085 		*bad_wr = wr;
3086 		nreq = 0;
3087 		goto out;
3088 	}
3089 
3090 	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3091 
3092 	for (nreq = 0; wr; ++nreq, wr = wr->next) {
3093 		if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3094 			err = -ENOMEM;
3095 			*bad_wr = wr;
3096 			goto out;
3097 		}
3098 
3099 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3100 			err = -EINVAL;
3101 			*bad_wr = wr;
3102 			goto out;
3103 		}
3104 
3105 		scat = get_recv_wqe(qp, ind);
3106 
3107 		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3108 		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3109 			ib_dma_sync_single_for_device(ibqp->device,
3110 						      qp->sqp_proxy_rcv[ind].map,
3111 						      sizeof (struct mlx4_ib_proxy_sqp_hdr),
3112 						      DMA_FROM_DEVICE);
3113 			scat->byte_count =
3114 				cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3115 			/* use dma lkey from upper layer entry */
3116 			scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3117 			scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3118 			scat++;
3119 			max_gs--;
3120 		}
3121 
3122 		for (i = 0; i < wr->num_sge; ++i)
3123 			__set_data_seg(scat + i, wr->sg_list + i);
3124 
3125 		if (i < max_gs) {
3126 			scat[i].byte_count = 0;
3127 			scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3128 			scat[i].addr       = 0;
3129 		}
3130 
3131 		qp->rq.wrid[ind] = wr->wr_id;
3132 
3133 		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3134 	}
3135 
3136 out:
3137 	if (likely(nreq)) {
3138 		qp->rq.head += nreq;
3139 
3140 		/*
3141 		 * Make sure that descriptors are written before
3142 		 * doorbell record.
3143 		 */
3144 		wmb();
3145 
3146 		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3147 	}
3148 
3149 	spin_unlock_irqrestore(&qp->rq.lock, flags);
3150 
3151 	return err;
3152 }
3153 
3154 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3155 {
3156 	switch (mlx4_state) {
3157 	case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3158 	case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3159 	case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3160 	case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3161 	case MLX4_QP_STATE_SQ_DRAINING:
3162 	case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3163 	case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3164 	case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3165 	default:		     return -1;
3166 	}
3167 }
3168 
3169 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3170 {
3171 	switch (mlx4_mig_state) {
3172 	case MLX4_QP_PM_ARMED:		return IB_MIG_ARMED;
3173 	case MLX4_QP_PM_REARM:		return IB_MIG_REARM;
3174 	case MLX4_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
3175 	default: return -1;
3176 	}
3177 }
3178 
3179 static int to_ib_qp_access_flags(int mlx4_flags)
3180 {
3181 	int ib_flags = 0;
3182 
3183 	if (mlx4_flags & MLX4_QP_BIT_RRE)
3184 		ib_flags |= IB_ACCESS_REMOTE_READ;
3185 	if (mlx4_flags & MLX4_QP_BIT_RWE)
3186 		ib_flags |= IB_ACCESS_REMOTE_WRITE;
3187 	if (mlx4_flags & MLX4_QP_BIT_RAE)
3188 		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3189 
3190 	return ib_flags;
3191 }
3192 
3193 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3194 				struct mlx4_qp_path *path)
3195 {
3196 	struct mlx4_dev *dev = ibdev->dev;
3197 	int is_eth;
3198 
3199 	memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3200 	ib_ah_attr->port_num	  = path->sched_queue & 0x40 ? 2 : 1;
3201 
3202 	if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3203 		return;
3204 
3205 	is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3206 		IB_LINK_LAYER_ETHERNET;
3207 	if (is_eth)
3208 		ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3209 		((path->sched_queue & 4) << 1);
3210 	else
3211 		ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3212 
3213 	ib_ah_attr->dlid	  = be16_to_cpu(path->rlid);
3214 	ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3215 	ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3216 	ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3217 	if (ib_ah_attr->ah_flags) {
3218 		ib_ah_attr->grh.sgid_index = path->mgid_index;
3219 		ib_ah_attr->grh.hop_limit  = path->hop_limit;
3220 		ib_ah_attr->grh.traffic_class =
3221 			(be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3222 		ib_ah_attr->grh.flow_label =
3223 			be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3224 		memcpy(ib_ah_attr->grh.dgid.raw,
3225 			path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3226 	}
3227 }
3228 
3229 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3230 		     struct ib_qp_init_attr *qp_init_attr)
3231 {
3232 	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3233 	struct mlx4_ib_qp *qp = to_mqp(ibqp);
3234 	struct mlx4_qp_context context;
3235 	int mlx4_state;
3236 	int err = 0;
3237 
3238 	mutex_lock(&qp->mutex);
3239 
3240 	if (qp->state == IB_QPS_RESET) {
3241 		qp_attr->qp_state = IB_QPS_RESET;
3242 		goto done;
3243 	}
3244 
3245 	err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3246 	if (err) {
3247 		err = -EINVAL;
3248 		goto out;
3249 	}
3250 
3251 	mlx4_state = be32_to_cpu(context.flags) >> 28;
3252 
3253 	qp->state		     = to_ib_qp_state(mlx4_state);
3254 	qp_attr->qp_state	     = qp->state;
3255 	qp_attr->path_mtu	     = context.mtu_msgmax >> 5;
3256 	qp_attr->path_mig_state	     =
3257 		to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3258 	qp_attr->qkey		     = be32_to_cpu(context.qkey);
3259 	qp_attr->rq_psn		     = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3260 	qp_attr->sq_psn		     = be32_to_cpu(context.next_send_psn) & 0xffffff;
3261 	qp_attr->dest_qp_num	     = be32_to_cpu(context.remote_qpn) & 0xffffff;
3262 	qp_attr->qp_access_flags     =
3263 		to_ib_qp_access_flags(be32_to_cpu(context.params2));
3264 
3265 	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3266 		to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3267 		to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3268 		qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3269 		qp_attr->alt_port_num	= qp_attr->alt_ah_attr.port_num;
3270 	}
3271 
3272 	qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3273 	if (qp_attr->qp_state == IB_QPS_INIT)
3274 		qp_attr->port_num = qp->port;
3275 	else
3276 		qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3277 
3278 	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3279 	qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3280 
3281 	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3282 
3283 	qp_attr->max_dest_rd_atomic =
3284 		1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3285 	qp_attr->min_rnr_timer	    =
3286 		(be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3287 	qp_attr->timeout	    = context.pri_path.ackto >> 3;
3288 	qp_attr->retry_cnt	    = (be32_to_cpu(context.params1) >> 16) & 0x7;
3289 	qp_attr->rnr_retry	    = (be32_to_cpu(context.params1) >> 13) & 0x7;
3290 	qp_attr->alt_timeout	    = context.alt_path.ackto >> 3;
3291 
3292 done:
3293 	qp_attr->cur_qp_state	     = qp_attr->qp_state;
3294 	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3295 	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3296 
3297 	if (!ibqp->uobject) {
3298 		qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3299 		qp_attr->cap.max_send_sge = qp->sq.max_gs;
3300 	} else {
3301 		qp_attr->cap.max_send_wr  = 0;
3302 		qp_attr->cap.max_send_sge = 0;
3303 	}
3304 
3305 	/*
3306 	 * We don't support inline sends for kernel QPs (yet), and we
3307 	 * don't know what userspace's value should be.
3308 	 */
3309 	qp_attr->cap.max_inline_data = 0;
3310 
3311 	qp_init_attr->cap	     = qp_attr->cap;
3312 
3313 	qp_init_attr->create_flags = 0;
3314 	if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3315 		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3316 
3317 	if (qp->flags & MLX4_IB_QP_LSO)
3318 		qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3319 
3320 	if (qp->flags & MLX4_IB_QP_NETIF)
3321 		qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3322 
3323 	qp_init_attr->sq_sig_type =
3324 		qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3325 		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3326 
3327 out:
3328 	mutex_unlock(&qp->mutex);
3329 	return err;
3330 }
3331 
3332