1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/slab.h> 36 #include <linux/netdevice.h> 37 38 #include <rdma/ib_cache.h> 39 #include <rdma/ib_pack.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_mad.h> 42 43 #include <linux/mlx4/driver.h> 44 #include <linux/mlx4/qp.h> 45 46 #include "mlx4_ib.h" 47 #include "user.h" 48 49 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 50 struct mlx4_ib_cq *recv_cq); 51 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 52 struct mlx4_ib_cq *recv_cq); 53 54 enum { 55 MLX4_IB_ACK_REQ_FREQ = 8, 56 }; 57 58 enum { 59 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 60 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 61 MLX4_IB_LINK_TYPE_IB = 0, 62 MLX4_IB_LINK_TYPE_ETH = 1 63 }; 64 65 enum { 66 /* 67 * Largest possible UD header: send with GRH and immediate 68 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 69 * tag. (LRH would only use 8 bytes, so Ethernet is the 70 * biggest case) 71 */ 72 MLX4_IB_UD_HEADER_SIZE = 82, 73 MLX4_IB_LSO_HEADER_SPARE = 128, 74 }; 75 76 enum { 77 MLX4_IB_IBOE_ETHERTYPE = 0x8915 78 }; 79 80 struct mlx4_ib_sqp { 81 struct mlx4_ib_qp qp; 82 int pkey_index; 83 u32 qkey; 84 u32 send_psn; 85 struct ib_ud_header ud_header; 86 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 87 }; 88 89 enum { 90 MLX4_IB_MIN_SQ_STRIDE = 6, 91 MLX4_IB_CACHE_LINE_SIZE = 64, 92 }; 93 94 enum { 95 MLX4_RAW_QP_MTU = 7, 96 MLX4_RAW_QP_MSGMAX = 31, 97 }; 98 99 #ifndef ETH_ALEN 100 #define ETH_ALEN 6 101 #endif 102 103 static const __be32 mlx4_ib_opcode[] = { 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 114 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 117 [IB_WR_BIND_MW] = cpu_to_be32(MLX4_OPCODE_BIND_MW), 118 }; 119 120 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 121 { 122 return container_of(mqp, struct mlx4_ib_sqp, qp); 123 } 124 125 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 126 { 127 if (!mlx4_is_master(dev->dev)) 128 return 0; 129 130 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 131 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 132 8 * MLX4_MFUNC_MAX; 133 } 134 135 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 136 { 137 int proxy_sqp = 0; 138 int real_sqp = 0; 139 int i; 140 /* PPF or Native -- real SQP */ 141 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 142 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 143 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 144 if (real_sqp) 145 return 1; 146 /* VF or PF -- proxy SQP */ 147 if (mlx4_is_mfunc(dev->dev)) { 148 for (i = 0; i < dev->dev->caps.num_ports; i++) { 149 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] || 150 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) { 151 proxy_sqp = 1; 152 break; 153 } 154 } 155 } 156 return proxy_sqp; 157 } 158 159 /* used for INIT/CLOSE port logic */ 160 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 161 { 162 int proxy_qp0 = 0; 163 int real_qp0 = 0; 164 int i; 165 /* PPF or Native -- real QP0 */ 166 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 167 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 168 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 169 if (real_qp0) 170 return 1; 171 /* VF or PF -- proxy QP0 */ 172 if (mlx4_is_mfunc(dev->dev)) { 173 for (i = 0; i < dev->dev->caps.num_ports; i++) { 174 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) { 175 proxy_qp0 = 1; 176 break; 177 } 178 } 179 } 180 return proxy_qp0; 181 } 182 183 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 184 { 185 return mlx4_buf_offset(&qp->buf, offset); 186 } 187 188 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 189 { 190 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 191 } 192 193 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 194 { 195 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 196 } 197 198 /* 199 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 200 * first four bytes of every 64 byte chunk with 201 * 0x7FFFFFF | (invalid_ownership_value << 31). 202 * 203 * When the max work request size is less than or equal to the WQE 204 * basic block size, as an optimization, we can stamp all WQEs with 205 * 0xffffffff, and skip the very first chunk of each WQE. 206 */ 207 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 208 { 209 __be32 *wqe; 210 int i; 211 int s; 212 int ind; 213 void *buf; 214 __be32 stamp; 215 struct mlx4_wqe_ctrl_seg *ctrl; 216 217 if (qp->sq_max_wqes_per_wr > 1) { 218 s = roundup(size, 1U << qp->sq.wqe_shift); 219 for (i = 0; i < s; i += 64) { 220 ind = (i >> qp->sq.wqe_shift) + n; 221 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 222 cpu_to_be32(0xffffffff); 223 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 224 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 225 *wqe = stamp; 226 } 227 } else { 228 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 229 s = (ctrl->fence_size & 0x3f) << 4; 230 for (i = 64; i < s; i += 64) { 231 wqe = buf + i; 232 *wqe = cpu_to_be32(0xffffffff); 233 } 234 } 235 } 236 237 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 238 { 239 struct mlx4_wqe_ctrl_seg *ctrl; 240 struct mlx4_wqe_inline_seg *inl; 241 void *wqe; 242 int s; 243 244 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 245 s = sizeof(struct mlx4_wqe_ctrl_seg); 246 247 if (qp->ibqp.qp_type == IB_QPT_UD) { 248 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 249 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 250 memset(dgram, 0, sizeof *dgram); 251 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 252 s += sizeof(struct mlx4_wqe_datagram_seg); 253 } 254 255 /* Pad the remainder of the WQE with an inline data segment. */ 256 if (size > s) { 257 inl = wqe + s; 258 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 259 } 260 ctrl->srcrb_flags = 0; 261 ctrl->fence_size = size / 16; 262 /* 263 * Make sure descriptor is fully written before setting ownership bit 264 * (because HW can start executing as soon as we do). 265 */ 266 wmb(); 267 268 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 269 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 270 271 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 272 } 273 274 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 275 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 276 { 277 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 278 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 279 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 280 ind += s; 281 } 282 return ind; 283 } 284 285 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 286 { 287 struct ib_event event; 288 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 289 290 if (type == MLX4_EVENT_TYPE_PATH_MIG) 291 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 292 293 if (ibqp->event_handler) { 294 event.device = ibqp->device; 295 event.element.qp = ibqp; 296 switch (type) { 297 case MLX4_EVENT_TYPE_PATH_MIG: 298 event.event = IB_EVENT_PATH_MIG; 299 break; 300 case MLX4_EVENT_TYPE_COMM_EST: 301 event.event = IB_EVENT_COMM_EST; 302 break; 303 case MLX4_EVENT_TYPE_SQ_DRAINED: 304 event.event = IB_EVENT_SQ_DRAINED; 305 break; 306 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 307 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 308 break; 309 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 310 event.event = IB_EVENT_QP_FATAL; 311 break; 312 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 313 event.event = IB_EVENT_PATH_MIG_ERR; 314 break; 315 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 316 event.event = IB_EVENT_QP_REQ_ERR; 317 break; 318 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 319 event.event = IB_EVENT_QP_ACCESS_ERR; 320 break; 321 default: 322 pr_warn("Unexpected event type %d " 323 "on QP %06x\n", type, qp->qpn); 324 return; 325 } 326 327 ibqp->event_handler(&event, ibqp->qp_context); 328 } 329 } 330 331 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 332 { 333 /* 334 * UD WQEs must have a datagram segment. 335 * RC and UC WQEs might have a remote address segment. 336 * MLX WQEs need two extra inline data segments (for the UD 337 * header and space for the ICRC). 338 */ 339 switch (type) { 340 case MLX4_IB_QPT_UD: 341 return sizeof (struct mlx4_wqe_ctrl_seg) + 342 sizeof (struct mlx4_wqe_datagram_seg) + 343 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 344 case MLX4_IB_QPT_PROXY_SMI_OWNER: 345 case MLX4_IB_QPT_PROXY_SMI: 346 case MLX4_IB_QPT_PROXY_GSI: 347 return sizeof (struct mlx4_wqe_ctrl_seg) + 348 sizeof (struct mlx4_wqe_datagram_seg) + 64; 349 case MLX4_IB_QPT_TUN_SMI_OWNER: 350 case MLX4_IB_QPT_TUN_GSI: 351 return sizeof (struct mlx4_wqe_ctrl_seg) + 352 sizeof (struct mlx4_wqe_datagram_seg); 353 354 case MLX4_IB_QPT_UC: 355 return sizeof (struct mlx4_wqe_ctrl_seg) + 356 sizeof (struct mlx4_wqe_raddr_seg); 357 case MLX4_IB_QPT_RC: 358 return sizeof (struct mlx4_wqe_ctrl_seg) + 359 sizeof (struct mlx4_wqe_atomic_seg) + 360 sizeof (struct mlx4_wqe_raddr_seg); 361 case MLX4_IB_QPT_SMI: 362 case MLX4_IB_QPT_GSI: 363 return sizeof (struct mlx4_wqe_ctrl_seg) + 364 ALIGN(MLX4_IB_UD_HEADER_SIZE + 365 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 366 MLX4_INLINE_ALIGN) * 367 sizeof (struct mlx4_wqe_inline_seg), 368 sizeof (struct mlx4_wqe_data_seg)) + 369 ALIGN(4 + 370 sizeof (struct mlx4_wqe_inline_seg), 371 sizeof (struct mlx4_wqe_data_seg)); 372 default: 373 return sizeof (struct mlx4_wqe_ctrl_seg); 374 } 375 } 376 377 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 378 int is_user, int has_rq, struct mlx4_ib_qp *qp) 379 { 380 /* Sanity check RQ size before proceeding */ 381 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 382 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 383 return -EINVAL; 384 385 if (!has_rq) { 386 if (cap->max_recv_wr) 387 return -EINVAL; 388 389 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 390 } else { 391 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 392 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 393 return -EINVAL; 394 395 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 396 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 397 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 398 } 399 400 /* leave userspace return values as they were, so as not to break ABI */ 401 if (is_user) { 402 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 403 cap->max_recv_sge = qp->rq.max_gs; 404 } else { 405 cap->max_recv_wr = qp->rq.max_post = 406 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 407 cap->max_recv_sge = min(qp->rq.max_gs, 408 min(dev->dev->caps.max_sq_sg, 409 dev->dev->caps.max_rq_sg)); 410 } 411 412 return 0; 413 } 414 415 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 416 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 417 { 418 int s; 419 420 /* Sanity check SQ size before proceeding */ 421 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 422 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 423 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 424 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 425 return -EINVAL; 426 427 /* 428 * For MLX transport we need 2 extra S/G entries: 429 * one for the header and one for the checksum at the end 430 */ 431 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 432 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 433 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 434 return -EINVAL; 435 436 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 437 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 438 send_wqe_overhead(type, qp->flags); 439 440 if (s > dev->dev->caps.max_sq_desc_sz) 441 return -EINVAL; 442 443 /* 444 * Hermon supports shrinking WQEs, such that a single work 445 * request can include multiple units of 1 << wqe_shift. This 446 * way, work requests can differ in size, and do not have to 447 * be a power of 2 in size, saving memory and speeding up send 448 * WR posting. Unfortunately, if we do this then the 449 * wqe_index field in CQEs can't be used to look up the WR ID 450 * anymore, so we do this only if selective signaling is off. 451 * 452 * Further, on 32-bit platforms, we can't use vmap() to make 453 * the QP buffer virtually contiguous. Thus we have to use 454 * constant-sized WRs to make sure a WR is always fully within 455 * a single page-sized chunk. 456 * 457 * Finally, we use NOP work requests to pad the end of the 458 * work queue, to avoid wrap-around in the middle of WR. We 459 * set NEC bit to avoid getting completions with error for 460 * these NOP WRs, but since NEC is only supported starting 461 * with firmware 2.2.232, we use constant-sized WRs for older 462 * firmware. 463 * 464 * And, since MLX QPs only support SEND, we use constant-sized 465 * WRs in this case. 466 * 467 * We look for the smallest value of wqe_shift such that the 468 * resulting number of wqes does not exceed device 469 * capabilities. 470 * 471 * We set WQE size to at least 64 bytes, this way stamping 472 * invalidates each WQE. 473 */ 474 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 475 qp->sq_signal_bits && BITS_PER_LONG == 64 && 476 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 477 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 478 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 479 qp->sq.wqe_shift = ilog2(64); 480 else 481 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 482 483 for (;;) { 484 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 485 486 /* 487 * We need to leave 2 KB + 1 WR of headroom in the SQ to 488 * allow HW to prefetch. 489 */ 490 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 491 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 492 qp->sq_max_wqes_per_wr + 493 qp->sq_spare_wqes); 494 495 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 496 break; 497 498 if (qp->sq_max_wqes_per_wr <= 1) 499 return -EINVAL; 500 501 ++qp->sq.wqe_shift; 502 } 503 504 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 505 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 506 send_wqe_overhead(type, qp->flags)) / 507 sizeof (struct mlx4_wqe_data_seg); 508 509 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 510 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 511 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 512 qp->rq.offset = 0; 513 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 514 } else { 515 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 516 qp->sq.offset = 0; 517 } 518 519 cap->max_send_wr = qp->sq.max_post = 520 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 521 cap->max_send_sge = min(qp->sq.max_gs, 522 min(dev->dev->caps.max_sq_sg, 523 dev->dev->caps.max_rq_sg)); 524 /* We don't support inline sends for kernel QPs (yet) */ 525 cap->max_inline_data = 0; 526 527 return 0; 528 } 529 530 static int set_user_sq_size(struct mlx4_ib_dev *dev, 531 struct mlx4_ib_qp *qp, 532 struct mlx4_ib_create_qp *ucmd) 533 { 534 /* Sanity check SQ size before proceeding */ 535 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 536 ucmd->log_sq_stride > 537 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 538 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 539 return -EINVAL; 540 541 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 542 qp->sq.wqe_shift = ucmd->log_sq_stride; 543 544 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 545 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 546 547 return 0; 548 } 549 550 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 551 { 552 int i; 553 554 qp->sqp_proxy_rcv = 555 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 556 GFP_KERNEL); 557 if (!qp->sqp_proxy_rcv) 558 return -ENOMEM; 559 for (i = 0; i < qp->rq.wqe_cnt; i++) { 560 qp->sqp_proxy_rcv[i].addr = 561 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 562 GFP_KERNEL); 563 if (!qp->sqp_proxy_rcv[i].addr) 564 goto err; 565 qp->sqp_proxy_rcv[i].map = 566 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 567 sizeof (struct mlx4_ib_proxy_sqp_hdr), 568 DMA_FROM_DEVICE); 569 } 570 return 0; 571 572 err: 573 while (i > 0) { 574 --i; 575 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 576 sizeof (struct mlx4_ib_proxy_sqp_hdr), 577 DMA_FROM_DEVICE); 578 kfree(qp->sqp_proxy_rcv[i].addr); 579 } 580 kfree(qp->sqp_proxy_rcv); 581 qp->sqp_proxy_rcv = NULL; 582 return -ENOMEM; 583 } 584 585 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 586 { 587 int i; 588 589 for (i = 0; i < qp->rq.wqe_cnt; i++) { 590 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 591 sizeof (struct mlx4_ib_proxy_sqp_hdr), 592 DMA_FROM_DEVICE); 593 kfree(qp->sqp_proxy_rcv[i].addr); 594 } 595 kfree(qp->sqp_proxy_rcv); 596 } 597 598 static int qp_has_rq(struct ib_qp_init_attr *attr) 599 { 600 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 601 return 0; 602 603 return !attr->srq; 604 } 605 606 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 607 { 608 int i; 609 for (i = 0; i < dev->caps.num_ports; i++) { 610 if (qpn == dev->caps.qp0_proxy[i]) 611 return !!dev->caps.qp0_qkey[i]; 612 } 613 return 0; 614 } 615 616 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 617 struct ib_qp_init_attr *init_attr, 618 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp, 619 gfp_t gfp) 620 { 621 int qpn; 622 int err; 623 struct mlx4_ib_sqp *sqp; 624 struct mlx4_ib_qp *qp; 625 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 626 struct mlx4_ib_cq *mcq; 627 unsigned long flags; 628 629 /* When tunneling special qps, we use a plain UD qp */ 630 if (sqpn) { 631 if (mlx4_is_mfunc(dev->dev) && 632 (!mlx4_is_master(dev->dev) || 633 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 634 if (init_attr->qp_type == IB_QPT_GSI) 635 qp_type = MLX4_IB_QPT_PROXY_GSI; 636 else { 637 if (mlx4_is_master(dev->dev) || 638 qp0_enabled_vf(dev->dev, sqpn)) 639 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 640 else 641 qp_type = MLX4_IB_QPT_PROXY_SMI; 642 } 643 } 644 qpn = sqpn; 645 /* add extra sg entry for tunneling */ 646 init_attr->cap.max_recv_sge++; 647 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 648 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 649 container_of(init_attr, 650 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 651 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 652 tnl_init->proxy_qp_type != IB_QPT_GSI) || 653 !mlx4_is_master(dev->dev)) 654 return -EINVAL; 655 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 656 qp_type = MLX4_IB_QPT_TUN_GSI; 657 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 658 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 659 tnl_init->port)) 660 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 661 else 662 qp_type = MLX4_IB_QPT_TUN_SMI; 663 /* we are definitely in the PPF here, since we are creating 664 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 665 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 666 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 667 sqpn = qpn; 668 } 669 670 if (!*caller_qp) { 671 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 672 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 673 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 674 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp); 675 if (!sqp) 676 return -ENOMEM; 677 qp = &sqp->qp; 678 qp->pri.vid = 0xFFFF; 679 qp->alt.vid = 0xFFFF; 680 } else { 681 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp); 682 if (!qp) 683 return -ENOMEM; 684 qp->pri.vid = 0xFFFF; 685 qp->alt.vid = 0xFFFF; 686 } 687 } else 688 qp = *caller_qp; 689 690 qp->mlx4_ib_qp_type = qp_type; 691 692 mutex_init(&qp->mutex); 693 spin_lock_init(&qp->sq.lock); 694 spin_lock_init(&qp->rq.lock); 695 INIT_LIST_HEAD(&qp->gid_list); 696 INIT_LIST_HEAD(&qp->steering_rules); 697 698 qp->state = IB_QPS_RESET; 699 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 700 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 701 702 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp); 703 if (err) 704 goto err; 705 706 if (pd->uobject) { 707 struct mlx4_ib_create_qp ucmd; 708 709 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 710 err = -EFAULT; 711 goto err; 712 } 713 714 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 715 716 err = set_user_sq_size(dev, qp, &ucmd); 717 if (err) 718 goto err; 719 720 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 721 qp->buf_size, 0, 0); 722 if (IS_ERR(qp->umem)) { 723 err = PTR_ERR(qp->umem); 724 goto err; 725 } 726 727 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 728 ilog2(qp->umem->page_size), &qp->mtt); 729 if (err) 730 goto err_buf; 731 732 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 733 if (err) 734 goto err_mtt; 735 736 if (qp_has_rq(init_attr)) { 737 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 738 ucmd.db_addr, &qp->db); 739 if (err) 740 goto err_mtt; 741 } 742 } else { 743 qp->sq_no_prefetch = 0; 744 745 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 746 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 747 748 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 749 qp->flags |= MLX4_IB_QP_LSO; 750 751 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 752 if (dev->steering_support == 753 MLX4_STEERING_MODE_DEVICE_MANAGED) 754 qp->flags |= MLX4_IB_QP_NETIF; 755 else 756 goto err; 757 } 758 759 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 760 if (err) 761 goto err; 762 763 if (qp_has_rq(init_attr)) { 764 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp); 765 if (err) 766 goto err; 767 768 *qp->db.db = 0; 769 } 770 771 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) { 772 err = -ENOMEM; 773 goto err_db; 774 } 775 776 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 777 &qp->mtt); 778 if (err) 779 goto err_buf; 780 781 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp); 782 if (err) 783 goto err_mtt; 784 785 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp); 786 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp); 787 if (!qp->sq.wrid || !qp->rq.wrid) { 788 err = -ENOMEM; 789 goto err_wrid; 790 } 791 } 792 793 if (sqpn) { 794 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 795 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 796 if (alloc_proxy_bufs(pd->device, qp)) { 797 err = -ENOMEM; 798 goto err_wrid; 799 } 800 } 801 } else { 802 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 803 * otherwise, the WQE BlueFlame setup flow wrongly causes 804 * VLAN insertion. */ 805 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 806 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 807 (init_attr->cap.max_send_wr ? 808 MLX4_RESERVE_ETH_BF_QP : 0) | 809 (init_attr->cap.max_recv_wr ? 810 MLX4_RESERVE_A0_QP : 0)); 811 else 812 if (qp->flags & MLX4_IB_QP_NETIF) 813 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 814 else 815 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 816 &qpn, 0); 817 if (err) 818 goto err_proxy; 819 } 820 821 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp); 822 if (err) 823 goto err_qpn; 824 825 if (init_attr->qp_type == IB_QPT_XRC_TGT) 826 qp->mqp.qpn |= (1 << 23); 827 828 /* 829 * Hardware wants QPN written in big-endian order (after 830 * shifting) for send doorbell. Precompute this value to save 831 * a little bit when posting sends. 832 */ 833 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 834 835 qp->mqp.event = mlx4_ib_qp_event; 836 if (!*caller_qp) 837 *caller_qp = qp; 838 839 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 840 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 841 to_mcq(init_attr->recv_cq)); 842 /* Maintain device to QPs access, needed for further handling 843 * via reset flow 844 */ 845 list_add_tail(&qp->qps_list, &dev->qp_list); 846 /* Maintain CQ to QPs access, needed for further handling 847 * via reset flow 848 */ 849 mcq = to_mcq(init_attr->send_cq); 850 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 851 mcq = to_mcq(init_attr->recv_cq); 852 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 853 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 854 to_mcq(init_attr->recv_cq)); 855 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 856 return 0; 857 858 err_qpn: 859 if (!sqpn) { 860 if (qp->flags & MLX4_IB_QP_NETIF) 861 mlx4_ib_steer_qp_free(dev, qpn, 1); 862 else 863 mlx4_qp_release_range(dev->dev, qpn, 1); 864 } 865 err_proxy: 866 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 867 free_proxy_bufs(pd->device, qp); 868 err_wrid: 869 if (pd->uobject) { 870 if (qp_has_rq(init_attr)) 871 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 872 } else { 873 kfree(qp->sq.wrid); 874 kfree(qp->rq.wrid); 875 } 876 877 err_mtt: 878 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 879 880 err_buf: 881 if (pd->uobject) 882 ib_umem_release(qp->umem); 883 else 884 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 885 886 err_db: 887 if (!pd->uobject && qp_has_rq(init_attr)) 888 mlx4_db_free(dev->dev, &qp->db); 889 890 err: 891 if (!*caller_qp) 892 kfree(qp); 893 return err; 894 } 895 896 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 897 { 898 switch (state) { 899 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 900 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 901 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 902 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 903 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 904 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 905 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 906 default: return -1; 907 } 908 } 909 910 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 911 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 912 { 913 if (send_cq == recv_cq) { 914 spin_lock(&send_cq->lock); 915 __acquire(&recv_cq->lock); 916 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 917 spin_lock(&send_cq->lock); 918 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 919 } else { 920 spin_lock(&recv_cq->lock); 921 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 922 } 923 } 924 925 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 926 __releases(&send_cq->lock) __releases(&recv_cq->lock) 927 { 928 if (send_cq == recv_cq) { 929 __release(&recv_cq->lock); 930 spin_unlock(&send_cq->lock); 931 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 932 spin_unlock(&recv_cq->lock); 933 spin_unlock(&send_cq->lock); 934 } else { 935 spin_unlock(&send_cq->lock); 936 spin_unlock(&recv_cq->lock); 937 } 938 } 939 940 static void del_gid_entries(struct mlx4_ib_qp *qp) 941 { 942 struct mlx4_ib_gid_entry *ge, *tmp; 943 944 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 945 list_del(&ge->list); 946 kfree(ge); 947 } 948 } 949 950 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 951 { 952 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 953 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 954 else 955 return to_mpd(qp->ibqp.pd); 956 } 957 958 static void get_cqs(struct mlx4_ib_qp *qp, 959 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 960 { 961 switch (qp->ibqp.qp_type) { 962 case IB_QPT_XRC_TGT: 963 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 964 *recv_cq = *send_cq; 965 break; 966 case IB_QPT_XRC_INI: 967 *send_cq = to_mcq(qp->ibqp.send_cq); 968 *recv_cq = *send_cq; 969 break; 970 default: 971 *send_cq = to_mcq(qp->ibqp.send_cq); 972 *recv_cq = to_mcq(qp->ibqp.recv_cq); 973 break; 974 } 975 } 976 977 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 978 int is_user) 979 { 980 struct mlx4_ib_cq *send_cq, *recv_cq; 981 unsigned long flags; 982 983 if (qp->state != IB_QPS_RESET) { 984 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 985 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 986 pr_warn("modify QP %06x to RESET failed.\n", 987 qp->mqp.qpn); 988 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 989 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 990 qp->pri.smac = 0; 991 qp->pri.smac_port = 0; 992 } 993 if (qp->alt.smac) { 994 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 995 qp->alt.smac = 0; 996 } 997 if (qp->pri.vid < 0x1000) { 998 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 999 qp->pri.vid = 0xFFFF; 1000 qp->pri.candidate_vid = 0xFFFF; 1001 qp->pri.update_vid = 0; 1002 } 1003 if (qp->alt.vid < 0x1000) { 1004 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1005 qp->alt.vid = 0xFFFF; 1006 qp->alt.candidate_vid = 0xFFFF; 1007 qp->alt.update_vid = 0; 1008 } 1009 } 1010 1011 get_cqs(qp, &send_cq, &recv_cq); 1012 1013 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1014 mlx4_ib_lock_cqs(send_cq, recv_cq); 1015 1016 /* del from lists under both locks above to protect reset flow paths */ 1017 list_del(&qp->qps_list); 1018 list_del(&qp->cq_send_list); 1019 list_del(&qp->cq_recv_list); 1020 if (!is_user) { 1021 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1022 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1023 if (send_cq != recv_cq) 1024 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1025 } 1026 1027 mlx4_qp_remove(dev->dev, &qp->mqp); 1028 1029 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1030 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1031 1032 mlx4_qp_free(dev->dev, &qp->mqp); 1033 1034 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1035 if (qp->flags & MLX4_IB_QP_NETIF) 1036 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1037 else 1038 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1039 } 1040 1041 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1042 1043 if (is_user) { 1044 if (qp->rq.wqe_cnt) 1045 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), 1046 &qp->db); 1047 ib_umem_release(qp->umem); 1048 } else { 1049 kfree(qp->sq.wrid); 1050 kfree(qp->rq.wrid); 1051 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1052 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1053 free_proxy_bufs(&dev->ib_dev, qp); 1054 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1055 if (qp->rq.wqe_cnt) 1056 mlx4_db_free(dev->dev, &qp->db); 1057 } 1058 1059 del_gid_entries(qp); 1060 } 1061 1062 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1063 { 1064 /* Native or PPF */ 1065 if (!mlx4_is_mfunc(dev->dev) || 1066 (mlx4_is_master(dev->dev) && 1067 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1068 return dev->dev->phys_caps.base_sqpn + 1069 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1070 attr->port_num - 1; 1071 } 1072 /* PF or VF -- creating proxies */ 1073 if (attr->qp_type == IB_QPT_SMI) 1074 return dev->dev->caps.qp0_proxy[attr->port_num - 1]; 1075 else 1076 return dev->dev->caps.qp1_proxy[attr->port_num - 1]; 1077 } 1078 1079 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1080 struct ib_qp_init_attr *init_attr, 1081 struct ib_udata *udata) 1082 { 1083 struct mlx4_ib_qp *qp = NULL; 1084 int err; 1085 u16 xrcdn = 0; 1086 gfp_t gfp; 1087 1088 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ? 1089 GFP_NOIO : GFP_KERNEL; 1090 /* 1091 * We only support LSO, vendor flag1, and multicast loopback blocking, 1092 * and only for kernel UD QPs. 1093 */ 1094 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1095 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1096 MLX4_IB_SRIOV_TUNNEL_QP | 1097 MLX4_IB_SRIOV_SQP | 1098 MLX4_IB_QP_NETIF | 1099 MLX4_IB_QP_CREATE_USE_GFP_NOIO)) 1100 return ERR_PTR(-EINVAL); 1101 1102 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1103 if (init_attr->qp_type != IB_QPT_UD) 1104 return ERR_PTR(-EINVAL); 1105 } 1106 1107 if (init_attr->create_flags && 1108 (udata || 1109 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) && 1110 init_attr->qp_type != IB_QPT_UD) || 1111 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) && 1112 init_attr->qp_type > IB_QPT_GSI))) 1113 return ERR_PTR(-EINVAL); 1114 1115 switch (init_attr->qp_type) { 1116 case IB_QPT_XRC_TGT: 1117 pd = to_mxrcd(init_attr->xrcd)->pd; 1118 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1119 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1120 /* fall through */ 1121 case IB_QPT_XRC_INI: 1122 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1123 return ERR_PTR(-ENOSYS); 1124 init_attr->recv_cq = init_attr->send_cq; 1125 /* fall through */ 1126 case IB_QPT_RC: 1127 case IB_QPT_UC: 1128 case IB_QPT_RAW_PACKET: 1129 qp = kzalloc(sizeof *qp, gfp); 1130 if (!qp) 1131 return ERR_PTR(-ENOMEM); 1132 qp->pri.vid = 0xFFFF; 1133 qp->alt.vid = 0xFFFF; 1134 /* fall through */ 1135 case IB_QPT_UD: 1136 { 1137 err = create_qp_common(to_mdev(pd->device), pd, init_attr, 1138 udata, 0, &qp, gfp); 1139 if (err) 1140 return ERR_PTR(err); 1141 1142 qp->ibqp.qp_num = qp->mqp.qpn; 1143 qp->xrcdn = xrcdn; 1144 1145 break; 1146 } 1147 case IB_QPT_SMI: 1148 case IB_QPT_GSI: 1149 { 1150 /* Userspace is not allowed to create special QPs: */ 1151 if (udata) 1152 return ERR_PTR(-EINVAL); 1153 1154 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata, 1155 get_sqp_num(to_mdev(pd->device), init_attr), 1156 &qp, gfp); 1157 if (err) 1158 return ERR_PTR(err); 1159 1160 qp->port = init_attr->port_num; 1161 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1; 1162 1163 break; 1164 } 1165 default: 1166 /* Don't support raw QPs */ 1167 return ERR_PTR(-EINVAL); 1168 } 1169 1170 return &qp->ibqp; 1171 } 1172 1173 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1174 { 1175 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1176 struct mlx4_ib_qp *mqp = to_mqp(qp); 1177 struct mlx4_ib_pd *pd; 1178 1179 if (is_qp0(dev, mqp)) 1180 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1181 1182 if (dev->qp1_proxy[mqp->port - 1] == mqp) { 1183 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1184 dev->qp1_proxy[mqp->port - 1] = NULL; 1185 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1186 } 1187 1188 pd = get_pd(mqp); 1189 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject); 1190 1191 if (is_sqp(dev, mqp)) 1192 kfree(to_msqp(mqp)); 1193 else 1194 kfree(mqp); 1195 1196 return 0; 1197 } 1198 1199 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1200 { 1201 switch (type) { 1202 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1203 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1204 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1205 case MLX4_IB_QPT_XRC_INI: 1206 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1207 case MLX4_IB_QPT_SMI: 1208 case MLX4_IB_QPT_GSI: 1209 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1210 1211 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1212 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1213 MLX4_QP_ST_MLX : -1); 1214 case MLX4_IB_QPT_PROXY_SMI: 1215 case MLX4_IB_QPT_TUN_SMI: 1216 case MLX4_IB_QPT_PROXY_GSI: 1217 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1218 MLX4_QP_ST_UD : -1); 1219 default: return -1; 1220 } 1221 } 1222 1223 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1224 int attr_mask) 1225 { 1226 u8 dest_rd_atomic; 1227 u32 access_flags; 1228 u32 hw_access_flags = 0; 1229 1230 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1231 dest_rd_atomic = attr->max_dest_rd_atomic; 1232 else 1233 dest_rd_atomic = qp->resp_depth; 1234 1235 if (attr_mask & IB_QP_ACCESS_FLAGS) 1236 access_flags = attr->qp_access_flags; 1237 else 1238 access_flags = qp->atomic_rd_en; 1239 1240 if (!dest_rd_atomic) 1241 access_flags &= IB_ACCESS_REMOTE_WRITE; 1242 1243 if (access_flags & IB_ACCESS_REMOTE_READ) 1244 hw_access_flags |= MLX4_QP_BIT_RRE; 1245 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1246 hw_access_flags |= MLX4_QP_BIT_RAE; 1247 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1248 hw_access_flags |= MLX4_QP_BIT_RWE; 1249 1250 return cpu_to_be32(hw_access_flags); 1251 } 1252 1253 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1254 int attr_mask) 1255 { 1256 if (attr_mask & IB_QP_PKEY_INDEX) 1257 sqp->pkey_index = attr->pkey_index; 1258 if (attr_mask & IB_QP_QKEY) 1259 sqp->qkey = attr->qkey; 1260 if (attr_mask & IB_QP_SQ_PSN) 1261 sqp->send_psn = attr->sq_psn; 1262 } 1263 1264 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1265 { 1266 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1267 } 1268 1269 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 1270 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1271 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1272 { 1273 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) == 1274 IB_LINK_LAYER_ETHERNET; 1275 int vidx; 1276 int smac_index; 1277 int err; 1278 1279 1280 path->grh_mylmc = ah->src_path_bits & 0x7f; 1281 path->rlid = cpu_to_be16(ah->dlid); 1282 if (ah->static_rate) { 1283 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET; 1284 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1285 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1286 --path->static_rate; 1287 } else 1288 path->static_rate = 0; 1289 1290 if (ah->ah_flags & IB_AH_GRH) { 1291 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) { 1292 pr_err("sgid_index (%u) too large. max is %d\n", 1293 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1294 return -1; 1295 } 1296 1297 path->grh_mylmc |= 1 << 7; 1298 path->mgid_index = ah->grh.sgid_index; 1299 path->hop_limit = ah->grh.hop_limit; 1300 path->tclass_flowlabel = 1301 cpu_to_be32((ah->grh.traffic_class << 20) | 1302 (ah->grh.flow_label)); 1303 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1304 } 1305 1306 if (is_eth) { 1307 if (!(ah->ah_flags & IB_AH_GRH)) 1308 return -1; 1309 1310 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1311 ((port - 1) << 6) | ((ah->sl & 7) << 3); 1312 1313 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1314 if (vlan_tag < 0x1000) { 1315 if (smac_info->vid < 0x1000) { 1316 /* both valid vlan ids */ 1317 if (smac_info->vid != vlan_tag) { 1318 /* different VIDs. unreg old and reg new */ 1319 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1320 if (err) 1321 return err; 1322 smac_info->candidate_vid = vlan_tag; 1323 smac_info->candidate_vlan_index = vidx; 1324 smac_info->candidate_vlan_port = port; 1325 smac_info->update_vid = 1; 1326 path->vlan_index = vidx; 1327 } else { 1328 path->vlan_index = smac_info->vlan_index; 1329 } 1330 } else { 1331 /* no current vlan tag in qp */ 1332 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1333 if (err) 1334 return err; 1335 smac_info->candidate_vid = vlan_tag; 1336 smac_info->candidate_vlan_index = vidx; 1337 smac_info->candidate_vlan_port = port; 1338 smac_info->update_vid = 1; 1339 path->vlan_index = vidx; 1340 } 1341 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1342 path->fl = 1 << 6; 1343 } else { 1344 /* have current vlan tag. unregister it at modify-qp success */ 1345 if (smac_info->vid < 0x1000) { 1346 smac_info->candidate_vid = 0xFFFF; 1347 smac_info->update_vid = 1; 1348 } 1349 } 1350 1351 /* get smac_index for RoCE use. 1352 * If no smac was yet assigned, register one. 1353 * If one was already assigned, but the new mac differs, 1354 * unregister the old one and register the new one. 1355 */ 1356 if ((!smac_info->smac && !smac_info->smac_port) || 1357 smac_info->smac != smac) { 1358 /* register candidate now, unreg if needed, after success */ 1359 smac_index = mlx4_register_mac(dev->dev, port, smac); 1360 if (smac_index >= 0) { 1361 smac_info->candidate_smac_index = smac_index; 1362 smac_info->candidate_smac = smac; 1363 smac_info->candidate_smac_port = port; 1364 } else { 1365 return -EINVAL; 1366 } 1367 } else { 1368 smac_index = smac_info->smac_index; 1369 } 1370 1371 memcpy(path->dmac, ah->dmac, 6); 1372 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1373 /* put MAC table smac index for IBoE */ 1374 path->grh_mylmc = (u8) (smac_index) | 0x80; 1375 } else { 1376 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1377 ((port - 1) << 6) | ((ah->sl & 0xf) << 2); 1378 } 1379 1380 return 0; 1381 } 1382 1383 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1384 enum ib_qp_attr_mask qp_attr_mask, 1385 struct mlx4_ib_qp *mqp, 1386 struct mlx4_qp_path *path, u8 port) 1387 { 1388 return _mlx4_set_path(dev, &qp->ah_attr, 1389 mlx4_mac_to_u64((u8 *)qp->smac), 1390 (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff, 1391 path, &mqp->pri, port); 1392 } 1393 1394 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1395 const struct ib_qp_attr *qp, 1396 enum ib_qp_attr_mask qp_attr_mask, 1397 struct mlx4_ib_qp *mqp, 1398 struct mlx4_qp_path *path, u8 port) 1399 { 1400 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1401 mlx4_mac_to_u64((u8 *)qp->alt_smac), 1402 (qp_attr_mask & IB_QP_ALT_VID) ? 1403 qp->alt_vlan_id : 0xffff, 1404 path, &mqp->alt, port); 1405 } 1406 1407 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1408 { 1409 struct mlx4_ib_gid_entry *ge, *tmp; 1410 1411 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1412 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1413 ge->added = 1; 1414 ge->port = qp->port; 1415 } 1416 } 1417 } 1418 1419 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac, 1420 struct mlx4_qp_context *context) 1421 { 1422 u64 u64_mac; 1423 int smac_index; 1424 1425 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1426 1427 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1428 if (!qp->pri.smac && !qp->pri.smac_port) { 1429 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1430 if (smac_index >= 0) { 1431 qp->pri.candidate_smac_index = smac_index; 1432 qp->pri.candidate_smac = u64_mac; 1433 qp->pri.candidate_smac_port = qp->port; 1434 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1435 } else { 1436 return -ENOENT; 1437 } 1438 } 1439 return 0; 1440 } 1441 1442 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 1443 const struct ib_qp_attr *attr, int attr_mask, 1444 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1445 { 1446 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1447 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1448 struct mlx4_ib_pd *pd; 1449 struct mlx4_ib_cq *send_cq, *recv_cq; 1450 struct mlx4_qp_context *context; 1451 enum mlx4_qp_optpar optpar = 0; 1452 int sqd_event; 1453 int steer_qp = 0; 1454 int err = -EINVAL; 1455 1456 /* APM is not supported under RoCE */ 1457 if (attr_mask & IB_QP_ALT_PATH && 1458 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1459 IB_LINK_LAYER_ETHERNET) 1460 return -ENOTSUPP; 1461 1462 context = kzalloc(sizeof *context, GFP_KERNEL); 1463 if (!context) 1464 return -ENOMEM; 1465 1466 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 1467 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 1468 1469 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 1470 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1471 else { 1472 optpar |= MLX4_QP_OPTPAR_PM_STATE; 1473 switch (attr->path_mig_state) { 1474 case IB_MIG_MIGRATED: 1475 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1476 break; 1477 case IB_MIG_REARM: 1478 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 1479 break; 1480 case IB_MIG_ARMED: 1481 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 1482 break; 1483 } 1484 } 1485 1486 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 1487 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 1488 else if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1489 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 1490 else if (ibqp->qp_type == IB_QPT_UD) { 1491 if (qp->flags & MLX4_IB_QP_LSO) 1492 context->mtu_msgmax = (IB_MTU_4096 << 5) | 1493 ilog2(dev->dev->caps.max_gso_sz); 1494 else 1495 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1496 } else if (attr_mask & IB_QP_PATH_MTU) { 1497 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 1498 pr_err("path MTU (%u) is invalid\n", 1499 attr->path_mtu); 1500 goto out; 1501 } 1502 context->mtu_msgmax = (attr->path_mtu << 5) | 1503 ilog2(dev->dev->caps.max_msg_sz); 1504 } 1505 1506 if (qp->rq.wqe_cnt) 1507 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 1508 context->rq_size_stride |= qp->rq.wqe_shift - 4; 1509 1510 if (qp->sq.wqe_cnt) 1511 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 1512 context->sq_size_stride |= qp->sq.wqe_shift - 4; 1513 1514 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1515 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 1516 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 1517 if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1518 context->param3 |= cpu_to_be32(1 << 30); 1519 } 1520 1521 if (qp->ibqp.uobject) 1522 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index); 1523 else 1524 context->usr_page = cpu_to_be32(dev->priv_uar.index); 1525 1526 if (attr_mask & IB_QP_DEST_QPN) 1527 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 1528 1529 if (attr_mask & IB_QP_PORT) { 1530 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 1531 !(attr_mask & IB_QP_AV)) { 1532 mlx4_set_sched(&context->pri_path, attr->port_num); 1533 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 1534 } 1535 } 1536 1537 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 1538 if (dev->counters[qp->port - 1] != -1) { 1539 context->pri_path.counter_index = 1540 dev->counters[qp->port - 1]; 1541 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 1542 } else 1543 context->pri_path.counter_index = 0xff; 1544 1545 if (qp->flags & MLX4_IB_QP_NETIF) { 1546 mlx4_ib_steer_qp_reg(dev, qp, 1); 1547 steer_qp = 1; 1548 } 1549 } 1550 1551 if (attr_mask & IB_QP_PKEY_INDEX) { 1552 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1553 context->pri_path.disable_pkey_check = 0x40; 1554 context->pri_path.pkey_index = attr->pkey_index; 1555 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 1556 } 1557 1558 if (attr_mask & IB_QP_AV) { 1559 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 1560 attr_mask & IB_QP_PORT ? 1561 attr->port_num : qp->port)) 1562 goto out; 1563 1564 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 1565 MLX4_QP_OPTPAR_SCHED_QUEUE); 1566 } 1567 1568 if (attr_mask & IB_QP_TIMEOUT) { 1569 context->pri_path.ackto |= attr->timeout << 3; 1570 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 1571 } 1572 1573 if (attr_mask & IB_QP_ALT_PATH) { 1574 if (attr->alt_port_num == 0 || 1575 attr->alt_port_num > dev->dev->caps.num_ports) 1576 goto out; 1577 1578 if (attr->alt_pkey_index >= 1579 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 1580 goto out; 1581 1582 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 1583 &context->alt_path, 1584 attr->alt_port_num)) 1585 goto out; 1586 1587 context->alt_path.pkey_index = attr->alt_pkey_index; 1588 context->alt_path.ackto = attr->alt_timeout << 3; 1589 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 1590 } 1591 1592 pd = get_pd(qp); 1593 get_cqs(qp, &send_cq, &recv_cq); 1594 context->pd = cpu_to_be32(pd->pdn); 1595 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1596 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 1597 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 1598 1599 /* Set "fast registration enabled" for all kernel QPs */ 1600 if (!qp->ibqp.uobject) 1601 context->params1 |= cpu_to_be32(1 << 11); 1602 1603 if (attr_mask & IB_QP_RNR_RETRY) { 1604 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1605 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 1606 } 1607 1608 if (attr_mask & IB_QP_RETRY_CNT) { 1609 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1610 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 1611 } 1612 1613 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1614 if (attr->max_rd_atomic) 1615 context->params1 |= 1616 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1617 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 1618 } 1619 1620 if (attr_mask & IB_QP_SQ_PSN) 1621 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1622 1623 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1624 if (attr->max_dest_rd_atomic) 1625 context->params2 |= 1626 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1627 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1628 } 1629 1630 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1631 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1632 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1633 } 1634 1635 if (ibqp->srq) 1636 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1637 1638 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1639 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1640 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1641 } 1642 if (attr_mask & IB_QP_RQ_PSN) 1643 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1644 1645 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 1646 if (attr_mask & IB_QP_QKEY) { 1647 if (qp->mlx4_ib_qp_type & 1648 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 1649 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 1650 else { 1651 if (mlx4_is_mfunc(dev->dev) && 1652 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 1653 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 1654 MLX4_RESERVED_QKEY_BASE) { 1655 pr_err("Cannot use reserved QKEY" 1656 " 0x%x (range 0xffff0000..0xffffffff" 1657 " is reserved)\n", attr->qkey); 1658 err = -EINVAL; 1659 goto out; 1660 } 1661 context->qkey = cpu_to_be32(attr->qkey); 1662 } 1663 optpar |= MLX4_QP_OPTPAR_Q_KEY; 1664 } 1665 1666 if (ibqp->srq) 1667 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 1668 1669 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1670 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1671 1672 if (cur_state == IB_QPS_INIT && 1673 new_state == IB_QPS_RTR && 1674 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 1675 ibqp->qp_type == IB_QPT_UD || 1676 ibqp->qp_type == IB_QPT_RAW_PACKET)) { 1677 context->pri_path.sched_queue = (qp->port - 1) << 6; 1678 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 1679 qp->mlx4_ib_qp_type & 1680 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 1681 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 1682 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 1683 context->pri_path.fl = 0x80; 1684 } else { 1685 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1686 context->pri_path.fl = 0x80; 1687 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 1688 } 1689 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1690 IB_LINK_LAYER_ETHERNET) { 1691 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 1692 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 1693 context->pri_path.feup = 1 << 7; /* don't fsm */ 1694 /* handle smac_index */ 1695 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 1696 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 1697 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 1698 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context); 1699 if (err) { 1700 err = -EINVAL; 1701 goto out; 1702 } 1703 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1704 dev->qp1_proxy[qp->port - 1] = qp; 1705 } 1706 } 1707 } 1708 1709 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1710 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 1711 MLX4_IB_LINK_TYPE_ETH; 1712 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1713 /* set QP to receive both tunneled & non-tunneled packets */ 1714 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET))) 1715 context->srqn = cpu_to_be32(7 << 28); 1716 } 1717 } 1718 1719 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 1720 int is_eth = rdma_port_get_link_layer( 1721 &dev->ib_dev, qp->port) == 1722 IB_LINK_LAYER_ETHERNET; 1723 if (is_eth) { 1724 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 1725 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 1726 } 1727 } 1728 1729 1730 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1731 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1732 sqd_event = 1; 1733 else 1734 sqd_event = 0; 1735 1736 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1737 context->rlkey |= (1 << 4); 1738 1739 /* 1740 * Before passing a kernel QP to the HW, make sure that the 1741 * ownership bits of the send queue are set and the SQ 1742 * headroom is stamped so that the hardware doesn't start 1743 * processing stale work requests. 1744 */ 1745 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1746 struct mlx4_wqe_ctrl_seg *ctrl; 1747 int i; 1748 1749 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 1750 ctrl = get_send_wqe(qp, i); 1751 ctrl->owner_opcode = cpu_to_be32(1 << 31); 1752 if (qp->sq_max_wqes_per_wr == 1) 1753 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); 1754 1755 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 1756 } 1757 } 1758 1759 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 1760 to_mlx4_state(new_state), context, optpar, 1761 sqd_event, &qp->mqp); 1762 if (err) 1763 goto out; 1764 1765 qp->state = new_state; 1766 1767 if (attr_mask & IB_QP_ACCESS_FLAGS) 1768 qp->atomic_rd_en = attr->qp_access_flags; 1769 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1770 qp->resp_depth = attr->max_dest_rd_atomic; 1771 if (attr_mask & IB_QP_PORT) { 1772 qp->port = attr->port_num; 1773 update_mcg_macs(dev, qp); 1774 } 1775 if (attr_mask & IB_QP_ALT_PATH) 1776 qp->alt_port = attr->alt_port_num; 1777 1778 if (is_sqp(dev, qp)) 1779 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 1780 1781 /* 1782 * If we moved QP0 to RTR, bring the IB link up; if we moved 1783 * QP0 to RESET or ERROR, bring the link back down. 1784 */ 1785 if (is_qp0(dev, qp)) { 1786 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 1787 if (mlx4_INIT_PORT(dev->dev, qp->port)) 1788 pr_warn("INIT_PORT failed for port %d\n", 1789 qp->port); 1790 1791 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 1792 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 1793 mlx4_CLOSE_PORT(dev->dev, qp->port); 1794 } 1795 1796 /* 1797 * If we moved a kernel QP to RESET, clean up all old CQ 1798 * entries and reinitialize the QP. 1799 */ 1800 if (new_state == IB_QPS_RESET) { 1801 if (!ibqp->uobject) { 1802 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1803 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 1804 if (send_cq != recv_cq) 1805 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1806 1807 qp->rq.head = 0; 1808 qp->rq.tail = 0; 1809 qp->sq.head = 0; 1810 qp->sq.tail = 0; 1811 qp->sq_next_wqe = 0; 1812 if (qp->rq.wqe_cnt) 1813 *qp->db.db = 0; 1814 1815 if (qp->flags & MLX4_IB_QP_NETIF) 1816 mlx4_ib_steer_qp_reg(dev, qp, 0); 1817 } 1818 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1819 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1820 qp->pri.smac = 0; 1821 qp->pri.smac_port = 0; 1822 } 1823 if (qp->alt.smac) { 1824 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1825 qp->alt.smac = 0; 1826 } 1827 if (qp->pri.vid < 0x1000) { 1828 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1829 qp->pri.vid = 0xFFFF; 1830 qp->pri.candidate_vid = 0xFFFF; 1831 qp->pri.update_vid = 0; 1832 } 1833 1834 if (qp->alt.vid < 0x1000) { 1835 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1836 qp->alt.vid = 0xFFFF; 1837 qp->alt.candidate_vid = 0xFFFF; 1838 qp->alt.update_vid = 0; 1839 } 1840 } 1841 out: 1842 if (err && steer_qp) 1843 mlx4_ib_steer_qp_reg(dev, qp, 0); 1844 kfree(context); 1845 if (qp->pri.candidate_smac || 1846 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 1847 if (err) { 1848 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 1849 } else { 1850 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 1851 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1852 qp->pri.smac = qp->pri.candidate_smac; 1853 qp->pri.smac_index = qp->pri.candidate_smac_index; 1854 qp->pri.smac_port = qp->pri.candidate_smac_port; 1855 } 1856 qp->pri.candidate_smac = 0; 1857 qp->pri.candidate_smac_index = 0; 1858 qp->pri.candidate_smac_port = 0; 1859 } 1860 if (qp->alt.candidate_smac) { 1861 if (err) { 1862 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 1863 } else { 1864 if (qp->alt.smac) 1865 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1866 qp->alt.smac = qp->alt.candidate_smac; 1867 qp->alt.smac_index = qp->alt.candidate_smac_index; 1868 qp->alt.smac_port = qp->alt.candidate_smac_port; 1869 } 1870 qp->alt.candidate_smac = 0; 1871 qp->alt.candidate_smac_index = 0; 1872 qp->alt.candidate_smac_port = 0; 1873 } 1874 1875 if (qp->pri.update_vid) { 1876 if (err) { 1877 if (qp->pri.candidate_vid < 0x1000) 1878 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 1879 qp->pri.candidate_vid); 1880 } else { 1881 if (qp->pri.vid < 0x1000) 1882 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 1883 qp->pri.vid); 1884 qp->pri.vid = qp->pri.candidate_vid; 1885 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 1886 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 1887 } 1888 qp->pri.candidate_vid = 0xFFFF; 1889 qp->pri.update_vid = 0; 1890 } 1891 1892 if (qp->alt.update_vid) { 1893 if (err) { 1894 if (qp->alt.candidate_vid < 0x1000) 1895 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 1896 qp->alt.candidate_vid); 1897 } else { 1898 if (qp->alt.vid < 0x1000) 1899 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 1900 qp->alt.vid); 1901 qp->alt.vid = qp->alt.candidate_vid; 1902 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 1903 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 1904 } 1905 qp->alt.candidate_vid = 0xFFFF; 1906 qp->alt.update_vid = 0; 1907 } 1908 1909 return err; 1910 } 1911 1912 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1913 int attr_mask, struct ib_udata *udata) 1914 { 1915 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1916 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1917 enum ib_qp_state cur_state, new_state; 1918 int err = -EINVAL; 1919 int ll; 1920 mutex_lock(&qp->mutex); 1921 1922 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 1923 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1924 1925 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1926 ll = IB_LINK_LAYER_UNSPECIFIED; 1927 } else { 1928 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1929 ll = rdma_port_get_link_layer(&dev->ib_dev, port); 1930 } 1931 1932 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 1933 attr_mask, ll)) { 1934 pr_debug("qpn 0x%x: invalid attribute mask specified " 1935 "for transition %d to %d. qp_type %d," 1936 " attr_mask 0x%x\n", 1937 ibqp->qp_num, cur_state, new_state, 1938 ibqp->qp_type, attr_mask); 1939 goto out; 1940 } 1941 1942 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 1943 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 1944 if ((ibqp->qp_type == IB_QPT_RC) || 1945 (ibqp->qp_type == IB_QPT_UD) || 1946 (ibqp->qp_type == IB_QPT_UC) || 1947 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 1948 (ibqp->qp_type == IB_QPT_XRC_INI)) { 1949 attr->port_num = mlx4_ib_bond_next_port(dev); 1950 } 1951 } else { 1952 /* no sense in changing port_num 1953 * when ports are bonded */ 1954 attr_mask &= ~IB_QP_PORT; 1955 } 1956 } 1957 1958 if ((attr_mask & IB_QP_PORT) && 1959 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 1960 pr_debug("qpn 0x%x: invalid port number (%d) specified " 1961 "for transition %d to %d. qp_type %d\n", 1962 ibqp->qp_num, attr->port_num, cur_state, 1963 new_state, ibqp->qp_type); 1964 goto out; 1965 } 1966 1967 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 1968 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 1969 IB_LINK_LAYER_ETHERNET)) 1970 goto out; 1971 1972 if (attr_mask & IB_QP_PKEY_INDEX) { 1973 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1974 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 1975 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 1976 "for transition %d to %d. qp_type %d\n", 1977 ibqp->qp_num, attr->pkey_index, cur_state, 1978 new_state, ibqp->qp_type); 1979 goto out; 1980 } 1981 } 1982 1983 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1984 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 1985 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 1986 "Transition %d to %d. qp_type %d\n", 1987 ibqp->qp_num, attr->max_rd_atomic, cur_state, 1988 new_state, ibqp->qp_type); 1989 goto out; 1990 } 1991 1992 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1993 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 1994 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 1995 "Transition %d to %d. qp_type %d\n", 1996 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 1997 new_state, ibqp->qp_type); 1998 goto out; 1999 } 2000 2001 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2002 err = 0; 2003 goto out; 2004 } 2005 2006 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2007 2008 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2009 attr->port_num = 1; 2010 2011 out: 2012 mutex_unlock(&qp->mutex); 2013 return err; 2014 } 2015 2016 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2017 { 2018 int i; 2019 for (i = 0; i < dev->caps.num_ports; i++) { 2020 if (qpn == dev->caps.qp0_proxy[i] || 2021 qpn == dev->caps.qp0_tunnel[i]) { 2022 *qkey = dev->caps.qp0_qkey[i]; 2023 return 0; 2024 } 2025 } 2026 return -EINVAL; 2027 } 2028 2029 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2030 struct ib_send_wr *wr, 2031 void *wqe, unsigned *mlx_seg_len) 2032 { 2033 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2034 struct ib_device *ib_dev = &mdev->ib_dev; 2035 struct mlx4_wqe_mlx_seg *mlx = wqe; 2036 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2037 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2038 u16 pkey; 2039 u32 qkey; 2040 int send_size; 2041 int header_size; 2042 int spc; 2043 int i; 2044 2045 if (wr->opcode != IB_WR_SEND) 2046 return -EINVAL; 2047 2048 send_size = 0; 2049 2050 for (i = 0; i < wr->num_sge; ++i) 2051 send_size += wr->sg_list[i].length; 2052 2053 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2054 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2055 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2056 send_size += sizeof (struct mlx4_ib_tunnel_header); 2057 2058 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header); 2059 2060 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2061 sqp->ud_header.lrh.service_level = 2062 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2063 sqp->ud_header.lrh.destination_lid = 2064 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2065 sqp->ud_header.lrh.source_lid = 2066 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2067 } 2068 2069 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2070 2071 /* force loopback */ 2072 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2073 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2074 2075 sqp->ud_header.lrh.virtual_lane = 0; 2076 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2077 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2078 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2079 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2080 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2081 else 2082 sqp->ud_header.bth.destination_qpn = 2083 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]); 2084 2085 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2086 if (mlx4_is_master(mdev->dev)) { 2087 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2088 return -EINVAL; 2089 } else { 2090 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2091 return -EINVAL; 2092 } 2093 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2094 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2095 2096 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2097 sqp->ud_header.immediate_present = 0; 2098 2099 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2100 2101 /* 2102 * Inline data segments may not cross a 64 byte boundary. If 2103 * our UD header is bigger than the space available up to the 2104 * next 64 byte boundary in the WQE, use two inline data 2105 * segments to hold the UD header. 2106 */ 2107 spc = MLX4_INLINE_ALIGN - 2108 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2109 if (header_size <= spc) { 2110 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2111 memcpy(inl + 1, sqp->header_buf, header_size); 2112 i = 1; 2113 } else { 2114 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2115 memcpy(inl + 1, sqp->header_buf, spc); 2116 2117 inl = (void *) (inl + 1) + spc; 2118 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2119 /* 2120 * Need a barrier here to make sure all the data is 2121 * visible before the byte_count field is set. 2122 * Otherwise the HCA prefetcher could grab the 64-byte 2123 * chunk with this inline segment and get a valid (!= 2124 * 0xffffffff) byte count but stale data, and end up 2125 * generating a packet with bad headers. 2126 * 2127 * The first inline segment's byte_count field doesn't 2128 * need a barrier, because it comes after a 2129 * control/MLX segment and therefore is at an offset 2130 * of 16 mod 64. 2131 */ 2132 wmb(); 2133 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2134 i = 2; 2135 } 2136 2137 *mlx_seg_len = 2138 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2139 return 0; 2140 } 2141 2142 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac) 2143 { 2144 int i; 2145 2146 for (i = ETH_ALEN; i; i--) { 2147 dst_mac[i - 1] = src_mac & 0xff; 2148 src_mac >>= 8; 2149 } 2150 } 2151 2152 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, 2153 void *wqe, unsigned *mlx_seg_len) 2154 { 2155 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2156 struct mlx4_wqe_mlx_seg *mlx = wqe; 2157 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2158 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2159 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2160 union ib_gid sgid; 2161 u16 pkey; 2162 int send_size; 2163 int header_size; 2164 int spc; 2165 int i; 2166 int err = 0; 2167 u16 vlan = 0xffff; 2168 bool is_eth; 2169 bool is_vlan = false; 2170 bool is_grh; 2171 2172 send_size = 0; 2173 for (i = 0; i < wr->num_sge; ++i) 2174 send_size += wr->sg_list[i].length; 2175 2176 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2177 is_grh = mlx4_ib_ah_grh_present(ah); 2178 if (is_eth) { 2179 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2180 /* When multi-function is enabled, the ib_core gid 2181 * indexes don't necessarily match the hw ones, so 2182 * we must use our own cache */ 2183 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2184 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2185 ah->av.ib.gid_index, &sgid.raw[0]); 2186 if (err) 2187 return err; 2188 } else { 2189 err = ib_get_cached_gid(ib_dev, 2190 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2191 ah->av.ib.gid_index, &sgid); 2192 if (err) 2193 return err; 2194 } 2195 2196 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 2197 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 2198 is_vlan = 1; 2199 } 2200 } 2201 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header); 2202 2203 if (!is_eth) { 2204 sqp->ud_header.lrh.service_level = 2205 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2206 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 2207 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2208 } 2209 2210 if (is_grh) { 2211 sqp->ud_header.grh.traffic_class = 2212 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2213 sqp->ud_header.grh.flow_label = 2214 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 2215 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 2216 if (is_eth) 2217 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 2218 else { 2219 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2220 /* When multi-function is enabled, the ib_core gid 2221 * indexes don't necessarily match the hw ones, so 2222 * we must use our own cache */ 2223 sqp->ud_header.grh.source_gid.global.subnet_prefix = 2224 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2225 subnet_prefix; 2226 sqp->ud_header.grh.source_gid.global.interface_id = 2227 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2228 guid_cache[ah->av.ib.gid_index]; 2229 } else 2230 ib_get_cached_gid(ib_dev, 2231 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2232 ah->av.ib.gid_index, 2233 &sqp->ud_header.grh.source_gid); 2234 } 2235 memcpy(sqp->ud_header.grh.destination_gid.raw, 2236 ah->av.ib.dgid, 16); 2237 } 2238 2239 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2240 2241 if (!is_eth) { 2242 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 2243 (sqp->ud_header.lrh.destination_lid == 2244 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 2245 (sqp->ud_header.lrh.service_level << 8)); 2246 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 2247 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 2248 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2249 } 2250 2251 switch (wr->opcode) { 2252 case IB_WR_SEND: 2253 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2254 sqp->ud_header.immediate_present = 0; 2255 break; 2256 case IB_WR_SEND_WITH_IMM: 2257 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2258 sqp->ud_header.immediate_present = 1; 2259 sqp->ud_header.immediate_data = wr->ex.imm_data; 2260 break; 2261 default: 2262 return -EINVAL; 2263 } 2264 2265 if (is_eth) { 2266 struct in6_addr in6; 2267 2268 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 2269 2270 mlx->sched_prio = cpu_to_be16(pcp); 2271 2272 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 2273 /* FIXME: cache smac value? */ 2274 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 2275 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 2276 memcpy(&in6, sgid.raw, sizeof(in6)); 2277 2278 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2279 u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]); 2280 u8 smac[ETH_ALEN]; 2281 2282 mlx4_u64_to_smac(smac, mac); 2283 memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN); 2284 } else { 2285 /* use the src mac of the tunnel */ 2286 memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN); 2287 } 2288 2289 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 2290 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 2291 if (!is_vlan) { 2292 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2293 } else { 2294 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2295 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 2296 } 2297 } else { 2298 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 2299 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 2300 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 2301 } 2302 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2303 if (!sqp->qp.ibqp.qp_num) 2304 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 2305 else 2306 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey); 2307 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2308 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2309 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2310 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 2311 sqp->qkey : wr->wr.ud.remote_qkey); 2312 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 2313 2314 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2315 2316 if (0) { 2317 pr_err("built UD header of size %d:\n", header_size); 2318 for (i = 0; i < header_size / 4; ++i) { 2319 if (i % 8 == 0) 2320 pr_err(" [%02x] ", i * 4); 2321 pr_cont(" %08x", 2322 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 2323 if ((i + 1) % 8 == 0) 2324 pr_cont("\n"); 2325 } 2326 pr_err("\n"); 2327 } 2328 2329 /* 2330 * Inline data segments may not cross a 64 byte boundary. If 2331 * our UD header is bigger than the space available up to the 2332 * next 64 byte boundary in the WQE, use two inline data 2333 * segments to hold the UD header. 2334 */ 2335 spc = MLX4_INLINE_ALIGN - 2336 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2337 if (header_size <= spc) { 2338 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2339 memcpy(inl + 1, sqp->header_buf, header_size); 2340 i = 1; 2341 } else { 2342 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2343 memcpy(inl + 1, sqp->header_buf, spc); 2344 2345 inl = (void *) (inl + 1) + spc; 2346 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2347 /* 2348 * Need a barrier here to make sure all the data is 2349 * visible before the byte_count field is set. 2350 * Otherwise the HCA prefetcher could grab the 64-byte 2351 * chunk with this inline segment and get a valid (!= 2352 * 0xffffffff) byte count but stale data, and end up 2353 * generating a packet with bad headers. 2354 * 2355 * The first inline segment's byte_count field doesn't 2356 * need a barrier, because it comes after a 2357 * control/MLX segment and therefore is at an offset 2358 * of 16 mod 64. 2359 */ 2360 wmb(); 2361 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2362 i = 2; 2363 } 2364 2365 *mlx_seg_len = 2366 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2367 return 0; 2368 } 2369 2370 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2371 { 2372 unsigned cur; 2373 struct mlx4_ib_cq *cq; 2374 2375 cur = wq->head - wq->tail; 2376 if (likely(cur + nreq < wq->max_post)) 2377 return 0; 2378 2379 cq = to_mcq(ib_cq); 2380 spin_lock(&cq->lock); 2381 cur = wq->head - wq->tail; 2382 spin_unlock(&cq->lock); 2383 2384 return cur + nreq >= wq->max_post; 2385 } 2386 2387 static __be32 convert_access(int acc) 2388 { 2389 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 2390 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 2391 (acc & IB_ACCESS_REMOTE_WRITE ? 2392 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 2393 (acc & IB_ACCESS_REMOTE_READ ? 2394 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 2395 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 2396 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 2397 } 2398 2399 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr) 2400 { 2401 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 2402 int i; 2403 2404 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i) 2405 mfrpl->mapped_page_list[i] = 2406 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] | 2407 MLX4_MTT_FLAG_PRESENT); 2408 2409 fseg->flags = convert_access(wr->wr.fast_reg.access_flags); 2410 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey); 2411 fseg->buf_list = cpu_to_be64(mfrpl->map); 2412 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 2413 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length); 2414 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 2415 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift); 2416 fseg->reserved[0] = 0; 2417 fseg->reserved[1] = 0; 2418 } 2419 2420 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr) 2421 { 2422 bseg->flags1 = 2423 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) & 2424 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ | 2425 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE | 2426 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC); 2427 bseg->flags2 = 0; 2428 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2) 2429 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2); 2430 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED) 2431 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED); 2432 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey); 2433 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey); 2434 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr); 2435 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length); 2436 } 2437 2438 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 2439 { 2440 memset(iseg, 0, sizeof(*iseg)); 2441 iseg->mem_key = cpu_to_be32(rkey); 2442 } 2443 2444 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 2445 u64 remote_addr, u32 rkey) 2446 { 2447 rseg->raddr = cpu_to_be64(remote_addr); 2448 rseg->rkey = cpu_to_be32(rkey); 2449 rseg->reserved = 0; 2450 } 2451 2452 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr) 2453 { 2454 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 2455 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2456 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2457 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 2458 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2459 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2460 } else { 2461 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2462 aseg->compare = 0; 2463 } 2464 2465 } 2466 2467 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 2468 struct ib_send_wr *wr) 2469 { 2470 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2471 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask); 2472 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2473 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2474 } 2475 2476 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 2477 struct ib_send_wr *wr) 2478 { 2479 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); 2480 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2481 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2482 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan; 2483 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6); 2484 } 2485 2486 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 2487 struct mlx4_wqe_datagram_seg *dseg, 2488 struct ib_send_wr *wr, 2489 enum mlx4_ib_qp_type qpt) 2490 { 2491 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av; 2492 struct mlx4_av sqp_av = {0}; 2493 int port = *((u8 *) &av->ib.port_pd) & 0x3; 2494 2495 /* force loopback */ 2496 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 2497 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 2498 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 2499 cpu_to_be32(0xf0000000); 2500 2501 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 2502 if (qpt == MLX4_IB_QPT_PROXY_GSI) 2503 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]); 2504 else 2505 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]); 2506 /* Use QKEY from the QP context, which is set by master */ 2507 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2508 } 2509 2510 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len) 2511 { 2512 struct mlx4_wqe_inline_seg *inl = wqe; 2513 struct mlx4_ib_tunnel_header hdr; 2514 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2515 int spc; 2516 int i; 2517 2518 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 2519 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2520 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index); 2521 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2522 memcpy(hdr.mac, ah->av.eth.mac, 6); 2523 hdr.vlan = ah->av.eth.vlan; 2524 2525 spc = MLX4_INLINE_ALIGN - 2526 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2527 if (sizeof (hdr) <= spc) { 2528 memcpy(inl + 1, &hdr, sizeof (hdr)); 2529 wmb(); 2530 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 2531 i = 1; 2532 } else { 2533 memcpy(inl + 1, &hdr, spc); 2534 wmb(); 2535 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2536 2537 inl = (void *) (inl + 1) + spc; 2538 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 2539 wmb(); 2540 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 2541 i = 2; 2542 } 2543 2544 *mlx_seg_len = 2545 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 2546 } 2547 2548 static void set_mlx_icrc_seg(void *dseg) 2549 { 2550 u32 *t = dseg; 2551 struct mlx4_wqe_inline_seg *iseg = dseg; 2552 2553 t[1] = 0; 2554 2555 /* 2556 * Need a barrier here before writing the byte_count field to 2557 * make sure that all the data is visible before the 2558 * byte_count field is set. Otherwise, if the segment begins 2559 * a new cacheline, the HCA prefetcher could grab the 64-byte 2560 * chunk and get a valid (!= * 0xffffffff) byte count but 2561 * stale data, and end up sending the wrong data. 2562 */ 2563 wmb(); 2564 2565 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 2566 } 2567 2568 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2569 { 2570 dseg->lkey = cpu_to_be32(sg->lkey); 2571 dseg->addr = cpu_to_be64(sg->addr); 2572 2573 /* 2574 * Need a barrier here before writing the byte_count field to 2575 * make sure that all the data is visible before the 2576 * byte_count field is set. Otherwise, if the segment begins 2577 * a new cacheline, the HCA prefetcher could grab the 64-byte 2578 * chunk and get a valid (!= * 0xffffffff) byte count but 2579 * stale data, and end up sending the wrong data. 2580 */ 2581 wmb(); 2582 2583 dseg->byte_count = cpu_to_be32(sg->length); 2584 } 2585 2586 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2587 { 2588 dseg->byte_count = cpu_to_be32(sg->length); 2589 dseg->lkey = cpu_to_be32(sg->lkey); 2590 dseg->addr = cpu_to_be64(sg->addr); 2591 } 2592 2593 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr, 2594 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 2595 __be32 *lso_hdr_sz, __be32 *blh) 2596 { 2597 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16); 2598 2599 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 2600 *blh = cpu_to_be32(1 << 6); 2601 2602 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 2603 wr->num_sge > qp->sq.max_gs - (halign >> 4))) 2604 return -EINVAL; 2605 2606 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen); 2607 2608 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 | 2609 wr->wr.ud.hlen); 2610 *lso_seg_len = halign; 2611 return 0; 2612 } 2613 2614 static __be32 send_ieth(struct ib_send_wr *wr) 2615 { 2616 switch (wr->opcode) { 2617 case IB_WR_SEND_WITH_IMM: 2618 case IB_WR_RDMA_WRITE_WITH_IMM: 2619 return wr->ex.imm_data; 2620 2621 case IB_WR_SEND_WITH_INV: 2622 return cpu_to_be32(wr->ex.invalidate_rkey); 2623 2624 default: 2625 return 0; 2626 } 2627 } 2628 2629 static void add_zero_len_inline(void *wqe) 2630 { 2631 struct mlx4_wqe_inline_seg *inl = wqe; 2632 memset(wqe, 0, 16); 2633 inl->byte_count = cpu_to_be32(1 << 31); 2634 } 2635 2636 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2637 struct ib_send_wr **bad_wr) 2638 { 2639 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2640 void *wqe; 2641 struct mlx4_wqe_ctrl_seg *ctrl; 2642 struct mlx4_wqe_data_seg *dseg; 2643 unsigned long flags; 2644 int nreq; 2645 int err = 0; 2646 unsigned ind; 2647 int uninitialized_var(stamp); 2648 int uninitialized_var(size); 2649 unsigned uninitialized_var(seglen); 2650 __be32 dummy; 2651 __be32 *lso_wqe; 2652 __be32 uninitialized_var(lso_hdr_sz); 2653 __be32 blh; 2654 int i; 2655 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2656 2657 spin_lock_irqsave(&qp->sq.lock, flags); 2658 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 2659 err = -EIO; 2660 *bad_wr = wr; 2661 nreq = 0; 2662 goto out; 2663 } 2664 2665 ind = qp->sq_next_wqe; 2666 2667 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2668 lso_wqe = &dummy; 2669 blh = 0; 2670 2671 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 2672 err = -ENOMEM; 2673 *bad_wr = wr; 2674 goto out; 2675 } 2676 2677 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 2678 err = -EINVAL; 2679 *bad_wr = wr; 2680 goto out; 2681 } 2682 2683 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 2684 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 2685 2686 ctrl->srcrb_flags = 2687 (wr->send_flags & IB_SEND_SIGNALED ? 2688 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 2689 (wr->send_flags & IB_SEND_SOLICITED ? 2690 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 2691 ((wr->send_flags & IB_SEND_IP_CSUM) ? 2692 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 2693 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 2694 qp->sq_signal_bits; 2695 2696 ctrl->imm = send_ieth(wr); 2697 2698 wqe += sizeof *ctrl; 2699 size = sizeof *ctrl / 16; 2700 2701 switch (qp->mlx4_ib_qp_type) { 2702 case MLX4_IB_QPT_RC: 2703 case MLX4_IB_QPT_UC: 2704 switch (wr->opcode) { 2705 case IB_WR_ATOMIC_CMP_AND_SWP: 2706 case IB_WR_ATOMIC_FETCH_AND_ADD: 2707 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 2708 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 2709 wr->wr.atomic.rkey); 2710 wqe += sizeof (struct mlx4_wqe_raddr_seg); 2711 2712 set_atomic_seg(wqe, wr); 2713 wqe += sizeof (struct mlx4_wqe_atomic_seg); 2714 2715 size += (sizeof (struct mlx4_wqe_raddr_seg) + 2716 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 2717 2718 break; 2719 2720 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 2721 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 2722 wr->wr.atomic.rkey); 2723 wqe += sizeof (struct mlx4_wqe_raddr_seg); 2724 2725 set_masked_atomic_seg(wqe, wr); 2726 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 2727 2728 size += (sizeof (struct mlx4_wqe_raddr_seg) + 2729 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 2730 2731 break; 2732 2733 case IB_WR_RDMA_READ: 2734 case IB_WR_RDMA_WRITE: 2735 case IB_WR_RDMA_WRITE_WITH_IMM: 2736 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 2737 wr->wr.rdma.rkey); 2738 wqe += sizeof (struct mlx4_wqe_raddr_seg); 2739 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 2740 break; 2741 2742 case IB_WR_LOCAL_INV: 2743 ctrl->srcrb_flags |= 2744 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 2745 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 2746 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 2747 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 2748 break; 2749 2750 case IB_WR_FAST_REG_MR: 2751 ctrl->srcrb_flags |= 2752 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 2753 set_fmr_seg(wqe, wr); 2754 wqe += sizeof (struct mlx4_wqe_fmr_seg); 2755 size += sizeof (struct mlx4_wqe_fmr_seg) / 16; 2756 break; 2757 2758 case IB_WR_BIND_MW: 2759 ctrl->srcrb_flags |= 2760 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 2761 set_bind_seg(wqe, wr); 2762 wqe += sizeof(struct mlx4_wqe_bind_seg); 2763 size += sizeof(struct mlx4_wqe_bind_seg) / 16; 2764 break; 2765 default: 2766 /* No extra segments required for sends */ 2767 break; 2768 } 2769 break; 2770 2771 case MLX4_IB_QPT_TUN_SMI_OWNER: 2772 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 2773 if (unlikely(err)) { 2774 *bad_wr = wr; 2775 goto out; 2776 } 2777 wqe += seglen; 2778 size += seglen / 16; 2779 break; 2780 case MLX4_IB_QPT_TUN_SMI: 2781 case MLX4_IB_QPT_TUN_GSI: 2782 /* this is a UD qp used in MAD responses to slaves. */ 2783 set_datagram_seg(wqe, wr); 2784 /* set the forced-loopback bit in the data seg av */ 2785 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 2786 wqe += sizeof (struct mlx4_wqe_datagram_seg); 2787 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 2788 break; 2789 case MLX4_IB_QPT_UD: 2790 set_datagram_seg(wqe, wr); 2791 wqe += sizeof (struct mlx4_wqe_datagram_seg); 2792 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 2793 2794 if (wr->opcode == IB_WR_LSO) { 2795 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh); 2796 if (unlikely(err)) { 2797 *bad_wr = wr; 2798 goto out; 2799 } 2800 lso_wqe = (__be32 *) wqe; 2801 wqe += seglen; 2802 size += seglen / 16; 2803 } 2804 break; 2805 2806 case MLX4_IB_QPT_PROXY_SMI_OWNER: 2807 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 2808 if (unlikely(err)) { 2809 *bad_wr = wr; 2810 goto out; 2811 } 2812 wqe += seglen; 2813 size += seglen / 16; 2814 /* to start tunnel header on a cache-line boundary */ 2815 add_zero_len_inline(wqe); 2816 wqe += 16; 2817 size++; 2818 build_tunnel_header(wr, wqe, &seglen); 2819 wqe += seglen; 2820 size += seglen / 16; 2821 break; 2822 case MLX4_IB_QPT_PROXY_SMI: 2823 case MLX4_IB_QPT_PROXY_GSI: 2824 /* If we are tunneling special qps, this is a UD qp. 2825 * In this case we first add a UD segment targeting 2826 * the tunnel qp, and then add a header with address 2827 * information */ 2828 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, 2829 qp->mlx4_ib_qp_type); 2830 wqe += sizeof (struct mlx4_wqe_datagram_seg); 2831 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 2832 build_tunnel_header(wr, wqe, &seglen); 2833 wqe += seglen; 2834 size += seglen / 16; 2835 break; 2836 2837 case MLX4_IB_QPT_SMI: 2838 case MLX4_IB_QPT_GSI: 2839 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen); 2840 if (unlikely(err)) { 2841 *bad_wr = wr; 2842 goto out; 2843 } 2844 wqe += seglen; 2845 size += seglen / 16; 2846 break; 2847 2848 default: 2849 break; 2850 } 2851 2852 /* 2853 * Write data segments in reverse order, so as to 2854 * overwrite cacheline stamp last within each 2855 * cacheline. This avoids issues with WQE 2856 * prefetching. 2857 */ 2858 2859 dseg = wqe; 2860 dseg += wr->num_sge - 1; 2861 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 2862 2863 /* Add one more inline data segment for ICRC for MLX sends */ 2864 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2865 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 2866 qp->mlx4_ib_qp_type & 2867 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 2868 set_mlx_icrc_seg(dseg + 1); 2869 size += sizeof (struct mlx4_wqe_data_seg) / 16; 2870 } 2871 2872 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 2873 set_data_seg(dseg, wr->sg_list + i); 2874 2875 /* 2876 * Possibly overwrite stamping in cacheline with LSO 2877 * segment only after making sure all data segments 2878 * are written. 2879 */ 2880 wmb(); 2881 *lso_wqe = lso_hdr_sz; 2882 2883 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 2884 MLX4_WQE_CTRL_FENCE : 0) | size; 2885 2886 /* 2887 * Make sure descriptor is fully written before 2888 * setting ownership bit (because HW can start 2889 * executing as soon as we do). 2890 */ 2891 wmb(); 2892 2893 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 2894 *bad_wr = wr; 2895 err = -EINVAL; 2896 goto out; 2897 } 2898 2899 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 2900 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 2901 2902 stamp = ind + qp->sq_spare_wqes; 2903 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 2904 2905 /* 2906 * We can improve latency by not stamping the last 2907 * send queue WQE until after ringing the doorbell, so 2908 * only stamp here if there are still more WQEs to post. 2909 * 2910 * Same optimization applies to padding with NOP wqe 2911 * in case of WQE shrinking (used to prevent wrap-around 2912 * in the middle of WR). 2913 */ 2914 if (wr->next) { 2915 stamp_send_wqe(qp, stamp, size * 16); 2916 ind = pad_wraparound(qp, ind); 2917 } 2918 } 2919 2920 out: 2921 if (likely(nreq)) { 2922 qp->sq.head += nreq; 2923 2924 /* 2925 * Make sure that descriptors are written before 2926 * doorbell record. 2927 */ 2928 wmb(); 2929 2930 writel(qp->doorbell_qpn, 2931 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 2932 2933 /* 2934 * Make sure doorbells don't leak out of SQ spinlock 2935 * and reach the HCA out of order. 2936 */ 2937 mmiowb(); 2938 2939 stamp_send_wqe(qp, stamp, size * 16); 2940 2941 ind = pad_wraparound(qp, ind); 2942 qp->sq_next_wqe = ind; 2943 } 2944 2945 spin_unlock_irqrestore(&qp->sq.lock, flags); 2946 2947 return err; 2948 } 2949 2950 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2951 struct ib_recv_wr **bad_wr) 2952 { 2953 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2954 struct mlx4_wqe_data_seg *scat; 2955 unsigned long flags; 2956 int err = 0; 2957 int nreq; 2958 int ind; 2959 int max_gs; 2960 int i; 2961 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2962 2963 max_gs = qp->rq.max_gs; 2964 spin_lock_irqsave(&qp->rq.lock, flags); 2965 2966 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 2967 err = -EIO; 2968 *bad_wr = wr; 2969 nreq = 0; 2970 goto out; 2971 } 2972 2973 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 2974 2975 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2976 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2977 err = -ENOMEM; 2978 *bad_wr = wr; 2979 goto out; 2980 } 2981 2982 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2983 err = -EINVAL; 2984 *bad_wr = wr; 2985 goto out; 2986 } 2987 2988 scat = get_recv_wqe(qp, ind); 2989 2990 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 2991 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 2992 ib_dma_sync_single_for_device(ibqp->device, 2993 qp->sqp_proxy_rcv[ind].map, 2994 sizeof (struct mlx4_ib_proxy_sqp_hdr), 2995 DMA_FROM_DEVICE); 2996 scat->byte_count = 2997 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 2998 /* use dma lkey from upper layer entry */ 2999 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3000 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3001 scat++; 3002 max_gs--; 3003 } 3004 3005 for (i = 0; i < wr->num_sge; ++i) 3006 __set_data_seg(scat + i, wr->sg_list + i); 3007 3008 if (i < max_gs) { 3009 scat[i].byte_count = 0; 3010 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3011 scat[i].addr = 0; 3012 } 3013 3014 qp->rq.wrid[ind] = wr->wr_id; 3015 3016 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3017 } 3018 3019 out: 3020 if (likely(nreq)) { 3021 qp->rq.head += nreq; 3022 3023 /* 3024 * Make sure that descriptors are written before 3025 * doorbell record. 3026 */ 3027 wmb(); 3028 3029 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3030 } 3031 3032 spin_unlock_irqrestore(&qp->rq.lock, flags); 3033 3034 return err; 3035 } 3036 3037 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3038 { 3039 switch (mlx4_state) { 3040 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3041 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3042 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3043 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3044 case MLX4_QP_STATE_SQ_DRAINING: 3045 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3046 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3047 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3048 default: return -1; 3049 } 3050 } 3051 3052 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3053 { 3054 switch (mlx4_mig_state) { 3055 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3056 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3057 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3058 default: return -1; 3059 } 3060 } 3061 3062 static int to_ib_qp_access_flags(int mlx4_flags) 3063 { 3064 int ib_flags = 0; 3065 3066 if (mlx4_flags & MLX4_QP_BIT_RRE) 3067 ib_flags |= IB_ACCESS_REMOTE_READ; 3068 if (mlx4_flags & MLX4_QP_BIT_RWE) 3069 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3070 if (mlx4_flags & MLX4_QP_BIT_RAE) 3071 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3072 3073 return ib_flags; 3074 } 3075 3076 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3077 struct mlx4_qp_path *path) 3078 { 3079 struct mlx4_dev *dev = ibdev->dev; 3080 int is_eth; 3081 3082 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 3083 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; 3084 3085 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 3086 return; 3087 3088 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) == 3089 IB_LINK_LAYER_ETHERNET; 3090 if (is_eth) 3091 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) | 3092 ((path->sched_queue & 4) << 1); 3093 else 3094 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; 3095 3096 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3097 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; 3098 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3099 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 3100 if (ib_ah_attr->ah_flags) { 3101 ib_ah_attr->grh.sgid_index = path->mgid_index; 3102 ib_ah_attr->grh.hop_limit = path->hop_limit; 3103 ib_ah_attr->grh.traffic_class = 3104 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3105 ib_ah_attr->grh.flow_label = 3106 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3107 memcpy(ib_ah_attr->grh.dgid.raw, 3108 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 3109 } 3110 } 3111 3112 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3113 struct ib_qp_init_attr *qp_init_attr) 3114 { 3115 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3116 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3117 struct mlx4_qp_context context; 3118 int mlx4_state; 3119 int err = 0; 3120 3121 mutex_lock(&qp->mutex); 3122 3123 if (qp->state == IB_QPS_RESET) { 3124 qp_attr->qp_state = IB_QPS_RESET; 3125 goto done; 3126 } 3127 3128 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3129 if (err) { 3130 err = -EINVAL; 3131 goto out; 3132 } 3133 3134 mlx4_state = be32_to_cpu(context.flags) >> 28; 3135 3136 qp->state = to_ib_qp_state(mlx4_state); 3137 qp_attr->qp_state = qp->state; 3138 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3139 qp_attr->path_mig_state = 3140 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3141 qp_attr->qkey = be32_to_cpu(context.qkey); 3142 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3143 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3144 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3145 qp_attr->qp_access_flags = 3146 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3147 3148 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3149 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3150 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3151 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3152 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3153 } 3154 3155 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3156 if (qp_attr->qp_state == IB_QPS_INIT) 3157 qp_attr->port_num = qp->port; 3158 else 3159 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3160 3161 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3162 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3163 3164 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3165 3166 qp_attr->max_dest_rd_atomic = 3167 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3168 qp_attr->min_rnr_timer = 3169 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3170 qp_attr->timeout = context.pri_path.ackto >> 3; 3171 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3172 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3173 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3174 3175 done: 3176 qp_attr->cur_qp_state = qp_attr->qp_state; 3177 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3178 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3179 3180 if (!ibqp->uobject) { 3181 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3182 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3183 } else { 3184 qp_attr->cap.max_send_wr = 0; 3185 qp_attr->cap.max_send_sge = 0; 3186 } 3187 3188 /* 3189 * We don't support inline sends for kernel QPs (yet), and we 3190 * don't know what userspace's value should be. 3191 */ 3192 qp_attr->cap.max_inline_data = 0; 3193 3194 qp_init_attr->cap = qp_attr->cap; 3195 3196 qp_init_attr->create_flags = 0; 3197 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3198 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3199 3200 if (qp->flags & MLX4_IB_QP_LSO) 3201 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 3202 3203 if (qp->flags & MLX4_IB_QP_NETIF) 3204 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 3205 3206 qp_init_attr->sq_sig_type = 3207 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 3208 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3209 3210 out: 3211 mutex_unlock(&qp->mutex); 3212 return err; 3213 } 3214 3215