1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include <rdma/mlx4-abi.h> 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 57 struct ib_udata *udata); 58 59 enum { 60 MLX4_IB_ACK_REQ_FREQ = 8, 61 }; 62 63 enum { 64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 66 MLX4_IB_LINK_TYPE_IB = 0, 67 MLX4_IB_LINK_TYPE_ETH = 1 68 }; 69 70 enum { 71 /* 72 * Largest possible UD header: send with GRH and immediate 73 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 74 * tag. (LRH would only use 8 bytes, so Ethernet is the 75 * biggest case) 76 */ 77 MLX4_IB_UD_HEADER_SIZE = 82, 78 MLX4_IB_LSO_HEADER_SPARE = 128, 79 }; 80 81 struct mlx4_ib_sqp { 82 struct mlx4_ib_qp qp; 83 int pkey_index; 84 u32 qkey; 85 u32 send_psn; 86 struct ib_ud_header ud_header; 87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 88 struct ib_qp *roce_v2_gsi; 89 }; 90 91 enum { 92 MLX4_IB_MIN_SQ_STRIDE = 6, 93 MLX4_IB_CACHE_LINE_SIZE = 64, 94 }; 95 96 enum { 97 MLX4_RAW_QP_MTU = 7, 98 MLX4_RAW_QP_MSGMAX = 31, 99 }; 100 101 #ifndef ETH_ALEN 102 #define ETH_ALEN 6 103 #endif 104 105 static const __be32 mlx4_ib_opcode[] = { 106 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 107 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 108 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 109 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 110 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 111 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 112 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 113 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 114 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 115 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 116 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 117 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 118 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 119 }; 120 121 enum mlx4_ib_source_type { 122 MLX4_IB_QP_SRC = 0, 123 MLX4_IB_RWQ_SRC = 1, 124 }; 125 126 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 127 { 128 return container_of(mqp, struct mlx4_ib_sqp, qp); 129 } 130 131 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 132 { 133 if (!mlx4_is_master(dev->dev)) 134 return 0; 135 136 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 137 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 138 8 * MLX4_MFUNC_MAX; 139 } 140 141 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 142 { 143 int proxy_sqp = 0; 144 int real_sqp = 0; 145 int i; 146 /* PPF or Native -- real SQP */ 147 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 148 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 149 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 150 if (real_sqp) 151 return 1; 152 /* VF or PF -- proxy SQP */ 153 if (mlx4_is_mfunc(dev->dev)) { 154 for (i = 0; i < dev->dev->caps.num_ports; i++) { 155 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 156 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 157 proxy_sqp = 1; 158 break; 159 } 160 } 161 } 162 if (proxy_sqp) 163 return 1; 164 165 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 166 } 167 168 /* used for INIT/CLOSE port logic */ 169 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 170 { 171 int proxy_qp0 = 0; 172 int real_qp0 = 0; 173 int i; 174 /* PPF or Native -- real QP0 */ 175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 178 if (real_qp0) 179 return 1; 180 /* VF or PF -- proxy QP0 */ 181 if (mlx4_is_mfunc(dev->dev)) { 182 for (i = 0; i < dev->dev->caps.num_ports; i++) { 183 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 184 proxy_qp0 = 1; 185 break; 186 } 187 } 188 } 189 return proxy_qp0; 190 } 191 192 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 193 { 194 return mlx4_buf_offset(&qp->buf, offset); 195 } 196 197 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 198 { 199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 200 } 201 202 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 203 { 204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 205 } 206 207 /* 208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 209 * first four bytes of every 64 byte chunk with 0xffffffff, except for 210 * the very first chunk of the WQE. 211 */ 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 213 { 214 __be32 *wqe; 215 int i; 216 int s; 217 void *buf; 218 struct mlx4_wqe_ctrl_seg *ctrl; 219 220 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 221 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 222 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 223 for (i = 64; i < s; i += 64) { 224 wqe = buf + i; 225 *wqe = cpu_to_be32(0xffffffff); 226 } 227 } 228 229 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 230 { 231 struct ib_event event; 232 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 233 234 if (type == MLX4_EVENT_TYPE_PATH_MIG) 235 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 236 237 if (ibqp->event_handler) { 238 event.device = ibqp->device; 239 event.element.qp = ibqp; 240 switch (type) { 241 case MLX4_EVENT_TYPE_PATH_MIG: 242 event.event = IB_EVENT_PATH_MIG; 243 break; 244 case MLX4_EVENT_TYPE_COMM_EST: 245 event.event = IB_EVENT_COMM_EST; 246 break; 247 case MLX4_EVENT_TYPE_SQ_DRAINED: 248 event.event = IB_EVENT_SQ_DRAINED; 249 break; 250 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 251 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 252 break; 253 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 254 event.event = IB_EVENT_QP_FATAL; 255 break; 256 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 257 event.event = IB_EVENT_PATH_MIG_ERR; 258 break; 259 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 260 event.event = IB_EVENT_QP_REQ_ERR; 261 break; 262 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 263 event.event = IB_EVENT_QP_ACCESS_ERR; 264 break; 265 default: 266 pr_warn("Unexpected event type %d " 267 "on QP %06x\n", type, qp->qpn); 268 return; 269 } 270 271 ibqp->event_handler(&event, ibqp->qp_context); 272 } 273 } 274 275 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 276 { 277 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 278 type, qp->qpn); 279 } 280 281 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 282 { 283 /* 284 * UD WQEs must have a datagram segment. 285 * RC and UC WQEs might have a remote address segment. 286 * MLX WQEs need two extra inline data segments (for the UD 287 * header and space for the ICRC). 288 */ 289 switch (type) { 290 case MLX4_IB_QPT_UD: 291 return sizeof (struct mlx4_wqe_ctrl_seg) + 292 sizeof (struct mlx4_wqe_datagram_seg) + 293 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 294 case MLX4_IB_QPT_PROXY_SMI_OWNER: 295 case MLX4_IB_QPT_PROXY_SMI: 296 case MLX4_IB_QPT_PROXY_GSI: 297 return sizeof (struct mlx4_wqe_ctrl_seg) + 298 sizeof (struct mlx4_wqe_datagram_seg) + 64; 299 case MLX4_IB_QPT_TUN_SMI_OWNER: 300 case MLX4_IB_QPT_TUN_GSI: 301 return sizeof (struct mlx4_wqe_ctrl_seg) + 302 sizeof (struct mlx4_wqe_datagram_seg); 303 304 case MLX4_IB_QPT_UC: 305 return sizeof (struct mlx4_wqe_ctrl_seg) + 306 sizeof (struct mlx4_wqe_raddr_seg); 307 case MLX4_IB_QPT_RC: 308 return sizeof (struct mlx4_wqe_ctrl_seg) + 309 sizeof (struct mlx4_wqe_masked_atomic_seg) + 310 sizeof (struct mlx4_wqe_raddr_seg); 311 case MLX4_IB_QPT_SMI: 312 case MLX4_IB_QPT_GSI: 313 return sizeof (struct mlx4_wqe_ctrl_seg) + 314 ALIGN(MLX4_IB_UD_HEADER_SIZE + 315 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 316 MLX4_INLINE_ALIGN) * 317 sizeof (struct mlx4_wqe_inline_seg), 318 sizeof (struct mlx4_wqe_data_seg)) + 319 ALIGN(4 + 320 sizeof (struct mlx4_wqe_inline_seg), 321 sizeof (struct mlx4_wqe_data_seg)); 322 default: 323 return sizeof (struct mlx4_wqe_ctrl_seg); 324 } 325 } 326 327 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 328 bool is_user, int has_rq, struct mlx4_ib_qp *qp, 329 u32 inl_recv_sz) 330 { 331 /* Sanity check RQ size before proceeding */ 332 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 333 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 334 return -EINVAL; 335 336 if (!has_rq) { 337 if (cap->max_recv_wr || inl_recv_sz) 338 return -EINVAL; 339 340 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 341 } else { 342 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 343 sizeof(struct mlx4_wqe_data_seg); 344 u32 wqe_size; 345 346 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 347 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 348 inl_recv_sz > max_inl_recv_sz)) 349 return -EINVAL; 350 351 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 352 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 353 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 354 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 355 } 356 357 /* leave userspace return values as they were, so as not to break ABI */ 358 if (is_user) { 359 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 360 cap->max_recv_sge = qp->rq.max_gs; 361 } else { 362 cap->max_recv_wr = qp->rq.max_post = 363 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 364 cap->max_recv_sge = min(qp->rq.max_gs, 365 min(dev->dev->caps.max_sq_sg, 366 dev->dev->caps.max_rq_sg)); 367 } 368 369 return 0; 370 } 371 372 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 373 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 374 { 375 int s; 376 377 /* Sanity check SQ size before proceeding */ 378 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 379 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 380 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 381 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 382 return -EINVAL; 383 384 /* 385 * For MLX transport we need 2 extra S/G entries: 386 * one for the header and one for the checksum at the end 387 */ 388 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 389 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 390 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 391 return -EINVAL; 392 393 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 394 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 395 send_wqe_overhead(type, qp->flags); 396 397 if (s > dev->dev->caps.max_sq_desc_sz) 398 return -EINVAL; 399 400 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 401 402 /* 403 * We need to leave 2 KB + 1 WR of headroom in the SQ to 404 * allow HW to prefetch. 405 */ 406 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 407 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 408 qp->sq_spare_wqes); 409 410 qp->sq.max_gs = 411 (min(dev->dev->caps.max_sq_desc_sz, 412 (1 << qp->sq.wqe_shift)) - 413 send_wqe_overhead(type, qp->flags)) / 414 sizeof (struct mlx4_wqe_data_seg); 415 416 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 417 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 418 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 419 qp->rq.offset = 0; 420 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 421 } else { 422 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 423 qp->sq.offset = 0; 424 } 425 426 cap->max_send_wr = qp->sq.max_post = 427 qp->sq.wqe_cnt - qp->sq_spare_wqes; 428 cap->max_send_sge = min(qp->sq.max_gs, 429 min(dev->dev->caps.max_sq_sg, 430 dev->dev->caps.max_rq_sg)); 431 /* We don't support inline sends for kernel QPs (yet) */ 432 cap->max_inline_data = 0; 433 434 return 0; 435 } 436 437 static int set_user_sq_size(struct mlx4_ib_dev *dev, 438 struct mlx4_ib_qp *qp, 439 struct mlx4_ib_create_qp *ucmd) 440 { 441 /* Sanity check SQ size before proceeding */ 442 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 443 ucmd->log_sq_stride > 444 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 445 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 446 return -EINVAL; 447 448 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 449 qp->sq.wqe_shift = ucmd->log_sq_stride; 450 451 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 452 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 453 454 return 0; 455 } 456 457 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 458 { 459 int i; 460 461 qp->sqp_proxy_rcv = 462 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf), 463 GFP_KERNEL); 464 if (!qp->sqp_proxy_rcv) 465 return -ENOMEM; 466 for (i = 0; i < qp->rq.wqe_cnt; i++) { 467 qp->sqp_proxy_rcv[i].addr = 468 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 469 GFP_KERNEL); 470 if (!qp->sqp_proxy_rcv[i].addr) 471 goto err; 472 qp->sqp_proxy_rcv[i].map = 473 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 474 sizeof (struct mlx4_ib_proxy_sqp_hdr), 475 DMA_FROM_DEVICE); 476 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 477 kfree(qp->sqp_proxy_rcv[i].addr); 478 goto err; 479 } 480 } 481 return 0; 482 483 err: 484 while (i > 0) { 485 --i; 486 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 487 sizeof (struct mlx4_ib_proxy_sqp_hdr), 488 DMA_FROM_DEVICE); 489 kfree(qp->sqp_proxy_rcv[i].addr); 490 } 491 kfree(qp->sqp_proxy_rcv); 492 qp->sqp_proxy_rcv = NULL; 493 return -ENOMEM; 494 } 495 496 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 497 { 498 int i; 499 500 for (i = 0; i < qp->rq.wqe_cnt; i++) { 501 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 502 sizeof (struct mlx4_ib_proxy_sqp_hdr), 503 DMA_FROM_DEVICE); 504 kfree(qp->sqp_proxy_rcv[i].addr); 505 } 506 kfree(qp->sqp_proxy_rcv); 507 } 508 509 static int qp_has_rq(struct ib_qp_init_attr *attr) 510 { 511 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 512 return 0; 513 514 return !attr->srq; 515 } 516 517 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 518 { 519 int i; 520 for (i = 0; i < dev->caps.num_ports; i++) { 521 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 522 return !!dev->caps.spec_qps[i].qp0_qkey; 523 } 524 return 0; 525 } 526 527 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 528 struct mlx4_ib_qp *qp) 529 { 530 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 531 mlx4_counter_free(dev->dev, qp->counter_index->index); 532 list_del(&qp->counter_index->list); 533 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 534 535 kfree(qp->counter_index); 536 qp->counter_index = NULL; 537 } 538 539 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 540 struct ib_qp_init_attr *init_attr, 541 struct mlx4_ib_create_qp_rss *ucmd) 542 { 543 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 544 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 545 546 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 547 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 548 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 549 MLX4_EN_RSS_KEY_SIZE); 550 } else { 551 pr_debug("RX Hash function is not supported\n"); 552 return (-EOPNOTSUPP); 553 } 554 555 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | 556 MLX4_IB_RX_HASH_DST_IPV4 | 557 MLX4_IB_RX_HASH_SRC_IPV6 | 558 MLX4_IB_RX_HASH_DST_IPV6 | 559 MLX4_IB_RX_HASH_SRC_PORT_TCP | 560 MLX4_IB_RX_HASH_DST_PORT_TCP | 561 MLX4_IB_RX_HASH_SRC_PORT_UDP | 562 MLX4_IB_RX_HASH_DST_PORT_UDP | 563 MLX4_IB_RX_HASH_INNER)) { 564 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 565 ucmd->rx_hash_fields_mask); 566 return (-EOPNOTSUPP); 567 } 568 569 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 570 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 571 rss_ctx->flags = MLX4_RSS_IPV4; 572 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 573 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 574 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 575 return (-EOPNOTSUPP); 576 } 577 578 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 579 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 580 rss_ctx->flags |= MLX4_RSS_IPV6; 581 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 582 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 583 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 584 return (-EOPNOTSUPP); 585 } 586 587 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 588 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 589 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 590 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 591 return (-EOPNOTSUPP); 592 } 593 594 if (rss_ctx->flags & MLX4_RSS_IPV4) 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 596 if (rss_ctx->flags & MLX4_RSS_IPV6) 597 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 598 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 599 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 600 return (-EOPNOTSUPP); 601 } 602 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 603 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 604 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 605 return (-EOPNOTSUPP); 606 } 607 608 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 609 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 610 if (rss_ctx->flags & MLX4_RSS_IPV4) 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 612 if (rss_ctx->flags & MLX4_RSS_IPV6) 613 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 614 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 615 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 616 return (-EOPNOTSUPP); 617 } 618 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 619 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 620 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 621 return (-EOPNOTSUPP); 622 } 623 624 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 625 if (dev->dev->caps.tunnel_offload_mode == 626 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 627 /* 628 * Hash according to inner headers if exist, otherwise 629 * according to outer headers. 630 */ 631 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 632 } else { 633 pr_debug("RSS Hash for inner headers isn't supported\n"); 634 return (-EOPNOTSUPP); 635 } 636 } 637 638 return 0; 639 } 640 641 static int create_qp_rss(struct mlx4_ib_dev *dev, 642 struct ib_qp_init_attr *init_attr, 643 struct mlx4_ib_create_qp_rss *ucmd, 644 struct mlx4_ib_qp *qp) 645 { 646 int qpn; 647 int err; 648 649 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 650 651 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 652 if (err) 653 return err; 654 655 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 656 if (err) 657 goto err_qpn; 658 659 mutex_init(&qp->mutex); 660 661 INIT_LIST_HEAD(&qp->gid_list); 662 INIT_LIST_HEAD(&qp->steering_rules); 663 664 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 665 qp->state = IB_QPS_RESET; 666 667 /* Set dummy send resources to be compatible with HV and PRM */ 668 qp->sq_no_prefetch = 1; 669 qp->sq.wqe_cnt = 1; 670 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 671 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 672 qp->mtt = (to_mqp( 673 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 674 675 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 676 if (!qp->rss_ctx) { 677 err = -ENOMEM; 678 goto err_qp_alloc; 679 } 680 681 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 682 if (err) 683 goto err; 684 685 return 0; 686 687 err: 688 kfree(qp->rss_ctx); 689 690 err_qp_alloc: 691 mlx4_qp_remove(dev->dev, &qp->mqp); 692 mlx4_qp_free(dev->dev, &qp->mqp); 693 694 err_qpn: 695 mlx4_qp_release_range(dev->dev, qpn, 1); 696 return err; 697 } 698 699 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd, 700 struct ib_qp_init_attr *init_attr, 701 struct ib_udata *udata) 702 { 703 struct mlx4_ib_qp *qp; 704 struct mlx4_ib_create_qp_rss ucmd = {}; 705 size_t required_cmd_sz; 706 int err; 707 708 if (!udata) { 709 pr_debug("RSS QP with NULL udata\n"); 710 return ERR_PTR(-EINVAL); 711 } 712 713 if (udata->outlen) 714 return ERR_PTR(-EOPNOTSUPP); 715 716 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 717 sizeof(ucmd.reserved1); 718 if (udata->inlen < required_cmd_sz) { 719 pr_debug("invalid inlen\n"); 720 return ERR_PTR(-EINVAL); 721 } 722 723 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 724 pr_debug("copy failed\n"); 725 return ERR_PTR(-EFAULT); 726 } 727 728 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 729 return ERR_PTR(-EOPNOTSUPP); 730 731 if (ucmd.comp_mask || ucmd.reserved1) 732 return ERR_PTR(-EOPNOTSUPP); 733 734 if (udata->inlen > sizeof(ucmd) && 735 !ib_is_udata_cleared(udata, sizeof(ucmd), 736 udata->inlen - sizeof(ucmd))) { 737 pr_debug("inlen is not supported\n"); 738 return ERR_PTR(-EOPNOTSUPP); 739 } 740 741 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 742 pr_debug("RSS QP with unsupported QP type %d\n", 743 init_attr->qp_type); 744 return ERR_PTR(-EOPNOTSUPP); 745 } 746 747 if (init_attr->create_flags) { 748 pr_debug("RSS QP doesn't support create flags\n"); 749 return ERR_PTR(-EOPNOTSUPP); 750 } 751 752 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 753 pr_debug("RSS QP with unsupported send attributes\n"); 754 return ERR_PTR(-EOPNOTSUPP); 755 } 756 757 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 758 if (!qp) 759 return ERR_PTR(-ENOMEM); 760 761 qp->pri.vid = 0xFFFF; 762 qp->alt.vid = 0xFFFF; 763 764 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 765 if (err) { 766 kfree(qp); 767 return ERR_PTR(err); 768 } 769 770 qp->ibqp.qp_num = qp->mqp.qpn; 771 772 return &qp->ibqp; 773 } 774 775 /* 776 * This function allocates a WQN from a range which is consecutive and aligned 777 * to its size. In case the range is full, then it creates a new range and 778 * allocates WQN from it. The new range will be used for following allocations. 779 */ 780 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 781 struct mlx4_ib_qp *qp, int range_size, int *wqn) 782 { 783 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 784 struct mlx4_wqn_range *range; 785 int err = 0; 786 787 mutex_lock(&context->wqn_ranges_mutex); 788 789 range = list_first_entry_or_null(&context->wqn_ranges_list, 790 struct mlx4_wqn_range, list); 791 792 if (!range || (range->refcount == range->size) || range->dirty) { 793 range = kzalloc(sizeof(*range), GFP_KERNEL); 794 if (!range) { 795 err = -ENOMEM; 796 goto out; 797 } 798 799 err = mlx4_qp_reserve_range(dev->dev, range_size, 800 range_size, &range->base_wqn, 0, 801 qp->mqp.usage); 802 if (err) { 803 kfree(range); 804 goto out; 805 } 806 807 range->size = range_size; 808 list_add(&range->list, &context->wqn_ranges_list); 809 } else if (range_size != 1) { 810 /* 811 * Requesting a new range (>1) when last range is still open, is 812 * not valid. 813 */ 814 err = -EINVAL; 815 goto out; 816 } 817 818 qp->wqn_range = range; 819 820 *wqn = range->base_wqn + range->refcount; 821 822 range->refcount++; 823 824 out: 825 mutex_unlock(&context->wqn_ranges_mutex); 826 827 return err; 828 } 829 830 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 831 struct mlx4_ib_qp *qp, bool dirty_release) 832 { 833 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 834 struct mlx4_wqn_range *range; 835 836 mutex_lock(&context->wqn_ranges_mutex); 837 838 range = qp->wqn_range; 839 840 range->refcount--; 841 if (!range->refcount) { 842 mlx4_qp_release_range(dev->dev, range->base_wqn, 843 range->size); 844 list_del(&range->list); 845 kfree(range); 846 } else if (dirty_release) { 847 /* 848 * A range which one of its WQNs is destroyed, won't be able to be 849 * reused for further WQN allocations. 850 * The next created WQ will allocate a new range. 851 */ 852 range->dirty = 1; 853 } 854 855 mutex_unlock(&context->wqn_ranges_mutex); 856 } 857 858 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 859 enum mlx4_ib_source_type src, 860 struct ib_qp_init_attr *init_attr, 861 struct ib_udata *udata, int sqpn, 862 struct mlx4_ib_qp **caller_qp) 863 { 864 int qpn; 865 int err; 866 struct mlx4_ib_sqp *sqp = NULL; 867 struct mlx4_ib_qp *qp; 868 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 869 udata, struct mlx4_ib_ucontext, ibucontext); 870 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 871 struct mlx4_ib_cq *mcq; 872 unsigned long flags; 873 int range_size = 0; 874 875 /* When tunneling special qps, we use a plain UD qp */ 876 if (sqpn) { 877 if (mlx4_is_mfunc(dev->dev) && 878 (!mlx4_is_master(dev->dev) || 879 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 880 if (init_attr->qp_type == IB_QPT_GSI) 881 qp_type = MLX4_IB_QPT_PROXY_GSI; 882 else { 883 if (mlx4_is_master(dev->dev) || 884 qp0_enabled_vf(dev->dev, sqpn)) 885 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 886 else 887 qp_type = MLX4_IB_QPT_PROXY_SMI; 888 } 889 } 890 qpn = sqpn; 891 /* add extra sg entry for tunneling */ 892 init_attr->cap.max_recv_sge++; 893 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 894 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 895 container_of(init_attr, 896 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 897 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 898 tnl_init->proxy_qp_type != IB_QPT_GSI) || 899 !mlx4_is_master(dev->dev)) 900 return -EINVAL; 901 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 902 qp_type = MLX4_IB_QPT_TUN_GSI; 903 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 904 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 905 tnl_init->port)) 906 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 907 else 908 qp_type = MLX4_IB_QPT_TUN_SMI; 909 /* we are definitely in the PPF here, since we are creating 910 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 911 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 912 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 913 sqpn = qpn; 914 } 915 916 if (!*caller_qp) { 917 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 918 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 919 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 920 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 921 if (!sqp) 922 return -ENOMEM; 923 qp = &sqp->qp; 924 qp->pri.vid = 0xFFFF; 925 qp->alt.vid = 0xFFFF; 926 } else { 927 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL); 928 if (!qp) 929 return -ENOMEM; 930 qp->pri.vid = 0xFFFF; 931 qp->alt.vid = 0xFFFF; 932 } 933 } else 934 qp = *caller_qp; 935 936 qp->mlx4_ib_qp_type = qp_type; 937 938 mutex_init(&qp->mutex); 939 spin_lock_init(&qp->sq.lock); 940 spin_lock_init(&qp->rq.lock); 941 INIT_LIST_HEAD(&qp->gid_list); 942 INIT_LIST_HEAD(&qp->steering_rules); 943 944 qp->state = IB_QPS_RESET; 945 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 946 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 947 948 949 if (udata) { 950 union { 951 struct mlx4_ib_create_qp qp; 952 struct mlx4_ib_create_wq wq; 953 } ucmd; 954 size_t copy_len; 955 int shift; 956 int n; 957 958 copy_len = (src == MLX4_IB_QP_SRC) ? 959 sizeof(struct mlx4_ib_create_qp) : 960 min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 961 962 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 963 err = -EFAULT; 964 goto err; 965 } 966 967 if (src == MLX4_IB_RWQ_SRC) { 968 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] || 969 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) { 970 pr_debug("user command isn't supported\n"); 971 err = -EOPNOTSUPP; 972 goto err; 973 } 974 975 if (ucmd.wq.log_range_size > 976 ilog2(dev->dev->caps.max_rss_tbl_sz)) { 977 pr_debug("WQN range size must be equal or smaller than %d\n", 978 dev->dev->caps.max_rss_tbl_sz); 979 err = -EOPNOTSUPP; 980 goto err; 981 } 982 range_size = 1 << ucmd.wq.log_range_size; 983 } else { 984 qp->inl_recv_sz = ucmd.qp.inl_recv_sz; 985 } 986 987 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 988 if (!(dev->dev->caps.flags & 989 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 990 pr_debug("scatter FCS is unsupported\n"); 991 err = -EOPNOTSUPP; 992 goto err; 993 } 994 995 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 996 } 997 998 err = set_rq_size(dev, &init_attr->cap, udata, 999 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1000 if (err) 1001 goto err; 1002 1003 if (src == MLX4_IB_QP_SRC) { 1004 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch; 1005 1006 err = set_user_sq_size(dev, qp, 1007 (struct mlx4_ib_create_qp *) 1008 &ucmd); 1009 if (err) 1010 goto err; 1011 } else { 1012 qp->sq_no_prefetch = 1; 1013 qp->sq.wqe_cnt = 1; 1014 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 1015 /* Allocated buffer expects to have at least that SQ 1016 * size. 1017 */ 1018 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 1019 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 1020 } 1021 1022 qp->umem = 1023 ib_umem_get(udata, 1024 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr : 1025 ucmd.wq.buf_addr, 1026 qp->buf_size, 0, 0); 1027 if (IS_ERR(qp->umem)) { 1028 err = PTR_ERR(qp->umem); 1029 goto err; 1030 } 1031 1032 n = ib_umem_page_count(qp->umem); 1033 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1034 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1035 1036 if (err) 1037 goto err_buf; 1038 1039 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1040 if (err) 1041 goto err_mtt; 1042 1043 if (qp_has_rq(init_attr)) { 1044 err = mlx4_ib_db_map_user(udata, 1045 (src == MLX4_IB_QP_SRC) ? 1046 ucmd.qp.db_addr : 1047 ucmd.wq.db_addr, 1048 &qp->db); 1049 if (err) 1050 goto err_mtt; 1051 } 1052 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1053 } else { 1054 err = set_rq_size(dev, &init_attr->cap, udata, 1055 qp_has_rq(init_attr), qp, 0); 1056 if (err) 1057 goto err; 1058 1059 qp->sq_no_prefetch = 0; 1060 1061 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1062 qp->flags |= MLX4_IB_QP_LSO; 1063 1064 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1065 if (dev->steering_support == 1066 MLX4_STEERING_MODE_DEVICE_MANAGED) 1067 qp->flags |= MLX4_IB_QP_NETIF; 1068 else 1069 goto err; 1070 } 1071 1072 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1073 if (err) 1074 goto err; 1075 1076 if (qp_has_rq(init_attr)) { 1077 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1078 if (err) 1079 goto err; 1080 1081 *qp->db.db = 0; 1082 } 1083 1084 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1085 &qp->buf)) { 1086 err = -ENOMEM; 1087 goto err_db; 1088 } 1089 1090 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1091 &qp->mtt); 1092 if (err) 1093 goto err_buf; 1094 1095 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1096 if (err) 1097 goto err_mtt; 1098 1099 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1100 sizeof(u64), GFP_KERNEL); 1101 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1102 sizeof(u64), GFP_KERNEL); 1103 if (!qp->sq.wrid || !qp->rq.wrid) { 1104 err = -ENOMEM; 1105 goto err_wrid; 1106 } 1107 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1108 } 1109 1110 if (sqpn) { 1111 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1112 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1113 if (alloc_proxy_bufs(pd->device, qp)) { 1114 err = -ENOMEM; 1115 goto err_wrid; 1116 } 1117 } 1118 } else if (src == MLX4_IB_RWQ_SRC) { 1119 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn); 1120 if (err) 1121 goto err_wrid; 1122 } else { 1123 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1124 * otherwise, the WQE BlueFlame setup flow wrongly causes 1125 * VLAN insertion. */ 1126 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1127 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1128 (init_attr->cap.max_send_wr ? 1129 MLX4_RESERVE_ETH_BF_QP : 0) | 1130 (init_attr->cap.max_recv_wr ? 1131 MLX4_RESERVE_A0_QP : 0), 1132 qp->mqp.usage); 1133 else 1134 if (qp->flags & MLX4_IB_QP_NETIF) 1135 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1136 else 1137 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1138 &qpn, 0, qp->mqp.usage); 1139 if (err) 1140 goto err_proxy; 1141 } 1142 1143 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1144 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1145 1146 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1147 if (err) 1148 goto err_qpn; 1149 1150 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1151 qp->mqp.qpn |= (1 << 23); 1152 1153 /* 1154 * Hardware wants QPN written in big-endian order (after 1155 * shifting) for send doorbell. Precompute this value to save 1156 * a little bit when posting sends. 1157 */ 1158 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1159 1160 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event : 1161 mlx4_ib_wq_event; 1162 1163 if (!*caller_qp) 1164 *caller_qp = qp; 1165 1166 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1167 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1168 to_mcq(init_attr->recv_cq)); 1169 /* Maintain device to QPs access, needed for further handling 1170 * via reset flow 1171 */ 1172 list_add_tail(&qp->qps_list, &dev->qp_list); 1173 /* Maintain CQ to QPs access, needed for further handling 1174 * via reset flow 1175 */ 1176 mcq = to_mcq(init_attr->send_cq); 1177 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1178 mcq = to_mcq(init_attr->recv_cq); 1179 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1180 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1181 to_mcq(init_attr->recv_cq)); 1182 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1183 return 0; 1184 1185 err_qpn: 1186 if (!sqpn) { 1187 if (qp->flags & MLX4_IB_QP_NETIF) 1188 mlx4_ib_steer_qp_free(dev, qpn, 1); 1189 else if (src == MLX4_IB_RWQ_SRC) 1190 mlx4_ib_release_wqn(context, qp, 0); 1191 else 1192 mlx4_qp_release_range(dev->dev, qpn, 1); 1193 } 1194 err_proxy: 1195 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1196 free_proxy_bufs(pd->device, qp); 1197 err_wrid: 1198 if (udata) { 1199 if (qp_has_rq(init_attr)) 1200 mlx4_ib_db_unmap_user(context, &qp->db); 1201 } else { 1202 kvfree(qp->sq.wrid); 1203 kvfree(qp->rq.wrid); 1204 } 1205 1206 err_mtt: 1207 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1208 1209 err_buf: 1210 if (qp->umem) 1211 ib_umem_release(qp->umem); 1212 else 1213 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1214 1215 err_db: 1216 if (!udata && qp_has_rq(init_attr)) 1217 mlx4_db_free(dev->dev, &qp->db); 1218 1219 err: 1220 if (!sqp && !*caller_qp) 1221 kfree(qp); 1222 kfree(sqp); 1223 1224 return err; 1225 } 1226 1227 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1228 { 1229 switch (state) { 1230 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1231 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1232 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1233 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1234 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1235 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1236 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1237 default: return -1; 1238 } 1239 } 1240 1241 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1242 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1243 { 1244 if (send_cq == recv_cq) { 1245 spin_lock(&send_cq->lock); 1246 __acquire(&recv_cq->lock); 1247 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1248 spin_lock(&send_cq->lock); 1249 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1250 } else { 1251 spin_lock(&recv_cq->lock); 1252 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1253 } 1254 } 1255 1256 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1257 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1258 { 1259 if (send_cq == recv_cq) { 1260 __release(&recv_cq->lock); 1261 spin_unlock(&send_cq->lock); 1262 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1263 spin_unlock(&recv_cq->lock); 1264 spin_unlock(&send_cq->lock); 1265 } else { 1266 spin_unlock(&send_cq->lock); 1267 spin_unlock(&recv_cq->lock); 1268 } 1269 } 1270 1271 static void del_gid_entries(struct mlx4_ib_qp *qp) 1272 { 1273 struct mlx4_ib_gid_entry *ge, *tmp; 1274 1275 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1276 list_del(&ge->list); 1277 kfree(ge); 1278 } 1279 } 1280 1281 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1282 { 1283 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1284 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1285 else 1286 return to_mpd(qp->ibqp.pd); 1287 } 1288 1289 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1290 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1291 { 1292 switch (qp->ibqp.qp_type) { 1293 case IB_QPT_XRC_TGT: 1294 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1295 *recv_cq = *send_cq; 1296 break; 1297 case IB_QPT_XRC_INI: 1298 *send_cq = to_mcq(qp->ibqp.send_cq); 1299 *recv_cq = *send_cq; 1300 break; 1301 default: 1302 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1303 to_mcq(qp->ibwq.cq); 1304 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1305 *recv_cq; 1306 break; 1307 } 1308 } 1309 1310 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1311 { 1312 if (qp->state != IB_QPS_RESET) { 1313 int i; 1314 1315 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1316 i++) { 1317 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1318 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1319 1320 mutex_lock(&wq->mutex); 1321 1322 wq->rss_usecnt--; 1323 1324 mutex_unlock(&wq->mutex); 1325 } 1326 1327 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1328 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1329 pr_warn("modify QP %06x to RESET failed.\n", 1330 qp->mqp.qpn); 1331 } 1332 1333 mlx4_qp_remove(dev->dev, &qp->mqp); 1334 mlx4_qp_free(dev->dev, &qp->mqp); 1335 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1336 del_gid_entries(qp); 1337 kfree(qp->rss_ctx); 1338 } 1339 1340 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1341 enum mlx4_ib_source_type src, 1342 struct ib_udata *udata) 1343 { 1344 struct mlx4_ib_cq *send_cq, *recv_cq; 1345 unsigned long flags; 1346 1347 if (qp->state != IB_QPS_RESET) { 1348 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1349 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1350 pr_warn("modify QP %06x to RESET failed.\n", 1351 qp->mqp.qpn); 1352 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1353 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1354 qp->pri.smac = 0; 1355 qp->pri.smac_port = 0; 1356 } 1357 if (qp->alt.smac) { 1358 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1359 qp->alt.smac = 0; 1360 } 1361 if (qp->pri.vid < 0x1000) { 1362 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1363 qp->pri.vid = 0xFFFF; 1364 qp->pri.candidate_vid = 0xFFFF; 1365 qp->pri.update_vid = 0; 1366 } 1367 if (qp->alt.vid < 0x1000) { 1368 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1369 qp->alt.vid = 0xFFFF; 1370 qp->alt.candidate_vid = 0xFFFF; 1371 qp->alt.update_vid = 0; 1372 } 1373 } 1374 1375 get_cqs(qp, src, &send_cq, &recv_cq); 1376 1377 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1378 mlx4_ib_lock_cqs(send_cq, recv_cq); 1379 1380 /* del from lists under both locks above to protect reset flow paths */ 1381 list_del(&qp->qps_list); 1382 list_del(&qp->cq_send_list); 1383 list_del(&qp->cq_recv_list); 1384 if (!udata) { 1385 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1386 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1387 if (send_cq != recv_cq) 1388 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1389 } 1390 1391 mlx4_qp_remove(dev->dev, &qp->mqp); 1392 1393 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1394 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1395 1396 mlx4_qp_free(dev->dev, &qp->mqp); 1397 1398 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1399 if (qp->flags & MLX4_IB_QP_NETIF) 1400 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1401 else if (src == MLX4_IB_RWQ_SRC) 1402 mlx4_ib_release_wqn( 1403 rdma_udata_to_drv_context( 1404 udata, 1405 struct mlx4_ib_ucontext, 1406 ibucontext), 1407 qp, 1); 1408 else 1409 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1410 } 1411 1412 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1413 1414 if (udata) { 1415 if (qp->rq.wqe_cnt) { 1416 struct mlx4_ib_ucontext *mcontext = 1417 rdma_udata_to_drv_context( 1418 udata, 1419 struct mlx4_ib_ucontext, 1420 ibucontext); 1421 1422 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1423 } 1424 ib_umem_release(qp->umem); 1425 } else { 1426 kvfree(qp->sq.wrid); 1427 kvfree(qp->rq.wrid); 1428 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1429 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1430 free_proxy_bufs(&dev->ib_dev, qp); 1431 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1432 if (qp->rq.wqe_cnt) 1433 mlx4_db_free(dev->dev, &qp->db); 1434 } 1435 1436 del_gid_entries(qp); 1437 } 1438 1439 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1440 { 1441 /* Native or PPF */ 1442 if (!mlx4_is_mfunc(dev->dev) || 1443 (mlx4_is_master(dev->dev) && 1444 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1445 return dev->dev->phys_caps.base_sqpn + 1446 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1447 attr->port_num - 1; 1448 } 1449 /* PF or VF -- creating proxies */ 1450 if (attr->qp_type == IB_QPT_SMI) 1451 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1452 else 1453 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1454 } 1455 1456 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1457 struct ib_qp_init_attr *init_attr, 1458 struct ib_udata *udata) 1459 { 1460 struct mlx4_ib_qp *qp = NULL; 1461 int err; 1462 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1463 u16 xrcdn = 0; 1464 1465 if (init_attr->rwq_ind_tbl) 1466 return _mlx4_ib_create_qp_rss(pd, init_attr, udata); 1467 1468 /* 1469 * We only support LSO, vendor flag1, and multicast loopback blocking, 1470 * and only for kernel UD QPs. 1471 */ 1472 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1473 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1474 MLX4_IB_SRIOV_TUNNEL_QP | 1475 MLX4_IB_SRIOV_SQP | 1476 MLX4_IB_QP_NETIF | 1477 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1478 return ERR_PTR(-EINVAL); 1479 1480 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1481 if (init_attr->qp_type != IB_QPT_UD) 1482 return ERR_PTR(-EINVAL); 1483 } 1484 1485 if (init_attr->create_flags) { 1486 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1487 return ERR_PTR(-EINVAL); 1488 1489 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1490 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1491 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1492 init_attr->qp_type != IB_QPT_UD) || 1493 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1494 init_attr->qp_type > IB_QPT_GSI) || 1495 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1496 init_attr->qp_type != IB_QPT_GSI)) 1497 return ERR_PTR(-EINVAL); 1498 } 1499 1500 switch (init_attr->qp_type) { 1501 case IB_QPT_XRC_TGT: 1502 pd = to_mxrcd(init_attr->xrcd)->pd; 1503 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1504 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1505 /* fall through */ 1506 case IB_QPT_XRC_INI: 1507 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1508 return ERR_PTR(-ENOSYS); 1509 init_attr->recv_cq = init_attr->send_cq; 1510 /* fall through */ 1511 case IB_QPT_RC: 1512 case IB_QPT_UC: 1513 case IB_QPT_RAW_PACKET: 1514 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1515 if (!qp) 1516 return ERR_PTR(-ENOMEM); 1517 qp->pri.vid = 0xFFFF; 1518 qp->alt.vid = 0xFFFF; 1519 /* fall through */ 1520 case IB_QPT_UD: 1521 { 1522 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1523 init_attr, udata, 0, &qp); 1524 if (err) { 1525 kfree(qp); 1526 return ERR_PTR(err); 1527 } 1528 1529 qp->ibqp.qp_num = qp->mqp.qpn; 1530 qp->xrcdn = xrcdn; 1531 1532 break; 1533 } 1534 case IB_QPT_SMI: 1535 case IB_QPT_GSI: 1536 { 1537 int sqpn; 1538 1539 /* Userspace is not allowed to create special QPs: */ 1540 if (udata) 1541 return ERR_PTR(-EINVAL); 1542 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1543 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1544 1, 1, &sqpn, 0, 1545 MLX4_RES_USAGE_DRIVER); 1546 1547 if (res) 1548 return ERR_PTR(res); 1549 } else { 1550 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1551 } 1552 1553 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1554 init_attr, udata, sqpn, &qp); 1555 if (err) 1556 return ERR_PTR(err); 1557 1558 qp->port = init_attr->port_num; 1559 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1560 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1561 break; 1562 } 1563 default: 1564 /* Don't support raw QPs */ 1565 return ERR_PTR(-EINVAL); 1566 } 1567 1568 return &qp->ibqp; 1569 } 1570 1571 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1572 struct ib_qp_init_attr *init_attr, 1573 struct ib_udata *udata) { 1574 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1575 struct ib_qp *ibqp; 1576 struct mlx4_ib_dev *dev = to_mdev(device); 1577 1578 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1579 1580 if (!IS_ERR(ibqp) && 1581 (init_attr->qp_type == IB_QPT_GSI) && 1582 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1583 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1584 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1585 1586 if (is_eth && 1587 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1588 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1589 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1590 1591 if (IS_ERR(sqp->roce_v2_gsi)) { 1592 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1593 sqp->roce_v2_gsi = NULL; 1594 } else { 1595 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1596 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1597 } 1598 1599 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1600 } 1601 } 1602 return ibqp; 1603 } 1604 1605 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1606 { 1607 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1608 struct mlx4_ib_qp *mqp = to_mqp(qp); 1609 1610 if (is_qp0(dev, mqp)) 1611 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1612 1613 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1614 dev->qp1_proxy[mqp->port - 1] == mqp) { 1615 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1616 dev->qp1_proxy[mqp->port - 1] = NULL; 1617 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1618 } 1619 1620 if (mqp->counter_index) 1621 mlx4_ib_free_qp_counter(dev, mqp); 1622 1623 if (qp->rwq_ind_tbl) { 1624 destroy_qp_rss(dev, mqp); 1625 } else { 1626 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata); 1627 } 1628 1629 if (is_sqp(dev, mqp)) 1630 kfree(to_msqp(mqp)); 1631 else 1632 kfree(mqp); 1633 1634 return 0; 1635 } 1636 1637 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1638 { 1639 struct mlx4_ib_qp *mqp = to_mqp(qp); 1640 1641 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1642 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1643 1644 if (sqp->roce_v2_gsi) 1645 ib_destroy_qp(sqp->roce_v2_gsi); 1646 } 1647 1648 return _mlx4_ib_destroy_qp(qp, udata); 1649 } 1650 1651 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1652 { 1653 switch (type) { 1654 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1655 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1656 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1657 case MLX4_IB_QPT_XRC_INI: 1658 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1659 case MLX4_IB_QPT_SMI: 1660 case MLX4_IB_QPT_GSI: 1661 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1662 1663 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1664 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1665 MLX4_QP_ST_MLX : -1); 1666 case MLX4_IB_QPT_PROXY_SMI: 1667 case MLX4_IB_QPT_TUN_SMI: 1668 case MLX4_IB_QPT_PROXY_GSI: 1669 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1670 MLX4_QP_ST_UD : -1); 1671 default: return -1; 1672 } 1673 } 1674 1675 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1676 int attr_mask) 1677 { 1678 u8 dest_rd_atomic; 1679 u32 access_flags; 1680 u32 hw_access_flags = 0; 1681 1682 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1683 dest_rd_atomic = attr->max_dest_rd_atomic; 1684 else 1685 dest_rd_atomic = qp->resp_depth; 1686 1687 if (attr_mask & IB_QP_ACCESS_FLAGS) 1688 access_flags = attr->qp_access_flags; 1689 else 1690 access_flags = qp->atomic_rd_en; 1691 1692 if (!dest_rd_atomic) 1693 access_flags &= IB_ACCESS_REMOTE_WRITE; 1694 1695 if (access_flags & IB_ACCESS_REMOTE_READ) 1696 hw_access_flags |= MLX4_QP_BIT_RRE; 1697 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1698 hw_access_flags |= MLX4_QP_BIT_RAE; 1699 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1700 hw_access_flags |= MLX4_QP_BIT_RWE; 1701 1702 return cpu_to_be32(hw_access_flags); 1703 } 1704 1705 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1706 int attr_mask) 1707 { 1708 if (attr_mask & IB_QP_PKEY_INDEX) 1709 sqp->pkey_index = attr->pkey_index; 1710 if (attr_mask & IB_QP_QKEY) 1711 sqp->qkey = attr->qkey; 1712 if (attr_mask & IB_QP_SQ_PSN) 1713 sqp->send_psn = attr->sq_psn; 1714 } 1715 1716 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1717 { 1718 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1719 } 1720 1721 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1722 const struct rdma_ah_attr *ah, 1723 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1724 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1725 { 1726 int vidx; 1727 int smac_index; 1728 int err; 1729 1730 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1731 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1732 if (rdma_ah_get_static_rate(ah)) { 1733 path->static_rate = rdma_ah_get_static_rate(ah) + 1734 MLX4_STAT_RATE_OFFSET; 1735 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1736 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1737 --path->static_rate; 1738 } else 1739 path->static_rate = 0; 1740 1741 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1742 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1743 int real_sgid_index = 1744 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1745 1746 if (real_sgid_index < 0) 1747 return real_sgid_index; 1748 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1749 pr_err("sgid_index (%u) too large. max is %d\n", 1750 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1751 return -1; 1752 } 1753 1754 path->grh_mylmc |= 1 << 7; 1755 path->mgid_index = real_sgid_index; 1756 path->hop_limit = grh->hop_limit; 1757 path->tclass_flowlabel = 1758 cpu_to_be32((grh->traffic_class << 20) | 1759 (grh->flow_label)); 1760 memcpy(path->rgid, grh->dgid.raw, 16); 1761 } 1762 1763 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1764 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1765 return -1; 1766 1767 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1768 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1769 1770 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1771 if (vlan_tag < 0x1000) { 1772 if (smac_info->vid < 0x1000) { 1773 /* both valid vlan ids */ 1774 if (smac_info->vid != vlan_tag) { 1775 /* different VIDs. unreg old and reg new */ 1776 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1777 if (err) 1778 return err; 1779 smac_info->candidate_vid = vlan_tag; 1780 smac_info->candidate_vlan_index = vidx; 1781 smac_info->candidate_vlan_port = port; 1782 smac_info->update_vid = 1; 1783 path->vlan_index = vidx; 1784 } else { 1785 path->vlan_index = smac_info->vlan_index; 1786 } 1787 } else { 1788 /* no current vlan tag in qp */ 1789 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1790 if (err) 1791 return err; 1792 smac_info->candidate_vid = vlan_tag; 1793 smac_info->candidate_vlan_index = vidx; 1794 smac_info->candidate_vlan_port = port; 1795 smac_info->update_vid = 1; 1796 path->vlan_index = vidx; 1797 } 1798 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1799 path->fl = 1 << 6; 1800 } else { 1801 /* have current vlan tag. unregister it at modify-qp success */ 1802 if (smac_info->vid < 0x1000) { 1803 smac_info->candidate_vid = 0xFFFF; 1804 smac_info->update_vid = 1; 1805 } 1806 } 1807 1808 /* get smac_index for RoCE use. 1809 * If no smac was yet assigned, register one. 1810 * If one was already assigned, but the new mac differs, 1811 * unregister the old one and register the new one. 1812 */ 1813 if ((!smac_info->smac && !smac_info->smac_port) || 1814 smac_info->smac != smac) { 1815 /* register candidate now, unreg if needed, after success */ 1816 smac_index = mlx4_register_mac(dev->dev, port, smac); 1817 if (smac_index >= 0) { 1818 smac_info->candidate_smac_index = smac_index; 1819 smac_info->candidate_smac = smac; 1820 smac_info->candidate_smac_port = port; 1821 } else { 1822 return -EINVAL; 1823 } 1824 } else { 1825 smac_index = smac_info->smac_index; 1826 } 1827 memcpy(path->dmac, ah->roce.dmac, 6); 1828 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1829 /* put MAC table smac index for IBoE */ 1830 path->grh_mylmc = (u8) (smac_index) | 0x80; 1831 } else { 1832 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1833 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1834 } 1835 1836 return 0; 1837 } 1838 1839 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1840 enum ib_qp_attr_mask qp_attr_mask, 1841 struct mlx4_ib_qp *mqp, 1842 struct mlx4_qp_path *path, u8 port, 1843 u16 vlan_id, u8 *smac) 1844 { 1845 return _mlx4_set_path(dev, &qp->ah_attr, 1846 mlx4_mac_to_u64(smac), 1847 vlan_id, 1848 path, &mqp->pri, port); 1849 } 1850 1851 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1852 const struct ib_qp_attr *qp, 1853 enum ib_qp_attr_mask qp_attr_mask, 1854 struct mlx4_ib_qp *mqp, 1855 struct mlx4_qp_path *path, u8 port) 1856 { 1857 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1858 0, 1859 0xffff, 1860 path, &mqp->alt, port); 1861 } 1862 1863 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1864 { 1865 struct mlx4_ib_gid_entry *ge, *tmp; 1866 1867 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1868 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1869 ge->added = 1; 1870 ge->port = qp->port; 1871 } 1872 } 1873 } 1874 1875 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1876 struct mlx4_ib_qp *qp, 1877 struct mlx4_qp_context *context) 1878 { 1879 u64 u64_mac; 1880 int smac_index; 1881 1882 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1883 1884 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1885 if (!qp->pri.smac && !qp->pri.smac_port) { 1886 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1887 if (smac_index >= 0) { 1888 qp->pri.candidate_smac_index = smac_index; 1889 qp->pri.candidate_smac = u64_mac; 1890 qp->pri.candidate_smac_port = qp->port; 1891 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1892 } else { 1893 return -ENOENT; 1894 } 1895 } 1896 return 0; 1897 } 1898 1899 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1900 { 1901 struct counter_index *new_counter_index; 1902 int err; 1903 u32 tmp_idx; 1904 1905 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1906 IB_LINK_LAYER_ETHERNET || 1907 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1908 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1909 return 0; 1910 1911 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1912 if (err) 1913 return err; 1914 1915 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1916 if (!new_counter_index) { 1917 mlx4_counter_free(dev->dev, tmp_idx); 1918 return -ENOMEM; 1919 } 1920 1921 new_counter_index->index = tmp_idx; 1922 new_counter_index->allocated = 1; 1923 qp->counter_index = new_counter_index; 1924 1925 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1926 list_add_tail(&new_counter_index->list, 1927 &dev->counters_table[qp->port - 1].counters_list); 1928 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1929 1930 return 0; 1931 } 1932 1933 enum { 1934 MLX4_QPC_ROCE_MODE_1 = 0, 1935 MLX4_QPC_ROCE_MODE_2 = 2, 1936 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1937 }; 1938 1939 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1940 { 1941 switch (gid_type) { 1942 case IB_GID_TYPE_ROCE: 1943 return MLX4_QPC_ROCE_MODE_1; 1944 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1945 return MLX4_QPC_ROCE_MODE_2; 1946 default: 1947 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1948 } 1949 } 1950 1951 /* 1952 * Go over all RSS QP's childes (WQs) and apply their HW state according to 1953 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 1954 */ 1955 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num, 1956 struct ib_udata *udata) 1957 { 1958 int err = 0; 1959 int i; 1960 1961 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 1962 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 1963 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1964 1965 mutex_lock(&wq->mutex); 1966 1967 /* Mlx4_ib restrictions: 1968 * WQ's is associated to a port according to the RSS QP it is 1969 * associates to. 1970 * In case the WQ is associated to a different port by another 1971 * RSS QP, return a failure. 1972 */ 1973 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 1974 err = -EINVAL; 1975 mutex_unlock(&wq->mutex); 1976 break; 1977 } 1978 wq->port = port_num; 1979 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 1980 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata); 1981 if (err) { 1982 mutex_unlock(&wq->mutex); 1983 break; 1984 } 1985 } 1986 wq->rss_usecnt++; 1987 1988 mutex_unlock(&wq->mutex); 1989 } 1990 1991 if (i && err) { 1992 int j; 1993 1994 for (j = (i - 1); j >= 0; j--) { 1995 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 1996 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1997 1998 mutex_lock(&wq->mutex); 1999 2000 if ((wq->rss_usecnt == 1) && 2001 (ibwq->state == IB_WQS_RDY)) 2002 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, 2003 udata)) 2004 pr_warn("failed to reverse WQN=0x%06x\n", 2005 ibwq->wq_num); 2006 wq->rss_usecnt--; 2007 2008 mutex_unlock(&wq->mutex); 2009 } 2010 } 2011 2012 return err; 2013 } 2014 2015 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, 2016 struct ib_udata *udata) 2017 { 2018 int i; 2019 2020 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2021 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2022 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2023 2024 mutex_lock(&wq->mutex); 2025 2026 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2027 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata)) 2028 pr_warn("failed to reverse WQN=%x\n", 2029 ibwq->wq_num); 2030 wq->rss_usecnt--; 2031 2032 mutex_unlock(&wq->mutex); 2033 } 2034 } 2035 2036 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2037 struct mlx4_ib_qp *qp) 2038 { 2039 struct mlx4_rss_context *rss_context; 2040 2041 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2042 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2043 2044 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2045 rss_context->default_qpn = 2046 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2047 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2048 rss_context->base_qpn_udp = rss_context->default_qpn; 2049 rss_context->flags = qp->rss_ctx->flags; 2050 /* Currently support just toeplitz */ 2051 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2052 2053 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2054 MLX4_EN_RSS_KEY_SIZE); 2055 } 2056 2057 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2058 const struct ib_qp_attr *attr, int attr_mask, 2059 enum ib_qp_state cur_state, 2060 enum ib_qp_state new_state, 2061 struct ib_udata *udata) 2062 { 2063 struct ib_srq *ibsrq; 2064 const struct ib_gid_attr *gid_attr = NULL; 2065 struct ib_rwq_ind_table *rwq_ind_tbl; 2066 enum ib_qp_type qp_type; 2067 struct mlx4_ib_dev *dev; 2068 struct mlx4_ib_qp *qp; 2069 struct mlx4_ib_pd *pd; 2070 struct mlx4_ib_cq *send_cq, *recv_cq; 2071 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2072 udata, struct mlx4_ib_ucontext, ibucontext); 2073 struct mlx4_qp_context *context; 2074 enum mlx4_qp_optpar optpar = 0; 2075 int sqd_event; 2076 int steer_qp = 0; 2077 int err = -EINVAL; 2078 int counter_index; 2079 2080 if (src_type == MLX4_IB_RWQ_SRC) { 2081 struct ib_wq *ibwq; 2082 2083 ibwq = (struct ib_wq *)src; 2084 ibsrq = NULL; 2085 rwq_ind_tbl = NULL; 2086 qp_type = IB_QPT_RAW_PACKET; 2087 qp = to_mqp((struct ib_qp *)ibwq); 2088 dev = to_mdev(ibwq->device); 2089 pd = to_mpd(ibwq->pd); 2090 } else { 2091 struct ib_qp *ibqp; 2092 2093 ibqp = (struct ib_qp *)src; 2094 ibsrq = ibqp->srq; 2095 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2096 qp_type = ibqp->qp_type; 2097 qp = to_mqp(ibqp); 2098 dev = to_mdev(ibqp->device); 2099 pd = get_pd(qp); 2100 } 2101 2102 /* APM is not supported under RoCE */ 2103 if (attr_mask & IB_QP_ALT_PATH && 2104 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2105 IB_LINK_LAYER_ETHERNET) 2106 return -ENOTSUPP; 2107 2108 context = kzalloc(sizeof *context, GFP_KERNEL); 2109 if (!context) 2110 return -ENOMEM; 2111 2112 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2113 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2114 2115 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2116 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2117 else { 2118 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2119 switch (attr->path_mig_state) { 2120 case IB_MIG_MIGRATED: 2121 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2122 break; 2123 case IB_MIG_REARM: 2124 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2125 break; 2126 case IB_MIG_ARMED: 2127 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2128 break; 2129 } 2130 } 2131 2132 if (qp->inl_recv_sz) 2133 context->param3 |= cpu_to_be32(1 << 25); 2134 2135 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2136 context->param3 |= cpu_to_be32(1 << 29); 2137 2138 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2139 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2140 else if (qp_type == IB_QPT_RAW_PACKET) 2141 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2142 else if (qp_type == IB_QPT_UD) { 2143 if (qp->flags & MLX4_IB_QP_LSO) 2144 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2145 ilog2(dev->dev->caps.max_gso_sz); 2146 else 2147 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2148 } else if (attr_mask & IB_QP_PATH_MTU) { 2149 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2150 pr_err("path MTU (%u) is invalid\n", 2151 attr->path_mtu); 2152 goto out; 2153 } 2154 context->mtu_msgmax = (attr->path_mtu << 5) | 2155 ilog2(dev->dev->caps.max_msg_sz); 2156 } 2157 2158 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2159 if (qp->rq.wqe_cnt) 2160 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2161 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2162 } 2163 2164 if (qp->sq.wqe_cnt) 2165 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2166 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2167 2168 if (new_state == IB_QPS_RESET && qp->counter_index) 2169 mlx4_ib_free_qp_counter(dev, qp); 2170 2171 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2172 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2173 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2174 if (qp_type == IB_QPT_RAW_PACKET) 2175 context->param3 |= cpu_to_be32(1 << 30); 2176 } 2177 2178 if (ucontext) 2179 context->usr_page = cpu_to_be32( 2180 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 2181 else 2182 context->usr_page = cpu_to_be32( 2183 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2184 2185 if (attr_mask & IB_QP_DEST_QPN) 2186 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2187 2188 if (attr_mask & IB_QP_PORT) { 2189 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2190 !(attr_mask & IB_QP_AV)) { 2191 mlx4_set_sched(&context->pri_path, attr->port_num); 2192 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2193 } 2194 } 2195 2196 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2197 err = create_qp_lb_counter(dev, qp); 2198 if (err) 2199 goto out; 2200 2201 counter_index = 2202 dev->counters_table[qp->port - 1].default_counter; 2203 if (qp->counter_index) 2204 counter_index = qp->counter_index->index; 2205 2206 if (counter_index != -1) { 2207 context->pri_path.counter_index = counter_index; 2208 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2209 if (qp->counter_index) { 2210 context->pri_path.fl |= 2211 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2212 context->pri_path.vlan_control |= 2213 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2214 } 2215 } else 2216 context->pri_path.counter_index = 2217 MLX4_SINK_COUNTER_INDEX(dev->dev); 2218 2219 if (qp->flags & MLX4_IB_QP_NETIF) { 2220 mlx4_ib_steer_qp_reg(dev, qp, 1); 2221 steer_qp = 1; 2222 } 2223 2224 if (qp_type == IB_QPT_GSI) { 2225 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2226 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2227 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2228 2229 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2230 } 2231 } 2232 2233 if (attr_mask & IB_QP_PKEY_INDEX) { 2234 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2235 context->pri_path.disable_pkey_check = 0x40; 2236 context->pri_path.pkey_index = attr->pkey_index; 2237 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2238 } 2239 2240 if (attr_mask & IB_QP_AV) { 2241 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2242 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2243 u16 vlan = 0xffff; 2244 u8 smac[ETH_ALEN]; 2245 int is_eth = 2246 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2247 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2248 2249 if (is_eth) { 2250 gid_attr = attr->ah_attr.grh.sgid_attr; 2251 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 2252 &smac[0]); 2253 if (err) 2254 goto out; 2255 } 2256 2257 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2258 port_num, vlan, smac)) 2259 goto out; 2260 2261 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2262 MLX4_QP_OPTPAR_SCHED_QUEUE); 2263 2264 if (is_eth && 2265 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2266 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2267 2268 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2269 err = -EINVAL; 2270 goto out; 2271 } 2272 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2273 } 2274 2275 } 2276 2277 if (attr_mask & IB_QP_TIMEOUT) { 2278 context->pri_path.ackto |= attr->timeout << 3; 2279 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2280 } 2281 2282 if (attr_mask & IB_QP_ALT_PATH) { 2283 if (attr->alt_port_num == 0 || 2284 attr->alt_port_num > dev->dev->caps.num_ports) 2285 goto out; 2286 2287 if (attr->alt_pkey_index >= 2288 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2289 goto out; 2290 2291 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2292 &context->alt_path, 2293 attr->alt_port_num)) 2294 goto out; 2295 2296 context->alt_path.pkey_index = attr->alt_pkey_index; 2297 context->alt_path.ackto = attr->alt_timeout << 3; 2298 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2299 } 2300 2301 context->pd = cpu_to_be32(pd->pdn); 2302 2303 if (!rwq_ind_tbl) { 2304 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2305 get_cqs(qp, src_type, &send_cq, &recv_cq); 2306 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2307 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2308 recv_cq = send_cq; 2309 } 2310 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2311 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2312 2313 /* Set "fast registration enabled" for all kernel QPs */ 2314 if (!ucontext) 2315 context->params1 |= cpu_to_be32(1 << 11); 2316 2317 if (attr_mask & IB_QP_RNR_RETRY) { 2318 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2319 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2320 } 2321 2322 if (attr_mask & IB_QP_RETRY_CNT) { 2323 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2324 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2325 } 2326 2327 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2328 if (attr->max_rd_atomic) 2329 context->params1 |= 2330 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2331 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2332 } 2333 2334 if (attr_mask & IB_QP_SQ_PSN) 2335 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2336 2337 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2338 if (attr->max_dest_rd_atomic) 2339 context->params2 |= 2340 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2341 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2342 } 2343 2344 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2345 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2346 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2347 } 2348 2349 if (ibsrq) 2350 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2351 2352 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2353 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2354 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2355 } 2356 if (attr_mask & IB_QP_RQ_PSN) 2357 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2358 2359 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2360 if (attr_mask & IB_QP_QKEY) { 2361 if (qp->mlx4_ib_qp_type & 2362 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2363 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2364 else { 2365 if (mlx4_is_mfunc(dev->dev) && 2366 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2367 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2368 MLX4_RESERVED_QKEY_BASE) { 2369 pr_err("Cannot use reserved QKEY" 2370 " 0x%x (range 0xffff0000..0xffffffff" 2371 " is reserved)\n", attr->qkey); 2372 err = -EINVAL; 2373 goto out; 2374 } 2375 context->qkey = cpu_to_be32(attr->qkey); 2376 } 2377 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2378 } 2379 2380 if (ibsrq) 2381 context->srqn = cpu_to_be32(1 << 24 | 2382 to_msrq(ibsrq)->msrq.srqn); 2383 2384 if (qp->rq.wqe_cnt && 2385 cur_state == IB_QPS_RESET && 2386 new_state == IB_QPS_INIT) 2387 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2388 2389 if (cur_state == IB_QPS_INIT && 2390 new_state == IB_QPS_RTR && 2391 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2392 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2393 context->pri_path.sched_queue = (qp->port - 1) << 6; 2394 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2395 qp->mlx4_ib_qp_type & 2396 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2397 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2398 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2399 context->pri_path.fl = 0x80; 2400 } else { 2401 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2402 context->pri_path.fl = 0x80; 2403 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2404 } 2405 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2406 IB_LINK_LAYER_ETHERNET) { 2407 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2408 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2409 context->pri_path.feup = 1 << 7; /* don't fsm */ 2410 /* handle smac_index */ 2411 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2412 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2413 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2414 err = handle_eth_ud_smac_index(dev, qp, context); 2415 if (err) { 2416 err = -EINVAL; 2417 goto out; 2418 } 2419 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2420 dev->qp1_proxy[qp->port - 1] = qp; 2421 } 2422 } 2423 } 2424 2425 if (qp_type == IB_QPT_RAW_PACKET) { 2426 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2427 MLX4_IB_LINK_TYPE_ETH; 2428 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2429 /* set QP to receive both tunneled & non-tunneled packets */ 2430 if (!rwq_ind_tbl) 2431 context->srqn = cpu_to_be32(7 << 28); 2432 } 2433 } 2434 2435 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2436 int is_eth = rdma_port_get_link_layer( 2437 &dev->ib_dev, qp->port) == 2438 IB_LINK_LAYER_ETHERNET; 2439 if (is_eth) { 2440 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2441 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2442 } 2443 } 2444 2445 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2446 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2447 sqd_event = 1; 2448 else 2449 sqd_event = 0; 2450 2451 if (!ucontext && 2452 cur_state == IB_QPS_RESET && 2453 new_state == IB_QPS_INIT) 2454 context->rlkey_roce_mode |= (1 << 4); 2455 2456 /* 2457 * Before passing a kernel QP to the HW, make sure that the 2458 * ownership bits of the send queue are set and the SQ 2459 * headroom is stamped so that the hardware doesn't start 2460 * processing stale work requests. 2461 */ 2462 if (!ucontext && 2463 cur_state == IB_QPS_RESET && 2464 new_state == IB_QPS_INIT) { 2465 struct mlx4_wqe_ctrl_seg *ctrl; 2466 int i; 2467 2468 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2469 ctrl = get_send_wqe(qp, i); 2470 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2471 ctrl->qpn_vlan.fence_size = 2472 1 << (qp->sq.wqe_shift - 4); 2473 stamp_send_wqe(qp, i); 2474 } 2475 } 2476 2477 if (rwq_ind_tbl && 2478 cur_state == IB_QPS_RESET && 2479 new_state == IB_QPS_INIT) { 2480 fill_qp_rss_context(context, qp); 2481 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2482 } 2483 2484 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2485 to_mlx4_state(new_state), context, optpar, 2486 sqd_event, &qp->mqp); 2487 if (err) 2488 goto out; 2489 2490 qp->state = new_state; 2491 2492 if (attr_mask & IB_QP_ACCESS_FLAGS) 2493 qp->atomic_rd_en = attr->qp_access_flags; 2494 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2495 qp->resp_depth = attr->max_dest_rd_atomic; 2496 if (attr_mask & IB_QP_PORT) { 2497 qp->port = attr->port_num; 2498 update_mcg_macs(dev, qp); 2499 } 2500 if (attr_mask & IB_QP_ALT_PATH) 2501 qp->alt_port = attr->alt_port_num; 2502 2503 if (is_sqp(dev, qp)) 2504 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2505 2506 /* 2507 * If we moved QP0 to RTR, bring the IB link up; if we moved 2508 * QP0 to RESET or ERROR, bring the link back down. 2509 */ 2510 if (is_qp0(dev, qp)) { 2511 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2512 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2513 pr_warn("INIT_PORT failed for port %d\n", 2514 qp->port); 2515 2516 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2517 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2518 mlx4_CLOSE_PORT(dev->dev, qp->port); 2519 } 2520 2521 /* 2522 * If we moved a kernel QP to RESET, clean up all old CQ 2523 * entries and reinitialize the QP. 2524 */ 2525 if (new_state == IB_QPS_RESET) { 2526 if (!ucontext) { 2527 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2528 ibsrq ? to_msrq(ibsrq) : NULL); 2529 if (send_cq != recv_cq) 2530 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2531 2532 qp->rq.head = 0; 2533 qp->rq.tail = 0; 2534 qp->sq.head = 0; 2535 qp->sq.tail = 0; 2536 qp->sq_next_wqe = 0; 2537 if (qp->rq.wqe_cnt) 2538 *qp->db.db = 0; 2539 2540 if (qp->flags & MLX4_IB_QP_NETIF) 2541 mlx4_ib_steer_qp_reg(dev, qp, 0); 2542 } 2543 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2544 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2545 qp->pri.smac = 0; 2546 qp->pri.smac_port = 0; 2547 } 2548 if (qp->alt.smac) { 2549 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2550 qp->alt.smac = 0; 2551 } 2552 if (qp->pri.vid < 0x1000) { 2553 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2554 qp->pri.vid = 0xFFFF; 2555 qp->pri.candidate_vid = 0xFFFF; 2556 qp->pri.update_vid = 0; 2557 } 2558 2559 if (qp->alt.vid < 0x1000) { 2560 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2561 qp->alt.vid = 0xFFFF; 2562 qp->alt.candidate_vid = 0xFFFF; 2563 qp->alt.update_vid = 0; 2564 } 2565 } 2566 out: 2567 if (err && qp->counter_index) 2568 mlx4_ib_free_qp_counter(dev, qp); 2569 if (err && steer_qp) 2570 mlx4_ib_steer_qp_reg(dev, qp, 0); 2571 kfree(context); 2572 if (qp->pri.candidate_smac || 2573 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2574 if (err) { 2575 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2576 } else { 2577 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2578 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2579 qp->pri.smac = qp->pri.candidate_smac; 2580 qp->pri.smac_index = qp->pri.candidate_smac_index; 2581 qp->pri.smac_port = qp->pri.candidate_smac_port; 2582 } 2583 qp->pri.candidate_smac = 0; 2584 qp->pri.candidate_smac_index = 0; 2585 qp->pri.candidate_smac_port = 0; 2586 } 2587 if (qp->alt.candidate_smac) { 2588 if (err) { 2589 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2590 } else { 2591 if (qp->alt.smac) 2592 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2593 qp->alt.smac = qp->alt.candidate_smac; 2594 qp->alt.smac_index = qp->alt.candidate_smac_index; 2595 qp->alt.smac_port = qp->alt.candidate_smac_port; 2596 } 2597 qp->alt.candidate_smac = 0; 2598 qp->alt.candidate_smac_index = 0; 2599 qp->alt.candidate_smac_port = 0; 2600 } 2601 2602 if (qp->pri.update_vid) { 2603 if (err) { 2604 if (qp->pri.candidate_vid < 0x1000) 2605 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2606 qp->pri.candidate_vid); 2607 } else { 2608 if (qp->pri.vid < 0x1000) 2609 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2610 qp->pri.vid); 2611 qp->pri.vid = qp->pri.candidate_vid; 2612 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2613 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2614 } 2615 qp->pri.candidate_vid = 0xFFFF; 2616 qp->pri.update_vid = 0; 2617 } 2618 2619 if (qp->alt.update_vid) { 2620 if (err) { 2621 if (qp->alt.candidate_vid < 0x1000) 2622 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2623 qp->alt.candidate_vid); 2624 } else { 2625 if (qp->alt.vid < 0x1000) 2626 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2627 qp->alt.vid); 2628 qp->alt.vid = qp->alt.candidate_vid; 2629 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2630 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2631 } 2632 qp->alt.candidate_vid = 0xFFFF; 2633 qp->alt.update_vid = 0; 2634 } 2635 2636 return err; 2637 } 2638 2639 enum { 2640 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2641 IB_QP_PORT), 2642 }; 2643 2644 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2645 int attr_mask, struct ib_udata *udata) 2646 { 2647 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2648 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2649 enum ib_qp_state cur_state, new_state; 2650 int err = -EINVAL; 2651 mutex_lock(&qp->mutex); 2652 2653 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2654 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2655 2656 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2657 attr_mask)) { 2658 pr_debug("qpn 0x%x: invalid attribute mask specified " 2659 "for transition %d to %d. qp_type %d," 2660 " attr_mask 0x%x\n", 2661 ibqp->qp_num, cur_state, new_state, 2662 ibqp->qp_type, attr_mask); 2663 goto out; 2664 } 2665 2666 if (ibqp->rwq_ind_tbl) { 2667 if (!(((cur_state == IB_QPS_RESET) && 2668 (new_state == IB_QPS_INIT)) || 2669 ((cur_state == IB_QPS_INIT) && 2670 (new_state == IB_QPS_RTR)))) { 2671 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2672 ibqp->qp_num, cur_state, new_state); 2673 2674 err = -EOPNOTSUPP; 2675 goto out; 2676 } 2677 2678 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2679 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2680 ibqp->qp_num, attr_mask, cur_state, new_state); 2681 2682 err = -EOPNOTSUPP; 2683 goto out; 2684 } 2685 } 2686 2687 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2688 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2689 if ((ibqp->qp_type == IB_QPT_RC) || 2690 (ibqp->qp_type == IB_QPT_UD) || 2691 (ibqp->qp_type == IB_QPT_UC) || 2692 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2693 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2694 attr->port_num = mlx4_ib_bond_next_port(dev); 2695 } 2696 } else { 2697 /* no sense in changing port_num 2698 * when ports are bonded */ 2699 attr_mask &= ~IB_QP_PORT; 2700 } 2701 } 2702 2703 if ((attr_mask & IB_QP_PORT) && 2704 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2705 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2706 "for transition %d to %d. qp_type %d\n", 2707 ibqp->qp_num, attr->port_num, cur_state, 2708 new_state, ibqp->qp_type); 2709 goto out; 2710 } 2711 2712 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2713 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2714 IB_LINK_LAYER_ETHERNET)) 2715 goto out; 2716 2717 if (attr_mask & IB_QP_PKEY_INDEX) { 2718 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2719 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2720 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2721 "for transition %d to %d. qp_type %d\n", 2722 ibqp->qp_num, attr->pkey_index, cur_state, 2723 new_state, ibqp->qp_type); 2724 goto out; 2725 } 2726 } 2727 2728 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2729 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2730 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2731 "Transition %d to %d. qp_type %d\n", 2732 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2733 new_state, ibqp->qp_type); 2734 goto out; 2735 } 2736 2737 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2738 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2739 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2740 "Transition %d to %d. qp_type %d\n", 2741 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2742 new_state, ibqp->qp_type); 2743 goto out; 2744 } 2745 2746 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2747 err = 0; 2748 goto out; 2749 } 2750 2751 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2752 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num, 2753 udata); 2754 if (err) 2755 goto out; 2756 } 2757 2758 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2759 cur_state, new_state, udata); 2760 2761 if (ibqp->rwq_ind_tbl && err) 2762 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata); 2763 2764 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2765 attr->port_num = 1; 2766 2767 out: 2768 mutex_unlock(&qp->mutex); 2769 return err; 2770 } 2771 2772 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2773 int attr_mask, struct ib_udata *udata) 2774 { 2775 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2776 int ret; 2777 2778 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2779 2780 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2781 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2782 int err = 0; 2783 2784 if (sqp->roce_v2_gsi) 2785 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2786 if (err) 2787 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2788 err); 2789 } 2790 return ret; 2791 } 2792 2793 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2794 { 2795 int i; 2796 for (i = 0; i < dev->caps.num_ports; i++) { 2797 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2798 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2799 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2800 return 0; 2801 } 2802 } 2803 return -EINVAL; 2804 } 2805 2806 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2807 const struct ib_ud_wr *wr, 2808 void *wqe, unsigned *mlx_seg_len) 2809 { 2810 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2811 struct ib_device *ib_dev = &mdev->ib_dev; 2812 struct mlx4_wqe_mlx_seg *mlx = wqe; 2813 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2814 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2815 u16 pkey; 2816 u32 qkey; 2817 int send_size; 2818 int header_size; 2819 int spc; 2820 int i; 2821 2822 if (wr->wr.opcode != IB_WR_SEND) 2823 return -EINVAL; 2824 2825 send_size = 0; 2826 2827 for (i = 0; i < wr->wr.num_sge; ++i) 2828 send_size += wr->wr.sg_list[i].length; 2829 2830 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2831 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2832 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2833 send_size += sizeof (struct mlx4_ib_tunnel_header); 2834 2835 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2836 2837 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2838 sqp->ud_header.lrh.service_level = 2839 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2840 sqp->ud_header.lrh.destination_lid = 2841 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2842 sqp->ud_header.lrh.source_lid = 2843 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2844 } 2845 2846 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2847 2848 /* force loopback */ 2849 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2850 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2851 2852 sqp->ud_header.lrh.virtual_lane = 0; 2853 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2854 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2855 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2856 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2857 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2858 else 2859 sqp->ud_header.bth.destination_qpn = 2860 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel); 2861 2862 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2863 if (mlx4_is_master(mdev->dev)) { 2864 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2865 return -EINVAL; 2866 } else { 2867 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2868 return -EINVAL; 2869 } 2870 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2871 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2872 2873 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2874 sqp->ud_header.immediate_present = 0; 2875 2876 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2877 2878 /* 2879 * Inline data segments may not cross a 64 byte boundary. If 2880 * our UD header is bigger than the space available up to the 2881 * next 64 byte boundary in the WQE, use two inline data 2882 * segments to hold the UD header. 2883 */ 2884 spc = MLX4_INLINE_ALIGN - 2885 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2886 if (header_size <= spc) { 2887 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2888 memcpy(inl + 1, sqp->header_buf, header_size); 2889 i = 1; 2890 } else { 2891 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2892 memcpy(inl + 1, sqp->header_buf, spc); 2893 2894 inl = (void *) (inl + 1) + spc; 2895 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2896 /* 2897 * Need a barrier here to make sure all the data is 2898 * visible before the byte_count field is set. 2899 * Otherwise the HCA prefetcher could grab the 64-byte 2900 * chunk with this inline segment and get a valid (!= 2901 * 0xffffffff) byte count but stale data, and end up 2902 * generating a packet with bad headers. 2903 * 2904 * The first inline segment's byte_count field doesn't 2905 * need a barrier, because it comes after a 2906 * control/MLX segment and therefore is at an offset 2907 * of 16 mod 64. 2908 */ 2909 wmb(); 2910 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2911 i = 2; 2912 } 2913 2914 *mlx_seg_len = 2915 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2916 return 0; 2917 } 2918 2919 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2920 { 2921 union sl2vl_tbl_to_u64 tmp_vltab; 2922 u8 vl; 2923 2924 if (sl > 15) 2925 return 0xf; 2926 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2927 vl = tmp_vltab.sl8[sl >> 1]; 2928 if (sl & 1) 2929 vl &= 0x0f; 2930 else 2931 vl >>= 4; 2932 return vl; 2933 } 2934 2935 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2936 int index, union ib_gid *gid, 2937 enum ib_gid_type *gid_type) 2938 { 2939 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2940 struct mlx4_port_gid_table *port_gid_table; 2941 unsigned long flags; 2942 2943 port_gid_table = &iboe->gids[port_num - 1]; 2944 spin_lock_irqsave(&iboe->lock, flags); 2945 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 2946 *gid_type = port_gid_table->gids[index].gid_type; 2947 spin_unlock_irqrestore(&iboe->lock, flags); 2948 if (rdma_is_zero_gid(gid)) 2949 return -ENOENT; 2950 2951 return 0; 2952 } 2953 2954 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2955 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr, 2956 void *wqe, unsigned *mlx_seg_len) 2957 { 2958 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2959 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 2960 struct mlx4_wqe_mlx_seg *mlx = wqe; 2961 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2962 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2963 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2964 union ib_gid sgid; 2965 u16 pkey; 2966 int send_size; 2967 int header_size; 2968 int spc; 2969 int i; 2970 int err = 0; 2971 u16 vlan = 0xffff; 2972 bool is_eth; 2973 bool is_vlan = false; 2974 bool is_grh; 2975 bool is_udp = false; 2976 int ip_version = 0; 2977 2978 send_size = 0; 2979 for (i = 0; i < wr->wr.num_sge; ++i) 2980 send_size += wr->wr.sg_list[i].length; 2981 2982 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2983 is_grh = mlx4_ib_ah_grh_present(ah); 2984 if (is_eth) { 2985 enum ib_gid_type gid_type; 2986 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2987 /* When multi-function is enabled, the ib_core gid 2988 * indexes don't necessarily match the hw ones, so 2989 * we must use our own cache */ 2990 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2991 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2992 ah->av.ib.gid_index, &sgid.raw[0]); 2993 if (err) 2994 return err; 2995 } else { 2996 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 2997 ah->av.ib.gid_index, 2998 &sgid, &gid_type); 2999 if (!err) { 3000 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3001 if (is_udp) { 3002 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3003 ip_version = 4; 3004 else 3005 ip_version = 6; 3006 is_grh = false; 3007 } 3008 } else { 3009 return err; 3010 } 3011 } 3012 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3013 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3014 is_vlan = 1; 3015 } 3016 } 3017 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3018 ip_version, is_udp, 0, &sqp->ud_header); 3019 if (err) 3020 return err; 3021 3022 if (!is_eth) { 3023 sqp->ud_header.lrh.service_level = 3024 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3025 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3026 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3027 } 3028 3029 if (is_grh || (ip_version == 6)) { 3030 sqp->ud_header.grh.traffic_class = 3031 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3032 sqp->ud_header.grh.flow_label = 3033 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3034 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3035 if (is_eth) { 3036 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3037 } else { 3038 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3039 /* When multi-function is enabled, the ib_core gid 3040 * indexes don't necessarily match the hw ones, so 3041 * we must use our own cache 3042 */ 3043 sqp->ud_header.grh.source_gid.global.subnet_prefix = 3044 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 3045 demux[sqp->qp.port - 1]. 3046 subnet_prefix))); 3047 sqp->ud_header.grh.source_gid.global.interface_id = 3048 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 3049 guid_cache[ah->av.ib.gid_index]; 3050 } else { 3051 sqp->ud_header.grh.source_gid = 3052 ah->ibah.sgid_attr->gid; 3053 } 3054 } 3055 memcpy(sqp->ud_header.grh.destination_gid.raw, 3056 ah->av.ib.dgid, 16); 3057 } 3058 3059 if (ip_version == 4) { 3060 sqp->ud_header.ip4.tos = 3061 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3062 sqp->ud_header.ip4.id = 0; 3063 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3064 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3065 3066 memcpy(&sqp->ud_header.ip4.saddr, 3067 sgid.raw + 12, 4); 3068 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3069 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3070 } 3071 3072 if (is_udp) { 3073 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3074 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3075 sqp->ud_header.udp.csum = 0; 3076 } 3077 3078 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3079 3080 if (!is_eth) { 3081 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3082 (sqp->ud_header.lrh.destination_lid == 3083 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 3084 (sqp->ud_header.lrh.service_level << 8)); 3085 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3086 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3087 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3088 } 3089 3090 switch (wr->wr.opcode) { 3091 case IB_WR_SEND: 3092 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3093 sqp->ud_header.immediate_present = 0; 3094 break; 3095 case IB_WR_SEND_WITH_IMM: 3096 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3097 sqp->ud_header.immediate_present = 1; 3098 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3099 break; 3100 default: 3101 return -EINVAL; 3102 } 3103 3104 if (is_eth) { 3105 struct in6_addr in6; 3106 u16 ether_type; 3107 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3108 3109 ether_type = (!is_udp) ? ETH_P_IBOE: 3110 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3111 3112 mlx->sched_prio = cpu_to_be16(pcp); 3113 3114 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3115 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 3116 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3117 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3118 memcpy(&in6, sgid.raw, sizeof(in6)); 3119 3120 3121 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3122 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3123 if (!is_vlan) { 3124 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3125 } else { 3126 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3127 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3128 } 3129 } else { 3130 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 3131 sl_to_vl(to_mdev(ib_dev), 3132 sqp->ud_header.lrh.service_level, 3133 sqp->qp.port); 3134 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3135 return -EINVAL; 3136 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3137 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3138 } 3139 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3140 if (!sqp->qp.ibqp.qp_num) 3141 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 3142 else 3143 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 3144 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3145 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3146 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3147 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3148 sqp->qkey : wr->remote_qkey); 3149 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 3150 3151 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3152 3153 if (0) { 3154 pr_err("built UD header of size %d:\n", header_size); 3155 for (i = 0; i < header_size / 4; ++i) { 3156 if (i % 8 == 0) 3157 pr_err(" [%02x] ", i * 4); 3158 pr_cont(" %08x", 3159 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3160 if ((i + 1) % 8 == 0) 3161 pr_cont("\n"); 3162 } 3163 pr_err("\n"); 3164 } 3165 3166 /* 3167 * Inline data segments may not cross a 64 byte boundary. If 3168 * our UD header is bigger than the space available up to the 3169 * next 64 byte boundary in the WQE, use two inline data 3170 * segments to hold the UD header. 3171 */ 3172 spc = MLX4_INLINE_ALIGN - 3173 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3174 if (header_size <= spc) { 3175 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3176 memcpy(inl + 1, sqp->header_buf, header_size); 3177 i = 1; 3178 } else { 3179 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3180 memcpy(inl + 1, sqp->header_buf, spc); 3181 3182 inl = (void *) (inl + 1) + spc; 3183 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3184 /* 3185 * Need a barrier here to make sure all the data is 3186 * visible before the byte_count field is set. 3187 * Otherwise the HCA prefetcher could grab the 64-byte 3188 * chunk with this inline segment and get a valid (!= 3189 * 0xffffffff) byte count but stale data, and end up 3190 * generating a packet with bad headers. 3191 * 3192 * The first inline segment's byte_count field doesn't 3193 * need a barrier, because it comes after a 3194 * control/MLX segment and therefore is at an offset 3195 * of 16 mod 64. 3196 */ 3197 wmb(); 3198 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3199 i = 2; 3200 } 3201 3202 *mlx_seg_len = 3203 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3204 return 0; 3205 } 3206 3207 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3208 { 3209 unsigned cur; 3210 struct mlx4_ib_cq *cq; 3211 3212 cur = wq->head - wq->tail; 3213 if (likely(cur + nreq < wq->max_post)) 3214 return 0; 3215 3216 cq = to_mcq(ib_cq); 3217 spin_lock(&cq->lock); 3218 cur = wq->head - wq->tail; 3219 spin_unlock(&cq->lock); 3220 3221 return cur + nreq >= wq->max_post; 3222 } 3223 3224 static __be32 convert_access(int acc) 3225 { 3226 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3227 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3228 (acc & IB_ACCESS_REMOTE_WRITE ? 3229 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3230 (acc & IB_ACCESS_REMOTE_READ ? 3231 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3232 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3233 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3234 } 3235 3236 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3237 const struct ib_reg_wr *wr) 3238 { 3239 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3240 3241 fseg->flags = convert_access(wr->access); 3242 fseg->mem_key = cpu_to_be32(wr->key); 3243 fseg->buf_list = cpu_to_be64(mr->page_map); 3244 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3245 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3246 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3247 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3248 fseg->reserved[0] = 0; 3249 fseg->reserved[1] = 0; 3250 } 3251 3252 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3253 { 3254 memset(iseg, 0, sizeof(*iseg)); 3255 iseg->mem_key = cpu_to_be32(rkey); 3256 } 3257 3258 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3259 u64 remote_addr, u32 rkey) 3260 { 3261 rseg->raddr = cpu_to_be64(remote_addr); 3262 rseg->rkey = cpu_to_be32(rkey); 3263 rseg->reserved = 0; 3264 } 3265 3266 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3267 const struct ib_atomic_wr *wr) 3268 { 3269 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3270 aseg->swap_add = cpu_to_be64(wr->swap); 3271 aseg->compare = cpu_to_be64(wr->compare_add); 3272 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3273 aseg->swap_add = cpu_to_be64(wr->compare_add); 3274 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3275 } else { 3276 aseg->swap_add = cpu_to_be64(wr->compare_add); 3277 aseg->compare = 0; 3278 } 3279 3280 } 3281 3282 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3283 const struct ib_atomic_wr *wr) 3284 { 3285 aseg->swap_add = cpu_to_be64(wr->swap); 3286 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3287 aseg->compare = cpu_to_be64(wr->compare_add); 3288 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3289 } 3290 3291 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3292 const struct ib_ud_wr *wr) 3293 { 3294 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3295 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3296 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3297 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3298 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3299 } 3300 3301 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3302 struct mlx4_wqe_datagram_seg *dseg, 3303 const struct ib_ud_wr *wr, 3304 enum mlx4_ib_qp_type qpt) 3305 { 3306 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3307 struct mlx4_av sqp_av = {0}; 3308 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3309 3310 /* force loopback */ 3311 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3312 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3313 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3314 cpu_to_be32(0xf0000000); 3315 3316 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3317 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3318 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3319 else 3320 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3321 /* Use QKEY from the QP context, which is set by master */ 3322 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3323 } 3324 3325 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3326 unsigned *mlx_seg_len) 3327 { 3328 struct mlx4_wqe_inline_seg *inl = wqe; 3329 struct mlx4_ib_tunnel_header hdr; 3330 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3331 int spc; 3332 int i; 3333 3334 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3335 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3336 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3337 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3338 memcpy(hdr.mac, ah->av.eth.mac, 6); 3339 hdr.vlan = ah->av.eth.vlan; 3340 3341 spc = MLX4_INLINE_ALIGN - 3342 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3343 if (sizeof (hdr) <= spc) { 3344 memcpy(inl + 1, &hdr, sizeof (hdr)); 3345 wmb(); 3346 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3347 i = 1; 3348 } else { 3349 memcpy(inl + 1, &hdr, spc); 3350 wmb(); 3351 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3352 3353 inl = (void *) (inl + 1) + spc; 3354 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3355 wmb(); 3356 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3357 i = 2; 3358 } 3359 3360 *mlx_seg_len = 3361 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3362 } 3363 3364 static void set_mlx_icrc_seg(void *dseg) 3365 { 3366 u32 *t = dseg; 3367 struct mlx4_wqe_inline_seg *iseg = dseg; 3368 3369 t[1] = 0; 3370 3371 /* 3372 * Need a barrier here before writing the byte_count field to 3373 * make sure that all the data is visible before the 3374 * byte_count field is set. Otherwise, if the segment begins 3375 * a new cacheline, the HCA prefetcher could grab the 64-byte 3376 * chunk and get a valid (!= * 0xffffffff) byte count but 3377 * stale data, and end up sending the wrong data. 3378 */ 3379 wmb(); 3380 3381 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3382 } 3383 3384 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3385 { 3386 dseg->lkey = cpu_to_be32(sg->lkey); 3387 dseg->addr = cpu_to_be64(sg->addr); 3388 3389 /* 3390 * Need a barrier here before writing the byte_count field to 3391 * make sure that all the data is visible before the 3392 * byte_count field is set. Otherwise, if the segment begins 3393 * a new cacheline, the HCA prefetcher could grab the 64-byte 3394 * chunk and get a valid (!= * 0xffffffff) byte count but 3395 * stale data, and end up sending the wrong data. 3396 */ 3397 wmb(); 3398 3399 dseg->byte_count = cpu_to_be32(sg->length); 3400 } 3401 3402 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3403 { 3404 dseg->byte_count = cpu_to_be32(sg->length); 3405 dseg->lkey = cpu_to_be32(sg->lkey); 3406 dseg->addr = cpu_to_be64(sg->addr); 3407 } 3408 3409 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3410 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3411 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3412 { 3413 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3414 3415 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3416 *blh = cpu_to_be32(1 << 6); 3417 3418 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3419 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3420 return -EINVAL; 3421 3422 memcpy(wqe->header, wr->header, wr->hlen); 3423 3424 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3425 *lso_seg_len = halign; 3426 return 0; 3427 } 3428 3429 static __be32 send_ieth(const struct ib_send_wr *wr) 3430 { 3431 switch (wr->opcode) { 3432 case IB_WR_SEND_WITH_IMM: 3433 case IB_WR_RDMA_WRITE_WITH_IMM: 3434 return wr->ex.imm_data; 3435 3436 case IB_WR_SEND_WITH_INV: 3437 return cpu_to_be32(wr->ex.invalidate_rkey); 3438 3439 default: 3440 return 0; 3441 } 3442 } 3443 3444 static void add_zero_len_inline(void *wqe) 3445 { 3446 struct mlx4_wqe_inline_seg *inl = wqe; 3447 memset(wqe, 0, 16); 3448 inl->byte_count = cpu_to_be32(1 << 31); 3449 } 3450 3451 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3452 const struct ib_send_wr **bad_wr, bool drain) 3453 { 3454 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3455 void *wqe; 3456 struct mlx4_wqe_ctrl_seg *ctrl; 3457 struct mlx4_wqe_data_seg *dseg; 3458 unsigned long flags; 3459 int nreq; 3460 int err = 0; 3461 unsigned ind; 3462 int uninitialized_var(size); 3463 unsigned uninitialized_var(seglen); 3464 __be32 dummy; 3465 __be32 *lso_wqe; 3466 __be32 uninitialized_var(lso_hdr_sz); 3467 __be32 blh; 3468 int i; 3469 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3470 3471 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3472 struct mlx4_ib_sqp *sqp = to_msqp(qp); 3473 3474 if (sqp->roce_v2_gsi) { 3475 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3476 enum ib_gid_type gid_type; 3477 union ib_gid gid; 3478 3479 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 3480 ah->av.ib.gid_index, 3481 &gid, &gid_type)) 3482 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3483 to_mqp(sqp->roce_v2_gsi) : qp; 3484 else 3485 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3486 ah->av.ib.gid_index); 3487 } 3488 } 3489 3490 spin_lock_irqsave(&qp->sq.lock, flags); 3491 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3492 !drain) { 3493 err = -EIO; 3494 *bad_wr = wr; 3495 nreq = 0; 3496 goto out; 3497 } 3498 3499 ind = qp->sq_next_wqe; 3500 3501 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3502 lso_wqe = &dummy; 3503 blh = 0; 3504 3505 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3506 err = -ENOMEM; 3507 *bad_wr = wr; 3508 goto out; 3509 } 3510 3511 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3512 err = -EINVAL; 3513 *bad_wr = wr; 3514 goto out; 3515 } 3516 3517 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3518 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3519 3520 ctrl->srcrb_flags = 3521 (wr->send_flags & IB_SEND_SIGNALED ? 3522 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3523 (wr->send_flags & IB_SEND_SOLICITED ? 3524 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3525 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3526 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3527 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3528 qp->sq_signal_bits; 3529 3530 ctrl->imm = send_ieth(wr); 3531 3532 wqe += sizeof *ctrl; 3533 size = sizeof *ctrl / 16; 3534 3535 switch (qp->mlx4_ib_qp_type) { 3536 case MLX4_IB_QPT_RC: 3537 case MLX4_IB_QPT_UC: 3538 switch (wr->opcode) { 3539 case IB_WR_ATOMIC_CMP_AND_SWP: 3540 case IB_WR_ATOMIC_FETCH_AND_ADD: 3541 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3542 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3543 atomic_wr(wr)->rkey); 3544 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3545 3546 set_atomic_seg(wqe, atomic_wr(wr)); 3547 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3548 3549 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3550 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3551 3552 break; 3553 3554 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3555 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3556 atomic_wr(wr)->rkey); 3557 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3558 3559 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3560 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3561 3562 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3563 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3564 3565 break; 3566 3567 case IB_WR_RDMA_READ: 3568 case IB_WR_RDMA_WRITE: 3569 case IB_WR_RDMA_WRITE_WITH_IMM: 3570 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3571 rdma_wr(wr)->rkey); 3572 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3573 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3574 break; 3575 3576 case IB_WR_LOCAL_INV: 3577 ctrl->srcrb_flags |= 3578 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3579 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3580 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3581 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3582 break; 3583 3584 case IB_WR_REG_MR: 3585 ctrl->srcrb_flags |= 3586 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3587 set_reg_seg(wqe, reg_wr(wr)); 3588 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3589 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3590 break; 3591 3592 default: 3593 /* No extra segments required for sends */ 3594 break; 3595 } 3596 break; 3597 3598 case MLX4_IB_QPT_TUN_SMI_OWNER: 3599 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3600 ctrl, &seglen); 3601 if (unlikely(err)) { 3602 *bad_wr = wr; 3603 goto out; 3604 } 3605 wqe += seglen; 3606 size += seglen / 16; 3607 break; 3608 case MLX4_IB_QPT_TUN_SMI: 3609 case MLX4_IB_QPT_TUN_GSI: 3610 /* this is a UD qp used in MAD responses to slaves. */ 3611 set_datagram_seg(wqe, ud_wr(wr)); 3612 /* set the forced-loopback bit in the data seg av */ 3613 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3614 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3615 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3616 break; 3617 case MLX4_IB_QPT_UD: 3618 set_datagram_seg(wqe, ud_wr(wr)); 3619 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3620 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3621 3622 if (wr->opcode == IB_WR_LSO) { 3623 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3624 &lso_hdr_sz, &blh); 3625 if (unlikely(err)) { 3626 *bad_wr = wr; 3627 goto out; 3628 } 3629 lso_wqe = (__be32 *) wqe; 3630 wqe += seglen; 3631 size += seglen / 16; 3632 } 3633 break; 3634 3635 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3636 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3637 ctrl, &seglen); 3638 if (unlikely(err)) { 3639 *bad_wr = wr; 3640 goto out; 3641 } 3642 wqe += seglen; 3643 size += seglen / 16; 3644 /* to start tunnel header on a cache-line boundary */ 3645 add_zero_len_inline(wqe); 3646 wqe += 16; 3647 size++; 3648 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3649 wqe += seglen; 3650 size += seglen / 16; 3651 break; 3652 case MLX4_IB_QPT_PROXY_SMI: 3653 case MLX4_IB_QPT_PROXY_GSI: 3654 /* If we are tunneling special qps, this is a UD qp. 3655 * In this case we first add a UD segment targeting 3656 * the tunnel qp, and then add a header with address 3657 * information */ 3658 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3659 ud_wr(wr), 3660 qp->mlx4_ib_qp_type); 3661 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3662 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3663 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3664 wqe += seglen; 3665 size += seglen / 16; 3666 break; 3667 3668 case MLX4_IB_QPT_SMI: 3669 case MLX4_IB_QPT_GSI: 3670 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3671 &seglen); 3672 if (unlikely(err)) { 3673 *bad_wr = wr; 3674 goto out; 3675 } 3676 wqe += seglen; 3677 size += seglen / 16; 3678 break; 3679 3680 default: 3681 break; 3682 } 3683 3684 /* 3685 * Write data segments in reverse order, so as to 3686 * overwrite cacheline stamp last within each 3687 * cacheline. This avoids issues with WQE 3688 * prefetching. 3689 */ 3690 3691 dseg = wqe; 3692 dseg += wr->num_sge - 1; 3693 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3694 3695 /* Add one more inline data segment for ICRC for MLX sends */ 3696 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3697 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3698 qp->mlx4_ib_qp_type & 3699 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3700 set_mlx_icrc_seg(dseg + 1); 3701 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3702 } 3703 3704 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3705 set_data_seg(dseg, wr->sg_list + i); 3706 3707 /* 3708 * Possibly overwrite stamping in cacheline with LSO 3709 * segment only after making sure all data segments 3710 * are written. 3711 */ 3712 wmb(); 3713 *lso_wqe = lso_hdr_sz; 3714 3715 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3716 MLX4_WQE_CTRL_FENCE : 0) | size; 3717 3718 /* 3719 * Make sure descriptor is fully written before 3720 * setting ownership bit (because HW can start 3721 * executing as soon as we do). 3722 */ 3723 wmb(); 3724 3725 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3726 *bad_wr = wr; 3727 err = -EINVAL; 3728 goto out; 3729 } 3730 3731 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3732 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3733 3734 /* 3735 * We can improve latency by not stamping the last 3736 * send queue WQE until after ringing the doorbell, so 3737 * only stamp here if there are still more WQEs to post. 3738 */ 3739 if (wr->next) 3740 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3741 ind++; 3742 } 3743 3744 out: 3745 if (likely(nreq)) { 3746 qp->sq.head += nreq; 3747 3748 /* 3749 * Make sure that descriptors are written before 3750 * doorbell record. 3751 */ 3752 wmb(); 3753 3754 writel_relaxed(qp->doorbell_qpn, 3755 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3756 3757 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3758 3759 qp->sq_next_wqe = ind; 3760 } 3761 3762 spin_unlock_irqrestore(&qp->sq.lock, flags); 3763 3764 return err; 3765 } 3766 3767 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3768 const struct ib_send_wr **bad_wr) 3769 { 3770 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3771 } 3772 3773 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3774 const struct ib_recv_wr **bad_wr, bool drain) 3775 { 3776 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3777 struct mlx4_wqe_data_seg *scat; 3778 unsigned long flags; 3779 int err = 0; 3780 int nreq; 3781 int ind; 3782 int max_gs; 3783 int i; 3784 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3785 3786 max_gs = qp->rq.max_gs; 3787 spin_lock_irqsave(&qp->rq.lock, flags); 3788 3789 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3790 !drain) { 3791 err = -EIO; 3792 *bad_wr = wr; 3793 nreq = 0; 3794 goto out; 3795 } 3796 3797 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3798 3799 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3800 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3801 err = -ENOMEM; 3802 *bad_wr = wr; 3803 goto out; 3804 } 3805 3806 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3807 err = -EINVAL; 3808 *bad_wr = wr; 3809 goto out; 3810 } 3811 3812 scat = get_recv_wqe(qp, ind); 3813 3814 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3815 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3816 ib_dma_sync_single_for_device(ibqp->device, 3817 qp->sqp_proxy_rcv[ind].map, 3818 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3819 DMA_FROM_DEVICE); 3820 scat->byte_count = 3821 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3822 /* use dma lkey from upper layer entry */ 3823 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3824 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3825 scat++; 3826 max_gs--; 3827 } 3828 3829 for (i = 0; i < wr->num_sge; ++i) 3830 __set_data_seg(scat + i, wr->sg_list + i); 3831 3832 if (i < max_gs) { 3833 scat[i].byte_count = 0; 3834 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3835 scat[i].addr = 0; 3836 } 3837 3838 qp->rq.wrid[ind] = wr->wr_id; 3839 3840 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3841 } 3842 3843 out: 3844 if (likely(nreq)) { 3845 qp->rq.head += nreq; 3846 3847 /* 3848 * Make sure that descriptors are written before 3849 * doorbell record. 3850 */ 3851 wmb(); 3852 3853 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3854 } 3855 3856 spin_unlock_irqrestore(&qp->rq.lock, flags); 3857 3858 return err; 3859 } 3860 3861 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3862 const struct ib_recv_wr **bad_wr) 3863 { 3864 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3865 } 3866 3867 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3868 { 3869 switch (mlx4_state) { 3870 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3871 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3872 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3873 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3874 case MLX4_QP_STATE_SQ_DRAINING: 3875 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3876 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3877 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3878 default: return -1; 3879 } 3880 } 3881 3882 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3883 { 3884 switch (mlx4_mig_state) { 3885 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3886 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3887 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3888 default: return -1; 3889 } 3890 } 3891 3892 static int to_ib_qp_access_flags(int mlx4_flags) 3893 { 3894 int ib_flags = 0; 3895 3896 if (mlx4_flags & MLX4_QP_BIT_RRE) 3897 ib_flags |= IB_ACCESS_REMOTE_READ; 3898 if (mlx4_flags & MLX4_QP_BIT_RWE) 3899 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3900 if (mlx4_flags & MLX4_QP_BIT_RAE) 3901 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3902 3903 return ib_flags; 3904 } 3905 3906 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3907 struct rdma_ah_attr *ah_attr, 3908 struct mlx4_qp_path *path) 3909 { 3910 struct mlx4_dev *dev = ibdev->dev; 3911 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3912 3913 memset(ah_attr, 0, sizeof(*ah_attr)); 3914 if (port_num == 0 || port_num > dev->caps.num_ports) 3915 return; 3916 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3917 3918 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3919 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3920 ((path->sched_queue & 4) << 1)); 3921 else 3922 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3923 rdma_ah_set_port_num(ah_attr, port_num); 3924 3925 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3926 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3927 rdma_ah_set_static_rate(ah_attr, 3928 path->static_rate ? path->static_rate - 5 : 0); 3929 if (path->grh_mylmc & (1 << 7)) { 3930 rdma_ah_set_grh(ah_attr, NULL, 3931 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3932 path->mgid_index, 3933 path->hop_limit, 3934 (be32_to_cpu(path->tclass_flowlabel) 3935 >> 20) & 0xff); 3936 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 3937 } 3938 } 3939 3940 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3941 struct ib_qp_init_attr *qp_init_attr) 3942 { 3943 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3944 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3945 struct mlx4_qp_context context; 3946 int mlx4_state; 3947 int err = 0; 3948 3949 if (ibqp->rwq_ind_tbl) 3950 return -EOPNOTSUPP; 3951 3952 mutex_lock(&qp->mutex); 3953 3954 if (qp->state == IB_QPS_RESET) { 3955 qp_attr->qp_state = IB_QPS_RESET; 3956 goto done; 3957 } 3958 3959 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3960 if (err) { 3961 err = -EINVAL; 3962 goto out; 3963 } 3964 3965 mlx4_state = be32_to_cpu(context.flags) >> 28; 3966 3967 qp->state = to_ib_qp_state(mlx4_state); 3968 qp_attr->qp_state = qp->state; 3969 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3970 qp_attr->path_mig_state = 3971 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3972 qp_attr->qkey = be32_to_cpu(context.qkey); 3973 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3974 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3975 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3976 qp_attr->qp_access_flags = 3977 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3978 3979 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3980 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3981 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3982 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3983 qp_attr->alt_port_num = 3984 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 3985 } 3986 3987 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3988 if (qp_attr->qp_state == IB_QPS_INIT) 3989 qp_attr->port_num = qp->port; 3990 else 3991 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3992 3993 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3994 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3995 3996 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3997 3998 qp_attr->max_dest_rd_atomic = 3999 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4000 qp_attr->min_rnr_timer = 4001 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4002 qp_attr->timeout = context.pri_path.ackto >> 3; 4003 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4004 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4005 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4006 4007 done: 4008 qp_attr->cur_qp_state = qp_attr->qp_state; 4009 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4010 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4011 4012 if (!ibqp->uobject) { 4013 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4014 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4015 } else { 4016 qp_attr->cap.max_send_wr = 0; 4017 qp_attr->cap.max_send_sge = 0; 4018 } 4019 4020 /* 4021 * We don't support inline sends for kernel QPs (yet), and we 4022 * don't know what userspace's value should be. 4023 */ 4024 qp_attr->cap.max_inline_data = 0; 4025 4026 qp_init_attr->cap = qp_attr->cap; 4027 4028 qp_init_attr->create_flags = 0; 4029 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4030 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4031 4032 if (qp->flags & MLX4_IB_QP_LSO) 4033 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4034 4035 if (qp->flags & MLX4_IB_QP_NETIF) 4036 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4037 4038 qp_init_attr->sq_sig_type = 4039 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4040 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4041 4042 out: 4043 mutex_unlock(&qp->mutex); 4044 return err; 4045 } 4046 4047 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4048 struct ib_wq_init_attr *init_attr, 4049 struct ib_udata *udata) 4050 { 4051 struct mlx4_ib_dev *dev; 4052 struct ib_qp_init_attr ib_qp_init_attr; 4053 struct mlx4_ib_qp *qp; 4054 struct mlx4_ib_create_wq ucmd; 4055 int err, required_cmd_sz; 4056 4057 if (!udata) 4058 return ERR_PTR(-EINVAL); 4059 4060 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4061 sizeof(ucmd.comp_mask); 4062 if (udata->inlen < required_cmd_sz) { 4063 pr_debug("invalid inlen\n"); 4064 return ERR_PTR(-EINVAL); 4065 } 4066 4067 if (udata->inlen > sizeof(ucmd) && 4068 !ib_is_udata_cleared(udata, sizeof(ucmd), 4069 udata->inlen - sizeof(ucmd))) { 4070 pr_debug("inlen is not supported\n"); 4071 return ERR_PTR(-EOPNOTSUPP); 4072 } 4073 4074 if (udata->outlen) 4075 return ERR_PTR(-EOPNOTSUPP); 4076 4077 dev = to_mdev(pd->device); 4078 4079 if (init_attr->wq_type != IB_WQT_RQ) { 4080 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4081 return ERR_PTR(-EOPNOTSUPP); 4082 } 4083 4084 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) { 4085 pr_debug("unsupported create_flags %u\n", 4086 init_attr->create_flags); 4087 return ERR_PTR(-EOPNOTSUPP); 4088 } 4089 4090 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4091 if (!qp) 4092 return ERR_PTR(-ENOMEM); 4093 4094 qp->pri.vid = 0xFFFF; 4095 qp->alt.vid = 0xFFFF; 4096 4097 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr)); 4098 ib_qp_init_attr.qp_context = init_attr->wq_context; 4099 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4100 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4101 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4102 ib_qp_init_attr.recv_cq = init_attr->cq; 4103 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4104 4105 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4106 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4107 4108 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr, 4109 udata, 0, &qp); 4110 if (err) { 4111 kfree(qp); 4112 return ERR_PTR(err); 4113 } 4114 4115 qp->ibwq.event_handler = init_attr->event_handler; 4116 qp->ibwq.wq_num = qp->mqp.qpn; 4117 qp->ibwq.state = IB_WQS_RESET; 4118 4119 return &qp->ibwq; 4120 } 4121 4122 static int ib_wq2qp_state(enum ib_wq_state state) 4123 { 4124 switch (state) { 4125 case IB_WQS_RESET: 4126 return IB_QPS_RESET; 4127 case IB_WQS_RDY: 4128 return IB_QPS_RTR; 4129 default: 4130 return IB_QPS_ERR; 4131 } 4132 } 4133 4134 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 4135 struct ib_udata *udata) 4136 { 4137 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4138 enum ib_qp_state qp_cur_state; 4139 enum ib_qp_state qp_new_state; 4140 int attr_mask; 4141 int err; 4142 4143 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4144 * the WQ logic state. 4145 */ 4146 qp_cur_state = qp->state; 4147 qp_new_state = ib_wq2qp_state(new_state); 4148 4149 if (ib_wq2qp_state(new_state) == qp_cur_state) 4150 return 0; 4151 4152 if (new_state == IB_WQS_RDY) { 4153 struct ib_qp_attr attr = {}; 4154 4155 attr.port_num = qp->port; 4156 attr_mask = IB_QP_PORT; 4157 4158 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4159 attr_mask, IB_QPS_RESET, IB_QPS_INIT, 4160 udata); 4161 if (err) { 4162 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4163 ibwq->wq_num); 4164 return err; 4165 } 4166 4167 qp_cur_state = IB_QPS_INIT; 4168 } 4169 4170 attr_mask = 0; 4171 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4172 qp_cur_state, qp_new_state, udata); 4173 4174 if (err && (qp_cur_state == IB_QPS_INIT)) { 4175 qp_new_state = IB_QPS_RESET; 4176 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4177 attr_mask, IB_QPS_INIT, IB_QPS_RESET, 4178 udata)) { 4179 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4180 ibwq->wq_num); 4181 qp_new_state = IB_QPS_INIT; 4182 } 4183 } 4184 4185 qp->state = qp_new_state; 4186 4187 return err; 4188 } 4189 4190 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4191 u32 wq_attr_mask, struct ib_udata *udata) 4192 { 4193 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4194 struct mlx4_ib_modify_wq ucmd = {}; 4195 size_t required_cmd_sz; 4196 enum ib_wq_state cur_state, new_state; 4197 int err = 0; 4198 4199 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4200 sizeof(ucmd.reserved); 4201 if (udata->inlen < required_cmd_sz) 4202 return -EINVAL; 4203 4204 if (udata->inlen > sizeof(ucmd) && 4205 !ib_is_udata_cleared(udata, sizeof(ucmd), 4206 udata->inlen - sizeof(ucmd))) 4207 return -EOPNOTSUPP; 4208 4209 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4210 return -EFAULT; 4211 4212 if (ucmd.comp_mask || ucmd.reserved) 4213 return -EOPNOTSUPP; 4214 4215 if (wq_attr_mask & IB_WQ_FLAGS) 4216 return -EOPNOTSUPP; 4217 4218 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state : 4219 ibwq->state; 4220 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state; 4221 4222 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR || 4223 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR) 4224 return -EINVAL; 4225 4226 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4227 return -EINVAL; 4228 4229 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4230 return -EINVAL; 4231 4232 /* Need to protect against the parent RSS which also may modify WQ 4233 * state. 4234 */ 4235 mutex_lock(&qp->mutex); 4236 4237 /* Can update HW state only if a RSS QP has already associated to this 4238 * WQ, so we can apply its port on the WQ. 4239 */ 4240 if (qp->rss_usecnt) 4241 err = _mlx4_ib_modify_wq(ibwq, new_state, udata); 4242 4243 if (!err) 4244 ibwq->state = new_state; 4245 4246 mutex_unlock(&qp->mutex); 4247 4248 return err; 4249 } 4250 4251 int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata) 4252 { 4253 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4254 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4255 4256 if (qp->counter_index) 4257 mlx4_ib_free_qp_counter(dev, qp); 4258 4259 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata); 4260 4261 kfree(qp); 4262 4263 return 0; 4264 } 4265 4266 struct ib_rwq_ind_table 4267 *mlx4_ib_create_rwq_ind_table(struct ib_device *device, 4268 struct ib_rwq_ind_table_init_attr *init_attr, 4269 struct ib_udata *udata) 4270 { 4271 struct ib_rwq_ind_table *rwq_ind_table; 4272 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4273 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4274 unsigned int base_wqn; 4275 size_t min_resp_len; 4276 int i; 4277 int err; 4278 4279 if (udata->inlen > 0 && 4280 !ib_is_udata_cleared(udata, 0, 4281 udata->inlen)) 4282 return ERR_PTR(-EOPNOTSUPP); 4283 4284 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4285 if (udata->outlen && udata->outlen < min_resp_len) 4286 return ERR_PTR(-EINVAL); 4287 4288 if (ind_tbl_size > 4289 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4290 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4291 ind_tbl_size, 4292 device->attrs.rss_caps.max_rwq_indirection_table_size); 4293 return ERR_PTR(-EINVAL); 4294 } 4295 4296 base_wqn = init_attr->ind_tbl[0]->wq_num; 4297 4298 if (base_wqn % ind_tbl_size) { 4299 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4300 base_wqn); 4301 return ERR_PTR(-EINVAL); 4302 } 4303 4304 for (i = 1; i < ind_tbl_size; i++) { 4305 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4306 pr_debug("indirection table's WQNs aren't consecutive\n"); 4307 return ERR_PTR(-EINVAL); 4308 } 4309 } 4310 4311 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL); 4312 if (!rwq_ind_table) 4313 return ERR_PTR(-ENOMEM); 4314 4315 if (udata->outlen) { 4316 resp.response_length = offsetof(typeof(resp), response_length) + 4317 sizeof(resp.response_length); 4318 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4319 if (err) 4320 goto err; 4321 } 4322 4323 return rwq_ind_table; 4324 4325 err: 4326 kfree(rwq_ind_table); 4327 return ERR_PTR(err); 4328 } 4329 4330 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4331 { 4332 kfree(ib_rwq_ind_tbl); 4333 return 0; 4334 } 4335 4336 struct mlx4_ib_drain_cqe { 4337 struct ib_cqe cqe; 4338 struct completion done; 4339 }; 4340 4341 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4342 { 4343 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4344 struct mlx4_ib_drain_cqe, 4345 cqe); 4346 4347 complete(&cqe->done); 4348 } 4349 4350 /* This function returns only once the drained WR was completed */ 4351 static void handle_drain_completion(struct ib_cq *cq, 4352 struct mlx4_ib_drain_cqe *sdrain, 4353 struct mlx4_ib_dev *dev) 4354 { 4355 struct mlx4_dev *mdev = dev->dev; 4356 4357 if (cq->poll_ctx == IB_POLL_DIRECT) { 4358 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4359 ib_process_cq_direct(cq, -1); 4360 return; 4361 } 4362 4363 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4364 struct mlx4_ib_cq *mcq = to_mcq(cq); 4365 bool triggered = false; 4366 unsigned long flags; 4367 4368 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4369 /* Make sure that the CQ handler won't run if wasn't run yet */ 4370 if (!mcq->mcq.reset_notify_added) 4371 mcq->mcq.reset_notify_added = 1; 4372 else 4373 triggered = true; 4374 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4375 4376 if (triggered) { 4377 /* Wait for any scheduled/running task to be ended */ 4378 switch (cq->poll_ctx) { 4379 case IB_POLL_SOFTIRQ: 4380 irq_poll_disable(&cq->iop); 4381 irq_poll_enable(&cq->iop); 4382 break; 4383 case IB_POLL_WORKQUEUE: 4384 cancel_work_sync(&cq->work); 4385 break; 4386 default: 4387 WARN_ON_ONCE(1); 4388 } 4389 } 4390 4391 /* Run the CQ handler - this makes sure that the drain WR will 4392 * be processed if wasn't processed yet. 4393 */ 4394 mcq->mcq.comp(&mcq->mcq); 4395 } 4396 4397 wait_for_completion(&sdrain->done); 4398 } 4399 4400 void mlx4_ib_drain_sq(struct ib_qp *qp) 4401 { 4402 struct ib_cq *cq = qp->send_cq; 4403 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4404 struct mlx4_ib_drain_cqe sdrain; 4405 const struct ib_send_wr *bad_swr; 4406 struct ib_rdma_wr swr = { 4407 .wr = { 4408 .next = NULL, 4409 { .wr_cqe = &sdrain.cqe, }, 4410 .opcode = IB_WR_RDMA_WRITE, 4411 }, 4412 }; 4413 int ret; 4414 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4415 struct mlx4_dev *mdev = dev->dev; 4416 4417 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4418 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4419 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4420 return; 4421 } 4422 4423 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4424 init_completion(&sdrain.done); 4425 4426 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4427 if (ret) { 4428 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4429 return; 4430 } 4431 4432 handle_drain_completion(cq, &sdrain, dev); 4433 } 4434 4435 void mlx4_ib_drain_rq(struct ib_qp *qp) 4436 { 4437 struct ib_cq *cq = qp->recv_cq; 4438 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4439 struct mlx4_ib_drain_cqe rdrain; 4440 struct ib_recv_wr rwr = {}; 4441 const struct ib_recv_wr *bad_rwr; 4442 int ret; 4443 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4444 struct mlx4_dev *mdev = dev->dev; 4445 4446 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4447 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4448 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4449 return; 4450 } 4451 4452 rwr.wr_cqe = &rdrain.cqe; 4453 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4454 init_completion(&rdrain.done); 4455 4456 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4457 if (ret) { 4458 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4459 return; 4460 } 4461 4462 handle_drain_completion(cq, &rdrain, dev); 4463 } 4464