1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/log2.h> 34 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_pack.h> 37 38 #include <linux/mlx4/qp.h> 39 40 #include "mlx4_ib.h" 41 #include "user.h" 42 43 enum { 44 MLX4_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f 50 }; 51 52 enum { 53 /* 54 * Largest possible UD header: send with GRH and immediate data. 55 */ 56 MLX4_IB_UD_HEADER_SIZE = 72 57 }; 58 59 struct mlx4_ib_sqp { 60 struct mlx4_ib_qp qp; 61 int pkey_index; 62 u32 qkey; 63 u32 send_psn; 64 struct ib_ud_header ud_header; 65 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 66 }; 67 68 enum { 69 MLX4_IB_MIN_SQ_STRIDE = 6 70 }; 71 72 static const __be32 mlx4_ib_opcode[] = { 73 [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND), 74 [IB_WR_LSO] = __constant_cpu_to_be32(MLX4_OPCODE_LSO), 75 [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM), 76 [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 77 [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 78 [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ), 79 [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 80 [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 81 }; 82 83 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 84 { 85 return container_of(mqp, struct mlx4_ib_sqp, qp); 86 } 87 88 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 89 { 90 return qp->mqp.qpn >= dev->dev->caps.sqp_start && 91 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3; 92 } 93 94 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 95 { 96 return qp->mqp.qpn >= dev->dev->caps.sqp_start && 97 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1; 98 } 99 100 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 101 { 102 return mlx4_buf_offset(&qp->buf, offset); 103 } 104 105 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 106 { 107 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 108 } 109 110 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 111 { 112 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 113 } 114 115 /* 116 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 117 * first four bytes of every 64 byte chunk with 118 * 0x7FFFFFF | (invalid_ownership_value << 31). 119 * 120 * When the max work request size is less than or equal to the WQE 121 * basic block size, as an optimization, we can stamp all WQEs with 122 * 0xffffffff, and skip the very first chunk of each WQE. 123 */ 124 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 125 { 126 __be32 *wqe; 127 int i; 128 int s; 129 int ind; 130 void *buf; 131 __be32 stamp; 132 133 s = roundup(size, 1U << qp->sq.wqe_shift); 134 if (qp->sq_max_wqes_per_wr > 1) { 135 for (i = 0; i < s; i += 64) { 136 ind = (i >> qp->sq.wqe_shift) + n; 137 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 138 cpu_to_be32(0xffffffff); 139 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 140 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 141 *wqe = stamp; 142 } 143 } else { 144 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 145 for (i = 64; i < s; i += 64) { 146 wqe = buf + i; 147 *wqe = cpu_to_be32(0xffffffff); 148 } 149 } 150 } 151 152 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 153 { 154 struct mlx4_wqe_ctrl_seg *ctrl; 155 struct mlx4_wqe_inline_seg *inl; 156 void *wqe; 157 int s; 158 159 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 160 s = sizeof(struct mlx4_wqe_ctrl_seg); 161 162 if (qp->ibqp.qp_type == IB_QPT_UD) { 163 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 164 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 165 memset(dgram, 0, sizeof *dgram); 166 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 167 s += sizeof(struct mlx4_wqe_datagram_seg); 168 } 169 170 /* Pad the remainder of the WQE with an inline data segment. */ 171 if (size > s) { 172 inl = wqe + s; 173 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 174 } 175 ctrl->srcrb_flags = 0; 176 ctrl->fence_size = size / 16; 177 /* 178 * Make sure descriptor is fully written before setting ownership bit 179 * (because HW can start executing as soon as we do). 180 */ 181 wmb(); 182 183 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 184 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 185 186 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 187 } 188 189 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 190 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 191 { 192 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 193 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 194 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 195 ind += s; 196 } 197 return ind; 198 } 199 200 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 201 { 202 struct ib_event event; 203 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 204 205 if (type == MLX4_EVENT_TYPE_PATH_MIG) 206 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 207 208 if (ibqp->event_handler) { 209 event.device = ibqp->device; 210 event.element.qp = ibqp; 211 switch (type) { 212 case MLX4_EVENT_TYPE_PATH_MIG: 213 event.event = IB_EVENT_PATH_MIG; 214 break; 215 case MLX4_EVENT_TYPE_COMM_EST: 216 event.event = IB_EVENT_COMM_EST; 217 break; 218 case MLX4_EVENT_TYPE_SQ_DRAINED: 219 event.event = IB_EVENT_SQ_DRAINED; 220 break; 221 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 222 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 223 break; 224 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 225 event.event = IB_EVENT_QP_FATAL; 226 break; 227 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 228 event.event = IB_EVENT_PATH_MIG_ERR; 229 break; 230 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 231 event.event = IB_EVENT_QP_REQ_ERR; 232 break; 233 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 234 event.event = IB_EVENT_QP_ACCESS_ERR; 235 break; 236 default: 237 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d " 238 "on QP %06x\n", type, qp->qpn); 239 return; 240 } 241 242 ibqp->event_handler(&event, ibqp->qp_context); 243 } 244 } 245 246 static int send_wqe_overhead(enum ib_qp_type type, u32 flags) 247 { 248 /* 249 * UD WQEs must have a datagram segment. 250 * RC and UC WQEs might have a remote address segment. 251 * MLX WQEs need two extra inline data segments (for the UD 252 * header and space for the ICRC). 253 */ 254 switch (type) { 255 case IB_QPT_UD: 256 return sizeof (struct mlx4_wqe_ctrl_seg) + 257 sizeof (struct mlx4_wqe_datagram_seg) + 258 ((flags & MLX4_IB_QP_LSO) ? 64 : 0); 259 case IB_QPT_UC: 260 return sizeof (struct mlx4_wqe_ctrl_seg) + 261 sizeof (struct mlx4_wqe_raddr_seg); 262 case IB_QPT_RC: 263 return sizeof (struct mlx4_wqe_ctrl_seg) + 264 sizeof (struct mlx4_wqe_atomic_seg) + 265 sizeof (struct mlx4_wqe_raddr_seg); 266 case IB_QPT_SMI: 267 case IB_QPT_GSI: 268 return sizeof (struct mlx4_wqe_ctrl_seg) + 269 ALIGN(MLX4_IB_UD_HEADER_SIZE + 270 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 271 MLX4_INLINE_ALIGN) * 272 sizeof (struct mlx4_wqe_inline_seg), 273 sizeof (struct mlx4_wqe_data_seg)) + 274 ALIGN(4 + 275 sizeof (struct mlx4_wqe_inline_seg), 276 sizeof (struct mlx4_wqe_data_seg)); 277 default: 278 return sizeof (struct mlx4_wqe_ctrl_seg); 279 } 280 } 281 282 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 283 int is_user, int has_srq, struct mlx4_ib_qp *qp) 284 { 285 /* Sanity check RQ size before proceeding */ 286 if (cap->max_recv_wr > dev->dev->caps.max_wqes || 287 cap->max_recv_sge > dev->dev->caps.max_rq_sg) 288 return -EINVAL; 289 290 if (has_srq) { 291 /* QPs attached to an SRQ should have no RQ */ 292 if (cap->max_recv_wr) 293 return -EINVAL; 294 295 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 296 } else { 297 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 298 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 299 return -EINVAL; 300 301 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 302 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 303 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 304 } 305 306 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 307 cap->max_recv_sge = qp->rq.max_gs; 308 309 return 0; 310 } 311 312 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 313 enum ib_qp_type type, struct mlx4_ib_qp *qp) 314 { 315 int s; 316 317 /* Sanity check SQ size before proceeding */ 318 if (cap->max_send_wr > dev->dev->caps.max_wqes || 319 cap->max_send_sge > dev->dev->caps.max_sq_sg || 320 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 321 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 322 return -EINVAL; 323 324 /* 325 * For MLX transport we need 2 extra S/G entries: 326 * one for the header and one for the checksum at the end 327 */ 328 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) && 329 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 330 return -EINVAL; 331 332 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 333 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 334 send_wqe_overhead(type, qp->flags); 335 336 if (s > dev->dev->caps.max_sq_desc_sz) 337 return -EINVAL; 338 339 /* 340 * Hermon supports shrinking WQEs, such that a single work 341 * request can include multiple units of 1 << wqe_shift. This 342 * way, work requests can differ in size, and do not have to 343 * be a power of 2 in size, saving memory and speeding up send 344 * WR posting. Unfortunately, if we do this then the 345 * wqe_index field in CQEs can't be used to look up the WR ID 346 * anymore, so we do this only if selective signaling is off. 347 * 348 * Further, on 32-bit platforms, we can't use vmap() to make 349 * the QP buffer virtually contigious. Thus we have to use 350 * constant-sized WRs to make sure a WR is always fully within 351 * a single page-sized chunk. 352 * 353 * Finally, we use NOP work requests to pad the end of the 354 * work queue, to avoid wrap-around in the middle of WR. We 355 * set NEC bit to avoid getting completions with error for 356 * these NOP WRs, but since NEC is only supported starting 357 * with firmware 2.2.232, we use constant-sized WRs for older 358 * firmware. 359 * 360 * And, since MLX QPs only support SEND, we use constant-sized 361 * WRs in this case. 362 * 363 * We look for the smallest value of wqe_shift such that the 364 * resulting number of wqes does not exceed device 365 * capabilities. 366 * 367 * We set WQE size to at least 64 bytes, this way stamping 368 * invalidates each WQE. 369 */ 370 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 371 qp->sq_signal_bits && BITS_PER_LONG == 64 && 372 type != IB_QPT_SMI && type != IB_QPT_GSI) 373 qp->sq.wqe_shift = ilog2(64); 374 else 375 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 376 377 for (;;) { 378 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 379 380 /* 381 * We need to leave 2 KB + 1 WR of headroom in the SQ to 382 * allow HW to prefetch. 383 */ 384 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 385 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 386 qp->sq_max_wqes_per_wr + 387 qp->sq_spare_wqes); 388 389 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 390 break; 391 392 if (qp->sq_max_wqes_per_wr <= 1) 393 return -EINVAL; 394 395 ++qp->sq.wqe_shift; 396 } 397 398 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 399 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 400 send_wqe_overhead(type, qp->flags)) / 401 sizeof (struct mlx4_wqe_data_seg); 402 403 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 404 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 405 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 406 qp->rq.offset = 0; 407 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 408 } else { 409 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 410 qp->sq.offset = 0; 411 } 412 413 cap->max_send_wr = qp->sq.max_post = 414 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 415 cap->max_send_sge = min(qp->sq.max_gs, 416 min(dev->dev->caps.max_sq_sg, 417 dev->dev->caps.max_rq_sg)); 418 /* We don't support inline sends for kernel QPs (yet) */ 419 cap->max_inline_data = 0; 420 421 return 0; 422 } 423 424 static int set_user_sq_size(struct mlx4_ib_dev *dev, 425 struct mlx4_ib_qp *qp, 426 struct mlx4_ib_create_qp *ucmd) 427 { 428 /* Sanity check SQ size before proceeding */ 429 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 430 ucmd->log_sq_stride > 431 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 432 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 433 return -EINVAL; 434 435 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 436 qp->sq.wqe_shift = ucmd->log_sq_stride; 437 438 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 439 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 440 441 return 0; 442 } 443 444 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 445 struct ib_qp_init_attr *init_attr, 446 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp) 447 { 448 int err; 449 450 mutex_init(&qp->mutex); 451 spin_lock_init(&qp->sq.lock); 452 spin_lock_init(&qp->rq.lock); 453 454 qp->state = IB_QPS_RESET; 455 qp->atomic_rd_en = 0; 456 qp->resp_depth = 0; 457 458 qp->rq.head = 0; 459 qp->rq.tail = 0; 460 qp->sq.head = 0; 461 qp->sq.tail = 0; 462 qp->sq_next_wqe = 0; 463 464 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 465 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 466 else 467 qp->sq_signal_bits = 0; 468 469 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp); 470 if (err) 471 goto err; 472 473 if (pd->uobject) { 474 struct mlx4_ib_create_qp ucmd; 475 476 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 477 err = -EFAULT; 478 goto err; 479 } 480 481 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 482 483 err = set_user_sq_size(dev, qp, &ucmd); 484 if (err) 485 goto err; 486 487 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 488 qp->buf_size, 0, 0); 489 if (IS_ERR(qp->umem)) { 490 err = PTR_ERR(qp->umem); 491 goto err; 492 } 493 494 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 495 ilog2(qp->umem->page_size), &qp->mtt); 496 if (err) 497 goto err_buf; 498 499 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 500 if (err) 501 goto err_mtt; 502 503 if (!init_attr->srq) { 504 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 505 ucmd.db_addr, &qp->db); 506 if (err) 507 goto err_mtt; 508 } 509 } else { 510 qp->sq_no_prefetch = 0; 511 512 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 513 qp->flags |= MLX4_IB_QP_LSO; 514 515 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp); 516 if (err) 517 goto err; 518 519 if (!init_attr->srq) { 520 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 521 if (err) 522 goto err; 523 524 *qp->db.db = 0; 525 } 526 527 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) { 528 err = -ENOMEM; 529 goto err_db; 530 } 531 532 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 533 &qp->mtt); 534 if (err) 535 goto err_buf; 536 537 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 538 if (err) 539 goto err_mtt; 540 541 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL); 542 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL); 543 544 if (!qp->sq.wrid || !qp->rq.wrid) { 545 err = -ENOMEM; 546 goto err_wrid; 547 } 548 } 549 550 err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp); 551 if (err) 552 goto err_wrid; 553 554 /* 555 * Hardware wants QPN written in big-endian order (after 556 * shifting) for send doorbell. Precompute this value to save 557 * a little bit when posting sends. 558 */ 559 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 560 561 qp->mqp.event = mlx4_ib_qp_event; 562 563 return 0; 564 565 err_wrid: 566 if (pd->uobject) { 567 if (!init_attr->srq) 568 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), 569 &qp->db); 570 } else { 571 kfree(qp->sq.wrid); 572 kfree(qp->rq.wrid); 573 } 574 575 err_mtt: 576 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 577 578 err_buf: 579 if (pd->uobject) 580 ib_umem_release(qp->umem); 581 else 582 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 583 584 err_db: 585 if (!pd->uobject && !init_attr->srq) 586 mlx4_db_free(dev->dev, &qp->db); 587 588 err: 589 return err; 590 } 591 592 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 593 { 594 switch (state) { 595 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 596 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 597 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 598 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 599 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 600 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 601 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 602 default: return -1; 603 } 604 } 605 606 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 607 { 608 if (send_cq == recv_cq) 609 spin_lock_irq(&send_cq->lock); 610 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 611 spin_lock_irq(&send_cq->lock); 612 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 613 } else { 614 spin_lock_irq(&recv_cq->lock); 615 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 616 } 617 } 618 619 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 620 { 621 if (send_cq == recv_cq) 622 spin_unlock_irq(&send_cq->lock); 623 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 624 spin_unlock(&recv_cq->lock); 625 spin_unlock_irq(&send_cq->lock); 626 } else { 627 spin_unlock(&send_cq->lock); 628 spin_unlock_irq(&recv_cq->lock); 629 } 630 } 631 632 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 633 int is_user) 634 { 635 struct mlx4_ib_cq *send_cq, *recv_cq; 636 637 if (qp->state != IB_QPS_RESET) 638 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 639 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 640 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n", 641 qp->mqp.qpn); 642 643 send_cq = to_mcq(qp->ibqp.send_cq); 644 recv_cq = to_mcq(qp->ibqp.recv_cq); 645 646 mlx4_ib_lock_cqs(send_cq, recv_cq); 647 648 if (!is_user) { 649 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 650 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 651 if (send_cq != recv_cq) 652 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 653 } 654 655 mlx4_qp_remove(dev->dev, &qp->mqp); 656 657 mlx4_ib_unlock_cqs(send_cq, recv_cq); 658 659 mlx4_qp_free(dev->dev, &qp->mqp); 660 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 661 662 if (is_user) { 663 if (!qp->ibqp.srq) 664 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), 665 &qp->db); 666 ib_umem_release(qp->umem); 667 } else { 668 kfree(qp->sq.wrid); 669 kfree(qp->rq.wrid); 670 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 671 if (!qp->ibqp.srq) 672 mlx4_db_free(dev->dev, &qp->db); 673 } 674 } 675 676 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 677 struct ib_qp_init_attr *init_attr, 678 struct ib_udata *udata) 679 { 680 struct mlx4_ib_dev *dev = to_mdev(pd->device); 681 struct mlx4_ib_sqp *sqp; 682 struct mlx4_ib_qp *qp; 683 int err; 684 685 /* We only support LSO, and only for kernel UD QPs. */ 686 if (init_attr->create_flags & ~IB_QP_CREATE_IPOIB_UD_LSO) 687 return ERR_PTR(-EINVAL); 688 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO && 689 (pd->uobject || init_attr->qp_type != IB_QPT_UD)) 690 return ERR_PTR(-EINVAL); 691 692 switch (init_attr->qp_type) { 693 case IB_QPT_RC: 694 case IB_QPT_UC: 695 case IB_QPT_UD: 696 { 697 qp = kmalloc(sizeof *qp, GFP_KERNEL); 698 if (!qp) 699 return ERR_PTR(-ENOMEM); 700 701 err = create_qp_common(dev, pd, init_attr, udata, 0, qp); 702 if (err) { 703 kfree(qp); 704 return ERR_PTR(err); 705 } 706 707 qp->ibqp.qp_num = qp->mqp.qpn; 708 709 break; 710 } 711 case IB_QPT_SMI: 712 case IB_QPT_GSI: 713 { 714 /* Userspace is not allowed to create special QPs: */ 715 if (pd->uobject) 716 return ERR_PTR(-EINVAL); 717 718 sqp = kmalloc(sizeof *sqp, GFP_KERNEL); 719 if (!sqp) 720 return ERR_PTR(-ENOMEM); 721 722 qp = &sqp->qp; 723 724 err = create_qp_common(dev, pd, init_attr, udata, 725 dev->dev->caps.sqp_start + 726 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) + 727 init_attr->port_num - 1, 728 qp); 729 if (err) { 730 kfree(sqp); 731 return ERR_PTR(err); 732 } 733 734 qp->port = init_attr->port_num; 735 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1; 736 737 break; 738 } 739 default: 740 /* Don't support raw QPs */ 741 return ERR_PTR(-EINVAL); 742 } 743 744 return &qp->ibqp; 745 } 746 747 int mlx4_ib_destroy_qp(struct ib_qp *qp) 748 { 749 struct mlx4_ib_dev *dev = to_mdev(qp->device); 750 struct mlx4_ib_qp *mqp = to_mqp(qp); 751 752 if (is_qp0(dev, mqp)) 753 mlx4_CLOSE_PORT(dev->dev, mqp->port); 754 755 destroy_qp_common(dev, mqp, !!qp->pd->uobject); 756 757 if (is_sqp(dev, mqp)) 758 kfree(to_msqp(mqp)); 759 else 760 kfree(mqp); 761 762 return 0; 763 } 764 765 static int to_mlx4_st(enum ib_qp_type type) 766 { 767 switch (type) { 768 case IB_QPT_RC: return MLX4_QP_ST_RC; 769 case IB_QPT_UC: return MLX4_QP_ST_UC; 770 case IB_QPT_UD: return MLX4_QP_ST_UD; 771 case IB_QPT_SMI: 772 case IB_QPT_GSI: return MLX4_QP_ST_MLX; 773 default: return -1; 774 } 775 } 776 777 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 778 int attr_mask) 779 { 780 u8 dest_rd_atomic; 781 u32 access_flags; 782 u32 hw_access_flags = 0; 783 784 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 785 dest_rd_atomic = attr->max_dest_rd_atomic; 786 else 787 dest_rd_atomic = qp->resp_depth; 788 789 if (attr_mask & IB_QP_ACCESS_FLAGS) 790 access_flags = attr->qp_access_flags; 791 else 792 access_flags = qp->atomic_rd_en; 793 794 if (!dest_rd_atomic) 795 access_flags &= IB_ACCESS_REMOTE_WRITE; 796 797 if (access_flags & IB_ACCESS_REMOTE_READ) 798 hw_access_flags |= MLX4_QP_BIT_RRE; 799 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 800 hw_access_flags |= MLX4_QP_BIT_RAE; 801 if (access_flags & IB_ACCESS_REMOTE_WRITE) 802 hw_access_flags |= MLX4_QP_BIT_RWE; 803 804 return cpu_to_be32(hw_access_flags); 805 } 806 807 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 808 int attr_mask) 809 { 810 if (attr_mask & IB_QP_PKEY_INDEX) 811 sqp->pkey_index = attr->pkey_index; 812 if (attr_mask & IB_QP_QKEY) 813 sqp->qkey = attr->qkey; 814 if (attr_mask & IB_QP_SQ_PSN) 815 sqp->send_psn = attr->sq_psn; 816 } 817 818 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 819 { 820 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 821 } 822 823 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 824 struct mlx4_qp_path *path, u8 port) 825 { 826 path->grh_mylmc = ah->src_path_bits & 0x7f; 827 path->rlid = cpu_to_be16(ah->dlid); 828 if (ah->static_rate) { 829 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET; 830 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 831 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 832 --path->static_rate; 833 } else 834 path->static_rate = 0; 835 path->counter_index = 0xff; 836 837 if (ah->ah_flags & IB_AH_GRH) { 838 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) { 839 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n", 840 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1); 841 return -1; 842 } 843 844 path->grh_mylmc |= 1 << 7; 845 path->mgid_index = ah->grh.sgid_index; 846 path->hop_limit = ah->grh.hop_limit; 847 path->tclass_flowlabel = 848 cpu_to_be32((ah->grh.traffic_class << 20) | 849 (ah->grh.flow_label)); 850 memcpy(path->rgid, ah->grh.dgid.raw, 16); 851 } 852 853 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 854 ((port - 1) << 6) | ((ah->sl & 0xf) << 2); 855 856 return 0; 857 } 858 859 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 860 const struct ib_qp_attr *attr, int attr_mask, 861 enum ib_qp_state cur_state, enum ib_qp_state new_state) 862 { 863 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 864 struct mlx4_ib_qp *qp = to_mqp(ibqp); 865 struct mlx4_qp_context *context; 866 enum mlx4_qp_optpar optpar = 0; 867 int sqd_event; 868 int err = -EINVAL; 869 870 context = kzalloc(sizeof *context, GFP_KERNEL); 871 if (!context) 872 return -ENOMEM; 873 874 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 875 (to_mlx4_st(ibqp->qp_type) << 16)); 876 context->flags |= cpu_to_be32(1 << 8); /* DE? */ 877 878 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 879 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 880 else { 881 optpar |= MLX4_QP_OPTPAR_PM_STATE; 882 switch (attr->path_mig_state) { 883 case IB_MIG_MIGRATED: 884 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 885 break; 886 case IB_MIG_REARM: 887 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 888 break; 889 case IB_MIG_ARMED: 890 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 891 break; 892 } 893 } 894 895 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 896 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 897 else if (ibqp->qp_type == IB_QPT_UD) { 898 if (qp->flags & MLX4_IB_QP_LSO) 899 context->mtu_msgmax = (IB_MTU_4096 << 5) | 900 ilog2(dev->dev->caps.max_gso_sz); 901 else 902 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 903 } else if (attr_mask & IB_QP_PATH_MTU) { 904 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 905 printk(KERN_ERR "path MTU (%u) is invalid\n", 906 attr->path_mtu); 907 goto out; 908 } 909 context->mtu_msgmax = (attr->path_mtu << 5) | 31; 910 } 911 912 if (qp->rq.wqe_cnt) 913 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 914 context->rq_size_stride |= qp->rq.wqe_shift - 4; 915 916 if (qp->sq.wqe_cnt) 917 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 918 context->sq_size_stride |= qp->sq.wqe_shift - 4; 919 920 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 921 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 922 923 if (qp->ibqp.uobject) 924 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index); 925 else 926 context->usr_page = cpu_to_be32(dev->priv_uar.index); 927 928 if (attr_mask & IB_QP_DEST_QPN) 929 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 930 931 if (attr_mask & IB_QP_PORT) { 932 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 933 !(attr_mask & IB_QP_AV)) { 934 mlx4_set_sched(&context->pri_path, attr->port_num); 935 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 936 } 937 } 938 939 if (attr_mask & IB_QP_PKEY_INDEX) { 940 context->pri_path.pkey_index = attr->pkey_index; 941 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 942 } 943 944 if (attr_mask & IB_QP_AV) { 945 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path, 946 attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) 947 goto out; 948 949 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 950 MLX4_QP_OPTPAR_SCHED_QUEUE); 951 } 952 953 if (attr_mask & IB_QP_TIMEOUT) { 954 context->pri_path.ackto = attr->timeout << 3; 955 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 956 } 957 958 if (attr_mask & IB_QP_ALT_PATH) { 959 if (attr->alt_port_num == 0 || 960 attr->alt_port_num > dev->dev->caps.num_ports) 961 goto out; 962 963 if (attr->alt_pkey_index >= 964 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 965 goto out; 966 967 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path, 968 attr->alt_port_num)) 969 goto out; 970 971 context->alt_path.pkey_index = attr->alt_pkey_index; 972 context->alt_path.ackto = attr->alt_timeout << 3; 973 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 974 } 975 976 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn); 977 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 978 979 if (attr_mask & IB_QP_RNR_RETRY) { 980 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 981 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 982 } 983 984 if (attr_mask & IB_QP_RETRY_CNT) { 985 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 986 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 987 } 988 989 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 990 if (attr->max_rd_atomic) 991 context->params1 |= 992 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 993 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 994 } 995 996 if (attr_mask & IB_QP_SQ_PSN) 997 context->next_send_psn = cpu_to_be32(attr->sq_psn); 998 999 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn); 1000 1001 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1002 if (attr->max_dest_rd_atomic) 1003 context->params2 |= 1004 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1005 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1006 } 1007 1008 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1009 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1010 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1011 } 1012 1013 if (ibqp->srq) 1014 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1015 1016 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1017 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1018 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1019 } 1020 if (attr_mask & IB_QP_RQ_PSN) 1021 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1022 1023 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn); 1024 1025 if (attr_mask & IB_QP_QKEY) { 1026 context->qkey = cpu_to_be32(attr->qkey); 1027 optpar |= MLX4_QP_OPTPAR_Q_KEY; 1028 } 1029 1030 if (ibqp->srq) 1031 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 1032 1033 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1034 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1035 1036 if (cur_state == IB_QPS_INIT && 1037 new_state == IB_QPS_RTR && 1038 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 1039 ibqp->qp_type == IB_QPT_UD)) { 1040 context->pri_path.sched_queue = (qp->port - 1) << 6; 1041 if (is_qp0(dev, qp)) 1042 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 1043 else 1044 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 1045 } 1046 1047 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1048 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1049 sqd_event = 1; 1050 else 1051 sqd_event = 0; 1052 1053 /* 1054 * Before passing a kernel QP to the HW, make sure that the 1055 * ownership bits of the send queue are set and the SQ 1056 * headroom is stamped so that the hardware doesn't start 1057 * processing stale work requests. 1058 */ 1059 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1060 struct mlx4_wqe_ctrl_seg *ctrl; 1061 int i; 1062 1063 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 1064 ctrl = get_send_wqe(qp, i); 1065 ctrl->owner_opcode = cpu_to_be32(1 << 31); 1066 1067 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 1068 } 1069 } 1070 1071 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 1072 to_mlx4_state(new_state), context, optpar, 1073 sqd_event, &qp->mqp); 1074 if (err) 1075 goto out; 1076 1077 qp->state = new_state; 1078 1079 if (attr_mask & IB_QP_ACCESS_FLAGS) 1080 qp->atomic_rd_en = attr->qp_access_flags; 1081 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1082 qp->resp_depth = attr->max_dest_rd_atomic; 1083 if (attr_mask & IB_QP_PORT) 1084 qp->port = attr->port_num; 1085 if (attr_mask & IB_QP_ALT_PATH) 1086 qp->alt_port = attr->alt_port_num; 1087 1088 if (is_sqp(dev, qp)) 1089 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 1090 1091 /* 1092 * If we moved QP0 to RTR, bring the IB link up; if we moved 1093 * QP0 to RESET or ERROR, bring the link back down. 1094 */ 1095 if (is_qp0(dev, qp)) { 1096 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 1097 if (mlx4_INIT_PORT(dev->dev, qp->port)) 1098 printk(KERN_WARNING "INIT_PORT failed for port %d\n", 1099 qp->port); 1100 1101 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 1102 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 1103 mlx4_CLOSE_PORT(dev->dev, qp->port); 1104 } 1105 1106 /* 1107 * If we moved a kernel QP to RESET, clean up all old CQ 1108 * entries and reinitialize the QP. 1109 */ 1110 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 1111 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn, 1112 ibqp->srq ? to_msrq(ibqp->srq): NULL); 1113 if (ibqp->send_cq != ibqp->recv_cq) 1114 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL); 1115 1116 qp->rq.head = 0; 1117 qp->rq.tail = 0; 1118 qp->sq.head = 0; 1119 qp->sq.tail = 0; 1120 qp->sq_next_wqe = 0; 1121 if (!ibqp->srq) 1122 *qp->db.db = 0; 1123 } 1124 1125 out: 1126 kfree(context); 1127 return err; 1128 } 1129 1130 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 }; 1131 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = { 1132 [IB_QPT_UD] = (IB_QP_PKEY_INDEX | 1133 IB_QP_PORT | 1134 IB_QP_QKEY), 1135 [IB_QPT_UC] = (IB_QP_PKEY_INDEX | 1136 IB_QP_PORT | 1137 IB_QP_ACCESS_FLAGS), 1138 [IB_QPT_RC] = (IB_QP_PKEY_INDEX | 1139 IB_QP_PORT | 1140 IB_QP_ACCESS_FLAGS), 1141 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX | 1142 IB_QP_QKEY), 1143 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX | 1144 IB_QP_QKEY), 1145 }; 1146 1147 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1148 int attr_mask, struct ib_udata *udata) 1149 { 1150 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1151 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1152 enum ib_qp_state cur_state, new_state; 1153 int err = -EINVAL; 1154 1155 mutex_lock(&qp->mutex); 1156 1157 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 1158 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1159 1160 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) 1161 goto out; 1162 1163 if ((attr_mask & IB_QP_PORT) && 1164 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) { 1165 goto out; 1166 } 1167 1168 if (attr_mask & IB_QP_PKEY_INDEX) { 1169 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1170 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) 1171 goto out; 1172 } 1173 1174 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1175 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 1176 goto out; 1177 } 1178 1179 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1180 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 1181 goto out; 1182 } 1183 1184 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1185 err = 0; 1186 goto out; 1187 } 1188 1189 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) { 1190 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr, 1191 mlx4_ib_qp_attr_mask_table[ibqp->qp_type], 1192 IB_QPS_RESET, IB_QPS_INIT); 1193 if (err) 1194 goto out; 1195 cur_state = IB_QPS_INIT; 1196 } 1197 1198 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 1199 1200 out: 1201 mutex_unlock(&qp->mutex); 1202 return err; 1203 } 1204 1205 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, 1206 void *wqe, unsigned *mlx_seg_len) 1207 { 1208 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev; 1209 struct mlx4_wqe_mlx_seg *mlx = wqe; 1210 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 1211 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 1212 u16 pkey; 1213 int send_size; 1214 int header_size; 1215 int spc; 1216 int i; 1217 1218 send_size = 0; 1219 for (i = 0; i < wr->num_sge; ++i) 1220 send_size += wr->sg_list[i].length; 1221 1222 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header); 1223 1224 sqp->ud_header.lrh.service_level = 1225 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28; 1226 sqp->ud_header.lrh.destination_lid = ah->av.dlid; 1227 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f); 1228 if (mlx4_ib_ah_grh_present(ah)) { 1229 sqp->ud_header.grh.traffic_class = 1230 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff; 1231 sqp->ud_header.grh.flow_label = 1232 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 1233 sqp->ud_header.grh.hop_limit = ah->av.hop_limit; 1234 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24, 1235 ah->av.gid_index, &sqp->ud_header.grh.source_gid); 1236 memcpy(sqp->ud_header.grh.destination_gid.raw, 1237 ah->av.dgid, 16); 1238 } 1239 1240 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1241 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 1242 (sqp->ud_header.lrh.destination_lid == 1243 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 1244 (sqp->ud_header.lrh.service_level << 8)); 1245 mlx->rlid = sqp->ud_header.lrh.destination_lid; 1246 1247 switch (wr->opcode) { 1248 case IB_WR_SEND: 1249 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1250 sqp->ud_header.immediate_present = 0; 1251 break; 1252 case IB_WR_SEND_WITH_IMM: 1253 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1254 sqp->ud_header.immediate_present = 1; 1255 sqp->ud_header.immediate_data = wr->ex.imm_data; 1256 break; 1257 default: 1258 return -EINVAL; 1259 } 1260 1261 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 1262 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 1263 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 1264 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 1265 if (!sqp->qp.ibqp.qp_num) 1266 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 1267 else 1268 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey); 1269 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 1270 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1271 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 1272 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 1273 sqp->qkey : wr->wr.ud.remote_qkey); 1274 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 1275 1276 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 1277 1278 if (0) { 1279 printk(KERN_ERR "built UD header of size %d:\n", header_size); 1280 for (i = 0; i < header_size / 4; ++i) { 1281 if (i % 8 == 0) 1282 printk(" [%02x] ", i * 4); 1283 printk(" %08x", 1284 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 1285 if ((i + 1) % 8 == 0) 1286 printk("\n"); 1287 } 1288 printk("\n"); 1289 } 1290 1291 /* 1292 * Inline data segments may not cross a 64 byte boundary. If 1293 * our UD header is bigger than the space available up to the 1294 * next 64 byte boundary in the WQE, use two inline data 1295 * segments to hold the UD header. 1296 */ 1297 spc = MLX4_INLINE_ALIGN - 1298 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 1299 if (header_size <= spc) { 1300 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 1301 memcpy(inl + 1, sqp->header_buf, header_size); 1302 i = 1; 1303 } else { 1304 inl->byte_count = cpu_to_be32(1 << 31 | spc); 1305 memcpy(inl + 1, sqp->header_buf, spc); 1306 1307 inl = (void *) (inl + 1) + spc; 1308 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 1309 /* 1310 * Need a barrier here to make sure all the data is 1311 * visible before the byte_count field is set. 1312 * Otherwise the HCA prefetcher could grab the 64-byte 1313 * chunk with this inline segment and get a valid (!= 1314 * 0xffffffff) byte count but stale data, and end up 1315 * generating a packet with bad headers. 1316 * 1317 * The first inline segment's byte_count field doesn't 1318 * need a barrier, because it comes after a 1319 * control/MLX segment and therefore is at an offset 1320 * of 16 mod 64. 1321 */ 1322 wmb(); 1323 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 1324 i = 2; 1325 } 1326 1327 *mlx_seg_len = 1328 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 1329 return 0; 1330 } 1331 1332 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 1333 { 1334 unsigned cur; 1335 struct mlx4_ib_cq *cq; 1336 1337 cur = wq->head - wq->tail; 1338 if (likely(cur + nreq < wq->max_post)) 1339 return 0; 1340 1341 cq = to_mcq(ib_cq); 1342 spin_lock(&cq->lock); 1343 cur = wq->head - wq->tail; 1344 spin_unlock(&cq->lock); 1345 1346 return cur + nreq >= wq->max_post; 1347 } 1348 1349 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 1350 u64 remote_addr, u32 rkey) 1351 { 1352 rseg->raddr = cpu_to_be64(remote_addr); 1353 rseg->rkey = cpu_to_be32(rkey); 1354 rseg->reserved = 0; 1355 } 1356 1357 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr) 1358 { 1359 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 1360 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 1361 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 1362 } else { 1363 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 1364 aseg->compare = 0; 1365 } 1366 1367 } 1368 1369 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 1370 struct ib_send_wr *wr) 1371 { 1372 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); 1373 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1374 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1375 } 1376 1377 static void set_mlx_icrc_seg(void *dseg) 1378 { 1379 u32 *t = dseg; 1380 struct mlx4_wqe_inline_seg *iseg = dseg; 1381 1382 t[1] = 0; 1383 1384 /* 1385 * Need a barrier here before writing the byte_count field to 1386 * make sure that all the data is visible before the 1387 * byte_count field is set. Otherwise, if the segment begins 1388 * a new cacheline, the HCA prefetcher could grab the 64-byte 1389 * chunk and get a valid (!= * 0xffffffff) byte count but 1390 * stale data, and end up sending the wrong data. 1391 */ 1392 wmb(); 1393 1394 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 1395 } 1396 1397 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 1398 { 1399 dseg->lkey = cpu_to_be32(sg->lkey); 1400 dseg->addr = cpu_to_be64(sg->addr); 1401 1402 /* 1403 * Need a barrier here before writing the byte_count field to 1404 * make sure that all the data is visible before the 1405 * byte_count field is set. Otherwise, if the segment begins 1406 * a new cacheline, the HCA prefetcher could grab the 64-byte 1407 * chunk and get a valid (!= * 0xffffffff) byte count but 1408 * stale data, and end up sending the wrong data. 1409 */ 1410 wmb(); 1411 1412 dseg->byte_count = cpu_to_be32(sg->length); 1413 } 1414 1415 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 1416 { 1417 dseg->byte_count = cpu_to_be32(sg->length); 1418 dseg->lkey = cpu_to_be32(sg->lkey); 1419 dseg->addr = cpu_to_be64(sg->addr); 1420 } 1421 1422 static int build_lso_seg(struct mlx4_lso_seg *wqe, struct ib_send_wr *wr, 1423 struct mlx4_ib_qp *qp, unsigned *lso_seg_len) 1424 { 1425 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16); 1426 1427 /* 1428 * This is a temporary limitation and will be removed in 1429 * a forthcoming FW release: 1430 */ 1431 if (unlikely(halign > 64)) 1432 return -EINVAL; 1433 1434 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 1435 wr->num_sge > qp->sq.max_gs - (halign >> 4))) 1436 return -EINVAL; 1437 1438 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen); 1439 1440 /* make sure LSO header is written before overwriting stamping */ 1441 wmb(); 1442 1443 wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 | 1444 wr->wr.ud.hlen); 1445 1446 *lso_seg_len = halign; 1447 return 0; 1448 } 1449 1450 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1451 struct ib_send_wr **bad_wr) 1452 { 1453 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1454 void *wqe; 1455 struct mlx4_wqe_ctrl_seg *ctrl; 1456 struct mlx4_wqe_data_seg *dseg; 1457 unsigned long flags; 1458 int nreq; 1459 int err = 0; 1460 unsigned ind; 1461 int uninitialized_var(stamp); 1462 int uninitialized_var(size); 1463 unsigned uninitialized_var(seglen); 1464 int i; 1465 1466 spin_lock_irqsave(&qp->sq.lock, flags); 1467 1468 ind = qp->sq_next_wqe; 1469 1470 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1471 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 1472 err = -ENOMEM; 1473 *bad_wr = wr; 1474 goto out; 1475 } 1476 1477 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 1478 err = -EINVAL; 1479 *bad_wr = wr; 1480 goto out; 1481 } 1482 1483 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 1484 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 1485 1486 ctrl->srcrb_flags = 1487 (wr->send_flags & IB_SEND_SIGNALED ? 1488 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 1489 (wr->send_flags & IB_SEND_SOLICITED ? 1490 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 1491 ((wr->send_flags & IB_SEND_IP_CSUM) ? 1492 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 1493 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 1494 qp->sq_signal_bits; 1495 1496 if (wr->opcode == IB_WR_SEND_WITH_IMM || 1497 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) 1498 ctrl->imm = wr->ex.imm_data; 1499 else 1500 ctrl->imm = 0; 1501 1502 wqe += sizeof *ctrl; 1503 size = sizeof *ctrl / 16; 1504 1505 switch (ibqp->qp_type) { 1506 case IB_QPT_RC: 1507 case IB_QPT_UC: 1508 switch (wr->opcode) { 1509 case IB_WR_ATOMIC_CMP_AND_SWP: 1510 case IB_WR_ATOMIC_FETCH_AND_ADD: 1511 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 1512 wr->wr.atomic.rkey); 1513 wqe += sizeof (struct mlx4_wqe_raddr_seg); 1514 1515 set_atomic_seg(wqe, wr); 1516 wqe += sizeof (struct mlx4_wqe_atomic_seg); 1517 1518 size += (sizeof (struct mlx4_wqe_raddr_seg) + 1519 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 1520 1521 break; 1522 1523 case IB_WR_RDMA_READ: 1524 case IB_WR_RDMA_WRITE: 1525 case IB_WR_RDMA_WRITE_WITH_IMM: 1526 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 1527 wr->wr.rdma.rkey); 1528 wqe += sizeof (struct mlx4_wqe_raddr_seg); 1529 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 1530 break; 1531 1532 default: 1533 /* No extra segments required for sends */ 1534 break; 1535 } 1536 break; 1537 1538 case IB_QPT_UD: 1539 set_datagram_seg(wqe, wr); 1540 wqe += sizeof (struct mlx4_wqe_datagram_seg); 1541 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 1542 1543 if (wr->opcode == IB_WR_LSO) { 1544 err = build_lso_seg(wqe, wr, qp, &seglen); 1545 if (unlikely(err)) { 1546 *bad_wr = wr; 1547 goto out; 1548 } 1549 wqe += seglen; 1550 size += seglen / 16; 1551 } 1552 break; 1553 1554 case IB_QPT_SMI: 1555 case IB_QPT_GSI: 1556 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen); 1557 if (unlikely(err)) { 1558 *bad_wr = wr; 1559 goto out; 1560 } 1561 wqe += seglen; 1562 size += seglen / 16; 1563 break; 1564 1565 default: 1566 break; 1567 } 1568 1569 /* 1570 * Write data segments in reverse order, so as to 1571 * overwrite cacheline stamp last within each 1572 * cacheline. This avoids issues with WQE 1573 * prefetching. 1574 */ 1575 1576 dseg = wqe; 1577 dseg += wr->num_sge - 1; 1578 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 1579 1580 /* Add one more inline data segment for ICRC for MLX sends */ 1581 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI || 1582 qp->ibqp.qp_type == IB_QPT_GSI)) { 1583 set_mlx_icrc_seg(dseg + 1); 1584 size += sizeof (struct mlx4_wqe_data_seg) / 16; 1585 } 1586 1587 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 1588 set_data_seg(dseg, wr->sg_list + i); 1589 1590 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 1591 MLX4_WQE_CTRL_FENCE : 0) | size; 1592 1593 /* 1594 * Make sure descriptor is fully written before 1595 * setting ownership bit (because HW can start 1596 * executing as soon as we do). 1597 */ 1598 wmb(); 1599 1600 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 1601 err = -EINVAL; 1602 goto out; 1603 } 1604 1605 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 1606 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 1607 1608 stamp = ind + qp->sq_spare_wqes; 1609 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 1610 1611 /* 1612 * We can improve latency by not stamping the last 1613 * send queue WQE until after ringing the doorbell, so 1614 * only stamp here if there are still more WQEs to post. 1615 * 1616 * Same optimization applies to padding with NOP wqe 1617 * in case of WQE shrinking (used to prevent wrap-around 1618 * in the middle of WR). 1619 */ 1620 if (wr->next) { 1621 stamp_send_wqe(qp, stamp, size * 16); 1622 ind = pad_wraparound(qp, ind); 1623 } 1624 1625 } 1626 1627 out: 1628 if (likely(nreq)) { 1629 qp->sq.head += nreq; 1630 1631 /* 1632 * Make sure that descriptors are written before 1633 * doorbell record. 1634 */ 1635 wmb(); 1636 1637 writel(qp->doorbell_qpn, 1638 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 1639 1640 /* 1641 * Make sure doorbells don't leak out of SQ spinlock 1642 * and reach the HCA out of order. 1643 */ 1644 mmiowb(); 1645 1646 stamp_send_wqe(qp, stamp, size * 16); 1647 1648 ind = pad_wraparound(qp, ind); 1649 qp->sq_next_wqe = ind; 1650 } 1651 1652 spin_unlock_irqrestore(&qp->sq.lock, flags); 1653 1654 return err; 1655 } 1656 1657 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1658 struct ib_recv_wr **bad_wr) 1659 { 1660 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1661 struct mlx4_wqe_data_seg *scat; 1662 unsigned long flags; 1663 int err = 0; 1664 int nreq; 1665 int ind; 1666 int i; 1667 1668 spin_lock_irqsave(&qp->rq.lock, flags); 1669 1670 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 1671 1672 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1673 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) { 1674 err = -ENOMEM; 1675 *bad_wr = wr; 1676 goto out; 1677 } 1678 1679 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 1680 err = -EINVAL; 1681 *bad_wr = wr; 1682 goto out; 1683 } 1684 1685 scat = get_recv_wqe(qp, ind); 1686 1687 for (i = 0; i < wr->num_sge; ++i) 1688 __set_data_seg(scat + i, wr->sg_list + i); 1689 1690 if (i < qp->rq.max_gs) { 1691 scat[i].byte_count = 0; 1692 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 1693 scat[i].addr = 0; 1694 } 1695 1696 qp->rq.wrid[ind] = wr->wr_id; 1697 1698 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 1699 } 1700 1701 out: 1702 if (likely(nreq)) { 1703 qp->rq.head += nreq; 1704 1705 /* 1706 * Make sure that descriptors are written before 1707 * doorbell record. 1708 */ 1709 wmb(); 1710 1711 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 1712 } 1713 1714 spin_unlock_irqrestore(&qp->rq.lock, flags); 1715 1716 return err; 1717 } 1718 1719 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 1720 { 1721 switch (mlx4_state) { 1722 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 1723 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 1724 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 1725 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 1726 case MLX4_QP_STATE_SQ_DRAINING: 1727 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 1728 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 1729 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 1730 default: return -1; 1731 } 1732 } 1733 1734 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 1735 { 1736 switch (mlx4_mig_state) { 1737 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 1738 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 1739 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 1740 default: return -1; 1741 } 1742 } 1743 1744 static int to_ib_qp_access_flags(int mlx4_flags) 1745 { 1746 int ib_flags = 0; 1747 1748 if (mlx4_flags & MLX4_QP_BIT_RRE) 1749 ib_flags |= IB_ACCESS_REMOTE_READ; 1750 if (mlx4_flags & MLX4_QP_BIT_RWE) 1751 ib_flags |= IB_ACCESS_REMOTE_WRITE; 1752 if (mlx4_flags & MLX4_QP_BIT_RAE) 1753 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 1754 1755 return ib_flags; 1756 } 1757 1758 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr, 1759 struct mlx4_qp_path *path) 1760 { 1761 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 1762 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; 1763 1764 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 1765 return; 1766 1767 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 1768 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; 1769 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; 1770 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 1771 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 1772 if (ib_ah_attr->ah_flags) { 1773 ib_ah_attr->grh.sgid_index = path->mgid_index; 1774 ib_ah_attr->grh.hop_limit = path->hop_limit; 1775 ib_ah_attr->grh.traffic_class = 1776 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 1777 ib_ah_attr->grh.flow_label = 1778 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 1779 memcpy(ib_ah_attr->grh.dgid.raw, 1780 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 1781 } 1782 } 1783 1784 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1785 struct ib_qp_init_attr *qp_init_attr) 1786 { 1787 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1788 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1789 struct mlx4_qp_context context; 1790 int mlx4_state; 1791 int err = 0; 1792 1793 mutex_lock(&qp->mutex); 1794 1795 if (qp->state == IB_QPS_RESET) { 1796 qp_attr->qp_state = IB_QPS_RESET; 1797 goto done; 1798 } 1799 1800 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 1801 if (err) { 1802 err = -EINVAL; 1803 goto out; 1804 } 1805 1806 mlx4_state = be32_to_cpu(context.flags) >> 28; 1807 1808 qp->state = to_ib_qp_state(mlx4_state); 1809 qp_attr->qp_state = qp->state; 1810 qp_attr->path_mtu = context.mtu_msgmax >> 5; 1811 qp_attr->path_mig_state = 1812 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 1813 qp_attr->qkey = be32_to_cpu(context.qkey); 1814 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 1815 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 1816 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 1817 qp_attr->qp_access_flags = 1818 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 1819 1820 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 1821 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path); 1822 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path); 1823 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 1824 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 1825 } 1826 1827 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 1828 if (qp_attr->qp_state == IB_QPS_INIT) 1829 qp_attr->port_num = qp->port; 1830 else 1831 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 1832 1833 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 1834 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 1835 1836 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 1837 1838 qp_attr->max_dest_rd_atomic = 1839 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 1840 qp_attr->min_rnr_timer = 1841 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 1842 qp_attr->timeout = context.pri_path.ackto >> 3; 1843 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 1844 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 1845 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 1846 1847 done: 1848 qp_attr->cur_qp_state = qp_attr->qp_state; 1849 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 1850 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 1851 1852 if (!ibqp->uobject) { 1853 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 1854 qp_attr->cap.max_send_sge = qp->sq.max_gs; 1855 } else { 1856 qp_attr->cap.max_send_wr = 0; 1857 qp_attr->cap.max_send_sge = 0; 1858 } 1859 1860 /* 1861 * We don't support inline sends for kernel QPs (yet), and we 1862 * don't know what userspace's value should be. 1863 */ 1864 qp_attr->cap.max_inline_data = 0; 1865 1866 qp_init_attr->cap = qp_attr->cap; 1867 1868 out: 1869 mutex_unlock(&qp->mutex); 1870 return err; 1871 } 1872 1873