1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 45 #include <linux/mlx4/driver.h> 46 #include <linux/mlx4/qp.h> 47 48 #include "mlx4_ib.h" 49 #include <rdma/mlx4-abi.h> 50 51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 52 struct mlx4_ib_cq *recv_cq); 53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 54 struct mlx4_ib_cq *recv_cq); 55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state); 56 57 enum { 58 MLX4_IB_ACK_REQ_FREQ = 8, 59 }; 60 61 enum { 62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 64 MLX4_IB_LINK_TYPE_IB = 0, 65 MLX4_IB_LINK_TYPE_ETH = 1 66 }; 67 68 enum { 69 /* 70 * Largest possible UD header: send with GRH and immediate 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 72 * tag. (LRH would only use 8 bytes, so Ethernet is the 73 * biggest case) 74 */ 75 MLX4_IB_UD_HEADER_SIZE = 82, 76 MLX4_IB_LSO_HEADER_SPARE = 128, 77 }; 78 79 struct mlx4_ib_sqp { 80 struct mlx4_ib_qp qp; 81 int pkey_index; 82 u32 qkey; 83 u32 send_psn; 84 struct ib_ud_header ud_header; 85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 86 struct ib_qp *roce_v2_gsi; 87 }; 88 89 enum { 90 MLX4_IB_MIN_SQ_STRIDE = 6, 91 MLX4_IB_CACHE_LINE_SIZE = 64, 92 }; 93 94 enum { 95 MLX4_RAW_QP_MTU = 7, 96 MLX4_RAW_QP_MSGMAX = 31, 97 }; 98 99 #ifndef ETH_ALEN 100 #define ETH_ALEN 6 101 #endif 102 103 static const __be32 mlx4_ib_opcode[] = { 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 117 }; 118 119 enum mlx4_ib_source_type { 120 MLX4_IB_QP_SRC = 0, 121 MLX4_IB_RWQ_SRC = 1, 122 }; 123 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 125 { 126 return container_of(mqp, struct mlx4_ib_sqp, qp); 127 } 128 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 130 { 131 if (!mlx4_is_master(dev->dev)) 132 return 0; 133 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 136 8 * MLX4_MFUNC_MAX; 137 } 138 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 140 { 141 int proxy_sqp = 0; 142 int real_sqp = 0; 143 int i; 144 /* PPF or Native -- real SQP */ 145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 148 if (real_sqp) 149 return 1; 150 /* VF or PF -- proxy SQP */ 151 if (mlx4_is_mfunc(dev->dev)) { 152 for (i = 0; i < dev->dev->caps.num_ports; i++) { 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 155 proxy_sqp = 1; 156 break; 157 } 158 } 159 } 160 if (proxy_sqp) 161 return 1; 162 163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 164 } 165 166 /* used for INIT/CLOSE port logic */ 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 168 { 169 int proxy_qp0 = 0; 170 int real_qp0 = 0; 171 int i; 172 /* PPF or Native -- real QP0 */ 173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 176 if (real_qp0) 177 return 1; 178 /* VF or PF -- proxy QP0 */ 179 if (mlx4_is_mfunc(dev->dev)) { 180 for (i = 0; i < dev->dev->caps.num_ports; i++) { 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 182 proxy_qp0 = 1; 183 break; 184 } 185 } 186 } 187 return proxy_qp0; 188 } 189 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 191 { 192 return mlx4_buf_offset(&qp->buf, offset); 193 } 194 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 196 { 197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 198 } 199 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 201 { 202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 203 } 204 205 /* 206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 207 * first four bytes of every 64 byte chunk with 208 * 0x7FFFFFF | (invalid_ownership_value << 31). 209 * 210 * When the max work request size is less than or equal to the WQE 211 * basic block size, as an optimization, we can stamp all WQEs with 212 * 0xffffffff, and skip the very first chunk of each WQE. 213 */ 214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 215 { 216 __be32 *wqe; 217 int i; 218 int s; 219 int ind; 220 void *buf; 221 __be32 stamp; 222 struct mlx4_wqe_ctrl_seg *ctrl; 223 224 if (qp->sq_max_wqes_per_wr > 1) { 225 s = roundup(size, 1U << qp->sq.wqe_shift); 226 for (i = 0; i < s; i += 64) { 227 ind = (i >> qp->sq.wqe_shift) + n; 228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 229 cpu_to_be32(0xffffffff); 230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 232 *wqe = stamp; 233 } 234 } else { 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 237 for (i = 64; i < s; i += 64) { 238 wqe = buf + i; 239 *wqe = cpu_to_be32(0xffffffff); 240 } 241 } 242 } 243 244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 245 { 246 struct mlx4_wqe_ctrl_seg *ctrl; 247 struct mlx4_wqe_inline_seg *inl; 248 void *wqe; 249 int s; 250 251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 252 s = sizeof(struct mlx4_wqe_ctrl_seg); 253 254 if (qp->ibqp.qp_type == IB_QPT_UD) { 255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 256 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 257 memset(dgram, 0, sizeof *dgram); 258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 259 s += sizeof(struct mlx4_wqe_datagram_seg); 260 } 261 262 /* Pad the remainder of the WQE with an inline data segment. */ 263 if (size > s) { 264 inl = wqe + s; 265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 266 } 267 ctrl->srcrb_flags = 0; 268 ctrl->qpn_vlan.fence_size = size / 16; 269 /* 270 * Make sure descriptor is fully written before setting ownership bit 271 * (because HW can start executing as soon as we do). 272 */ 273 wmb(); 274 275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 277 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 279 } 280 281 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 283 { 284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 285 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 287 ind += s; 288 } 289 return ind; 290 } 291 292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 293 { 294 struct ib_event event; 295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 296 297 if (type == MLX4_EVENT_TYPE_PATH_MIG) 298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 299 300 if (ibqp->event_handler) { 301 event.device = ibqp->device; 302 event.element.qp = ibqp; 303 switch (type) { 304 case MLX4_EVENT_TYPE_PATH_MIG: 305 event.event = IB_EVENT_PATH_MIG; 306 break; 307 case MLX4_EVENT_TYPE_COMM_EST: 308 event.event = IB_EVENT_COMM_EST; 309 break; 310 case MLX4_EVENT_TYPE_SQ_DRAINED: 311 event.event = IB_EVENT_SQ_DRAINED; 312 break; 313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 314 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 315 break; 316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 317 event.event = IB_EVENT_QP_FATAL; 318 break; 319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 320 event.event = IB_EVENT_PATH_MIG_ERR; 321 break; 322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 323 event.event = IB_EVENT_QP_REQ_ERR; 324 break; 325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 326 event.event = IB_EVENT_QP_ACCESS_ERR; 327 break; 328 default: 329 pr_warn("Unexpected event type %d " 330 "on QP %06x\n", type, qp->qpn); 331 return; 332 } 333 334 ibqp->event_handler(&event, ibqp->qp_context); 335 } 336 } 337 338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 339 { 340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 341 type, qp->qpn); 342 } 343 344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 345 { 346 /* 347 * UD WQEs must have a datagram segment. 348 * RC and UC WQEs might have a remote address segment. 349 * MLX WQEs need two extra inline data segments (for the UD 350 * header and space for the ICRC). 351 */ 352 switch (type) { 353 case MLX4_IB_QPT_UD: 354 return sizeof (struct mlx4_wqe_ctrl_seg) + 355 sizeof (struct mlx4_wqe_datagram_seg) + 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 357 case MLX4_IB_QPT_PROXY_SMI_OWNER: 358 case MLX4_IB_QPT_PROXY_SMI: 359 case MLX4_IB_QPT_PROXY_GSI: 360 return sizeof (struct mlx4_wqe_ctrl_seg) + 361 sizeof (struct mlx4_wqe_datagram_seg) + 64; 362 case MLX4_IB_QPT_TUN_SMI_OWNER: 363 case MLX4_IB_QPT_TUN_GSI: 364 return sizeof (struct mlx4_wqe_ctrl_seg) + 365 sizeof (struct mlx4_wqe_datagram_seg); 366 367 case MLX4_IB_QPT_UC: 368 return sizeof (struct mlx4_wqe_ctrl_seg) + 369 sizeof (struct mlx4_wqe_raddr_seg); 370 case MLX4_IB_QPT_RC: 371 return sizeof (struct mlx4_wqe_ctrl_seg) + 372 sizeof (struct mlx4_wqe_masked_atomic_seg) + 373 sizeof (struct mlx4_wqe_raddr_seg); 374 case MLX4_IB_QPT_SMI: 375 case MLX4_IB_QPT_GSI: 376 return sizeof (struct mlx4_wqe_ctrl_seg) + 377 ALIGN(MLX4_IB_UD_HEADER_SIZE + 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 379 MLX4_INLINE_ALIGN) * 380 sizeof (struct mlx4_wqe_inline_seg), 381 sizeof (struct mlx4_wqe_data_seg)) + 382 ALIGN(4 + 383 sizeof (struct mlx4_wqe_inline_seg), 384 sizeof (struct mlx4_wqe_data_seg)); 385 default: 386 return sizeof (struct mlx4_wqe_ctrl_seg); 387 } 388 } 389 390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 391 int is_user, int has_rq, struct mlx4_ib_qp *qp, 392 u32 inl_recv_sz) 393 { 394 /* Sanity check RQ size before proceeding */ 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 397 return -EINVAL; 398 399 if (!has_rq) { 400 if (cap->max_recv_wr || inl_recv_sz) 401 return -EINVAL; 402 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 404 } else { 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 406 sizeof(struct mlx4_wqe_data_seg); 407 u32 wqe_size; 408 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 411 inl_recv_sz > max_inl_recv_sz)) 412 return -EINVAL; 413 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 418 } 419 420 /* leave userspace return values as they were, so as not to break ABI */ 421 if (is_user) { 422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 423 cap->max_recv_sge = qp->rq.max_gs; 424 } else { 425 cap->max_recv_wr = qp->rq.max_post = 426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 427 cap->max_recv_sge = min(qp->rq.max_gs, 428 min(dev->dev->caps.max_sq_sg, 429 dev->dev->caps.max_rq_sg)); 430 } 431 432 return 0; 433 } 434 435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp, 437 bool shrink_wqe) 438 { 439 int s; 440 441 /* Sanity check SQ size before proceeding */ 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 446 return -EINVAL; 447 448 /* 449 * For MLX transport we need 2 extra S/G entries: 450 * one for the header and one for the checksum at the end 451 */ 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 455 return -EINVAL; 456 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 459 send_wqe_overhead(type, qp->flags); 460 461 if (s > dev->dev->caps.max_sq_desc_sz) 462 return -EINVAL; 463 464 /* 465 * Hermon supports shrinking WQEs, such that a single work 466 * request can include multiple units of 1 << wqe_shift. This 467 * way, work requests can differ in size, and do not have to 468 * be a power of 2 in size, saving memory and speeding up send 469 * WR posting. Unfortunately, if we do this then the 470 * wqe_index field in CQEs can't be used to look up the WR ID 471 * anymore, so we do this only if selective signaling is off. 472 * 473 * Further, on 32-bit platforms, we can't use vmap() to make 474 * the QP buffer virtually contiguous. Thus we have to use 475 * constant-sized WRs to make sure a WR is always fully within 476 * a single page-sized chunk. 477 * 478 * Finally, we use NOP work requests to pad the end of the 479 * work queue, to avoid wrap-around in the middle of WR. We 480 * set NEC bit to avoid getting completions with error for 481 * these NOP WRs, but since NEC is only supported starting 482 * with firmware 2.2.232, we use constant-sized WRs for older 483 * firmware. 484 * 485 * And, since MLX QPs only support SEND, we use constant-sized 486 * WRs in this case. 487 * 488 * We look for the smallest value of wqe_shift such that the 489 * resulting number of wqes does not exceed device 490 * capabilities. 491 * 492 * We set WQE size to at least 64 bytes, this way stamping 493 * invalidates each WQE. 494 */ 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 496 qp->sq_signal_bits && BITS_PER_LONG == 64 && 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 500 qp->sq.wqe_shift = ilog2(64); 501 else 502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 503 504 for (;;) { 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 506 507 /* 508 * We need to leave 2 KB + 1 WR of headroom in the SQ to 509 * allow HW to prefetch. 510 */ 511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 513 qp->sq_max_wqes_per_wr + 514 qp->sq_spare_wqes); 515 516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 517 break; 518 519 if (qp->sq_max_wqes_per_wr <= 1) 520 return -EINVAL; 521 522 ++qp->sq.wqe_shift; 523 } 524 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 527 send_wqe_overhead(type, qp->flags)) / 528 sizeof (struct mlx4_wqe_data_seg); 529 530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 531 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 533 qp->rq.offset = 0; 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 535 } else { 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 537 qp->sq.offset = 0; 538 } 539 540 cap->max_send_wr = qp->sq.max_post = 541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 542 cap->max_send_sge = min(qp->sq.max_gs, 543 min(dev->dev->caps.max_sq_sg, 544 dev->dev->caps.max_rq_sg)); 545 /* We don't support inline sends for kernel QPs (yet) */ 546 cap->max_inline_data = 0; 547 548 return 0; 549 } 550 551 static int set_user_sq_size(struct mlx4_ib_dev *dev, 552 struct mlx4_ib_qp *qp, 553 struct mlx4_ib_create_qp *ucmd) 554 { 555 /* Sanity check SQ size before proceeding */ 556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 557 ucmd->log_sq_stride > 558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 560 return -EINVAL; 561 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 563 qp->sq.wqe_shift = ucmd->log_sq_stride; 564 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 566 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 567 568 return 0; 569 } 570 571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 572 { 573 int i; 574 575 qp->sqp_proxy_rcv = 576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 577 GFP_KERNEL); 578 if (!qp->sqp_proxy_rcv) 579 return -ENOMEM; 580 for (i = 0; i < qp->rq.wqe_cnt; i++) { 581 qp->sqp_proxy_rcv[i].addr = 582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 583 GFP_KERNEL); 584 if (!qp->sqp_proxy_rcv[i].addr) 585 goto err; 586 qp->sqp_proxy_rcv[i].map = 587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 588 sizeof (struct mlx4_ib_proxy_sqp_hdr), 589 DMA_FROM_DEVICE); 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 591 kfree(qp->sqp_proxy_rcv[i].addr); 592 goto err; 593 } 594 } 595 return 0; 596 597 err: 598 while (i > 0) { 599 --i; 600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 601 sizeof (struct mlx4_ib_proxy_sqp_hdr), 602 DMA_FROM_DEVICE); 603 kfree(qp->sqp_proxy_rcv[i].addr); 604 } 605 kfree(qp->sqp_proxy_rcv); 606 qp->sqp_proxy_rcv = NULL; 607 return -ENOMEM; 608 } 609 610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 611 { 612 int i; 613 614 for (i = 0; i < qp->rq.wqe_cnt; i++) { 615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 616 sizeof (struct mlx4_ib_proxy_sqp_hdr), 617 DMA_FROM_DEVICE); 618 kfree(qp->sqp_proxy_rcv[i].addr); 619 } 620 kfree(qp->sqp_proxy_rcv); 621 } 622 623 static int qp_has_rq(struct ib_qp_init_attr *attr) 624 { 625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 626 return 0; 627 628 return !attr->srq; 629 } 630 631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 632 { 633 int i; 634 for (i = 0; i < dev->caps.num_ports; i++) { 635 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 636 return !!dev->caps.spec_qps[i].qp0_qkey; 637 } 638 return 0; 639 } 640 641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 642 struct mlx4_ib_qp *qp) 643 { 644 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 645 mlx4_counter_free(dev->dev, qp->counter_index->index); 646 list_del(&qp->counter_index->list); 647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 648 649 kfree(qp->counter_index); 650 qp->counter_index = NULL; 651 } 652 653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 654 struct ib_qp_init_attr *init_attr, 655 struct mlx4_ib_create_qp_rss *ucmd) 656 { 657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 659 660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 663 MLX4_EN_RSS_KEY_SIZE); 664 } else { 665 pr_debug("RX Hash function is not supported\n"); 666 return (-EOPNOTSUPP); 667 } 668 669 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 670 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 671 rss_ctx->flags = MLX4_RSS_IPV4; 672 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 673 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 674 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 675 return (-EOPNOTSUPP); 676 } 677 678 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 679 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 680 rss_ctx->flags |= MLX4_RSS_IPV6; 681 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 682 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 683 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 684 return (-EOPNOTSUPP); 685 } 686 687 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 688 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 689 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 690 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 691 return (-EOPNOTSUPP); 692 } 693 694 if (rss_ctx->flags & MLX4_RSS_IPV4) { 695 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 696 } else if (rss_ctx->flags & MLX4_RSS_IPV6) { 697 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 698 } else { 699 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 700 return (-EOPNOTSUPP); 701 } 702 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 703 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 704 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 705 return (-EOPNOTSUPP); 706 } 707 708 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 709 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 710 if (rss_ctx->flags & MLX4_RSS_IPV4) { 711 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 712 } else if (rss_ctx->flags & MLX4_RSS_IPV6) { 713 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 714 } else { 715 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 716 return (-EOPNOTSUPP); 717 } 718 719 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 720 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 721 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 722 return (-EOPNOTSUPP); 723 } 724 725 return 0; 726 } 727 728 static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd, 729 struct ib_qp_init_attr *init_attr, 730 struct mlx4_ib_create_qp_rss *ucmd, 731 struct mlx4_ib_qp *qp) 732 { 733 int qpn; 734 int err; 735 736 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 737 738 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 739 if (err) 740 return err; 741 742 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 743 if (err) 744 goto err_qpn; 745 746 mutex_init(&qp->mutex); 747 748 INIT_LIST_HEAD(&qp->gid_list); 749 INIT_LIST_HEAD(&qp->steering_rules); 750 751 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 752 qp->state = IB_QPS_RESET; 753 754 /* Set dummy send resources to be compatible with HV and PRM */ 755 qp->sq_no_prefetch = 1; 756 qp->sq.wqe_cnt = 1; 757 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 758 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 759 qp->mtt = (to_mqp( 760 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 761 762 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 763 if (!qp->rss_ctx) { 764 err = -ENOMEM; 765 goto err_qp_alloc; 766 } 767 768 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 769 if (err) 770 goto err; 771 772 return 0; 773 774 err: 775 kfree(qp->rss_ctx); 776 777 err_qp_alloc: 778 mlx4_qp_remove(dev->dev, &qp->mqp); 779 mlx4_qp_free(dev->dev, &qp->mqp); 780 781 err_qpn: 782 mlx4_qp_release_range(dev->dev, qpn, 1); 783 return err; 784 } 785 786 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd, 787 struct ib_qp_init_attr *init_attr, 788 struct ib_udata *udata) 789 { 790 struct mlx4_ib_qp *qp; 791 struct mlx4_ib_create_qp_rss ucmd = {}; 792 size_t required_cmd_sz; 793 int err; 794 795 if (!udata) { 796 pr_debug("RSS QP with NULL udata\n"); 797 return ERR_PTR(-EINVAL); 798 } 799 800 if (udata->outlen) 801 return ERR_PTR(-EOPNOTSUPP); 802 803 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 804 sizeof(ucmd.reserved1); 805 if (udata->inlen < required_cmd_sz) { 806 pr_debug("invalid inlen\n"); 807 return ERR_PTR(-EINVAL); 808 } 809 810 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 811 pr_debug("copy failed\n"); 812 return ERR_PTR(-EFAULT); 813 } 814 815 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 816 return ERR_PTR(-EOPNOTSUPP); 817 818 if (ucmd.comp_mask || ucmd.reserved1) 819 return ERR_PTR(-EOPNOTSUPP); 820 821 if (udata->inlen > sizeof(ucmd) && 822 !ib_is_udata_cleared(udata, sizeof(ucmd), 823 udata->inlen - sizeof(ucmd))) { 824 pr_debug("inlen is not supported\n"); 825 return ERR_PTR(-EOPNOTSUPP); 826 } 827 828 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 829 pr_debug("RSS QP with unsupported QP type %d\n", 830 init_attr->qp_type); 831 return ERR_PTR(-EOPNOTSUPP); 832 } 833 834 if (init_attr->create_flags) { 835 pr_debug("RSS QP doesn't support create flags\n"); 836 return ERR_PTR(-EOPNOTSUPP); 837 } 838 839 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 840 pr_debug("RSS QP with unsupported send attributes\n"); 841 return ERR_PTR(-EOPNOTSUPP); 842 } 843 844 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 845 if (!qp) 846 return ERR_PTR(-ENOMEM); 847 848 qp->pri.vid = 0xFFFF; 849 qp->alt.vid = 0xFFFF; 850 851 err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp); 852 if (err) { 853 kfree(qp); 854 return ERR_PTR(err); 855 } 856 857 qp->ibqp.qp_num = qp->mqp.qpn; 858 859 return &qp->ibqp; 860 } 861 862 /* 863 * This function allocates a WQN from a range which is consecutive and aligned 864 * to its size. In case the range is full, then it creates a new range and 865 * allocates WQN from it. The new range will be used for following allocations. 866 */ 867 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 868 struct mlx4_ib_qp *qp, int range_size, int *wqn) 869 { 870 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 871 struct mlx4_wqn_range *range; 872 int err = 0; 873 874 mutex_lock(&context->wqn_ranges_mutex); 875 876 range = list_first_entry_or_null(&context->wqn_ranges_list, 877 struct mlx4_wqn_range, list); 878 879 if (!range || (range->refcount == range->size) || range->dirty) { 880 range = kzalloc(sizeof(*range), GFP_KERNEL); 881 if (!range) { 882 err = -ENOMEM; 883 goto out; 884 } 885 886 err = mlx4_qp_reserve_range(dev->dev, range_size, 887 range_size, &range->base_wqn, 0, 888 qp->mqp.usage); 889 if (err) { 890 kfree(range); 891 goto out; 892 } 893 894 range->size = range_size; 895 list_add(&range->list, &context->wqn_ranges_list); 896 } else if (range_size != 1) { 897 /* 898 * Requesting a new range (>1) when last range is still open, is 899 * not valid. 900 */ 901 err = -EINVAL; 902 goto out; 903 } 904 905 qp->wqn_range = range; 906 907 *wqn = range->base_wqn + range->refcount; 908 909 range->refcount++; 910 911 out: 912 mutex_unlock(&context->wqn_ranges_mutex); 913 914 return err; 915 } 916 917 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 918 struct mlx4_ib_qp *qp, bool dirty_release) 919 { 920 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 921 struct mlx4_wqn_range *range; 922 923 mutex_lock(&context->wqn_ranges_mutex); 924 925 range = qp->wqn_range; 926 927 range->refcount--; 928 if (!range->refcount) { 929 mlx4_qp_release_range(dev->dev, range->base_wqn, 930 range->size); 931 list_del(&range->list); 932 kfree(range); 933 } else if (dirty_release) { 934 /* 935 * A range which one of its WQNs is destroyed, won't be able to be 936 * reused for further WQN allocations. 937 * The next created WQ will allocate a new range. 938 */ 939 range->dirty = 1; 940 } 941 942 mutex_unlock(&context->wqn_ranges_mutex); 943 } 944 945 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 946 enum mlx4_ib_source_type src, 947 struct ib_qp_init_attr *init_attr, 948 struct ib_udata *udata, int sqpn, 949 struct mlx4_ib_qp **caller_qp) 950 { 951 int qpn; 952 int err; 953 struct ib_qp_cap backup_cap; 954 struct mlx4_ib_sqp *sqp = NULL; 955 struct mlx4_ib_qp *qp; 956 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 957 struct mlx4_ib_cq *mcq; 958 unsigned long flags; 959 int range_size = 0; 960 961 /* When tunneling special qps, we use a plain UD qp */ 962 if (sqpn) { 963 if (mlx4_is_mfunc(dev->dev) && 964 (!mlx4_is_master(dev->dev) || 965 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 966 if (init_attr->qp_type == IB_QPT_GSI) 967 qp_type = MLX4_IB_QPT_PROXY_GSI; 968 else { 969 if (mlx4_is_master(dev->dev) || 970 qp0_enabled_vf(dev->dev, sqpn)) 971 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 972 else 973 qp_type = MLX4_IB_QPT_PROXY_SMI; 974 } 975 } 976 qpn = sqpn; 977 /* add extra sg entry for tunneling */ 978 init_attr->cap.max_recv_sge++; 979 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 980 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 981 container_of(init_attr, 982 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 983 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 984 tnl_init->proxy_qp_type != IB_QPT_GSI) || 985 !mlx4_is_master(dev->dev)) 986 return -EINVAL; 987 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 988 qp_type = MLX4_IB_QPT_TUN_GSI; 989 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 990 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 991 tnl_init->port)) 992 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 993 else 994 qp_type = MLX4_IB_QPT_TUN_SMI; 995 /* we are definitely in the PPF here, since we are creating 996 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 997 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 998 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 999 sqpn = qpn; 1000 } 1001 1002 if (!*caller_qp) { 1003 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 1004 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 1005 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 1006 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 1007 if (!sqp) 1008 return -ENOMEM; 1009 qp = &sqp->qp; 1010 qp->pri.vid = 0xFFFF; 1011 qp->alt.vid = 0xFFFF; 1012 } else { 1013 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL); 1014 if (!qp) 1015 return -ENOMEM; 1016 qp->pri.vid = 0xFFFF; 1017 qp->alt.vid = 0xFFFF; 1018 } 1019 } else 1020 qp = *caller_qp; 1021 1022 qp->mlx4_ib_qp_type = qp_type; 1023 1024 mutex_init(&qp->mutex); 1025 spin_lock_init(&qp->sq.lock); 1026 spin_lock_init(&qp->rq.lock); 1027 INIT_LIST_HEAD(&qp->gid_list); 1028 INIT_LIST_HEAD(&qp->steering_rules); 1029 1030 qp->state = IB_QPS_RESET; 1031 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1032 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1033 1034 1035 if (pd->uobject) { 1036 union { 1037 struct mlx4_ib_create_qp qp; 1038 struct mlx4_ib_create_wq wq; 1039 } ucmd; 1040 size_t copy_len; 1041 1042 copy_len = (src == MLX4_IB_QP_SRC) ? 1043 sizeof(struct mlx4_ib_create_qp) : 1044 min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 1045 1046 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 1047 err = -EFAULT; 1048 goto err; 1049 } 1050 1051 if (src == MLX4_IB_RWQ_SRC) { 1052 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] || 1053 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) { 1054 pr_debug("user command isn't supported\n"); 1055 err = -EOPNOTSUPP; 1056 goto err; 1057 } 1058 1059 if (ucmd.wq.log_range_size > 1060 ilog2(dev->dev->caps.max_rss_tbl_sz)) { 1061 pr_debug("WQN range size must be equal or smaller than %d\n", 1062 dev->dev->caps.max_rss_tbl_sz); 1063 err = -EOPNOTSUPP; 1064 goto err; 1065 } 1066 range_size = 1 << ucmd.wq.log_range_size; 1067 } else { 1068 qp->inl_recv_sz = ucmd.qp.inl_recv_sz; 1069 } 1070 1071 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, 1072 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1073 if (err) 1074 goto err; 1075 1076 if (src == MLX4_IB_QP_SRC) { 1077 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch; 1078 1079 err = set_user_sq_size(dev, qp, 1080 (struct mlx4_ib_create_qp *) 1081 &ucmd); 1082 if (err) 1083 goto err; 1084 } else { 1085 qp->sq_no_prefetch = 1; 1086 qp->sq.wqe_cnt = 1; 1087 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 1088 /* Allocated buffer expects to have at least that SQ 1089 * size. 1090 */ 1091 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 1092 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 1093 } 1094 1095 qp->umem = ib_umem_get(pd->uobject->context, 1096 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr : 1097 ucmd.wq.buf_addr, qp->buf_size, 0, 0); 1098 if (IS_ERR(qp->umem)) { 1099 err = PTR_ERR(qp->umem); 1100 goto err; 1101 } 1102 1103 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 1104 qp->umem->page_shift, &qp->mtt); 1105 if (err) 1106 goto err_buf; 1107 1108 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1109 if (err) 1110 goto err_mtt; 1111 1112 if (qp_has_rq(init_attr)) { 1113 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 1114 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr : 1115 ucmd.wq.db_addr, &qp->db); 1116 if (err) 1117 goto err_mtt; 1118 } 1119 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1120 } else { 1121 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, 1122 qp_has_rq(init_attr), qp, 0); 1123 if (err) 1124 goto err; 1125 1126 qp->sq_no_prefetch = 0; 1127 1128 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1129 qp->flags |= MLX4_IB_QP_LSO; 1130 1131 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1132 if (dev->steering_support == 1133 MLX4_STEERING_MODE_DEVICE_MANAGED) 1134 qp->flags |= MLX4_IB_QP_NETIF; 1135 else 1136 goto err; 1137 } 1138 1139 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap)); 1140 err = set_kernel_sq_size(dev, &init_attr->cap, 1141 qp_type, qp, true); 1142 if (err) 1143 goto err; 1144 1145 if (qp_has_rq(init_attr)) { 1146 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1147 if (err) 1148 goto err; 1149 1150 *qp->db.db = 0; 1151 } 1152 1153 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size, 1154 &qp->buf)) { 1155 memcpy(&init_attr->cap, &backup_cap, 1156 sizeof(backup_cap)); 1157 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, 1158 qp, false); 1159 if (err) 1160 goto err_db; 1161 1162 if (mlx4_buf_alloc(dev->dev, qp->buf_size, 1163 PAGE_SIZE * 2, &qp->buf)) { 1164 err = -ENOMEM; 1165 goto err_db; 1166 } 1167 } 1168 1169 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1170 &qp->mtt); 1171 if (err) 1172 goto err_buf; 1173 1174 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1175 if (err) 1176 goto err_mtt; 1177 1178 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1179 sizeof(u64), GFP_KERNEL); 1180 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1181 sizeof(u64), GFP_KERNEL); 1182 if (!qp->sq.wrid || !qp->rq.wrid) { 1183 err = -ENOMEM; 1184 goto err_wrid; 1185 } 1186 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1187 } 1188 1189 if (sqpn) { 1190 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1191 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1192 if (alloc_proxy_bufs(pd->device, qp)) { 1193 err = -ENOMEM; 1194 goto err_wrid; 1195 } 1196 } 1197 } else if (src == MLX4_IB_RWQ_SRC) { 1198 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp, 1199 range_size, &qpn); 1200 if (err) 1201 goto err_wrid; 1202 } else { 1203 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1204 * otherwise, the WQE BlueFlame setup flow wrongly causes 1205 * VLAN insertion. */ 1206 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1207 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1208 (init_attr->cap.max_send_wr ? 1209 MLX4_RESERVE_ETH_BF_QP : 0) | 1210 (init_attr->cap.max_recv_wr ? 1211 MLX4_RESERVE_A0_QP : 0), 1212 qp->mqp.usage); 1213 else 1214 if (qp->flags & MLX4_IB_QP_NETIF) 1215 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1216 else 1217 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1218 &qpn, 0, qp->mqp.usage); 1219 if (err) 1220 goto err_proxy; 1221 } 1222 1223 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1224 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1225 1226 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1227 if (err) 1228 goto err_qpn; 1229 1230 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1231 qp->mqp.qpn |= (1 << 23); 1232 1233 /* 1234 * Hardware wants QPN written in big-endian order (after 1235 * shifting) for send doorbell. Precompute this value to save 1236 * a little bit when posting sends. 1237 */ 1238 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1239 1240 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event : 1241 mlx4_ib_wq_event; 1242 1243 if (!*caller_qp) 1244 *caller_qp = qp; 1245 1246 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1247 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1248 to_mcq(init_attr->recv_cq)); 1249 /* Maintain device to QPs access, needed for further handling 1250 * via reset flow 1251 */ 1252 list_add_tail(&qp->qps_list, &dev->qp_list); 1253 /* Maintain CQ to QPs access, needed for further handling 1254 * via reset flow 1255 */ 1256 mcq = to_mcq(init_attr->send_cq); 1257 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1258 mcq = to_mcq(init_attr->recv_cq); 1259 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1260 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1261 to_mcq(init_attr->recv_cq)); 1262 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1263 return 0; 1264 1265 err_qpn: 1266 if (!sqpn) { 1267 if (qp->flags & MLX4_IB_QP_NETIF) 1268 mlx4_ib_steer_qp_free(dev, qpn, 1); 1269 else if (src == MLX4_IB_RWQ_SRC) 1270 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context), 1271 qp, 0); 1272 else 1273 mlx4_qp_release_range(dev->dev, qpn, 1); 1274 } 1275 err_proxy: 1276 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1277 free_proxy_bufs(pd->device, qp); 1278 err_wrid: 1279 if (pd->uobject) { 1280 if (qp_has_rq(init_attr)) 1281 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 1282 } else { 1283 kvfree(qp->sq.wrid); 1284 kvfree(qp->rq.wrid); 1285 } 1286 1287 err_mtt: 1288 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1289 1290 err_buf: 1291 if (pd->uobject) 1292 ib_umem_release(qp->umem); 1293 else 1294 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1295 1296 err_db: 1297 if (!pd->uobject && qp_has_rq(init_attr)) 1298 mlx4_db_free(dev->dev, &qp->db); 1299 1300 err: 1301 if (sqp) 1302 kfree(sqp); 1303 else if (!*caller_qp) 1304 kfree(qp); 1305 return err; 1306 } 1307 1308 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1309 { 1310 switch (state) { 1311 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1312 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1313 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1314 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1315 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1316 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1317 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1318 default: return -1; 1319 } 1320 } 1321 1322 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1323 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1324 { 1325 if (send_cq == recv_cq) { 1326 spin_lock(&send_cq->lock); 1327 __acquire(&recv_cq->lock); 1328 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1329 spin_lock(&send_cq->lock); 1330 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1331 } else { 1332 spin_lock(&recv_cq->lock); 1333 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1334 } 1335 } 1336 1337 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1338 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1339 { 1340 if (send_cq == recv_cq) { 1341 __release(&recv_cq->lock); 1342 spin_unlock(&send_cq->lock); 1343 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1344 spin_unlock(&recv_cq->lock); 1345 spin_unlock(&send_cq->lock); 1346 } else { 1347 spin_unlock(&send_cq->lock); 1348 spin_unlock(&recv_cq->lock); 1349 } 1350 } 1351 1352 static void del_gid_entries(struct mlx4_ib_qp *qp) 1353 { 1354 struct mlx4_ib_gid_entry *ge, *tmp; 1355 1356 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1357 list_del(&ge->list); 1358 kfree(ge); 1359 } 1360 } 1361 1362 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1363 { 1364 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1365 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1366 else 1367 return to_mpd(qp->ibqp.pd); 1368 } 1369 1370 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1371 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1372 { 1373 switch (qp->ibqp.qp_type) { 1374 case IB_QPT_XRC_TGT: 1375 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1376 *recv_cq = *send_cq; 1377 break; 1378 case IB_QPT_XRC_INI: 1379 *send_cq = to_mcq(qp->ibqp.send_cq); 1380 *recv_cq = *send_cq; 1381 break; 1382 default: 1383 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1384 to_mcq(qp->ibwq.cq); 1385 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1386 *recv_cq; 1387 break; 1388 } 1389 } 1390 1391 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1392 { 1393 if (qp->state != IB_QPS_RESET) { 1394 int i; 1395 1396 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1397 i++) { 1398 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1399 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1400 1401 mutex_lock(&wq->mutex); 1402 1403 wq->rss_usecnt--; 1404 1405 mutex_unlock(&wq->mutex); 1406 } 1407 1408 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1409 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1410 pr_warn("modify QP %06x to RESET failed.\n", 1411 qp->mqp.qpn); 1412 } 1413 1414 mlx4_qp_remove(dev->dev, &qp->mqp); 1415 mlx4_qp_free(dev->dev, &qp->mqp); 1416 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1417 del_gid_entries(qp); 1418 kfree(qp->rss_ctx); 1419 } 1420 1421 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1422 enum mlx4_ib_source_type src, int is_user) 1423 { 1424 struct mlx4_ib_cq *send_cq, *recv_cq; 1425 unsigned long flags; 1426 1427 if (qp->state != IB_QPS_RESET) { 1428 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1429 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1430 pr_warn("modify QP %06x to RESET failed.\n", 1431 qp->mqp.qpn); 1432 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1433 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1434 qp->pri.smac = 0; 1435 qp->pri.smac_port = 0; 1436 } 1437 if (qp->alt.smac) { 1438 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1439 qp->alt.smac = 0; 1440 } 1441 if (qp->pri.vid < 0x1000) { 1442 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1443 qp->pri.vid = 0xFFFF; 1444 qp->pri.candidate_vid = 0xFFFF; 1445 qp->pri.update_vid = 0; 1446 } 1447 if (qp->alt.vid < 0x1000) { 1448 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1449 qp->alt.vid = 0xFFFF; 1450 qp->alt.candidate_vid = 0xFFFF; 1451 qp->alt.update_vid = 0; 1452 } 1453 } 1454 1455 get_cqs(qp, src, &send_cq, &recv_cq); 1456 1457 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1458 mlx4_ib_lock_cqs(send_cq, recv_cq); 1459 1460 /* del from lists under both locks above to protect reset flow paths */ 1461 list_del(&qp->qps_list); 1462 list_del(&qp->cq_send_list); 1463 list_del(&qp->cq_recv_list); 1464 if (!is_user) { 1465 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1466 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1467 if (send_cq != recv_cq) 1468 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1469 } 1470 1471 mlx4_qp_remove(dev->dev, &qp->mqp); 1472 1473 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1474 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1475 1476 mlx4_qp_free(dev->dev, &qp->mqp); 1477 1478 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1479 if (qp->flags & MLX4_IB_QP_NETIF) 1480 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1481 else if (src == MLX4_IB_RWQ_SRC) 1482 mlx4_ib_release_wqn(to_mucontext( 1483 qp->ibwq.uobject->context), qp, 1); 1484 else 1485 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1486 } 1487 1488 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1489 1490 if (is_user) { 1491 if (qp->rq.wqe_cnt) { 1492 struct mlx4_ib_ucontext *mcontext = !src ? 1493 to_mucontext(qp->ibqp.uobject->context) : 1494 to_mucontext(qp->ibwq.uobject->context); 1495 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1496 } 1497 ib_umem_release(qp->umem); 1498 } else { 1499 kvfree(qp->sq.wrid); 1500 kvfree(qp->rq.wrid); 1501 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1502 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1503 free_proxy_bufs(&dev->ib_dev, qp); 1504 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1505 if (qp->rq.wqe_cnt) 1506 mlx4_db_free(dev->dev, &qp->db); 1507 } 1508 1509 del_gid_entries(qp); 1510 } 1511 1512 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1513 { 1514 /* Native or PPF */ 1515 if (!mlx4_is_mfunc(dev->dev) || 1516 (mlx4_is_master(dev->dev) && 1517 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1518 return dev->dev->phys_caps.base_sqpn + 1519 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1520 attr->port_num - 1; 1521 } 1522 /* PF or VF -- creating proxies */ 1523 if (attr->qp_type == IB_QPT_SMI) 1524 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1525 else 1526 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1527 } 1528 1529 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1530 struct ib_qp_init_attr *init_attr, 1531 struct ib_udata *udata) 1532 { 1533 struct mlx4_ib_qp *qp = NULL; 1534 int err; 1535 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1536 u16 xrcdn = 0; 1537 1538 if (init_attr->rwq_ind_tbl) 1539 return _mlx4_ib_create_qp_rss(pd, init_attr, udata); 1540 1541 /* 1542 * We only support LSO, vendor flag1, and multicast loopback blocking, 1543 * and only for kernel UD QPs. 1544 */ 1545 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1546 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1547 MLX4_IB_SRIOV_TUNNEL_QP | 1548 MLX4_IB_SRIOV_SQP | 1549 MLX4_IB_QP_NETIF | 1550 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1551 return ERR_PTR(-EINVAL); 1552 1553 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1554 if (init_attr->qp_type != IB_QPT_UD) 1555 return ERR_PTR(-EINVAL); 1556 } 1557 1558 if (init_attr->create_flags) { 1559 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1560 return ERR_PTR(-EINVAL); 1561 1562 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1563 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1564 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1565 init_attr->qp_type != IB_QPT_UD) || 1566 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1567 init_attr->qp_type > IB_QPT_GSI) || 1568 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1569 init_attr->qp_type != IB_QPT_GSI)) 1570 return ERR_PTR(-EINVAL); 1571 } 1572 1573 switch (init_attr->qp_type) { 1574 case IB_QPT_XRC_TGT: 1575 pd = to_mxrcd(init_attr->xrcd)->pd; 1576 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1577 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1578 /* fall through */ 1579 case IB_QPT_XRC_INI: 1580 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1581 return ERR_PTR(-ENOSYS); 1582 init_attr->recv_cq = init_attr->send_cq; 1583 /* fall through */ 1584 case IB_QPT_RC: 1585 case IB_QPT_UC: 1586 case IB_QPT_RAW_PACKET: 1587 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1588 if (!qp) 1589 return ERR_PTR(-ENOMEM); 1590 qp->pri.vid = 0xFFFF; 1591 qp->alt.vid = 0xFFFF; 1592 /* fall through */ 1593 case IB_QPT_UD: 1594 { 1595 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1596 init_attr, udata, 0, &qp); 1597 if (err) { 1598 kfree(qp); 1599 return ERR_PTR(err); 1600 } 1601 1602 qp->ibqp.qp_num = qp->mqp.qpn; 1603 qp->xrcdn = xrcdn; 1604 1605 break; 1606 } 1607 case IB_QPT_SMI: 1608 case IB_QPT_GSI: 1609 { 1610 int sqpn; 1611 1612 /* Userspace is not allowed to create special QPs: */ 1613 if (udata) 1614 return ERR_PTR(-EINVAL); 1615 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1616 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1617 1, 1, &sqpn, 0, 1618 MLX4_RES_USAGE_DRIVER); 1619 1620 if (res) 1621 return ERR_PTR(res); 1622 } else { 1623 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1624 } 1625 1626 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1627 init_attr, udata, sqpn, &qp); 1628 if (err) 1629 return ERR_PTR(err); 1630 1631 qp->port = init_attr->port_num; 1632 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1633 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1634 break; 1635 } 1636 default: 1637 /* Don't support raw QPs */ 1638 return ERR_PTR(-EINVAL); 1639 } 1640 1641 return &qp->ibqp; 1642 } 1643 1644 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1645 struct ib_qp_init_attr *init_attr, 1646 struct ib_udata *udata) { 1647 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1648 struct ib_qp *ibqp; 1649 struct mlx4_ib_dev *dev = to_mdev(device); 1650 1651 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1652 1653 if (!IS_ERR(ibqp) && 1654 (init_attr->qp_type == IB_QPT_GSI) && 1655 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1656 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1657 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1658 1659 if (is_eth && 1660 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1661 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1662 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1663 1664 if (IS_ERR(sqp->roce_v2_gsi)) { 1665 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1666 sqp->roce_v2_gsi = NULL; 1667 } else { 1668 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1669 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1670 } 1671 1672 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1673 } 1674 } 1675 return ibqp; 1676 } 1677 1678 static int _mlx4_ib_destroy_qp(struct ib_qp *qp) 1679 { 1680 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1681 struct mlx4_ib_qp *mqp = to_mqp(qp); 1682 1683 if (is_qp0(dev, mqp)) 1684 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1685 1686 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1687 dev->qp1_proxy[mqp->port - 1] == mqp) { 1688 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1689 dev->qp1_proxy[mqp->port - 1] = NULL; 1690 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1691 } 1692 1693 if (mqp->counter_index) 1694 mlx4_ib_free_qp_counter(dev, mqp); 1695 1696 if (qp->rwq_ind_tbl) { 1697 destroy_qp_rss(dev, mqp); 1698 } else { 1699 struct mlx4_ib_pd *pd; 1700 1701 pd = get_pd(mqp); 1702 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject); 1703 } 1704 1705 if (is_sqp(dev, mqp)) 1706 kfree(to_msqp(mqp)); 1707 else 1708 kfree(mqp); 1709 1710 return 0; 1711 } 1712 1713 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1714 { 1715 struct mlx4_ib_qp *mqp = to_mqp(qp); 1716 1717 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1718 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1719 1720 if (sqp->roce_v2_gsi) 1721 ib_destroy_qp(sqp->roce_v2_gsi); 1722 } 1723 1724 return _mlx4_ib_destroy_qp(qp); 1725 } 1726 1727 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1728 { 1729 switch (type) { 1730 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1731 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1732 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1733 case MLX4_IB_QPT_XRC_INI: 1734 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1735 case MLX4_IB_QPT_SMI: 1736 case MLX4_IB_QPT_GSI: 1737 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1738 1739 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1740 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1741 MLX4_QP_ST_MLX : -1); 1742 case MLX4_IB_QPT_PROXY_SMI: 1743 case MLX4_IB_QPT_TUN_SMI: 1744 case MLX4_IB_QPT_PROXY_GSI: 1745 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1746 MLX4_QP_ST_UD : -1); 1747 default: return -1; 1748 } 1749 } 1750 1751 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1752 int attr_mask) 1753 { 1754 u8 dest_rd_atomic; 1755 u32 access_flags; 1756 u32 hw_access_flags = 0; 1757 1758 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1759 dest_rd_atomic = attr->max_dest_rd_atomic; 1760 else 1761 dest_rd_atomic = qp->resp_depth; 1762 1763 if (attr_mask & IB_QP_ACCESS_FLAGS) 1764 access_flags = attr->qp_access_flags; 1765 else 1766 access_flags = qp->atomic_rd_en; 1767 1768 if (!dest_rd_atomic) 1769 access_flags &= IB_ACCESS_REMOTE_WRITE; 1770 1771 if (access_flags & IB_ACCESS_REMOTE_READ) 1772 hw_access_flags |= MLX4_QP_BIT_RRE; 1773 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1774 hw_access_flags |= MLX4_QP_BIT_RAE; 1775 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1776 hw_access_flags |= MLX4_QP_BIT_RWE; 1777 1778 return cpu_to_be32(hw_access_flags); 1779 } 1780 1781 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1782 int attr_mask) 1783 { 1784 if (attr_mask & IB_QP_PKEY_INDEX) 1785 sqp->pkey_index = attr->pkey_index; 1786 if (attr_mask & IB_QP_QKEY) 1787 sqp->qkey = attr->qkey; 1788 if (attr_mask & IB_QP_SQ_PSN) 1789 sqp->send_psn = attr->sq_psn; 1790 } 1791 1792 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1793 { 1794 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1795 } 1796 1797 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1798 const struct rdma_ah_attr *ah, 1799 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1800 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1801 { 1802 int vidx; 1803 int smac_index; 1804 int err; 1805 1806 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1807 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1808 if (rdma_ah_get_static_rate(ah)) { 1809 path->static_rate = rdma_ah_get_static_rate(ah) + 1810 MLX4_STAT_RATE_OFFSET; 1811 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1812 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1813 --path->static_rate; 1814 } else 1815 path->static_rate = 0; 1816 1817 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1818 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1819 int real_sgid_index = 1820 mlx4_ib_gid_index_to_real_index(dev, port, 1821 grh->sgid_index); 1822 1823 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1824 pr_err("sgid_index (%u) too large. max is %d\n", 1825 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1826 return -1; 1827 } 1828 1829 path->grh_mylmc |= 1 << 7; 1830 path->mgid_index = real_sgid_index; 1831 path->hop_limit = grh->hop_limit; 1832 path->tclass_flowlabel = 1833 cpu_to_be32((grh->traffic_class << 20) | 1834 (grh->flow_label)); 1835 memcpy(path->rgid, grh->dgid.raw, 16); 1836 } 1837 1838 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1839 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1840 return -1; 1841 1842 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1843 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1844 1845 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1846 if (vlan_tag < 0x1000) { 1847 if (smac_info->vid < 0x1000) { 1848 /* both valid vlan ids */ 1849 if (smac_info->vid != vlan_tag) { 1850 /* different VIDs. unreg old and reg new */ 1851 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1852 if (err) 1853 return err; 1854 smac_info->candidate_vid = vlan_tag; 1855 smac_info->candidate_vlan_index = vidx; 1856 smac_info->candidate_vlan_port = port; 1857 smac_info->update_vid = 1; 1858 path->vlan_index = vidx; 1859 } else { 1860 path->vlan_index = smac_info->vlan_index; 1861 } 1862 } else { 1863 /* no current vlan tag in qp */ 1864 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1865 if (err) 1866 return err; 1867 smac_info->candidate_vid = vlan_tag; 1868 smac_info->candidate_vlan_index = vidx; 1869 smac_info->candidate_vlan_port = port; 1870 smac_info->update_vid = 1; 1871 path->vlan_index = vidx; 1872 } 1873 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1874 path->fl = 1 << 6; 1875 } else { 1876 /* have current vlan tag. unregister it at modify-qp success */ 1877 if (smac_info->vid < 0x1000) { 1878 smac_info->candidate_vid = 0xFFFF; 1879 smac_info->update_vid = 1; 1880 } 1881 } 1882 1883 /* get smac_index for RoCE use. 1884 * If no smac was yet assigned, register one. 1885 * If one was already assigned, but the new mac differs, 1886 * unregister the old one and register the new one. 1887 */ 1888 if ((!smac_info->smac && !smac_info->smac_port) || 1889 smac_info->smac != smac) { 1890 /* register candidate now, unreg if needed, after success */ 1891 smac_index = mlx4_register_mac(dev->dev, port, smac); 1892 if (smac_index >= 0) { 1893 smac_info->candidate_smac_index = smac_index; 1894 smac_info->candidate_smac = smac; 1895 smac_info->candidate_smac_port = port; 1896 } else { 1897 return -EINVAL; 1898 } 1899 } else { 1900 smac_index = smac_info->smac_index; 1901 } 1902 memcpy(path->dmac, ah->roce.dmac, 6); 1903 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1904 /* put MAC table smac index for IBoE */ 1905 path->grh_mylmc = (u8) (smac_index) | 0x80; 1906 } else { 1907 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1908 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1909 } 1910 1911 return 0; 1912 } 1913 1914 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1915 enum ib_qp_attr_mask qp_attr_mask, 1916 struct mlx4_ib_qp *mqp, 1917 struct mlx4_qp_path *path, u8 port, 1918 u16 vlan_id, u8 *smac) 1919 { 1920 return _mlx4_set_path(dev, &qp->ah_attr, 1921 mlx4_mac_to_u64(smac), 1922 vlan_id, 1923 path, &mqp->pri, port); 1924 } 1925 1926 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1927 const struct ib_qp_attr *qp, 1928 enum ib_qp_attr_mask qp_attr_mask, 1929 struct mlx4_ib_qp *mqp, 1930 struct mlx4_qp_path *path, u8 port) 1931 { 1932 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1933 0, 1934 0xffff, 1935 path, &mqp->alt, port); 1936 } 1937 1938 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1939 { 1940 struct mlx4_ib_gid_entry *ge, *tmp; 1941 1942 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1943 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1944 ge->added = 1; 1945 ge->port = qp->port; 1946 } 1947 } 1948 } 1949 1950 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1951 struct mlx4_ib_qp *qp, 1952 struct mlx4_qp_context *context) 1953 { 1954 u64 u64_mac; 1955 int smac_index; 1956 1957 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1958 1959 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1960 if (!qp->pri.smac && !qp->pri.smac_port) { 1961 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1962 if (smac_index >= 0) { 1963 qp->pri.candidate_smac_index = smac_index; 1964 qp->pri.candidate_smac = u64_mac; 1965 qp->pri.candidate_smac_port = qp->port; 1966 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1967 } else { 1968 return -ENOENT; 1969 } 1970 } 1971 return 0; 1972 } 1973 1974 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1975 { 1976 struct counter_index *new_counter_index; 1977 int err; 1978 u32 tmp_idx; 1979 1980 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1981 IB_LINK_LAYER_ETHERNET || 1982 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1983 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1984 return 0; 1985 1986 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1987 if (err) 1988 return err; 1989 1990 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1991 if (!new_counter_index) { 1992 mlx4_counter_free(dev->dev, tmp_idx); 1993 return -ENOMEM; 1994 } 1995 1996 new_counter_index->index = tmp_idx; 1997 new_counter_index->allocated = 1; 1998 qp->counter_index = new_counter_index; 1999 2000 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 2001 list_add_tail(&new_counter_index->list, 2002 &dev->counters_table[qp->port - 1].counters_list); 2003 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 2004 2005 return 0; 2006 } 2007 2008 enum { 2009 MLX4_QPC_ROCE_MODE_1 = 0, 2010 MLX4_QPC_ROCE_MODE_2 = 2, 2011 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 2012 }; 2013 2014 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 2015 { 2016 switch (gid_type) { 2017 case IB_GID_TYPE_ROCE: 2018 return MLX4_QPC_ROCE_MODE_1; 2019 case IB_GID_TYPE_ROCE_UDP_ENCAP: 2020 return MLX4_QPC_ROCE_MODE_2; 2021 default: 2022 return MLX4_QPC_ROCE_MODE_UNDEFINED; 2023 } 2024 } 2025 2026 /* 2027 * Go over all RSS QP's childes (WQs) and apply their HW state according to 2028 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 2029 */ 2030 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num) 2031 { 2032 int err = 0; 2033 int i; 2034 2035 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2036 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2037 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2038 2039 mutex_lock(&wq->mutex); 2040 2041 /* Mlx4_ib restrictions: 2042 * WQ's is associated to a port according to the RSS QP it is 2043 * associates to. 2044 * In case the WQ is associated to a different port by another 2045 * RSS QP, return a failure. 2046 */ 2047 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 2048 err = -EINVAL; 2049 mutex_unlock(&wq->mutex); 2050 break; 2051 } 2052 wq->port = port_num; 2053 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 2054 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY); 2055 if (err) { 2056 mutex_unlock(&wq->mutex); 2057 break; 2058 } 2059 } 2060 wq->rss_usecnt++; 2061 2062 mutex_unlock(&wq->mutex); 2063 } 2064 2065 if (i && err) { 2066 int j; 2067 2068 for (j = (i - 1); j >= 0; j--) { 2069 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 2070 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2071 2072 mutex_lock(&wq->mutex); 2073 2074 if ((wq->rss_usecnt == 1) && 2075 (ibwq->state == IB_WQS_RDY)) 2076 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 2077 pr_warn("failed to reverse WQN=0x%06x\n", 2078 ibwq->wq_num); 2079 wq->rss_usecnt--; 2080 2081 mutex_unlock(&wq->mutex); 2082 } 2083 } 2084 2085 return err; 2086 } 2087 2088 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl) 2089 { 2090 int i; 2091 2092 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2093 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2094 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2095 2096 mutex_lock(&wq->mutex); 2097 2098 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2099 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 2100 pr_warn("failed to reverse WQN=%x\n", 2101 ibwq->wq_num); 2102 wq->rss_usecnt--; 2103 2104 mutex_unlock(&wq->mutex); 2105 } 2106 } 2107 2108 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2109 struct mlx4_ib_qp *qp) 2110 { 2111 struct mlx4_rss_context *rss_context; 2112 2113 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2114 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2115 2116 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2117 rss_context->default_qpn = 2118 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2119 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2120 rss_context->base_qpn_udp = rss_context->default_qpn; 2121 rss_context->flags = qp->rss_ctx->flags; 2122 /* Currently support just toeplitz */ 2123 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2124 2125 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2126 MLX4_EN_RSS_KEY_SIZE); 2127 } 2128 2129 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2130 const struct ib_qp_attr *attr, int attr_mask, 2131 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2132 { 2133 struct ib_uobject *ibuobject; 2134 struct ib_srq *ibsrq; 2135 struct ib_rwq_ind_table *rwq_ind_tbl; 2136 enum ib_qp_type qp_type; 2137 struct mlx4_ib_dev *dev; 2138 struct mlx4_ib_qp *qp; 2139 struct mlx4_ib_pd *pd; 2140 struct mlx4_ib_cq *send_cq, *recv_cq; 2141 struct mlx4_qp_context *context; 2142 enum mlx4_qp_optpar optpar = 0; 2143 int sqd_event; 2144 int steer_qp = 0; 2145 int err = -EINVAL; 2146 int counter_index; 2147 2148 if (src_type == MLX4_IB_RWQ_SRC) { 2149 struct ib_wq *ibwq; 2150 2151 ibwq = (struct ib_wq *)src; 2152 ibuobject = ibwq->uobject; 2153 ibsrq = NULL; 2154 rwq_ind_tbl = NULL; 2155 qp_type = IB_QPT_RAW_PACKET; 2156 qp = to_mqp((struct ib_qp *)ibwq); 2157 dev = to_mdev(ibwq->device); 2158 pd = to_mpd(ibwq->pd); 2159 } else { 2160 struct ib_qp *ibqp; 2161 2162 ibqp = (struct ib_qp *)src; 2163 ibuobject = ibqp->uobject; 2164 ibsrq = ibqp->srq; 2165 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2166 qp_type = ibqp->qp_type; 2167 qp = to_mqp(ibqp); 2168 dev = to_mdev(ibqp->device); 2169 pd = get_pd(qp); 2170 } 2171 2172 /* APM is not supported under RoCE */ 2173 if (attr_mask & IB_QP_ALT_PATH && 2174 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2175 IB_LINK_LAYER_ETHERNET) 2176 return -ENOTSUPP; 2177 2178 context = kzalloc(sizeof *context, GFP_KERNEL); 2179 if (!context) 2180 return -ENOMEM; 2181 2182 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2183 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2184 2185 if (rwq_ind_tbl) { 2186 fill_qp_rss_context(context, qp); 2187 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2188 } 2189 2190 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2191 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2192 else { 2193 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2194 switch (attr->path_mig_state) { 2195 case IB_MIG_MIGRATED: 2196 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2197 break; 2198 case IB_MIG_REARM: 2199 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2200 break; 2201 case IB_MIG_ARMED: 2202 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2203 break; 2204 } 2205 } 2206 2207 if (qp->inl_recv_sz) 2208 context->param3 |= cpu_to_be32(1 << 25); 2209 2210 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2211 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2212 else if (qp_type == IB_QPT_RAW_PACKET) 2213 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2214 else if (qp_type == IB_QPT_UD) { 2215 if (qp->flags & MLX4_IB_QP_LSO) 2216 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2217 ilog2(dev->dev->caps.max_gso_sz); 2218 else 2219 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2220 } else if (attr_mask & IB_QP_PATH_MTU) { 2221 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2222 pr_err("path MTU (%u) is invalid\n", 2223 attr->path_mtu); 2224 goto out; 2225 } 2226 context->mtu_msgmax = (attr->path_mtu << 5) | 2227 ilog2(dev->dev->caps.max_msg_sz); 2228 } 2229 2230 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2231 if (qp->rq.wqe_cnt) 2232 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2233 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2234 } 2235 2236 if (qp->sq.wqe_cnt) 2237 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2238 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2239 2240 if (new_state == IB_QPS_RESET && qp->counter_index) 2241 mlx4_ib_free_qp_counter(dev, qp); 2242 2243 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2244 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2245 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2246 if (qp_type == IB_QPT_RAW_PACKET) 2247 context->param3 |= cpu_to_be32(1 << 30); 2248 } 2249 2250 if (ibuobject) 2251 context->usr_page = cpu_to_be32( 2252 mlx4_to_hw_uar_index(dev->dev, 2253 to_mucontext(ibuobject->context) 2254 ->uar.index)); 2255 else 2256 context->usr_page = cpu_to_be32( 2257 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2258 2259 if (attr_mask & IB_QP_DEST_QPN) 2260 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2261 2262 if (attr_mask & IB_QP_PORT) { 2263 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2264 !(attr_mask & IB_QP_AV)) { 2265 mlx4_set_sched(&context->pri_path, attr->port_num); 2266 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2267 } 2268 } 2269 2270 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2271 err = create_qp_lb_counter(dev, qp); 2272 if (err) 2273 goto out; 2274 2275 counter_index = 2276 dev->counters_table[qp->port - 1].default_counter; 2277 if (qp->counter_index) 2278 counter_index = qp->counter_index->index; 2279 2280 if (counter_index != -1) { 2281 context->pri_path.counter_index = counter_index; 2282 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2283 if (qp->counter_index) { 2284 context->pri_path.fl |= 2285 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2286 context->pri_path.vlan_control |= 2287 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2288 } 2289 } else 2290 context->pri_path.counter_index = 2291 MLX4_SINK_COUNTER_INDEX(dev->dev); 2292 2293 if (qp->flags & MLX4_IB_QP_NETIF) { 2294 mlx4_ib_steer_qp_reg(dev, qp, 1); 2295 steer_qp = 1; 2296 } 2297 2298 if (qp_type == IB_QPT_GSI) { 2299 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2300 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2301 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2302 2303 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2304 } 2305 } 2306 2307 if (attr_mask & IB_QP_PKEY_INDEX) { 2308 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2309 context->pri_path.disable_pkey_check = 0x40; 2310 context->pri_path.pkey_index = attr->pkey_index; 2311 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2312 } 2313 2314 if (attr_mask & IB_QP_AV) { 2315 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2316 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2317 union ib_gid gid; 2318 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB}; 2319 u16 vlan = 0xffff; 2320 u8 smac[ETH_ALEN]; 2321 int status = 0; 2322 int is_eth = 2323 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2324 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2325 2326 if (is_eth) { 2327 int index = 2328 rdma_ah_read_grh(&attr->ah_attr)->sgid_index; 2329 2330 status = ib_get_cached_gid(&dev->ib_dev, port_num, 2331 index, &gid, &gid_attr); 2332 if (!status && !memcmp(&gid, &zgid, sizeof(gid))) 2333 status = -ENOENT; 2334 if (!status && gid_attr.ndev) { 2335 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev); 2336 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN); 2337 dev_put(gid_attr.ndev); 2338 } 2339 } 2340 if (status) 2341 goto out; 2342 2343 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2344 port_num, vlan, smac)) 2345 goto out; 2346 2347 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2348 MLX4_QP_OPTPAR_SCHED_QUEUE); 2349 2350 if (is_eth && 2351 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2352 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type); 2353 2354 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2355 err = -EINVAL; 2356 goto out; 2357 } 2358 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2359 } 2360 2361 } 2362 2363 if (attr_mask & IB_QP_TIMEOUT) { 2364 context->pri_path.ackto |= attr->timeout << 3; 2365 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2366 } 2367 2368 if (attr_mask & IB_QP_ALT_PATH) { 2369 if (attr->alt_port_num == 0 || 2370 attr->alt_port_num > dev->dev->caps.num_ports) 2371 goto out; 2372 2373 if (attr->alt_pkey_index >= 2374 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2375 goto out; 2376 2377 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2378 &context->alt_path, 2379 attr->alt_port_num)) 2380 goto out; 2381 2382 context->alt_path.pkey_index = attr->alt_pkey_index; 2383 context->alt_path.ackto = attr->alt_timeout << 3; 2384 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2385 } 2386 2387 context->pd = cpu_to_be32(pd->pdn); 2388 2389 if (!rwq_ind_tbl) { 2390 get_cqs(qp, src_type, &send_cq, &recv_cq); 2391 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2392 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2393 recv_cq = send_cq; 2394 } 2395 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2396 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2397 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2398 2399 /* Set "fast registration enabled" for all kernel QPs */ 2400 if (!ibuobject) 2401 context->params1 |= cpu_to_be32(1 << 11); 2402 2403 if (attr_mask & IB_QP_RNR_RETRY) { 2404 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2405 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2406 } 2407 2408 if (attr_mask & IB_QP_RETRY_CNT) { 2409 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2410 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2411 } 2412 2413 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2414 if (attr->max_rd_atomic) 2415 context->params1 |= 2416 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2417 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2418 } 2419 2420 if (attr_mask & IB_QP_SQ_PSN) 2421 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2422 2423 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2424 if (attr->max_dest_rd_atomic) 2425 context->params2 |= 2426 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2427 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2428 } 2429 2430 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2431 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2432 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2433 } 2434 2435 if (ibsrq) 2436 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2437 2438 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2439 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2440 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2441 } 2442 if (attr_mask & IB_QP_RQ_PSN) 2443 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2444 2445 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2446 if (attr_mask & IB_QP_QKEY) { 2447 if (qp->mlx4_ib_qp_type & 2448 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2449 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2450 else { 2451 if (mlx4_is_mfunc(dev->dev) && 2452 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2453 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2454 MLX4_RESERVED_QKEY_BASE) { 2455 pr_err("Cannot use reserved QKEY" 2456 " 0x%x (range 0xffff0000..0xffffffff" 2457 " is reserved)\n", attr->qkey); 2458 err = -EINVAL; 2459 goto out; 2460 } 2461 context->qkey = cpu_to_be32(attr->qkey); 2462 } 2463 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2464 } 2465 2466 if (ibsrq) 2467 context->srqn = cpu_to_be32(1 << 24 | 2468 to_msrq(ibsrq)->msrq.srqn); 2469 2470 if (qp->rq.wqe_cnt && 2471 cur_state == IB_QPS_RESET && 2472 new_state == IB_QPS_INIT) 2473 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2474 2475 if (cur_state == IB_QPS_INIT && 2476 new_state == IB_QPS_RTR && 2477 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2478 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2479 context->pri_path.sched_queue = (qp->port - 1) << 6; 2480 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2481 qp->mlx4_ib_qp_type & 2482 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2483 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2484 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2485 context->pri_path.fl = 0x80; 2486 } else { 2487 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2488 context->pri_path.fl = 0x80; 2489 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2490 } 2491 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2492 IB_LINK_LAYER_ETHERNET) { 2493 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2494 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2495 context->pri_path.feup = 1 << 7; /* don't fsm */ 2496 /* handle smac_index */ 2497 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2498 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2499 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2500 err = handle_eth_ud_smac_index(dev, qp, context); 2501 if (err) { 2502 err = -EINVAL; 2503 goto out; 2504 } 2505 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2506 dev->qp1_proxy[qp->port - 1] = qp; 2507 } 2508 } 2509 } 2510 2511 if (qp_type == IB_QPT_RAW_PACKET) { 2512 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2513 MLX4_IB_LINK_TYPE_ETH; 2514 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2515 /* set QP to receive both tunneled & non-tunneled packets */ 2516 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET))) 2517 context->srqn = cpu_to_be32(7 << 28); 2518 } 2519 } 2520 2521 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2522 int is_eth = rdma_port_get_link_layer( 2523 &dev->ib_dev, qp->port) == 2524 IB_LINK_LAYER_ETHERNET; 2525 if (is_eth) { 2526 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2527 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2528 } 2529 } 2530 2531 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2532 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2533 sqd_event = 1; 2534 else 2535 sqd_event = 0; 2536 2537 if (!ibuobject && 2538 cur_state == IB_QPS_RESET && 2539 new_state == IB_QPS_INIT) 2540 context->rlkey_roce_mode |= (1 << 4); 2541 2542 /* 2543 * Before passing a kernel QP to the HW, make sure that the 2544 * ownership bits of the send queue are set and the SQ 2545 * headroom is stamped so that the hardware doesn't start 2546 * processing stale work requests. 2547 */ 2548 if (!ibuobject && 2549 cur_state == IB_QPS_RESET && 2550 new_state == IB_QPS_INIT) { 2551 struct mlx4_wqe_ctrl_seg *ctrl; 2552 int i; 2553 2554 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2555 ctrl = get_send_wqe(qp, i); 2556 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2557 if (qp->sq_max_wqes_per_wr == 1) 2558 ctrl->qpn_vlan.fence_size = 2559 1 << (qp->sq.wqe_shift - 4); 2560 2561 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 2562 } 2563 } 2564 2565 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2566 to_mlx4_state(new_state), context, optpar, 2567 sqd_event, &qp->mqp); 2568 if (err) 2569 goto out; 2570 2571 qp->state = new_state; 2572 2573 if (attr_mask & IB_QP_ACCESS_FLAGS) 2574 qp->atomic_rd_en = attr->qp_access_flags; 2575 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2576 qp->resp_depth = attr->max_dest_rd_atomic; 2577 if (attr_mask & IB_QP_PORT) { 2578 qp->port = attr->port_num; 2579 update_mcg_macs(dev, qp); 2580 } 2581 if (attr_mask & IB_QP_ALT_PATH) 2582 qp->alt_port = attr->alt_port_num; 2583 2584 if (is_sqp(dev, qp)) 2585 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2586 2587 /* 2588 * If we moved QP0 to RTR, bring the IB link up; if we moved 2589 * QP0 to RESET or ERROR, bring the link back down. 2590 */ 2591 if (is_qp0(dev, qp)) { 2592 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2593 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2594 pr_warn("INIT_PORT failed for port %d\n", 2595 qp->port); 2596 2597 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2598 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2599 mlx4_CLOSE_PORT(dev->dev, qp->port); 2600 } 2601 2602 /* 2603 * If we moved a kernel QP to RESET, clean up all old CQ 2604 * entries and reinitialize the QP. 2605 */ 2606 if (new_state == IB_QPS_RESET) { 2607 if (!ibuobject) { 2608 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2609 ibsrq ? to_msrq(ibsrq) : NULL); 2610 if (send_cq != recv_cq) 2611 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2612 2613 qp->rq.head = 0; 2614 qp->rq.tail = 0; 2615 qp->sq.head = 0; 2616 qp->sq.tail = 0; 2617 qp->sq_next_wqe = 0; 2618 if (qp->rq.wqe_cnt) 2619 *qp->db.db = 0; 2620 2621 if (qp->flags & MLX4_IB_QP_NETIF) 2622 mlx4_ib_steer_qp_reg(dev, qp, 0); 2623 } 2624 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2625 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2626 qp->pri.smac = 0; 2627 qp->pri.smac_port = 0; 2628 } 2629 if (qp->alt.smac) { 2630 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2631 qp->alt.smac = 0; 2632 } 2633 if (qp->pri.vid < 0x1000) { 2634 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2635 qp->pri.vid = 0xFFFF; 2636 qp->pri.candidate_vid = 0xFFFF; 2637 qp->pri.update_vid = 0; 2638 } 2639 2640 if (qp->alt.vid < 0x1000) { 2641 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2642 qp->alt.vid = 0xFFFF; 2643 qp->alt.candidate_vid = 0xFFFF; 2644 qp->alt.update_vid = 0; 2645 } 2646 } 2647 out: 2648 if (err && qp->counter_index) 2649 mlx4_ib_free_qp_counter(dev, qp); 2650 if (err && steer_qp) 2651 mlx4_ib_steer_qp_reg(dev, qp, 0); 2652 kfree(context); 2653 if (qp->pri.candidate_smac || 2654 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2655 if (err) { 2656 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2657 } else { 2658 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2659 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2660 qp->pri.smac = qp->pri.candidate_smac; 2661 qp->pri.smac_index = qp->pri.candidate_smac_index; 2662 qp->pri.smac_port = qp->pri.candidate_smac_port; 2663 } 2664 qp->pri.candidate_smac = 0; 2665 qp->pri.candidate_smac_index = 0; 2666 qp->pri.candidate_smac_port = 0; 2667 } 2668 if (qp->alt.candidate_smac) { 2669 if (err) { 2670 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2671 } else { 2672 if (qp->alt.smac) 2673 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2674 qp->alt.smac = qp->alt.candidate_smac; 2675 qp->alt.smac_index = qp->alt.candidate_smac_index; 2676 qp->alt.smac_port = qp->alt.candidate_smac_port; 2677 } 2678 qp->alt.candidate_smac = 0; 2679 qp->alt.candidate_smac_index = 0; 2680 qp->alt.candidate_smac_port = 0; 2681 } 2682 2683 if (qp->pri.update_vid) { 2684 if (err) { 2685 if (qp->pri.candidate_vid < 0x1000) 2686 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2687 qp->pri.candidate_vid); 2688 } else { 2689 if (qp->pri.vid < 0x1000) 2690 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2691 qp->pri.vid); 2692 qp->pri.vid = qp->pri.candidate_vid; 2693 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2694 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2695 } 2696 qp->pri.candidate_vid = 0xFFFF; 2697 qp->pri.update_vid = 0; 2698 } 2699 2700 if (qp->alt.update_vid) { 2701 if (err) { 2702 if (qp->alt.candidate_vid < 0x1000) 2703 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2704 qp->alt.candidate_vid); 2705 } else { 2706 if (qp->alt.vid < 0x1000) 2707 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2708 qp->alt.vid); 2709 qp->alt.vid = qp->alt.candidate_vid; 2710 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2711 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2712 } 2713 qp->alt.candidate_vid = 0xFFFF; 2714 qp->alt.update_vid = 0; 2715 } 2716 2717 return err; 2718 } 2719 2720 enum { 2721 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2722 IB_QP_PORT), 2723 }; 2724 2725 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2726 int attr_mask, struct ib_udata *udata) 2727 { 2728 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2729 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2730 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2731 enum ib_qp_state cur_state, new_state; 2732 int err = -EINVAL; 2733 mutex_lock(&qp->mutex); 2734 2735 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2736 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2737 2738 if (cur_state != new_state || cur_state != IB_QPS_RESET) { 2739 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2740 ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2741 } 2742 2743 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2744 attr_mask, ll)) { 2745 pr_debug("qpn 0x%x: invalid attribute mask specified " 2746 "for transition %d to %d. qp_type %d," 2747 " attr_mask 0x%x\n", 2748 ibqp->qp_num, cur_state, new_state, 2749 ibqp->qp_type, attr_mask); 2750 goto out; 2751 } 2752 2753 if (ibqp->rwq_ind_tbl) { 2754 if (!(((cur_state == IB_QPS_RESET) && 2755 (new_state == IB_QPS_INIT)) || 2756 ((cur_state == IB_QPS_INIT) && 2757 (new_state == IB_QPS_RTR)))) { 2758 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2759 ibqp->qp_num, cur_state, new_state); 2760 2761 err = -EOPNOTSUPP; 2762 goto out; 2763 } 2764 2765 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2766 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2767 ibqp->qp_num, attr_mask, cur_state, new_state); 2768 2769 err = -EOPNOTSUPP; 2770 goto out; 2771 } 2772 } 2773 2774 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2775 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2776 if ((ibqp->qp_type == IB_QPT_RC) || 2777 (ibqp->qp_type == IB_QPT_UD) || 2778 (ibqp->qp_type == IB_QPT_UC) || 2779 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2780 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2781 attr->port_num = mlx4_ib_bond_next_port(dev); 2782 } 2783 } else { 2784 /* no sense in changing port_num 2785 * when ports are bonded */ 2786 attr_mask &= ~IB_QP_PORT; 2787 } 2788 } 2789 2790 if ((attr_mask & IB_QP_PORT) && 2791 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2792 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2793 "for transition %d to %d. qp_type %d\n", 2794 ibqp->qp_num, attr->port_num, cur_state, 2795 new_state, ibqp->qp_type); 2796 goto out; 2797 } 2798 2799 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2800 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2801 IB_LINK_LAYER_ETHERNET)) 2802 goto out; 2803 2804 if (attr_mask & IB_QP_PKEY_INDEX) { 2805 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2806 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2807 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2808 "for transition %d to %d. qp_type %d\n", 2809 ibqp->qp_num, attr->pkey_index, cur_state, 2810 new_state, ibqp->qp_type); 2811 goto out; 2812 } 2813 } 2814 2815 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2816 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2817 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2818 "Transition %d to %d. qp_type %d\n", 2819 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2820 new_state, ibqp->qp_type); 2821 goto out; 2822 } 2823 2824 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2825 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2826 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2827 "Transition %d to %d. qp_type %d\n", 2828 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2829 new_state, ibqp->qp_type); 2830 goto out; 2831 } 2832 2833 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2834 err = 0; 2835 goto out; 2836 } 2837 2838 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2839 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num); 2840 if (err) 2841 goto out; 2842 } 2843 2844 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2845 cur_state, new_state); 2846 2847 if (ibqp->rwq_ind_tbl && err) 2848 bring_down_rss_rwqs(ibqp->rwq_ind_tbl); 2849 2850 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2851 attr->port_num = 1; 2852 2853 out: 2854 mutex_unlock(&qp->mutex); 2855 return err; 2856 } 2857 2858 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2859 int attr_mask, struct ib_udata *udata) 2860 { 2861 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2862 int ret; 2863 2864 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2865 2866 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2867 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2868 int err = 0; 2869 2870 if (sqp->roce_v2_gsi) 2871 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2872 if (err) 2873 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2874 err); 2875 } 2876 return ret; 2877 } 2878 2879 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2880 { 2881 int i; 2882 for (i = 0; i < dev->caps.num_ports; i++) { 2883 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2884 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2885 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2886 return 0; 2887 } 2888 } 2889 return -EINVAL; 2890 } 2891 2892 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2893 struct ib_ud_wr *wr, 2894 void *wqe, unsigned *mlx_seg_len) 2895 { 2896 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2897 struct ib_device *ib_dev = &mdev->ib_dev; 2898 struct mlx4_wqe_mlx_seg *mlx = wqe; 2899 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2900 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2901 u16 pkey; 2902 u32 qkey; 2903 int send_size; 2904 int header_size; 2905 int spc; 2906 int i; 2907 2908 if (wr->wr.opcode != IB_WR_SEND) 2909 return -EINVAL; 2910 2911 send_size = 0; 2912 2913 for (i = 0; i < wr->wr.num_sge; ++i) 2914 send_size += wr->wr.sg_list[i].length; 2915 2916 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2917 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2918 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2919 send_size += sizeof (struct mlx4_ib_tunnel_header); 2920 2921 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2922 2923 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2924 sqp->ud_header.lrh.service_level = 2925 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2926 sqp->ud_header.lrh.destination_lid = 2927 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2928 sqp->ud_header.lrh.source_lid = 2929 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2930 } 2931 2932 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2933 2934 /* force loopback */ 2935 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2936 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2937 2938 sqp->ud_header.lrh.virtual_lane = 0; 2939 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2940 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2941 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2942 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2943 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2944 else 2945 sqp->ud_header.bth.destination_qpn = 2946 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel); 2947 2948 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2949 if (mlx4_is_master(mdev->dev)) { 2950 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2951 return -EINVAL; 2952 } else { 2953 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2954 return -EINVAL; 2955 } 2956 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2957 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2958 2959 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2960 sqp->ud_header.immediate_present = 0; 2961 2962 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2963 2964 /* 2965 * Inline data segments may not cross a 64 byte boundary. If 2966 * our UD header is bigger than the space available up to the 2967 * next 64 byte boundary in the WQE, use two inline data 2968 * segments to hold the UD header. 2969 */ 2970 spc = MLX4_INLINE_ALIGN - 2971 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2972 if (header_size <= spc) { 2973 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2974 memcpy(inl + 1, sqp->header_buf, header_size); 2975 i = 1; 2976 } else { 2977 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2978 memcpy(inl + 1, sqp->header_buf, spc); 2979 2980 inl = (void *) (inl + 1) + spc; 2981 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2982 /* 2983 * Need a barrier here to make sure all the data is 2984 * visible before the byte_count field is set. 2985 * Otherwise the HCA prefetcher could grab the 64-byte 2986 * chunk with this inline segment and get a valid (!= 2987 * 0xffffffff) byte count but stale data, and end up 2988 * generating a packet with bad headers. 2989 * 2990 * The first inline segment's byte_count field doesn't 2991 * need a barrier, because it comes after a 2992 * control/MLX segment and therefore is at an offset 2993 * of 16 mod 64. 2994 */ 2995 wmb(); 2996 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2997 i = 2; 2998 } 2999 3000 *mlx_seg_len = 3001 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3002 return 0; 3003 } 3004 3005 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 3006 { 3007 union sl2vl_tbl_to_u64 tmp_vltab; 3008 u8 vl; 3009 3010 if (sl > 15) 3011 return 0xf; 3012 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 3013 vl = tmp_vltab.sl8[sl >> 1]; 3014 if (sl & 1) 3015 vl &= 0x0f; 3016 else 3017 vl >>= 4; 3018 return vl; 3019 } 3020 3021 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 3022 int index, union ib_gid *gid, 3023 enum ib_gid_type *gid_type) 3024 { 3025 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 3026 struct mlx4_port_gid_table *port_gid_table; 3027 unsigned long flags; 3028 3029 port_gid_table = &iboe->gids[port_num - 1]; 3030 spin_lock_irqsave(&iboe->lock, flags); 3031 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 3032 *gid_type = port_gid_table->gids[index].gid_type; 3033 spin_unlock_irqrestore(&iboe->lock, flags); 3034 if (!memcmp(gid, &zgid, sizeof(*gid))) 3035 return -ENOENT; 3036 3037 return 0; 3038 } 3039 3040 #define MLX4_ROCEV2_QP1_SPORT 0xC000 3041 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr, 3042 void *wqe, unsigned *mlx_seg_len) 3043 { 3044 struct ib_device *ib_dev = sqp->qp.ibqp.device; 3045 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 3046 struct mlx4_wqe_mlx_seg *mlx = wqe; 3047 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 3048 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 3049 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3050 union ib_gid sgid; 3051 u16 pkey; 3052 int send_size; 3053 int header_size; 3054 int spc; 3055 int i; 3056 int err = 0; 3057 u16 vlan = 0xffff; 3058 bool is_eth; 3059 bool is_vlan = false; 3060 bool is_grh; 3061 bool is_udp = false; 3062 int ip_version = 0; 3063 3064 send_size = 0; 3065 for (i = 0; i < wr->wr.num_sge; ++i) 3066 send_size += wr->wr.sg_list[i].length; 3067 3068 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 3069 is_grh = mlx4_ib_ah_grh_present(ah); 3070 if (is_eth) { 3071 enum ib_gid_type gid_type; 3072 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3073 /* When multi-function is enabled, the ib_core gid 3074 * indexes don't necessarily match the hw ones, so 3075 * we must use our own cache */ 3076 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 3077 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3078 ah->av.ib.gid_index, &sgid.raw[0]); 3079 if (err) 3080 return err; 3081 } else { 3082 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 3083 ah->av.ib.gid_index, 3084 &sgid, &gid_type); 3085 if (!err) { 3086 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3087 if (is_udp) { 3088 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3089 ip_version = 4; 3090 else 3091 ip_version = 6; 3092 is_grh = false; 3093 } 3094 } else { 3095 return err; 3096 } 3097 } 3098 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3099 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3100 is_vlan = 1; 3101 } 3102 } 3103 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3104 ip_version, is_udp, 0, &sqp->ud_header); 3105 if (err) 3106 return err; 3107 3108 if (!is_eth) { 3109 sqp->ud_header.lrh.service_level = 3110 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3111 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3112 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3113 } 3114 3115 if (is_grh || (ip_version == 6)) { 3116 sqp->ud_header.grh.traffic_class = 3117 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3118 sqp->ud_header.grh.flow_label = 3119 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3120 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3121 if (is_eth) { 3122 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3123 } else { 3124 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3125 /* When multi-function is enabled, the ib_core gid 3126 * indexes don't necessarily match the hw ones, so 3127 * we must use our own cache 3128 */ 3129 sqp->ud_header.grh.source_gid.global.subnet_prefix = 3130 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 3131 demux[sqp->qp.port - 1]. 3132 subnet_prefix))); 3133 sqp->ud_header.grh.source_gid.global.interface_id = 3134 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 3135 guid_cache[ah->av.ib.gid_index]; 3136 } else { 3137 ib_get_cached_gid(ib_dev, 3138 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3139 ah->av.ib.gid_index, 3140 &sqp->ud_header.grh.source_gid, NULL); 3141 } 3142 } 3143 memcpy(sqp->ud_header.grh.destination_gid.raw, 3144 ah->av.ib.dgid, 16); 3145 } 3146 3147 if (ip_version == 4) { 3148 sqp->ud_header.ip4.tos = 3149 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3150 sqp->ud_header.ip4.id = 0; 3151 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3152 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3153 3154 memcpy(&sqp->ud_header.ip4.saddr, 3155 sgid.raw + 12, 4); 3156 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3157 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3158 } 3159 3160 if (is_udp) { 3161 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3162 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3163 sqp->ud_header.udp.csum = 0; 3164 } 3165 3166 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3167 3168 if (!is_eth) { 3169 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3170 (sqp->ud_header.lrh.destination_lid == 3171 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 3172 (sqp->ud_header.lrh.service_level << 8)); 3173 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3174 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3175 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3176 } 3177 3178 switch (wr->wr.opcode) { 3179 case IB_WR_SEND: 3180 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3181 sqp->ud_header.immediate_present = 0; 3182 break; 3183 case IB_WR_SEND_WITH_IMM: 3184 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3185 sqp->ud_header.immediate_present = 1; 3186 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3187 break; 3188 default: 3189 return -EINVAL; 3190 } 3191 3192 if (is_eth) { 3193 struct in6_addr in6; 3194 u16 ether_type; 3195 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3196 3197 ether_type = (!is_udp) ? ETH_P_IBOE: 3198 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3199 3200 mlx->sched_prio = cpu_to_be16(pcp); 3201 3202 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3203 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 3204 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3205 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3206 memcpy(&in6, sgid.raw, sizeof(in6)); 3207 3208 3209 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3210 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3211 if (!is_vlan) { 3212 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3213 } else { 3214 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3215 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3216 } 3217 } else { 3218 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 3219 sl_to_vl(to_mdev(ib_dev), 3220 sqp->ud_header.lrh.service_level, 3221 sqp->qp.port); 3222 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3223 return -EINVAL; 3224 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3225 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3226 } 3227 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3228 if (!sqp->qp.ibqp.qp_num) 3229 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 3230 else 3231 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 3232 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3233 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3234 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3235 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3236 sqp->qkey : wr->remote_qkey); 3237 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 3238 3239 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3240 3241 if (0) { 3242 pr_err("built UD header of size %d:\n", header_size); 3243 for (i = 0; i < header_size / 4; ++i) { 3244 if (i % 8 == 0) 3245 pr_err(" [%02x] ", i * 4); 3246 pr_cont(" %08x", 3247 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3248 if ((i + 1) % 8 == 0) 3249 pr_cont("\n"); 3250 } 3251 pr_err("\n"); 3252 } 3253 3254 /* 3255 * Inline data segments may not cross a 64 byte boundary. If 3256 * our UD header is bigger than the space available up to the 3257 * next 64 byte boundary in the WQE, use two inline data 3258 * segments to hold the UD header. 3259 */ 3260 spc = MLX4_INLINE_ALIGN - 3261 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3262 if (header_size <= spc) { 3263 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3264 memcpy(inl + 1, sqp->header_buf, header_size); 3265 i = 1; 3266 } else { 3267 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3268 memcpy(inl + 1, sqp->header_buf, spc); 3269 3270 inl = (void *) (inl + 1) + spc; 3271 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3272 /* 3273 * Need a barrier here to make sure all the data is 3274 * visible before the byte_count field is set. 3275 * Otherwise the HCA prefetcher could grab the 64-byte 3276 * chunk with this inline segment and get a valid (!= 3277 * 0xffffffff) byte count but stale data, and end up 3278 * generating a packet with bad headers. 3279 * 3280 * The first inline segment's byte_count field doesn't 3281 * need a barrier, because it comes after a 3282 * control/MLX segment and therefore is at an offset 3283 * of 16 mod 64. 3284 */ 3285 wmb(); 3286 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3287 i = 2; 3288 } 3289 3290 *mlx_seg_len = 3291 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3292 return 0; 3293 } 3294 3295 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3296 { 3297 unsigned cur; 3298 struct mlx4_ib_cq *cq; 3299 3300 cur = wq->head - wq->tail; 3301 if (likely(cur + nreq < wq->max_post)) 3302 return 0; 3303 3304 cq = to_mcq(ib_cq); 3305 spin_lock(&cq->lock); 3306 cur = wq->head - wq->tail; 3307 spin_unlock(&cq->lock); 3308 3309 return cur + nreq >= wq->max_post; 3310 } 3311 3312 static __be32 convert_access(int acc) 3313 { 3314 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3315 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3316 (acc & IB_ACCESS_REMOTE_WRITE ? 3317 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3318 (acc & IB_ACCESS_REMOTE_READ ? 3319 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3320 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3321 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3322 } 3323 3324 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3325 struct ib_reg_wr *wr) 3326 { 3327 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3328 3329 fseg->flags = convert_access(wr->access); 3330 fseg->mem_key = cpu_to_be32(wr->key); 3331 fseg->buf_list = cpu_to_be64(mr->page_map); 3332 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3333 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3334 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3335 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3336 fseg->reserved[0] = 0; 3337 fseg->reserved[1] = 0; 3338 } 3339 3340 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3341 { 3342 memset(iseg, 0, sizeof(*iseg)); 3343 iseg->mem_key = cpu_to_be32(rkey); 3344 } 3345 3346 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3347 u64 remote_addr, u32 rkey) 3348 { 3349 rseg->raddr = cpu_to_be64(remote_addr); 3350 rseg->rkey = cpu_to_be32(rkey); 3351 rseg->reserved = 0; 3352 } 3353 3354 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3355 struct ib_atomic_wr *wr) 3356 { 3357 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3358 aseg->swap_add = cpu_to_be64(wr->swap); 3359 aseg->compare = cpu_to_be64(wr->compare_add); 3360 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3361 aseg->swap_add = cpu_to_be64(wr->compare_add); 3362 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3363 } else { 3364 aseg->swap_add = cpu_to_be64(wr->compare_add); 3365 aseg->compare = 0; 3366 } 3367 3368 } 3369 3370 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3371 struct ib_atomic_wr *wr) 3372 { 3373 aseg->swap_add = cpu_to_be64(wr->swap); 3374 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3375 aseg->compare = cpu_to_be64(wr->compare_add); 3376 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3377 } 3378 3379 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3380 struct ib_ud_wr *wr) 3381 { 3382 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3383 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3384 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3385 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3386 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3387 } 3388 3389 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3390 struct mlx4_wqe_datagram_seg *dseg, 3391 struct ib_ud_wr *wr, 3392 enum mlx4_ib_qp_type qpt) 3393 { 3394 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3395 struct mlx4_av sqp_av = {0}; 3396 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3397 3398 /* force loopback */ 3399 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3400 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3401 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3402 cpu_to_be32(0xf0000000); 3403 3404 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3405 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3406 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3407 else 3408 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3409 /* Use QKEY from the QP context, which is set by master */ 3410 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3411 } 3412 3413 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len) 3414 { 3415 struct mlx4_wqe_inline_seg *inl = wqe; 3416 struct mlx4_ib_tunnel_header hdr; 3417 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3418 int spc; 3419 int i; 3420 3421 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3422 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3423 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3424 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3425 memcpy(hdr.mac, ah->av.eth.mac, 6); 3426 hdr.vlan = ah->av.eth.vlan; 3427 3428 spc = MLX4_INLINE_ALIGN - 3429 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3430 if (sizeof (hdr) <= spc) { 3431 memcpy(inl + 1, &hdr, sizeof (hdr)); 3432 wmb(); 3433 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3434 i = 1; 3435 } else { 3436 memcpy(inl + 1, &hdr, spc); 3437 wmb(); 3438 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3439 3440 inl = (void *) (inl + 1) + spc; 3441 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3442 wmb(); 3443 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3444 i = 2; 3445 } 3446 3447 *mlx_seg_len = 3448 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3449 } 3450 3451 static void set_mlx_icrc_seg(void *dseg) 3452 { 3453 u32 *t = dseg; 3454 struct mlx4_wqe_inline_seg *iseg = dseg; 3455 3456 t[1] = 0; 3457 3458 /* 3459 * Need a barrier here before writing the byte_count field to 3460 * make sure that all the data is visible before the 3461 * byte_count field is set. Otherwise, if the segment begins 3462 * a new cacheline, the HCA prefetcher could grab the 64-byte 3463 * chunk and get a valid (!= * 0xffffffff) byte count but 3464 * stale data, and end up sending the wrong data. 3465 */ 3466 wmb(); 3467 3468 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3469 } 3470 3471 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3472 { 3473 dseg->lkey = cpu_to_be32(sg->lkey); 3474 dseg->addr = cpu_to_be64(sg->addr); 3475 3476 /* 3477 * Need a barrier here before writing the byte_count field to 3478 * make sure that all the data is visible before the 3479 * byte_count field is set. Otherwise, if the segment begins 3480 * a new cacheline, the HCA prefetcher could grab the 64-byte 3481 * chunk and get a valid (!= * 0xffffffff) byte count but 3482 * stale data, and end up sending the wrong data. 3483 */ 3484 wmb(); 3485 3486 dseg->byte_count = cpu_to_be32(sg->length); 3487 } 3488 3489 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3490 { 3491 dseg->byte_count = cpu_to_be32(sg->length); 3492 dseg->lkey = cpu_to_be32(sg->lkey); 3493 dseg->addr = cpu_to_be64(sg->addr); 3494 } 3495 3496 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr, 3497 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 3498 __be32 *lso_hdr_sz, __be32 *blh) 3499 { 3500 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3501 3502 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3503 *blh = cpu_to_be32(1 << 6); 3504 3505 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3506 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3507 return -EINVAL; 3508 3509 memcpy(wqe->header, wr->header, wr->hlen); 3510 3511 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3512 *lso_seg_len = halign; 3513 return 0; 3514 } 3515 3516 static __be32 send_ieth(struct ib_send_wr *wr) 3517 { 3518 switch (wr->opcode) { 3519 case IB_WR_SEND_WITH_IMM: 3520 case IB_WR_RDMA_WRITE_WITH_IMM: 3521 return wr->ex.imm_data; 3522 3523 case IB_WR_SEND_WITH_INV: 3524 return cpu_to_be32(wr->ex.invalidate_rkey); 3525 3526 default: 3527 return 0; 3528 } 3529 } 3530 3531 static void add_zero_len_inline(void *wqe) 3532 { 3533 struct mlx4_wqe_inline_seg *inl = wqe; 3534 memset(wqe, 0, 16); 3535 inl->byte_count = cpu_to_be32(1 << 31); 3536 } 3537 3538 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3539 struct ib_send_wr **bad_wr) 3540 { 3541 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3542 void *wqe; 3543 struct mlx4_wqe_ctrl_seg *ctrl; 3544 struct mlx4_wqe_data_seg *dseg; 3545 unsigned long flags; 3546 int nreq; 3547 int err = 0; 3548 unsigned ind; 3549 int uninitialized_var(stamp); 3550 int uninitialized_var(size); 3551 unsigned uninitialized_var(seglen); 3552 __be32 dummy; 3553 __be32 *lso_wqe; 3554 __be32 uninitialized_var(lso_hdr_sz); 3555 __be32 blh; 3556 int i; 3557 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3558 3559 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3560 struct mlx4_ib_sqp *sqp = to_msqp(qp); 3561 3562 if (sqp->roce_v2_gsi) { 3563 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3564 enum ib_gid_type gid_type; 3565 union ib_gid gid; 3566 3567 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 3568 ah->av.ib.gid_index, 3569 &gid, &gid_type)) 3570 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3571 to_mqp(sqp->roce_v2_gsi) : qp; 3572 else 3573 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3574 ah->av.ib.gid_index); 3575 } 3576 } 3577 3578 spin_lock_irqsave(&qp->sq.lock, flags); 3579 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3580 err = -EIO; 3581 *bad_wr = wr; 3582 nreq = 0; 3583 goto out; 3584 } 3585 3586 ind = qp->sq_next_wqe; 3587 3588 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3589 lso_wqe = &dummy; 3590 blh = 0; 3591 3592 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3593 err = -ENOMEM; 3594 *bad_wr = wr; 3595 goto out; 3596 } 3597 3598 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3599 err = -EINVAL; 3600 *bad_wr = wr; 3601 goto out; 3602 } 3603 3604 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3605 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3606 3607 ctrl->srcrb_flags = 3608 (wr->send_flags & IB_SEND_SIGNALED ? 3609 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3610 (wr->send_flags & IB_SEND_SOLICITED ? 3611 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3612 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3613 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3614 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3615 qp->sq_signal_bits; 3616 3617 ctrl->imm = send_ieth(wr); 3618 3619 wqe += sizeof *ctrl; 3620 size = sizeof *ctrl / 16; 3621 3622 switch (qp->mlx4_ib_qp_type) { 3623 case MLX4_IB_QPT_RC: 3624 case MLX4_IB_QPT_UC: 3625 switch (wr->opcode) { 3626 case IB_WR_ATOMIC_CMP_AND_SWP: 3627 case IB_WR_ATOMIC_FETCH_AND_ADD: 3628 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3629 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3630 atomic_wr(wr)->rkey); 3631 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3632 3633 set_atomic_seg(wqe, atomic_wr(wr)); 3634 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3635 3636 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3637 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3638 3639 break; 3640 3641 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3642 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3643 atomic_wr(wr)->rkey); 3644 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3645 3646 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3647 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3648 3649 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3650 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3651 3652 break; 3653 3654 case IB_WR_RDMA_READ: 3655 case IB_WR_RDMA_WRITE: 3656 case IB_WR_RDMA_WRITE_WITH_IMM: 3657 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3658 rdma_wr(wr)->rkey); 3659 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3660 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3661 break; 3662 3663 case IB_WR_LOCAL_INV: 3664 ctrl->srcrb_flags |= 3665 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3666 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3667 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3668 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3669 break; 3670 3671 case IB_WR_REG_MR: 3672 ctrl->srcrb_flags |= 3673 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3674 set_reg_seg(wqe, reg_wr(wr)); 3675 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3676 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3677 break; 3678 3679 default: 3680 /* No extra segments required for sends */ 3681 break; 3682 } 3683 break; 3684 3685 case MLX4_IB_QPT_TUN_SMI_OWNER: 3686 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3687 ctrl, &seglen); 3688 if (unlikely(err)) { 3689 *bad_wr = wr; 3690 goto out; 3691 } 3692 wqe += seglen; 3693 size += seglen / 16; 3694 break; 3695 case MLX4_IB_QPT_TUN_SMI: 3696 case MLX4_IB_QPT_TUN_GSI: 3697 /* this is a UD qp used in MAD responses to slaves. */ 3698 set_datagram_seg(wqe, ud_wr(wr)); 3699 /* set the forced-loopback bit in the data seg av */ 3700 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3701 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3702 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3703 break; 3704 case MLX4_IB_QPT_UD: 3705 set_datagram_seg(wqe, ud_wr(wr)); 3706 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3707 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3708 3709 if (wr->opcode == IB_WR_LSO) { 3710 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3711 &lso_hdr_sz, &blh); 3712 if (unlikely(err)) { 3713 *bad_wr = wr; 3714 goto out; 3715 } 3716 lso_wqe = (__be32 *) wqe; 3717 wqe += seglen; 3718 size += seglen / 16; 3719 } 3720 break; 3721 3722 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3723 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3724 ctrl, &seglen); 3725 if (unlikely(err)) { 3726 *bad_wr = wr; 3727 goto out; 3728 } 3729 wqe += seglen; 3730 size += seglen / 16; 3731 /* to start tunnel header on a cache-line boundary */ 3732 add_zero_len_inline(wqe); 3733 wqe += 16; 3734 size++; 3735 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3736 wqe += seglen; 3737 size += seglen / 16; 3738 break; 3739 case MLX4_IB_QPT_PROXY_SMI: 3740 case MLX4_IB_QPT_PROXY_GSI: 3741 /* If we are tunneling special qps, this is a UD qp. 3742 * In this case we first add a UD segment targeting 3743 * the tunnel qp, and then add a header with address 3744 * information */ 3745 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3746 ud_wr(wr), 3747 qp->mlx4_ib_qp_type); 3748 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3749 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3750 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3751 wqe += seglen; 3752 size += seglen / 16; 3753 break; 3754 3755 case MLX4_IB_QPT_SMI: 3756 case MLX4_IB_QPT_GSI: 3757 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3758 &seglen); 3759 if (unlikely(err)) { 3760 *bad_wr = wr; 3761 goto out; 3762 } 3763 wqe += seglen; 3764 size += seglen / 16; 3765 break; 3766 3767 default: 3768 break; 3769 } 3770 3771 /* 3772 * Write data segments in reverse order, so as to 3773 * overwrite cacheline stamp last within each 3774 * cacheline. This avoids issues with WQE 3775 * prefetching. 3776 */ 3777 3778 dseg = wqe; 3779 dseg += wr->num_sge - 1; 3780 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3781 3782 /* Add one more inline data segment for ICRC for MLX sends */ 3783 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3784 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3785 qp->mlx4_ib_qp_type & 3786 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3787 set_mlx_icrc_seg(dseg + 1); 3788 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3789 } 3790 3791 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3792 set_data_seg(dseg, wr->sg_list + i); 3793 3794 /* 3795 * Possibly overwrite stamping in cacheline with LSO 3796 * segment only after making sure all data segments 3797 * are written. 3798 */ 3799 wmb(); 3800 *lso_wqe = lso_hdr_sz; 3801 3802 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3803 MLX4_WQE_CTRL_FENCE : 0) | size; 3804 3805 /* 3806 * Make sure descriptor is fully written before 3807 * setting ownership bit (because HW can start 3808 * executing as soon as we do). 3809 */ 3810 wmb(); 3811 3812 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3813 *bad_wr = wr; 3814 err = -EINVAL; 3815 goto out; 3816 } 3817 3818 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3819 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3820 3821 stamp = ind + qp->sq_spare_wqes; 3822 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3823 3824 /* 3825 * We can improve latency by not stamping the last 3826 * send queue WQE until after ringing the doorbell, so 3827 * only stamp here if there are still more WQEs to post. 3828 * 3829 * Same optimization applies to padding with NOP wqe 3830 * in case of WQE shrinking (used to prevent wrap-around 3831 * in the middle of WR). 3832 */ 3833 if (wr->next) { 3834 stamp_send_wqe(qp, stamp, size * 16); 3835 ind = pad_wraparound(qp, ind); 3836 } 3837 } 3838 3839 out: 3840 if (likely(nreq)) { 3841 qp->sq.head += nreq; 3842 3843 /* 3844 * Make sure that descriptors are written before 3845 * doorbell record. 3846 */ 3847 wmb(); 3848 3849 writel(qp->doorbell_qpn, 3850 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3851 3852 /* 3853 * Make sure doorbells don't leak out of SQ spinlock 3854 * and reach the HCA out of order. 3855 */ 3856 mmiowb(); 3857 3858 stamp_send_wqe(qp, stamp, size * 16); 3859 3860 ind = pad_wraparound(qp, ind); 3861 qp->sq_next_wqe = ind; 3862 } 3863 3864 spin_unlock_irqrestore(&qp->sq.lock, flags); 3865 3866 return err; 3867 } 3868 3869 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3870 struct ib_recv_wr **bad_wr) 3871 { 3872 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3873 struct mlx4_wqe_data_seg *scat; 3874 unsigned long flags; 3875 int err = 0; 3876 int nreq; 3877 int ind; 3878 int max_gs; 3879 int i; 3880 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3881 3882 max_gs = qp->rq.max_gs; 3883 spin_lock_irqsave(&qp->rq.lock, flags); 3884 3885 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3886 err = -EIO; 3887 *bad_wr = wr; 3888 nreq = 0; 3889 goto out; 3890 } 3891 3892 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3893 3894 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3895 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3896 err = -ENOMEM; 3897 *bad_wr = wr; 3898 goto out; 3899 } 3900 3901 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3902 err = -EINVAL; 3903 *bad_wr = wr; 3904 goto out; 3905 } 3906 3907 scat = get_recv_wqe(qp, ind); 3908 3909 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3910 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3911 ib_dma_sync_single_for_device(ibqp->device, 3912 qp->sqp_proxy_rcv[ind].map, 3913 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3914 DMA_FROM_DEVICE); 3915 scat->byte_count = 3916 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3917 /* use dma lkey from upper layer entry */ 3918 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3919 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3920 scat++; 3921 max_gs--; 3922 } 3923 3924 for (i = 0; i < wr->num_sge; ++i) 3925 __set_data_seg(scat + i, wr->sg_list + i); 3926 3927 if (i < max_gs) { 3928 scat[i].byte_count = 0; 3929 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3930 scat[i].addr = 0; 3931 } 3932 3933 qp->rq.wrid[ind] = wr->wr_id; 3934 3935 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3936 } 3937 3938 out: 3939 if (likely(nreq)) { 3940 qp->rq.head += nreq; 3941 3942 /* 3943 * Make sure that descriptors are written before 3944 * doorbell record. 3945 */ 3946 wmb(); 3947 3948 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3949 } 3950 3951 spin_unlock_irqrestore(&qp->rq.lock, flags); 3952 3953 return err; 3954 } 3955 3956 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3957 { 3958 switch (mlx4_state) { 3959 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3960 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3961 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3962 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3963 case MLX4_QP_STATE_SQ_DRAINING: 3964 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3965 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3966 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3967 default: return -1; 3968 } 3969 } 3970 3971 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3972 { 3973 switch (mlx4_mig_state) { 3974 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3975 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3976 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3977 default: return -1; 3978 } 3979 } 3980 3981 static int to_ib_qp_access_flags(int mlx4_flags) 3982 { 3983 int ib_flags = 0; 3984 3985 if (mlx4_flags & MLX4_QP_BIT_RRE) 3986 ib_flags |= IB_ACCESS_REMOTE_READ; 3987 if (mlx4_flags & MLX4_QP_BIT_RWE) 3988 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3989 if (mlx4_flags & MLX4_QP_BIT_RAE) 3990 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3991 3992 return ib_flags; 3993 } 3994 3995 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3996 struct rdma_ah_attr *ah_attr, 3997 struct mlx4_qp_path *path) 3998 { 3999 struct mlx4_dev *dev = ibdev->dev; 4000 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 4001 4002 memset(ah_attr, 0, sizeof(*ah_attr)); 4003 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 4004 if (port_num == 0 || port_num > dev->caps.num_ports) 4005 return; 4006 4007 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 4008 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 4009 ((path->sched_queue & 4) << 1)); 4010 else 4011 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 4012 rdma_ah_set_port_num(ah_attr, port_num); 4013 4014 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4015 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 4016 rdma_ah_set_static_rate(ah_attr, 4017 path->static_rate ? path->static_rate - 5 : 0); 4018 if (path->grh_mylmc & (1 << 7)) { 4019 rdma_ah_set_grh(ah_attr, NULL, 4020 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 4021 path->mgid_index, 4022 path->hop_limit, 4023 (be32_to_cpu(path->tclass_flowlabel) 4024 >> 20) & 0xff); 4025 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4026 } 4027 } 4028 4029 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 4030 struct ib_qp_init_attr *qp_init_attr) 4031 { 4032 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 4033 struct mlx4_ib_qp *qp = to_mqp(ibqp); 4034 struct mlx4_qp_context context; 4035 int mlx4_state; 4036 int err = 0; 4037 4038 if (ibqp->rwq_ind_tbl) 4039 return -EOPNOTSUPP; 4040 4041 mutex_lock(&qp->mutex); 4042 4043 if (qp->state == IB_QPS_RESET) { 4044 qp_attr->qp_state = IB_QPS_RESET; 4045 goto done; 4046 } 4047 4048 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 4049 if (err) { 4050 err = -EINVAL; 4051 goto out; 4052 } 4053 4054 mlx4_state = be32_to_cpu(context.flags) >> 28; 4055 4056 qp->state = to_ib_qp_state(mlx4_state); 4057 qp_attr->qp_state = qp->state; 4058 qp_attr->path_mtu = context.mtu_msgmax >> 5; 4059 qp_attr->path_mig_state = 4060 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 4061 qp_attr->qkey = be32_to_cpu(context.qkey); 4062 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 4063 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 4064 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 4065 qp_attr->qp_access_flags = 4066 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 4067 4068 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4069 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 4070 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 4071 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 4072 qp_attr->alt_port_num = 4073 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4074 } 4075 4076 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 4077 if (qp_attr->qp_state == IB_QPS_INIT) 4078 qp_attr->port_num = qp->port; 4079 else 4080 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 4081 4082 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4083 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 4084 4085 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 4086 4087 qp_attr->max_dest_rd_atomic = 4088 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4089 qp_attr->min_rnr_timer = 4090 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4091 qp_attr->timeout = context.pri_path.ackto >> 3; 4092 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4093 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4094 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4095 4096 done: 4097 qp_attr->cur_qp_state = qp_attr->qp_state; 4098 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4099 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4100 4101 if (!ibqp->uobject) { 4102 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4103 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4104 } else { 4105 qp_attr->cap.max_send_wr = 0; 4106 qp_attr->cap.max_send_sge = 0; 4107 } 4108 4109 /* 4110 * We don't support inline sends for kernel QPs (yet), and we 4111 * don't know what userspace's value should be. 4112 */ 4113 qp_attr->cap.max_inline_data = 0; 4114 4115 qp_init_attr->cap = qp_attr->cap; 4116 4117 qp_init_attr->create_flags = 0; 4118 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4119 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4120 4121 if (qp->flags & MLX4_IB_QP_LSO) 4122 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4123 4124 if (qp->flags & MLX4_IB_QP_NETIF) 4125 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4126 4127 qp_init_attr->sq_sig_type = 4128 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4129 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4130 4131 out: 4132 mutex_unlock(&qp->mutex); 4133 return err; 4134 } 4135 4136 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4137 struct ib_wq_init_attr *init_attr, 4138 struct ib_udata *udata) 4139 { 4140 struct mlx4_ib_dev *dev; 4141 struct ib_qp_init_attr ib_qp_init_attr; 4142 struct mlx4_ib_qp *qp; 4143 struct mlx4_ib_create_wq ucmd; 4144 int err, required_cmd_sz; 4145 4146 if (!(udata && pd->uobject)) 4147 return ERR_PTR(-EINVAL); 4148 4149 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4150 sizeof(ucmd.comp_mask); 4151 if (udata->inlen < required_cmd_sz) { 4152 pr_debug("invalid inlen\n"); 4153 return ERR_PTR(-EINVAL); 4154 } 4155 4156 if (udata->inlen > sizeof(ucmd) && 4157 !ib_is_udata_cleared(udata, sizeof(ucmd), 4158 udata->inlen - sizeof(ucmd))) { 4159 pr_debug("inlen is not supported\n"); 4160 return ERR_PTR(-EOPNOTSUPP); 4161 } 4162 4163 if (udata->outlen) 4164 return ERR_PTR(-EOPNOTSUPP); 4165 4166 dev = to_mdev(pd->device); 4167 4168 if (init_attr->wq_type != IB_WQT_RQ) { 4169 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4170 return ERR_PTR(-EOPNOTSUPP); 4171 } 4172 4173 if (init_attr->create_flags) { 4174 pr_debug("unsupported create_flags %u\n", 4175 init_attr->create_flags); 4176 return ERR_PTR(-EOPNOTSUPP); 4177 } 4178 4179 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4180 if (!qp) 4181 return ERR_PTR(-ENOMEM); 4182 4183 qp->pri.vid = 0xFFFF; 4184 qp->alt.vid = 0xFFFF; 4185 4186 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr)); 4187 ib_qp_init_attr.qp_context = init_attr->wq_context; 4188 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4189 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4190 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4191 ib_qp_init_attr.recv_cq = init_attr->cq; 4192 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4193 4194 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr, 4195 udata, 0, &qp); 4196 if (err) { 4197 kfree(qp); 4198 return ERR_PTR(err); 4199 } 4200 4201 qp->ibwq.event_handler = init_attr->event_handler; 4202 qp->ibwq.wq_num = qp->mqp.qpn; 4203 qp->ibwq.state = IB_WQS_RESET; 4204 4205 return &qp->ibwq; 4206 } 4207 4208 static int ib_wq2qp_state(enum ib_wq_state state) 4209 { 4210 switch (state) { 4211 case IB_WQS_RESET: 4212 return IB_QPS_RESET; 4213 case IB_WQS_RDY: 4214 return IB_QPS_RTR; 4215 default: 4216 return IB_QPS_ERR; 4217 } 4218 } 4219 4220 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state) 4221 { 4222 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4223 enum ib_qp_state qp_cur_state; 4224 enum ib_qp_state qp_new_state; 4225 int attr_mask; 4226 int err; 4227 4228 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4229 * the WQ logic state. 4230 */ 4231 qp_cur_state = qp->state; 4232 qp_new_state = ib_wq2qp_state(new_state); 4233 4234 if (ib_wq2qp_state(new_state) == qp_cur_state) 4235 return 0; 4236 4237 if (new_state == IB_WQS_RDY) { 4238 struct ib_qp_attr attr = {}; 4239 4240 attr.port_num = qp->port; 4241 attr_mask = IB_QP_PORT; 4242 4243 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4244 attr_mask, IB_QPS_RESET, IB_QPS_INIT); 4245 if (err) { 4246 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4247 ibwq->wq_num); 4248 return err; 4249 } 4250 4251 qp_cur_state = IB_QPS_INIT; 4252 } 4253 4254 attr_mask = 0; 4255 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4256 qp_cur_state, qp_new_state); 4257 4258 if (err && (qp_cur_state == IB_QPS_INIT)) { 4259 qp_new_state = IB_QPS_RESET; 4260 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4261 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) { 4262 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4263 ibwq->wq_num); 4264 qp_new_state = IB_QPS_INIT; 4265 } 4266 } 4267 4268 qp->state = qp_new_state; 4269 4270 return err; 4271 } 4272 4273 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4274 u32 wq_attr_mask, struct ib_udata *udata) 4275 { 4276 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4277 struct mlx4_ib_modify_wq ucmd = {}; 4278 size_t required_cmd_sz; 4279 enum ib_wq_state cur_state, new_state; 4280 int err = 0; 4281 4282 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4283 sizeof(ucmd.reserved); 4284 if (udata->inlen < required_cmd_sz) 4285 return -EINVAL; 4286 4287 if (udata->inlen > sizeof(ucmd) && 4288 !ib_is_udata_cleared(udata, sizeof(ucmd), 4289 udata->inlen - sizeof(ucmd))) 4290 return -EOPNOTSUPP; 4291 4292 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4293 return -EFAULT; 4294 4295 if (ucmd.comp_mask || ucmd.reserved) 4296 return -EOPNOTSUPP; 4297 4298 if (wq_attr_mask & IB_WQ_FLAGS) 4299 return -EOPNOTSUPP; 4300 4301 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state : 4302 ibwq->state; 4303 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state; 4304 4305 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR || 4306 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR) 4307 return -EINVAL; 4308 4309 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4310 return -EINVAL; 4311 4312 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4313 return -EINVAL; 4314 4315 /* Need to protect against the parent RSS which also may modify WQ 4316 * state. 4317 */ 4318 mutex_lock(&qp->mutex); 4319 4320 /* Can update HW state only if a RSS QP has already associated to this 4321 * WQ, so we can apply its port on the WQ. 4322 */ 4323 if (qp->rss_usecnt) 4324 err = _mlx4_ib_modify_wq(ibwq, new_state); 4325 4326 if (!err) 4327 ibwq->state = new_state; 4328 4329 mutex_unlock(&qp->mutex); 4330 4331 return err; 4332 } 4333 4334 int mlx4_ib_destroy_wq(struct ib_wq *ibwq) 4335 { 4336 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4337 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4338 4339 if (qp->counter_index) 4340 mlx4_ib_free_qp_counter(dev, qp); 4341 4342 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1); 4343 4344 kfree(qp); 4345 4346 return 0; 4347 } 4348 4349 struct ib_rwq_ind_table 4350 *mlx4_ib_create_rwq_ind_table(struct ib_device *device, 4351 struct ib_rwq_ind_table_init_attr *init_attr, 4352 struct ib_udata *udata) 4353 { 4354 struct ib_rwq_ind_table *rwq_ind_table; 4355 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4356 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4357 unsigned int base_wqn; 4358 size_t min_resp_len; 4359 int i; 4360 int err; 4361 4362 if (udata->inlen > 0 && 4363 !ib_is_udata_cleared(udata, 0, 4364 udata->inlen)) 4365 return ERR_PTR(-EOPNOTSUPP); 4366 4367 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4368 if (udata->outlen && udata->outlen < min_resp_len) 4369 return ERR_PTR(-EINVAL); 4370 4371 if (ind_tbl_size > 4372 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4373 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4374 ind_tbl_size, 4375 device->attrs.rss_caps.max_rwq_indirection_table_size); 4376 return ERR_PTR(-EINVAL); 4377 } 4378 4379 base_wqn = init_attr->ind_tbl[0]->wq_num; 4380 4381 if (base_wqn % ind_tbl_size) { 4382 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4383 base_wqn); 4384 return ERR_PTR(-EINVAL); 4385 } 4386 4387 for (i = 1; i < ind_tbl_size; i++) { 4388 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4389 pr_debug("indirection table's WQNs aren't consecutive\n"); 4390 return ERR_PTR(-EINVAL); 4391 } 4392 } 4393 4394 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL); 4395 if (!rwq_ind_table) 4396 return ERR_PTR(-ENOMEM); 4397 4398 if (udata->outlen) { 4399 resp.response_length = offsetof(typeof(resp), response_length) + 4400 sizeof(resp.response_length); 4401 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4402 if (err) 4403 goto err; 4404 } 4405 4406 return rwq_ind_table; 4407 4408 err: 4409 kfree(rwq_ind_table); 4410 return ERR_PTR(err); 4411 } 4412 4413 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4414 { 4415 kfree(ib_rwq_ind_tbl); 4416 return 0; 4417 } 4418