1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 45 #include <linux/mlx4/driver.h> 46 #include <linux/mlx4/qp.h> 47 48 #include "mlx4_ib.h" 49 #include <rdma/mlx4-abi.h> 50 51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 52 struct mlx4_ib_cq *recv_cq); 53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 54 struct mlx4_ib_cq *recv_cq); 55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state); 56 57 enum { 58 MLX4_IB_ACK_REQ_FREQ = 8, 59 }; 60 61 enum { 62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 64 MLX4_IB_LINK_TYPE_IB = 0, 65 MLX4_IB_LINK_TYPE_ETH = 1 66 }; 67 68 enum { 69 /* 70 * Largest possible UD header: send with GRH and immediate 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 72 * tag. (LRH would only use 8 bytes, so Ethernet is the 73 * biggest case) 74 */ 75 MLX4_IB_UD_HEADER_SIZE = 82, 76 MLX4_IB_LSO_HEADER_SPARE = 128, 77 }; 78 79 struct mlx4_ib_sqp { 80 struct mlx4_ib_qp qp; 81 int pkey_index; 82 u32 qkey; 83 u32 send_psn; 84 struct ib_ud_header ud_header; 85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 86 struct ib_qp *roce_v2_gsi; 87 }; 88 89 enum { 90 MLX4_IB_MIN_SQ_STRIDE = 6, 91 MLX4_IB_CACHE_LINE_SIZE = 64, 92 }; 93 94 enum { 95 MLX4_RAW_QP_MTU = 7, 96 MLX4_RAW_QP_MSGMAX = 31, 97 }; 98 99 #ifndef ETH_ALEN 100 #define ETH_ALEN 6 101 #endif 102 103 static const __be32 mlx4_ib_opcode[] = { 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 117 }; 118 119 enum mlx4_ib_source_type { 120 MLX4_IB_QP_SRC = 0, 121 MLX4_IB_RWQ_SRC = 1, 122 }; 123 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 125 { 126 return container_of(mqp, struct mlx4_ib_sqp, qp); 127 } 128 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 130 { 131 if (!mlx4_is_master(dev->dev)) 132 return 0; 133 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 136 8 * MLX4_MFUNC_MAX; 137 } 138 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 140 { 141 int proxy_sqp = 0; 142 int real_sqp = 0; 143 int i; 144 /* PPF or Native -- real SQP */ 145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 148 if (real_sqp) 149 return 1; 150 /* VF or PF -- proxy SQP */ 151 if (mlx4_is_mfunc(dev->dev)) { 152 for (i = 0; i < dev->dev->caps.num_ports; i++) { 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 155 proxy_sqp = 1; 156 break; 157 } 158 } 159 } 160 if (proxy_sqp) 161 return 1; 162 163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 164 } 165 166 /* used for INIT/CLOSE port logic */ 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 168 { 169 int proxy_qp0 = 0; 170 int real_qp0 = 0; 171 int i; 172 /* PPF or Native -- real QP0 */ 173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 176 if (real_qp0) 177 return 1; 178 /* VF or PF -- proxy QP0 */ 179 if (mlx4_is_mfunc(dev->dev)) { 180 for (i = 0; i < dev->dev->caps.num_ports; i++) { 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 182 proxy_qp0 = 1; 183 break; 184 } 185 } 186 } 187 return proxy_qp0; 188 } 189 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 191 { 192 return mlx4_buf_offset(&qp->buf, offset); 193 } 194 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 196 { 197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 198 } 199 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 201 { 202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 203 } 204 205 /* 206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 207 * first four bytes of every 64 byte chunk with 208 * 0x7FFFFFF | (invalid_ownership_value << 31). 209 * 210 * When the max work request size is less than or equal to the WQE 211 * basic block size, as an optimization, we can stamp all WQEs with 212 * 0xffffffff, and skip the very first chunk of each WQE. 213 */ 214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 215 { 216 __be32 *wqe; 217 int i; 218 int s; 219 int ind; 220 void *buf; 221 __be32 stamp; 222 struct mlx4_wqe_ctrl_seg *ctrl; 223 224 if (qp->sq_max_wqes_per_wr > 1) { 225 s = roundup(size, 1U << qp->sq.wqe_shift); 226 for (i = 0; i < s; i += 64) { 227 ind = (i >> qp->sq.wqe_shift) + n; 228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 229 cpu_to_be32(0xffffffff); 230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 232 *wqe = stamp; 233 } 234 } else { 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 237 for (i = 64; i < s; i += 64) { 238 wqe = buf + i; 239 *wqe = cpu_to_be32(0xffffffff); 240 } 241 } 242 } 243 244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 245 { 246 struct mlx4_wqe_ctrl_seg *ctrl; 247 struct mlx4_wqe_inline_seg *inl; 248 void *wqe; 249 int s; 250 251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 252 s = sizeof(struct mlx4_wqe_ctrl_seg); 253 254 if (qp->ibqp.qp_type == IB_QPT_UD) { 255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 256 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 257 memset(dgram, 0, sizeof *dgram); 258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 259 s += sizeof(struct mlx4_wqe_datagram_seg); 260 } 261 262 /* Pad the remainder of the WQE with an inline data segment. */ 263 if (size > s) { 264 inl = wqe + s; 265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 266 } 267 ctrl->srcrb_flags = 0; 268 ctrl->qpn_vlan.fence_size = size / 16; 269 /* 270 * Make sure descriptor is fully written before setting ownership bit 271 * (because HW can start executing as soon as we do). 272 */ 273 wmb(); 274 275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 277 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 279 } 280 281 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 283 { 284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 285 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 287 ind += s; 288 } 289 return ind; 290 } 291 292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 293 { 294 struct ib_event event; 295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 296 297 if (type == MLX4_EVENT_TYPE_PATH_MIG) 298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 299 300 if (ibqp->event_handler) { 301 event.device = ibqp->device; 302 event.element.qp = ibqp; 303 switch (type) { 304 case MLX4_EVENT_TYPE_PATH_MIG: 305 event.event = IB_EVENT_PATH_MIG; 306 break; 307 case MLX4_EVENT_TYPE_COMM_EST: 308 event.event = IB_EVENT_COMM_EST; 309 break; 310 case MLX4_EVENT_TYPE_SQ_DRAINED: 311 event.event = IB_EVENT_SQ_DRAINED; 312 break; 313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 314 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 315 break; 316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 317 event.event = IB_EVENT_QP_FATAL; 318 break; 319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 320 event.event = IB_EVENT_PATH_MIG_ERR; 321 break; 322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 323 event.event = IB_EVENT_QP_REQ_ERR; 324 break; 325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 326 event.event = IB_EVENT_QP_ACCESS_ERR; 327 break; 328 default: 329 pr_warn("Unexpected event type %d " 330 "on QP %06x\n", type, qp->qpn); 331 return; 332 } 333 334 ibqp->event_handler(&event, ibqp->qp_context); 335 } 336 } 337 338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 339 { 340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 341 type, qp->qpn); 342 } 343 344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 345 { 346 /* 347 * UD WQEs must have a datagram segment. 348 * RC and UC WQEs might have a remote address segment. 349 * MLX WQEs need two extra inline data segments (for the UD 350 * header and space for the ICRC). 351 */ 352 switch (type) { 353 case MLX4_IB_QPT_UD: 354 return sizeof (struct mlx4_wqe_ctrl_seg) + 355 sizeof (struct mlx4_wqe_datagram_seg) + 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 357 case MLX4_IB_QPT_PROXY_SMI_OWNER: 358 case MLX4_IB_QPT_PROXY_SMI: 359 case MLX4_IB_QPT_PROXY_GSI: 360 return sizeof (struct mlx4_wqe_ctrl_seg) + 361 sizeof (struct mlx4_wqe_datagram_seg) + 64; 362 case MLX4_IB_QPT_TUN_SMI_OWNER: 363 case MLX4_IB_QPT_TUN_GSI: 364 return sizeof (struct mlx4_wqe_ctrl_seg) + 365 sizeof (struct mlx4_wqe_datagram_seg); 366 367 case MLX4_IB_QPT_UC: 368 return sizeof (struct mlx4_wqe_ctrl_seg) + 369 sizeof (struct mlx4_wqe_raddr_seg); 370 case MLX4_IB_QPT_RC: 371 return sizeof (struct mlx4_wqe_ctrl_seg) + 372 sizeof (struct mlx4_wqe_masked_atomic_seg) + 373 sizeof (struct mlx4_wqe_raddr_seg); 374 case MLX4_IB_QPT_SMI: 375 case MLX4_IB_QPT_GSI: 376 return sizeof (struct mlx4_wqe_ctrl_seg) + 377 ALIGN(MLX4_IB_UD_HEADER_SIZE + 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 379 MLX4_INLINE_ALIGN) * 380 sizeof (struct mlx4_wqe_inline_seg), 381 sizeof (struct mlx4_wqe_data_seg)) + 382 ALIGN(4 + 383 sizeof (struct mlx4_wqe_inline_seg), 384 sizeof (struct mlx4_wqe_data_seg)); 385 default: 386 return sizeof (struct mlx4_wqe_ctrl_seg); 387 } 388 } 389 390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 391 int is_user, int has_rq, struct mlx4_ib_qp *qp, 392 u32 inl_recv_sz) 393 { 394 /* Sanity check RQ size before proceeding */ 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 397 return -EINVAL; 398 399 if (!has_rq) { 400 if (cap->max_recv_wr || inl_recv_sz) 401 return -EINVAL; 402 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 404 } else { 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 406 sizeof(struct mlx4_wqe_data_seg); 407 u32 wqe_size; 408 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 411 inl_recv_sz > max_inl_recv_sz)) 412 return -EINVAL; 413 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 418 } 419 420 /* leave userspace return values as they were, so as not to break ABI */ 421 if (is_user) { 422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 423 cap->max_recv_sge = qp->rq.max_gs; 424 } else { 425 cap->max_recv_wr = qp->rq.max_post = 426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 427 cap->max_recv_sge = min(qp->rq.max_gs, 428 min(dev->dev->caps.max_sq_sg, 429 dev->dev->caps.max_rq_sg)); 430 } 431 432 return 0; 433 } 434 435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp, 437 bool shrink_wqe) 438 { 439 int s; 440 441 /* Sanity check SQ size before proceeding */ 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 446 return -EINVAL; 447 448 /* 449 * For MLX transport we need 2 extra S/G entries: 450 * one for the header and one for the checksum at the end 451 */ 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 455 return -EINVAL; 456 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 459 send_wqe_overhead(type, qp->flags); 460 461 if (s > dev->dev->caps.max_sq_desc_sz) 462 return -EINVAL; 463 464 /* 465 * Hermon supports shrinking WQEs, such that a single work 466 * request can include multiple units of 1 << wqe_shift. This 467 * way, work requests can differ in size, and do not have to 468 * be a power of 2 in size, saving memory and speeding up send 469 * WR posting. Unfortunately, if we do this then the 470 * wqe_index field in CQEs can't be used to look up the WR ID 471 * anymore, so we do this only if selective signaling is off. 472 * 473 * Further, on 32-bit platforms, we can't use vmap() to make 474 * the QP buffer virtually contiguous. Thus we have to use 475 * constant-sized WRs to make sure a WR is always fully within 476 * a single page-sized chunk. 477 * 478 * Finally, we use NOP work requests to pad the end of the 479 * work queue, to avoid wrap-around in the middle of WR. We 480 * set NEC bit to avoid getting completions with error for 481 * these NOP WRs, but since NEC is only supported starting 482 * with firmware 2.2.232, we use constant-sized WRs for older 483 * firmware. 484 * 485 * And, since MLX QPs only support SEND, we use constant-sized 486 * WRs in this case. 487 * 488 * We look for the smallest value of wqe_shift such that the 489 * resulting number of wqes does not exceed device 490 * capabilities. 491 * 492 * We set WQE size to at least 64 bytes, this way stamping 493 * invalidates each WQE. 494 */ 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 496 qp->sq_signal_bits && BITS_PER_LONG == 64 && 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 500 qp->sq.wqe_shift = ilog2(64); 501 else 502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 503 504 for (;;) { 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 506 507 /* 508 * We need to leave 2 KB + 1 WR of headroom in the SQ to 509 * allow HW to prefetch. 510 */ 511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 513 qp->sq_max_wqes_per_wr + 514 qp->sq_spare_wqes); 515 516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 517 break; 518 519 if (qp->sq_max_wqes_per_wr <= 1) 520 return -EINVAL; 521 522 ++qp->sq.wqe_shift; 523 } 524 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 527 send_wqe_overhead(type, qp->flags)) / 528 sizeof (struct mlx4_wqe_data_seg); 529 530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 531 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 533 qp->rq.offset = 0; 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 535 } else { 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 537 qp->sq.offset = 0; 538 } 539 540 cap->max_send_wr = qp->sq.max_post = 541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 542 cap->max_send_sge = min(qp->sq.max_gs, 543 min(dev->dev->caps.max_sq_sg, 544 dev->dev->caps.max_rq_sg)); 545 /* We don't support inline sends for kernel QPs (yet) */ 546 cap->max_inline_data = 0; 547 548 return 0; 549 } 550 551 static int set_user_sq_size(struct mlx4_ib_dev *dev, 552 struct mlx4_ib_qp *qp, 553 struct mlx4_ib_create_qp *ucmd) 554 { 555 /* Sanity check SQ size before proceeding */ 556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 557 ucmd->log_sq_stride > 558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 560 return -EINVAL; 561 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 563 qp->sq.wqe_shift = ucmd->log_sq_stride; 564 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 566 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 567 568 return 0; 569 } 570 571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 572 { 573 int i; 574 575 qp->sqp_proxy_rcv = 576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 577 GFP_KERNEL); 578 if (!qp->sqp_proxy_rcv) 579 return -ENOMEM; 580 for (i = 0; i < qp->rq.wqe_cnt; i++) { 581 qp->sqp_proxy_rcv[i].addr = 582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 583 GFP_KERNEL); 584 if (!qp->sqp_proxy_rcv[i].addr) 585 goto err; 586 qp->sqp_proxy_rcv[i].map = 587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 588 sizeof (struct mlx4_ib_proxy_sqp_hdr), 589 DMA_FROM_DEVICE); 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 591 kfree(qp->sqp_proxy_rcv[i].addr); 592 goto err; 593 } 594 } 595 return 0; 596 597 err: 598 while (i > 0) { 599 --i; 600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 601 sizeof (struct mlx4_ib_proxy_sqp_hdr), 602 DMA_FROM_DEVICE); 603 kfree(qp->sqp_proxy_rcv[i].addr); 604 } 605 kfree(qp->sqp_proxy_rcv); 606 qp->sqp_proxy_rcv = NULL; 607 return -ENOMEM; 608 } 609 610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 611 { 612 int i; 613 614 for (i = 0; i < qp->rq.wqe_cnt; i++) { 615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 616 sizeof (struct mlx4_ib_proxy_sqp_hdr), 617 DMA_FROM_DEVICE); 618 kfree(qp->sqp_proxy_rcv[i].addr); 619 } 620 kfree(qp->sqp_proxy_rcv); 621 } 622 623 static int qp_has_rq(struct ib_qp_init_attr *attr) 624 { 625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 626 return 0; 627 628 return !attr->srq; 629 } 630 631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 632 { 633 int i; 634 for (i = 0; i < dev->caps.num_ports; i++) { 635 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 636 return !!dev->caps.spec_qps[i].qp0_qkey; 637 } 638 return 0; 639 } 640 641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 642 struct mlx4_ib_qp *qp) 643 { 644 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 645 mlx4_counter_free(dev->dev, qp->counter_index->index); 646 list_del(&qp->counter_index->list); 647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 648 649 kfree(qp->counter_index); 650 qp->counter_index = NULL; 651 } 652 653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 654 struct ib_qp_init_attr *init_attr, 655 struct mlx4_ib_create_qp_rss *ucmd) 656 { 657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 659 660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 663 MLX4_EN_RSS_KEY_SIZE); 664 } else { 665 pr_debug("RX Hash function is not supported\n"); 666 return (-EOPNOTSUPP); 667 } 668 669 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 670 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 671 rss_ctx->flags = MLX4_RSS_IPV4; 672 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 673 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 674 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 675 return (-EOPNOTSUPP); 676 } 677 678 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 679 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 680 rss_ctx->flags |= MLX4_RSS_IPV6; 681 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 682 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 683 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 684 return (-EOPNOTSUPP); 685 } 686 687 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 688 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 689 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 690 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 691 return (-EOPNOTSUPP); 692 } 693 694 if (rss_ctx->flags & MLX4_RSS_IPV4) { 695 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 696 } else if (rss_ctx->flags & MLX4_RSS_IPV6) { 697 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 698 } else { 699 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 700 return (-EOPNOTSUPP); 701 } 702 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 703 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 704 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 705 return (-EOPNOTSUPP); 706 } 707 708 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 709 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 710 if (rss_ctx->flags & MLX4_RSS_IPV4) { 711 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 712 } else if (rss_ctx->flags & MLX4_RSS_IPV6) { 713 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 714 } else { 715 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 716 return (-EOPNOTSUPP); 717 } 718 719 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 720 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 721 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 722 return (-EOPNOTSUPP); 723 } 724 725 return 0; 726 } 727 728 static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd, 729 struct ib_qp_init_attr *init_attr, 730 struct mlx4_ib_create_qp_rss *ucmd, 731 struct mlx4_ib_qp *qp) 732 { 733 int qpn; 734 int err; 735 736 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 737 738 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 739 if (err) 740 return err; 741 742 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 743 if (err) 744 goto err_qpn; 745 746 mutex_init(&qp->mutex); 747 748 INIT_LIST_HEAD(&qp->gid_list); 749 INIT_LIST_HEAD(&qp->steering_rules); 750 751 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 752 qp->state = IB_QPS_RESET; 753 754 /* Set dummy send resources to be compatible with HV and PRM */ 755 qp->sq_no_prefetch = 1; 756 qp->sq.wqe_cnt = 1; 757 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 758 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 759 qp->mtt = (to_mqp( 760 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 761 762 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 763 if (!qp->rss_ctx) { 764 err = -ENOMEM; 765 goto err_qp_alloc; 766 } 767 768 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 769 if (err) 770 goto err; 771 772 return 0; 773 774 err: 775 kfree(qp->rss_ctx); 776 777 err_qp_alloc: 778 mlx4_qp_remove(dev->dev, &qp->mqp); 779 mlx4_qp_free(dev->dev, &qp->mqp); 780 781 err_qpn: 782 mlx4_qp_release_range(dev->dev, qpn, 1); 783 return err; 784 } 785 786 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd, 787 struct ib_qp_init_attr *init_attr, 788 struct ib_udata *udata) 789 { 790 struct mlx4_ib_qp *qp; 791 struct mlx4_ib_create_qp_rss ucmd = {}; 792 size_t required_cmd_sz; 793 int err; 794 795 if (!udata) { 796 pr_debug("RSS QP with NULL udata\n"); 797 return ERR_PTR(-EINVAL); 798 } 799 800 if (udata->outlen) 801 return ERR_PTR(-EOPNOTSUPP); 802 803 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 804 sizeof(ucmd.reserved1); 805 if (udata->inlen < required_cmd_sz) { 806 pr_debug("invalid inlen\n"); 807 return ERR_PTR(-EINVAL); 808 } 809 810 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 811 pr_debug("copy failed\n"); 812 return ERR_PTR(-EFAULT); 813 } 814 815 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 816 return ERR_PTR(-EOPNOTSUPP); 817 818 if (ucmd.comp_mask || ucmd.reserved1) 819 return ERR_PTR(-EOPNOTSUPP); 820 821 if (udata->inlen > sizeof(ucmd) && 822 !ib_is_udata_cleared(udata, sizeof(ucmd), 823 udata->inlen - sizeof(ucmd))) { 824 pr_debug("inlen is not supported\n"); 825 return ERR_PTR(-EOPNOTSUPP); 826 } 827 828 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 829 pr_debug("RSS QP with unsupported QP type %d\n", 830 init_attr->qp_type); 831 return ERR_PTR(-EOPNOTSUPP); 832 } 833 834 if (init_attr->create_flags) { 835 pr_debug("RSS QP doesn't support create flags\n"); 836 return ERR_PTR(-EOPNOTSUPP); 837 } 838 839 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 840 pr_debug("RSS QP with unsupported send attributes\n"); 841 return ERR_PTR(-EOPNOTSUPP); 842 } 843 844 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 845 if (!qp) 846 return ERR_PTR(-ENOMEM); 847 848 qp->pri.vid = 0xFFFF; 849 qp->alt.vid = 0xFFFF; 850 851 err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp); 852 if (err) { 853 kfree(qp); 854 return ERR_PTR(err); 855 } 856 857 qp->ibqp.qp_num = qp->mqp.qpn; 858 859 return &qp->ibqp; 860 } 861 862 /* 863 * This function allocates a WQN from a range which is consecutive and aligned 864 * to its size. In case the range is full, then it creates a new range and 865 * allocates WQN from it. The new range will be used for following allocations. 866 */ 867 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 868 struct mlx4_ib_qp *qp, int range_size, int *wqn) 869 { 870 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 871 struct mlx4_wqn_range *range; 872 int err = 0; 873 874 mutex_lock(&context->wqn_ranges_mutex); 875 876 range = list_first_entry_or_null(&context->wqn_ranges_list, 877 struct mlx4_wqn_range, list); 878 879 if (!range || (range->refcount == range->size) || range->dirty) { 880 range = kzalloc(sizeof(*range), GFP_KERNEL); 881 if (!range) { 882 err = -ENOMEM; 883 goto out; 884 } 885 886 err = mlx4_qp_reserve_range(dev->dev, range_size, 887 range_size, &range->base_wqn, 0, 888 qp->mqp.usage); 889 if (err) { 890 kfree(range); 891 goto out; 892 } 893 894 range->size = range_size; 895 list_add(&range->list, &context->wqn_ranges_list); 896 } else if (range_size != 1) { 897 /* 898 * Requesting a new range (>1) when last range is still open, is 899 * not valid. 900 */ 901 err = -EINVAL; 902 goto out; 903 } 904 905 qp->wqn_range = range; 906 907 *wqn = range->base_wqn + range->refcount; 908 909 range->refcount++; 910 911 out: 912 mutex_unlock(&context->wqn_ranges_mutex); 913 914 return err; 915 } 916 917 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 918 struct mlx4_ib_qp *qp, bool dirty_release) 919 { 920 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 921 struct mlx4_wqn_range *range; 922 923 mutex_lock(&context->wqn_ranges_mutex); 924 925 range = qp->wqn_range; 926 927 range->refcount--; 928 if (!range->refcount) { 929 mlx4_qp_release_range(dev->dev, range->base_wqn, 930 range->size); 931 list_del(&range->list); 932 kfree(range); 933 } else if (dirty_release) { 934 /* 935 * A range which one of its WQNs is destroyed, won't be able to be 936 * reused for further WQN allocations. 937 * The next created WQ will allocate a new range. 938 */ 939 range->dirty = 1; 940 } 941 942 mutex_unlock(&context->wqn_ranges_mutex); 943 } 944 945 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 946 enum mlx4_ib_source_type src, 947 struct ib_qp_init_attr *init_attr, 948 struct ib_udata *udata, int sqpn, 949 struct mlx4_ib_qp **caller_qp) 950 { 951 int qpn; 952 int err; 953 struct ib_qp_cap backup_cap; 954 struct mlx4_ib_sqp *sqp = NULL; 955 struct mlx4_ib_qp *qp; 956 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 957 struct mlx4_ib_cq *mcq; 958 unsigned long flags; 959 int range_size = 0; 960 961 /* When tunneling special qps, we use a plain UD qp */ 962 if (sqpn) { 963 if (mlx4_is_mfunc(dev->dev) && 964 (!mlx4_is_master(dev->dev) || 965 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 966 if (init_attr->qp_type == IB_QPT_GSI) 967 qp_type = MLX4_IB_QPT_PROXY_GSI; 968 else { 969 if (mlx4_is_master(dev->dev) || 970 qp0_enabled_vf(dev->dev, sqpn)) 971 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 972 else 973 qp_type = MLX4_IB_QPT_PROXY_SMI; 974 } 975 } 976 qpn = sqpn; 977 /* add extra sg entry for tunneling */ 978 init_attr->cap.max_recv_sge++; 979 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 980 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 981 container_of(init_attr, 982 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 983 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 984 tnl_init->proxy_qp_type != IB_QPT_GSI) || 985 !mlx4_is_master(dev->dev)) 986 return -EINVAL; 987 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 988 qp_type = MLX4_IB_QPT_TUN_GSI; 989 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 990 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 991 tnl_init->port)) 992 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 993 else 994 qp_type = MLX4_IB_QPT_TUN_SMI; 995 /* we are definitely in the PPF here, since we are creating 996 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 997 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 998 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 999 sqpn = qpn; 1000 } 1001 1002 if (!*caller_qp) { 1003 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 1004 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 1005 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 1006 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 1007 if (!sqp) 1008 return -ENOMEM; 1009 qp = &sqp->qp; 1010 qp->pri.vid = 0xFFFF; 1011 qp->alt.vid = 0xFFFF; 1012 } else { 1013 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL); 1014 if (!qp) 1015 return -ENOMEM; 1016 qp->pri.vid = 0xFFFF; 1017 qp->alt.vid = 0xFFFF; 1018 } 1019 } else 1020 qp = *caller_qp; 1021 1022 qp->mlx4_ib_qp_type = qp_type; 1023 1024 mutex_init(&qp->mutex); 1025 spin_lock_init(&qp->sq.lock); 1026 spin_lock_init(&qp->rq.lock); 1027 INIT_LIST_HEAD(&qp->gid_list); 1028 INIT_LIST_HEAD(&qp->steering_rules); 1029 1030 qp->state = IB_QPS_RESET; 1031 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1032 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1033 1034 1035 if (pd->uobject) { 1036 union { 1037 struct mlx4_ib_create_qp qp; 1038 struct mlx4_ib_create_wq wq; 1039 } ucmd; 1040 size_t copy_len; 1041 int shift; 1042 int n; 1043 1044 copy_len = (src == MLX4_IB_QP_SRC) ? 1045 sizeof(struct mlx4_ib_create_qp) : 1046 min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 1047 1048 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 1049 err = -EFAULT; 1050 goto err; 1051 } 1052 1053 if (src == MLX4_IB_RWQ_SRC) { 1054 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] || 1055 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) { 1056 pr_debug("user command isn't supported\n"); 1057 err = -EOPNOTSUPP; 1058 goto err; 1059 } 1060 1061 if (ucmd.wq.log_range_size > 1062 ilog2(dev->dev->caps.max_rss_tbl_sz)) { 1063 pr_debug("WQN range size must be equal or smaller than %d\n", 1064 dev->dev->caps.max_rss_tbl_sz); 1065 err = -EOPNOTSUPP; 1066 goto err; 1067 } 1068 range_size = 1 << ucmd.wq.log_range_size; 1069 } else { 1070 qp->inl_recv_sz = ucmd.qp.inl_recv_sz; 1071 } 1072 1073 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, 1074 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1075 if (err) 1076 goto err; 1077 1078 if (src == MLX4_IB_QP_SRC) { 1079 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch; 1080 1081 err = set_user_sq_size(dev, qp, 1082 (struct mlx4_ib_create_qp *) 1083 &ucmd); 1084 if (err) 1085 goto err; 1086 } else { 1087 qp->sq_no_prefetch = 1; 1088 qp->sq.wqe_cnt = 1; 1089 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 1090 /* Allocated buffer expects to have at least that SQ 1091 * size. 1092 */ 1093 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 1094 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 1095 } 1096 1097 qp->umem = ib_umem_get(pd->uobject->context, 1098 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr : 1099 ucmd.wq.buf_addr, qp->buf_size, 0, 0); 1100 if (IS_ERR(qp->umem)) { 1101 err = PTR_ERR(qp->umem); 1102 goto err; 1103 } 1104 1105 n = ib_umem_page_count(qp->umem); 1106 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1107 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1108 1109 if (err) 1110 goto err_buf; 1111 1112 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1113 if (err) 1114 goto err_mtt; 1115 1116 if (qp_has_rq(init_attr)) { 1117 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 1118 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr : 1119 ucmd.wq.db_addr, &qp->db); 1120 if (err) 1121 goto err_mtt; 1122 } 1123 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1124 } else { 1125 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, 1126 qp_has_rq(init_attr), qp, 0); 1127 if (err) 1128 goto err; 1129 1130 qp->sq_no_prefetch = 0; 1131 1132 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1133 qp->flags |= MLX4_IB_QP_LSO; 1134 1135 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1136 if (dev->steering_support == 1137 MLX4_STEERING_MODE_DEVICE_MANAGED) 1138 qp->flags |= MLX4_IB_QP_NETIF; 1139 else 1140 goto err; 1141 } 1142 1143 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap)); 1144 err = set_kernel_sq_size(dev, &init_attr->cap, 1145 qp_type, qp, true); 1146 if (err) 1147 goto err; 1148 1149 if (qp_has_rq(init_attr)) { 1150 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1151 if (err) 1152 goto err; 1153 1154 *qp->db.db = 0; 1155 } 1156 1157 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size, 1158 &qp->buf)) { 1159 memcpy(&init_attr->cap, &backup_cap, 1160 sizeof(backup_cap)); 1161 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, 1162 qp, false); 1163 if (err) 1164 goto err_db; 1165 1166 if (mlx4_buf_alloc(dev->dev, qp->buf_size, 1167 PAGE_SIZE * 2, &qp->buf)) { 1168 err = -ENOMEM; 1169 goto err_db; 1170 } 1171 } 1172 1173 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1174 &qp->mtt); 1175 if (err) 1176 goto err_buf; 1177 1178 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1179 if (err) 1180 goto err_mtt; 1181 1182 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1183 sizeof(u64), GFP_KERNEL); 1184 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1185 sizeof(u64), GFP_KERNEL); 1186 if (!qp->sq.wrid || !qp->rq.wrid) { 1187 err = -ENOMEM; 1188 goto err_wrid; 1189 } 1190 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1191 } 1192 1193 if (sqpn) { 1194 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1195 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1196 if (alloc_proxy_bufs(pd->device, qp)) { 1197 err = -ENOMEM; 1198 goto err_wrid; 1199 } 1200 } 1201 } else if (src == MLX4_IB_RWQ_SRC) { 1202 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp, 1203 range_size, &qpn); 1204 if (err) 1205 goto err_wrid; 1206 } else { 1207 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1208 * otherwise, the WQE BlueFlame setup flow wrongly causes 1209 * VLAN insertion. */ 1210 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1211 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1212 (init_attr->cap.max_send_wr ? 1213 MLX4_RESERVE_ETH_BF_QP : 0) | 1214 (init_attr->cap.max_recv_wr ? 1215 MLX4_RESERVE_A0_QP : 0), 1216 qp->mqp.usage); 1217 else 1218 if (qp->flags & MLX4_IB_QP_NETIF) 1219 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1220 else 1221 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1222 &qpn, 0, qp->mqp.usage); 1223 if (err) 1224 goto err_proxy; 1225 } 1226 1227 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1228 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1229 1230 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1231 if (err) 1232 goto err_qpn; 1233 1234 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1235 qp->mqp.qpn |= (1 << 23); 1236 1237 /* 1238 * Hardware wants QPN written in big-endian order (after 1239 * shifting) for send doorbell. Precompute this value to save 1240 * a little bit when posting sends. 1241 */ 1242 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1243 1244 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event : 1245 mlx4_ib_wq_event; 1246 1247 if (!*caller_qp) 1248 *caller_qp = qp; 1249 1250 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1251 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1252 to_mcq(init_attr->recv_cq)); 1253 /* Maintain device to QPs access, needed for further handling 1254 * via reset flow 1255 */ 1256 list_add_tail(&qp->qps_list, &dev->qp_list); 1257 /* Maintain CQ to QPs access, needed for further handling 1258 * via reset flow 1259 */ 1260 mcq = to_mcq(init_attr->send_cq); 1261 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1262 mcq = to_mcq(init_attr->recv_cq); 1263 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1264 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1265 to_mcq(init_attr->recv_cq)); 1266 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1267 return 0; 1268 1269 err_qpn: 1270 if (!sqpn) { 1271 if (qp->flags & MLX4_IB_QP_NETIF) 1272 mlx4_ib_steer_qp_free(dev, qpn, 1); 1273 else if (src == MLX4_IB_RWQ_SRC) 1274 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context), 1275 qp, 0); 1276 else 1277 mlx4_qp_release_range(dev->dev, qpn, 1); 1278 } 1279 err_proxy: 1280 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1281 free_proxy_bufs(pd->device, qp); 1282 err_wrid: 1283 if (pd->uobject) { 1284 if (qp_has_rq(init_attr)) 1285 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 1286 } else { 1287 kvfree(qp->sq.wrid); 1288 kvfree(qp->rq.wrid); 1289 } 1290 1291 err_mtt: 1292 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1293 1294 err_buf: 1295 if (pd->uobject) 1296 ib_umem_release(qp->umem); 1297 else 1298 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1299 1300 err_db: 1301 if (!pd->uobject && qp_has_rq(init_attr)) 1302 mlx4_db_free(dev->dev, &qp->db); 1303 1304 err: 1305 if (sqp) 1306 kfree(sqp); 1307 else if (!*caller_qp) 1308 kfree(qp); 1309 return err; 1310 } 1311 1312 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1313 { 1314 switch (state) { 1315 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1316 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1317 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1318 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1319 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1320 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1321 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1322 default: return -1; 1323 } 1324 } 1325 1326 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1327 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1328 { 1329 if (send_cq == recv_cq) { 1330 spin_lock(&send_cq->lock); 1331 __acquire(&recv_cq->lock); 1332 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1333 spin_lock(&send_cq->lock); 1334 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1335 } else { 1336 spin_lock(&recv_cq->lock); 1337 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1338 } 1339 } 1340 1341 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1342 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1343 { 1344 if (send_cq == recv_cq) { 1345 __release(&recv_cq->lock); 1346 spin_unlock(&send_cq->lock); 1347 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1348 spin_unlock(&recv_cq->lock); 1349 spin_unlock(&send_cq->lock); 1350 } else { 1351 spin_unlock(&send_cq->lock); 1352 spin_unlock(&recv_cq->lock); 1353 } 1354 } 1355 1356 static void del_gid_entries(struct mlx4_ib_qp *qp) 1357 { 1358 struct mlx4_ib_gid_entry *ge, *tmp; 1359 1360 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1361 list_del(&ge->list); 1362 kfree(ge); 1363 } 1364 } 1365 1366 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1367 { 1368 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1369 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1370 else 1371 return to_mpd(qp->ibqp.pd); 1372 } 1373 1374 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1375 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1376 { 1377 switch (qp->ibqp.qp_type) { 1378 case IB_QPT_XRC_TGT: 1379 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1380 *recv_cq = *send_cq; 1381 break; 1382 case IB_QPT_XRC_INI: 1383 *send_cq = to_mcq(qp->ibqp.send_cq); 1384 *recv_cq = *send_cq; 1385 break; 1386 default: 1387 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1388 to_mcq(qp->ibwq.cq); 1389 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1390 *recv_cq; 1391 break; 1392 } 1393 } 1394 1395 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1396 { 1397 if (qp->state != IB_QPS_RESET) { 1398 int i; 1399 1400 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1401 i++) { 1402 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1403 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1404 1405 mutex_lock(&wq->mutex); 1406 1407 wq->rss_usecnt--; 1408 1409 mutex_unlock(&wq->mutex); 1410 } 1411 1412 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1413 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1414 pr_warn("modify QP %06x to RESET failed.\n", 1415 qp->mqp.qpn); 1416 } 1417 1418 mlx4_qp_remove(dev->dev, &qp->mqp); 1419 mlx4_qp_free(dev->dev, &qp->mqp); 1420 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1421 del_gid_entries(qp); 1422 kfree(qp->rss_ctx); 1423 } 1424 1425 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1426 enum mlx4_ib_source_type src, int is_user) 1427 { 1428 struct mlx4_ib_cq *send_cq, *recv_cq; 1429 unsigned long flags; 1430 1431 if (qp->state != IB_QPS_RESET) { 1432 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1433 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1434 pr_warn("modify QP %06x to RESET failed.\n", 1435 qp->mqp.qpn); 1436 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1437 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1438 qp->pri.smac = 0; 1439 qp->pri.smac_port = 0; 1440 } 1441 if (qp->alt.smac) { 1442 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1443 qp->alt.smac = 0; 1444 } 1445 if (qp->pri.vid < 0x1000) { 1446 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1447 qp->pri.vid = 0xFFFF; 1448 qp->pri.candidate_vid = 0xFFFF; 1449 qp->pri.update_vid = 0; 1450 } 1451 if (qp->alt.vid < 0x1000) { 1452 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1453 qp->alt.vid = 0xFFFF; 1454 qp->alt.candidate_vid = 0xFFFF; 1455 qp->alt.update_vid = 0; 1456 } 1457 } 1458 1459 get_cqs(qp, src, &send_cq, &recv_cq); 1460 1461 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1462 mlx4_ib_lock_cqs(send_cq, recv_cq); 1463 1464 /* del from lists under both locks above to protect reset flow paths */ 1465 list_del(&qp->qps_list); 1466 list_del(&qp->cq_send_list); 1467 list_del(&qp->cq_recv_list); 1468 if (!is_user) { 1469 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1470 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1471 if (send_cq != recv_cq) 1472 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1473 } 1474 1475 mlx4_qp_remove(dev->dev, &qp->mqp); 1476 1477 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1478 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1479 1480 mlx4_qp_free(dev->dev, &qp->mqp); 1481 1482 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1483 if (qp->flags & MLX4_IB_QP_NETIF) 1484 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1485 else if (src == MLX4_IB_RWQ_SRC) 1486 mlx4_ib_release_wqn(to_mucontext( 1487 qp->ibwq.uobject->context), qp, 1); 1488 else 1489 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1490 } 1491 1492 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1493 1494 if (is_user) { 1495 if (qp->rq.wqe_cnt) { 1496 struct mlx4_ib_ucontext *mcontext = !src ? 1497 to_mucontext(qp->ibqp.uobject->context) : 1498 to_mucontext(qp->ibwq.uobject->context); 1499 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1500 } 1501 ib_umem_release(qp->umem); 1502 } else { 1503 kvfree(qp->sq.wrid); 1504 kvfree(qp->rq.wrid); 1505 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1506 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1507 free_proxy_bufs(&dev->ib_dev, qp); 1508 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1509 if (qp->rq.wqe_cnt) 1510 mlx4_db_free(dev->dev, &qp->db); 1511 } 1512 1513 del_gid_entries(qp); 1514 } 1515 1516 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1517 { 1518 /* Native or PPF */ 1519 if (!mlx4_is_mfunc(dev->dev) || 1520 (mlx4_is_master(dev->dev) && 1521 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1522 return dev->dev->phys_caps.base_sqpn + 1523 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1524 attr->port_num - 1; 1525 } 1526 /* PF or VF -- creating proxies */ 1527 if (attr->qp_type == IB_QPT_SMI) 1528 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1529 else 1530 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1531 } 1532 1533 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1534 struct ib_qp_init_attr *init_attr, 1535 struct ib_udata *udata) 1536 { 1537 struct mlx4_ib_qp *qp = NULL; 1538 int err; 1539 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1540 u16 xrcdn = 0; 1541 1542 if (init_attr->rwq_ind_tbl) 1543 return _mlx4_ib_create_qp_rss(pd, init_attr, udata); 1544 1545 /* 1546 * We only support LSO, vendor flag1, and multicast loopback blocking, 1547 * and only for kernel UD QPs. 1548 */ 1549 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1550 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1551 MLX4_IB_SRIOV_TUNNEL_QP | 1552 MLX4_IB_SRIOV_SQP | 1553 MLX4_IB_QP_NETIF | 1554 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1555 return ERR_PTR(-EINVAL); 1556 1557 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1558 if (init_attr->qp_type != IB_QPT_UD) 1559 return ERR_PTR(-EINVAL); 1560 } 1561 1562 if (init_attr->create_flags) { 1563 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1564 return ERR_PTR(-EINVAL); 1565 1566 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1567 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1568 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1569 init_attr->qp_type != IB_QPT_UD) || 1570 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1571 init_attr->qp_type > IB_QPT_GSI) || 1572 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1573 init_attr->qp_type != IB_QPT_GSI)) 1574 return ERR_PTR(-EINVAL); 1575 } 1576 1577 switch (init_attr->qp_type) { 1578 case IB_QPT_XRC_TGT: 1579 pd = to_mxrcd(init_attr->xrcd)->pd; 1580 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1581 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1582 /* fall through */ 1583 case IB_QPT_XRC_INI: 1584 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1585 return ERR_PTR(-ENOSYS); 1586 init_attr->recv_cq = init_attr->send_cq; 1587 /* fall through */ 1588 case IB_QPT_RC: 1589 case IB_QPT_UC: 1590 case IB_QPT_RAW_PACKET: 1591 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1592 if (!qp) 1593 return ERR_PTR(-ENOMEM); 1594 qp->pri.vid = 0xFFFF; 1595 qp->alt.vid = 0xFFFF; 1596 /* fall through */ 1597 case IB_QPT_UD: 1598 { 1599 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1600 init_attr, udata, 0, &qp); 1601 if (err) { 1602 kfree(qp); 1603 return ERR_PTR(err); 1604 } 1605 1606 qp->ibqp.qp_num = qp->mqp.qpn; 1607 qp->xrcdn = xrcdn; 1608 1609 break; 1610 } 1611 case IB_QPT_SMI: 1612 case IB_QPT_GSI: 1613 { 1614 int sqpn; 1615 1616 /* Userspace is not allowed to create special QPs: */ 1617 if (udata) 1618 return ERR_PTR(-EINVAL); 1619 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1620 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1621 1, 1, &sqpn, 0, 1622 MLX4_RES_USAGE_DRIVER); 1623 1624 if (res) 1625 return ERR_PTR(res); 1626 } else { 1627 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1628 } 1629 1630 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1631 init_attr, udata, sqpn, &qp); 1632 if (err) 1633 return ERR_PTR(err); 1634 1635 qp->port = init_attr->port_num; 1636 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1637 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1638 break; 1639 } 1640 default: 1641 /* Don't support raw QPs */ 1642 return ERR_PTR(-EINVAL); 1643 } 1644 1645 return &qp->ibqp; 1646 } 1647 1648 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1649 struct ib_qp_init_attr *init_attr, 1650 struct ib_udata *udata) { 1651 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1652 struct ib_qp *ibqp; 1653 struct mlx4_ib_dev *dev = to_mdev(device); 1654 1655 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1656 1657 if (!IS_ERR(ibqp) && 1658 (init_attr->qp_type == IB_QPT_GSI) && 1659 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1660 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1661 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1662 1663 if (is_eth && 1664 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1665 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1666 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1667 1668 if (IS_ERR(sqp->roce_v2_gsi)) { 1669 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1670 sqp->roce_v2_gsi = NULL; 1671 } else { 1672 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1673 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1674 } 1675 1676 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1677 } 1678 } 1679 return ibqp; 1680 } 1681 1682 static int _mlx4_ib_destroy_qp(struct ib_qp *qp) 1683 { 1684 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1685 struct mlx4_ib_qp *mqp = to_mqp(qp); 1686 1687 if (is_qp0(dev, mqp)) 1688 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1689 1690 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1691 dev->qp1_proxy[mqp->port - 1] == mqp) { 1692 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1693 dev->qp1_proxy[mqp->port - 1] = NULL; 1694 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1695 } 1696 1697 if (mqp->counter_index) 1698 mlx4_ib_free_qp_counter(dev, mqp); 1699 1700 if (qp->rwq_ind_tbl) { 1701 destroy_qp_rss(dev, mqp); 1702 } else { 1703 struct mlx4_ib_pd *pd; 1704 1705 pd = get_pd(mqp); 1706 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject); 1707 } 1708 1709 if (is_sqp(dev, mqp)) 1710 kfree(to_msqp(mqp)); 1711 else 1712 kfree(mqp); 1713 1714 return 0; 1715 } 1716 1717 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1718 { 1719 struct mlx4_ib_qp *mqp = to_mqp(qp); 1720 1721 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1722 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1723 1724 if (sqp->roce_v2_gsi) 1725 ib_destroy_qp(sqp->roce_v2_gsi); 1726 } 1727 1728 return _mlx4_ib_destroy_qp(qp); 1729 } 1730 1731 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1732 { 1733 switch (type) { 1734 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1735 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1736 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1737 case MLX4_IB_QPT_XRC_INI: 1738 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1739 case MLX4_IB_QPT_SMI: 1740 case MLX4_IB_QPT_GSI: 1741 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1742 1743 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1744 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1745 MLX4_QP_ST_MLX : -1); 1746 case MLX4_IB_QPT_PROXY_SMI: 1747 case MLX4_IB_QPT_TUN_SMI: 1748 case MLX4_IB_QPT_PROXY_GSI: 1749 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1750 MLX4_QP_ST_UD : -1); 1751 default: return -1; 1752 } 1753 } 1754 1755 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1756 int attr_mask) 1757 { 1758 u8 dest_rd_atomic; 1759 u32 access_flags; 1760 u32 hw_access_flags = 0; 1761 1762 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1763 dest_rd_atomic = attr->max_dest_rd_atomic; 1764 else 1765 dest_rd_atomic = qp->resp_depth; 1766 1767 if (attr_mask & IB_QP_ACCESS_FLAGS) 1768 access_flags = attr->qp_access_flags; 1769 else 1770 access_flags = qp->atomic_rd_en; 1771 1772 if (!dest_rd_atomic) 1773 access_flags &= IB_ACCESS_REMOTE_WRITE; 1774 1775 if (access_flags & IB_ACCESS_REMOTE_READ) 1776 hw_access_flags |= MLX4_QP_BIT_RRE; 1777 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1778 hw_access_flags |= MLX4_QP_BIT_RAE; 1779 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1780 hw_access_flags |= MLX4_QP_BIT_RWE; 1781 1782 return cpu_to_be32(hw_access_flags); 1783 } 1784 1785 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1786 int attr_mask) 1787 { 1788 if (attr_mask & IB_QP_PKEY_INDEX) 1789 sqp->pkey_index = attr->pkey_index; 1790 if (attr_mask & IB_QP_QKEY) 1791 sqp->qkey = attr->qkey; 1792 if (attr_mask & IB_QP_SQ_PSN) 1793 sqp->send_psn = attr->sq_psn; 1794 } 1795 1796 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1797 { 1798 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1799 } 1800 1801 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1802 const struct rdma_ah_attr *ah, 1803 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1804 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1805 { 1806 int vidx; 1807 int smac_index; 1808 int err; 1809 1810 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1811 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1812 if (rdma_ah_get_static_rate(ah)) { 1813 path->static_rate = rdma_ah_get_static_rate(ah) + 1814 MLX4_STAT_RATE_OFFSET; 1815 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1816 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1817 --path->static_rate; 1818 } else 1819 path->static_rate = 0; 1820 1821 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1822 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1823 int real_sgid_index = 1824 mlx4_ib_gid_index_to_real_index(dev, port, 1825 grh->sgid_index); 1826 1827 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1828 pr_err("sgid_index (%u) too large. max is %d\n", 1829 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1830 return -1; 1831 } 1832 1833 path->grh_mylmc |= 1 << 7; 1834 path->mgid_index = real_sgid_index; 1835 path->hop_limit = grh->hop_limit; 1836 path->tclass_flowlabel = 1837 cpu_to_be32((grh->traffic_class << 20) | 1838 (grh->flow_label)); 1839 memcpy(path->rgid, grh->dgid.raw, 16); 1840 } 1841 1842 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1843 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1844 return -1; 1845 1846 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1847 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1848 1849 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1850 if (vlan_tag < 0x1000) { 1851 if (smac_info->vid < 0x1000) { 1852 /* both valid vlan ids */ 1853 if (smac_info->vid != vlan_tag) { 1854 /* different VIDs. unreg old and reg new */ 1855 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1856 if (err) 1857 return err; 1858 smac_info->candidate_vid = vlan_tag; 1859 smac_info->candidate_vlan_index = vidx; 1860 smac_info->candidate_vlan_port = port; 1861 smac_info->update_vid = 1; 1862 path->vlan_index = vidx; 1863 } else { 1864 path->vlan_index = smac_info->vlan_index; 1865 } 1866 } else { 1867 /* no current vlan tag in qp */ 1868 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1869 if (err) 1870 return err; 1871 smac_info->candidate_vid = vlan_tag; 1872 smac_info->candidate_vlan_index = vidx; 1873 smac_info->candidate_vlan_port = port; 1874 smac_info->update_vid = 1; 1875 path->vlan_index = vidx; 1876 } 1877 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1878 path->fl = 1 << 6; 1879 } else { 1880 /* have current vlan tag. unregister it at modify-qp success */ 1881 if (smac_info->vid < 0x1000) { 1882 smac_info->candidate_vid = 0xFFFF; 1883 smac_info->update_vid = 1; 1884 } 1885 } 1886 1887 /* get smac_index for RoCE use. 1888 * If no smac was yet assigned, register one. 1889 * If one was already assigned, but the new mac differs, 1890 * unregister the old one and register the new one. 1891 */ 1892 if ((!smac_info->smac && !smac_info->smac_port) || 1893 smac_info->smac != smac) { 1894 /* register candidate now, unreg if needed, after success */ 1895 smac_index = mlx4_register_mac(dev->dev, port, smac); 1896 if (smac_index >= 0) { 1897 smac_info->candidate_smac_index = smac_index; 1898 smac_info->candidate_smac = smac; 1899 smac_info->candidate_smac_port = port; 1900 } else { 1901 return -EINVAL; 1902 } 1903 } else { 1904 smac_index = smac_info->smac_index; 1905 } 1906 memcpy(path->dmac, ah->roce.dmac, 6); 1907 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1908 /* put MAC table smac index for IBoE */ 1909 path->grh_mylmc = (u8) (smac_index) | 0x80; 1910 } else { 1911 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1912 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1919 enum ib_qp_attr_mask qp_attr_mask, 1920 struct mlx4_ib_qp *mqp, 1921 struct mlx4_qp_path *path, u8 port, 1922 u16 vlan_id, u8 *smac) 1923 { 1924 return _mlx4_set_path(dev, &qp->ah_attr, 1925 mlx4_mac_to_u64(smac), 1926 vlan_id, 1927 path, &mqp->pri, port); 1928 } 1929 1930 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1931 const struct ib_qp_attr *qp, 1932 enum ib_qp_attr_mask qp_attr_mask, 1933 struct mlx4_ib_qp *mqp, 1934 struct mlx4_qp_path *path, u8 port) 1935 { 1936 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1937 0, 1938 0xffff, 1939 path, &mqp->alt, port); 1940 } 1941 1942 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1943 { 1944 struct mlx4_ib_gid_entry *ge, *tmp; 1945 1946 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1947 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1948 ge->added = 1; 1949 ge->port = qp->port; 1950 } 1951 } 1952 } 1953 1954 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1955 struct mlx4_ib_qp *qp, 1956 struct mlx4_qp_context *context) 1957 { 1958 u64 u64_mac; 1959 int smac_index; 1960 1961 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1962 1963 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1964 if (!qp->pri.smac && !qp->pri.smac_port) { 1965 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1966 if (smac_index >= 0) { 1967 qp->pri.candidate_smac_index = smac_index; 1968 qp->pri.candidate_smac = u64_mac; 1969 qp->pri.candidate_smac_port = qp->port; 1970 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1971 } else { 1972 return -ENOENT; 1973 } 1974 } 1975 return 0; 1976 } 1977 1978 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1979 { 1980 struct counter_index *new_counter_index; 1981 int err; 1982 u32 tmp_idx; 1983 1984 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1985 IB_LINK_LAYER_ETHERNET || 1986 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1987 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1988 return 0; 1989 1990 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1991 if (err) 1992 return err; 1993 1994 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1995 if (!new_counter_index) { 1996 mlx4_counter_free(dev->dev, tmp_idx); 1997 return -ENOMEM; 1998 } 1999 2000 new_counter_index->index = tmp_idx; 2001 new_counter_index->allocated = 1; 2002 qp->counter_index = new_counter_index; 2003 2004 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 2005 list_add_tail(&new_counter_index->list, 2006 &dev->counters_table[qp->port - 1].counters_list); 2007 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 2008 2009 return 0; 2010 } 2011 2012 enum { 2013 MLX4_QPC_ROCE_MODE_1 = 0, 2014 MLX4_QPC_ROCE_MODE_2 = 2, 2015 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 2016 }; 2017 2018 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 2019 { 2020 switch (gid_type) { 2021 case IB_GID_TYPE_ROCE: 2022 return MLX4_QPC_ROCE_MODE_1; 2023 case IB_GID_TYPE_ROCE_UDP_ENCAP: 2024 return MLX4_QPC_ROCE_MODE_2; 2025 default: 2026 return MLX4_QPC_ROCE_MODE_UNDEFINED; 2027 } 2028 } 2029 2030 /* 2031 * Go over all RSS QP's childes (WQs) and apply their HW state according to 2032 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 2033 */ 2034 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num) 2035 { 2036 int err = 0; 2037 int i; 2038 2039 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2040 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2041 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2042 2043 mutex_lock(&wq->mutex); 2044 2045 /* Mlx4_ib restrictions: 2046 * WQ's is associated to a port according to the RSS QP it is 2047 * associates to. 2048 * In case the WQ is associated to a different port by another 2049 * RSS QP, return a failure. 2050 */ 2051 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 2052 err = -EINVAL; 2053 mutex_unlock(&wq->mutex); 2054 break; 2055 } 2056 wq->port = port_num; 2057 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 2058 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY); 2059 if (err) { 2060 mutex_unlock(&wq->mutex); 2061 break; 2062 } 2063 } 2064 wq->rss_usecnt++; 2065 2066 mutex_unlock(&wq->mutex); 2067 } 2068 2069 if (i && err) { 2070 int j; 2071 2072 for (j = (i - 1); j >= 0; j--) { 2073 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 2074 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2075 2076 mutex_lock(&wq->mutex); 2077 2078 if ((wq->rss_usecnt == 1) && 2079 (ibwq->state == IB_WQS_RDY)) 2080 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 2081 pr_warn("failed to reverse WQN=0x%06x\n", 2082 ibwq->wq_num); 2083 wq->rss_usecnt--; 2084 2085 mutex_unlock(&wq->mutex); 2086 } 2087 } 2088 2089 return err; 2090 } 2091 2092 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl) 2093 { 2094 int i; 2095 2096 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2097 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2098 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2099 2100 mutex_lock(&wq->mutex); 2101 2102 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2103 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 2104 pr_warn("failed to reverse WQN=%x\n", 2105 ibwq->wq_num); 2106 wq->rss_usecnt--; 2107 2108 mutex_unlock(&wq->mutex); 2109 } 2110 } 2111 2112 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2113 struct mlx4_ib_qp *qp) 2114 { 2115 struct mlx4_rss_context *rss_context; 2116 2117 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2118 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2119 2120 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2121 rss_context->default_qpn = 2122 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2123 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2124 rss_context->base_qpn_udp = rss_context->default_qpn; 2125 rss_context->flags = qp->rss_ctx->flags; 2126 /* Currently support just toeplitz */ 2127 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2128 2129 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2130 MLX4_EN_RSS_KEY_SIZE); 2131 } 2132 2133 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2134 const struct ib_qp_attr *attr, int attr_mask, 2135 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2136 { 2137 struct ib_uobject *ibuobject; 2138 struct ib_srq *ibsrq; 2139 struct ib_rwq_ind_table *rwq_ind_tbl; 2140 enum ib_qp_type qp_type; 2141 struct mlx4_ib_dev *dev; 2142 struct mlx4_ib_qp *qp; 2143 struct mlx4_ib_pd *pd; 2144 struct mlx4_ib_cq *send_cq, *recv_cq; 2145 struct mlx4_qp_context *context; 2146 enum mlx4_qp_optpar optpar = 0; 2147 int sqd_event; 2148 int steer_qp = 0; 2149 int err = -EINVAL; 2150 int counter_index; 2151 2152 if (src_type == MLX4_IB_RWQ_SRC) { 2153 struct ib_wq *ibwq; 2154 2155 ibwq = (struct ib_wq *)src; 2156 ibuobject = ibwq->uobject; 2157 ibsrq = NULL; 2158 rwq_ind_tbl = NULL; 2159 qp_type = IB_QPT_RAW_PACKET; 2160 qp = to_mqp((struct ib_qp *)ibwq); 2161 dev = to_mdev(ibwq->device); 2162 pd = to_mpd(ibwq->pd); 2163 } else { 2164 struct ib_qp *ibqp; 2165 2166 ibqp = (struct ib_qp *)src; 2167 ibuobject = ibqp->uobject; 2168 ibsrq = ibqp->srq; 2169 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2170 qp_type = ibqp->qp_type; 2171 qp = to_mqp(ibqp); 2172 dev = to_mdev(ibqp->device); 2173 pd = get_pd(qp); 2174 } 2175 2176 /* APM is not supported under RoCE */ 2177 if (attr_mask & IB_QP_ALT_PATH && 2178 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2179 IB_LINK_LAYER_ETHERNET) 2180 return -ENOTSUPP; 2181 2182 context = kzalloc(sizeof *context, GFP_KERNEL); 2183 if (!context) 2184 return -ENOMEM; 2185 2186 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2187 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2188 2189 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2190 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2191 else { 2192 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2193 switch (attr->path_mig_state) { 2194 case IB_MIG_MIGRATED: 2195 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2196 break; 2197 case IB_MIG_REARM: 2198 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2199 break; 2200 case IB_MIG_ARMED: 2201 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2202 break; 2203 } 2204 } 2205 2206 if (qp->inl_recv_sz) 2207 context->param3 |= cpu_to_be32(1 << 25); 2208 2209 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2210 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2211 else if (qp_type == IB_QPT_RAW_PACKET) 2212 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2213 else if (qp_type == IB_QPT_UD) { 2214 if (qp->flags & MLX4_IB_QP_LSO) 2215 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2216 ilog2(dev->dev->caps.max_gso_sz); 2217 else 2218 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2219 } else if (attr_mask & IB_QP_PATH_MTU) { 2220 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2221 pr_err("path MTU (%u) is invalid\n", 2222 attr->path_mtu); 2223 goto out; 2224 } 2225 context->mtu_msgmax = (attr->path_mtu << 5) | 2226 ilog2(dev->dev->caps.max_msg_sz); 2227 } 2228 2229 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2230 if (qp->rq.wqe_cnt) 2231 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2232 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2233 } 2234 2235 if (qp->sq.wqe_cnt) 2236 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2237 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2238 2239 if (new_state == IB_QPS_RESET && qp->counter_index) 2240 mlx4_ib_free_qp_counter(dev, qp); 2241 2242 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2243 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2244 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2245 if (qp_type == IB_QPT_RAW_PACKET) 2246 context->param3 |= cpu_to_be32(1 << 30); 2247 } 2248 2249 if (ibuobject) 2250 context->usr_page = cpu_to_be32( 2251 mlx4_to_hw_uar_index(dev->dev, 2252 to_mucontext(ibuobject->context) 2253 ->uar.index)); 2254 else 2255 context->usr_page = cpu_to_be32( 2256 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2257 2258 if (attr_mask & IB_QP_DEST_QPN) 2259 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2260 2261 if (attr_mask & IB_QP_PORT) { 2262 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2263 !(attr_mask & IB_QP_AV)) { 2264 mlx4_set_sched(&context->pri_path, attr->port_num); 2265 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2266 } 2267 } 2268 2269 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2270 err = create_qp_lb_counter(dev, qp); 2271 if (err) 2272 goto out; 2273 2274 counter_index = 2275 dev->counters_table[qp->port - 1].default_counter; 2276 if (qp->counter_index) 2277 counter_index = qp->counter_index->index; 2278 2279 if (counter_index != -1) { 2280 context->pri_path.counter_index = counter_index; 2281 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2282 if (qp->counter_index) { 2283 context->pri_path.fl |= 2284 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2285 context->pri_path.vlan_control |= 2286 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2287 } 2288 } else 2289 context->pri_path.counter_index = 2290 MLX4_SINK_COUNTER_INDEX(dev->dev); 2291 2292 if (qp->flags & MLX4_IB_QP_NETIF) { 2293 mlx4_ib_steer_qp_reg(dev, qp, 1); 2294 steer_qp = 1; 2295 } 2296 2297 if (qp_type == IB_QPT_GSI) { 2298 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2299 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2300 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2301 2302 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2303 } 2304 } 2305 2306 if (attr_mask & IB_QP_PKEY_INDEX) { 2307 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2308 context->pri_path.disable_pkey_check = 0x40; 2309 context->pri_path.pkey_index = attr->pkey_index; 2310 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2311 } 2312 2313 if (attr_mask & IB_QP_AV) { 2314 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2315 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2316 union ib_gid gid; 2317 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB}; 2318 u16 vlan = 0xffff; 2319 u8 smac[ETH_ALEN]; 2320 int status = 0; 2321 int is_eth = 2322 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2323 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2324 2325 if (is_eth) { 2326 int index = 2327 rdma_ah_read_grh(&attr->ah_attr)->sgid_index; 2328 2329 status = ib_get_cached_gid(&dev->ib_dev, port_num, 2330 index, &gid, &gid_attr); 2331 if (!status && !memcmp(&gid, &zgid, sizeof(gid))) 2332 status = -ENOENT; 2333 if (!status && gid_attr.ndev) { 2334 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev); 2335 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN); 2336 dev_put(gid_attr.ndev); 2337 } 2338 } 2339 if (status) 2340 goto out; 2341 2342 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2343 port_num, vlan, smac)) 2344 goto out; 2345 2346 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2347 MLX4_QP_OPTPAR_SCHED_QUEUE); 2348 2349 if (is_eth && 2350 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2351 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type); 2352 2353 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2354 err = -EINVAL; 2355 goto out; 2356 } 2357 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2358 } 2359 2360 } 2361 2362 if (attr_mask & IB_QP_TIMEOUT) { 2363 context->pri_path.ackto |= attr->timeout << 3; 2364 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2365 } 2366 2367 if (attr_mask & IB_QP_ALT_PATH) { 2368 if (attr->alt_port_num == 0 || 2369 attr->alt_port_num > dev->dev->caps.num_ports) 2370 goto out; 2371 2372 if (attr->alt_pkey_index >= 2373 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2374 goto out; 2375 2376 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2377 &context->alt_path, 2378 attr->alt_port_num)) 2379 goto out; 2380 2381 context->alt_path.pkey_index = attr->alt_pkey_index; 2382 context->alt_path.ackto = attr->alt_timeout << 3; 2383 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2384 } 2385 2386 context->pd = cpu_to_be32(pd->pdn); 2387 2388 if (!rwq_ind_tbl) { 2389 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2390 get_cqs(qp, src_type, &send_cq, &recv_cq); 2391 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2392 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2393 recv_cq = send_cq; 2394 } 2395 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2396 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2397 2398 /* Set "fast registration enabled" for all kernel QPs */ 2399 if (!ibuobject) 2400 context->params1 |= cpu_to_be32(1 << 11); 2401 2402 if (attr_mask & IB_QP_RNR_RETRY) { 2403 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2404 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2405 } 2406 2407 if (attr_mask & IB_QP_RETRY_CNT) { 2408 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2409 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2410 } 2411 2412 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2413 if (attr->max_rd_atomic) 2414 context->params1 |= 2415 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2416 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2417 } 2418 2419 if (attr_mask & IB_QP_SQ_PSN) 2420 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2421 2422 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2423 if (attr->max_dest_rd_atomic) 2424 context->params2 |= 2425 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2426 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2427 } 2428 2429 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2430 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2431 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2432 } 2433 2434 if (ibsrq) 2435 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2436 2437 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2438 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2439 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2440 } 2441 if (attr_mask & IB_QP_RQ_PSN) 2442 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2443 2444 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2445 if (attr_mask & IB_QP_QKEY) { 2446 if (qp->mlx4_ib_qp_type & 2447 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2448 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2449 else { 2450 if (mlx4_is_mfunc(dev->dev) && 2451 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2452 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2453 MLX4_RESERVED_QKEY_BASE) { 2454 pr_err("Cannot use reserved QKEY" 2455 " 0x%x (range 0xffff0000..0xffffffff" 2456 " is reserved)\n", attr->qkey); 2457 err = -EINVAL; 2458 goto out; 2459 } 2460 context->qkey = cpu_to_be32(attr->qkey); 2461 } 2462 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2463 } 2464 2465 if (ibsrq) 2466 context->srqn = cpu_to_be32(1 << 24 | 2467 to_msrq(ibsrq)->msrq.srqn); 2468 2469 if (qp->rq.wqe_cnt && 2470 cur_state == IB_QPS_RESET && 2471 new_state == IB_QPS_INIT) 2472 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2473 2474 if (cur_state == IB_QPS_INIT && 2475 new_state == IB_QPS_RTR && 2476 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2477 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2478 context->pri_path.sched_queue = (qp->port - 1) << 6; 2479 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2480 qp->mlx4_ib_qp_type & 2481 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2482 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2483 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2484 context->pri_path.fl = 0x80; 2485 } else { 2486 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2487 context->pri_path.fl = 0x80; 2488 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2489 } 2490 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2491 IB_LINK_LAYER_ETHERNET) { 2492 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2493 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2494 context->pri_path.feup = 1 << 7; /* don't fsm */ 2495 /* handle smac_index */ 2496 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2497 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2498 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2499 err = handle_eth_ud_smac_index(dev, qp, context); 2500 if (err) { 2501 err = -EINVAL; 2502 goto out; 2503 } 2504 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2505 dev->qp1_proxy[qp->port - 1] = qp; 2506 } 2507 } 2508 } 2509 2510 if (qp_type == IB_QPT_RAW_PACKET) { 2511 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2512 MLX4_IB_LINK_TYPE_ETH; 2513 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2514 /* set QP to receive both tunneled & non-tunneled packets */ 2515 if (!rwq_ind_tbl) 2516 context->srqn = cpu_to_be32(7 << 28); 2517 } 2518 } 2519 2520 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2521 int is_eth = rdma_port_get_link_layer( 2522 &dev->ib_dev, qp->port) == 2523 IB_LINK_LAYER_ETHERNET; 2524 if (is_eth) { 2525 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2526 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2527 } 2528 } 2529 2530 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2531 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2532 sqd_event = 1; 2533 else 2534 sqd_event = 0; 2535 2536 if (!ibuobject && 2537 cur_state == IB_QPS_RESET && 2538 new_state == IB_QPS_INIT) 2539 context->rlkey_roce_mode |= (1 << 4); 2540 2541 /* 2542 * Before passing a kernel QP to the HW, make sure that the 2543 * ownership bits of the send queue are set and the SQ 2544 * headroom is stamped so that the hardware doesn't start 2545 * processing stale work requests. 2546 */ 2547 if (!ibuobject && 2548 cur_state == IB_QPS_RESET && 2549 new_state == IB_QPS_INIT) { 2550 struct mlx4_wqe_ctrl_seg *ctrl; 2551 int i; 2552 2553 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2554 ctrl = get_send_wqe(qp, i); 2555 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2556 if (qp->sq_max_wqes_per_wr == 1) 2557 ctrl->qpn_vlan.fence_size = 2558 1 << (qp->sq.wqe_shift - 4); 2559 2560 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 2561 } 2562 } 2563 2564 if (rwq_ind_tbl && 2565 cur_state == IB_QPS_RESET && 2566 new_state == IB_QPS_INIT) { 2567 fill_qp_rss_context(context, qp); 2568 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2569 } 2570 2571 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2572 to_mlx4_state(new_state), context, optpar, 2573 sqd_event, &qp->mqp); 2574 if (err) 2575 goto out; 2576 2577 qp->state = new_state; 2578 2579 if (attr_mask & IB_QP_ACCESS_FLAGS) 2580 qp->atomic_rd_en = attr->qp_access_flags; 2581 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2582 qp->resp_depth = attr->max_dest_rd_atomic; 2583 if (attr_mask & IB_QP_PORT) { 2584 qp->port = attr->port_num; 2585 update_mcg_macs(dev, qp); 2586 } 2587 if (attr_mask & IB_QP_ALT_PATH) 2588 qp->alt_port = attr->alt_port_num; 2589 2590 if (is_sqp(dev, qp)) 2591 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2592 2593 /* 2594 * If we moved QP0 to RTR, bring the IB link up; if we moved 2595 * QP0 to RESET or ERROR, bring the link back down. 2596 */ 2597 if (is_qp0(dev, qp)) { 2598 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2599 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2600 pr_warn("INIT_PORT failed for port %d\n", 2601 qp->port); 2602 2603 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2604 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2605 mlx4_CLOSE_PORT(dev->dev, qp->port); 2606 } 2607 2608 /* 2609 * If we moved a kernel QP to RESET, clean up all old CQ 2610 * entries and reinitialize the QP. 2611 */ 2612 if (new_state == IB_QPS_RESET) { 2613 if (!ibuobject) { 2614 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2615 ibsrq ? to_msrq(ibsrq) : NULL); 2616 if (send_cq != recv_cq) 2617 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2618 2619 qp->rq.head = 0; 2620 qp->rq.tail = 0; 2621 qp->sq.head = 0; 2622 qp->sq.tail = 0; 2623 qp->sq_next_wqe = 0; 2624 if (qp->rq.wqe_cnt) 2625 *qp->db.db = 0; 2626 2627 if (qp->flags & MLX4_IB_QP_NETIF) 2628 mlx4_ib_steer_qp_reg(dev, qp, 0); 2629 } 2630 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2631 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2632 qp->pri.smac = 0; 2633 qp->pri.smac_port = 0; 2634 } 2635 if (qp->alt.smac) { 2636 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2637 qp->alt.smac = 0; 2638 } 2639 if (qp->pri.vid < 0x1000) { 2640 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2641 qp->pri.vid = 0xFFFF; 2642 qp->pri.candidate_vid = 0xFFFF; 2643 qp->pri.update_vid = 0; 2644 } 2645 2646 if (qp->alt.vid < 0x1000) { 2647 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2648 qp->alt.vid = 0xFFFF; 2649 qp->alt.candidate_vid = 0xFFFF; 2650 qp->alt.update_vid = 0; 2651 } 2652 } 2653 out: 2654 if (err && qp->counter_index) 2655 mlx4_ib_free_qp_counter(dev, qp); 2656 if (err && steer_qp) 2657 mlx4_ib_steer_qp_reg(dev, qp, 0); 2658 kfree(context); 2659 if (qp->pri.candidate_smac || 2660 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2661 if (err) { 2662 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2663 } else { 2664 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2665 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2666 qp->pri.smac = qp->pri.candidate_smac; 2667 qp->pri.smac_index = qp->pri.candidate_smac_index; 2668 qp->pri.smac_port = qp->pri.candidate_smac_port; 2669 } 2670 qp->pri.candidate_smac = 0; 2671 qp->pri.candidate_smac_index = 0; 2672 qp->pri.candidate_smac_port = 0; 2673 } 2674 if (qp->alt.candidate_smac) { 2675 if (err) { 2676 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2677 } else { 2678 if (qp->alt.smac) 2679 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2680 qp->alt.smac = qp->alt.candidate_smac; 2681 qp->alt.smac_index = qp->alt.candidate_smac_index; 2682 qp->alt.smac_port = qp->alt.candidate_smac_port; 2683 } 2684 qp->alt.candidate_smac = 0; 2685 qp->alt.candidate_smac_index = 0; 2686 qp->alt.candidate_smac_port = 0; 2687 } 2688 2689 if (qp->pri.update_vid) { 2690 if (err) { 2691 if (qp->pri.candidate_vid < 0x1000) 2692 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2693 qp->pri.candidate_vid); 2694 } else { 2695 if (qp->pri.vid < 0x1000) 2696 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2697 qp->pri.vid); 2698 qp->pri.vid = qp->pri.candidate_vid; 2699 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2700 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2701 } 2702 qp->pri.candidate_vid = 0xFFFF; 2703 qp->pri.update_vid = 0; 2704 } 2705 2706 if (qp->alt.update_vid) { 2707 if (err) { 2708 if (qp->alt.candidate_vid < 0x1000) 2709 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2710 qp->alt.candidate_vid); 2711 } else { 2712 if (qp->alt.vid < 0x1000) 2713 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2714 qp->alt.vid); 2715 qp->alt.vid = qp->alt.candidate_vid; 2716 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2717 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2718 } 2719 qp->alt.candidate_vid = 0xFFFF; 2720 qp->alt.update_vid = 0; 2721 } 2722 2723 return err; 2724 } 2725 2726 enum { 2727 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2728 IB_QP_PORT), 2729 }; 2730 2731 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2732 int attr_mask, struct ib_udata *udata) 2733 { 2734 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2735 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2736 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2737 enum ib_qp_state cur_state, new_state; 2738 int err = -EINVAL; 2739 mutex_lock(&qp->mutex); 2740 2741 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2742 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2743 2744 if (cur_state != new_state || cur_state != IB_QPS_RESET) { 2745 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2746 ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2747 } 2748 2749 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2750 attr_mask, ll)) { 2751 pr_debug("qpn 0x%x: invalid attribute mask specified " 2752 "for transition %d to %d. qp_type %d," 2753 " attr_mask 0x%x\n", 2754 ibqp->qp_num, cur_state, new_state, 2755 ibqp->qp_type, attr_mask); 2756 goto out; 2757 } 2758 2759 if (ibqp->rwq_ind_tbl) { 2760 if (!(((cur_state == IB_QPS_RESET) && 2761 (new_state == IB_QPS_INIT)) || 2762 ((cur_state == IB_QPS_INIT) && 2763 (new_state == IB_QPS_RTR)))) { 2764 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2765 ibqp->qp_num, cur_state, new_state); 2766 2767 err = -EOPNOTSUPP; 2768 goto out; 2769 } 2770 2771 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2772 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2773 ibqp->qp_num, attr_mask, cur_state, new_state); 2774 2775 err = -EOPNOTSUPP; 2776 goto out; 2777 } 2778 } 2779 2780 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2781 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2782 if ((ibqp->qp_type == IB_QPT_RC) || 2783 (ibqp->qp_type == IB_QPT_UD) || 2784 (ibqp->qp_type == IB_QPT_UC) || 2785 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2786 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2787 attr->port_num = mlx4_ib_bond_next_port(dev); 2788 } 2789 } else { 2790 /* no sense in changing port_num 2791 * when ports are bonded */ 2792 attr_mask &= ~IB_QP_PORT; 2793 } 2794 } 2795 2796 if ((attr_mask & IB_QP_PORT) && 2797 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2798 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2799 "for transition %d to %d. qp_type %d\n", 2800 ibqp->qp_num, attr->port_num, cur_state, 2801 new_state, ibqp->qp_type); 2802 goto out; 2803 } 2804 2805 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2806 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2807 IB_LINK_LAYER_ETHERNET)) 2808 goto out; 2809 2810 if (attr_mask & IB_QP_PKEY_INDEX) { 2811 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2812 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2813 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2814 "for transition %d to %d. qp_type %d\n", 2815 ibqp->qp_num, attr->pkey_index, cur_state, 2816 new_state, ibqp->qp_type); 2817 goto out; 2818 } 2819 } 2820 2821 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2822 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2823 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2824 "Transition %d to %d. qp_type %d\n", 2825 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2826 new_state, ibqp->qp_type); 2827 goto out; 2828 } 2829 2830 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2831 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2832 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2833 "Transition %d to %d. qp_type %d\n", 2834 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2835 new_state, ibqp->qp_type); 2836 goto out; 2837 } 2838 2839 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2840 err = 0; 2841 goto out; 2842 } 2843 2844 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2845 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num); 2846 if (err) 2847 goto out; 2848 } 2849 2850 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2851 cur_state, new_state); 2852 2853 if (ibqp->rwq_ind_tbl && err) 2854 bring_down_rss_rwqs(ibqp->rwq_ind_tbl); 2855 2856 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2857 attr->port_num = 1; 2858 2859 out: 2860 mutex_unlock(&qp->mutex); 2861 return err; 2862 } 2863 2864 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2865 int attr_mask, struct ib_udata *udata) 2866 { 2867 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2868 int ret; 2869 2870 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2871 2872 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2873 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2874 int err = 0; 2875 2876 if (sqp->roce_v2_gsi) 2877 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2878 if (err) 2879 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2880 err); 2881 } 2882 return ret; 2883 } 2884 2885 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2886 { 2887 int i; 2888 for (i = 0; i < dev->caps.num_ports; i++) { 2889 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2890 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2891 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2892 return 0; 2893 } 2894 } 2895 return -EINVAL; 2896 } 2897 2898 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2899 struct ib_ud_wr *wr, 2900 void *wqe, unsigned *mlx_seg_len) 2901 { 2902 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2903 struct ib_device *ib_dev = &mdev->ib_dev; 2904 struct mlx4_wqe_mlx_seg *mlx = wqe; 2905 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2906 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2907 u16 pkey; 2908 u32 qkey; 2909 int send_size; 2910 int header_size; 2911 int spc; 2912 int i; 2913 2914 if (wr->wr.opcode != IB_WR_SEND) 2915 return -EINVAL; 2916 2917 send_size = 0; 2918 2919 for (i = 0; i < wr->wr.num_sge; ++i) 2920 send_size += wr->wr.sg_list[i].length; 2921 2922 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2923 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2924 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2925 send_size += sizeof (struct mlx4_ib_tunnel_header); 2926 2927 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2928 2929 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2930 sqp->ud_header.lrh.service_level = 2931 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2932 sqp->ud_header.lrh.destination_lid = 2933 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2934 sqp->ud_header.lrh.source_lid = 2935 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2936 } 2937 2938 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2939 2940 /* force loopback */ 2941 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2942 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2943 2944 sqp->ud_header.lrh.virtual_lane = 0; 2945 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2946 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2947 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2948 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2949 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2950 else 2951 sqp->ud_header.bth.destination_qpn = 2952 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel); 2953 2954 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2955 if (mlx4_is_master(mdev->dev)) { 2956 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2957 return -EINVAL; 2958 } else { 2959 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2960 return -EINVAL; 2961 } 2962 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2963 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2964 2965 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2966 sqp->ud_header.immediate_present = 0; 2967 2968 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2969 2970 /* 2971 * Inline data segments may not cross a 64 byte boundary. If 2972 * our UD header is bigger than the space available up to the 2973 * next 64 byte boundary in the WQE, use two inline data 2974 * segments to hold the UD header. 2975 */ 2976 spc = MLX4_INLINE_ALIGN - 2977 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2978 if (header_size <= spc) { 2979 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2980 memcpy(inl + 1, sqp->header_buf, header_size); 2981 i = 1; 2982 } else { 2983 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2984 memcpy(inl + 1, sqp->header_buf, spc); 2985 2986 inl = (void *) (inl + 1) + spc; 2987 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2988 /* 2989 * Need a barrier here to make sure all the data is 2990 * visible before the byte_count field is set. 2991 * Otherwise the HCA prefetcher could grab the 64-byte 2992 * chunk with this inline segment and get a valid (!= 2993 * 0xffffffff) byte count but stale data, and end up 2994 * generating a packet with bad headers. 2995 * 2996 * The first inline segment's byte_count field doesn't 2997 * need a barrier, because it comes after a 2998 * control/MLX segment and therefore is at an offset 2999 * of 16 mod 64. 3000 */ 3001 wmb(); 3002 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3003 i = 2; 3004 } 3005 3006 *mlx_seg_len = 3007 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3008 return 0; 3009 } 3010 3011 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 3012 { 3013 union sl2vl_tbl_to_u64 tmp_vltab; 3014 u8 vl; 3015 3016 if (sl > 15) 3017 return 0xf; 3018 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 3019 vl = tmp_vltab.sl8[sl >> 1]; 3020 if (sl & 1) 3021 vl &= 0x0f; 3022 else 3023 vl >>= 4; 3024 return vl; 3025 } 3026 3027 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 3028 int index, union ib_gid *gid, 3029 enum ib_gid_type *gid_type) 3030 { 3031 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 3032 struct mlx4_port_gid_table *port_gid_table; 3033 unsigned long flags; 3034 3035 port_gid_table = &iboe->gids[port_num - 1]; 3036 spin_lock_irqsave(&iboe->lock, flags); 3037 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 3038 *gid_type = port_gid_table->gids[index].gid_type; 3039 spin_unlock_irqrestore(&iboe->lock, flags); 3040 if (!memcmp(gid, &zgid, sizeof(*gid))) 3041 return -ENOENT; 3042 3043 return 0; 3044 } 3045 3046 #define MLX4_ROCEV2_QP1_SPORT 0xC000 3047 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr, 3048 void *wqe, unsigned *mlx_seg_len) 3049 { 3050 struct ib_device *ib_dev = sqp->qp.ibqp.device; 3051 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 3052 struct mlx4_wqe_mlx_seg *mlx = wqe; 3053 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 3054 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 3055 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3056 union ib_gid sgid; 3057 u16 pkey; 3058 int send_size; 3059 int header_size; 3060 int spc; 3061 int i; 3062 int err = 0; 3063 u16 vlan = 0xffff; 3064 bool is_eth; 3065 bool is_vlan = false; 3066 bool is_grh; 3067 bool is_udp = false; 3068 int ip_version = 0; 3069 3070 send_size = 0; 3071 for (i = 0; i < wr->wr.num_sge; ++i) 3072 send_size += wr->wr.sg_list[i].length; 3073 3074 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 3075 is_grh = mlx4_ib_ah_grh_present(ah); 3076 if (is_eth) { 3077 enum ib_gid_type gid_type; 3078 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3079 /* When multi-function is enabled, the ib_core gid 3080 * indexes don't necessarily match the hw ones, so 3081 * we must use our own cache */ 3082 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 3083 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3084 ah->av.ib.gid_index, &sgid.raw[0]); 3085 if (err) 3086 return err; 3087 } else { 3088 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 3089 ah->av.ib.gid_index, 3090 &sgid, &gid_type); 3091 if (!err) { 3092 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3093 if (is_udp) { 3094 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3095 ip_version = 4; 3096 else 3097 ip_version = 6; 3098 is_grh = false; 3099 } 3100 } else { 3101 return err; 3102 } 3103 } 3104 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3105 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3106 is_vlan = 1; 3107 } 3108 } 3109 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3110 ip_version, is_udp, 0, &sqp->ud_header); 3111 if (err) 3112 return err; 3113 3114 if (!is_eth) { 3115 sqp->ud_header.lrh.service_level = 3116 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3117 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3118 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3119 } 3120 3121 if (is_grh || (ip_version == 6)) { 3122 sqp->ud_header.grh.traffic_class = 3123 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3124 sqp->ud_header.grh.flow_label = 3125 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3126 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3127 if (is_eth) { 3128 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3129 } else { 3130 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3131 /* When multi-function is enabled, the ib_core gid 3132 * indexes don't necessarily match the hw ones, so 3133 * we must use our own cache 3134 */ 3135 sqp->ud_header.grh.source_gid.global.subnet_prefix = 3136 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 3137 demux[sqp->qp.port - 1]. 3138 subnet_prefix))); 3139 sqp->ud_header.grh.source_gid.global.interface_id = 3140 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 3141 guid_cache[ah->av.ib.gid_index]; 3142 } else { 3143 ib_get_cached_gid(ib_dev, 3144 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3145 ah->av.ib.gid_index, 3146 &sqp->ud_header.grh.source_gid, NULL); 3147 } 3148 } 3149 memcpy(sqp->ud_header.grh.destination_gid.raw, 3150 ah->av.ib.dgid, 16); 3151 } 3152 3153 if (ip_version == 4) { 3154 sqp->ud_header.ip4.tos = 3155 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3156 sqp->ud_header.ip4.id = 0; 3157 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3158 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3159 3160 memcpy(&sqp->ud_header.ip4.saddr, 3161 sgid.raw + 12, 4); 3162 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3163 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3164 } 3165 3166 if (is_udp) { 3167 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3168 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3169 sqp->ud_header.udp.csum = 0; 3170 } 3171 3172 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3173 3174 if (!is_eth) { 3175 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3176 (sqp->ud_header.lrh.destination_lid == 3177 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 3178 (sqp->ud_header.lrh.service_level << 8)); 3179 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3180 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3181 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3182 } 3183 3184 switch (wr->wr.opcode) { 3185 case IB_WR_SEND: 3186 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3187 sqp->ud_header.immediate_present = 0; 3188 break; 3189 case IB_WR_SEND_WITH_IMM: 3190 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3191 sqp->ud_header.immediate_present = 1; 3192 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3193 break; 3194 default: 3195 return -EINVAL; 3196 } 3197 3198 if (is_eth) { 3199 struct in6_addr in6; 3200 u16 ether_type; 3201 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3202 3203 ether_type = (!is_udp) ? ETH_P_IBOE: 3204 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3205 3206 mlx->sched_prio = cpu_to_be16(pcp); 3207 3208 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3209 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 3210 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3211 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3212 memcpy(&in6, sgid.raw, sizeof(in6)); 3213 3214 3215 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3216 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3217 if (!is_vlan) { 3218 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3219 } else { 3220 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3221 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3222 } 3223 } else { 3224 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 3225 sl_to_vl(to_mdev(ib_dev), 3226 sqp->ud_header.lrh.service_level, 3227 sqp->qp.port); 3228 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3229 return -EINVAL; 3230 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3231 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3232 } 3233 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3234 if (!sqp->qp.ibqp.qp_num) 3235 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 3236 else 3237 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 3238 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3239 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3240 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3241 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3242 sqp->qkey : wr->remote_qkey); 3243 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 3244 3245 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3246 3247 if (0) { 3248 pr_err("built UD header of size %d:\n", header_size); 3249 for (i = 0; i < header_size / 4; ++i) { 3250 if (i % 8 == 0) 3251 pr_err(" [%02x] ", i * 4); 3252 pr_cont(" %08x", 3253 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3254 if ((i + 1) % 8 == 0) 3255 pr_cont("\n"); 3256 } 3257 pr_err("\n"); 3258 } 3259 3260 /* 3261 * Inline data segments may not cross a 64 byte boundary. If 3262 * our UD header is bigger than the space available up to the 3263 * next 64 byte boundary in the WQE, use two inline data 3264 * segments to hold the UD header. 3265 */ 3266 spc = MLX4_INLINE_ALIGN - 3267 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3268 if (header_size <= spc) { 3269 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3270 memcpy(inl + 1, sqp->header_buf, header_size); 3271 i = 1; 3272 } else { 3273 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3274 memcpy(inl + 1, sqp->header_buf, spc); 3275 3276 inl = (void *) (inl + 1) + spc; 3277 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3278 /* 3279 * Need a barrier here to make sure all the data is 3280 * visible before the byte_count field is set. 3281 * Otherwise the HCA prefetcher could grab the 64-byte 3282 * chunk with this inline segment and get a valid (!= 3283 * 0xffffffff) byte count but stale data, and end up 3284 * generating a packet with bad headers. 3285 * 3286 * The first inline segment's byte_count field doesn't 3287 * need a barrier, because it comes after a 3288 * control/MLX segment and therefore is at an offset 3289 * of 16 mod 64. 3290 */ 3291 wmb(); 3292 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3293 i = 2; 3294 } 3295 3296 *mlx_seg_len = 3297 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3298 return 0; 3299 } 3300 3301 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3302 { 3303 unsigned cur; 3304 struct mlx4_ib_cq *cq; 3305 3306 cur = wq->head - wq->tail; 3307 if (likely(cur + nreq < wq->max_post)) 3308 return 0; 3309 3310 cq = to_mcq(ib_cq); 3311 spin_lock(&cq->lock); 3312 cur = wq->head - wq->tail; 3313 spin_unlock(&cq->lock); 3314 3315 return cur + nreq >= wq->max_post; 3316 } 3317 3318 static __be32 convert_access(int acc) 3319 { 3320 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3321 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3322 (acc & IB_ACCESS_REMOTE_WRITE ? 3323 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3324 (acc & IB_ACCESS_REMOTE_READ ? 3325 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3326 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3327 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3328 } 3329 3330 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3331 struct ib_reg_wr *wr) 3332 { 3333 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3334 3335 fseg->flags = convert_access(wr->access); 3336 fseg->mem_key = cpu_to_be32(wr->key); 3337 fseg->buf_list = cpu_to_be64(mr->page_map); 3338 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3339 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3340 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3341 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3342 fseg->reserved[0] = 0; 3343 fseg->reserved[1] = 0; 3344 } 3345 3346 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3347 { 3348 memset(iseg, 0, sizeof(*iseg)); 3349 iseg->mem_key = cpu_to_be32(rkey); 3350 } 3351 3352 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3353 u64 remote_addr, u32 rkey) 3354 { 3355 rseg->raddr = cpu_to_be64(remote_addr); 3356 rseg->rkey = cpu_to_be32(rkey); 3357 rseg->reserved = 0; 3358 } 3359 3360 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3361 struct ib_atomic_wr *wr) 3362 { 3363 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3364 aseg->swap_add = cpu_to_be64(wr->swap); 3365 aseg->compare = cpu_to_be64(wr->compare_add); 3366 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3367 aseg->swap_add = cpu_to_be64(wr->compare_add); 3368 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3369 } else { 3370 aseg->swap_add = cpu_to_be64(wr->compare_add); 3371 aseg->compare = 0; 3372 } 3373 3374 } 3375 3376 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3377 struct ib_atomic_wr *wr) 3378 { 3379 aseg->swap_add = cpu_to_be64(wr->swap); 3380 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3381 aseg->compare = cpu_to_be64(wr->compare_add); 3382 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3383 } 3384 3385 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3386 struct ib_ud_wr *wr) 3387 { 3388 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3389 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3390 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3391 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3392 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3393 } 3394 3395 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3396 struct mlx4_wqe_datagram_seg *dseg, 3397 struct ib_ud_wr *wr, 3398 enum mlx4_ib_qp_type qpt) 3399 { 3400 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3401 struct mlx4_av sqp_av = {0}; 3402 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3403 3404 /* force loopback */ 3405 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3406 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3407 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3408 cpu_to_be32(0xf0000000); 3409 3410 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3411 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3412 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3413 else 3414 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3415 /* Use QKEY from the QP context, which is set by master */ 3416 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3417 } 3418 3419 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len) 3420 { 3421 struct mlx4_wqe_inline_seg *inl = wqe; 3422 struct mlx4_ib_tunnel_header hdr; 3423 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3424 int spc; 3425 int i; 3426 3427 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3428 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3429 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3430 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3431 memcpy(hdr.mac, ah->av.eth.mac, 6); 3432 hdr.vlan = ah->av.eth.vlan; 3433 3434 spc = MLX4_INLINE_ALIGN - 3435 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3436 if (sizeof (hdr) <= spc) { 3437 memcpy(inl + 1, &hdr, sizeof (hdr)); 3438 wmb(); 3439 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3440 i = 1; 3441 } else { 3442 memcpy(inl + 1, &hdr, spc); 3443 wmb(); 3444 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3445 3446 inl = (void *) (inl + 1) + spc; 3447 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3448 wmb(); 3449 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3450 i = 2; 3451 } 3452 3453 *mlx_seg_len = 3454 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3455 } 3456 3457 static void set_mlx_icrc_seg(void *dseg) 3458 { 3459 u32 *t = dseg; 3460 struct mlx4_wqe_inline_seg *iseg = dseg; 3461 3462 t[1] = 0; 3463 3464 /* 3465 * Need a barrier here before writing the byte_count field to 3466 * make sure that all the data is visible before the 3467 * byte_count field is set. Otherwise, if the segment begins 3468 * a new cacheline, the HCA prefetcher could grab the 64-byte 3469 * chunk and get a valid (!= * 0xffffffff) byte count but 3470 * stale data, and end up sending the wrong data. 3471 */ 3472 wmb(); 3473 3474 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3475 } 3476 3477 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3478 { 3479 dseg->lkey = cpu_to_be32(sg->lkey); 3480 dseg->addr = cpu_to_be64(sg->addr); 3481 3482 /* 3483 * Need a barrier here before writing the byte_count field to 3484 * make sure that all the data is visible before the 3485 * byte_count field is set. Otherwise, if the segment begins 3486 * a new cacheline, the HCA prefetcher could grab the 64-byte 3487 * chunk and get a valid (!= * 0xffffffff) byte count but 3488 * stale data, and end up sending the wrong data. 3489 */ 3490 wmb(); 3491 3492 dseg->byte_count = cpu_to_be32(sg->length); 3493 } 3494 3495 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3496 { 3497 dseg->byte_count = cpu_to_be32(sg->length); 3498 dseg->lkey = cpu_to_be32(sg->lkey); 3499 dseg->addr = cpu_to_be64(sg->addr); 3500 } 3501 3502 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr, 3503 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 3504 __be32 *lso_hdr_sz, __be32 *blh) 3505 { 3506 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3507 3508 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3509 *blh = cpu_to_be32(1 << 6); 3510 3511 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3512 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3513 return -EINVAL; 3514 3515 memcpy(wqe->header, wr->header, wr->hlen); 3516 3517 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3518 *lso_seg_len = halign; 3519 return 0; 3520 } 3521 3522 static __be32 send_ieth(struct ib_send_wr *wr) 3523 { 3524 switch (wr->opcode) { 3525 case IB_WR_SEND_WITH_IMM: 3526 case IB_WR_RDMA_WRITE_WITH_IMM: 3527 return wr->ex.imm_data; 3528 3529 case IB_WR_SEND_WITH_INV: 3530 return cpu_to_be32(wr->ex.invalidate_rkey); 3531 3532 default: 3533 return 0; 3534 } 3535 } 3536 3537 static void add_zero_len_inline(void *wqe) 3538 { 3539 struct mlx4_wqe_inline_seg *inl = wqe; 3540 memset(wqe, 0, 16); 3541 inl->byte_count = cpu_to_be32(1 << 31); 3542 } 3543 3544 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3545 struct ib_send_wr **bad_wr) 3546 { 3547 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3548 void *wqe; 3549 struct mlx4_wqe_ctrl_seg *ctrl; 3550 struct mlx4_wqe_data_seg *dseg; 3551 unsigned long flags; 3552 int nreq; 3553 int err = 0; 3554 unsigned ind; 3555 int uninitialized_var(stamp); 3556 int uninitialized_var(size); 3557 unsigned uninitialized_var(seglen); 3558 __be32 dummy; 3559 __be32 *lso_wqe; 3560 __be32 uninitialized_var(lso_hdr_sz); 3561 __be32 blh; 3562 int i; 3563 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3564 3565 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3566 struct mlx4_ib_sqp *sqp = to_msqp(qp); 3567 3568 if (sqp->roce_v2_gsi) { 3569 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3570 enum ib_gid_type gid_type; 3571 union ib_gid gid; 3572 3573 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 3574 ah->av.ib.gid_index, 3575 &gid, &gid_type)) 3576 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3577 to_mqp(sqp->roce_v2_gsi) : qp; 3578 else 3579 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3580 ah->av.ib.gid_index); 3581 } 3582 } 3583 3584 spin_lock_irqsave(&qp->sq.lock, flags); 3585 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3586 err = -EIO; 3587 *bad_wr = wr; 3588 nreq = 0; 3589 goto out; 3590 } 3591 3592 ind = qp->sq_next_wqe; 3593 3594 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3595 lso_wqe = &dummy; 3596 blh = 0; 3597 3598 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3599 err = -ENOMEM; 3600 *bad_wr = wr; 3601 goto out; 3602 } 3603 3604 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3605 err = -EINVAL; 3606 *bad_wr = wr; 3607 goto out; 3608 } 3609 3610 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3611 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3612 3613 ctrl->srcrb_flags = 3614 (wr->send_flags & IB_SEND_SIGNALED ? 3615 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3616 (wr->send_flags & IB_SEND_SOLICITED ? 3617 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3618 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3619 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3620 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3621 qp->sq_signal_bits; 3622 3623 ctrl->imm = send_ieth(wr); 3624 3625 wqe += sizeof *ctrl; 3626 size = sizeof *ctrl / 16; 3627 3628 switch (qp->mlx4_ib_qp_type) { 3629 case MLX4_IB_QPT_RC: 3630 case MLX4_IB_QPT_UC: 3631 switch (wr->opcode) { 3632 case IB_WR_ATOMIC_CMP_AND_SWP: 3633 case IB_WR_ATOMIC_FETCH_AND_ADD: 3634 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3635 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3636 atomic_wr(wr)->rkey); 3637 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3638 3639 set_atomic_seg(wqe, atomic_wr(wr)); 3640 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3641 3642 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3643 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3644 3645 break; 3646 3647 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3648 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3649 atomic_wr(wr)->rkey); 3650 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3651 3652 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3653 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3654 3655 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3656 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3657 3658 break; 3659 3660 case IB_WR_RDMA_READ: 3661 case IB_WR_RDMA_WRITE: 3662 case IB_WR_RDMA_WRITE_WITH_IMM: 3663 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3664 rdma_wr(wr)->rkey); 3665 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3666 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3667 break; 3668 3669 case IB_WR_LOCAL_INV: 3670 ctrl->srcrb_flags |= 3671 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3672 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3673 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3674 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3675 break; 3676 3677 case IB_WR_REG_MR: 3678 ctrl->srcrb_flags |= 3679 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3680 set_reg_seg(wqe, reg_wr(wr)); 3681 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3682 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3683 break; 3684 3685 default: 3686 /* No extra segments required for sends */ 3687 break; 3688 } 3689 break; 3690 3691 case MLX4_IB_QPT_TUN_SMI_OWNER: 3692 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3693 ctrl, &seglen); 3694 if (unlikely(err)) { 3695 *bad_wr = wr; 3696 goto out; 3697 } 3698 wqe += seglen; 3699 size += seglen / 16; 3700 break; 3701 case MLX4_IB_QPT_TUN_SMI: 3702 case MLX4_IB_QPT_TUN_GSI: 3703 /* this is a UD qp used in MAD responses to slaves. */ 3704 set_datagram_seg(wqe, ud_wr(wr)); 3705 /* set the forced-loopback bit in the data seg av */ 3706 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3707 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3708 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3709 break; 3710 case MLX4_IB_QPT_UD: 3711 set_datagram_seg(wqe, ud_wr(wr)); 3712 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3713 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3714 3715 if (wr->opcode == IB_WR_LSO) { 3716 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3717 &lso_hdr_sz, &blh); 3718 if (unlikely(err)) { 3719 *bad_wr = wr; 3720 goto out; 3721 } 3722 lso_wqe = (__be32 *) wqe; 3723 wqe += seglen; 3724 size += seglen / 16; 3725 } 3726 break; 3727 3728 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3729 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3730 ctrl, &seglen); 3731 if (unlikely(err)) { 3732 *bad_wr = wr; 3733 goto out; 3734 } 3735 wqe += seglen; 3736 size += seglen / 16; 3737 /* to start tunnel header on a cache-line boundary */ 3738 add_zero_len_inline(wqe); 3739 wqe += 16; 3740 size++; 3741 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3742 wqe += seglen; 3743 size += seglen / 16; 3744 break; 3745 case MLX4_IB_QPT_PROXY_SMI: 3746 case MLX4_IB_QPT_PROXY_GSI: 3747 /* If we are tunneling special qps, this is a UD qp. 3748 * In this case we first add a UD segment targeting 3749 * the tunnel qp, and then add a header with address 3750 * information */ 3751 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3752 ud_wr(wr), 3753 qp->mlx4_ib_qp_type); 3754 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3755 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3756 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3757 wqe += seglen; 3758 size += seglen / 16; 3759 break; 3760 3761 case MLX4_IB_QPT_SMI: 3762 case MLX4_IB_QPT_GSI: 3763 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3764 &seglen); 3765 if (unlikely(err)) { 3766 *bad_wr = wr; 3767 goto out; 3768 } 3769 wqe += seglen; 3770 size += seglen / 16; 3771 break; 3772 3773 default: 3774 break; 3775 } 3776 3777 /* 3778 * Write data segments in reverse order, so as to 3779 * overwrite cacheline stamp last within each 3780 * cacheline. This avoids issues with WQE 3781 * prefetching. 3782 */ 3783 3784 dseg = wqe; 3785 dseg += wr->num_sge - 1; 3786 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3787 3788 /* Add one more inline data segment for ICRC for MLX sends */ 3789 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3790 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3791 qp->mlx4_ib_qp_type & 3792 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3793 set_mlx_icrc_seg(dseg + 1); 3794 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3795 } 3796 3797 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3798 set_data_seg(dseg, wr->sg_list + i); 3799 3800 /* 3801 * Possibly overwrite stamping in cacheline with LSO 3802 * segment only after making sure all data segments 3803 * are written. 3804 */ 3805 wmb(); 3806 *lso_wqe = lso_hdr_sz; 3807 3808 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3809 MLX4_WQE_CTRL_FENCE : 0) | size; 3810 3811 /* 3812 * Make sure descriptor is fully written before 3813 * setting ownership bit (because HW can start 3814 * executing as soon as we do). 3815 */ 3816 wmb(); 3817 3818 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3819 *bad_wr = wr; 3820 err = -EINVAL; 3821 goto out; 3822 } 3823 3824 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3825 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3826 3827 stamp = ind + qp->sq_spare_wqes; 3828 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3829 3830 /* 3831 * We can improve latency by not stamping the last 3832 * send queue WQE until after ringing the doorbell, so 3833 * only stamp here if there are still more WQEs to post. 3834 * 3835 * Same optimization applies to padding with NOP wqe 3836 * in case of WQE shrinking (used to prevent wrap-around 3837 * in the middle of WR). 3838 */ 3839 if (wr->next) { 3840 stamp_send_wqe(qp, stamp, size * 16); 3841 ind = pad_wraparound(qp, ind); 3842 } 3843 } 3844 3845 out: 3846 if (likely(nreq)) { 3847 qp->sq.head += nreq; 3848 3849 /* 3850 * Make sure that descriptors are written before 3851 * doorbell record. 3852 */ 3853 wmb(); 3854 3855 writel(qp->doorbell_qpn, 3856 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3857 3858 /* 3859 * Make sure doorbells don't leak out of SQ spinlock 3860 * and reach the HCA out of order. 3861 */ 3862 mmiowb(); 3863 3864 stamp_send_wqe(qp, stamp, size * 16); 3865 3866 ind = pad_wraparound(qp, ind); 3867 qp->sq_next_wqe = ind; 3868 } 3869 3870 spin_unlock_irqrestore(&qp->sq.lock, flags); 3871 3872 return err; 3873 } 3874 3875 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3876 struct ib_recv_wr **bad_wr) 3877 { 3878 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3879 struct mlx4_wqe_data_seg *scat; 3880 unsigned long flags; 3881 int err = 0; 3882 int nreq; 3883 int ind; 3884 int max_gs; 3885 int i; 3886 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3887 3888 max_gs = qp->rq.max_gs; 3889 spin_lock_irqsave(&qp->rq.lock, flags); 3890 3891 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3892 err = -EIO; 3893 *bad_wr = wr; 3894 nreq = 0; 3895 goto out; 3896 } 3897 3898 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3899 3900 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3901 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3902 err = -ENOMEM; 3903 *bad_wr = wr; 3904 goto out; 3905 } 3906 3907 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3908 err = -EINVAL; 3909 *bad_wr = wr; 3910 goto out; 3911 } 3912 3913 scat = get_recv_wqe(qp, ind); 3914 3915 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3916 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3917 ib_dma_sync_single_for_device(ibqp->device, 3918 qp->sqp_proxy_rcv[ind].map, 3919 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3920 DMA_FROM_DEVICE); 3921 scat->byte_count = 3922 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3923 /* use dma lkey from upper layer entry */ 3924 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3925 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3926 scat++; 3927 max_gs--; 3928 } 3929 3930 for (i = 0; i < wr->num_sge; ++i) 3931 __set_data_seg(scat + i, wr->sg_list + i); 3932 3933 if (i < max_gs) { 3934 scat[i].byte_count = 0; 3935 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3936 scat[i].addr = 0; 3937 } 3938 3939 qp->rq.wrid[ind] = wr->wr_id; 3940 3941 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3942 } 3943 3944 out: 3945 if (likely(nreq)) { 3946 qp->rq.head += nreq; 3947 3948 /* 3949 * Make sure that descriptors are written before 3950 * doorbell record. 3951 */ 3952 wmb(); 3953 3954 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3955 } 3956 3957 spin_unlock_irqrestore(&qp->rq.lock, flags); 3958 3959 return err; 3960 } 3961 3962 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3963 { 3964 switch (mlx4_state) { 3965 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3966 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3967 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3968 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3969 case MLX4_QP_STATE_SQ_DRAINING: 3970 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3971 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3972 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3973 default: return -1; 3974 } 3975 } 3976 3977 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3978 { 3979 switch (mlx4_mig_state) { 3980 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3981 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3982 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3983 default: return -1; 3984 } 3985 } 3986 3987 static int to_ib_qp_access_flags(int mlx4_flags) 3988 { 3989 int ib_flags = 0; 3990 3991 if (mlx4_flags & MLX4_QP_BIT_RRE) 3992 ib_flags |= IB_ACCESS_REMOTE_READ; 3993 if (mlx4_flags & MLX4_QP_BIT_RWE) 3994 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3995 if (mlx4_flags & MLX4_QP_BIT_RAE) 3996 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3997 3998 return ib_flags; 3999 } 4000 4001 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 4002 struct rdma_ah_attr *ah_attr, 4003 struct mlx4_qp_path *path) 4004 { 4005 struct mlx4_dev *dev = ibdev->dev; 4006 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 4007 4008 memset(ah_attr, 0, sizeof(*ah_attr)); 4009 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 4010 if (port_num == 0 || port_num > dev->caps.num_ports) 4011 return; 4012 4013 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 4014 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 4015 ((path->sched_queue & 4) << 1)); 4016 else 4017 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 4018 rdma_ah_set_port_num(ah_attr, port_num); 4019 4020 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4021 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 4022 rdma_ah_set_static_rate(ah_attr, 4023 path->static_rate ? path->static_rate - 5 : 0); 4024 if (path->grh_mylmc & (1 << 7)) { 4025 rdma_ah_set_grh(ah_attr, NULL, 4026 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 4027 path->mgid_index, 4028 path->hop_limit, 4029 (be32_to_cpu(path->tclass_flowlabel) 4030 >> 20) & 0xff); 4031 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4032 } 4033 } 4034 4035 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 4036 struct ib_qp_init_attr *qp_init_attr) 4037 { 4038 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 4039 struct mlx4_ib_qp *qp = to_mqp(ibqp); 4040 struct mlx4_qp_context context; 4041 int mlx4_state; 4042 int err = 0; 4043 4044 if (ibqp->rwq_ind_tbl) 4045 return -EOPNOTSUPP; 4046 4047 mutex_lock(&qp->mutex); 4048 4049 if (qp->state == IB_QPS_RESET) { 4050 qp_attr->qp_state = IB_QPS_RESET; 4051 goto done; 4052 } 4053 4054 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 4055 if (err) { 4056 err = -EINVAL; 4057 goto out; 4058 } 4059 4060 mlx4_state = be32_to_cpu(context.flags) >> 28; 4061 4062 qp->state = to_ib_qp_state(mlx4_state); 4063 qp_attr->qp_state = qp->state; 4064 qp_attr->path_mtu = context.mtu_msgmax >> 5; 4065 qp_attr->path_mig_state = 4066 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 4067 qp_attr->qkey = be32_to_cpu(context.qkey); 4068 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 4069 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 4070 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 4071 qp_attr->qp_access_flags = 4072 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 4073 4074 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4075 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 4076 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 4077 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 4078 qp_attr->alt_port_num = 4079 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4080 } 4081 4082 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 4083 if (qp_attr->qp_state == IB_QPS_INIT) 4084 qp_attr->port_num = qp->port; 4085 else 4086 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 4087 4088 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4089 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 4090 4091 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 4092 4093 qp_attr->max_dest_rd_atomic = 4094 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4095 qp_attr->min_rnr_timer = 4096 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4097 qp_attr->timeout = context.pri_path.ackto >> 3; 4098 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4099 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4100 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4101 4102 done: 4103 qp_attr->cur_qp_state = qp_attr->qp_state; 4104 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4105 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4106 4107 if (!ibqp->uobject) { 4108 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4109 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4110 } else { 4111 qp_attr->cap.max_send_wr = 0; 4112 qp_attr->cap.max_send_sge = 0; 4113 } 4114 4115 /* 4116 * We don't support inline sends for kernel QPs (yet), and we 4117 * don't know what userspace's value should be. 4118 */ 4119 qp_attr->cap.max_inline_data = 0; 4120 4121 qp_init_attr->cap = qp_attr->cap; 4122 4123 qp_init_attr->create_flags = 0; 4124 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4125 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4126 4127 if (qp->flags & MLX4_IB_QP_LSO) 4128 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4129 4130 if (qp->flags & MLX4_IB_QP_NETIF) 4131 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4132 4133 qp_init_attr->sq_sig_type = 4134 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4135 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4136 4137 out: 4138 mutex_unlock(&qp->mutex); 4139 return err; 4140 } 4141 4142 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4143 struct ib_wq_init_attr *init_attr, 4144 struct ib_udata *udata) 4145 { 4146 struct mlx4_ib_dev *dev; 4147 struct ib_qp_init_attr ib_qp_init_attr; 4148 struct mlx4_ib_qp *qp; 4149 struct mlx4_ib_create_wq ucmd; 4150 int err, required_cmd_sz; 4151 4152 if (!(udata && pd->uobject)) 4153 return ERR_PTR(-EINVAL); 4154 4155 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4156 sizeof(ucmd.comp_mask); 4157 if (udata->inlen < required_cmd_sz) { 4158 pr_debug("invalid inlen\n"); 4159 return ERR_PTR(-EINVAL); 4160 } 4161 4162 if (udata->inlen > sizeof(ucmd) && 4163 !ib_is_udata_cleared(udata, sizeof(ucmd), 4164 udata->inlen - sizeof(ucmd))) { 4165 pr_debug("inlen is not supported\n"); 4166 return ERR_PTR(-EOPNOTSUPP); 4167 } 4168 4169 if (udata->outlen) 4170 return ERR_PTR(-EOPNOTSUPP); 4171 4172 dev = to_mdev(pd->device); 4173 4174 if (init_attr->wq_type != IB_WQT_RQ) { 4175 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4176 return ERR_PTR(-EOPNOTSUPP); 4177 } 4178 4179 if (init_attr->create_flags) { 4180 pr_debug("unsupported create_flags %u\n", 4181 init_attr->create_flags); 4182 return ERR_PTR(-EOPNOTSUPP); 4183 } 4184 4185 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4186 if (!qp) 4187 return ERR_PTR(-ENOMEM); 4188 4189 qp->pri.vid = 0xFFFF; 4190 qp->alt.vid = 0xFFFF; 4191 4192 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr)); 4193 ib_qp_init_attr.qp_context = init_attr->wq_context; 4194 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4195 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4196 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4197 ib_qp_init_attr.recv_cq = init_attr->cq; 4198 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4199 4200 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr, 4201 udata, 0, &qp); 4202 if (err) { 4203 kfree(qp); 4204 return ERR_PTR(err); 4205 } 4206 4207 qp->ibwq.event_handler = init_attr->event_handler; 4208 qp->ibwq.wq_num = qp->mqp.qpn; 4209 qp->ibwq.state = IB_WQS_RESET; 4210 4211 return &qp->ibwq; 4212 } 4213 4214 static int ib_wq2qp_state(enum ib_wq_state state) 4215 { 4216 switch (state) { 4217 case IB_WQS_RESET: 4218 return IB_QPS_RESET; 4219 case IB_WQS_RDY: 4220 return IB_QPS_RTR; 4221 default: 4222 return IB_QPS_ERR; 4223 } 4224 } 4225 4226 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state) 4227 { 4228 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4229 enum ib_qp_state qp_cur_state; 4230 enum ib_qp_state qp_new_state; 4231 int attr_mask; 4232 int err; 4233 4234 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4235 * the WQ logic state. 4236 */ 4237 qp_cur_state = qp->state; 4238 qp_new_state = ib_wq2qp_state(new_state); 4239 4240 if (ib_wq2qp_state(new_state) == qp_cur_state) 4241 return 0; 4242 4243 if (new_state == IB_WQS_RDY) { 4244 struct ib_qp_attr attr = {}; 4245 4246 attr.port_num = qp->port; 4247 attr_mask = IB_QP_PORT; 4248 4249 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4250 attr_mask, IB_QPS_RESET, IB_QPS_INIT); 4251 if (err) { 4252 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4253 ibwq->wq_num); 4254 return err; 4255 } 4256 4257 qp_cur_state = IB_QPS_INIT; 4258 } 4259 4260 attr_mask = 0; 4261 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4262 qp_cur_state, qp_new_state); 4263 4264 if (err && (qp_cur_state == IB_QPS_INIT)) { 4265 qp_new_state = IB_QPS_RESET; 4266 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4267 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) { 4268 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4269 ibwq->wq_num); 4270 qp_new_state = IB_QPS_INIT; 4271 } 4272 } 4273 4274 qp->state = qp_new_state; 4275 4276 return err; 4277 } 4278 4279 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4280 u32 wq_attr_mask, struct ib_udata *udata) 4281 { 4282 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4283 struct mlx4_ib_modify_wq ucmd = {}; 4284 size_t required_cmd_sz; 4285 enum ib_wq_state cur_state, new_state; 4286 int err = 0; 4287 4288 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4289 sizeof(ucmd.reserved); 4290 if (udata->inlen < required_cmd_sz) 4291 return -EINVAL; 4292 4293 if (udata->inlen > sizeof(ucmd) && 4294 !ib_is_udata_cleared(udata, sizeof(ucmd), 4295 udata->inlen - sizeof(ucmd))) 4296 return -EOPNOTSUPP; 4297 4298 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4299 return -EFAULT; 4300 4301 if (ucmd.comp_mask || ucmd.reserved) 4302 return -EOPNOTSUPP; 4303 4304 if (wq_attr_mask & IB_WQ_FLAGS) 4305 return -EOPNOTSUPP; 4306 4307 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state : 4308 ibwq->state; 4309 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state; 4310 4311 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR || 4312 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR) 4313 return -EINVAL; 4314 4315 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4316 return -EINVAL; 4317 4318 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4319 return -EINVAL; 4320 4321 /* Need to protect against the parent RSS which also may modify WQ 4322 * state. 4323 */ 4324 mutex_lock(&qp->mutex); 4325 4326 /* Can update HW state only if a RSS QP has already associated to this 4327 * WQ, so we can apply its port on the WQ. 4328 */ 4329 if (qp->rss_usecnt) 4330 err = _mlx4_ib_modify_wq(ibwq, new_state); 4331 4332 if (!err) 4333 ibwq->state = new_state; 4334 4335 mutex_unlock(&qp->mutex); 4336 4337 return err; 4338 } 4339 4340 int mlx4_ib_destroy_wq(struct ib_wq *ibwq) 4341 { 4342 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4343 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4344 4345 if (qp->counter_index) 4346 mlx4_ib_free_qp_counter(dev, qp); 4347 4348 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1); 4349 4350 kfree(qp); 4351 4352 return 0; 4353 } 4354 4355 struct ib_rwq_ind_table 4356 *mlx4_ib_create_rwq_ind_table(struct ib_device *device, 4357 struct ib_rwq_ind_table_init_attr *init_attr, 4358 struct ib_udata *udata) 4359 { 4360 struct ib_rwq_ind_table *rwq_ind_table; 4361 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4362 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4363 unsigned int base_wqn; 4364 size_t min_resp_len; 4365 int i; 4366 int err; 4367 4368 if (udata->inlen > 0 && 4369 !ib_is_udata_cleared(udata, 0, 4370 udata->inlen)) 4371 return ERR_PTR(-EOPNOTSUPP); 4372 4373 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4374 if (udata->outlen && udata->outlen < min_resp_len) 4375 return ERR_PTR(-EINVAL); 4376 4377 if (ind_tbl_size > 4378 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4379 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4380 ind_tbl_size, 4381 device->attrs.rss_caps.max_rwq_indirection_table_size); 4382 return ERR_PTR(-EINVAL); 4383 } 4384 4385 base_wqn = init_attr->ind_tbl[0]->wq_num; 4386 4387 if (base_wqn % ind_tbl_size) { 4388 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4389 base_wqn); 4390 return ERR_PTR(-EINVAL); 4391 } 4392 4393 for (i = 1; i < ind_tbl_size; i++) { 4394 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4395 pr_debug("indirection table's WQNs aren't consecutive\n"); 4396 return ERR_PTR(-EINVAL); 4397 } 4398 } 4399 4400 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL); 4401 if (!rwq_ind_table) 4402 return ERR_PTR(-ENOMEM); 4403 4404 if (udata->outlen) { 4405 resp.response_length = offsetof(typeof(resp), response_length) + 4406 sizeof(resp.response_length); 4407 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4408 if (err) 4409 goto err; 4410 } 4411 4412 return rwq_ind_table; 4413 4414 err: 4415 kfree(rwq_ind_table); 4416 return ERR_PTR(err); 4417 } 4418 4419 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4420 { 4421 kfree(ib_rwq_ind_tbl); 4422 return 0; 4423 } 4424