1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 45 #include <linux/mlx4/driver.h> 46 #include <linux/mlx4/qp.h> 47 48 #include "mlx4_ib.h" 49 #include <rdma/mlx4-abi.h> 50 51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 52 struct mlx4_ib_cq *recv_cq); 53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 54 struct mlx4_ib_cq *recv_cq); 55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state); 56 57 enum { 58 MLX4_IB_ACK_REQ_FREQ = 8, 59 }; 60 61 enum { 62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 64 MLX4_IB_LINK_TYPE_IB = 0, 65 MLX4_IB_LINK_TYPE_ETH = 1 66 }; 67 68 enum { 69 /* 70 * Largest possible UD header: send with GRH and immediate 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 72 * tag. (LRH would only use 8 bytes, so Ethernet is the 73 * biggest case) 74 */ 75 MLX4_IB_UD_HEADER_SIZE = 82, 76 MLX4_IB_LSO_HEADER_SPARE = 128, 77 }; 78 79 struct mlx4_ib_sqp { 80 struct mlx4_ib_qp qp; 81 int pkey_index; 82 u32 qkey; 83 u32 send_psn; 84 struct ib_ud_header ud_header; 85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 86 struct ib_qp *roce_v2_gsi; 87 }; 88 89 enum { 90 MLX4_IB_MIN_SQ_STRIDE = 6, 91 MLX4_IB_CACHE_LINE_SIZE = 64, 92 }; 93 94 enum { 95 MLX4_RAW_QP_MTU = 7, 96 MLX4_RAW_QP_MSGMAX = 31, 97 }; 98 99 #ifndef ETH_ALEN 100 #define ETH_ALEN 6 101 #endif 102 103 static const __be32 mlx4_ib_opcode[] = { 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 117 }; 118 119 enum mlx4_ib_source_type { 120 MLX4_IB_QP_SRC = 0, 121 MLX4_IB_RWQ_SRC = 1, 122 }; 123 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 125 { 126 return container_of(mqp, struct mlx4_ib_sqp, qp); 127 } 128 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 130 { 131 if (!mlx4_is_master(dev->dev)) 132 return 0; 133 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 136 8 * MLX4_MFUNC_MAX; 137 } 138 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 140 { 141 int proxy_sqp = 0; 142 int real_sqp = 0; 143 int i; 144 /* PPF or Native -- real SQP */ 145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 148 if (real_sqp) 149 return 1; 150 /* VF or PF -- proxy SQP */ 151 if (mlx4_is_mfunc(dev->dev)) { 152 for (i = 0; i < dev->dev->caps.num_ports; i++) { 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 155 proxy_sqp = 1; 156 break; 157 } 158 } 159 } 160 if (proxy_sqp) 161 return 1; 162 163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 164 } 165 166 /* used for INIT/CLOSE port logic */ 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 168 { 169 int proxy_qp0 = 0; 170 int real_qp0 = 0; 171 int i; 172 /* PPF or Native -- real QP0 */ 173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 176 if (real_qp0) 177 return 1; 178 /* VF or PF -- proxy QP0 */ 179 if (mlx4_is_mfunc(dev->dev)) { 180 for (i = 0; i < dev->dev->caps.num_ports; i++) { 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 182 proxy_qp0 = 1; 183 break; 184 } 185 } 186 } 187 return proxy_qp0; 188 } 189 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 191 { 192 return mlx4_buf_offset(&qp->buf, offset); 193 } 194 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 196 { 197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 198 } 199 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 201 { 202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 203 } 204 205 /* 206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 207 * first four bytes of every 64 byte chunk with 0xffffffff, except for 208 * the very first chunk of the WQE. 209 */ 210 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 211 { 212 __be32 *wqe; 213 int i; 214 int s; 215 void *buf; 216 struct mlx4_wqe_ctrl_seg *ctrl; 217 218 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 219 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 220 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 221 for (i = 64; i < s; i += 64) { 222 wqe = buf + i; 223 *wqe = cpu_to_be32(0xffffffff); 224 } 225 } 226 227 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 228 { 229 struct ib_event event; 230 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 231 232 if (type == MLX4_EVENT_TYPE_PATH_MIG) 233 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 234 235 if (ibqp->event_handler) { 236 event.device = ibqp->device; 237 event.element.qp = ibqp; 238 switch (type) { 239 case MLX4_EVENT_TYPE_PATH_MIG: 240 event.event = IB_EVENT_PATH_MIG; 241 break; 242 case MLX4_EVENT_TYPE_COMM_EST: 243 event.event = IB_EVENT_COMM_EST; 244 break; 245 case MLX4_EVENT_TYPE_SQ_DRAINED: 246 event.event = IB_EVENT_SQ_DRAINED; 247 break; 248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 249 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 250 break; 251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 252 event.event = IB_EVENT_QP_FATAL; 253 break; 254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 255 event.event = IB_EVENT_PATH_MIG_ERR; 256 break; 257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 258 event.event = IB_EVENT_QP_REQ_ERR; 259 break; 260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 261 event.event = IB_EVENT_QP_ACCESS_ERR; 262 break; 263 default: 264 pr_warn("Unexpected event type %d " 265 "on QP %06x\n", type, qp->qpn); 266 return; 267 } 268 269 ibqp->event_handler(&event, ibqp->qp_context); 270 } 271 } 272 273 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 274 { 275 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 276 type, qp->qpn); 277 } 278 279 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 280 { 281 /* 282 * UD WQEs must have a datagram segment. 283 * RC and UC WQEs might have a remote address segment. 284 * MLX WQEs need two extra inline data segments (for the UD 285 * header and space for the ICRC). 286 */ 287 switch (type) { 288 case MLX4_IB_QPT_UD: 289 return sizeof (struct mlx4_wqe_ctrl_seg) + 290 sizeof (struct mlx4_wqe_datagram_seg) + 291 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 292 case MLX4_IB_QPT_PROXY_SMI_OWNER: 293 case MLX4_IB_QPT_PROXY_SMI: 294 case MLX4_IB_QPT_PROXY_GSI: 295 return sizeof (struct mlx4_wqe_ctrl_seg) + 296 sizeof (struct mlx4_wqe_datagram_seg) + 64; 297 case MLX4_IB_QPT_TUN_SMI_OWNER: 298 case MLX4_IB_QPT_TUN_GSI: 299 return sizeof (struct mlx4_wqe_ctrl_seg) + 300 sizeof (struct mlx4_wqe_datagram_seg); 301 302 case MLX4_IB_QPT_UC: 303 return sizeof (struct mlx4_wqe_ctrl_seg) + 304 sizeof (struct mlx4_wqe_raddr_seg); 305 case MLX4_IB_QPT_RC: 306 return sizeof (struct mlx4_wqe_ctrl_seg) + 307 sizeof (struct mlx4_wqe_masked_atomic_seg) + 308 sizeof (struct mlx4_wqe_raddr_seg); 309 case MLX4_IB_QPT_SMI: 310 case MLX4_IB_QPT_GSI: 311 return sizeof (struct mlx4_wqe_ctrl_seg) + 312 ALIGN(MLX4_IB_UD_HEADER_SIZE + 313 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 314 MLX4_INLINE_ALIGN) * 315 sizeof (struct mlx4_wqe_inline_seg), 316 sizeof (struct mlx4_wqe_data_seg)) + 317 ALIGN(4 + 318 sizeof (struct mlx4_wqe_inline_seg), 319 sizeof (struct mlx4_wqe_data_seg)); 320 default: 321 return sizeof (struct mlx4_wqe_ctrl_seg); 322 } 323 } 324 325 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 326 bool is_user, int has_rq, struct mlx4_ib_qp *qp, 327 u32 inl_recv_sz) 328 { 329 /* Sanity check RQ size before proceeding */ 330 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 331 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 332 return -EINVAL; 333 334 if (!has_rq) { 335 if (cap->max_recv_wr || inl_recv_sz) 336 return -EINVAL; 337 338 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 339 } else { 340 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 341 sizeof(struct mlx4_wqe_data_seg); 342 u32 wqe_size; 343 344 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 345 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 346 inl_recv_sz > max_inl_recv_sz)) 347 return -EINVAL; 348 349 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 350 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 351 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 352 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 353 } 354 355 /* leave userspace return values as they were, so as not to break ABI */ 356 if (is_user) { 357 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 358 cap->max_recv_sge = qp->rq.max_gs; 359 } else { 360 cap->max_recv_wr = qp->rq.max_post = 361 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 362 cap->max_recv_sge = min(qp->rq.max_gs, 363 min(dev->dev->caps.max_sq_sg, 364 dev->dev->caps.max_rq_sg)); 365 } 366 367 return 0; 368 } 369 370 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 371 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 372 { 373 int s; 374 375 /* Sanity check SQ size before proceeding */ 376 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 377 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 378 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 379 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 380 return -EINVAL; 381 382 /* 383 * For MLX transport we need 2 extra S/G entries: 384 * one for the header and one for the checksum at the end 385 */ 386 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 387 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 388 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 389 return -EINVAL; 390 391 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 392 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 393 send_wqe_overhead(type, qp->flags); 394 395 if (s > dev->dev->caps.max_sq_desc_sz) 396 return -EINVAL; 397 398 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 399 400 /* 401 * We need to leave 2 KB + 1 WR of headroom in the SQ to 402 * allow HW to prefetch. 403 */ 404 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 405 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 406 qp->sq_spare_wqes); 407 408 qp->sq.max_gs = 409 (min(dev->dev->caps.max_sq_desc_sz, 410 (1 << qp->sq.wqe_shift)) - 411 send_wqe_overhead(type, qp->flags)) / 412 sizeof (struct mlx4_wqe_data_seg); 413 414 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 415 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 416 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 417 qp->rq.offset = 0; 418 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 419 } else { 420 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 421 qp->sq.offset = 0; 422 } 423 424 cap->max_send_wr = qp->sq.max_post = 425 qp->sq.wqe_cnt - qp->sq_spare_wqes; 426 cap->max_send_sge = min(qp->sq.max_gs, 427 min(dev->dev->caps.max_sq_sg, 428 dev->dev->caps.max_rq_sg)); 429 /* We don't support inline sends for kernel QPs (yet) */ 430 cap->max_inline_data = 0; 431 432 return 0; 433 } 434 435 static int set_user_sq_size(struct mlx4_ib_dev *dev, 436 struct mlx4_ib_qp *qp, 437 struct mlx4_ib_create_qp *ucmd) 438 { 439 /* Sanity check SQ size before proceeding */ 440 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 441 ucmd->log_sq_stride > 442 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 443 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 444 return -EINVAL; 445 446 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 447 qp->sq.wqe_shift = ucmd->log_sq_stride; 448 449 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 450 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 451 452 return 0; 453 } 454 455 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 456 { 457 int i; 458 459 qp->sqp_proxy_rcv = 460 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf), 461 GFP_KERNEL); 462 if (!qp->sqp_proxy_rcv) 463 return -ENOMEM; 464 for (i = 0; i < qp->rq.wqe_cnt; i++) { 465 qp->sqp_proxy_rcv[i].addr = 466 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 467 GFP_KERNEL); 468 if (!qp->sqp_proxy_rcv[i].addr) 469 goto err; 470 qp->sqp_proxy_rcv[i].map = 471 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 472 sizeof (struct mlx4_ib_proxy_sqp_hdr), 473 DMA_FROM_DEVICE); 474 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 475 kfree(qp->sqp_proxy_rcv[i].addr); 476 goto err; 477 } 478 } 479 return 0; 480 481 err: 482 while (i > 0) { 483 --i; 484 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 485 sizeof (struct mlx4_ib_proxy_sqp_hdr), 486 DMA_FROM_DEVICE); 487 kfree(qp->sqp_proxy_rcv[i].addr); 488 } 489 kfree(qp->sqp_proxy_rcv); 490 qp->sqp_proxy_rcv = NULL; 491 return -ENOMEM; 492 } 493 494 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 495 { 496 int i; 497 498 for (i = 0; i < qp->rq.wqe_cnt; i++) { 499 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 500 sizeof (struct mlx4_ib_proxy_sqp_hdr), 501 DMA_FROM_DEVICE); 502 kfree(qp->sqp_proxy_rcv[i].addr); 503 } 504 kfree(qp->sqp_proxy_rcv); 505 } 506 507 static int qp_has_rq(struct ib_qp_init_attr *attr) 508 { 509 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 510 return 0; 511 512 return !attr->srq; 513 } 514 515 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 516 { 517 int i; 518 for (i = 0; i < dev->caps.num_ports; i++) { 519 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 520 return !!dev->caps.spec_qps[i].qp0_qkey; 521 } 522 return 0; 523 } 524 525 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 526 struct mlx4_ib_qp *qp) 527 { 528 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 529 mlx4_counter_free(dev->dev, qp->counter_index->index); 530 list_del(&qp->counter_index->list); 531 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 532 533 kfree(qp->counter_index); 534 qp->counter_index = NULL; 535 } 536 537 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 538 struct ib_qp_init_attr *init_attr, 539 struct mlx4_ib_create_qp_rss *ucmd) 540 { 541 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 542 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 543 544 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 545 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 546 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 547 MLX4_EN_RSS_KEY_SIZE); 548 } else { 549 pr_debug("RX Hash function is not supported\n"); 550 return (-EOPNOTSUPP); 551 } 552 553 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | 554 MLX4_IB_RX_HASH_DST_IPV4 | 555 MLX4_IB_RX_HASH_SRC_IPV6 | 556 MLX4_IB_RX_HASH_DST_IPV6 | 557 MLX4_IB_RX_HASH_SRC_PORT_TCP | 558 MLX4_IB_RX_HASH_DST_PORT_TCP | 559 MLX4_IB_RX_HASH_SRC_PORT_UDP | 560 MLX4_IB_RX_HASH_DST_PORT_UDP | 561 MLX4_IB_RX_HASH_INNER)) { 562 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 563 ucmd->rx_hash_fields_mask); 564 return (-EOPNOTSUPP); 565 } 566 567 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 568 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 569 rss_ctx->flags = MLX4_RSS_IPV4; 570 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 571 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 572 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 573 return (-EOPNOTSUPP); 574 } 575 576 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 578 rss_ctx->flags |= MLX4_RSS_IPV6; 579 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 580 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 581 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 582 return (-EOPNOTSUPP); 583 } 584 585 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 586 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 587 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 588 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 589 return (-EOPNOTSUPP); 590 } 591 592 if (rss_ctx->flags & MLX4_RSS_IPV4) 593 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 594 if (rss_ctx->flags & MLX4_RSS_IPV6) 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 596 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 597 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 598 return (-EOPNOTSUPP); 599 } 600 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 601 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 602 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 603 return (-EOPNOTSUPP); 604 } 605 606 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 607 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 608 if (rss_ctx->flags & MLX4_RSS_IPV4) 609 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 610 if (rss_ctx->flags & MLX4_RSS_IPV6) 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 612 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 613 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 614 return (-EOPNOTSUPP); 615 } 616 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 617 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 618 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 619 return (-EOPNOTSUPP); 620 } 621 622 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 623 if (dev->dev->caps.tunnel_offload_mode == 624 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 625 /* 626 * Hash according to inner headers if exist, otherwise 627 * according to outer headers. 628 */ 629 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 630 } else { 631 pr_debug("RSS Hash for inner headers isn't supported\n"); 632 return (-EOPNOTSUPP); 633 } 634 } 635 636 return 0; 637 } 638 639 static int create_qp_rss(struct mlx4_ib_dev *dev, 640 struct ib_qp_init_attr *init_attr, 641 struct mlx4_ib_create_qp_rss *ucmd, 642 struct mlx4_ib_qp *qp) 643 { 644 int qpn; 645 int err; 646 647 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 648 649 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 650 if (err) 651 return err; 652 653 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 654 if (err) 655 goto err_qpn; 656 657 mutex_init(&qp->mutex); 658 659 INIT_LIST_HEAD(&qp->gid_list); 660 INIT_LIST_HEAD(&qp->steering_rules); 661 662 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 663 qp->state = IB_QPS_RESET; 664 665 /* Set dummy send resources to be compatible with HV and PRM */ 666 qp->sq_no_prefetch = 1; 667 qp->sq.wqe_cnt = 1; 668 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 669 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 670 qp->mtt = (to_mqp( 671 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 672 673 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL); 674 if (!qp->rss_ctx) { 675 err = -ENOMEM; 676 goto err_qp_alloc; 677 } 678 679 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 680 if (err) 681 goto err; 682 683 return 0; 684 685 err: 686 kfree(qp->rss_ctx); 687 688 err_qp_alloc: 689 mlx4_qp_remove(dev->dev, &qp->mqp); 690 mlx4_qp_free(dev->dev, &qp->mqp); 691 692 err_qpn: 693 mlx4_qp_release_range(dev->dev, qpn, 1); 694 return err; 695 } 696 697 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd, 698 struct ib_qp_init_attr *init_attr, 699 struct ib_udata *udata) 700 { 701 struct mlx4_ib_qp *qp; 702 struct mlx4_ib_create_qp_rss ucmd = {}; 703 size_t required_cmd_sz; 704 int err; 705 706 if (!udata) { 707 pr_debug("RSS QP with NULL udata\n"); 708 return ERR_PTR(-EINVAL); 709 } 710 711 if (udata->outlen) 712 return ERR_PTR(-EOPNOTSUPP); 713 714 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 715 sizeof(ucmd.reserved1); 716 if (udata->inlen < required_cmd_sz) { 717 pr_debug("invalid inlen\n"); 718 return ERR_PTR(-EINVAL); 719 } 720 721 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 722 pr_debug("copy failed\n"); 723 return ERR_PTR(-EFAULT); 724 } 725 726 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 727 return ERR_PTR(-EOPNOTSUPP); 728 729 if (ucmd.comp_mask || ucmd.reserved1) 730 return ERR_PTR(-EOPNOTSUPP); 731 732 if (udata->inlen > sizeof(ucmd) && 733 !ib_is_udata_cleared(udata, sizeof(ucmd), 734 udata->inlen - sizeof(ucmd))) { 735 pr_debug("inlen is not supported\n"); 736 return ERR_PTR(-EOPNOTSUPP); 737 } 738 739 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 740 pr_debug("RSS QP with unsupported QP type %d\n", 741 init_attr->qp_type); 742 return ERR_PTR(-EOPNOTSUPP); 743 } 744 745 if (init_attr->create_flags) { 746 pr_debug("RSS QP doesn't support create flags\n"); 747 return ERR_PTR(-EOPNOTSUPP); 748 } 749 750 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 751 pr_debug("RSS QP with unsupported send attributes\n"); 752 return ERR_PTR(-EOPNOTSUPP); 753 } 754 755 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 756 if (!qp) 757 return ERR_PTR(-ENOMEM); 758 759 qp->pri.vid = 0xFFFF; 760 qp->alt.vid = 0xFFFF; 761 762 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 763 if (err) { 764 kfree(qp); 765 return ERR_PTR(err); 766 } 767 768 qp->ibqp.qp_num = qp->mqp.qpn; 769 770 return &qp->ibqp; 771 } 772 773 /* 774 * This function allocates a WQN from a range which is consecutive and aligned 775 * to its size. In case the range is full, then it creates a new range and 776 * allocates WQN from it. The new range will be used for following allocations. 777 */ 778 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 779 struct mlx4_ib_qp *qp, int range_size, int *wqn) 780 { 781 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 782 struct mlx4_wqn_range *range; 783 int err = 0; 784 785 mutex_lock(&context->wqn_ranges_mutex); 786 787 range = list_first_entry_or_null(&context->wqn_ranges_list, 788 struct mlx4_wqn_range, list); 789 790 if (!range || (range->refcount == range->size) || range->dirty) { 791 range = kzalloc(sizeof(*range), GFP_KERNEL); 792 if (!range) { 793 err = -ENOMEM; 794 goto out; 795 } 796 797 err = mlx4_qp_reserve_range(dev->dev, range_size, 798 range_size, &range->base_wqn, 0, 799 qp->mqp.usage); 800 if (err) { 801 kfree(range); 802 goto out; 803 } 804 805 range->size = range_size; 806 list_add(&range->list, &context->wqn_ranges_list); 807 } else if (range_size != 1) { 808 /* 809 * Requesting a new range (>1) when last range is still open, is 810 * not valid. 811 */ 812 err = -EINVAL; 813 goto out; 814 } 815 816 qp->wqn_range = range; 817 818 *wqn = range->base_wqn + range->refcount; 819 820 range->refcount++; 821 822 out: 823 mutex_unlock(&context->wqn_ranges_mutex); 824 825 return err; 826 } 827 828 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 829 struct mlx4_ib_qp *qp, bool dirty_release) 830 { 831 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 832 struct mlx4_wqn_range *range; 833 834 mutex_lock(&context->wqn_ranges_mutex); 835 836 range = qp->wqn_range; 837 838 range->refcount--; 839 if (!range->refcount) { 840 mlx4_qp_release_range(dev->dev, range->base_wqn, 841 range->size); 842 list_del(&range->list); 843 kfree(range); 844 } else if (dirty_release) { 845 /* 846 * A range which one of its WQNs is destroyed, won't be able to be 847 * reused for further WQN allocations. 848 * The next created WQ will allocate a new range. 849 */ 850 range->dirty = 1; 851 } 852 853 mutex_unlock(&context->wqn_ranges_mutex); 854 } 855 856 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 857 enum mlx4_ib_source_type src, 858 struct ib_qp_init_attr *init_attr, 859 struct ib_udata *udata, int sqpn, 860 struct mlx4_ib_qp **caller_qp) 861 { 862 int qpn; 863 int err; 864 struct mlx4_ib_sqp *sqp = NULL; 865 struct mlx4_ib_qp *qp; 866 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 867 struct mlx4_ib_cq *mcq; 868 unsigned long flags; 869 int range_size = 0; 870 871 /* When tunneling special qps, we use a plain UD qp */ 872 if (sqpn) { 873 if (mlx4_is_mfunc(dev->dev) && 874 (!mlx4_is_master(dev->dev) || 875 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 876 if (init_attr->qp_type == IB_QPT_GSI) 877 qp_type = MLX4_IB_QPT_PROXY_GSI; 878 else { 879 if (mlx4_is_master(dev->dev) || 880 qp0_enabled_vf(dev->dev, sqpn)) 881 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 882 else 883 qp_type = MLX4_IB_QPT_PROXY_SMI; 884 } 885 } 886 qpn = sqpn; 887 /* add extra sg entry for tunneling */ 888 init_attr->cap.max_recv_sge++; 889 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 890 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 891 container_of(init_attr, 892 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 893 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 894 tnl_init->proxy_qp_type != IB_QPT_GSI) || 895 !mlx4_is_master(dev->dev)) 896 return -EINVAL; 897 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 898 qp_type = MLX4_IB_QPT_TUN_GSI; 899 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 900 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 901 tnl_init->port)) 902 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 903 else 904 qp_type = MLX4_IB_QPT_TUN_SMI; 905 /* we are definitely in the PPF here, since we are creating 906 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 907 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 908 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 909 sqpn = qpn; 910 } 911 912 if (!*caller_qp) { 913 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 914 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 915 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 916 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL); 917 if (!sqp) 918 return -ENOMEM; 919 qp = &sqp->qp; 920 qp->pri.vid = 0xFFFF; 921 qp->alt.vid = 0xFFFF; 922 } else { 923 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL); 924 if (!qp) 925 return -ENOMEM; 926 qp->pri.vid = 0xFFFF; 927 qp->alt.vid = 0xFFFF; 928 } 929 } else 930 qp = *caller_qp; 931 932 qp->mlx4_ib_qp_type = qp_type; 933 934 mutex_init(&qp->mutex); 935 spin_lock_init(&qp->sq.lock); 936 spin_lock_init(&qp->rq.lock); 937 INIT_LIST_HEAD(&qp->gid_list); 938 INIT_LIST_HEAD(&qp->steering_rules); 939 940 qp->state = IB_QPS_RESET; 941 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 942 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 943 944 945 if (udata) { 946 union { 947 struct mlx4_ib_create_qp qp; 948 struct mlx4_ib_create_wq wq; 949 } ucmd; 950 size_t copy_len; 951 int shift; 952 int n; 953 954 copy_len = (src == MLX4_IB_QP_SRC) ? 955 sizeof(struct mlx4_ib_create_qp) : 956 min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 957 958 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 959 err = -EFAULT; 960 goto err; 961 } 962 963 if (src == MLX4_IB_RWQ_SRC) { 964 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] || 965 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) { 966 pr_debug("user command isn't supported\n"); 967 err = -EOPNOTSUPP; 968 goto err; 969 } 970 971 if (ucmd.wq.log_range_size > 972 ilog2(dev->dev->caps.max_rss_tbl_sz)) { 973 pr_debug("WQN range size must be equal or smaller than %d\n", 974 dev->dev->caps.max_rss_tbl_sz); 975 err = -EOPNOTSUPP; 976 goto err; 977 } 978 range_size = 1 << ucmd.wq.log_range_size; 979 } else { 980 qp->inl_recv_sz = ucmd.qp.inl_recv_sz; 981 } 982 983 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 984 if (!(dev->dev->caps.flags & 985 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 986 pr_debug("scatter FCS is unsupported\n"); 987 err = -EOPNOTSUPP; 988 goto err; 989 } 990 991 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 992 } 993 994 err = set_rq_size(dev, &init_attr->cap, udata, 995 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 996 if (err) 997 goto err; 998 999 if (src == MLX4_IB_QP_SRC) { 1000 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch; 1001 1002 err = set_user_sq_size(dev, qp, 1003 (struct mlx4_ib_create_qp *) 1004 &ucmd); 1005 if (err) 1006 goto err; 1007 } else { 1008 qp->sq_no_prefetch = 1; 1009 qp->sq.wqe_cnt = 1; 1010 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 1011 /* Allocated buffer expects to have at least that SQ 1012 * size. 1013 */ 1014 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 1015 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 1016 } 1017 1018 qp->umem = ib_umem_get(pd->uobject->context, 1019 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr : 1020 ucmd.wq.buf_addr, qp->buf_size, 0, 0); 1021 if (IS_ERR(qp->umem)) { 1022 err = PTR_ERR(qp->umem); 1023 goto err; 1024 } 1025 1026 n = ib_umem_page_count(qp->umem); 1027 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1028 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1029 1030 if (err) 1031 goto err_buf; 1032 1033 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1034 if (err) 1035 goto err_mtt; 1036 1037 if (qp_has_rq(init_attr)) { 1038 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 1039 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr : 1040 ucmd.wq.db_addr, &qp->db); 1041 if (err) 1042 goto err_mtt; 1043 } 1044 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1045 } else { 1046 err = set_rq_size(dev, &init_attr->cap, udata, 1047 qp_has_rq(init_attr), qp, 0); 1048 if (err) 1049 goto err; 1050 1051 qp->sq_no_prefetch = 0; 1052 1053 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1054 qp->flags |= MLX4_IB_QP_LSO; 1055 1056 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1057 if (dev->steering_support == 1058 MLX4_STEERING_MODE_DEVICE_MANAGED) 1059 qp->flags |= MLX4_IB_QP_NETIF; 1060 else 1061 goto err; 1062 } 1063 1064 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1065 if (err) 1066 goto err; 1067 1068 if (qp_has_rq(init_attr)) { 1069 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1070 if (err) 1071 goto err; 1072 1073 *qp->db.db = 0; 1074 } 1075 1076 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1077 &qp->buf)) { 1078 err = -ENOMEM; 1079 goto err_db; 1080 } 1081 1082 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1083 &qp->mtt); 1084 if (err) 1085 goto err_buf; 1086 1087 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1088 if (err) 1089 goto err_mtt; 1090 1091 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1092 sizeof(u64), GFP_KERNEL); 1093 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1094 sizeof(u64), GFP_KERNEL); 1095 if (!qp->sq.wrid || !qp->rq.wrid) { 1096 err = -ENOMEM; 1097 goto err_wrid; 1098 } 1099 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1100 } 1101 1102 if (sqpn) { 1103 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1104 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1105 if (alloc_proxy_bufs(pd->device, qp)) { 1106 err = -ENOMEM; 1107 goto err_wrid; 1108 } 1109 } 1110 } else if (src == MLX4_IB_RWQ_SRC) { 1111 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp, 1112 range_size, &qpn); 1113 if (err) 1114 goto err_wrid; 1115 } else { 1116 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1117 * otherwise, the WQE BlueFlame setup flow wrongly causes 1118 * VLAN insertion. */ 1119 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1120 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1121 (init_attr->cap.max_send_wr ? 1122 MLX4_RESERVE_ETH_BF_QP : 0) | 1123 (init_attr->cap.max_recv_wr ? 1124 MLX4_RESERVE_A0_QP : 0), 1125 qp->mqp.usage); 1126 else 1127 if (qp->flags & MLX4_IB_QP_NETIF) 1128 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1129 else 1130 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1131 &qpn, 0, qp->mqp.usage); 1132 if (err) 1133 goto err_proxy; 1134 } 1135 1136 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1137 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1138 1139 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1140 if (err) 1141 goto err_qpn; 1142 1143 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1144 qp->mqp.qpn |= (1 << 23); 1145 1146 /* 1147 * Hardware wants QPN written in big-endian order (after 1148 * shifting) for send doorbell. Precompute this value to save 1149 * a little bit when posting sends. 1150 */ 1151 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1152 1153 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event : 1154 mlx4_ib_wq_event; 1155 1156 if (!*caller_qp) 1157 *caller_qp = qp; 1158 1159 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1160 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1161 to_mcq(init_attr->recv_cq)); 1162 /* Maintain device to QPs access, needed for further handling 1163 * via reset flow 1164 */ 1165 list_add_tail(&qp->qps_list, &dev->qp_list); 1166 /* Maintain CQ to QPs access, needed for further handling 1167 * via reset flow 1168 */ 1169 mcq = to_mcq(init_attr->send_cq); 1170 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1171 mcq = to_mcq(init_attr->recv_cq); 1172 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1173 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1174 to_mcq(init_attr->recv_cq)); 1175 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1176 return 0; 1177 1178 err_qpn: 1179 if (!sqpn) { 1180 if (qp->flags & MLX4_IB_QP_NETIF) 1181 mlx4_ib_steer_qp_free(dev, qpn, 1); 1182 else if (src == MLX4_IB_RWQ_SRC) 1183 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context), 1184 qp, 0); 1185 else 1186 mlx4_qp_release_range(dev->dev, qpn, 1); 1187 } 1188 err_proxy: 1189 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1190 free_proxy_bufs(pd->device, qp); 1191 err_wrid: 1192 if (udata) { 1193 if (qp_has_rq(init_attr)) 1194 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 1195 } else { 1196 kvfree(qp->sq.wrid); 1197 kvfree(qp->rq.wrid); 1198 } 1199 1200 err_mtt: 1201 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1202 1203 err_buf: 1204 if (qp->umem) 1205 ib_umem_release(qp->umem); 1206 else 1207 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1208 1209 err_db: 1210 if (!udata && qp_has_rq(init_attr)) 1211 mlx4_db_free(dev->dev, &qp->db); 1212 1213 err: 1214 if (!sqp && !*caller_qp) 1215 kfree(qp); 1216 kfree(sqp); 1217 1218 return err; 1219 } 1220 1221 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1222 { 1223 switch (state) { 1224 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1225 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1226 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1227 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1228 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1229 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1230 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1231 default: return -1; 1232 } 1233 } 1234 1235 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1236 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1237 { 1238 if (send_cq == recv_cq) { 1239 spin_lock(&send_cq->lock); 1240 __acquire(&recv_cq->lock); 1241 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1242 spin_lock(&send_cq->lock); 1243 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1244 } else { 1245 spin_lock(&recv_cq->lock); 1246 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1247 } 1248 } 1249 1250 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1251 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1252 { 1253 if (send_cq == recv_cq) { 1254 __release(&recv_cq->lock); 1255 spin_unlock(&send_cq->lock); 1256 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1257 spin_unlock(&recv_cq->lock); 1258 spin_unlock(&send_cq->lock); 1259 } else { 1260 spin_unlock(&send_cq->lock); 1261 spin_unlock(&recv_cq->lock); 1262 } 1263 } 1264 1265 static void del_gid_entries(struct mlx4_ib_qp *qp) 1266 { 1267 struct mlx4_ib_gid_entry *ge, *tmp; 1268 1269 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1270 list_del(&ge->list); 1271 kfree(ge); 1272 } 1273 } 1274 1275 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1276 { 1277 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1278 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1279 else 1280 return to_mpd(qp->ibqp.pd); 1281 } 1282 1283 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1284 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1285 { 1286 switch (qp->ibqp.qp_type) { 1287 case IB_QPT_XRC_TGT: 1288 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1289 *recv_cq = *send_cq; 1290 break; 1291 case IB_QPT_XRC_INI: 1292 *send_cq = to_mcq(qp->ibqp.send_cq); 1293 *recv_cq = *send_cq; 1294 break; 1295 default: 1296 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1297 to_mcq(qp->ibwq.cq); 1298 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1299 *recv_cq; 1300 break; 1301 } 1302 } 1303 1304 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1305 { 1306 if (qp->state != IB_QPS_RESET) { 1307 int i; 1308 1309 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1310 i++) { 1311 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1312 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1313 1314 mutex_lock(&wq->mutex); 1315 1316 wq->rss_usecnt--; 1317 1318 mutex_unlock(&wq->mutex); 1319 } 1320 1321 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1322 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1323 pr_warn("modify QP %06x to RESET failed.\n", 1324 qp->mqp.qpn); 1325 } 1326 1327 mlx4_qp_remove(dev->dev, &qp->mqp); 1328 mlx4_qp_free(dev->dev, &qp->mqp); 1329 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1330 del_gid_entries(qp); 1331 kfree(qp->rss_ctx); 1332 } 1333 1334 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1335 enum mlx4_ib_source_type src, bool is_user) 1336 { 1337 struct mlx4_ib_cq *send_cq, *recv_cq; 1338 unsigned long flags; 1339 1340 if (qp->state != IB_QPS_RESET) { 1341 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1342 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1343 pr_warn("modify QP %06x to RESET failed.\n", 1344 qp->mqp.qpn); 1345 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1346 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1347 qp->pri.smac = 0; 1348 qp->pri.smac_port = 0; 1349 } 1350 if (qp->alt.smac) { 1351 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1352 qp->alt.smac = 0; 1353 } 1354 if (qp->pri.vid < 0x1000) { 1355 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1356 qp->pri.vid = 0xFFFF; 1357 qp->pri.candidate_vid = 0xFFFF; 1358 qp->pri.update_vid = 0; 1359 } 1360 if (qp->alt.vid < 0x1000) { 1361 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1362 qp->alt.vid = 0xFFFF; 1363 qp->alt.candidate_vid = 0xFFFF; 1364 qp->alt.update_vid = 0; 1365 } 1366 } 1367 1368 get_cqs(qp, src, &send_cq, &recv_cq); 1369 1370 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1371 mlx4_ib_lock_cqs(send_cq, recv_cq); 1372 1373 /* del from lists under both locks above to protect reset flow paths */ 1374 list_del(&qp->qps_list); 1375 list_del(&qp->cq_send_list); 1376 list_del(&qp->cq_recv_list); 1377 if (!is_user) { 1378 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1379 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1380 if (send_cq != recv_cq) 1381 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1382 } 1383 1384 mlx4_qp_remove(dev->dev, &qp->mqp); 1385 1386 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1387 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1388 1389 mlx4_qp_free(dev->dev, &qp->mqp); 1390 1391 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1392 if (qp->flags & MLX4_IB_QP_NETIF) 1393 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1394 else if (src == MLX4_IB_RWQ_SRC) 1395 mlx4_ib_release_wqn(to_mucontext( 1396 qp->ibwq.uobject->context), qp, 1); 1397 else 1398 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1399 } 1400 1401 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1402 1403 if (is_user) { 1404 if (qp->rq.wqe_cnt) { 1405 struct mlx4_ib_ucontext *mcontext = !src ? 1406 to_mucontext(qp->ibqp.uobject->context) : 1407 to_mucontext(qp->ibwq.uobject->context); 1408 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1409 } 1410 ib_umem_release(qp->umem); 1411 } else { 1412 kvfree(qp->sq.wrid); 1413 kvfree(qp->rq.wrid); 1414 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1415 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1416 free_proxy_bufs(&dev->ib_dev, qp); 1417 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1418 if (qp->rq.wqe_cnt) 1419 mlx4_db_free(dev->dev, &qp->db); 1420 } 1421 1422 del_gid_entries(qp); 1423 } 1424 1425 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1426 { 1427 /* Native or PPF */ 1428 if (!mlx4_is_mfunc(dev->dev) || 1429 (mlx4_is_master(dev->dev) && 1430 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1431 return dev->dev->phys_caps.base_sqpn + 1432 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1433 attr->port_num - 1; 1434 } 1435 /* PF or VF -- creating proxies */ 1436 if (attr->qp_type == IB_QPT_SMI) 1437 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1438 else 1439 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1440 } 1441 1442 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1443 struct ib_qp_init_attr *init_attr, 1444 struct ib_udata *udata) 1445 { 1446 struct mlx4_ib_qp *qp = NULL; 1447 int err; 1448 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1449 u16 xrcdn = 0; 1450 1451 if (init_attr->rwq_ind_tbl) 1452 return _mlx4_ib_create_qp_rss(pd, init_attr, udata); 1453 1454 /* 1455 * We only support LSO, vendor flag1, and multicast loopback blocking, 1456 * and only for kernel UD QPs. 1457 */ 1458 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1459 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1460 MLX4_IB_SRIOV_TUNNEL_QP | 1461 MLX4_IB_SRIOV_SQP | 1462 MLX4_IB_QP_NETIF | 1463 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1464 return ERR_PTR(-EINVAL); 1465 1466 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1467 if (init_attr->qp_type != IB_QPT_UD) 1468 return ERR_PTR(-EINVAL); 1469 } 1470 1471 if (init_attr->create_flags) { 1472 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1473 return ERR_PTR(-EINVAL); 1474 1475 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1476 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1477 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1478 init_attr->qp_type != IB_QPT_UD) || 1479 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1480 init_attr->qp_type > IB_QPT_GSI) || 1481 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1482 init_attr->qp_type != IB_QPT_GSI)) 1483 return ERR_PTR(-EINVAL); 1484 } 1485 1486 switch (init_attr->qp_type) { 1487 case IB_QPT_XRC_TGT: 1488 pd = to_mxrcd(init_attr->xrcd)->pd; 1489 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1490 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1491 /* fall through */ 1492 case IB_QPT_XRC_INI: 1493 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1494 return ERR_PTR(-ENOSYS); 1495 init_attr->recv_cq = init_attr->send_cq; 1496 /* fall through */ 1497 case IB_QPT_RC: 1498 case IB_QPT_UC: 1499 case IB_QPT_RAW_PACKET: 1500 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1501 if (!qp) 1502 return ERR_PTR(-ENOMEM); 1503 qp->pri.vid = 0xFFFF; 1504 qp->alt.vid = 0xFFFF; 1505 /* fall through */ 1506 case IB_QPT_UD: 1507 { 1508 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1509 init_attr, udata, 0, &qp); 1510 if (err) { 1511 kfree(qp); 1512 return ERR_PTR(err); 1513 } 1514 1515 qp->ibqp.qp_num = qp->mqp.qpn; 1516 qp->xrcdn = xrcdn; 1517 1518 break; 1519 } 1520 case IB_QPT_SMI: 1521 case IB_QPT_GSI: 1522 { 1523 int sqpn; 1524 1525 /* Userspace is not allowed to create special QPs: */ 1526 if (udata) 1527 return ERR_PTR(-EINVAL); 1528 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1529 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1530 1, 1, &sqpn, 0, 1531 MLX4_RES_USAGE_DRIVER); 1532 1533 if (res) 1534 return ERR_PTR(res); 1535 } else { 1536 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1537 } 1538 1539 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC, 1540 init_attr, udata, sqpn, &qp); 1541 if (err) 1542 return ERR_PTR(err); 1543 1544 qp->port = init_attr->port_num; 1545 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1546 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1547 break; 1548 } 1549 default: 1550 /* Don't support raw QPs */ 1551 return ERR_PTR(-EINVAL); 1552 } 1553 1554 return &qp->ibqp; 1555 } 1556 1557 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1558 struct ib_qp_init_attr *init_attr, 1559 struct ib_udata *udata) { 1560 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1561 struct ib_qp *ibqp; 1562 struct mlx4_ib_dev *dev = to_mdev(device); 1563 1564 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1565 1566 if (!IS_ERR(ibqp) && 1567 (init_attr->qp_type == IB_QPT_GSI) && 1568 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1569 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1570 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1571 1572 if (is_eth && 1573 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1574 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1575 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1576 1577 if (IS_ERR(sqp->roce_v2_gsi)) { 1578 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1579 sqp->roce_v2_gsi = NULL; 1580 } else { 1581 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1582 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1583 } 1584 1585 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1586 } 1587 } 1588 return ibqp; 1589 } 1590 1591 static int _mlx4_ib_destroy_qp(struct ib_qp *qp) 1592 { 1593 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1594 struct mlx4_ib_qp *mqp = to_mqp(qp); 1595 1596 if (is_qp0(dev, mqp)) 1597 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1598 1599 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1600 dev->qp1_proxy[mqp->port - 1] == mqp) { 1601 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1602 dev->qp1_proxy[mqp->port - 1] = NULL; 1603 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1604 } 1605 1606 if (mqp->counter_index) 1607 mlx4_ib_free_qp_counter(dev, mqp); 1608 1609 if (qp->rwq_ind_tbl) { 1610 destroy_qp_rss(dev, mqp); 1611 } else { 1612 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, qp->uobject); 1613 } 1614 1615 if (is_sqp(dev, mqp)) 1616 kfree(to_msqp(mqp)); 1617 else 1618 kfree(mqp); 1619 1620 return 0; 1621 } 1622 1623 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1624 { 1625 struct mlx4_ib_qp *mqp = to_mqp(qp); 1626 1627 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1628 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1629 1630 if (sqp->roce_v2_gsi) 1631 ib_destroy_qp(sqp->roce_v2_gsi); 1632 } 1633 1634 return _mlx4_ib_destroy_qp(qp); 1635 } 1636 1637 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1638 { 1639 switch (type) { 1640 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1641 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1642 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1643 case MLX4_IB_QPT_XRC_INI: 1644 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1645 case MLX4_IB_QPT_SMI: 1646 case MLX4_IB_QPT_GSI: 1647 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1648 1649 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1650 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1651 MLX4_QP_ST_MLX : -1); 1652 case MLX4_IB_QPT_PROXY_SMI: 1653 case MLX4_IB_QPT_TUN_SMI: 1654 case MLX4_IB_QPT_PROXY_GSI: 1655 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1656 MLX4_QP_ST_UD : -1); 1657 default: return -1; 1658 } 1659 } 1660 1661 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1662 int attr_mask) 1663 { 1664 u8 dest_rd_atomic; 1665 u32 access_flags; 1666 u32 hw_access_flags = 0; 1667 1668 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1669 dest_rd_atomic = attr->max_dest_rd_atomic; 1670 else 1671 dest_rd_atomic = qp->resp_depth; 1672 1673 if (attr_mask & IB_QP_ACCESS_FLAGS) 1674 access_flags = attr->qp_access_flags; 1675 else 1676 access_flags = qp->atomic_rd_en; 1677 1678 if (!dest_rd_atomic) 1679 access_flags &= IB_ACCESS_REMOTE_WRITE; 1680 1681 if (access_flags & IB_ACCESS_REMOTE_READ) 1682 hw_access_flags |= MLX4_QP_BIT_RRE; 1683 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1684 hw_access_flags |= MLX4_QP_BIT_RAE; 1685 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1686 hw_access_flags |= MLX4_QP_BIT_RWE; 1687 1688 return cpu_to_be32(hw_access_flags); 1689 } 1690 1691 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1692 int attr_mask) 1693 { 1694 if (attr_mask & IB_QP_PKEY_INDEX) 1695 sqp->pkey_index = attr->pkey_index; 1696 if (attr_mask & IB_QP_QKEY) 1697 sqp->qkey = attr->qkey; 1698 if (attr_mask & IB_QP_SQ_PSN) 1699 sqp->send_psn = attr->sq_psn; 1700 } 1701 1702 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1703 { 1704 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1705 } 1706 1707 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1708 const struct rdma_ah_attr *ah, 1709 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1710 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1711 { 1712 int vidx; 1713 int smac_index; 1714 int err; 1715 1716 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1717 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1718 if (rdma_ah_get_static_rate(ah)) { 1719 path->static_rate = rdma_ah_get_static_rate(ah) + 1720 MLX4_STAT_RATE_OFFSET; 1721 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1722 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1723 --path->static_rate; 1724 } else 1725 path->static_rate = 0; 1726 1727 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1728 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1729 int real_sgid_index = 1730 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1731 1732 if (real_sgid_index < 0) 1733 return real_sgid_index; 1734 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1735 pr_err("sgid_index (%u) too large. max is %d\n", 1736 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1737 return -1; 1738 } 1739 1740 path->grh_mylmc |= 1 << 7; 1741 path->mgid_index = real_sgid_index; 1742 path->hop_limit = grh->hop_limit; 1743 path->tclass_flowlabel = 1744 cpu_to_be32((grh->traffic_class << 20) | 1745 (grh->flow_label)); 1746 memcpy(path->rgid, grh->dgid.raw, 16); 1747 } 1748 1749 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1750 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1751 return -1; 1752 1753 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1754 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1755 1756 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1757 if (vlan_tag < 0x1000) { 1758 if (smac_info->vid < 0x1000) { 1759 /* both valid vlan ids */ 1760 if (smac_info->vid != vlan_tag) { 1761 /* different VIDs. unreg old and reg new */ 1762 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1763 if (err) 1764 return err; 1765 smac_info->candidate_vid = vlan_tag; 1766 smac_info->candidate_vlan_index = vidx; 1767 smac_info->candidate_vlan_port = port; 1768 smac_info->update_vid = 1; 1769 path->vlan_index = vidx; 1770 } else { 1771 path->vlan_index = smac_info->vlan_index; 1772 } 1773 } else { 1774 /* no current vlan tag in qp */ 1775 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1776 if (err) 1777 return err; 1778 smac_info->candidate_vid = vlan_tag; 1779 smac_info->candidate_vlan_index = vidx; 1780 smac_info->candidate_vlan_port = port; 1781 smac_info->update_vid = 1; 1782 path->vlan_index = vidx; 1783 } 1784 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1785 path->fl = 1 << 6; 1786 } else { 1787 /* have current vlan tag. unregister it at modify-qp success */ 1788 if (smac_info->vid < 0x1000) { 1789 smac_info->candidate_vid = 0xFFFF; 1790 smac_info->update_vid = 1; 1791 } 1792 } 1793 1794 /* get smac_index for RoCE use. 1795 * If no smac was yet assigned, register one. 1796 * If one was already assigned, but the new mac differs, 1797 * unregister the old one and register the new one. 1798 */ 1799 if ((!smac_info->smac && !smac_info->smac_port) || 1800 smac_info->smac != smac) { 1801 /* register candidate now, unreg if needed, after success */ 1802 smac_index = mlx4_register_mac(dev->dev, port, smac); 1803 if (smac_index >= 0) { 1804 smac_info->candidate_smac_index = smac_index; 1805 smac_info->candidate_smac = smac; 1806 smac_info->candidate_smac_port = port; 1807 } else { 1808 return -EINVAL; 1809 } 1810 } else { 1811 smac_index = smac_info->smac_index; 1812 } 1813 memcpy(path->dmac, ah->roce.dmac, 6); 1814 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1815 /* put MAC table smac index for IBoE */ 1816 path->grh_mylmc = (u8) (smac_index) | 0x80; 1817 } else { 1818 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1819 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1826 enum ib_qp_attr_mask qp_attr_mask, 1827 struct mlx4_ib_qp *mqp, 1828 struct mlx4_qp_path *path, u8 port, 1829 u16 vlan_id, u8 *smac) 1830 { 1831 return _mlx4_set_path(dev, &qp->ah_attr, 1832 mlx4_mac_to_u64(smac), 1833 vlan_id, 1834 path, &mqp->pri, port); 1835 } 1836 1837 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1838 const struct ib_qp_attr *qp, 1839 enum ib_qp_attr_mask qp_attr_mask, 1840 struct mlx4_ib_qp *mqp, 1841 struct mlx4_qp_path *path, u8 port) 1842 { 1843 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1844 0, 1845 0xffff, 1846 path, &mqp->alt, port); 1847 } 1848 1849 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1850 { 1851 struct mlx4_ib_gid_entry *ge, *tmp; 1852 1853 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1854 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1855 ge->added = 1; 1856 ge->port = qp->port; 1857 } 1858 } 1859 } 1860 1861 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1862 struct mlx4_ib_qp *qp, 1863 struct mlx4_qp_context *context) 1864 { 1865 u64 u64_mac; 1866 int smac_index; 1867 1868 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1869 1870 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1871 if (!qp->pri.smac && !qp->pri.smac_port) { 1872 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1873 if (smac_index >= 0) { 1874 qp->pri.candidate_smac_index = smac_index; 1875 qp->pri.candidate_smac = u64_mac; 1876 qp->pri.candidate_smac_port = qp->port; 1877 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1878 } else { 1879 return -ENOENT; 1880 } 1881 } 1882 return 0; 1883 } 1884 1885 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1886 { 1887 struct counter_index *new_counter_index; 1888 int err; 1889 u32 tmp_idx; 1890 1891 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1892 IB_LINK_LAYER_ETHERNET || 1893 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1894 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1895 return 0; 1896 1897 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1898 if (err) 1899 return err; 1900 1901 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1902 if (!new_counter_index) { 1903 mlx4_counter_free(dev->dev, tmp_idx); 1904 return -ENOMEM; 1905 } 1906 1907 new_counter_index->index = tmp_idx; 1908 new_counter_index->allocated = 1; 1909 qp->counter_index = new_counter_index; 1910 1911 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1912 list_add_tail(&new_counter_index->list, 1913 &dev->counters_table[qp->port - 1].counters_list); 1914 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1915 1916 return 0; 1917 } 1918 1919 enum { 1920 MLX4_QPC_ROCE_MODE_1 = 0, 1921 MLX4_QPC_ROCE_MODE_2 = 2, 1922 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1923 }; 1924 1925 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1926 { 1927 switch (gid_type) { 1928 case IB_GID_TYPE_ROCE: 1929 return MLX4_QPC_ROCE_MODE_1; 1930 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1931 return MLX4_QPC_ROCE_MODE_2; 1932 default: 1933 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1934 } 1935 } 1936 1937 /* 1938 * Go over all RSS QP's childes (WQs) and apply their HW state according to 1939 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 1940 */ 1941 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num) 1942 { 1943 int err = 0; 1944 int i; 1945 1946 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 1947 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 1948 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1949 1950 mutex_lock(&wq->mutex); 1951 1952 /* Mlx4_ib restrictions: 1953 * WQ's is associated to a port according to the RSS QP it is 1954 * associates to. 1955 * In case the WQ is associated to a different port by another 1956 * RSS QP, return a failure. 1957 */ 1958 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 1959 err = -EINVAL; 1960 mutex_unlock(&wq->mutex); 1961 break; 1962 } 1963 wq->port = port_num; 1964 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 1965 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY); 1966 if (err) { 1967 mutex_unlock(&wq->mutex); 1968 break; 1969 } 1970 } 1971 wq->rss_usecnt++; 1972 1973 mutex_unlock(&wq->mutex); 1974 } 1975 1976 if (i && err) { 1977 int j; 1978 1979 for (j = (i - 1); j >= 0; j--) { 1980 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 1981 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1982 1983 mutex_lock(&wq->mutex); 1984 1985 if ((wq->rss_usecnt == 1) && 1986 (ibwq->state == IB_WQS_RDY)) 1987 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 1988 pr_warn("failed to reverse WQN=0x%06x\n", 1989 ibwq->wq_num); 1990 wq->rss_usecnt--; 1991 1992 mutex_unlock(&wq->mutex); 1993 } 1994 } 1995 1996 return err; 1997 } 1998 1999 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl) 2000 { 2001 int i; 2002 2003 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2004 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2005 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2006 2007 mutex_lock(&wq->mutex); 2008 2009 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2010 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET)) 2011 pr_warn("failed to reverse WQN=%x\n", 2012 ibwq->wq_num); 2013 wq->rss_usecnt--; 2014 2015 mutex_unlock(&wq->mutex); 2016 } 2017 } 2018 2019 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2020 struct mlx4_ib_qp *qp) 2021 { 2022 struct mlx4_rss_context *rss_context; 2023 2024 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2025 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2026 2027 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2028 rss_context->default_qpn = 2029 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2030 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2031 rss_context->base_qpn_udp = rss_context->default_qpn; 2032 rss_context->flags = qp->rss_ctx->flags; 2033 /* Currently support just toeplitz */ 2034 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2035 2036 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2037 MLX4_EN_RSS_KEY_SIZE); 2038 } 2039 2040 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2041 const struct ib_qp_attr *attr, int attr_mask, 2042 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2043 { 2044 struct ib_uobject *ibuobject; 2045 struct ib_srq *ibsrq; 2046 const struct ib_gid_attr *gid_attr = NULL; 2047 struct ib_rwq_ind_table *rwq_ind_tbl; 2048 enum ib_qp_type qp_type; 2049 struct mlx4_ib_dev *dev; 2050 struct mlx4_ib_qp *qp; 2051 struct mlx4_ib_pd *pd; 2052 struct mlx4_ib_cq *send_cq, *recv_cq; 2053 struct mlx4_qp_context *context; 2054 enum mlx4_qp_optpar optpar = 0; 2055 int sqd_event; 2056 int steer_qp = 0; 2057 int err = -EINVAL; 2058 int counter_index; 2059 2060 if (src_type == MLX4_IB_RWQ_SRC) { 2061 struct ib_wq *ibwq; 2062 2063 ibwq = (struct ib_wq *)src; 2064 ibuobject = ibwq->uobject; 2065 ibsrq = NULL; 2066 rwq_ind_tbl = NULL; 2067 qp_type = IB_QPT_RAW_PACKET; 2068 qp = to_mqp((struct ib_qp *)ibwq); 2069 dev = to_mdev(ibwq->device); 2070 pd = to_mpd(ibwq->pd); 2071 } else { 2072 struct ib_qp *ibqp; 2073 2074 ibqp = (struct ib_qp *)src; 2075 ibuobject = ibqp->uobject; 2076 ibsrq = ibqp->srq; 2077 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2078 qp_type = ibqp->qp_type; 2079 qp = to_mqp(ibqp); 2080 dev = to_mdev(ibqp->device); 2081 pd = get_pd(qp); 2082 } 2083 2084 /* APM is not supported under RoCE */ 2085 if (attr_mask & IB_QP_ALT_PATH && 2086 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2087 IB_LINK_LAYER_ETHERNET) 2088 return -ENOTSUPP; 2089 2090 context = kzalloc(sizeof *context, GFP_KERNEL); 2091 if (!context) 2092 return -ENOMEM; 2093 2094 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2095 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2096 2097 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2098 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2099 else { 2100 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2101 switch (attr->path_mig_state) { 2102 case IB_MIG_MIGRATED: 2103 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2104 break; 2105 case IB_MIG_REARM: 2106 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2107 break; 2108 case IB_MIG_ARMED: 2109 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2110 break; 2111 } 2112 } 2113 2114 if (qp->inl_recv_sz) 2115 context->param3 |= cpu_to_be32(1 << 25); 2116 2117 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2118 context->param3 |= cpu_to_be32(1 << 29); 2119 2120 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2121 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2122 else if (qp_type == IB_QPT_RAW_PACKET) 2123 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2124 else if (qp_type == IB_QPT_UD) { 2125 if (qp->flags & MLX4_IB_QP_LSO) 2126 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2127 ilog2(dev->dev->caps.max_gso_sz); 2128 else 2129 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2130 } else if (attr_mask & IB_QP_PATH_MTU) { 2131 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2132 pr_err("path MTU (%u) is invalid\n", 2133 attr->path_mtu); 2134 goto out; 2135 } 2136 context->mtu_msgmax = (attr->path_mtu << 5) | 2137 ilog2(dev->dev->caps.max_msg_sz); 2138 } 2139 2140 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2141 if (qp->rq.wqe_cnt) 2142 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2143 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2144 } 2145 2146 if (qp->sq.wqe_cnt) 2147 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2148 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2149 2150 if (new_state == IB_QPS_RESET && qp->counter_index) 2151 mlx4_ib_free_qp_counter(dev, qp); 2152 2153 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2154 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2155 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2156 if (qp_type == IB_QPT_RAW_PACKET) 2157 context->param3 |= cpu_to_be32(1 << 30); 2158 } 2159 2160 if (ibuobject) 2161 context->usr_page = cpu_to_be32( 2162 mlx4_to_hw_uar_index(dev->dev, 2163 to_mucontext(ibuobject->context) 2164 ->uar.index)); 2165 else 2166 context->usr_page = cpu_to_be32( 2167 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2168 2169 if (attr_mask & IB_QP_DEST_QPN) 2170 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2171 2172 if (attr_mask & IB_QP_PORT) { 2173 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2174 !(attr_mask & IB_QP_AV)) { 2175 mlx4_set_sched(&context->pri_path, attr->port_num); 2176 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2177 } 2178 } 2179 2180 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2181 err = create_qp_lb_counter(dev, qp); 2182 if (err) 2183 goto out; 2184 2185 counter_index = 2186 dev->counters_table[qp->port - 1].default_counter; 2187 if (qp->counter_index) 2188 counter_index = qp->counter_index->index; 2189 2190 if (counter_index != -1) { 2191 context->pri_path.counter_index = counter_index; 2192 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2193 if (qp->counter_index) { 2194 context->pri_path.fl |= 2195 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2196 context->pri_path.vlan_control |= 2197 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2198 } 2199 } else 2200 context->pri_path.counter_index = 2201 MLX4_SINK_COUNTER_INDEX(dev->dev); 2202 2203 if (qp->flags & MLX4_IB_QP_NETIF) { 2204 mlx4_ib_steer_qp_reg(dev, qp, 1); 2205 steer_qp = 1; 2206 } 2207 2208 if (qp_type == IB_QPT_GSI) { 2209 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2210 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2211 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2212 2213 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2214 } 2215 } 2216 2217 if (attr_mask & IB_QP_PKEY_INDEX) { 2218 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2219 context->pri_path.disable_pkey_check = 0x40; 2220 context->pri_path.pkey_index = attr->pkey_index; 2221 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2222 } 2223 2224 if (attr_mask & IB_QP_AV) { 2225 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2226 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2227 u16 vlan = 0xffff; 2228 u8 smac[ETH_ALEN]; 2229 int is_eth = 2230 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2231 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2232 2233 if (is_eth) { 2234 gid_attr = attr->ah_attr.grh.sgid_attr; 2235 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev); 2236 memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN); 2237 } 2238 2239 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2240 port_num, vlan, smac)) 2241 goto out; 2242 2243 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2244 MLX4_QP_OPTPAR_SCHED_QUEUE); 2245 2246 if (is_eth && 2247 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2248 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2249 2250 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2251 err = -EINVAL; 2252 goto out; 2253 } 2254 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2255 } 2256 2257 } 2258 2259 if (attr_mask & IB_QP_TIMEOUT) { 2260 context->pri_path.ackto |= attr->timeout << 3; 2261 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2262 } 2263 2264 if (attr_mask & IB_QP_ALT_PATH) { 2265 if (attr->alt_port_num == 0 || 2266 attr->alt_port_num > dev->dev->caps.num_ports) 2267 goto out; 2268 2269 if (attr->alt_pkey_index >= 2270 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2271 goto out; 2272 2273 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2274 &context->alt_path, 2275 attr->alt_port_num)) 2276 goto out; 2277 2278 context->alt_path.pkey_index = attr->alt_pkey_index; 2279 context->alt_path.ackto = attr->alt_timeout << 3; 2280 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2281 } 2282 2283 context->pd = cpu_to_be32(pd->pdn); 2284 2285 if (!rwq_ind_tbl) { 2286 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2287 get_cqs(qp, src_type, &send_cq, &recv_cq); 2288 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2289 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2290 recv_cq = send_cq; 2291 } 2292 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2293 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2294 2295 /* Set "fast registration enabled" for all kernel QPs */ 2296 if (!ibuobject) 2297 context->params1 |= cpu_to_be32(1 << 11); 2298 2299 if (attr_mask & IB_QP_RNR_RETRY) { 2300 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2301 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2302 } 2303 2304 if (attr_mask & IB_QP_RETRY_CNT) { 2305 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2306 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2307 } 2308 2309 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2310 if (attr->max_rd_atomic) 2311 context->params1 |= 2312 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2313 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2314 } 2315 2316 if (attr_mask & IB_QP_SQ_PSN) 2317 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2318 2319 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2320 if (attr->max_dest_rd_atomic) 2321 context->params2 |= 2322 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2323 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2324 } 2325 2326 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2327 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2328 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2329 } 2330 2331 if (ibsrq) 2332 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2333 2334 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2335 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2336 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2337 } 2338 if (attr_mask & IB_QP_RQ_PSN) 2339 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2340 2341 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2342 if (attr_mask & IB_QP_QKEY) { 2343 if (qp->mlx4_ib_qp_type & 2344 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2345 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2346 else { 2347 if (mlx4_is_mfunc(dev->dev) && 2348 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2349 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2350 MLX4_RESERVED_QKEY_BASE) { 2351 pr_err("Cannot use reserved QKEY" 2352 " 0x%x (range 0xffff0000..0xffffffff" 2353 " is reserved)\n", attr->qkey); 2354 err = -EINVAL; 2355 goto out; 2356 } 2357 context->qkey = cpu_to_be32(attr->qkey); 2358 } 2359 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2360 } 2361 2362 if (ibsrq) 2363 context->srqn = cpu_to_be32(1 << 24 | 2364 to_msrq(ibsrq)->msrq.srqn); 2365 2366 if (qp->rq.wqe_cnt && 2367 cur_state == IB_QPS_RESET && 2368 new_state == IB_QPS_INIT) 2369 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2370 2371 if (cur_state == IB_QPS_INIT && 2372 new_state == IB_QPS_RTR && 2373 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2374 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2375 context->pri_path.sched_queue = (qp->port - 1) << 6; 2376 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2377 qp->mlx4_ib_qp_type & 2378 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2379 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2380 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2381 context->pri_path.fl = 0x80; 2382 } else { 2383 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2384 context->pri_path.fl = 0x80; 2385 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2386 } 2387 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2388 IB_LINK_LAYER_ETHERNET) { 2389 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2390 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2391 context->pri_path.feup = 1 << 7; /* don't fsm */ 2392 /* handle smac_index */ 2393 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2394 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2395 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2396 err = handle_eth_ud_smac_index(dev, qp, context); 2397 if (err) { 2398 err = -EINVAL; 2399 goto out; 2400 } 2401 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2402 dev->qp1_proxy[qp->port - 1] = qp; 2403 } 2404 } 2405 } 2406 2407 if (qp_type == IB_QPT_RAW_PACKET) { 2408 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2409 MLX4_IB_LINK_TYPE_ETH; 2410 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2411 /* set QP to receive both tunneled & non-tunneled packets */ 2412 if (!rwq_ind_tbl) 2413 context->srqn = cpu_to_be32(7 << 28); 2414 } 2415 } 2416 2417 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2418 int is_eth = rdma_port_get_link_layer( 2419 &dev->ib_dev, qp->port) == 2420 IB_LINK_LAYER_ETHERNET; 2421 if (is_eth) { 2422 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2423 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2424 } 2425 } 2426 2427 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2428 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2429 sqd_event = 1; 2430 else 2431 sqd_event = 0; 2432 2433 if (!ibuobject && 2434 cur_state == IB_QPS_RESET && 2435 new_state == IB_QPS_INIT) 2436 context->rlkey_roce_mode |= (1 << 4); 2437 2438 /* 2439 * Before passing a kernel QP to the HW, make sure that the 2440 * ownership bits of the send queue are set and the SQ 2441 * headroom is stamped so that the hardware doesn't start 2442 * processing stale work requests. 2443 */ 2444 if (!ibuobject && 2445 cur_state == IB_QPS_RESET && 2446 new_state == IB_QPS_INIT) { 2447 struct mlx4_wqe_ctrl_seg *ctrl; 2448 int i; 2449 2450 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2451 ctrl = get_send_wqe(qp, i); 2452 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2453 ctrl->qpn_vlan.fence_size = 2454 1 << (qp->sq.wqe_shift - 4); 2455 stamp_send_wqe(qp, i); 2456 } 2457 } 2458 2459 if (rwq_ind_tbl && 2460 cur_state == IB_QPS_RESET && 2461 new_state == IB_QPS_INIT) { 2462 fill_qp_rss_context(context, qp); 2463 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2464 } 2465 2466 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2467 to_mlx4_state(new_state), context, optpar, 2468 sqd_event, &qp->mqp); 2469 if (err) 2470 goto out; 2471 2472 qp->state = new_state; 2473 2474 if (attr_mask & IB_QP_ACCESS_FLAGS) 2475 qp->atomic_rd_en = attr->qp_access_flags; 2476 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2477 qp->resp_depth = attr->max_dest_rd_atomic; 2478 if (attr_mask & IB_QP_PORT) { 2479 qp->port = attr->port_num; 2480 update_mcg_macs(dev, qp); 2481 } 2482 if (attr_mask & IB_QP_ALT_PATH) 2483 qp->alt_port = attr->alt_port_num; 2484 2485 if (is_sqp(dev, qp)) 2486 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2487 2488 /* 2489 * If we moved QP0 to RTR, bring the IB link up; if we moved 2490 * QP0 to RESET or ERROR, bring the link back down. 2491 */ 2492 if (is_qp0(dev, qp)) { 2493 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2494 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2495 pr_warn("INIT_PORT failed for port %d\n", 2496 qp->port); 2497 2498 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2499 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2500 mlx4_CLOSE_PORT(dev->dev, qp->port); 2501 } 2502 2503 /* 2504 * If we moved a kernel QP to RESET, clean up all old CQ 2505 * entries and reinitialize the QP. 2506 */ 2507 if (new_state == IB_QPS_RESET) { 2508 if (!ibuobject) { 2509 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2510 ibsrq ? to_msrq(ibsrq) : NULL); 2511 if (send_cq != recv_cq) 2512 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2513 2514 qp->rq.head = 0; 2515 qp->rq.tail = 0; 2516 qp->sq.head = 0; 2517 qp->sq.tail = 0; 2518 qp->sq_next_wqe = 0; 2519 if (qp->rq.wqe_cnt) 2520 *qp->db.db = 0; 2521 2522 if (qp->flags & MLX4_IB_QP_NETIF) 2523 mlx4_ib_steer_qp_reg(dev, qp, 0); 2524 } 2525 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2526 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2527 qp->pri.smac = 0; 2528 qp->pri.smac_port = 0; 2529 } 2530 if (qp->alt.smac) { 2531 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2532 qp->alt.smac = 0; 2533 } 2534 if (qp->pri.vid < 0x1000) { 2535 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2536 qp->pri.vid = 0xFFFF; 2537 qp->pri.candidate_vid = 0xFFFF; 2538 qp->pri.update_vid = 0; 2539 } 2540 2541 if (qp->alt.vid < 0x1000) { 2542 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2543 qp->alt.vid = 0xFFFF; 2544 qp->alt.candidate_vid = 0xFFFF; 2545 qp->alt.update_vid = 0; 2546 } 2547 } 2548 out: 2549 if (err && qp->counter_index) 2550 mlx4_ib_free_qp_counter(dev, qp); 2551 if (err && steer_qp) 2552 mlx4_ib_steer_qp_reg(dev, qp, 0); 2553 kfree(context); 2554 if (qp->pri.candidate_smac || 2555 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2556 if (err) { 2557 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2558 } else { 2559 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2560 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2561 qp->pri.smac = qp->pri.candidate_smac; 2562 qp->pri.smac_index = qp->pri.candidate_smac_index; 2563 qp->pri.smac_port = qp->pri.candidate_smac_port; 2564 } 2565 qp->pri.candidate_smac = 0; 2566 qp->pri.candidate_smac_index = 0; 2567 qp->pri.candidate_smac_port = 0; 2568 } 2569 if (qp->alt.candidate_smac) { 2570 if (err) { 2571 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2572 } else { 2573 if (qp->alt.smac) 2574 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2575 qp->alt.smac = qp->alt.candidate_smac; 2576 qp->alt.smac_index = qp->alt.candidate_smac_index; 2577 qp->alt.smac_port = qp->alt.candidate_smac_port; 2578 } 2579 qp->alt.candidate_smac = 0; 2580 qp->alt.candidate_smac_index = 0; 2581 qp->alt.candidate_smac_port = 0; 2582 } 2583 2584 if (qp->pri.update_vid) { 2585 if (err) { 2586 if (qp->pri.candidate_vid < 0x1000) 2587 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2588 qp->pri.candidate_vid); 2589 } else { 2590 if (qp->pri.vid < 0x1000) 2591 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2592 qp->pri.vid); 2593 qp->pri.vid = qp->pri.candidate_vid; 2594 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2595 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2596 } 2597 qp->pri.candidate_vid = 0xFFFF; 2598 qp->pri.update_vid = 0; 2599 } 2600 2601 if (qp->alt.update_vid) { 2602 if (err) { 2603 if (qp->alt.candidate_vid < 0x1000) 2604 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2605 qp->alt.candidate_vid); 2606 } else { 2607 if (qp->alt.vid < 0x1000) 2608 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2609 qp->alt.vid); 2610 qp->alt.vid = qp->alt.candidate_vid; 2611 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2612 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2613 } 2614 qp->alt.candidate_vid = 0xFFFF; 2615 qp->alt.update_vid = 0; 2616 } 2617 2618 return err; 2619 } 2620 2621 enum { 2622 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2623 IB_QP_PORT), 2624 }; 2625 2626 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2627 int attr_mask, struct ib_udata *udata) 2628 { 2629 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2630 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2631 enum ib_qp_state cur_state, new_state; 2632 int err = -EINVAL; 2633 mutex_lock(&qp->mutex); 2634 2635 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2636 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2637 2638 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2639 attr_mask)) { 2640 pr_debug("qpn 0x%x: invalid attribute mask specified " 2641 "for transition %d to %d. qp_type %d," 2642 " attr_mask 0x%x\n", 2643 ibqp->qp_num, cur_state, new_state, 2644 ibqp->qp_type, attr_mask); 2645 goto out; 2646 } 2647 2648 if (ibqp->rwq_ind_tbl) { 2649 if (!(((cur_state == IB_QPS_RESET) && 2650 (new_state == IB_QPS_INIT)) || 2651 ((cur_state == IB_QPS_INIT) && 2652 (new_state == IB_QPS_RTR)))) { 2653 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2654 ibqp->qp_num, cur_state, new_state); 2655 2656 err = -EOPNOTSUPP; 2657 goto out; 2658 } 2659 2660 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2661 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2662 ibqp->qp_num, attr_mask, cur_state, new_state); 2663 2664 err = -EOPNOTSUPP; 2665 goto out; 2666 } 2667 } 2668 2669 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2670 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2671 if ((ibqp->qp_type == IB_QPT_RC) || 2672 (ibqp->qp_type == IB_QPT_UD) || 2673 (ibqp->qp_type == IB_QPT_UC) || 2674 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2675 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2676 attr->port_num = mlx4_ib_bond_next_port(dev); 2677 } 2678 } else { 2679 /* no sense in changing port_num 2680 * when ports are bonded */ 2681 attr_mask &= ~IB_QP_PORT; 2682 } 2683 } 2684 2685 if ((attr_mask & IB_QP_PORT) && 2686 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2687 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2688 "for transition %d to %d. qp_type %d\n", 2689 ibqp->qp_num, attr->port_num, cur_state, 2690 new_state, ibqp->qp_type); 2691 goto out; 2692 } 2693 2694 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2695 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2696 IB_LINK_LAYER_ETHERNET)) 2697 goto out; 2698 2699 if (attr_mask & IB_QP_PKEY_INDEX) { 2700 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2701 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2702 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2703 "for transition %d to %d. qp_type %d\n", 2704 ibqp->qp_num, attr->pkey_index, cur_state, 2705 new_state, ibqp->qp_type); 2706 goto out; 2707 } 2708 } 2709 2710 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2711 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2712 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2713 "Transition %d to %d. qp_type %d\n", 2714 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2715 new_state, ibqp->qp_type); 2716 goto out; 2717 } 2718 2719 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2720 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2721 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2722 "Transition %d to %d. qp_type %d\n", 2723 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2724 new_state, ibqp->qp_type); 2725 goto out; 2726 } 2727 2728 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2729 err = 0; 2730 goto out; 2731 } 2732 2733 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2734 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num); 2735 if (err) 2736 goto out; 2737 } 2738 2739 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2740 cur_state, new_state); 2741 2742 if (ibqp->rwq_ind_tbl && err) 2743 bring_down_rss_rwqs(ibqp->rwq_ind_tbl); 2744 2745 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2746 attr->port_num = 1; 2747 2748 out: 2749 mutex_unlock(&qp->mutex); 2750 return err; 2751 } 2752 2753 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2754 int attr_mask, struct ib_udata *udata) 2755 { 2756 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2757 int ret; 2758 2759 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2760 2761 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2762 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2763 int err = 0; 2764 2765 if (sqp->roce_v2_gsi) 2766 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2767 if (err) 2768 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2769 err); 2770 } 2771 return ret; 2772 } 2773 2774 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2775 { 2776 int i; 2777 for (i = 0; i < dev->caps.num_ports; i++) { 2778 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2779 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2780 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2781 return 0; 2782 } 2783 } 2784 return -EINVAL; 2785 } 2786 2787 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2788 const struct ib_ud_wr *wr, 2789 void *wqe, unsigned *mlx_seg_len) 2790 { 2791 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2792 struct ib_device *ib_dev = &mdev->ib_dev; 2793 struct mlx4_wqe_mlx_seg *mlx = wqe; 2794 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2795 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2796 u16 pkey; 2797 u32 qkey; 2798 int send_size; 2799 int header_size; 2800 int spc; 2801 int i; 2802 2803 if (wr->wr.opcode != IB_WR_SEND) 2804 return -EINVAL; 2805 2806 send_size = 0; 2807 2808 for (i = 0; i < wr->wr.num_sge; ++i) 2809 send_size += wr->wr.sg_list[i].length; 2810 2811 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2812 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2813 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2814 send_size += sizeof (struct mlx4_ib_tunnel_header); 2815 2816 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2817 2818 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2819 sqp->ud_header.lrh.service_level = 2820 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2821 sqp->ud_header.lrh.destination_lid = 2822 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2823 sqp->ud_header.lrh.source_lid = 2824 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2825 } 2826 2827 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2828 2829 /* force loopback */ 2830 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2831 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2832 2833 sqp->ud_header.lrh.virtual_lane = 0; 2834 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2835 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2836 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2837 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2838 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2839 else 2840 sqp->ud_header.bth.destination_qpn = 2841 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel); 2842 2843 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2844 if (mlx4_is_master(mdev->dev)) { 2845 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2846 return -EINVAL; 2847 } else { 2848 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2849 return -EINVAL; 2850 } 2851 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2852 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2853 2854 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2855 sqp->ud_header.immediate_present = 0; 2856 2857 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2858 2859 /* 2860 * Inline data segments may not cross a 64 byte boundary. If 2861 * our UD header is bigger than the space available up to the 2862 * next 64 byte boundary in the WQE, use two inline data 2863 * segments to hold the UD header. 2864 */ 2865 spc = MLX4_INLINE_ALIGN - 2866 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2867 if (header_size <= spc) { 2868 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2869 memcpy(inl + 1, sqp->header_buf, header_size); 2870 i = 1; 2871 } else { 2872 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2873 memcpy(inl + 1, sqp->header_buf, spc); 2874 2875 inl = (void *) (inl + 1) + spc; 2876 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2877 /* 2878 * Need a barrier here to make sure all the data is 2879 * visible before the byte_count field is set. 2880 * Otherwise the HCA prefetcher could grab the 64-byte 2881 * chunk with this inline segment and get a valid (!= 2882 * 0xffffffff) byte count but stale data, and end up 2883 * generating a packet with bad headers. 2884 * 2885 * The first inline segment's byte_count field doesn't 2886 * need a barrier, because it comes after a 2887 * control/MLX segment and therefore is at an offset 2888 * of 16 mod 64. 2889 */ 2890 wmb(); 2891 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2892 i = 2; 2893 } 2894 2895 *mlx_seg_len = 2896 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2897 return 0; 2898 } 2899 2900 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2901 { 2902 union sl2vl_tbl_to_u64 tmp_vltab; 2903 u8 vl; 2904 2905 if (sl > 15) 2906 return 0xf; 2907 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2908 vl = tmp_vltab.sl8[sl >> 1]; 2909 if (sl & 1) 2910 vl &= 0x0f; 2911 else 2912 vl >>= 4; 2913 return vl; 2914 } 2915 2916 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2917 int index, union ib_gid *gid, 2918 enum ib_gid_type *gid_type) 2919 { 2920 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2921 struct mlx4_port_gid_table *port_gid_table; 2922 unsigned long flags; 2923 2924 port_gid_table = &iboe->gids[port_num - 1]; 2925 spin_lock_irqsave(&iboe->lock, flags); 2926 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 2927 *gid_type = port_gid_table->gids[index].gid_type; 2928 spin_unlock_irqrestore(&iboe->lock, flags); 2929 if (rdma_is_zero_gid(gid)) 2930 return -ENOENT; 2931 2932 return 0; 2933 } 2934 2935 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2936 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr, 2937 void *wqe, unsigned *mlx_seg_len) 2938 { 2939 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2940 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 2941 struct mlx4_wqe_mlx_seg *mlx = wqe; 2942 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2943 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2944 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2945 union ib_gid sgid; 2946 u16 pkey; 2947 int send_size; 2948 int header_size; 2949 int spc; 2950 int i; 2951 int err = 0; 2952 u16 vlan = 0xffff; 2953 bool is_eth; 2954 bool is_vlan = false; 2955 bool is_grh; 2956 bool is_udp = false; 2957 int ip_version = 0; 2958 2959 send_size = 0; 2960 for (i = 0; i < wr->wr.num_sge; ++i) 2961 send_size += wr->wr.sg_list[i].length; 2962 2963 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2964 is_grh = mlx4_ib_ah_grh_present(ah); 2965 if (is_eth) { 2966 enum ib_gid_type gid_type; 2967 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2968 /* When multi-function is enabled, the ib_core gid 2969 * indexes don't necessarily match the hw ones, so 2970 * we must use our own cache */ 2971 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2972 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2973 ah->av.ib.gid_index, &sgid.raw[0]); 2974 if (err) 2975 return err; 2976 } else { 2977 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 2978 ah->av.ib.gid_index, 2979 &sgid, &gid_type); 2980 if (!err) { 2981 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2982 if (is_udp) { 2983 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 2984 ip_version = 4; 2985 else 2986 ip_version = 6; 2987 is_grh = false; 2988 } 2989 } else { 2990 return err; 2991 } 2992 } 2993 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 2994 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 2995 is_vlan = 1; 2996 } 2997 } 2998 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 2999 ip_version, is_udp, 0, &sqp->ud_header); 3000 if (err) 3001 return err; 3002 3003 if (!is_eth) { 3004 sqp->ud_header.lrh.service_level = 3005 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3006 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3007 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3008 } 3009 3010 if (is_grh || (ip_version == 6)) { 3011 sqp->ud_header.grh.traffic_class = 3012 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3013 sqp->ud_header.grh.flow_label = 3014 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3015 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3016 if (is_eth) { 3017 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3018 } else { 3019 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3020 /* When multi-function is enabled, the ib_core gid 3021 * indexes don't necessarily match the hw ones, so 3022 * we must use our own cache 3023 */ 3024 sqp->ud_header.grh.source_gid.global.subnet_prefix = 3025 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 3026 demux[sqp->qp.port - 1]. 3027 subnet_prefix))); 3028 sqp->ud_header.grh.source_gid.global.interface_id = 3029 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 3030 guid_cache[ah->av.ib.gid_index]; 3031 } else { 3032 sqp->ud_header.grh.source_gid = 3033 ah->ibah.sgid_attr->gid; 3034 } 3035 } 3036 memcpy(sqp->ud_header.grh.destination_gid.raw, 3037 ah->av.ib.dgid, 16); 3038 } 3039 3040 if (ip_version == 4) { 3041 sqp->ud_header.ip4.tos = 3042 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3043 sqp->ud_header.ip4.id = 0; 3044 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3045 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3046 3047 memcpy(&sqp->ud_header.ip4.saddr, 3048 sgid.raw + 12, 4); 3049 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3050 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3051 } 3052 3053 if (is_udp) { 3054 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3055 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3056 sqp->ud_header.udp.csum = 0; 3057 } 3058 3059 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3060 3061 if (!is_eth) { 3062 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3063 (sqp->ud_header.lrh.destination_lid == 3064 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 3065 (sqp->ud_header.lrh.service_level << 8)); 3066 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3067 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3068 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3069 } 3070 3071 switch (wr->wr.opcode) { 3072 case IB_WR_SEND: 3073 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3074 sqp->ud_header.immediate_present = 0; 3075 break; 3076 case IB_WR_SEND_WITH_IMM: 3077 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3078 sqp->ud_header.immediate_present = 1; 3079 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3080 break; 3081 default: 3082 return -EINVAL; 3083 } 3084 3085 if (is_eth) { 3086 struct in6_addr in6; 3087 u16 ether_type; 3088 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3089 3090 ether_type = (!is_udp) ? ETH_P_IBOE: 3091 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3092 3093 mlx->sched_prio = cpu_to_be16(pcp); 3094 3095 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3096 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 3097 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3098 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3099 memcpy(&in6, sgid.raw, sizeof(in6)); 3100 3101 3102 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3103 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3104 if (!is_vlan) { 3105 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3106 } else { 3107 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3108 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3109 } 3110 } else { 3111 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 3112 sl_to_vl(to_mdev(ib_dev), 3113 sqp->ud_header.lrh.service_level, 3114 sqp->qp.port); 3115 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3116 return -EINVAL; 3117 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3118 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3119 } 3120 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3121 if (!sqp->qp.ibqp.qp_num) 3122 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 3123 else 3124 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 3125 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3126 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3127 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3128 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3129 sqp->qkey : wr->remote_qkey); 3130 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 3131 3132 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3133 3134 if (0) { 3135 pr_err("built UD header of size %d:\n", header_size); 3136 for (i = 0; i < header_size / 4; ++i) { 3137 if (i % 8 == 0) 3138 pr_err(" [%02x] ", i * 4); 3139 pr_cont(" %08x", 3140 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3141 if ((i + 1) % 8 == 0) 3142 pr_cont("\n"); 3143 } 3144 pr_err("\n"); 3145 } 3146 3147 /* 3148 * Inline data segments may not cross a 64 byte boundary. If 3149 * our UD header is bigger than the space available up to the 3150 * next 64 byte boundary in the WQE, use two inline data 3151 * segments to hold the UD header. 3152 */ 3153 spc = MLX4_INLINE_ALIGN - 3154 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3155 if (header_size <= spc) { 3156 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3157 memcpy(inl + 1, sqp->header_buf, header_size); 3158 i = 1; 3159 } else { 3160 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3161 memcpy(inl + 1, sqp->header_buf, spc); 3162 3163 inl = (void *) (inl + 1) + spc; 3164 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3165 /* 3166 * Need a barrier here to make sure all the data is 3167 * visible before the byte_count field is set. 3168 * Otherwise the HCA prefetcher could grab the 64-byte 3169 * chunk with this inline segment and get a valid (!= 3170 * 0xffffffff) byte count but stale data, and end up 3171 * generating a packet with bad headers. 3172 * 3173 * The first inline segment's byte_count field doesn't 3174 * need a barrier, because it comes after a 3175 * control/MLX segment and therefore is at an offset 3176 * of 16 mod 64. 3177 */ 3178 wmb(); 3179 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3180 i = 2; 3181 } 3182 3183 *mlx_seg_len = 3184 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3185 return 0; 3186 } 3187 3188 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3189 { 3190 unsigned cur; 3191 struct mlx4_ib_cq *cq; 3192 3193 cur = wq->head - wq->tail; 3194 if (likely(cur + nreq < wq->max_post)) 3195 return 0; 3196 3197 cq = to_mcq(ib_cq); 3198 spin_lock(&cq->lock); 3199 cur = wq->head - wq->tail; 3200 spin_unlock(&cq->lock); 3201 3202 return cur + nreq >= wq->max_post; 3203 } 3204 3205 static __be32 convert_access(int acc) 3206 { 3207 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3208 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3209 (acc & IB_ACCESS_REMOTE_WRITE ? 3210 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3211 (acc & IB_ACCESS_REMOTE_READ ? 3212 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3213 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3214 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3215 } 3216 3217 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3218 const struct ib_reg_wr *wr) 3219 { 3220 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3221 3222 fseg->flags = convert_access(wr->access); 3223 fseg->mem_key = cpu_to_be32(wr->key); 3224 fseg->buf_list = cpu_to_be64(mr->page_map); 3225 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3226 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3227 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3228 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3229 fseg->reserved[0] = 0; 3230 fseg->reserved[1] = 0; 3231 } 3232 3233 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3234 { 3235 memset(iseg, 0, sizeof(*iseg)); 3236 iseg->mem_key = cpu_to_be32(rkey); 3237 } 3238 3239 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3240 u64 remote_addr, u32 rkey) 3241 { 3242 rseg->raddr = cpu_to_be64(remote_addr); 3243 rseg->rkey = cpu_to_be32(rkey); 3244 rseg->reserved = 0; 3245 } 3246 3247 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3248 const struct ib_atomic_wr *wr) 3249 { 3250 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3251 aseg->swap_add = cpu_to_be64(wr->swap); 3252 aseg->compare = cpu_to_be64(wr->compare_add); 3253 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3254 aseg->swap_add = cpu_to_be64(wr->compare_add); 3255 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3256 } else { 3257 aseg->swap_add = cpu_to_be64(wr->compare_add); 3258 aseg->compare = 0; 3259 } 3260 3261 } 3262 3263 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3264 const struct ib_atomic_wr *wr) 3265 { 3266 aseg->swap_add = cpu_to_be64(wr->swap); 3267 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3268 aseg->compare = cpu_to_be64(wr->compare_add); 3269 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3270 } 3271 3272 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3273 const struct ib_ud_wr *wr) 3274 { 3275 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3276 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3277 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3278 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3279 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3280 } 3281 3282 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3283 struct mlx4_wqe_datagram_seg *dseg, 3284 const struct ib_ud_wr *wr, 3285 enum mlx4_ib_qp_type qpt) 3286 { 3287 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3288 struct mlx4_av sqp_av = {0}; 3289 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3290 3291 /* force loopback */ 3292 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3293 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3294 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3295 cpu_to_be32(0xf0000000); 3296 3297 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3298 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3299 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3300 else 3301 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3302 /* Use QKEY from the QP context, which is set by master */ 3303 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3304 } 3305 3306 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3307 unsigned *mlx_seg_len) 3308 { 3309 struct mlx4_wqe_inline_seg *inl = wqe; 3310 struct mlx4_ib_tunnel_header hdr; 3311 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3312 int spc; 3313 int i; 3314 3315 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3316 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3317 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3318 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3319 memcpy(hdr.mac, ah->av.eth.mac, 6); 3320 hdr.vlan = ah->av.eth.vlan; 3321 3322 spc = MLX4_INLINE_ALIGN - 3323 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3324 if (sizeof (hdr) <= spc) { 3325 memcpy(inl + 1, &hdr, sizeof (hdr)); 3326 wmb(); 3327 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3328 i = 1; 3329 } else { 3330 memcpy(inl + 1, &hdr, spc); 3331 wmb(); 3332 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3333 3334 inl = (void *) (inl + 1) + spc; 3335 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3336 wmb(); 3337 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3338 i = 2; 3339 } 3340 3341 *mlx_seg_len = 3342 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3343 } 3344 3345 static void set_mlx_icrc_seg(void *dseg) 3346 { 3347 u32 *t = dseg; 3348 struct mlx4_wqe_inline_seg *iseg = dseg; 3349 3350 t[1] = 0; 3351 3352 /* 3353 * Need a barrier here before writing the byte_count field to 3354 * make sure that all the data is visible before the 3355 * byte_count field is set. Otherwise, if the segment begins 3356 * a new cacheline, the HCA prefetcher could grab the 64-byte 3357 * chunk and get a valid (!= * 0xffffffff) byte count but 3358 * stale data, and end up sending the wrong data. 3359 */ 3360 wmb(); 3361 3362 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3363 } 3364 3365 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3366 { 3367 dseg->lkey = cpu_to_be32(sg->lkey); 3368 dseg->addr = cpu_to_be64(sg->addr); 3369 3370 /* 3371 * Need a barrier here before writing the byte_count field to 3372 * make sure that all the data is visible before the 3373 * byte_count field is set. Otherwise, if the segment begins 3374 * a new cacheline, the HCA prefetcher could grab the 64-byte 3375 * chunk and get a valid (!= * 0xffffffff) byte count but 3376 * stale data, and end up sending the wrong data. 3377 */ 3378 wmb(); 3379 3380 dseg->byte_count = cpu_to_be32(sg->length); 3381 } 3382 3383 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3384 { 3385 dseg->byte_count = cpu_to_be32(sg->length); 3386 dseg->lkey = cpu_to_be32(sg->lkey); 3387 dseg->addr = cpu_to_be64(sg->addr); 3388 } 3389 3390 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3391 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3392 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3393 { 3394 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3395 3396 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3397 *blh = cpu_to_be32(1 << 6); 3398 3399 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3400 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3401 return -EINVAL; 3402 3403 memcpy(wqe->header, wr->header, wr->hlen); 3404 3405 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3406 *lso_seg_len = halign; 3407 return 0; 3408 } 3409 3410 static __be32 send_ieth(const struct ib_send_wr *wr) 3411 { 3412 switch (wr->opcode) { 3413 case IB_WR_SEND_WITH_IMM: 3414 case IB_WR_RDMA_WRITE_WITH_IMM: 3415 return wr->ex.imm_data; 3416 3417 case IB_WR_SEND_WITH_INV: 3418 return cpu_to_be32(wr->ex.invalidate_rkey); 3419 3420 default: 3421 return 0; 3422 } 3423 } 3424 3425 static void add_zero_len_inline(void *wqe) 3426 { 3427 struct mlx4_wqe_inline_seg *inl = wqe; 3428 memset(wqe, 0, 16); 3429 inl->byte_count = cpu_to_be32(1 << 31); 3430 } 3431 3432 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3433 const struct ib_send_wr **bad_wr, bool drain) 3434 { 3435 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3436 void *wqe; 3437 struct mlx4_wqe_ctrl_seg *ctrl; 3438 struct mlx4_wqe_data_seg *dseg; 3439 unsigned long flags; 3440 int nreq; 3441 int err = 0; 3442 unsigned ind; 3443 int uninitialized_var(size); 3444 unsigned uninitialized_var(seglen); 3445 __be32 dummy; 3446 __be32 *lso_wqe; 3447 __be32 uninitialized_var(lso_hdr_sz); 3448 __be32 blh; 3449 int i; 3450 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3451 3452 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3453 struct mlx4_ib_sqp *sqp = to_msqp(qp); 3454 3455 if (sqp->roce_v2_gsi) { 3456 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3457 enum ib_gid_type gid_type; 3458 union ib_gid gid; 3459 3460 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 3461 ah->av.ib.gid_index, 3462 &gid, &gid_type)) 3463 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3464 to_mqp(sqp->roce_v2_gsi) : qp; 3465 else 3466 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3467 ah->av.ib.gid_index); 3468 } 3469 } 3470 3471 spin_lock_irqsave(&qp->sq.lock, flags); 3472 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3473 !drain) { 3474 err = -EIO; 3475 *bad_wr = wr; 3476 nreq = 0; 3477 goto out; 3478 } 3479 3480 ind = qp->sq_next_wqe; 3481 3482 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3483 lso_wqe = &dummy; 3484 blh = 0; 3485 3486 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3487 err = -ENOMEM; 3488 *bad_wr = wr; 3489 goto out; 3490 } 3491 3492 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3493 err = -EINVAL; 3494 *bad_wr = wr; 3495 goto out; 3496 } 3497 3498 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3499 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3500 3501 ctrl->srcrb_flags = 3502 (wr->send_flags & IB_SEND_SIGNALED ? 3503 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3504 (wr->send_flags & IB_SEND_SOLICITED ? 3505 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3506 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3507 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3508 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3509 qp->sq_signal_bits; 3510 3511 ctrl->imm = send_ieth(wr); 3512 3513 wqe += sizeof *ctrl; 3514 size = sizeof *ctrl / 16; 3515 3516 switch (qp->mlx4_ib_qp_type) { 3517 case MLX4_IB_QPT_RC: 3518 case MLX4_IB_QPT_UC: 3519 switch (wr->opcode) { 3520 case IB_WR_ATOMIC_CMP_AND_SWP: 3521 case IB_WR_ATOMIC_FETCH_AND_ADD: 3522 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3523 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3524 atomic_wr(wr)->rkey); 3525 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3526 3527 set_atomic_seg(wqe, atomic_wr(wr)); 3528 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3529 3530 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3531 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3532 3533 break; 3534 3535 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3536 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3537 atomic_wr(wr)->rkey); 3538 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3539 3540 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3541 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3542 3543 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3544 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3545 3546 break; 3547 3548 case IB_WR_RDMA_READ: 3549 case IB_WR_RDMA_WRITE: 3550 case IB_WR_RDMA_WRITE_WITH_IMM: 3551 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3552 rdma_wr(wr)->rkey); 3553 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3554 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3555 break; 3556 3557 case IB_WR_LOCAL_INV: 3558 ctrl->srcrb_flags |= 3559 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3560 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3561 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3562 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3563 break; 3564 3565 case IB_WR_REG_MR: 3566 ctrl->srcrb_flags |= 3567 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3568 set_reg_seg(wqe, reg_wr(wr)); 3569 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3570 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3571 break; 3572 3573 default: 3574 /* No extra segments required for sends */ 3575 break; 3576 } 3577 break; 3578 3579 case MLX4_IB_QPT_TUN_SMI_OWNER: 3580 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3581 ctrl, &seglen); 3582 if (unlikely(err)) { 3583 *bad_wr = wr; 3584 goto out; 3585 } 3586 wqe += seglen; 3587 size += seglen / 16; 3588 break; 3589 case MLX4_IB_QPT_TUN_SMI: 3590 case MLX4_IB_QPT_TUN_GSI: 3591 /* this is a UD qp used in MAD responses to slaves. */ 3592 set_datagram_seg(wqe, ud_wr(wr)); 3593 /* set the forced-loopback bit in the data seg av */ 3594 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3595 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3596 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3597 break; 3598 case MLX4_IB_QPT_UD: 3599 set_datagram_seg(wqe, ud_wr(wr)); 3600 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3601 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3602 3603 if (wr->opcode == IB_WR_LSO) { 3604 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3605 &lso_hdr_sz, &blh); 3606 if (unlikely(err)) { 3607 *bad_wr = wr; 3608 goto out; 3609 } 3610 lso_wqe = (__be32 *) wqe; 3611 wqe += seglen; 3612 size += seglen / 16; 3613 } 3614 break; 3615 3616 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3617 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3618 ctrl, &seglen); 3619 if (unlikely(err)) { 3620 *bad_wr = wr; 3621 goto out; 3622 } 3623 wqe += seglen; 3624 size += seglen / 16; 3625 /* to start tunnel header on a cache-line boundary */ 3626 add_zero_len_inline(wqe); 3627 wqe += 16; 3628 size++; 3629 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3630 wqe += seglen; 3631 size += seglen / 16; 3632 break; 3633 case MLX4_IB_QPT_PROXY_SMI: 3634 case MLX4_IB_QPT_PROXY_GSI: 3635 /* If we are tunneling special qps, this is a UD qp. 3636 * In this case we first add a UD segment targeting 3637 * the tunnel qp, and then add a header with address 3638 * information */ 3639 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3640 ud_wr(wr), 3641 qp->mlx4_ib_qp_type); 3642 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3643 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3644 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3645 wqe += seglen; 3646 size += seglen / 16; 3647 break; 3648 3649 case MLX4_IB_QPT_SMI: 3650 case MLX4_IB_QPT_GSI: 3651 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3652 &seglen); 3653 if (unlikely(err)) { 3654 *bad_wr = wr; 3655 goto out; 3656 } 3657 wqe += seglen; 3658 size += seglen / 16; 3659 break; 3660 3661 default: 3662 break; 3663 } 3664 3665 /* 3666 * Write data segments in reverse order, so as to 3667 * overwrite cacheline stamp last within each 3668 * cacheline. This avoids issues with WQE 3669 * prefetching. 3670 */ 3671 3672 dseg = wqe; 3673 dseg += wr->num_sge - 1; 3674 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3675 3676 /* Add one more inline data segment for ICRC for MLX sends */ 3677 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3678 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3679 qp->mlx4_ib_qp_type & 3680 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3681 set_mlx_icrc_seg(dseg + 1); 3682 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3683 } 3684 3685 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3686 set_data_seg(dseg, wr->sg_list + i); 3687 3688 /* 3689 * Possibly overwrite stamping in cacheline with LSO 3690 * segment only after making sure all data segments 3691 * are written. 3692 */ 3693 wmb(); 3694 *lso_wqe = lso_hdr_sz; 3695 3696 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3697 MLX4_WQE_CTRL_FENCE : 0) | size; 3698 3699 /* 3700 * Make sure descriptor is fully written before 3701 * setting ownership bit (because HW can start 3702 * executing as soon as we do). 3703 */ 3704 wmb(); 3705 3706 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3707 *bad_wr = wr; 3708 err = -EINVAL; 3709 goto out; 3710 } 3711 3712 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3713 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3714 3715 /* 3716 * We can improve latency by not stamping the last 3717 * send queue WQE until after ringing the doorbell, so 3718 * only stamp here if there are still more WQEs to post. 3719 */ 3720 if (wr->next) 3721 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3722 ind++; 3723 } 3724 3725 out: 3726 if (likely(nreq)) { 3727 qp->sq.head += nreq; 3728 3729 /* 3730 * Make sure that descriptors are written before 3731 * doorbell record. 3732 */ 3733 wmb(); 3734 3735 writel_relaxed(qp->doorbell_qpn, 3736 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3737 3738 /* 3739 * Make sure doorbells don't leak out of SQ spinlock 3740 * and reach the HCA out of order. 3741 */ 3742 mmiowb(); 3743 3744 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3745 3746 qp->sq_next_wqe = ind; 3747 } 3748 3749 spin_unlock_irqrestore(&qp->sq.lock, flags); 3750 3751 return err; 3752 } 3753 3754 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3755 const struct ib_send_wr **bad_wr) 3756 { 3757 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3758 } 3759 3760 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3761 const struct ib_recv_wr **bad_wr, bool drain) 3762 { 3763 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3764 struct mlx4_wqe_data_seg *scat; 3765 unsigned long flags; 3766 int err = 0; 3767 int nreq; 3768 int ind; 3769 int max_gs; 3770 int i; 3771 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3772 3773 max_gs = qp->rq.max_gs; 3774 spin_lock_irqsave(&qp->rq.lock, flags); 3775 3776 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3777 !drain) { 3778 err = -EIO; 3779 *bad_wr = wr; 3780 nreq = 0; 3781 goto out; 3782 } 3783 3784 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3785 3786 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3787 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3788 err = -ENOMEM; 3789 *bad_wr = wr; 3790 goto out; 3791 } 3792 3793 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3794 err = -EINVAL; 3795 *bad_wr = wr; 3796 goto out; 3797 } 3798 3799 scat = get_recv_wqe(qp, ind); 3800 3801 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3802 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3803 ib_dma_sync_single_for_device(ibqp->device, 3804 qp->sqp_proxy_rcv[ind].map, 3805 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3806 DMA_FROM_DEVICE); 3807 scat->byte_count = 3808 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3809 /* use dma lkey from upper layer entry */ 3810 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3811 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3812 scat++; 3813 max_gs--; 3814 } 3815 3816 for (i = 0; i < wr->num_sge; ++i) 3817 __set_data_seg(scat + i, wr->sg_list + i); 3818 3819 if (i < max_gs) { 3820 scat[i].byte_count = 0; 3821 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3822 scat[i].addr = 0; 3823 } 3824 3825 qp->rq.wrid[ind] = wr->wr_id; 3826 3827 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3828 } 3829 3830 out: 3831 if (likely(nreq)) { 3832 qp->rq.head += nreq; 3833 3834 /* 3835 * Make sure that descriptors are written before 3836 * doorbell record. 3837 */ 3838 wmb(); 3839 3840 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3841 } 3842 3843 spin_unlock_irqrestore(&qp->rq.lock, flags); 3844 3845 return err; 3846 } 3847 3848 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3849 const struct ib_recv_wr **bad_wr) 3850 { 3851 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3852 } 3853 3854 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3855 { 3856 switch (mlx4_state) { 3857 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3858 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3859 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3860 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3861 case MLX4_QP_STATE_SQ_DRAINING: 3862 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3863 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3864 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3865 default: return -1; 3866 } 3867 } 3868 3869 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3870 { 3871 switch (mlx4_mig_state) { 3872 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3873 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3874 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3875 default: return -1; 3876 } 3877 } 3878 3879 static int to_ib_qp_access_flags(int mlx4_flags) 3880 { 3881 int ib_flags = 0; 3882 3883 if (mlx4_flags & MLX4_QP_BIT_RRE) 3884 ib_flags |= IB_ACCESS_REMOTE_READ; 3885 if (mlx4_flags & MLX4_QP_BIT_RWE) 3886 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3887 if (mlx4_flags & MLX4_QP_BIT_RAE) 3888 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3889 3890 return ib_flags; 3891 } 3892 3893 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3894 struct rdma_ah_attr *ah_attr, 3895 struct mlx4_qp_path *path) 3896 { 3897 struct mlx4_dev *dev = ibdev->dev; 3898 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3899 3900 memset(ah_attr, 0, sizeof(*ah_attr)); 3901 if (port_num == 0 || port_num > dev->caps.num_ports) 3902 return; 3903 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3904 3905 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3906 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3907 ((path->sched_queue & 4) << 1)); 3908 else 3909 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3910 rdma_ah_set_port_num(ah_attr, port_num); 3911 3912 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3913 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3914 rdma_ah_set_static_rate(ah_attr, 3915 path->static_rate ? path->static_rate - 5 : 0); 3916 if (path->grh_mylmc & (1 << 7)) { 3917 rdma_ah_set_grh(ah_attr, NULL, 3918 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3919 path->mgid_index, 3920 path->hop_limit, 3921 (be32_to_cpu(path->tclass_flowlabel) 3922 >> 20) & 0xff); 3923 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 3924 } 3925 } 3926 3927 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3928 struct ib_qp_init_attr *qp_init_attr) 3929 { 3930 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3931 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3932 struct mlx4_qp_context context; 3933 int mlx4_state; 3934 int err = 0; 3935 3936 if (ibqp->rwq_ind_tbl) 3937 return -EOPNOTSUPP; 3938 3939 mutex_lock(&qp->mutex); 3940 3941 if (qp->state == IB_QPS_RESET) { 3942 qp_attr->qp_state = IB_QPS_RESET; 3943 goto done; 3944 } 3945 3946 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3947 if (err) { 3948 err = -EINVAL; 3949 goto out; 3950 } 3951 3952 mlx4_state = be32_to_cpu(context.flags) >> 28; 3953 3954 qp->state = to_ib_qp_state(mlx4_state); 3955 qp_attr->qp_state = qp->state; 3956 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3957 qp_attr->path_mig_state = 3958 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3959 qp_attr->qkey = be32_to_cpu(context.qkey); 3960 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3961 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3962 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3963 qp_attr->qp_access_flags = 3964 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3965 3966 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3967 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3968 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3969 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3970 qp_attr->alt_port_num = 3971 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 3972 } 3973 3974 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3975 if (qp_attr->qp_state == IB_QPS_INIT) 3976 qp_attr->port_num = qp->port; 3977 else 3978 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3979 3980 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3981 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3982 3983 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3984 3985 qp_attr->max_dest_rd_atomic = 3986 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3987 qp_attr->min_rnr_timer = 3988 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3989 qp_attr->timeout = context.pri_path.ackto >> 3; 3990 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3991 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3992 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3993 3994 done: 3995 qp_attr->cur_qp_state = qp_attr->qp_state; 3996 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3997 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3998 3999 if (!ibqp->uobject) { 4000 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4001 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4002 } else { 4003 qp_attr->cap.max_send_wr = 0; 4004 qp_attr->cap.max_send_sge = 0; 4005 } 4006 4007 /* 4008 * We don't support inline sends for kernel QPs (yet), and we 4009 * don't know what userspace's value should be. 4010 */ 4011 qp_attr->cap.max_inline_data = 0; 4012 4013 qp_init_attr->cap = qp_attr->cap; 4014 4015 qp_init_attr->create_flags = 0; 4016 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4017 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4018 4019 if (qp->flags & MLX4_IB_QP_LSO) 4020 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4021 4022 if (qp->flags & MLX4_IB_QP_NETIF) 4023 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4024 4025 qp_init_attr->sq_sig_type = 4026 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4027 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4028 4029 out: 4030 mutex_unlock(&qp->mutex); 4031 return err; 4032 } 4033 4034 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4035 struct ib_wq_init_attr *init_attr, 4036 struct ib_udata *udata) 4037 { 4038 struct mlx4_ib_dev *dev; 4039 struct ib_qp_init_attr ib_qp_init_attr; 4040 struct mlx4_ib_qp *qp; 4041 struct mlx4_ib_create_wq ucmd; 4042 int err, required_cmd_sz; 4043 4044 if (!udata) 4045 return ERR_PTR(-EINVAL); 4046 4047 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4048 sizeof(ucmd.comp_mask); 4049 if (udata->inlen < required_cmd_sz) { 4050 pr_debug("invalid inlen\n"); 4051 return ERR_PTR(-EINVAL); 4052 } 4053 4054 if (udata->inlen > sizeof(ucmd) && 4055 !ib_is_udata_cleared(udata, sizeof(ucmd), 4056 udata->inlen - sizeof(ucmd))) { 4057 pr_debug("inlen is not supported\n"); 4058 return ERR_PTR(-EOPNOTSUPP); 4059 } 4060 4061 if (udata->outlen) 4062 return ERR_PTR(-EOPNOTSUPP); 4063 4064 dev = to_mdev(pd->device); 4065 4066 if (init_attr->wq_type != IB_WQT_RQ) { 4067 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4068 return ERR_PTR(-EOPNOTSUPP); 4069 } 4070 4071 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) { 4072 pr_debug("unsupported create_flags %u\n", 4073 init_attr->create_flags); 4074 return ERR_PTR(-EOPNOTSUPP); 4075 } 4076 4077 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 4078 if (!qp) 4079 return ERR_PTR(-ENOMEM); 4080 4081 qp->pri.vid = 0xFFFF; 4082 qp->alt.vid = 0xFFFF; 4083 4084 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr)); 4085 ib_qp_init_attr.qp_context = init_attr->wq_context; 4086 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4087 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4088 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4089 ib_qp_init_attr.recv_cq = init_attr->cq; 4090 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4091 4092 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4093 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4094 4095 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr, 4096 udata, 0, &qp); 4097 if (err) { 4098 kfree(qp); 4099 return ERR_PTR(err); 4100 } 4101 4102 qp->ibwq.event_handler = init_attr->event_handler; 4103 qp->ibwq.wq_num = qp->mqp.qpn; 4104 qp->ibwq.state = IB_WQS_RESET; 4105 4106 return &qp->ibwq; 4107 } 4108 4109 static int ib_wq2qp_state(enum ib_wq_state state) 4110 { 4111 switch (state) { 4112 case IB_WQS_RESET: 4113 return IB_QPS_RESET; 4114 case IB_WQS_RDY: 4115 return IB_QPS_RTR; 4116 default: 4117 return IB_QPS_ERR; 4118 } 4119 } 4120 4121 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state) 4122 { 4123 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4124 enum ib_qp_state qp_cur_state; 4125 enum ib_qp_state qp_new_state; 4126 int attr_mask; 4127 int err; 4128 4129 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4130 * the WQ logic state. 4131 */ 4132 qp_cur_state = qp->state; 4133 qp_new_state = ib_wq2qp_state(new_state); 4134 4135 if (ib_wq2qp_state(new_state) == qp_cur_state) 4136 return 0; 4137 4138 if (new_state == IB_WQS_RDY) { 4139 struct ib_qp_attr attr = {}; 4140 4141 attr.port_num = qp->port; 4142 attr_mask = IB_QP_PORT; 4143 4144 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4145 attr_mask, IB_QPS_RESET, IB_QPS_INIT); 4146 if (err) { 4147 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4148 ibwq->wq_num); 4149 return err; 4150 } 4151 4152 qp_cur_state = IB_QPS_INIT; 4153 } 4154 4155 attr_mask = 0; 4156 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4157 qp_cur_state, qp_new_state); 4158 4159 if (err && (qp_cur_state == IB_QPS_INIT)) { 4160 qp_new_state = IB_QPS_RESET; 4161 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4162 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) { 4163 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4164 ibwq->wq_num); 4165 qp_new_state = IB_QPS_INIT; 4166 } 4167 } 4168 4169 qp->state = qp_new_state; 4170 4171 return err; 4172 } 4173 4174 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4175 u32 wq_attr_mask, struct ib_udata *udata) 4176 { 4177 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4178 struct mlx4_ib_modify_wq ucmd = {}; 4179 size_t required_cmd_sz; 4180 enum ib_wq_state cur_state, new_state; 4181 int err = 0; 4182 4183 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4184 sizeof(ucmd.reserved); 4185 if (udata->inlen < required_cmd_sz) 4186 return -EINVAL; 4187 4188 if (udata->inlen > sizeof(ucmd) && 4189 !ib_is_udata_cleared(udata, sizeof(ucmd), 4190 udata->inlen - sizeof(ucmd))) 4191 return -EOPNOTSUPP; 4192 4193 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4194 return -EFAULT; 4195 4196 if (ucmd.comp_mask || ucmd.reserved) 4197 return -EOPNOTSUPP; 4198 4199 if (wq_attr_mask & IB_WQ_FLAGS) 4200 return -EOPNOTSUPP; 4201 4202 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state : 4203 ibwq->state; 4204 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state; 4205 4206 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR || 4207 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR) 4208 return -EINVAL; 4209 4210 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4211 return -EINVAL; 4212 4213 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4214 return -EINVAL; 4215 4216 /* Need to protect against the parent RSS which also may modify WQ 4217 * state. 4218 */ 4219 mutex_lock(&qp->mutex); 4220 4221 /* Can update HW state only if a RSS QP has already associated to this 4222 * WQ, so we can apply its port on the WQ. 4223 */ 4224 if (qp->rss_usecnt) 4225 err = _mlx4_ib_modify_wq(ibwq, new_state); 4226 4227 if (!err) 4228 ibwq->state = new_state; 4229 4230 mutex_unlock(&qp->mutex); 4231 4232 return err; 4233 } 4234 4235 int mlx4_ib_destroy_wq(struct ib_wq *ibwq) 4236 { 4237 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4238 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4239 4240 if (qp->counter_index) 4241 mlx4_ib_free_qp_counter(dev, qp); 4242 4243 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1); 4244 4245 kfree(qp); 4246 4247 return 0; 4248 } 4249 4250 struct ib_rwq_ind_table 4251 *mlx4_ib_create_rwq_ind_table(struct ib_device *device, 4252 struct ib_rwq_ind_table_init_attr *init_attr, 4253 struct ib_udata *udata) 4254 { 4255 struct ib_rwq_ind_table *rwq_ind_table; 4256 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4257 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4258 unsigned int base_wqn; 4259 size_t min_resp_len; 4260 int i; 4261 int err; 4262 4263 if (udata->inlen > 0 && 4264 !ib_is_udata_cleared(udata, 0, 4265 udata->inlen)) 4266 return ERR_PTR(-EOPNOTSUPP); 4267 4268 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4269 if (udata->outlen && udata->outlen < min_resp_len) 4270 return ERR_PTR(-EINVAL); 4271 4272 if (ind_tbl_size > 4273 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4274 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4275 ind_tbl_size, 4276 device->attrs.rss_caps.max_rwq_indirection_table_size); 4277 return ERR_PTR(-EINVAL); 4278 } 4279 4280 base_wqn = init_attr->ind_tbl[0]->wq_num; 4281 4282 if (base_wqn % ind_tbl_size) { 4283 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4284 base_wqn); 4285 return ERR_PTR(-EINVAL); 4286 } 4287 4288 for (i = 1; i < ind_tbl_size; i++) { 4289 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4290 pr_debug("indirection table's WQNs aren't consecutive\n"); 4291 return ERR_PTR(-EINVAL); 4292 } 4293 } 4294 4295 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL); 4296 if (!rwq_ind_table) 4297 return ERR_PTR(-ENOMEM); 4298 4299 if (udata->outlen) { 4300 resp.response_length = offsetof(typeof(resp), response_length) + 4301 sizeof(resp.response_length); 4302 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4303 if (err) 4304 goto err; 4305 } 4306 4307 return rwq_ind_table; 4308 4309 err: 4310 kfree(rwq_ind_table); 4311 return ERR_PTR(err); 4312 } 4313 4314 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4315 { 4316 kfree(ib_rwq_ind_tbl); 4317 return 0; 4318 } 4319 4320 struct mlx4_ib_drain_cqe { 4321 struct ib_cqe cqe; 4322 struct completion done; 4323 }; 4324 4325 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4326 { 4327 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4328 struct mlx4_ib_drain_cqe, 4329 cqe); 4330 4331 complete(&cqe->done); 4332 } 4333 4334 /* This function returns only once the drained WR was completed */ 4335 static void handle_drain_completion(struct ib_cq *cq, 4336 struct mlx4_ib_drain_cqe *sdrain, 4337 struct mlx4_ib_dev *dev) 4338 { 4339 struct mlx4_dev *mdev = dev->dev; 4340 4341 if (cq->poll_ctx == IB_POLL_DIRECT) { 4342 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4343 ib_process_cq_direct(cq, -1); 4344 return; 4345 } 4346 4347 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4348 struct mlx4_ib_cq *mcq = to_mcq(cq); 4349 bool triggered = false; 4350 unsigned long flags; 4351 4352 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4353 /* Make sure that the CQ handler won't run if wasn't run yet */ 4354 if (!mcq->mcq.reset_notify_added) 4355 mcq->mcq.reset_notify_added = 1; 4356 else 4357 triggered = true; 4358 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4359 4360 if (triggered) { 4361 /* Wait for any scheduled/running task to be ended */ 4362 switch (cq->poll_ctx) { 4363 case IB_POLL_SOFTIRQ: 4364 irq_poll_disable(&cq->iop); 4365 irq_poll_enable(&cq->iop); 4366 break; 4367 case IB_POLL_WORKQUEUE: 4368 cancel_work_sync(&cq->work); 4369 break; 4370 default: 4371 WARN_ON_ONCE(1); 4372 } 4373 } 4374 4375 /* Run the CQ handler - this makes sure that the drain WR will 4376 * be processed if wasn't processed yet. 4377 */ 4378 mcq->mcq.comp(&mcq->mcq); 4379 } 4380 4381 wait_for_completion(&sdrain->done); 4382 } 4383 4384 void mlx4_ib_drain_sq(struct ib_qp *qp) 4385 { 4386 struct ib_cq *cq = qp->send_cq; 4387 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4388 struct mlx4_ib_drain_cqe sdrain; 4389 const struct ib_send_wr *bad_swr; 4390 struct ib_rdma_wr swr = { 4391 .wr = { 4392 .next = NULL, 4393 { .wr_cqe = &sdrain.cqe, }, 4394 .opcode = IB_WR_RDMA_WRITE, 4395 }, 4396 }; 4397 int ret; 4398 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4399 struct mlx4_dev *mdev = dev->dev; 4400 4401 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4402 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4403 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4404 return; 4405 } 4406 4407 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4408 init_completion(&sdrain.done); 4409 4410 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4411 if (ret) { 4412 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4413 return; 4414 } 4415 4416 handle_drain_completion(cq, &sdrain, dev); 4417 } 4418 4419 void mlx4_ib_drain_rq(struct ib_qp *qp) 4420 { 4421 struct ib_cq *cq = qp->recv_cq; 4422 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4423 struct mlx4_ib_drain_cqe rdrain; 4424 struct ib_recv_wr rwr = {}; 4425 const struct ib_recv_wr *bad_rwr; 4426 int ret; 4427 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4428 struct mlx4_dev *mdev = dev->dev; 4429 4430 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4431 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4432 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4433 return; 4434 } 4435 4436 rwr.wr_cqe = &rdrain.cqe; 4437 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4438 init_completion(&rdrain.done); 4439 4440 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4441 if (ret) { 4442 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4443 return; 4444 } 4445 4446 handle_drain_completion(cq, &rdrain, dev); 4447 } 4448