1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 #include <linux/vmalloc.h> 40 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_pack.h> 43 #include <rdma/ib_addr.h> 44 #include <rdma/ib_mad.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include "user.h" 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 57 enum { 58 MLX4_IB_ACK_REQ_FREQ = 8, 59 }; 60 61 enum { 62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 64 MLX4_IB_LINK_TYPE_IB = 0, 65 MLX4_IB_LINK_TYPE_ETH = 1 66 }; 67 68 enum { 69 /* 70 * Largest possible UD header: send with GRH and immediate 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 72 * tag. (LRH would only use 8 bytes, so Ethernet is the 73 * biggest case) 74 */ 75 MLX4_IB_UD_HEADER_SIZE = 82, 76 MLX4_IB_LSO_HEADER_SPARE = 128, 77 }; 78 79 enum { 80 MLX4_IB_IBOE_ETHERTYPE = 0x8915 81 }; 82 83 struct mlx4_ib_sqp { 84 struct mlx4_ib_qp qp; 85 int pkey_index; 86 u32 qkey; 87 u32 send_psn; 88 struct ib_ud_header ud_header; 89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 90 struct ib_qp *roce_v2_gsi; 91 }; 92 93 enum { 94 MLX4_IB_MIN_SQ_STRIDE = 6, 95 MLX4_IB_CACHE_LINE_SIZE = 64, 96 }; 97 98 enum { 99 MLX4_RAW_QP_MTU = 7, 100 MLX4_RAW_QP_MSGMAX = 31, 101 }; 102 103 #ifndef ETH_ALEN 104 #define ETH_ALEN 6 105 #endif 106 107 static const __be32 mlx4_ib_opcode[] = { 108 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 109 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 110 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 111 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 112 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 113 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 114 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 115 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 116 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 117 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 118 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 119 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 120 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 121 }; 122 123 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 124 { 125 return container_of(mqp, struct mlx4_ib_sqp, qp); 126 } 127 128 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 129 { 130 if (!mlx4_is_master(dev->dev)) 131 return 0; 132 133 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 134 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 135 8 * MLX4_MFUNC_MAX; 136 } 137 138 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 139 { 140 int proxy_sqp = 0; 141 int real_sqp = 0; 142 int i; 143 /* PPF or Native -- real SQP */ 144 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 145 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 146 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 147 if (real_sqp) 148 return 1; 149 /* VF or PF -- proxy SQP */ 150 if (mlx4_is_mfunc(dev->dev)) { 151 for (i = 0; i < dev->dev->caps.num_ports; i++) { 152 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] || 153 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) { 154 proxy_sqp = 1; 155 break; 156 } 157 } 158 } 159 if (proxy_sqp) 160 return 1; 161 162 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 163 } 164 165 /* used for INIT/CLOSE port logic */ 166 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 167 { 168 int proxy_qp0 = 0; 169 int real_qp0 = 0; 170 int i; 171 /* PPF or Native -- real QP0 */ 172 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 173 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 174 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 175 if (real_qp0) 176 return 1; 177 /* VF or PF -- proxy QP0 */ 178 if (mlx4_is_mfunc(dev->dev)) { 179 for (i = 0; i < dev->dev->caps.num_ports; i++) { 180 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) { 181 proxy_qp0 = 1; 182 break; 183 } 184 } 185 } 186 return proxy_qp0; 187 } 188 189 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 190 { 191 return mlx4_buf_offset(&qp->buf, offset); 192 } 193 194 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 195 { 196 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 197 } 198 199 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 200 { 201 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 202 } 203 204 /* 205 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 206 * first four bytes of every 64 byte chunk with 207 * 0x7FFFFFF | (invalid_ownership_value << 31). 208 * 209 * When the max work request size is less than or equal to the WQE 210 * basic block size, as an optimization, we can stamp all WQEs with 211 * 0xffffffff, and skip the very first chunk of each WQE. 212 */ 213 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 214 { 215 __be32 *wqe; 216 int i; 217 int s; 218 int ind; 219 void *buf; 220 __be32 stamp; 221 struct mlx4_wqe_ctrl_seg *ctrl; 222 223 if (qp->sq_max_wqes_per_wr > 1) { 224 s = roundup(size, 1U << qp->sq.wqe_shift); 225 for (i = 0; i < s; i += 64) { 226 ind = (i >> qp->sq.wqe_shift) + n; 227 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 228 cpu_to_be32(0xffffffff); 229 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 230 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 231 *wqe = stamp; 232 } 233 } else { 234 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 235 s = (ctrl->fence_size & 0x3f) << 4; 236 for (i = 64; i < s; i += 64) { 237 wqe = buf + i; 238 *wqe = cpu_to_be32(0xffffffff); 239 } 240 } 241 } 242 243 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 244 { 245 struct mlx4_wqe_ctrl_seg *ctrl; 246 struct mlx4_wqe_inline_seg *inl; 247 void *wqe; 248 int s; 249 250 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 251 s = sizeof(struct mlx4_wqe_ctrl_seg); 252 253 if (qp->ibqp.qp_type == IB_QPT_UD) { 254 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 255 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 256 memset(dgram, 0, sizeof *dgram); 257 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 258 s += sizeof(struct mlx4_wqe_datagram_seg); 259 } 260 261 /* Pad the remainder of the WQE with an inline data segment. */ 262 if (size > s) { 263 inl = wqe + s; 264 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 265 } 266 ctrl->srcrb_flags = 0; 267 ctrl->fence_size = size / 16; 268 /* 269 * Make sure descriptor is fully written before setting ownership bit 270 * (because HW can start executing as soon as we do). 271 */ 272 wmb(); 273 274 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 275 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 276 277 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 278 } 279 280 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 281 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 282 { 283 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 284 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 285 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 286 ind += s; 287 } 288 return ind; 289 } 290 291 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 292 { 293 struct ib_event event; 294 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 295 296 if (type == MLX4_EVENT_TYPE_PATH_MIG) 297 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 298 299 if (ibqp->event_handler) { 300 event.device = ibqp->device; 301 event.element.qp = ibqp; 302 switch (type) { 303 case MLX4_EVENT_TYPE_PATH_MIG: 304 event.event = IB_EVENT_PATH_MIG; 305 break; 306 case MLX4_EVENT_TYPE_COMM_EST: 307 event.event = IB_EVENT_COMM_EST; 308 break; 309 case MLX4_EVENT_TYPE_SQ_DRAINED: 310 event.event = IB_EVENT_SQ_DRAINED; 311 break; 312 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 313 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 314 break; 315 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 316 event.event = IB_EVENT_QP_FATAL; 317 break; 318 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 319 event.event = IB_EVENT_PATH_MIG_ERR; 320 break; 321 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 322 event.event = IB_EVENT_QP_REQ_ERR; 323 break; 324 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 325 event.event = IB_EVENT_QP_ACCESS_ERR; 326 break; 327 default: 328 pr_warn("Unexpected event type %d " 329 "on QP %06x\n", type, qp->qpn); 330 return; 331 } 332 333 ibqp->event_handler(&event, ibqp->qp_context); 334 } 335 } 336 337 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 338 { 339 /* 340 * UD WQEs must have a datagram segment. 341 * RC and UC WQEs might have a remote address segment. 342 * MLX WQEs need two extra inline data segments (for the UD 343 * header and space for the ICRC). 344 */ 345 switch (type) { 346 case MLX4_IB_QPT_UD: 347 return sizeof (struct mlx4_wqe_ctrl_seg) + 348 sizeof (struct mlx4_wqe_datagram_seg) + 349 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 350 case MLX4_IB_QPT_PROXY_SMI_OWNER: 351 case MLX4_IB_QPT_PROXY_SMI: 352 case MLX4_IB_QPT_PROXY_GSI: 353 return sizeof (struct mlx4_wqe_ctrl_seg) + 354 sizeof (struct mlx4_wqe_datagram_seg) + 64; 355 case MLX4_IB_QPT_TUN_SMI_OWNER: 356 case MLX4_IB_QPT_TUN_GSI: 357 return sizeof (struct mlx4_wqe_ctrl_seg) + 358 sizeof (struct mlx4_wqe_datagram_seg); 359 360 case MLX4_IB_QPT_UC: 361 return sizeof (struct mlx4_wqe_ctrl_seg) + 362 sizeof (struct mlx4_wqe_raddr_seg); 363 case MLX4_IB_QPT_RC: 364 return sizeof (struct mlx4_wqe_ctrl_seg) + 365 sizeof (struct mlx4_wqe_masked_atomic_seg) + 366 sizeof (struct mlx4_wqe_raddr_seg); 367 case MLX4_IB_QPT_SMI: 368 case MLX4_IB_QPT_GSI: 369 return sizeof (struct mlx4_wqe_ctrl_seg) + 370 ALIGN(MLX4_IB_UD_HEADER_SIZE + 371 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 372 MLX4_INLINE_ALIGN) * 373 sizeof (struct mlx4_wqe_inline_seg), 374 sizeof (struct mlx4_wqe_data_seg)) + 375 ALIGN(4 + 376 sizeof (struct mlx4_wqe_inline_seg), 377 sizeof (struct mlx4_wqe_data_seg)); 378 default: 379 return sizeof (struct mlx4_wqe_ctrl_seg); 380 } 381 } 382 383 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 384 int is_user, int has_rq, struct mlx4_ib_qp *qp) 385 { 386 /* Sanity check RQ size before proceeding */ 387 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 388 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 389 return -EINVAL; 390 391 if (!has_rq) { 392 if (cap->max_recv_wr) 393 return -EINVAL; 394 395 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 396 } else { 397 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 398 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 399 return -EINVAL; 400 401 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 402 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 403 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 404 } 405 406 /* leave userspace return values as they were, so as not to break ABI */ 407 if (is_user) { 408 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 409 cap->max_recv_sge = qp->rq.max_gs; 410 } else { 411 cap->max_recv_wr = qp->rq.max_post = 412 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 413 cap->max_recv_sge = min(qp->rq.max_gs, 414 min(dev->dev->caps.max_sq_sg, 415 dev->dev->caps.max_rq_sg)); 416 } 417 418 return 0; 419 } 420 421 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 422 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp, 423 bool shrink_wqe) 424 { 425 int s; 426 427 /* Sanity check SQ size before proceeding */ 428 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 429 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 430 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 431 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 432 return -EINVAL; 433 434 /* 435 * For MLX transport we need 2 extra S/G entries: 436 * one for the header and one for the checksum at the end 437 */ 438 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 439 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 440 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 441 return -EINVAL; 442 443 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 444 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 445 send_wqe_overhead(type, qp->flags); 446 447 if (s > dev->dev->caps.max_sq_desc_sz) 448 return -EINVAL; 449 450 /* 451 * Hermon supports shrinking WQEs, such that a single work 452 * request can include multiple units of 1 << wqe_shift. This 453 * way, work requests can differ in size, and do not have to 454 * be a power of 2 in size, saving memory and speeding up send 455 * WR posting. Unfortunately, if we do this then the 456 * wqe_index field in CQEs can't be used to look up the WR ID 457 * anymore, so we do this only if selective signaling is off. 458 * 459 * Further, on 32-bit platforms, we can't use vmap() to make 460 * the QP buffer virtually contiguous. Thus we have to use 461 * constant-sized WRs to make sure a WR is always fully within 462 * a single page-sized chunk. 463 * 464 * Finally, we use NOP work requests to pad the end of the 465 * work queue, to avoid wrap-around in the middle of WR. We 466 * set NEC bit to avoid getting completions with error for 467 * these NOP WRs, but since NEC is only supported starting 468 * with firmware 2.2.232, we use constant-sized WRs for older 469 * firmware. 470 * 471 * And, since MLX QPs only support SEND, we use constant-sized 472 * WRs in this case. 473 * 474 * We look for the smallest value of wqe_shift such that the 475 * resulting number of wqes does not exceed device 476 * capabilities. 477 * 478 * We set WQE size to at least 64 bytes, this way stamping 479 * invalidates each WQE. 480 */ 481 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 482 qp->sq_signal_bits && BITS_PER_LONG == 64 && 483 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 484 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 485 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 486 qp->sq.wqe_shift = ilog2(64); 487 else 488 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 489 490 for (;;) { 491 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 492 493 /* 494 * We need to leave 2 KB + 1 WR of headroom in the SQ to 495 * allow HW to prefetch. 496 */ 497 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 498 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 499 qp->sq_max_wqes_per_wr + 500 qp->sq_spare_wqes); 501 502 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 503 break; 504 505 if (qp->sq_max_wqes_per_wr <= 1) 506 return -EINVAL; 507 508 ++qp->sq.wqe_shift; 509 } 510 511 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 512 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 513 send_wqe_overhead(type, qp->flags)) / 514 sizeof (struct mlx4_wqe_data_seg); 515 516 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 517 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 518 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 519 qp->rq.offset = 0; 520 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 521 } else { 522 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 523 qp->sq.offset = 0; 524 } 525 526 cap->max_send_wr = qp->sq.max_post = 527 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 528 cap->max_send_sge = min(qp->sq.max_gs, 529 min(dev->dev->caps.max_sq_sg, 530 dev->dev->caps.max_rq_sg)); 531 /* We don't support inline sends for kernel QPs (yet) */ 532 cap->max_inline_data = 0; 533 534 return 0; 535 } 536 537 static int set_user_sq_size(struct mlx4_ib_dev *dev, 538 struct mlx4_ib_qp *qp, 539 struct mlx4_ib_create_qp *ucmd) 540 { 541 /* Sanity check SQ size before proceeding */ 542 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 543 ucmd->log_sq_stride > 544 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 545 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 546 return -EINVAL; 547 548 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 549 qp->sq.wqe_shift = ucmd->log_sq_stride; 550 551 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 552 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 553 554 return 0; 555 } 556 557 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 558 { 559 int i; 560 561 qp->sqp_proxy_rcv = 562 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 563 GFP_KERNEL); 564 if (!qp->sqp_proxy_rcv) 565 return -ENOMEM; 566 for (i = 0; i < qp->rq.wqe_cnt; i++) { 567 qp->sqp_proxy_rcv[i].addr = 568 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 569 GFP_KERNEL); 570 if (!qp->sqp_proxy_rcv[i].addr) 571 goto err; 572 qp->sqp_proxy_rcv[i].map = 573 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 574 sizeof (struct mlx4_ib_proxy_sqp_hdr), 575 DMA_FROM_DEVICE); 576 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 577 kfree(qp->sqp_proxy_rcv[i].addr); 578 goto err; 579 } 580 } 581 return 0; 582 583 err: 584 while (i > 0) { 585 --i; 586 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 587 sizeof (struct mlx4_ib_proxy_sqp_hdr), 588 DMA_FROM_DEVICE); 589 kfree(qp->sqp_proxy_rcv[i].addr); 590 } 591 kfree(qp->sqp_proxy_rcv); 592 qp->sqp_proxy_rcv = NULL; 593 return -ENOMEM; 594 } 595 596 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 597 { 598 int i; 599 600 for (i = 0; i < qp->rq.wqe_cnt; i++) { 601 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 602 sizeof (struct mlx4_ib_proxy_sqp_hdr), 603 DMA_FROM_DEVICE); 604 kfree(qp->sqp_proxy_rcv[i].addr); 605 } 606 kfree(qp->sqp_proxy_rcv); 607 } 608 609 static int qp_has_rq(struct ib_qp_init_attr *attr) 610 { 611 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 612 return 0; 613 614 return !attr->srq; 615 } 616 617 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 618 { 619 int i; 620 for (i = 0; i < dev->caps.num_ports; i++) { 621 if (qpn == dev->caps.qp0_proxy[i]) 622 return !!dev->caps.qp0_qkey[i]; 623 } 624 return 0; 625 } 626 627 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 628 struct mlx4_ib_qp *qp) 629 { 630 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 631 mlx4_counter_free(dev->dev, qp->counter_index->index); 632 list_del(&qp->counter_index->list); 633 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 634 635 kfree(qp->counter_index); 636 qp->counter_index = NULL; 637 } 638 639 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 640 struct ib_qp_init_attr *init_attr, 641 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp, 642 gfp_t gfp) 643 { 644 int qpn; 645 int err; 646 struct ib_qp_cap backup_cap; 647 struct mlx4_ib_sqp *sqp; 648 struct mlx4_ib_qp *qp; 649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 650 struct mlx4_ib_cq *mcq; 651 unsigned long flags; 652 653 /* When tunneling special qps, we use a plain UD qp */ 654 if (sqpn) { 655 if (mlx4_is_mfunc(dev->dev) && 656 (!mlx4_is_master(dev->dev) || 657 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 658 if (init_attr->qp_type == IB_QPT_GSI) 659 qp_type = MLX4_IB_QPT_PROXY_GSI; 660 else { 661 if (mlx4_is_master(dev->dev) || 662 qp0_enabled_vf(dev->dev, sqpn)) 663 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 664 else 665 qp_type = MLX4_IB_QPT_PROXY_SMI; 666 } 667 } 668 qpn = sqpn; 669 /* add extra sg entry for tunneling */ 670 init_attr->cap.max_recv_sge++; 671 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 672 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 673 container_of(init_attr, 674 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 675 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 676 tnl_init->proxy_qp_type != IB_QPT_GSI) || 677 !mlx4_is_master(dev->dev)) 678 return -EINVAL; 679 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 680 qp_type = MLX4_IB_QPT_TUN_GSI; 681 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 682 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 683 tnl_init->port)) 684 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 685 else 686 qp_type = MLX4_IB_QPT_TUN_SMI; 687 /* we are definitely in the PPF here, since we are creating 688 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 689 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 690 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 691 sqpn = qpn; 692 } 693 694 if (!*caller_qp) { 695 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 696 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 697 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 698 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp); 699 if (!sqp) 700 return -ENOMEM; 701 qp = &sqp->qp; 702 qp->pri.vid = 0xFFFF; 703 qp->alt.vid = 0xFFFF; 704 } else { 705 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp); 706 if (!qp) 707 return -ENOMEM; 708 qp->pri.vid = 0xFFFF; 709 qp->alt.vid = 0xFFFF; 710 } 711 } else 712 qp = *caller_qp; 713 714 qp->mlx4_ib_qp_type = qp_type; 715 716 mutex_init(&qp->mutex); 717 spin_lock_init(&qp->sq.lock); 718 spin_lock_init(&qp->rq.lock); 719 INIT_LIST_HEAD(&qp->gid_list); 720 INIT_LIST_HEAD(&qp->steering_rules); 721 722 qp->state = IB_QPS_RESET; 723 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 724 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 725 726 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp); 727 if (err) 728 goto err; 729 730 if (pd->uobject) { 731 struct mlx4_ib_create_qp ucmd; 732 733 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 734 err = -EFAULT; 735 goto err; 736 } 737 738 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 739 740 err = set_user_sq_size(dev, qp, &ucmd); 741 if (err) 742 goto err; 743 744 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 745 qp->buf_size, 0, 0); 746 if (IS_ERR(qp->umem)) { 747 err = PTR_ERR(qp->umem); 748 goto err; 749 } 750 751 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 752 ilog2(qp->umem->page_size), &qp->mtt); 753 if (err) 754 goto err_buf; 755 756 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 757 if (err) 758 goto err_mtt; 759 760 if (qp_has_rq(init_attr)) { 761 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 762 ucmd.db_addr, &qp->db); 763 if (err) 764 goto err_mtt; 765 } 766 } else { 767 qp->sq_no_prefetch = 0; 768 769 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 770 qp->flags |= MLX4_IB_QP_LSO; 771 772 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 773 if (dev->steering_support == 774 MLX4_STEERING_MODE_DEVICE_MANAGED) 775 qp->flags |= MLX4_IB_QP_NETIF; 776 else 777 goto err; 778 } 779 780 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap)); 781 err = set_kernel_sq_size(dev, &init_attr->cap, 782 qp_type, qp, true); 783 if (err) 784 goto err; 785 786 if (qp_has_rq(init_attr)) { 787 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp); 788 if (err) 789 goto err; 790 791 *qp->db.db = 0; 792 } 793 794 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size, 795 &qp->buf, gfp)) { 796 memcpy(&init_attr->cap, &backup_cap, 797 sizeof(backup_cap)); 798 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, 799 qp, false); 800 if (err) 801 goto err_db; 802 803 if (mlx4_buf_alloc(dev->dev, qp->buf_size, 804 PAGE_SIZE * 2, &qp->buf, gfp)) { 805 err = -ENOMEM; 806 goto err_db; 807 } 808 } 809 810 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 811 &qp->mtt); 812 if (err) 813 goto err_buf; 814 815 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp); 816 if (err) 817 goto err_mtt; 818 819 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64), 820 gfp | __GFP_NOWARN); 821 if (!qp->sq.wrid) 822 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64), 823 gfp, PAGE_KERNEL); 824 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64), 825 gfp | __GFP_NOWARN); 826 if (!qp->rq.wrid) 827 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64), 828 gfp, PAGE_KERNEL); 829 if (!qp->sq.wrid || !qp->rq.wrid) { 830 err = -ENOMEM; 831 goto err_wrid; 832 } 833 } 834 835 if (sqpn) { 836 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 837 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 838 if (alloc_proxy_bufs(pd->device, qp)) { 839 err = -ENOMEM; 840 goto err_wrid; 841 } 842 } 843 } else { 844 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 845 * otherwise, the WQE BlueFlame setup flow wrongly causes 846 * VLAN insertion. */ 847 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 848 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 849 (init_attr->cap.max_send_wr ? 850 MLX4_RESERVE_ETH_BF_QP : 0) | 851 (init_attr->cap.max_recv_wr ? 852 MLX4_RESERVE_A0_QP : 0)); 853 else 854 if (qp->flags & MLX4_IB_QP_NETIF) 855 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 856 else 857 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 858 &qpn, 0); 859 if (err) 860 goto err_proxy; 861 } 862 863 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 864 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 865 866 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp); 867 if (err) 868 goto err_qpn; 869 870 if (init_attr->qp_type == IB_QPT_XRC_TGT) 871 qp->mqp.qpn |= (1 << 23); 872 873 /* 874 * Hardware wants QPN written in big-endian order (after 875 * shifting) for send doorbell. Precompute this value to save 876 * a little bit when posting sends. 877 */ 878 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 879 880 qp->mqp.event = mlx4_ib_qp_event; 881 if (!*caller_qp) 882 *caller_qp = qp; 883 884 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 885 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 886 to_mcq(init_attr->recv_cq)); 887 /* Maintain device to QPs access, needed for further handling 888 * via reset flow 889 */ 890 list_add_tail(&qp->qps_list, &dev->qp_list); 891 /* Maintain CQ to QPs access, needed for further handling 892 * via reset flow 893 */ 894 mcq = to_mcq(init_attr->send_cq); 895 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 896 mcq = to_mcq(init_attr->recv_cq); 897 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 898 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 899 to_mcq(init_attr->recv_cq)); 900 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 901 return 0; 902 903 err_qpn: 904 if (!sqpn) { 905 if (qp->flags & MLX4_IB_QP_NETIF) 906 mlx4_ib_steer_qp_free(dev, qpn, 1); 907 else 908 mlx4_qp_release_range(dev->dev, qpn, 1); 909 } 910 err_proxy: 911 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 912 free_proxy_bufs(pd->device, qp); 913 err_wrid: 914 if (pd->uobject) { 915 if (qp_has_rq(init_attr)) 916 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 917 } else { 918 kvfree(qp->sq.wrid); 919 kvfree(qp->rq.wrid); 920 } 921 922 err_mtt: 923 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 924 925 err_buf: 926 if (pd->uobject) 927 ib_umem_release(qp->umem); 928 else 929 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 930 931 err_db: 932 if (!pd->uobject && qp_has_rq(init_attr)) 933 mlx4_db_free(dev->dev, &qp->db); 934 935 err: 936 if (!*caller_qp) 937 kfree(qp); 938 return err; 939 } 940 941 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 942 { 943 switch (state) { 944 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 945 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 946 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 947 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 948 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 949 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 950 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 951 default: return -1; 952 } 953 } 954 955 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 956 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 957 { 958 if (send_cq == recv_cq) { 959 spin_lock(&send_cq->lock); 960 __acquire(&recv_cq->lock); 961 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 962 spin_lock(&send_cq->lock); 963 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 964 } else { 965 spin_lock(&recv_cq->lock); 966 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 967 } 968 } 969 970 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 971 __releases(&send_cq->lock) __releases(&recv_cq->lock) 972 { 973 if (send_cq == recv_cq) { 974 __release(&recv_cq->lock); 975 spin_unlock(&send_cq->lock); 976 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 977 spin_unlock(&recv_cq->lock); 978 spin_unlock(&send_cq->lock); 979 } else { 980 spin_unlock(&send_cq->lock); 981 spin_unlock(&recv_cq->lock); 982 } 983 } 984 985 static void del_gid_entries(struct mlx4_ib_qp *qp) 986 { 987 struct mlx4_ib_gid_entry *ge, *tmp; 988 989 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 990 list_del(&ge->list); 991 kfree(ge); 992 } 993 } 994 995 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 996 { 997 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 998 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 999 else 1000 return to_mpd(qp->ibqp.pd); 1001 } 1002 1003 static void get_cqs(struct mlx4_ib_qp *qp, 1004 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1005 { 1006 switch (qp->ibqp.qp_type) { 1007 case IB_QPT_XRC_TGT: 1008 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1009 *recv_cq = *send_cq; 1010 break; 1011 case IB_QPT_XRC_INI: 1012 *send_cq = to_mcq(qp->ibqp.send_cq); 1013 *recv_cq = *send_cq; 1014 break; 1015 default: 1016 *send_cq = to_mcq(qp->ibqp.send_cq); 1017 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1018 break; 1019 } 1020 } 1021 1022 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1023 int is_user) 1024 { 1025 struct mlx4_ib_cq *send_cq, *recv_cq; 1026 unsigned long flags; 1027 1028 if (qp->state != IB_QPS_RESET) { 1029 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1030 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1031 pr_warn("modify QP %06x to RESET failed.\n", 1032 qp->mqp.qpn); 1033 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1034 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1035 qp->pri.smac = 0; 1036 qp->pri.smac_port = 0; 1037 } 1038 if (qp->alt.smac) { 1039 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1040 qp->alt.smac = 0; 1041 } 1042 if (qp->pri.vid < 0x1000) { 1043 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1044 qp->pri.vid = 0xFFFF; 1045 qp->pri.candidate_vid = 0xFFFF; 1046 qp->pri.update_vid = 0; 1047 } 1048 if (qp->alt.vid < 0x1000) { 1049 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1050 qp->alt.vid = 0xFFFF; 1051 qp->alt.candidate_vid = 0xFFFF; 1052 qp->alt.update_vid = 0; 1053 } 1054 } 1055 1056 get_cqs(qp, &send_cq, &recv_cq); 1057 1058 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1059 mlx4_ib_lock_cqs(send_cq, recv_cq); 1060 1061 /* del from lists under both locks above to protect reset flow paths */ 1062 list_del(&qp->qps_list); 1063 list_del(&qp->cq_send_list); 1064 list_del(&qp->cq_recv_list); 1065 if (!is_user) { 1066 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1067 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1068 if (send_cq != recv_cq) 1069 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1070 } 1071 1072 mlx4_qp_remove(dev->dev, &qp->mqp); 1073 1074 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1075 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1076 1077 mlx4_qp_free(dev->dev, &qp->mqp); 1078 1079 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1080 if (qp->flags & MLX4_IB_QP_NETIF) 1081 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1082 else 1083 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1084 } 1085 1086 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1087 1088 if (is_user) { 1089 if (qp->rq.wqe_cnt) 1090 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), 1091 &qp->db); 1092 ib_umem_release(qp->umem); 1093 } else { 1094 kvfree(qp->sq.wrid); 1095 kvfree(qp->rq.wrid); 1096 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1097 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1098 free_proxy_bufs(&dev->ib_dev, qp); 1099 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1100 if (qp->rq.wqe_cnt) 1101 mlx4_db_free(dev->dev, &qp->db); 1102 } 1103 1104 del_gid_entries(qp); 1105 } 1106 1107 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1108 { 1109 /* Native or PPF */ 1110 if (!mlx4_is_mfunc(dev->dev) || 1111 (mlx4_is_master(dev->dev) && 1112 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1113 return dev->dev->phys_caps.base_sqpn + 1114 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1115 attr->port_num - 1; 1116 } 1117 /* PF or VF -- creating proxies */ 1118 if (attr->qp_type == IB_QPT_SMI) 1119 return dev->dev->caps.qp0_proxy[attr->port_num - 1]; 1120 else 1121 return dev->dev->caps.qp1_proxy[attr->port_num - 1]; 1122 } 1123 1124 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1125 struct ib_qp_init_attr *init_attr, 1126 struct ib_udata *udata) 1127 { 1128 struct mlx4_ib_qp *qp = NULL; 1129 int err; 1130 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1131 u16 xrcdn = 0; 1132 gfp_t gfp; 1133 1134 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ? 1135 GFP_NOIO : GFP_KERNEL; 1136 /* 1137 * We only support LSO, vendor flag1, and multicast loopback blocking, 1138 * and only for kernel UD QPs. 1139 */ 1140 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1141 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1142 MLX4_IB_SRIOV_TUNNEL_QP | 1143 MLX4_IB_SRIOV_SQP | 1144 MLX4_IB_QP_NETIF | 1145 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1146 MLX4_IB_QP_CREATE_USE_GFP_NOIO)) 1147 return ERR_PTR(-EINVAL); 1148 1149 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1150 if (init_attr->qp_type != IB_QPT_UD) 1151 return ERR_PTR(-EINVAL); 1152 } 1153 1154 if (init_attr->create_flags) { 1155 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1156 return ERR_PTR(-EINVAL); 1157 1158 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1159 MLX4_IB_QP_CREATE_USE_GFP_NOIO | 1160 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1161 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1162 init_attr->qp_type != IB_QPT_UD) || 1163 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1164 init_attr->qp_type > IB_QPT_GSI) || 1165 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1166 init_attr->qp_type != IB_QPT_GSI)) 1167 return ERR_PTR(-EINVAL); 1168 } 1169 1170 switch (init_attr->qp_type) { 1171 case IB_QPT_XRC_TGT: 1172 pd = to_mxrcd(init_attr->xrcd)->pd; 1173 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1174 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1175 /* fall through */ 1176 case IB_QPT_XRC_INI: 1177 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1178 return ERR_PTR(-ENOSYS); 1179 init_attr->recv_cq = init_attr->send_cq; 1180 /* fall through */ 1181 case IB_QPT_RC: 1182 case IB_QPT_UC: 1183 case IB_QPT_RAW_PACKET: 1184 qp = kzalloc(sizeof *qp, gfp); 1185 if (!qp) 1186 return ERR_PTR(-ENOMEM); 1187 qp->pri.vid = 0xFFFF; 1188 qp->alt.vid = 0xFFFF; 1189 /* fall through */ 1190 case IB_QPT_UD: 1191 { 1192 err = create_qp_common(to_mdev(pd->device), pd, init_attr, 1193 udata, 0, &qp, gfp); 1194 if (err) { 1195 kfree(qp); 1196 return ERR_PTR(err); 1197 } 1198 1199 qp->ibqp.qp_num = qp->mqp.qpn; 1200 qp->xrcdn = xrcdn; 1201 1202 break; 1203 } 1204 case IB_QPT_SMI: 1205 case IB_QPT_GSI: 1206 { 1207 int sqpn; 1208 1209 /* Userspace is not allowed to create special QPs: */ 1210 if (udata) 1211 return ERR_PTR(-EINVAL); 1212 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1213 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0); 1214 1215 if (res) 1216 return ERR_PTR(res); 1217 } else { 1218 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1219 } 1220 1221 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata, 1222 sqpn, 1223 &qp, gfp); 1224 if (err) 1225 return ERR_PTR(err); 1226 1227 qp->port = init_attr->port_num; 1228 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1229 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1230 break; 1231 } 1232 default: 1233 /* Don't support raw QPs */ 1234 return ERR_PTR(-EINVAL); 1235 } 1236 1237 return &qp->ibqp; 1238 } 1239 1240 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1241 struct ib_qp_init_attr *init_attr, 1242 struct ib_udata *udata) { 1243 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1244 struct ib_qp *ibqp; 1245 struct mlx4_ib_dev *dev = to_mdev(device); 1246 1247 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1248 1249 if (!IS_ERR(ibqp) && 1250 (init_attr->qp_type == IB_QPT_GSI) && 1251 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1252 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1253 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1254 1255 if (is_eth && 1256 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1257 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1258 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1259 1260 if (IS_ERR(sqp->roce_v2_gsi)) { 1261 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1262 sqp->roce_v2_gsi = NULL; 1263 } else { 1264 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1265 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1266 } 1267 1268 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1269 } 1270 } 1271 return ibqp; 1272 } 1273 1274 static int _mlx4_ib_destroy_qp(struct ib_qp *qp) 1275 { 1276 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1277 struct mlx4_ib_qp *mqp = to_mqp(qp); 1278 struct mlx4_ib_pd *pd; 1279 1280 if (is_qp0(dev, mqp)) 1281 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1282 1283 if (dev->qp1_proxy[mqp->port - 1] == mqp) { 1284 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1285 dev->qp1_proxy[mqp->port - 1] = NULL; 1286 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1287 } 1288 1289 if (mqp->counter_index) 1290 mlx4_ib_free_qp_counter(dev, mqp); 1291 1292 pd = get_pd(mqp); 1293 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject); 1294 1295 if (is_sqp(dev, mqp)) 1296 kfree(to_msqp(mqp)); 1297 else 1298 kfree(mqp); 1299 1300 return 0; 1301 } 1302 1303 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1304 { 1305 struct mlx4_ib_qp *mqp = to_mqp(qp); 1306 1307 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1308 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1309 1310 if (sqp->roce_v2_gsi) 1311 ib_destroy_qp(sqp->roce_v2_gsi); 1312 } 1313 1314 return _mlx4_ib_destroy_qp(qp); 1315 } 1316 1317 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1318 { 1319 switch (type) { 1320 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1321 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1322 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1323 case MLX4_IB_QPT_XRC_INI: 1324 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1325 case MLX4_IB_QPT_SMI: 1326 case MLX4_IB_QPT_GSI: 1327 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1328 1329 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1330 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1331 MLX4_QP_ST_MLX : -1); 1332 case MLX4_IB_QPT_PROXY_SMI: 1333 case MLX4_IB_QPT_TUN_SMI: 1334 case MLX4_IB_QPT_PROXY_GSI: 1335 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1336 MLX4_QP_ST_UD : -1); 1337 default: return -1; 1338 } 1339 } 1340 1341 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1342 int attr_mask) 1343 { 1344 u8 dest_rd_atomic; 1345 u32 access_flags; 1346 u32 hw_access_flags = 0; 1347 1348 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1349 dest_rd_atomic = attr->max_dest_rd_atomic; 1350 else 1351 dest_rd_atomic = qp->resp_depth; 1352 1353 if (attr_mask & IB_QP_ACCESS_FLAGS) 1354 access_flags = attr->qp_access_flags; 1355 else 1356 access_flags = qp->atomic_rd_en; 1357 1358 if (!dest_rd_atomic) 1359 access_flags &= IB_ACCESS_REMOTE_WRITE; 1360 1361 if (access_flags & IB_ACCESS_REMOTE_READ) 1362 hw_access_flags |= MLX4_QP_BIT_RRE; 1363 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1364 hw_access_flags |= MLX4_QP_BIT_RAE; 1365 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1366 hw_access_flags |= MLX4_QP_BIT_RWE; 1367 1368 return cpu_to_be32(hw_access_flags); 1369 } 1370 1371 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1372 int attr_mask) 1373 { 1374 if (attr_mask & IB_QP_PKEY_INDEX) 1375 sqp->pkey_index = attr->pkey_index; 1376 if (attr_mask & IB_QP_QKEY) 1377 sqp->qkey = attr->qkey; 1378 if (attr_mask & IB_QP_SQ_PSN) 1379 sqp->send_psn = attr->sq_psn; 1380 } 1381 1382 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1383 { 1384 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1385 } 1386 1387 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 1388 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1389 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1390 { 1391 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) == 1392 IB_LINK_LAYER_ETHERNET; 1393 int vidx; 1394 int smac_index; 1395 int err; 1396 1397 1398 path->grh_mylmc = ah->src_path_bits & 0x7f; 1399 path->rlid = cpu_to_be16(ah->dlid); 1400 if (ah->static_rate) { 1401 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET; 1402 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1403 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1404 --path->static_rate; 1405 } else 1406 path->static_rate = 0; 1407 1408 if (ah->ah_flags & IB_AH_GRH) { 1409 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev, 1410 port, 1411 ah->grh.sgid_index); 1412 1413 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1414 pr_err("sgid_index (%u) too large. max is %d\n", 1415 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1416 return -1; 1417 } 1418 1419 path->grh_mylmc |= 1 << 7; 1420 path->mgid_index = real_sgid_index; 1421 path->hop_limit = ah->grh.hop_limit; 1422 path->tclass_flowlabel = 1423 cpu_to_be32((ah->grh.traffic_class << 20) | 1424 (ah->grh.flow_label)); 1425 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1426 } 1427 1428 if (is_eth) { 1429 if (!(ah->ah_flags & IB_AH_GRH)) 1430 return -1; 1431 1432 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1433 ((port - 1) << 6) | ((ah->sl & 7) << 3); 1434 1435 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1436 if (vlan_tag < 0x1000) { 1437 if (smac_info->vid < 0x1000) { 1438 /* both valid vlan ids */ 1439 if (smac_info->vid != vlan_tag) { 1440 /* different VIDs. unreg old and reg new */ 1441 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1442 if (err) 1443 return err; 1444 smac_info->candidate_vid = vlan_tag; 1445 smac_info->candidate_vlan_index = vidx; 1446 smac_info->candidate_vlan_port = port; 1447 smac_info->update_vid = 1; 1448 path->vlan_index = vidx; 1449 } else { 1450 path->vlan_index = smac_info->vlan_index; 1451 } 1452 } else { 1453 /* no current vlan tag in qp */ 1454 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1455 if (err) 1456 return err; 1457 smac_info->candidate_vid = vlan_tag; 1458 smac_info->candidate_vlan_index = vidx; 1459 smac_info->candidate_vlan_port = port; 1460 smac_info->update_vid = 1; 1461 path->vlan_index = vidx; 1462 } 1463 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1464 path->fl = 1 << 6; 1465 } else { 1466 /* have current vlan tag. unregister it at modify-qp success */ 1467 if (smac_info->vid < 0x1000) { 1468 smac_info->candidate_vid = 0xFFFF; 1469 smac_info->update_vid = 1; 1470 } 1471 } 1472 1473 /* get smac_index for RoCE use. 1474 * If no smac was yet assigned, register one. 1475 * If one was already assigned, but the new mac differs, 1476 * unregister the old one and register the new one. 1477 */ 1478 if ((!smac_info->smac && !smac_info->smac_port) || 1479 smac_info->smac != smac) { 1480 /* register candidate now, unreg if needed, after success */ 1481 smac_index = mlx4_register_mac(dev->dev, port, smac); 1482 if (smac_index >= 0) { 1483 smac_info->candidate_smac_index = smac_index; 1484 smac_info->candidate_smac = smac; 1485 smac_info->candidate_smac_port = port; 1486 } else { 1487 return -EINVAL; 1488 } 1489 } else { 1490 smac_index = smac_info->smac_index; 1491 } 1492 1493 memcpy(path->dmac, ah->dmac, 6); 1494 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1495 /* put MAC table smac index for IBoE */ 1496 path->grh_mylmc = (u8) (smac_index) | 0x80; 1497 } else { 1498 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1499 ((port - 1) << 6) | ((ah->sl & 0xf) << 2); 1500 } 1501 1502 return 0; 1503 } 1504 1505 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1506 enum ib_qp_attr_mask qp_attr_mask, 1507 struct mlx4_ib_qp *mqp, 1508 struct mlx4_qp_path *path, u8 port, 1509 u16 vlan_id, u8 *smac) 1510 { 1511 return _mlx4_set_path(dev, &qp->ah_attr, 1512 mlx4_mac_to_u64(smac), 1513 vlan_id, 1514 path, &mqp->pri, port); 1515 } 1516 1517 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1518 const struct ib_qp_attr *qp, 1519 enum ib_qp_attr_mask qp_attr_mask, 1520 struct mlx4_ib_qp *mqp, 1521 struct mlx4_qp_path *path, u8 port) 1522 { 1523 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1524 0, 1525 0xffff, 1526 path, &mqp->alt, port); 1527 } 1528 1529 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1530 { 1531 struct mlx4_ib_gid_entry *ge, *tmp; 1532 1533 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1534 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1535 ge->added = 1; 1536 ge->port = qp->port; 1537 } 1538 } 1539 } 1540 1541 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1542 struct mlx4_ib_qp *qp, 1543 struct mlx4_qp_context *context) 1544 { 1545 u64 u64_mac; 1546 int smac_index; 1547 1548 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1549 1550 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1551 if (!qp->pri.smac && !qp->pri.smac_port) { 1552 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1553 if (smac_index >= 0) { 1554 qp->pri.candidate_smac_index = smac_index; 1555 qp->pri.candidate_smac = u64_mac; 1556 qp->pri.candidate_smac_port = qp->port; 1557 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1558 } else { 1559 return -ENOENT; 1560 } 1561 } 1562 return 0; 1563 } 1564 1565 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1566 { 1567 struct counter_index *new_counter_index; 1568 int err; 1569 u32 tmp_idx; 1570 1571 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1572 IB_LINK_LAYER_ETHERNET || 1573 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1574 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1575 return 0; 1576 1577 err = mlx4_counter_alloc(dev->dev, &tmp_idx); 1578 if (err) 1579 return err; 1580 1581 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1582 if (!new_counter_index) { 1583 mlx4_counter_free(dev->dev, tmp_idx); 1584 return -ENOMEM; 1585 } 1586 1587 new_counter_index->index = tmp_idx; 1588 new_counter_index->allocated = 1; 1589 qp->counter_index = new_counter_index; 1590 1591 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1592 list_add_tail(&new_counter_index->list, 1593 &dev->counters_table[qp->port - 1].counters_list); 1594 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1595 1596 return 0; 1597 } 1598 1599 enum { 1600 MLX4_QPC_ROCE_MODE_1 = 0, 1601 MLX4_QPC_ROCE_MODE_2 = 2, 1602 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1603 }; 1604 1605 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1606 { 1607 switch (gid_type) { 1608 case IB_GID_TYPE_ROCE: 1609 return MLX4_QPC_ROCE_MODE_1; 1610 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1611 return MLX4_QPC_ROCE_MODE_2; 1612 default: 1613 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1614 } 1615 } 1616 1617 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 1618 const struct ib_qp_attr *attr, int attr_mask, 1619 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1620 { 1621 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1622 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1623 struct mlx4_ib_pd *pd; 1624 struct mlx4_ib_cq *send_cq, *recv_cq; 1625 struct mlx4_qp_context *context; 1626 enum mlx4_qp_optpar optpar = 0; 1627 int sqd_event; 1628 int steer_qp = 0; 1629 int err = -EINVAL; 1630 int counter_index; 1631 1632 /* APM is not supported under RoCE */ 1633 if (attr_mask & IB_QP_ALT_PATH && 1634 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1635 IB_LINK_LAYER_ETHERNET) 1636 return -ENOTSUPP; 1637 1638 context = kzalloc(sizeof *context, GFP_KERNEL); 1639 if (!context) 1640 return -ENOMEM; 1641 1642 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 1643 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 1644 1645 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 1646 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1647 else { 1648 optpar |= MLX4_QP_OPTPAR_PM_STATE; 1649 switch (attr->path_mig_state) { 1650 case IB_MIG_MIGRATED: 1651 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1652 break; 1653 case IB_MIG_REARM: 1654 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 1655 break; 1656 case IB_MIG_ARMED: 1657 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 1658 break; 1659 } 1660 } 1661 1662 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 1663 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 1664 else if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1665 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 1666 else if (ibqp->qp_type == IB_QPT_UD) { 1667 if (qp->flags & MLX4_IB_QP_LSO) 1668 context->mtu_msgmax = (IB_MTU_4096 << 5) | 1669 ilog2(dev->dev->caps.max_gso_sz); 1670 else 1671 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1672 } else if (attr_mask & IB_QP_PATH_MTU) { 1673 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 1674 pr_err("path MTU (%u) is invalid\n", 1675 attr->path_mtu); 1676 goto out; 1677 } 1678 context->mtu_msgmax = (attr->path_mtu << 5) | 1679 ilog2(dev->dev->caps.max_msg_sz); 1680 } 1681 1682 if (qp->rq.wqe_cnt) 1683 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 1684 context->rq_size_stride |= qp->rq.wqe_shift - 4; 1685 1686 if (qp->sq.wqe_cnt) 1687 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 1688 context->sq_size_stride |= qp->sq.wqe_shift - 4; 1689 1690 if (new_state == IB_QPS_RESET && qp->counter_index) 1691 mlx4_ib_free_qp_counter(dev, qp); 1692 1693 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1694 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 1695 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 1696 if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1697 context->param3 |= cpu_to_be32(1 << 30); 1698 } 1699 1700 if (qp->ibqp.uobject) 1701 context->usr_page = cpu_to_be32( 1702 mlx4_to_hw_uar_index(dev->dev, 1703 to_mucontext(ibqp->uobject->context)->uar.index)); 1704 else 1705 context->usr_page = cpu_to_be32( 1706 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 1707 1708 if (attr_mask & IB_QP_DEST_QPN) 1709 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 1710 1711 if (attr_mask & IB_QP_PORT) { 1712 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 1713 !(attr_mask & IB_QP_AV)) { 1714 mlx4_set_sched(&context->pri_path, attr->port_num); 1715 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 1716 } 1717 } 1718 1719 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 1720 err = create_qp_lb_counter(dev, qp); 1721 if (err) 1722 goto out; 1723 1724 counter_index = 1725 dev->counters_table[qp->port - 1].default_counter; 1726 if (qp->counter_index) 1727 counter_index = qp->counter_index->index; 1728 1729 if (counter_index != -1) { 1730 context->pri_path.counter_index = counter_index; 1731 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 1732 if (qp->counter_index) { 1733 context->pri_path.fl |= 1734 MLX4_FL_ETH_SRC_CHECK_MC_LB; 1735 context->pri_path.vlan_control |= 1736 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 1737 } 1738 } else 1739 context->pri_path.counter_index = 1740 MLX4_SINK_COUNTER_INDEX(dev->dev); 1741 1742 if (qp->flags & MLX4_IB_QP_NETIF) { 1743 mlx4_ib_steer_qp_reg(dev, qp, 1); 1744 steer_qp = 1; 1745 } 1746 1747 if (ibqp->qp_type == IB_QPT_GSI) { 1748 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 1749 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 1750 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 1751 1752 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 1753 } 1754 } 1755 1756 if (attr_mask & IB_QP_PKEY_INDEX) { 1757 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1758 context->pri_path.disable_pkey_check = 0x40; 1759 context->pri_path.pkey_index = attr->pkey_index; 1760 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 1761 } 1762 1763 if (attr_mask & IB_QP_AV) { 1764 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 : 1765 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1766 union ib_gid gid; 1767 struct ib_gid_attr gid_attr; 1768 u16 vlan = 0xffff; 1769 u8 smac[ETH_ALEN]; 1770 int status = 0; 1771 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) && 1772 attr->ah_attr.ah_flags & IB_AH_GRH; 1773 1774 if (is_eth) { 1775 int index = attr->ah_attr.grh.sgid_index; 1776 1777 status = ib_get_cached_gid(ibqp->device, port_num, 1778 index, &gid, &gid_attr); 1779 if (!status && !memcmp(&gid, &zgid, sizeof(gid))) 1780 status = -ENOENT; 1781 if (!status && gid_attr.ndev) { 1782 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev); 1783 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN); 1784 dev_put(gid_attr.ndev); 1785 } 1786 } 1787 if (status) 1788 goto out; 1789 1790 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 1791 port_num, vlan, smac)) 1792 goto out; 1793 1794 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 1795 MLX4_QP_OPTPAR_SCHED_QUEUE); 1796 1797 if (is_eth && 1798 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 1799 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type); 1800 1801 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 1802 err = -EINVAL; 1803 goto out; 1804 } 1805 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 1806 } 1807 1808 } 1809 1810 if (attr_mask & IB_QP_TIMEOUT) { 1811 context->pri_path.ackto |= attr->timeout << 3; 1812 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 1813 } 1814 1815 if (attr_mask & IB_QP_ALT_PATH) { 1816 if (attr->alt_port_num == 0 || 1817 attr->alt_port_num > dev->dev->caps.num_ports) 1818 goto out; 1819 1820 if (attr->alt_pkey_index >= 1821 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 1822 goto out; 1823 1824 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 1825 &context->alt_path, 1826 attr->alt_port_num)) 1827 goto out; 1828 1829 context->alt_path.pkey_index = attr->alt_pkey_index; 1830 context->alt_path.ackto = attr->alt_timeout << 3; 1831 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 1832 } 1833 1834 pd = get_pd(qp); 1835 get_cqs(qp, &send_cq, &recv_cq); 1836 context->pd = cpu_to_be32(pd->pdn); 1837 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1838 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 1839 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 1840 1841 /* Set "fast registration enabled" for all kernel QPs */ 1842 if (!qp->ibqp.uobject) 1843 context->params1 |= cpu_to_be32(1 << 11); 1844 1845 if (attr_mask & IB_QP_RNR_RETRY) { 1846 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1847 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 1848 } 1849 1850 if (attr_mask & IB_QP_RETRY_CNT) { 1851 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1852 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 1853 } 1854 1855 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1856 if (attr->max_rd_atomic) 1857 context->params1 |= 1858 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1859 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 1860 } 1861 1862 if (attr_mask & IB_QP_SQ_PSN) 1863 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1864 1865 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1866 if (attr->max_dest_rd_atomic) 1867 context->params2 |= 1868 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1869 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1870 } 1871 1872 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1873 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1874 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1875 } 1876 1877 if (ibqp->srq) 1878 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1879 1880 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1881 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1882 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1883 } 1884 if (attr_mask & IB_QP_RQ_PSN) 1885 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1886 1887 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 1888 if (attr_mask & IB_QP_QKEY) { 1889 if (qp->mlx4_ib_qp_type & 1890 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 1891 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 1892 else { 1893 if (mlx4_is_mfunc(dev->dev) && 1894 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 1895 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 1896 MLX4_RESERVED_QKEY_BASE) { 1897 pr_err("Cannot use reserved QKEY" 1898 " 0x%x (range 0xffff0000..0xffffffff" 1899 " is reserved)\n", attr->qkey); 1900 err = -EINVAL; 1901 goto out; 1902 } 1903 context->qkey = cpu_to_be32(attr->qkey); 1904 } 1905 optpar |= MLX4_QP_OPTPAR_Q_KEY; 1906 } 1907 1908 if (ibqp->srq) 1909 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 1910 1911 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1912 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1913 1914 if (cur_state == IB_QPS_INIT && 1915 new_state == IB_QPS_RTR && 1916 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 1917 ibqp->qp_type == IB_QPT_UD || 1918 ibqp->qp_type == IB_QPT_RAW_PACKET)) { 1919 context->pri_path.sched_queue = (qp->port - 1) << 6; 1920 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 1921 qp->mlx4_ib_qp_type & 1922 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 1923 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 1924 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 1925 context->pri_path.fl = 0x80; 1926 } else { 1927 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1928 context->pri_path.fl = 0x80; 1929 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 1930 } 1931 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1932 IB_LINK_LAYER_ETHERNET) { 1933 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 1934 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 1935 context->pri_path.feup = 1 << 7; /* don't fsm */ 1936 /* handle smac_index */ 1937 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 1938 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 1939 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 1940 err = handle_eth_ud_smac_index(dev, qp, context); 1941 if (err) { 1942 err = -EINVAL; 1943 goto out; 1944 } 1945 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1946 dev->qp1_proxy[qp->port - 1] = qp; 1947 } 1948 } 1949 } 1950 1951 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1952 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 1953 MLX4_IB_LINK_TYPE_ETH; 1954 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1955 /* set QP to receive both tunneled & non-tunneled packets */ 1956 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET))) 1957 context->srqn = cpu_to_be32(7 << 28); 1958 } 1959 } 1960 1961 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 1962 int is_eth = rdma_port_get_link_layer( 1963 &dev->ib_dev, qp->port) == 1964 IB_LINK_LAYER_ETHERNET; 1965 if (is_eth) { 1966 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 1967 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 1968 } 1969 } 1970 1971 1972 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1973 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1974 sqd_event = 1; 1975 else 1976 sqd_event = 0; 1977 1978 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1979 context->rlkey_roce_mode |= (1 << 4); 1980 1981 /* 1982 * Before passing a kernel QP to the HW, make sure that the 1983 * ownership bits of the send queue are set and the SQ 1984 * headroom is stamped so that the hardware doesn't start 1985 * processing stale work requests. 1986 */ 1987 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1988 struct mlx4_wqe_ctrl_seg *ctrl; 1989 int i; 1990 1991 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 1992 ctrl = get_send_wqe(qp, i); 1993 ctrl->owner_opcode = cpu_to_be32(1 << 31); 1994 if (qp->sq_max_wqes_per_wr == 1) 1995 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); 1996 1997 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 1998 } 1999 } 2000 2001 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2002 to_mlx4_state(new_state), context, optpar, 2003 sqd_event, &qp->mqp); 2004 if (err) 2005 goto out; 2006 2007 qp->state = new_state; 2008 2009 if (attr_mask & IB_QP_ACCESS_FLAGS) 2010 qp->atomic_rd_en = attr->qp_access_flags; 2011 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2012 qp->resp_depth = attr->max_dest_rd_atomic; 2013 if (attr_mask & IB_QP_PORT) { 2014 qp->port = attr->port_num; 2015 update_mcg_macs(dev, qp); 2016 } 2017 if (attr_mask & IB_QP_ALT_PATH) 2018 qp->alt_port = attr->alt_port_num; 2019 2020 if (is_sqp(dev, qp)) 2021 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2022 2023 /* 2024 * If we moved QP0 to RTR, bring the IB link up; if we moved 2025 * QP0 to RESET or ERROR, bring the link back down. 2026 */ 2027 if (is_qp0(dev, qp)) { 2028 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2029 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2030 pr_warn("INIT_PORT failed for port %d\n", 2031 qp->port); 2032 2033 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2034 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2035 mlx4_CLOSE_PORT(dev->dev, qp->port); 2036 } 2037 2038 /* 2039 * If we moved a kernel QP to RESET, clean up all old CQ 2040 * entries and reinitialize the QP. 2041 */ 2042 if (new_state == IB_QPS_RESET) { 2043 if (!ibqp->uobject) { 2044 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2045 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2046 if (send_cq != recv_cq) 2047 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2048 2049 qp->rq.head = 0; 2050 qp->rq.tail = 0; 2051 qp->sq.head = 0; 2052 qp->sq.tail = 0; 2053 qp->sq_next_wqe = 0; 2054 if (qp->rq.wqe_cnt) 2055 *qp->db.db = 0; 2056 2057 if (qp->flags & MLX4_IB_QP_NETIF) 2058 mlx4_ib_steer_qp_reg(dev, qp, 0); 2059 } 2060 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2061 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2062 qp->pri.smac = 0; 2063 qp->pri.smac_port = 0; 2064 } 2065 if (qp->alt.smac) { 2066 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2067 qp->alt.smac = 0; 2068 } 2069 if (qp->pri.vid < 0x1000) { 2070 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2071 qp->pri.vid = 0xFFFF; 2072 qp->pri.candidate_vid = 0xFFFF; 2073 qp->pri.update_vid = 0; 2074 } 2075 2076 if (qp->alt.vid < 0x1000) { 2077 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2078 qp->alt.vid = 0xFFFF; 2079 qp->alt.candidate_vid = 0xFFFF; 2080 qp->alt.update_vid = 0; 2081 } 2082 } 2083 out: 2084 if (err && qp->counter_index) 2085 mlx4_ib_free_qp_counter(dev, qp); 2086 if (err && steer_qp) 2087 mlx4_ib_steer_qp_reg(dev, qp, 0); 2088 kfree(context); 2089 if (qp->pri.candidate_smac || 2090 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2091 if (err) { 2092 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2093 } else { 2094 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2095 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2096 qp->pri.smac = qp->pri.candidate_smac; 2097 qp->pri.smac_index = qp->pri.candidate_smac_index; 2098 qp->pri.smac_port = qp->pri.candidate_smac_port; 2099 } 2100 qp->pri.candidate_smac = 0; 2101 qp->pri.candidate_smac_index = 0; 2102 qp->pri.candidate_smac_port = 0; 2103 } 2104 if (qp->alt.candidate_smac) { 2105 if (err) { 2106 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2107 } else { 2108 if (qp->alt.smac) 2109 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2110 qp->alt.smac = qp->alt.candidate_smac; 2111 qp->alt.smac_index = qp->alt.candidate_smac_index; 2112 qp->alt.smac_port = qp->alt.candidate_smac_port; 2113 } 2114 qp->alt.candidate_smac = 0; 2115 qp->alt.candidate_smac_index = 0; 2116 qp->alt.candidate_smac_port = 0; 2117 } 2118 2119 if (qp->pri.update_vid) { 2120 if (err) { 2121 if (qp->pri.candidate_vid < 0x1000) 2122 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2123 qp->pri.candidate_vid); 2124 } else { 2125 if (qp->pri.vid < 0x1000) 2126 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2127 qp->pri.vid); 2128 qp->pri.vid = qp->pri.candidate_vid; 2129 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2130 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2131 } 2132 qp->pri.candidate_vid = 0xFFFF; 2133 qp->pri.update_vid = 0; 2134 } 2135 2136 if (qp->alt.update_vid) { 2137 if (err) { 2138 if (qp->alt.candidate_vid < 0x1000) 2139 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2140 qp->alt.candidate_vid); 2141 } else { 2142 if (qp->alt.vid < 0x1000) 2143 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2144 qp->alt.vid); 2145 qp->alt.vid = qp->alt.candidate_vid; 2146 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2147 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2148 } 2149 qp->alt.candidate_vid = 0xFFFF; 2150 qp->alt.update_vid = 0; 2151 } 2152 2153 return err; 2154 } 2155 2156 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2157 int attr_mask, struct ib_udata *udata) 2158 { 2159 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2160 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2161 enum ib_qp_state cur_state, new_state; 2162 int err = -EINVAL; 2163 int ll; 2164 mutex_lock(&qp->mutex); 2165 2166 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2167 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2168 2169 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2170 ll = IB_LINK_LAYER_UNSPECIFIED; 2171 } else { 2172 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2173 ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2174 } 2175 2176 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2177 attr_mask, ll)) { 2178 pr_debug("qpn 0x%x: invalid attribute mask specified " 2179 "for transition %d to %d. qp_type %d," 2180 " attr_mask 0x%x\n", 2181 ibqp->qp_num, cur_state, new_state, 2182 ibqp->qp_type, attr_mask); 2183 goto out; 2184 } 2185 2186 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2187 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2188 if ((ibqp->qp_type == IB_QPT_RC) || 2189 (ibqp->qp_type == IB_QPT_UD) || 2190 (ibqp->qp_type == IB_QPT_UC) || 2191 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2192 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2193 attr->port_num = mlx4_ib_bond_next_port(dev); 2194 } 2195 } else { 2196 /* no sense in changing port_num 2197 * when ports are bonded */ 2198 attr_mask &= ~IB_QP_PORT; 2199 } 2200 } 2201 2202 if ((attr_mask & IB_QP_PORT) && 2203 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2204 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2205 "for transition %d to %d. qp_type %d\n", 2206 ibqp->qp_num, attr->port_num, cur_state, 2207 new_state, ibqp->qp_type); 2208 goto out; 2209 } 2210 2211 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2212 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2213 IB_LINK_LAYER_ETHERNET)) 2214 goto out; 2215 2216 if (attr_mask & IB_QP_PKEY_INDEX) { 2217 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2218 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2219 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2220 "for transition %d to %d. qp_type %d\n", 2221 ibqp->qp_num, attr->pkey_index, cur_state, 2222 new_state, ibqp->qp_type); 2223 goto out; 2224 } 2225 } 2226 2227 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2228 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2229 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2230 "Transition %d to %d. qp_type %d\n", 2231 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2232 new_state, ibqp->qp_type); 2233 goto out; 2234 } 2235 2236 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2237 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2238 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2239 "Transition %d to %d. qp_type %d\n", 2240 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2241 new_state, ibqp->qp_type); 2242 goto out; 2243 } 2244 2245 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2246 err = 0; 2247 goto out; 2248 } 2249 2250 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2251 2252 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2253 attr->port_num = 1; 2254 2255 out: 2256 mutex_unlock(&qp->mutex); 2257 return err; 2258 } 2259 2260 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2261 int attr_mask, struct ib_udata *udata) 2262 { 2263 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2264 int ret; 2265 2266 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2267 2268 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2269 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2270 int err = 0; 2271 2272 if (sqp->roce_v2_gsi) 2273 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2274 if (err) 2275 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2276 err); 2277 } 2278 return ret; 2279 } 2280 2281 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2282 { 2283 int i; 2284 for (i = 0; i < dev->caps.num_ports; i++) { 2285 if (qpn == dev->caps.qp0_proxy[i] || 2286 qpn == dev->caps.qp0_tunnel[i]) { 2287 *qkey = dev->caps.qp0_qkey[i]; 2288 return 0; 2289 } 2290 } 2291 return -EINVAL; 2292 } 2293 2294 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2295 struct ib_ud_wr *wr, 2296 void *wqe, unsigned *mlx_seg_len) 2297 { 2298 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2299 struct ib_device *ib_dev = &mdev->ib_dev; 2300 struct mlx4_wqe_mlx_seg *mlx = wqe; 2301 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2302 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2303 u16 pkey; 2304 u32 qkey; 2305 int send_size; 2306 int header_size; 2307 int spc; 2308 int i; 2309 2310 if (wr->wr.opcode != IB_WR_SEND) 2311 return -EINVAL; 2312 2313 send_size = 0; 2314 2315 for (i = 0; i < wr->wr.num_sge; ++i) 2316 send_size += wr->wr.sg_list[i].length; 2317 2318 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2319 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2320 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2321 send_size += sizeof (struct mlx4_ib_tunnel_header); 2322 2323 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2324 2325 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2326 sqp->ud_header.lrh.service_level = 2327 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2328 sqp->ud_header.lrh.destination_lid = 2329 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2330 sqp->ud_header.lrh.source_lid = 2331 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2332 } 2333 2334 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2335 2336 /* force loopback */ 2337 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2338 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2339 2340 sqp->ud_header.lrh.virtual_lane = 0; 2341 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2342 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2343 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2344 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2345 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2346 else 2347 sqp->ud_header.bth.destination_qpn = 2348 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]); 2349 2350 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2351 if (mlx4_is_master(mdev->dev)) { 2352 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2353 return -EINVAL; 2354 } else { 2355 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2356 return -EINVAL; 2357 } 2358 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2359 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2360 2361 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2362 sqp->ud_header.immediate_present = 0; 2363 2364 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2365 2366 /* 2367 * Inline data segments may not cross a 64 byte boundary. If 2368 * our UD header is bigger than the space available up to the 2369 * next 64 byte boundary in the WQE, use two inline data 2370 * segments to hold the UD header. 2371 */ 2372 spc = MLX4_INLINE_ALIGN - 2373 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2374 if (header_size <= spc) { 2375 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2376 memcpy(inl + 1, sqp->header_buf, header_size); 2377 i = 1; 2378 } else { 2379 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2380 memcpy(inl + 1, sqp->header_buf, spc); 2381 2382 inl = (void *) (inl + 1) + spc; 2383 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2384 /* 2385 * Need a barrier here to make sure all the data is 2386 * visible before the byte_count field is set. 2387 * Otherwise the HCA prefetcher could grab the 64-byte 2388 * chunk with this inline segment and get a valid (!= 2389 * 0xffffffff) byte count but stale data, and end up 2390 * generating a packet with bad headers. 2391 * 2392 * The first inline segment's byte_count field doesn't 2393 * need a barrier, because it comes after a 2394 * control/MLX segment and therefore is at an offset 2395 * of 16 mod 64. 2396 */ 2397 wmb(); 2398 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2399 i = 2; 2400 } 2401 2402 *mlx_seg_len = 2403 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2404 return 0; 2405 } 2406 2407 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2408 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr, 2409 void *wqe, unsigned *mlx_seg_len) 2410 { 2411 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2412 struct mlx4_wqe_mlx_seg *mlx = wqe; 2413 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2414 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2415 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2416 union ib_gid sgid; 2417 u16 pkey; 2418 int send_size; 2419 int header_size; 2420 int spc; 2421 int i; 2422 int err = 0; 2423 u16 vlan = 0xffff; 2424 bool is_eth; 2425 bool is_vlan = false; 2426 bool is_grh; 2427 bool is_udp = false; 2428 int ip_version = 0; 2429 2430 send_size = 0; 2431 for (i = 0; i < wr->wr.num_sge; ++i) 2432 send_size += wr->wr.sg_list[i].length; 2433 2434 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2435 is_grh = mlx4_ib_ah_grh_present(ah); 2436 if (is_eth) { 2437 struct ib_gid_attr gid_attr; 2438 2439 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2440 /* When multi-function is enabled, the ib_core gid 2441 * indexes don't necessarily match the hw ones, so 2442 * we must use our own cache */ 2443 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2444 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2445 ah->av.ib.gid_index, &sgid.raw[0]); 2446 if (err) 2447 return err; 2448 } else { 2449 err = ib_get_cached_gid(ib_dev, 2450 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2451 ah->av.ib.gid_index, &sgid, 2452 &gid_attr); 2453 if (!err) { 2454 if (gid_attr.ndev) 2455 dev_put(gid_attr.ndev); 2456 if (!memcmp(&sgid, &zgid, sizeof(sgid))) 2457 err = -ENOENT; 2458 } 2459 if (!err) { 2460 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2461 if (is_udp) { 2462 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 2463 ip_version = 4; 2464 else 2465 ip_version = 6; 2466 is_grh = false; 2467 } 2468 } else { 2469 return err; 2470 } 2471 } 2472 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 2473 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 2474 is_vlan = 1; 2475 } 2476 } 2477 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 2478 ip_version, is_udp, 0, &sqp->ud_header); 2479 if (err) 2480 return err; 2481 2482 if (!is_eth) { 2483 sqp->ud_header.lrh.service_level = 2484 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2485 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 2486 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2487 } 2488 2489 if (is_grh || (ip_version == 6)) { 2490 sqp->ud_header.grh.traffic_class = 2491 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2492 sqp->ud_header.grh.flow_label = 2493 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 2494 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 2495 if (is_eth) 2496 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 2497 else { 2498 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2499 /* When multi-function is enabled, the ib_core gid 2500 * indexes don't necessarily match the hw ones, so 2501 * we must use our own cache */ 2502 sqp->ud_header.grh.source_gid.global.subnet_prefix = 2503 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2504 subnet_prefix; 2505 sqp->ud_header.grh.source_gid.global.interface_id = 2506 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2507 guid_cache[ah->av.ib.gid_index]; 2508 } else 2509 ib_get_cached_gid(ib_dev, 2510 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2511 ah->av.ib.gid_index, 2512 &sqp->ud_header.grh.source_gid, NULL); 2513 } 2514 memcpy(sqp->ud_header.grh.destination_gid.raw, 2515 ah->av.ib.dgid, 16); 2516 } 2517 2518 if (ip_version == 4) { 2519 sqp->ud_header.ip4.tos = 2520 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2521 sqp->ud_header.ip4.id = 0; 2522 sqp->ud_header.ip4.frag_off = htons(IP_DF); 2523 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 2524 2525 memcpy(&sqp->ud_header.ip4.saddr, 2526 sgid.raw + 12, 4); 2527 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 2528 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 2529 } 2530 2531 if (is_udp) { 2532 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 2533 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 2534 sqp->ud_header.udp.csum = 0; 2535 } 2536 2537 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2538 2539 if (!is_eth) { 2540 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 2541 (sqp->ud_header.lrh.destination_lid == 2542 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 2543 (sqp->ud_header.lrh.service_level << 8)); 2544 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 2545 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 2546 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2547 } 2548 2549 switch (wr->wr.opcode) { 2550 case IB_WR_SEND: 2551 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2552 sqp->ud_header.immediate_present = 0; 2553 break; 2554 case IB_WR_SEND_WITH_IMM: 2555 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2556 sqp->ud_header.immediate_present = 1; 2557 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 2558 break; 2559 default: 2560 return -EINVAL; 2561 } 2562 2563 if (is_eth) { 2564 struct in6_addr in6; 2565 u16 ether_type; 2566 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 2567 2568 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE : 2569 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 2570 2571 mlx->sched_prio = cpu_to_be16(pcp); 2572 2573 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 2574 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 2575 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 2576 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 2577 memcpy(&in6, sgid.raw, sizeof(in6)); 2578 2579 2580 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 2581 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 2582 if (!is_vlan) { 2583 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 2584 } else { 2585 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 2586 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 2587 } 2588 } else { 2589 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 2590 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 2591 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 2592 } 2593 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2594 if (!sqp->qp.ibqp.qp_num) 2595 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 2596 else 2597 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 2598 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2599 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2600 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2601 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 2602 sqp->qkey : wr->remote_qkey); 2603 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 2604 2605 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2606 2607 if (0) { 2608 pr_err("built UD header of size %d:\n", header_size); 2609 for (i = 0; i < header_size / 4; ++i) { 2610 if (i % 8 == 0) 2611 pr_err(" [%02x] ", i * 4); 2612 pr_cont(" %08x", 2613 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 2614 if ((i + 1) % 8 == 0) 2615 pr_cont("\n"); 2616 } 2617 pr_err("\n"); 2618 } 2619 2620 /* 2621 * Inline data segments may not cross a 64 byte boundary. If 2622 * our UD header is bigger than the space available up to the 2623 * next 64 byte boundary in the WQE, use two inline data 2624 * segments to hold the UD header. 2625 */ 2626 spc = MLX4_INLINE_ALIGN - 2627 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2628 if (header_size <= spc) { 2629 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2630 memcpy(inl + 1, sqp->header_buf, header_size); 2631 i = 1; 2632 } else { 2633 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2634 memcpy(inl + 1, sqp->header_buf, spc); 2635 2636 inl = (void *) (inl + 1) + spc; 2637 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2638 /* 2639 * Need a barrier here to make sure all the data is 2640 * visible before the byte_count field is set. 2641 * Otherwise the HCA prefetcher could grab the 64-byte 2642 * chunk with this inline segment and get a valid (!= 2643 * 0xffffffff) byte count but stale data, and end up 2644 * generating a packet with bad headers. 2645 * 2646 * The first inline segment's byte_count field doesn't 2647 * need a barrier, because it comes after a 2648 * control/MLX segment and therefore is at an offset 2649 * of 16 mod 64. 2650 */ 2651 wmb(); 2652 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2653 i = 2; 2654 } 2655 2656 *mlx_seg_len = 2657 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2658 return 0; 2659 } 2660 2661 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2662 { 2663 unsigned cur; 2664 struct mlx4_ib_cq *cq; 2665 2666 cur = wq->head - wq->tail; 2667 if (likely(cur + nreq < wq->max_post)) 2668 return 0; 2669 2670 cq = to_mcq(ib_cq); 2671 spin_lock(&cq->lock); 2672 cur = wq->head - wq->tail; 2673 spin_unlock(&cq->lock); 2674 2675 return cur + nreq >= wq->max_post; 2676 } 2677 2678 static __be32 convert_access(int acc) 2679 { 2680 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 2681 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 2682 (acc & IB_ACCESS_REMOTE_WRITE ? 2683 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 2684 (acc & IB_ACCESS_REMOTE_READ ? 2685 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 2686 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 2687 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 2688 } 2689 2690 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 2691 struct ib_reg_wr *wr) 2692 { 2693 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 2694 2695 fseg->flags = convert_access(wr->access); 2696 fseg->mem_key = cpu_to_be32(wr->key); 2697 fseg->buf_list = cpu_to_be64(mr->page_map); 2698 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 2699 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 2700 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 2701 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 2702 fseg->reserved[0] = 0; 2703 fseg->reserved[1] = 0; 2704 } 2705 2706 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 2707 { 2708 memset(iseg, 0, sizeof(*iseg)); 2709 iseg->mem_key = cpu_to_be32(rkey); 2710 } 2711 2712 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 2713 u64 remote_addr, u32 rkey) 2714 { 2715 rseg->raddr = cpu_to_be64(remote_addr); 2716 rseg->rkey = cpu_to_be32(rkey); 2717 rseg->reserved = 0; 2718 } 2719 2720 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 2721 struct ib_atomic_wr *wr) 2722 { 2723 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 2724 aseg->swap_add = cpu_to_be64(wr->swap); 2725 aseg->compare = cpu_to_be64(wr->compare_add); 2726 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 2727 aseg->swap_add = cpu_to_be64(wr->compare_add); 2728 aseg->compare = cpu_to_be64(wr->compare_add_mask); 2729 } else { 2730 aseg->swap_add = cpu_to_be64(wr->compare_add); 2731 aseg->compare = 0; 2732 } 2733 2734 } 2735 2736 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 2737 struct ib_atomic_wr *wr) 2738 { 2739 aseg->swap_add = cpu_to_be64(wr->swap); 2740 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 2741 aseg->compare = cpu_to_be64(wr->compare_add); 2742 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 2743 } 2744 2745 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 2746 struct ib_ud_wr *wr) 2747 { 2748 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 2749 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 2750 dseg->qkey = cpu_to_be32(wr->remote_qkey); 2751 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 2752 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 2753 } 2754 2755 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 2756 struct mlx4_wqe_datagram_seg *dseg, 2757 struct ib_ud_wr *wr, 2758 enum mlx4_ib_qp_type qpt) 2759 { 2760 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 2761 struct mlx4_av sqp_av = {0}; 2762 int port = *((u8 *) &av->ib.port_pd) & 0x3; 2763 2764 /* force loopback */ 2765 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 2766 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 2767 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 2768 cpu_to_be32(0xf0000000); 2769 2770 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 2771 if (qpt == MLX4_IB_QPT_PROXY_GSI) 2772 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]); 2773 else 2774 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]); 2775 /* Use QKEY from the QP context, which is set by master */ 2776 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2777 } 2778 2779 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len) 2780 { 2781 struct mlx4_wqe_inline_seg *inl = wqe; 2782 struct mlx4_ib_tunnel_header hdr; 2783 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2784 int spc; 2785 int i; 2786 2787 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 2788 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 2789 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 2790 hdr.qkey = cpu_to_be32(wr->remote_qkey); 2791 memcpy(hdr.mac, ah->av.eth.mac, 6); 2792 hdr.vlan = ah->av.eth.vlan; 2793 2794 spc = MLX4_INLINE_ALIGN - 2795 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2796 if (sizeof (hdr) <= spc) { 2797 memcpy(inl + 1, &hdr, sizeof (hdr)); 2798 wmb(); 2799 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 2800 i = 1; 2801 } else { 2802 memcpy(inl + 1, &hdr, spc); 2803 wmb(); 2804 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2805 2806 inl = (void *) (inl + 1) + spc; 2807 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 2808 wmb(); 2809 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 2810 i = 2; 2811 } 2812 2813 *mlx_seg_len = 2814 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 2815 } 2816 2817 static void set_mlx_icrc_seg(void *dseg) 2818 { 2819 u32 *t = dseg; 2820 struct mlx4_wqe_inline_seg *iseg = dseg; 2821 2822 t[1] = 0; 2823 2824 /* 2825 * Need a barrier here before writing the byte_count field to 2826 * make sure that all the data is visible before the 2827 * byte_count field is set. Otherwise, if the segment begins 2828 * a new cacheline, the HCA prefetcher could grab the 64-byte 2829 * chunk and get a valid (!= * 0xffffffff) byte count but 2830 * stale data, and end up sending the wrong data. 2831 */ 2832 wmb(); 2833 2834 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 2835 } 2836 2837 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2838 { 2839 dseg->lkey = cpu_to_be32(sg->lkey); 2840 dseg->addr = cpu_to_be64(sg->addr); 2841 2842 /* 2843 * Need a barrier here before writing the byte_count field to 2844 * make sure that all the data is visible before the 2845 * byte_count field is set. Otherwise, if the segment begins 2846 * a new cacheline, the HCA prefetcher could grab the 64-byte 2847 * chunk and get a valid (!= * 0xffffffff) byte count but 2848 * stale data, and end up sending the wrong data. 2849 */ 2850 wmb(); 2851 2852 dseg->byte_count = cpu_to_be32(sg->length); 2853 } 2854 2855 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2856 { 2857 dseg->byte_count = cpu_to_be32(sg->length); 2858 dseg->lkey = cpu_to_be32(sg->lkey); 2859 dseg->addr = cpu_to_be64(sg->addr); 2860 } 2861 2862 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr, 2863 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 2864 __be32 *lso_hdr_sz, __be32 *blh) 2865 { 2866 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 2867 2868 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 2869 *blh = cpu_to_be32(1 << 6); 2870 2871 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 2872 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 2873 return -EINVAL; 2874 2875 memcpy(wqe->header, wr->header, wr->hlen); 2876 2877 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 2878 *lso_seg_len = halign; 2879 return 0; 2880 } 2881 2882 static __be32 send_ieth(struct ib_send_wr *wr) 2883 { 2884 switch (wr->opcode) { 2885 case IB_WR_SEND_WITH_IMM: 2886 case IB_WR_RDMA_WRITE_WITH_IMM: 2887 return wr->ex.imm_data; 2888 2889 case IB_WR_SEND_WITH_INV: 2890 return cpu_to_be32(wr->ex.invalidate_rkey); 2891 2892 default: 2893 return 0; 2894 } 2895 } 2896 2897 static void add_zero_len_inline(void *wqe) 2898 { 2899 struct mlx4_wqe_inline_seg *inl = wqe; 2900 memset(wqe, 0, 16); 2901 inl->byte_count = cpu_to_be32(1 << 31); 2902 } 2903 2904 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2905 struct ib_send_wr **bad_wr) 2906 { 2907 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2908 void *wqe; 2909 struct mlx4_wqe_ctrl_seg *ctrl; 2910 struct mlx4_wqe_data_seg *dseg; 2911 unsigned long flags; 2912 int nreq; 2913 int err = 0; 2914 unsigned ind; 2915 int uninitialized_var(stamp); 2916 int uninitialized_var(size); 2917 unsigned uninitialized_var(seglen); 2918 __be32 dummy; 2919 __be32 *lso_wqe; 2920 __be32 uninitialized_var(lso_hdr_sz); 2921 __be32 blh; 2922 int i; 2923 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2924 2925 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2926 struct mlx4_ib_sqp *sqp = to_msqp(qp); 2927 2928 if (sqp->roce_v2_gsi) { 2929 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 2930 struct ib_gid_attr gid_attr; 2931 union ib_gid gid; 2932 2933 if (!ib_get_cached_gid(ibqp->device, 2934 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2935 ah->av.ib.gid_index, &gid, 2936 &gid_attr)) { 2937 if (gid_attr.ndev) 2938 dev_put(gid_attr.ndev); 2939 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 2940 to_mqp(sqp->roce_v2_gsi) : qp; 2941 } else { 2942 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 2943 ah->av.ib.gid_index); 2944 } 2945 } 2946 } 2947 2948 spin_lock_irqsave(&qp->sq.lock, flags); 2949 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 2950 err = -EIO; 2951 *bad_wr = wr; 2952 nreq = 0; 2953 goto out; 2954 } 2955 2956 ind = qp->sq_next_wqe; 2957 2958 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2959 lso_wqe = &dummy; 2960 blh = 0; 2961 2962 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 2963 err = -ENOMEM; 2964 *bad_wr = wr; 2965 goto out; 2966 } 2967 2968 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 2969 err = -EINVAL; 2970 *bad_wr = wr; 2971 goto out; 2972 } 2973 2974 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 2975 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 2976 2977 ctrl->srcrb_flags = 2978 (wr->send_flags & IB_SEND_SIGNALED ? 2979 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 2980 (wr->send_flags & IB_SEND_SOLICITED ? 2981 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 2982 ((wr->send_flags & IB_SEND_IP_CSUM) ? 2983 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 2984 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 2985 qp->sq_signal_bits; 2986 2987 ctrl->imm = send_ieth(wr); 2988 2989 wqe += sizeof *ctrl; 2990 size = sizeof *ctrl / 16; 2991 2992 switch (qp->mlx4_ib_qp_type) { 2993 case MLX4_IB_QPT_RC: 2994 case MLX4_IB_QPT_UC: 2995 switch (wr->opcode) { 2996 case IB_WR_ATOMIC_CMP_AND_SWP: 2997 case IB_WR_ATOMIC_FETCH_AND_ADD: 2998 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 2999 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3000 atomic_wr(wr)->rkey); 3001 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3002 3003 set_atomic_seg(wqe, atomic_wr(wr)); 3004 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3005 3006 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3007 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3008 3009 break; 3010 3011 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3012 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3013 atomic_wr(wr)->rkey); 3014 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3015 3016 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3017 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3018 3019 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3020 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3021 3022 break; 3023 3024 case IB_WR_RDMA_READ: 3025 case IB_WR_RDMA_WRITE: 3026 case IB_WR_RDMA_WRITE_WITH_IMM: 3027 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3028 rdma_wr(wr)->rkey); 3029 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3030 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3031 break; 3032 3033 case IB_WR_LOCAL_INV: 3034 ctrl->srcrb_flags |= 3035 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3036 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3037 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3038 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3039 break; 3040 3041 case IB_WR_REG_MR: 3042 ctrl->srcrb_flags |= 3043 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3044 set_reg_seg(wqe, reg_wr(wr)); 3045 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3046 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3047 break; 3048 3049 default: 3050 /* No extra segments required for sends */ 3051 break; 3052 } 3053 break; 3054 3055 case MLX4_IB_QPT_TUN_SMI_OWNER: 3056 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3057 ctrl, &seglen); 3058 if (unlikely(err)) { 3059 *bad_wr = wr; 3060 goto out; 3061 } 3062 wqe += seglen; 3063 size += seglen / 16; 3064 break; 3065 case MLX4_IB_QPT_TUN_SMI: 3066 case MLX4_IB_QPT_TUN_GSI: 3067 /* this is a UD qp used in MAD responses to slaves. */ 3068 set_datagram_seg(wqe, ud_wr(wr)); 3069 /* set the forced-loopback bit in the data seg av */ 3070 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3071 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3072 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3073 break; 3074 case MLX4_IB_QPT_UD: 3075 set_datagram_seg(wqe, ud_wr(wr)); 3076 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3077 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3078 3079 if (wr->opcode == IB_WR_LSO) { 3080 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3081 &lso_hdr_sz, &blh); 3082 if (unlikely(err)) { 3083 *bad_wr = wr; 3084 goto out; 3085 } 3086 lso_wqe = (__be32 *) wqe; 3087 wqe += seglen; 3088 size += seglen / 16; 3089 } 3090 break; 3091 3092 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3093 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3094 ctrl, &seglen); 3095 if (unlikely(err)) { 3096 *bad_wr = wr; 3097 goto out; 3098 } 3099 wqe += seglen; 3100 size += seglen / 16; 3101 /* to start tunnel header on a cache-line boundary */ 3102 add_zero_len_inline(wqe); 3103 wqe += 16; 3104 size++; 3105 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3106 wqe += seglen; 3107 size += seglen / 16; 3108 break; 3109 case MLX4_IB_QPT_PROXY_SMI: 3110 case MLX4_IB_QPT_PROXY_GSI: 3111 /* If we are tunneling special qps, this is a UD qp. 3112 * In this case we first add a UD segment targeting 3113 * the tunnel qp, and then add a header with address 3114 * information */ 3115 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3116 ud_wr(wr), 3117 qp->mlx4_ib_qp_type); 3118 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3119 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3120 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3121 wqe += seglen; 3122 size += seglen / 16; 3123 break; 3124 3125 case MLX4_IB_QPT_SMI: 3126 case MLX4_IB_QPT_GSI: 3127 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3128 &seglen); 3129 if (unlikely(err)) { 3130 *bad_wr = wr; 3131 goto out; 3132 } 3133 wqe += seglen; 3134 size += seglen / 16; 3135 break; 3136 3137 default: 3138 break; 3139 } 3140 3141 /* 3142 * Write data segments in reverse order, so as to 3143 * overwrite cacheline stamp last within each 3144 * cacheline. This avoids issues with WQE 3145 * prefetching. 3146 */ 3147 3148 dseg = wqe; 3149 dseg += wr->num_sge - 1; 3150 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3151 3152 /* Add one more inline data segment for ICRC for MLX sends */ 3153 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3154 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3155 qp->mlx4_ib_qp_type & 3156 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3157 set_mlx_icrc_seg(dseg + 1); 3158 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3159 } 3160 3161 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3162 set_data_seg(dseg, wr->sg_list + i); 3163 3164 /* 3165 * Possibly overwrite stamping in cacheline with LSO 3166 * segment only after making sure all data segments 3167 * are written. 3168 */ 3169 wmb(); 3170 *lso_wqe = lso_hdr_sz; 3171 3172 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 3173 MLX4_WQE_CTRL_FENCE : 0) | size; 3174 3175 /* 3176 * Make sure descriptor is fully written before 3177 * setting ownership bit (because HW can start 3178 * executing as soon as we do). 3179 */ 3180 wmb(); 3181 3182 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3183 *bad_wr = wr; 3184 err = -EINVAL; 3185 goto out; 3186 } 3187 3188 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3189 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3190 3191 stamp = ind + qp->sq_spare_wqes; 3192 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3193 3194 /* 3195 * We can improve latency by not stamping the last 3196 * send queue WQE until after ringing the doorbell, so 3197 * only stamp here if there are still more WQEs to post. 3198 * 3199 * Same optimization applies to padding with NOP wqe 3200 * in case of WQE shrinking (used to prevent wrap-around 3201 * in the middle of WR). 3202 */ 3203 if (wr->next) { 3204 stamp_send_wqe(qp, stamp, size * 16); 3205 ind = pad_wraparound(qp, ind); 3206 } 3207 } 3208 3209 out: 3210 if (likely(nreq)) { 3211 qp->sq.head += nreq; 3212 3213 /* 3214 * Make sure that descriptors are written before 3215 * doorbell record. 3216 */ 3217 wmb(); 3218 3219 writel(qp->doorbell_qpn, 3220 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3221 3222 /* 3223 * Make sure doorbells don't leak out of SQ spinlock 3224 * and reach the HCA out of order. 3225 */ 3226 mmiowb(); 3227 3228 stamp_send_wqe(qp, stamp, size * 16); 3229 3230 ind = pad_wraparound(qp, ind); 3231 qp->sq_next_wqe = ind; 3232 } 3233 3234 spin_unlock_irqrestore(&qp->sq.lock, flags); 3235 3236 return err; 3237 } 3238 3239 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3240 struct ib_recv_wr **bad_wr) 3241 { 3242 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3243 struct mlx4_wqe_data_seg *scat; 3244 unsigned long flags; 3245 int err = 0; 3246 int nreq; 3247 int ind; 3248 int max_gs; 3249 int i; 3250 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3251 3252 max_gs = qp->rq.max_gs; 3253 spin_lock_irqsave(&qp->rq.lock, flags); 3254 3255 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3256 err = -EIO; 3257 *bad_wr = wr; 3258 nreq = 0; 3259 goto out; 3260 } 3261 3262 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3263 3264 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3265 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3266 err = -ENOMEM; 3267 *bad_wr = wr; 3268 goto out; 3269 } 3270 3271 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3272 err = -EINVAL; 3273 *bad_wr = wr; 3274 goto out; 3275 } 3276 3277 scat = get_recv_wqe(qp, ind); 3278 3279 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3280 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3281 ib_dma_sync_single_for_device(ibqp->device, 3282 qp->sqp_proxy_rcv[ind].map, 3283 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3284 DMA_FROM_DEVICE); 3285 scat->byte_count = 3286 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3287 /* use dma lkey from upper layer entry */ 3288 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3289 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3290 scat++; 3291 max_gs--; 3292 } 3293 3294 for (i = 0; i < wr->num_sge; ++i) 3295 __set_data_seg(scat + i, wr->sg_list + i); 3296 3297 if (i < max_gs) { 3298 scat[i].byte_count = 0; 3299 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3300 scat[i].addr = 0; 3301 } 3302 3303 qp->rq.wrid[ind] = wr->wr_id; 3304 3305 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3306 } 3307 3308 out: 3309 if (likely(nreq)) { 3310 qp->rq.head += nreq; 3311 3312 /* 3313 * Make sure that descriptors are written before 3314 * doorbell record. 3315 */ 3316 wmb(); 3317 3318 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3319 } 3320 3321 spin_unlock_irqrestore(&qp->rq.lock, flags); 3322 3323 return err; 3324 } 3325 3326 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3327 { 3328 switch (mlx4_state) { 3329 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3330 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3331 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3332 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3333 case MLX4_QP_STATE_SQ_DRAINING: 3334 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3335 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3336 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3337 default: return -1; 3338 } 3339 } 3340 3341 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3342 { 3343 switch (mlx4_mig_state) { 3344 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3345 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3346 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3347 default: return -1; 3348 } 3349 } 3350 3351 static int to_ib_qp_access_flags(int mlx4_flags) 3352 { 3353 int ib_flags = 0; 3354 3355 if (mlx4_flags & MLX4_QP_BIT_RRE) 3356 ib_flags |= IB_ACCESS_REMOTE_READ; 3357 if (mlx4_flags & MLX4_QP_BIT_RWE) 3358 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3359 if (mlx4_flags & MLX4_QP_BIT_RAE) 3360 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3361 3362 return ib_flags; 3363 } 3364 3365 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3366 struct mlx4_qp_path *path) 3367 { 3368 struct mlx4_dev *dev = ibdev->dev; 3369 int is_eth; 3370 3371 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 3372 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; 3373 3374 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 3375 return; 3376 3377 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) == 3378 IB_LINK_LAYER_ETHERNET; 3379 if (is_eth) 3380 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) | 3381 ((path->sched_queue & 4) << 1); 3382 else 3383 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; 3384 3385 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3386 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; 3387 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3388 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 3389 if (ib_ah_attr->ah_flags) { 3390 ib_ah_attr->grh.sgid_index = path->mgid_index; 3391 ib_ah_attr->grh.hop_limit = path->hop_limit; 3392 ib_ah_attr->grh.traffic_class = 3393 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3394 ib_ah_attr->grh.flow_label = 3395 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3396 memcpy(ib_ah_attr->grh.dgid.raw, 3397 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 3398 } 3399 } 3400 3401 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3402 struct ib_qp_init_attr *qp_init_attr) 3403 { 3404 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3405 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3406 struct mlx4_qp_context context; 3407 int mlx4_state; 3408 int err = 0; 3409 3410 mutex_lock(&qp->mutex); 3411 3412 if (qp->state == IB_QPS_RESET) { 3413 qp_attr->qp_state = IB_QPS_RESET; 3414 goto done; 3415 } 3416 3417 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3418 if (err) { 3419 err = -EINVAL; 3420 goto out; 3421 } 3422 3423 mlx4_state = be32_to_cpu(context.flags) >> 28; 3424 3425 qp->state = to_ib_qp_state(mlx4_state); 3426 qp_attr->qp_state = qp->state; 3427 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3428 qp_attr->path_mig_state = 3429 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3430 qp_attr->qkey = be32_to_cpu(context.qkey); 3431 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3432 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3433 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3434 qp_attr->qp_access_flags = 3435 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3436 3437 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3438 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3439 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3440 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3441 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3442 } 3443 3444 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3445 if (qp_attr->qp_state == IB_QPS_INIT) 3446 qp_attr->port_num = qp->port; 3447 else 3448 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3449 3450 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3451 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3452 3453 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3454 3455 qp_attr->max_dest_rd_atomic = 3456 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3457 qp_attr->min_rnr_timer = 3458 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3459 qp_attr->timeout = context.pri_path.ackto >> 3; 3460 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3461 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3462 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3463 3464 done: 3465 qp_attr->cur_qp_state = qp_attr->qp_state; 3466 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3467 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3468 3469 if (!ibqp->uobject) { 3470 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3471 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3472 } else { 3473 qp_attr->cap.max_send_wr = 0; 3474 qp_attr->cap.max_send_sge = 0; 3475 } 3476 3477 /* 3478 * We don't support inline sends for kernel QPs (yet), and we 3479 * don't know what userspace's value should be. 3480 */ 3481 qp_attr->cap.max_inline_data = 0; 3482 3483 qp_init_attr->cap = qp_attr->cap; 3484 3485 qp_init_attr->create_flags = 0; 3486 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3487 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3488 3489 if (qp->flags & MLX4_IB_QP_LSO) 3490 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 3491 3492 if (qp->flags & MLX4_IB_QP_NETIF) 3493 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 3494 3495 qp_init_attr->sq_sig_type = 3496 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 3497 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3498 3499 out: 3500 mutex_unlock(&qp->mutex); 3501 return err; 3502 } 3503 3504