1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static void free_gid_entry(struct gid_entry *entry) 250 { 251 memset(&entry->gid, 0, sizeof(entry->gid)); 252 kfree(entry->ctx); 253 entry->ctx = NULL; 254 } 255 256 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 257 { 258 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 259 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 260 struct mlx4_port_gid_table *port_gid_table; 261 int free = -1, found = -1; 262 int ret = 0; 263 int hw_update = 0; 264 int i; 265 struct gid_entry *gids = NULL; 266 u16 vlan_id = 0xffff; 267 u8 mac[ETH_ALEN]; 268 269 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 270 return -EINVAL; 271 272 if (attr->port_num > MLX4_MAX_PORTS) 273 return -EINVAL; 274 275 if (!context) 276 return -EINVAL; 277 278 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 279 if (ret) 280 return ret; 281 port_gid_table = &iboe->gids[attr->port_num - 1]; 282 spin_lock_bh(&iboe->lock); 283 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 284 if (!memcmp(&port_gid_table->gids[i].gid, 285 &attr->gid, sizeof(attr->gid)) && 286 port_gid_table->gids[i].gid_type == attr->gid_type && 287 port_gid_table->gids[i].vlan_id == vlan_id) { 288 found = i; 289 break; 290 } 291 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 292 free = i; /* HW has space */ 293 } 294 295 if (found < 0) { 296 if (free < 0) { 297 ret = -ENOSPC; 298 } else { 299 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 300 if (!port_gid_table->gids[free].ctx) { 301 ret = -ENOMEM; 302 } else { 303 *context = port_gid_table->gids[free].ctx; 304 memcpy(&port_gid_table->gids[free].gid, 305 &attr->gid, sizeof(attr->gid)); 306 port_gid_table->gids[free].gid_type = attr->gid_type; 307 port_gid_table->gids[free].vlan_id = vlan_id; 308 port_gid_table->gids[free].ctx->real_index = free; 309 port_gid_table->gids[free].ctx->refcount = 1; 310 hw_update = 1; 311 } 312 } 313 } else { 314 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 315 *context = ctx; 316 ctx->refcount++; 317 } 318 if (!ret && hw_update) { 319 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 320 GFP_ATOMIC); 321 if (!gids) { 322 ret = -ENOMEM; 323 *context = NULL; 324 free_gid_entry(&port_gid_table->gids[free]); 325 } else { 326 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 327 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 328 gids[i].gid_type = port_gid_table->gids[i].gid_type; 329 } 330 } 331 } 332 spin_unlock_bh(&iboe->lock); 333 334 if (!ret && hw_update) { 335 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 336 if (ret) { 337 spin_lock_bh(&iboe->lock); 338 *context = NULL; 339 free_gid_entry(&port_gid_table->gids[free]); 340 spin_unlock_bh(&iboe->lock); 341 } 342 kfree(gids); 343 } 344 345 return ret; 346 } 347 348 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 349 { 350 struct gid_cache_context *ctx = *context; 351 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 352 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 353 struct mlx4_port_gid_table *port_gid_table; 354 int ret = 0; 355 int hw_update = 0; 356 struct gid_entry *gids = NULL; 357 358 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 359 return -EINVAL; 360 361 if (attr->port_num > MLX4_MAX_PORTS) 362 return -EINVAL; 363 364 port_gid_table = &iboe->gids[attr->port_num - 1]; 365 spin_lock_bh(&iboe->lock); 366 if (ctx) { 367 ctx->refcount--; 368 if (!ctx->refcount) { 369 unsigned int real_index = ctx->real_index; 370 371 free_gid_entry(&port_gid_table->gids[real_index]); 372 hw_update = 1; 373 } 374 } 375 if (!ret && hw_update) { 376 int i; 377 378 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 379 GFP_ATOMIC); 380 if (!gids) { 381 ret = -ENOMEM; 382 } else { 383 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 384 memcpy(&gids[i].gid, 385 &port_gid_table->gids[i].gid, 386 sizeof(union ib_gid)); 387 gids[i].gid_type = 388 port_gid_table->gids[i].gid_type; 389 } 390 } 391 } 392 spin_unlock_bh(&iboe->lock); 393 394 if (!ret && hw_update) { 395 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 396 kfree(gids); 397 } 398 return ret; 399 } 400 401 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 402 const struct ib_gid_attr *attr) 403 { 404 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 405 struct gid_cache_context *ctx = NULL; 406 struct mlx4_port_gid_table *port_gid_table; 407 int real_index = -EINVAL; 408 int i; 409 unsigned long flags; 410 u8 port_num = attr->port_num; 411 412 if (port_num > MLX4_MAX_PORTS) 413 return -EINVAL; 414 415 if (mlx4_is_bonded(ibdev->dev)) 416 port_num = 1; 417 418 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 419 return attr->index; 420 421 spin_lock_irqsave(&iboe->lock, flags); 422 port_gid_table = &iboe->gids[port_num - 1]; 423 424 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 425 if (!memcmp(&port_gid_table->gids[i].gid, 426 &attr->gid, sizeof(attr->gid)) && 427 attr->gid_type == port_gid_table->gids[i].gid_type) { 428 ctx = port_gid_table->gids[i].ctx; 429 break; 430 } 431 if (ctx) 432 real_index = ctx->real_index; 433 spin_unlock_irqrestore(&iboe->lock, flags); 434 return real_index; 435 } 436 437 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 438 sizeof(((type *)0)->fld) <= (sz)) 439 440 static int mlx4_ib_query_device(struct ib_device *ibdev, 441 struct ib_device_attr *props, 442 struct ib_udata *uhw) 443 { 444 struct mlx4_ib_dev *dev = to_mdev(ibdev); 445 struct ib_smp *in_mad = NULL; 446 struct ib_smp *out_mad = NULL; 447 int err; 448 int have_ib_ports; 449 struct mlx4_uverbs_ex_query_device cmd; 450 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 451 struct mlx4_clock_params clock_params; 452 453 if (uhw->inlen) { 454 if (uhw->inlen < sizeof(cmd)) 455 return -EINVAL; 456 457 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 458 if (err) 459 return err; 460 461 if (cmd.comp_mask) 462 return -EINVAL; 463 464 if (cmd.reserved) 465 return -EINVAL; 466 } 467 468 resp.response_length = offsetof(typeof(resp), response_length) + 469 sizeof(resp.response_length); 470 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 471 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 472 err = -ENOMEM; 473 if (!in_mad || !out_mad) 474 goto out; 475 476 init_query_mad(in_mad); 477 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 478 479 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 480 1, NULL, NULL, in_mad, out_mad); 481 if (err) 482 goto out; 483 484 memset(props, 0, sizeof *props); 485 486 have_ib_ports = num_ib_ports(dev->dev); 487 488 props->fw_ver = dev->dev->caps.fw_ver; 489 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 490 IB_DEVICE_PORT_ACTIVE_EVENT | 491 IB_DEVICE_SYS_IMAGE_GUID | 492 IB_DEVICE_RC_RNR_NAK_GEN | 493 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 494 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 495 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 496 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 497 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 498 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 499 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 500 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 501 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 502 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 503 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 504 if (dev->dev->caps.max_gso_sz && 505 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 506 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 507 props->device_cap_flags |= IB_DEVICE_UD_TSO; 508 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 509 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 510 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 511 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 512 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 513 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 514 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 515 props->device_cap_flags |= IB_DEVICE_XRC; 516 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 517 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 518 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 519 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 520 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 521 else 522 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 523 } 524 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 525 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 526 527 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 528 529 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 530 0xffffff; 531 props->vendor_part_id = dev->dev->persist->pdev->device; 532 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 533 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 534 535 props->max_mr_size = ~0ull; 536 props->page_size_cap = dev->dev->caps.page_size_cap; 537 props->max_qp = dev->dev->quotas.qp; 538 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 539 props->max_send_sge = 540 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 541 props->max_recv_sge = 542 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 543 props->max_sge_rd = MLX4_MAX_SGE_RD; 544 props->max_cq = dev->dev->quotas.cq; 545 props->max_cqe = dev->dev->caps.max_cqes; 546 props->max_mr = dev->dev->quotas.mpt; 547 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 548 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 549 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 550 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 551 props->max_srq = dev->dev->quotas.srq; 552 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 553 props->max_srq_sge = dev->dev->caps.max_srq_sge; 554 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 555 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 556 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 557 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 558 props->masked_atomic_cap = props->atomic_cap; 559 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 560 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 561 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 562 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 563 props->max_mcast_grp; 564 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 565 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 566 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 567 props->max_ah = INT_MAX; 568 569 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 570 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 571 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 572 props->rss_caps.max_rwq_indirection_tables = 573 props->max_qp; 574 props->rss_caps.max_rwq_indirection_table_size = 575 dev->dev->caps.max_rss_tbl_sz; 576 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 577 props->max_wq_type_rq = props->max_qp; 578 } 579 580 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 581 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 582 } 583 584 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 585 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 586 587 if (!mlx4_is_slave(dev->dev)) 588 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 589 590 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 591 resp.response_length += sizeof(resp.hca_core_clock_offset); 592 if (!err && !mlx4_is_slave(dev->dev)) { 593 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 594 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 595 } 596 } 597 598 if (uhw->outlen >= resp.response_length + 599 sizeof(resp.max_inl_recv_sz)) { 600 resp.response_length += sizeof(resp.max_inl_recv_sz); 601 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 602 sizeof(struct mlx4_wqe_data_seg); 603 } 604 605 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 606 if (props->rss_caps.supported_qpts) { 607 resp.rss_caps.rx_hash_function = 608 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 609 610 resp.rss_caps.rx_hash_fields_mask = 611 MLX4_IB_RX_HASH_SRC_IPV4 | 612 MLX4_IB_RX_HASH_DST_IPV4 | 613 MLX4_IB_RX_HASH_SRC_IPV6 | 614 MLX4_IB_RX_HASH_DST_IPV6 | 615 MLX4_IB_RX_HASH_SRC_PORT_TCP | 616 MLX4_IB_RX_HASH_DST_PORT_TCP | 617 MLX4_IB_RX_HASH_SRC_PORT_UDP | 618 MLX4_IB_RX_HASH_DST_PORT_UDP; 619 620 if (dev->dev->caps.tunnel_offload_mode == 621 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 622 resp.rss_caps.rx_hash_fields_mask |= 623 MLX4_IB_RX_HASH_INNER; 624 } 625 resp.response_length = offsetof(typeof(resp), rss_caps) + 626 sizeof(resp.rss_caps); 627 } 628 629 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 630 if (dev->dev->caps.max_gso_sz && 631 ((mlx4_ib_port_link_layer(ibdev, 1) == 632 IB_LINK_LAYER_ETHERNET) || 633 (mlx4_ib_port_link_layer(ibdev, 2) == 634 IB_LINK_LAYER_ETHERNET))) { 635 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 636 resp.tso_caps.supported_qpts |= 637 1 << IB_QPT_RAW_PACKET; 638 } 639 resp.response_length = offsetof(typeof(resp), tso_caps) + 640 sizeof(resp.tso_caps); 641 } 642 643 if (uhw->outlen) { 644 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 645 if (err) 646 goto out; 647 } 648 out: 649 kfree(in_mad); 650 kfree(out_mad); 651 652 return err; 653 } 654 655 static enum rdma_link_layer 656 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 657 { 658 struct mlx4_dev *dev = to_mdev(device)->dev; 659 660 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 661 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 662 } 663 664 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 665 struct ib_port_attr *props, int netw_view) 666 { 667 struct ib_smp *in_mad = NULL; 668 struct ib_smp *out_mad = NULL; 669 int ext_active_speed; 670 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 671 int err = -ENOMEM; 672 673 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 674 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 675 if (!in_mad || !out_mad) 676 goto out; 677 678 init_query_mad(in_mad); 679 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 680 in_mad->attr_mod = cpu_to_be32(port); 681 682 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 683 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 684 685 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 686 in_mad, out_mad); 687 if (err) 688 goto out; 689 690 691 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 692 props->lmc = out_mad->data[34] & 0x7; 693 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 694 props->sm_sl = out_mad->data[36] & 0xf; 695 props->state = out_mad->data[32] & 0xf; 696 props->phys_state = out_mad->data[33] >> 4; 697 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 698 if (netw_view) 699 props->gid_tbl_len = out_mad->data[50]; 700 else 701 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 702 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 703 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 704 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 705 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 706 props->active_width = out_mad->data[31] & 0xf; 707 props->active_speed = out_mad->data[35] >> 4; 708 props->max_mtu = out_mad->data[41] & 0xf; 709 props->active_mtu = out_mad->data[36] >> 4; 710 props->subnet_timeout = out_mad->data[51] & 0x1f; 711 props->max_vl_num = out_mad->data[37] >> 4; 712 props->init_type_reply = out_mad->data[41] >> 4; 713 714 /* Check if extended speeds (EDR/FDR/...) are supported */ 715 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 716 ext_active_speed = out_mad->data[62] >> 4; 717 718 switch (ext_active_speed) { 719 case 1: 720 props->active_speed = IB_SPEED_FDR; 721 break; 722 case 2: 723 props->active_speed = IB_SPEED_EDR; 724 break; 725 } 726 } 727 728 /* If reported active speed is QDR, check if is FDR-10 */ 729 if (props->active_speed == IB_SPEED_QDR) { 730 init_query_mad(in_mad); 731 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 732 in_mad->attr_mod = cpu_to_be32(port); 733 734 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 735 NULL, NULL, in_mad, out_mad); 736 if (err) 737 goto out; 738 739 /* Checking LinkSpeedActive for FDR-10 */ 740 if (out_mad->data[15] & 0x1) 741 props->active_speed = IB_SPEED_FDR10; 742 } 743 744 /* Avoid wrong speed value returned by FW if the IB link is down. */ 745 if (props->state == IB_PORT_DOWN) 746 props->active_speed = IB_SPEED_SDR; 747 748 out: 749 kfree(in_mad); 750 kfree(out_mad); 751 return err; 752 } 753 754 static u8 state_to_phys_state(enum ib_port_state state) 755 { 756 return state == IB_PORT_ACTIVE ? 757 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 758 } 759 760 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 761 struct ib_port_attr *props) 762 { 763 764 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 765 struct mlx4_ib_iboe *iboe = &mdev->iboe; 766 struct net_device *ndev; 767 enum ib_mtu tmp; 768 struct mlx4_cmd_mailbox *mailbox; 769 int err = 0; 770 int is_bonded = mlx4_is_bonded(mdev->dev); 771 772 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 773 if (IS_ERR(mailbox)) 774 return PTR_ERR(mailbox); 775 776 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 777 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 778 MLX4_CMD_WRAPPED); 779 if (err) 780 goto out; 781 782 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 783 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 784 IB_WIDTH_4X : IB_WIDTH_1X; 785 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 786 IB_SPEED_FDR : IB_SPEED_QDR; 787 props->port_cap_flags = IB_PORT_CM_SUP; 788 props->ip_gids = true; 789 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 790 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 791 props->pkey_tbl_len = 1; 792 props->max_mtu = IB_MTU_4096; 793 props->max_vl_num = 2; 794 props->state = IB_PORT_DOWN; 795 props->phys_state = state_to_phys_state(props->state); 796 props->active_mtu = IB_MTU_256; 797 spin_lock_bh(&iboe->lock); 798 ndev = iboe->netdevs[port - 1]; 799 if (ndev && is_bonded) { 800 rcu_read_lock(); /* required to get upper dev */ 801 ndev = netdev_master_upper_dev_get_rcu(ndev); 802 rcu_read_unlock(); 803 } 804 if (!ndev) 805 goto out_unlock; 806 807 tmp = iboe_get_mtu(ndev->mtu); 808 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 809 810 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 811 IB_PORT_ACTIVE : IB_PORT_DOWN; 812 props->phys_state = state_to_phys_state(props->state); 813 out_unlock: 814 spin_unlock_bh(&iboe->lock); 815 out: 816 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 817 return err; 818 } 819 820 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 821 struct ib_port_attr *props, int netw_view) 822 { 823 int err; 824 825 /* props being zeroed by the caller, avoid zeroing it here */ 826 827 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 828 ib_link_query_port(ibdev, port, props, netw_view) : 829 eth_link_query_port(ibdev, port, props); 830 831 return err; 832 } 833 834 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 835 struct ib_port_attr *props) 836 { 837 /* returns host view */ 838 return __mlx4_ib_query_port(ibdev, port, props, 0); 839 } 840 841 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 842 union ib_gid *gid, int netw_view) 843 { 844 struct ib_smp *in_mad = NULL; 845 struct ib_smp *out_mad = NULL; 846 int err = -ENOMEM; 847 struct mlx4_ib_dev *dev = to_mdev(ibdev); 848 int clear = 0; 849 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 850 851 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 852 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 853 if (!in_mad || !out_mad) 854 goto out; 855 856 init_query_mad(in_mad); 857 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 858 in_mad->attr_mod = cpu_to_be32(port); 859 860 if (mlx4_is_mfunc(dev->dev) && netw_view) 861 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 862 863 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 864 if (err) 865 goto out; 866 867 memcpy(gid->raw, out_mad->data + 8, 8); 868 869 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 870 if (index) { 871 /* For any index > 0, return the null guid */ 872 err = 0; 873 clear = 1; 874 goto out; 875 } 876 } 877 878 init_query_mad(in_mad); 879 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 880 in_mad->attr_mod = cpu_to_be32(index / 8); 881 882 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 883 NULL, NULL, in_mad, out_mad); 884 if (err) 885 goto out; 886 887 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 888 889 out: 890 if (clear) 891 memset(gid->raw + 8, 0, 8); 892 kfree(in_mad); 893 kfree(out_mad); 894 return err; 895 } 896 897 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 898 union ib_gid *gid) 899 { 900 if (rdma_protocol_ib(ibdev, port)) 901 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 902 return 0; 903 } 904 905 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 906 { 907 union sl2vl_tbl_to_u64 sl2vl64; 908 struct ib_smp *in_mad = NULL; 909 struct ib_smp *out_mad = NULL; 910 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 911 int err = -ENOMEM; 912 int jj; 913 914 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 915 *sl2vl_tbl = 0; 916 return 0; 917 } 918 919 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 920 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 921 if (!in_mad || !out_mad) 922 goto out; 923 924 init_query_mad(in_mad); 925 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 926 in_mad->attr_mod = 0; 927 928 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 929 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 930 931 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 932 in_mad, out_mad); 933 if (err) 934 goto out; 935 936 for (jj = 0; jj < 8; jj++) 937 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 938 *sl2vl_tbl = sl2vl64.sl64; 939 940 out: 941 kfree(in_mad); 942 kfree(out_mad); 943 return err; 944 } 945 946 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 947 { 948 u64 sl2vl; 949 int i; 950 int err; 951 952 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 953 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 954 continue; 955 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 956 if (err) { 957 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 958 i, err); 959 sl2vl = 0; 960 } 961 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 962 } 963 } 964 965 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 966 u16 *pkey, int netw_view) 967 { 968 struct ib_smp *in_mad = NULL; 969 struct ib_smp *out_mad = NULL; 970 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 971 int err = -ENOMEM; 972 973 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 974 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 975 if (!in_mad || !out_mad) 976 goto out; 977 978 init_query_mad(in_mad); 979 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 980 in_mad->attr_mod = cpu_to_be32(index / 32); 981 982 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 983 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 984 985 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 986 in_mad, out_mad); 987 if (err) 988 goto out; 989 990 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 991 992 out: 993 kfree(in_mad); 994 kfree(out_mad); 995 return err; 996 } 997 998 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 999 { 1000 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 1001 } 1002 1003 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 1004 struct ib_device_modify *props) 1005 { 1006 struct mlx4_cmd_mailbox *mailbox; 1007 unsigned long flags; 1008 1009 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1010 return -EOPNOTSUPP; 1011 1012 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1013 return 0; 1014 1015 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 1016 return -EOPNOTSUPP; 1017 1018 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 1019 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1020 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1021 1022 /* 1023 * If possible, pass node desc to FW, so it can generate 1024 * a 144 trap. If cmd fails, just ignore. 1025 */ 1026 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1027 if (IS_ERR(mailbox)) 1028 return 0; 1029 1030 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1031 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1032 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1033 1034 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1035 1036 return 0; 1037 } 1038 1039 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1040 u32 cap_mask) 1041 { 1042 struct mlx4_cmd_mailbox *mailbox; 1043 int err; 1044 1045 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1046 if (IS_ERR(mailbox)) 1047 return PTR_ERR(mailbox); 1048 1049 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1050 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1051 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1052 } else { 1053 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1054 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1055 } 1056 1057 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1058 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1059 MLX4_CMD_WRAPPED); 1060 1061 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1062 return err; 1063 } 1064 1065 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1066 struct ib_port_modify *props) 1067 { 1068 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1069 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1070 struct ib_port_attr attr; 1071 u32 cap_mask; 1072 int err; 1073 1074 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1075 * of whether port link layer is ETH or IB. For ETH ports, qkey 1076 * violations and port capabilities are not meaningful. 1077 */ 1078 if (is_eth) 1079 return 0; 1080 1081 mutex_lock(&mdev->cap_mask_mutex); 1082 1083 err = ib_query_port(ibdev, port, &attr); 1084 if (err) 1085 goto out; 1086 1087 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1088 ~props->clr_port_cap_mask; 1089 1090 err = mlx4_ib_SET_PORT(mdev, port, 1091 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1092 cap_mask); 1093 1094 out: 1095 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1096 return err; 1097 } 1098 1099 static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx, 1100 struct ib_udata *udata) 1101 { 1102 struct ib_device *ibdev = uctx->device; 1103 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1104 struct mlx4_ib_ucontext *context = to_mucontext(uctx); 1105 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1106 struct mlx4_ib_alloc_ucontext_resp resp; 1107 int err; 1108 1109 if (!dev->ib_active) 1110 return -EAGAIN; 1111 1112 if (ibdev->ops.uverbs_abi_ver == 1113 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1114 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1115 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1116 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1117 } else { 1118 resp.dev_caps = dev->dev->caps.userspace_caps; 1119 resp.qp_tab_size = dev->dev->caps.num_qps; 1120 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1121 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1122 resp.cqe_size = dev->dev->caps.cqe_size; 1123 } 1124 1125 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1126 if (err) 1127 return err; 1128 1129 INIT_LIST_HEAD(&context->db_page_list); 1130 mutex_init(&context->db_page_mutex); 1131 1132 INIT_LIST_HEAD(&context->wqn_ranges_list); 1133 mutex_init(&context->wqn_ranges_mutex); 1134 1135 if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1136 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1137 else 1138 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1139 1140 if (err) { 1141 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1142 return -EFAULT; 1143 } 1144 1145 return err; 1146 } 1147 1148 static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1149 { 1150 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1151 1152 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1153 } 1154 1155 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1156 { 1157 } 1158 1159 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1160 { 1161 struct mlx4_ib_dev *dev = to_mdev(context->device); 1162 1163 switch (vma->vm_pgoff) { 1164 case 0: 1165 return rdma_user_mmap_io(context, vma, 1166 to_mucontext(context)->uar.pfn, 1167 PAGE_SIZE, 1168 pgprot_noncached(vma->vm_page_prot), 1169 NULL); 1170 1171 case 1: 1172 if (dev->dev->caps.bf_reg_size == 0) 1173 return -EINVAL; 1174 return rdma_user_mmap_io( 1175 context, vma, 1176 to_mucontext(context)->uar.pfn + 1177 dev->dev->caps.num_uars, 1178 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot), 1179 NULL); 1180 1181 case 3: { 1182 struct mlx4_clock_params params; 1183 int ret; 1184 1185 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1186 if (ret) 1187 return ret; 1188 1189 return rdma_user_mmap_io( 1190 context, vma, 1191 (pci_resource_start(dev->dev->persist->pdev, 1192 params.bar) + 1193 params.offset) >> 1194 PAGE_SHIFT, 1195 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot), 1196 NULL); 1197 } 1198 1199 default: 1200 return -EINVAL; 1201 } 1202 } 1203 1204 static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1205 { 1206 struct mlx4_ib_pd *pd = to_mpd(ibpd); 1207 struct ib_device *ibdev = ibpd->device; 1208 int err; 1209 1210 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1211 if (err) 1212 return err; 1213 1214 if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) { 1215 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1216 return -EFAULT; 1217 } 1218 return 0; 1219 } 1220 1221 static void mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1222 { 1223 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1224 } 1225 1226 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1227 struct ib_udata *udata) 1228 { 1229 struct mlx4_ib_xrcd *xrcd; 1230 struct ib_cq_init_attr cq_attr = {}; 1231 int err; 1232 1233 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1234 return ERR_PTR(-ENOSYS); 1235 1236 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1237 if (!xrcd) 1238 return ERR_PTR(-ENOMEM); 1239 1240 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1241 if (err) 1242 goto err1; 1243 1244 xrcd->pd = ib_alloc_pd(ibdev, 0); 1245 if (IS_ERR(xrcd->pd)) { 1246 err = PTR_ERR(xrcd->pd); 1247 goto err2; 1248 } 1249 1250 cq_attr.cqe = 1; 1251 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1252 if (IS_ERR(xrcd->cq)) { 1253 err = PTR_ERR(xrcd->cq); 1254 goto err3; 1255 } 1256 1257 return &xrcd->ibxrcd; 1258 1259 err3: 1260 ib_dealloc_pd(xrcd->pd); 1261 err2: 1262 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1263 err1: 1264 kfree(xrcd); 1265 return ERR_PTR(err); 1266 } 1267 1268 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 1269 { 1270 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1271 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1272 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1273 kfree(xrcd); 1274 1275 return 0; 1276 } 1277 1278 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1279 { 1280 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1281 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1282 struct mlx4_ib_gid_entry *ge; 1283 1284 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1285 if (!ge) 1286 return -ENOMEM; 1287 1288 ge->gid = *gid; 1289 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1290 ge->port = mqp->port; 1291 ge->added = 1; 1292 } 1293 1294 mutex_lock(&mqp->mutex); 1295 list_add_tail(&ge->list, &mqp->gid_list); 1296 mutex_unlock(&mqp->mutex); 1297 1298 return 0; 1299 } 1300 1301 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1302 struct mlx4_ib_counters *ctr_table) 1303 { 1304 struct counter_index *counter, *tmp_count; 1305 1306 mutex_lock(&ctr_table->mutex); 1307 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1308 list) { 1309 if (counter->allocated) 1310 mlx4_counter_free(ibdev->dev, counter->index); 1311 list_del(&counter->list); 1312 kfree(counter); 1313 } 1314 mutex_unlock(&ctr_table->mutex); 1315 } 1316 1317 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1318 union ib_gid *gid) 1319 { 1320 struct net_device *ndev; 1321 int ret = 0; 1322 1323 if (!mqp->port) 1324 return 0; 1325 1326 spin_lock_bh(&mdev->iboe.lock); 1327 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1328 if (ndev) 1329 dev_hold(ndev); 1330 spin_unlock_bh(&mdev->iboe.lock); 1331 1332 if (ndev) { 1333 ret = 1; 1334 dev_put(ndev); 1335 } 1336 1337 return ret; 1338 } 1339 1340 struct mlx4_ib_steering { 1341 struct list_head list; 1342 struct mlx4_flow_reg_id reg_id; 1343 union ib_gid gid; 1344 }; 1345 1346 #define LAST_ETH_FIELD vlan_tag 1347 #define LAST_IB_FIELD sl 1348 #define LAST_IPV4_FIELD dst_ip 1349 #define LAST_TCP_UDP_FIELD src_port 1350 1351 /* Field is the last supported field */ 1352 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1353 memchr_inv((void *)&filter.field +\ 1354 sizeof(filter.field), 0,\ 1355 sizeof(filter) -\ 1356 offsetof(typeof(filter), field) -\ 1357 sizeof(filter.field)) 1358 1359 static int parse_flow_attr(struct mlx4_dev *dev, 1360 u32 qp_num, 1361 union ib_flow_spec *ib_spec, 1362 struct _rule_hw *mlx4_spec) 1363 { 1364 enum mlx4_net_trans_rule_id type; 1365 1366 switch (ib_spec->type) { 1367 case IB_FLOW_SPEC_ETH: 1368 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1369 return -ENOTSUPP; 1370 1371 type = MLX4_NET_TRANS_RULE_ID_ETH; 1372 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1373 ETH_ALEN); 1374 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1375 ETH_ALEN); 1376 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1377 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1378 break; 1379 case IB_FLOW_SPEC_IB: 1380 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1381 return -ENOTSUPP; 1382 1383 type = MLX4_NET_TRANS_RULE_ID_IB; 1384 mlx4_spec->ib.l3_qpn = 1385 cpu_to_be32(qp_num); 1386 mlx4_spec->ib.qpn_mask = 1387 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1388 break; 1389 1390 1391 case IB_FLOW_SPEC_IPV4: 1392 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1393 return -ENOTSUPP; 1394 1395 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1396 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1397 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1398 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1399 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1400 break; 1401 1402 case IB_FLOW_SPEC_TCP: 1403 case IB_FLOW_SPEC_UDP: 1404 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1405 return -ENOTSUPP; 1406 1407 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1408 MLX4_NET_TRANS_RULE_ID_TCP : 1409 MLX4_NET_TRANS_RULE_ID_UDP; 1410 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1411 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1412 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1413 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1414 break; 1415 1416 default: 1417 return -EINVAL; 1418 } 1419 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1420 mlx4_hw_rule_sz(dev, type) < 0) 1421 return -EINVAL; 1422 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1423 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1424 return mlx4_hw_rule_sz(dev, type); 1425 } 1426 1427 struct default_rules { 1428 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1429 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1430 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1431 __u8 link_layer; 1432 }; 1433 static const struct default_rules default_table[] = { 1434 { 1435 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1436 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1437 .rules_create_list = {IB_FLOW_SPEC_IB}, 1438 .link_layer = IB_LINK_LAYER_INFINIBAND 1439 } 1440 }; 1441 1442 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1443 struct ib_flow_attr *flow_attr) 1444 { 1445 int i, j, k; 1446 void *ib_flow; 1447 const struct default_rules *pdefault_rules = default_table; 1448 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1449 1450 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1451 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1452 memset(&field_types, 0, sizeof(field_types)); 1453 1454 if (link_layer != pdefault_rules->link_layer) 1455 continue; 1456 1457 ib_flow = flow_attr + 1; 1458 /* we assume the specs are sorted */ 1459 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1460 j < flow_attr->num_of_specs; k++) { 1461 union ib_flow_spec *current_flow = 1462 (union ib_flow_spec *)ib_flow; 1463 1464 /* same layer but different type */ 1465 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1466 (pdefault_rules->mandatory_fields[k] & 1467 IB_FLOW_SPEC_LAYER_MASK)) && 1468 (current_flow->type != 1469 pdefault_rules->mandatory_fields[k])) 1470 goto out; 1471 1472 /* same layer, try match next one */ 1473 if (current_flow->type == 1474 pdefault_rules->mandatory_fields[k]) { 1475 j++; 1476 ib_flow += 1477 ((union ib_flow_spec *)ib_flow)->size; 1478 } 1479 } 1480 1481 ib_flow = flow_attr + 1; 1482 for (j = 0; j < flow_attr->num_of_specs; 1483 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1484 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1485 /* same layer and same type */ 1486 if (((union ib_flow_spec *)ib_flow)->type == 1487 pdefault_rules->mandatory_not_fields[k]) 1488 goto out; 1489 1490 return i; 1491 } 1492 out: 1493 return -1; 1494 } 1495 1496 static int __mlx4_ib_create_default_rules( 1497 struct mlx4_ib_dev *mdev, 1498 struct ib_qp *qp, 1499 const struct default_rules *pdefault_rules, 1500 struct _rule_hw *mlx4_spec) { 1501 int size = 0; 1502 int i; 1503 1504 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1505 int ret; 1506 union ib_flow_spec ib_spec; 1507 switch (pdefault_rules->rules_create_list[i]) { 1508 case 0: 1509 /* no rule */ 1510 continue; 1511 case IB_FLOW_SPEC_IB: 1512 ib_spec.type = IB_FLOW_SPEC_IB; 1513 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1514 1515 break; 1516 default: 1517 /* invalid rule */ 1518 return -EINVAL; 1519 } 1520 /* We must put empty rule, qpn is being ignored */ 1521 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1522 mlx4_spec); 1523 if (ret < 0) { 1524 pr_info("invalid parsing\n"); 1525 return -EINVAL; 1526 } 1527 1528 mlx4_spec = (void *)mlx4_spec + ret; 1529 size += ret; 1530 } 1531 return size; 1532 } 1533 1534 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1535 int domain, 1536 enum mlx4_net_trans_promisc_mode flow_type, 1537 u64 *reg_id) 1538 { 1539 int ret, i; 1540 int size = 0; 1541 void *ib_flow; 1542 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1543 struct mlx4_cmd_mailbox *mailbox; 1544 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1545 int default_flow; 1546 1547 static const u16 __mlx4_domain[] = { 1548 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1549 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1550 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1551 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1552 }; 1553 1554 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1555 pr_err("Invalid priority value %d\n", flow_attr->priority); 1556 return -EINVAL; 1557 } 1558 1559 if (domain >= IB_FLOW_DOMAIN_NUM) { 1560 pr_err("Invalid domain value %d\n", domain); 1561 return -EINVAL; 1562 } 1563 1564 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1565 return -EINVAL; 1566 1567 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1568 if (IS_ERR(mailbox)) 1569 return PTR_ERR(mailbox); 1570 ctrl = mailbox->buf; 1571 1572 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1573 flow_attr->priority); 1574 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1575 ctrl->port = flow_attr->port; 1576 ctrl->qpn = cpu_to_be32(qp->qp_num); 1577 1578 ib_flow = flow_attr + 1; 1579 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1580 /* Add default flows */ 1581 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1582 if (default_flow >= 0) { 1583 ret = __mlx4_ib_create_default_rules( 1584 mdev, qp, default_table + default_flow, 1585 mailbox->buf + size); 1586 if (ret < 0) { 1587 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1588 return -EINVAL; 1589 } 1590 size += ret; 1591 } 1592 for (i = 0; i < flow_attr->num_of_specs; i++) { 1593 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1594 mailbox->buf + size); 1595 if (ret < 0) { 1596 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1597 return -EINVAL; 1598 } 1599 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1600 size += ret; 1601 } 1602 1603 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1604 flow_attr->num_of_specs == 1) { 1605 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1606 enum ib_flow_spec_type header_spec = 1607 ((union ib_flow_spec *)(flow_attr + 1))->type; 1608 1609 if (header_spec == IB_FLOW_SPEC_ETH) 1610 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1611 } 1612 1613 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1614 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1615 MLX4_CMD_NATIVE); 1616 if (ret == -ENOMEM) 1617 pr_err("mcg table is full. Fail to register network rule.\n"); 1618 else if (ret == -ENXIO) 1619 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1620 else if (ret) 1621 pr_err("Invalid argument. Fail to register network rule.\n"); 1622 1623 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1624 return ret; 1625 } 1626 1627 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1628 { 1629 int err; 1630 err = mlx4_cmd(dev, reg_id, 0, 0, 1631 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1632 MLX4_CMD_NATIVE); 1633 if (err) 1634 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1635 reg_id); 1636 return err; 1637 } 1638 1639 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1640 u64 *reg_id) 1641 { 1642 void *ib_flow; 1643 union ib_flow_spec *ib_spec; 1644 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1645 int err = 0; 1646 1647 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1648 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1649 return 0; /* do nothing */ 1650 1651 ib_flow = flow_attr + 1; 1652 ib_spec = (union ib_flow_spec *)ib_flow; 1653 1654 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1655 return 0; /* do nothing */ 1656 1657 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1658 flow_attr->port, qp->qp_num, 1659 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1660 reg_id); 1661 return err; 1662 } 1663 1664 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1665 struct ib_flow_attr *flow_attr, 1666 enum mlx4_net_trans_promisc_mode *type) 1667 { 1668 int err = 0; 1669 1670 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1671 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1672 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1673 return -EOPNOTSUPP; 1674 } 1675 1676 if (flow_attr->num_of_specs == 0) { 1677 type[0] = MLX4_FS_MC_SNIFFER; 1678 type[1] = MLX4_FS_UC_SNIFFER; 1679 } else { 1680 union ib_flow_spec *ib_spec; 1681 1682 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1683 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1684 return -EINVAL; 1685 1686 /* if all is zero than MC and UC */ 1687 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1688 type[0] = MLX4_FS_MC_SNIFFER; 1689 type[1] = MLX4_FS_UC_SNIFFER; 1690 } else { 1691 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1692 ib_spec->eth.mask.dst_mac[1], 1693 ib_spec->eth.mask.dst_mac[2], 1694 ib_spec->eth.mask.dst_mac[3], 1695 ib_spec->eth.mask.dst_mac[4], 1696 ib_spec->eth.mask.dst_mac[5]}; 1697 1698 /* Above xor was only on MC bit, non empty mask is valid 1699 * only if this bit is set and rest are zero. 1700 */ 1701 if (!is_zero_ether_addr(&mac[0])) 1702 return -EINVAL; 1703 1704 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1705 type[0] = MLX4_FS_MC_SNIFFER; 1706 else 1707 type[0] = MLX4_FS_UC_SNIFFER; 1708 } 1709 } 1710 1711 return err; 1712 } 1713 1714 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1715 struct ib_flow_attr *flow_attr, 1716 int domain, struct ib_udata *udata) 1717 { 1718 int err = 0, i = 0, j = 0; 1719 struct mlx4_ib_flow *mflow; 1720 enum mlx4_net_trans_promisc_mode type[2]; 1721 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1722 int is_bonded = mlx4_is_bonded(dev); 1723 1724 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1725 return ERR_PTR(-EINVAL); 1726 1727 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1728 return ERR_PTR(-EOPNOTSUPP); 1729 1730 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1731 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1732 return ERR_PTR(-EOPNOTSUPP); 1733 1734 if (udata && 1735 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1736 return ERR_PTR(-EOPNOTSUPP); 1737 1738 memset(type, 0, sizeof(type)); 1739 1740 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1741 if (!mflow) { 1742 err = -ENOMEM; 1743 goto err_free; 1744 } 1745 1746 switch (flow_attr->type) { 1747 case IB_FLOW_ATTR_NORMAL: 1748 /* If dont trap flag (continue match) is set, under specific 1749 * condition traffic be replicated to given qp, 1750 * without stealing it 1751 */ 1752 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1753 err = mlx4_ib_add_dont_trap_rule(dev, 1754 flow_attr, 1755 type); 1756 if (err) 1757 goto err_free; 1758 } else { 1759 type[0] = MLX4_FS_REGULAR; 1760 } 1761 break; 1762 1763 case IB_FLOW_ATTR_ALL_DEFAULT: 1764 type[0] = MLX4_FS_ALL_DEFAULT; 1765 break; 1766 1767 case IB_FLOW_ATTR_MC_DEFAULT: 1768 type[0] = MLX4_FS_MC_DEFAULT; 1769 break; 1770 1771 case IB_FLOW_ATTR_SNIFFER: 1772 type[0] = MLX4_FS_MIRROR_RX_PORT; 1773 type[1] = MLX4_FS_MIRROR_SX_PORT; 1774 break; 1775 1776 default: 1777 err = -EINVAL; 1778 goto err_free; 1779 } 1780 1781 while (i < ARRAY_SIZE(type) && type[i]) { 1782 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1783 &mflow->reg_id[i].id); 1784 if (err) 1785 goto err_create_flow; 1786 if (is_bonded) { 1787 /* Application always sees one port so the mirror rule 1788 * must be on port #2 1789 */ 1790 flow_attr->port = 2; 1791 err = __mlx4_ib_create_flow(qp, flow_attr, 1792 domain, type[j], 1793 &mflow->reg_id[j].mirror); 1794 flow_attr->port = 1; 1795 if (err) 1796 goto err_create_flow; 1797 j++; 1798 } 1799 1800 i++; 1801 } 1802 1803 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1804 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1805 &mflow->reg_id[i].id); 1806 if (err) 1807 goto err_create_flow; 1808 1809 if (is_bonded) { 1810 flow_attr->port = 2; 1811 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1812 &mflow->reg_id[j].mirror); 1813 flow_attr->port = 1; 1814 if (err) 1815 goto err_create_flow; 1816 j++; 1817 } 1818 /* function to create mirror rule */ 1819 i++; 1820 } 1821 1822 return &mflow->ibflow; 1823 1824 err_create_flow: 1825 while (i) { 1826 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1827 mflow->reg_id[i].id); 1828 i--; 1829 } 1830 1831 while (j) { 1832 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1833 mflow->reg_id[j].mirror); 1834 j--; 1835 } 1836 err_free: 1837 kfree(mflow); 1838 return ERR_PTR(err); 1839 } 1840 1841 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1842 { 1843 int err, ret = 0; 1844 int i = 0; 1845 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1846 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1847 1848 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1849 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1850 if (err) 1851 ret = err; 1852 if (mflow->reg_id[i].mirror) { 1853 err = __mlx4_ib_destroy_flow(mdev->dev, 1854 mflow->reg_id[i].mirror); 1855 if (err) 1856 ret = err; 1857 } 1858 i++; 1859 } 1860 1861 kfree(mflow); 1862 return ret; 1863 } 1864 1865 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1866 { 1867 int err; 1868 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1869 struct mlx4_dev *dev = mdev->dev; 1870 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1871 struct mlx4_ib_steering *ib_steering = NULL; 1872 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1873 struct mlx4_flow_reg_id reg_id; 1874 1875 if (mdev->dev->caps.steering_mode == 1876 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1877 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1878 if (!ib_steering) 1879 return -ENOMEM; 1880 } 1881 1882 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1883 !!(mqp->flags & 1884 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1885 prot, ®_id.id); 1886 if (err) { 1887 pr_err("multicast attach op failed, err %d\n", err); 1888 goto err_malloc; 1889 } 1890 1891 reg_id.mirror = 0; 1892 if (mlx4_is_bonded(dev)) { 1893 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1894 (mqp->port == 1) ? 2 : 1, 1895 !!(mqp->flags & 1896 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1897 prot, ®_id.mirror); 1898 if (err) 1899 goto err_add; 1900 } 1901 1902 err = add_gid_entry(ibqp, gid); 1903 if (err) 1904 goto err_add; 1905 1906 if (ib_steering) { 1907 memcpy(ib_steering->gid.raw, gid->raw, 16); 1908 ib_steering->reg_id = reg_id; 1909 mutex_lock(&mqp->mutex); 1910 list_add(&ib_steering->list, &mqp->steering_rules); 1911 mutex_unlock(&mqp->mutex); 1912 } 1913 return 0; 1914 1915 err_add: 1916 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1917 prot, reg_id.id); 1918 if (reg_id.mirror) 1919 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1920 prot, reg_id.mirror); 1921 err_malloc: 1922 kfree(ib_steering); 1923 1924 return err; 1925 } 1926 1927 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 1928 { 1929 struct mlx4_ib_gid_entry *ge; 1930 struct mlx4_ib_gid_entry *tmp; 1931 struct mlx4_ib_gid_entry *ret = NULL; 1932 1933 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1934 if (!memcmp(raw, ge->gid.raw, 16)) { 1935 ret = ge; 1936 break; 1937 } 1938 } 1939 1940 return ret; 1941 } 1942 1943 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1944 { 1945 int err; 1946 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1947 struct mlx4_dev *dev = mdev->dev; 1948 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1949 struct net_device *ndev; 1950 struct mlx4_ib_gid_entry *ge; 1951 struct mlx4_flow_reg_id reg_id = {0, 0}; 1952 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1953 1954 if (mdev->dev->caps.steering_mode == 1955 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1956 struct mlx4_ib_steering *ib_steering; 1957 1958 mutex_lock(&mqp->mutex); 1959 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 1960 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 1961 list_del(&ib_steering->list); 1962 break; 1963 } 1964 } 1965 mutex_unlock(&mqp->mutex); 1966 if (&ib_steering->list == &mqp->steering_rules) { 1967 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 1968 return -EINVAL; 1969 } 1970 reg_id = ib_steering->reg_id; 1971 kfree(ib_steering); 1972 } 1973 1974 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1975 prot, reg_id.id); 1976 if (err) 1977 return err; 1978 1979 if (mlx4_is_bonded(dev)) { 1980 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1981 prot, reg_id.mirror); 1982 if (err) 1983 return err; 1984 } 1985 1986 mutex_lock(&mqp->mutex); 1987 ge = find_gid_entry(mqp, gid->raw); 1988 if (ge) { 1989 spin_lock_bh(&mdev->iboe.lock); 1990 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 1991 if (ndev) 1992 dev_hold(ndev); 1993 spin_unlock_bh(&mdev->iboe.lock); 1994 if (ndev) 1995 dev_put(ndev); 1996 list_del(&ge->list); 1997 kfree(ge); 1998 } else 1999 pr_warn("could not find mgid entry\n"); 2000 2001 mutex_unlock(&mqp->mutex); 2002 2003 return 0; 2004 } 2005 2006 static int init_node_data(struct mlx4_ib_dev *dev) 2007 { 2008 struct ib_smp *in_mad = NULL; 2009 struct ib_smp *out_mad = NULL; 2010 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2011 int err = -ENOMEM; 2012 2013 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2014 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2015 if (!in_mad || !out_mad) 2016 goto out; 2017 2018 init_query_mad(in_mad); 2019 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2020 if (mlx4_is_master(dev->dev)) 2021 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2022 2023 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2024 if (err) 2025 goto out; 2026 2027 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2028 2029 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2030 2031 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2032 if (err) 2033 goto out; 2034 2035 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2036 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2037 2038 out: 2039 kfree(in_mad); 2040 kfree(out_mad); 2041 return err; 2042 } 2043 2044 static ssize_t hca_type_show(struct device *device, 2045 struct device_attribute *attr, char *buf) 2046 { 2047 struct mlx4_ib_dev *dev = 2048 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2049 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2050 } 2051 static DEVICE_ATTR_RO(hca_type); 2052 2053 static ssize_t hw_rev_show(struct device *device, 2054 struct device_attribute *attr, char *buf) 2055 { 2056 struct mlx4_ib_dev *dev = 2057 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2058 return sprintf(buf, "%x\n", dev->dev->rev_id); 2059 } 2060 static DEVICE_ATTR_RO(hw_rev); 2061 2062 static ssize_t board_id_show(struct device *device, 2063 struct device_attribute *attr, char *buf) 2064 { 2065 struct mlx4_ib_dev *dev = 2066 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2067 2068 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2069 dev->dev->board_id); 2070 } 2071 static DEVICE_ATTR_RO(board_id); 2072 2073 static struct attribute *mlx4_class_attributes[] = { 2074 &dev_attr_hw_rev.attr, 2075 &dev_attr_hca_type.attr, 2076 &dev_attr_board_id.attr, 2077 NULL 2078 }; 2079 2080 static const struct attribute_group mlx4_attr_group = { 2081 .attrs = mlx4_class_attributes, 2082 }; 2083 2084 struct diag_counter { 2085 const char *name; 2086 u32 offset; 2087 }; 2088 2089 #define DIAG_COUNTER(_name, _offset) \ 2090 { .name = #_name, .offset = _offset } 2091 2092 static const struct diag_counter diag_basic[] = { 2093 DIAG_COUNTER(rq_num_lle, 0x00), 2094 DIAG_COUNTER(sq_num_lle, 0x04), 2095 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2096 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2097 DIAG_COUNTER(rq_num_lpe, 0x18), 2098 DIAG_COUNTER(sq_num_lpe, 0x1C), 2099 DIAG_COUNTER(rq_num_wrfe, 0x20), 2100 DIAG_COUNTER(sq_num_wrfe, 0x24), 2101 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2102 DIAG_COUNTER(sq_num_bre, 0x34), 2103 DIAG_COUNTER(sq_num_rire, 0x44), 2104 DIAG_COUNTER(rq_num_rire, 0x48), 2105 DIAG_COUNTER(sq_num_rae, 0x4C), 2106 DIAG_COUNTER(rq_num_rae, 0x50), 2107 DIAG_COUNTER(sq_num_roe, 0x54), 2108 DIAG_COUNTER(sq_num_tree, 0x5C), 2109 DIAG_COUNTER(sq_num_rree, 0x64), 2110 DIAG_COUNTER(rq_num_rnr, 0x68), 2111 DIAG_COUNTER(sq_num_rnr, 0x6C), 2112 DIAG_COUNTER(rq_num_oos, 0x100), 2113 DIAG_COUNTER(sq_num_oos, 0x104), 2114 }; 2115 2116 static const struct diag_counter diag_ext[] = { 2117 DIAG_COUNTER(rq_num_dup, 0x130), 2118 DIAG_COUNTER(sq_num_to, 0x134), 2119 }; 2120 2121 static const struct diag_counter diag_device_only[] = { 2122 DIAG_COUNTER(num_cqovf, 0x1A0), 2123 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2124 }; 2125 2126 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2127 u8 port_num) 2128 { 2129 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2130 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2131 2132 if (!diag[!!port_num].name) 2133 return NULL; 2134 2135 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2136 diag[!!port_num].num_counters, 2137 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2138 } 2139 2140 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2141 struct rdma_hw_stats *stats, 2142 u8 port, int index) 2143 { 2144 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2145 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2146 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2147 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2148 int ret; 2149 int i; 2150 2151 ret = mlx4_query_diag_counters(dev->dev, 2152 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2153 diag[!!port].offset, hw_value, 2154 diag[!!port].num_counters, port); 2155 2156 if (ret) 2157 return ret; 2158 2159 for (i = 0; i < diag[!!port].num_counters; i++) 2160 stats->value[i] = hw_value[i]; 2161 2162 return diag[!!port].num_counters; 2163 } 2164 2165 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2166 const char ***name, 2167 u32 **offset, 2168 u32 *num, 2169 bool port) 2170 { 2171 u32 num_counters; 2172 2173 num_counters = ARRAY_SIZE(diag_basic); 2174 2175 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2176 num_counters += ARRAY_SIZE(diag_ext); 2177 2178 if (!port) 2179 num_counters += ARRAY_SIZE(diag_device_only); 2180 2181 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2182 if (!*name) 2183 return -ENOMEM; 2184 2185 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2186 if (!*offset) 2187 goto err_name; 2188 2189 *num = num_counters; 2190 2191 return 0; 2192 2193 err_name: 2194 kfree(*name); 2195 return -ENOMEM; 2196 } 2197 2198 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2199 const char **name, 2200 u32 *offset, 2201 bool port) 2202 { 2203 int i; 2204 int j; 2205 2206 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2207 name[i] = diag_basic[i].name; 2208 offset[i] = diag_basic[i].offset; 2209 } 2210 2211 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2212 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2213 name[j] = diag_ext[i].name; 2214 offset[j] = diag_ext[i].offset; 2215 } 2216 } 2217 2218 if (!port) { 2219 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2220 name[j] = diag_device_only[i].name; 2221 offset[j] = diag_device_only[i].offset; 2222 } 2223 } 2224 } 2225 2226 static const struct ib_device_ops mlx4_ib_hw_stats_ops = { 2227 .alloc_hw_stats = mlx4_ib_alloc_hw_stats, 2228 .get_hw_stats = mlx4_ib_get_hw_stats, 2229 }; 2230 2231 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2232 { 2233 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2234 int i; 2235 int ret; 2236 bool per_port = !!(ibdev->dev->caps.flags2 & 2237 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2238 2239 if (mlx4_is_slave(ibdev->dev)) 2240 return 0; 2241 2242 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2243 /* i == 1 means we are building port counters */ 2244 if (i && !per_port) 2245 continue; 2246 2247 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2248 &diag[i].offset, 2249 &diag[i].num_counters, i); 2250 if (ret) 2251 goto err_alloc; 2252 2253 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2254 diag[i].offset, i); 2255 } 2256 2257 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops); 2258 2259 return 0; 2260 2261 err_alloc: 2262 if (i) { 2263 kfree(diag[i - 1].name); 2264 kfree(diag[i - 1].offset); 2265 } 2266 2267 return ret; 2268 } 2269 2270 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2271 { 2272 int i; 2273 2274 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2275 kfree(ibdev->diag_counters[i].offset); 2276 kfree(ibdev->diag_counters[i].name); 2277 } 2278 } 2279 2280 #define MLX4_IB_INVALID_MAC ((u64)-1) 2281 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2282 struct net_device *dev, 2283 int port) 2284 { 2285 u64 new_smac = 0; 2286 u64 release_mac = MLX4_IB_INVALID_MAC; 2287 struct mlx4_ib_qp *qp; 2288 2289 read_lock(&dev_base_lock); 2290 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2291 read_unlock(&dev_base_lock); 2292 2293 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2294 2295 /* no need for update QP1 and mac registration in non-SRIOV */ 2296 if (!mlx4_is_mfunc(ibdev->dev)) 2297 return; 2298 2299 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2300 qp = ibdev->qp1_proxy[port - 1]; 2301 if (qp) { 2302 int new_smac_index; 2303 u64 old_smac; 2304 struct mlx4_update_qp_params update_params; 2305 2306 mutex_lock(&qp->mutex); 2307 old_smac = qp->pri.smac; 2308 if (new_smac == old_smac) 2309 goto unlock; 2310 2311 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2312 2313 if (new_smac_index < 0) 2314 goto unlock; 2315 2316 update_params.smac_index = new_smac_index; 2317 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2318 &update_params)) { 2319 release_mac = new_smac; 2320 goto unlock; 2321 } 2322 /* if old port was zero, no mac was yet registered for this QP */ 2323 if (qp->pri.smac_port) 2324 release_mac = old_smac; 2325 qp->pri.smac = new_smac; 2326 qp->pri.smac_port = port; 2327 qp->pri.smac_index = new_smac_index; 2328 } 2329 2330 unlock: 2331 if (release_mac != MLX4_IB_INVALID_MAC) 2332 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2333 if (qp) 2334 mutex_unlock(&qp->mutex); 2335 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2336 } 2337 2338 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2339 struct net_device *dev, 2340 unsigned long event) 2341 2342 { 2343 struct mlx4_ib_iboe *iboe; 2344 int update_qps_port = -1; 2345 int port; 2346 2347 ASSERT_RTNL(); 2348 2349 iboe = &ibdev->iboe; 2350 2351 spin_lock_bh(&iboe->lock); 2352 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2353 2354 iboe->netdevs[port - 1] = 2355 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2356 2357 if (dev == iboe->netdevs[port - 1] && 2358 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2359 event == NETDEV_UP || event == NETDEV_CHANGE)) 2360 update_qps_port = port; 2361 2362 if (dev == iboe->netdevs[port - 1] && 2363 (event == NETDEV_UP || event == NETDEV_DOWN)) { 2364 enum ib_port_state port_state; 2365 struct ib_event ibev = { }; 2366 2367 if (ib_get_cached_port_state(&ibdev->ib_dev, port, 2368 &port_state)) 2369 continue; 2370 2371 if (event == NETDEV_UP && 2372 (port_state != IB_PORT_ACTIVE || 2373 iboe->last_port_state[port - 1] != IB_PORT_DOWN)) 2374 continue; 2375 if (event == NETDEV_DOWN && 2376 (port_state != IB_PORT_DOWN || 2377 iboe->last_port_state[port - 1] != IB_PORT_ACTIVE)) 2378 continue; 2379 iboe->last_port_state[port - 1] = port_state; 2380 2381 ibev.device = &ibdev->ib_dev; 2382 ibev.element.port_num = port; 2383 ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE : 2384 IB_EVENT_PORT_ERR; 2385 ib_dispatch_event(&ibev); 2386 } 2387 2388 } 2389 spin_unlock_bh(&iboe->lock); 2390 2391 if (update_qps_port > 0) 2392 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2393 } 2394 2395 static int mlx4_ib_netdev_event(struct notifier_block *this, 2396 unsigned long event, void *ptr) 2397 { 2398 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2399 struct mlx4_ib_dev *ibdev; 2400 2401 if (!net_eq(dev_net(dev), &init_net)) 2402 return NOTIFY_DONE; 2403 2404 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2405 mlx4_ib_scan_netdevs(ibdev, dev, event); 2406 2407 return NOTIFY_DONE; 2408 } 2409 2410 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2411 { 2412 int port; 2413 int slave; 2414 int i; 2415 2416 if (mlx4_is_master(ibdev->dev)) { 2417 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2418 ++slave) { 2419 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2420 for (i = 0; 2421 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2422 ++i) { 2423 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2424 /* master has the identity virt2phys pkey mapping */ 2425 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2426 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2427 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2428 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2429 } 2430 } 2431 } 2432 /* initialize pkey cache */ 2433 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2434 for (i = 0; 2435 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2436 ++i) 2437 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2438 (i) ? 0 : 0xFFFF; 2439 } 2440 } 2441 } 2442 2443 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2444 { 2445 int i, j, eq = 0, total_eqs = 0; 2446 2447 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2448 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2449 if (!ibdev->eq_table) 2450 return; 2451 2452 for (i = 1; i <= dev->caps.num_ports; i++) { 2453 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2454 j++, total_eqs++) { 2455 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2456 continue; 2457 ibdev->eq_table[eq] = total_eqs; 2458 if (!mlx4_assign_eq(dev, i, 2459 &ibdev->eq_table[eq])) 2460 eq++; 2461 else 2462 ibdev->eq_table[eq] = -1; 2463 } 2464 } 2465 2466 for (i = eq; i < dev->caps.num_comp_vectors; 2467 ibdev->eq_table[i++] = -1) 2468 ; 2469 2470 /* Advertise the new number of EQs to clients */ 2471 ibdev->ib_dev.num_comp_vectors = eq; 2472 } 2473 2474 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2475 { 2476 int i; 2477 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2478 2479 /* no eqs were allocated */ 2480 if (!ibdev->eq_table) 2481 return; 2482 2483 /* Reset the advertised EQ number */ 2484 ibdev->ib_dev.num_comp_vectors = 0; 2485 2486 for (i = 0; i < total_eqs; i++) 2487 mlx4_release_eq(dev, ibdev->eq_table[i]); 2488 2489 kfree(ibdev->eq_table); 2490 ibdev->eq_table = NULL; 2491 } 2492 2493 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2494 struct ib_port_immutable *immutable) 2495 { 2496 struct ib_port_attr attr; 2497 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2498 int err; 2499 2500 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2501 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2502 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2503 } else { 2504 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2505 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2506 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2507 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2508 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2509 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2510 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2511 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2512 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2513 } 2514 2515 err = ib_query_port(ibdev, port_num, &attr); 2516 if (err) 2517 return err; 2518 2519 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2520 immutable->gid_tbl_len = attr.gid_tbl_len; 2521 2522 return 0; 2523 } 2524 2525 static void get_fw_ver_str(struct ib_device *device, char *str) 2526 { 2527 struct mlx4_ib_dev *dev = 2528 container_of(device, struct mlx4_ib_dev, ib_dev); 2529 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2530 (int) (dev->dev->caps.fw_ver >> 32), 2531 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2532 (int) dev->dev->caps.fw_ver & 0xffff); 2533 } 2534 2535 static const struct ib_device_ops mlx4_ib_dev_ops = { 2536 .owner = THIS_MODULE, 2537 .driver_id = RDMA_DRIVER_MLX4, 2538 .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION, 2539 2540 .add_gid = mlx4_ib_add_gid, 2541 .alloc_mr = mlx4_ib_alloc_mr, 2542 .alloc_pd = mlx4_ib_alloc_pd, 2543 .alloc_ucontext = mlx4_ib_alloc_ucontext, 2544 .attach_mcast = mlx4_ib_mcg_attach, 2545 .create_ah = mlx4_ib_create_ah, 2546 .create_cq = mlx4_ib_create_cq, 2547 .create_qp = mlx4_ib_create_qp, 2548 .create_srq = mlx4_ib_create_srq, 2549 .dealloc_pd = mlx4_ib_dealloc_pd, 2550 .dealloc_ucontext = mlx4_ib_dealloc_ucontext, 2551 .del_gid = mlx4_ib_del_gid, 2552 .dereg_mr = mlx4_ib_dereg_mr, 2553 .destroy_ah = mlx4_ib_destroy_ah, 2554 .destroy_cq = mlx4_ib_destroy_cq, 2555 .destroy_qp = mlx4_ib_destroy_qp, 2556 .destroy_srq = mlx4_ib_destroy_srq, 2557 .detach_mcast = mlx4_ib_mcg_detach, 2558 .disassociate_ucontext = mlx4_ib_disassociate_ucontext, 2559 .drain_rq = mlx4_ib_drain_rq, 2560 .drain_sq = mlx4_ib_drain_sq, 2561 .get_dev_fw_str = get_fw_ver_str, 2562 .get_dma_mr = mlx4_ib_get_dma_mr, 2563 .get_link_layer = mlx4_ib_port_link_layer, 2564 .get_netdev = mlx4_ib_get_netdev, 2565 .get_port_immutable = mlx4_port_immutable, 2566 .map_mr_sg = mlx4_ib_map_mr_sg, 2567 .mmap = mlx4_ib_mmap, 2568 .modify_cq = mlx4_ib_modify_cq, 2569 .modify_device = mlx4_ib_modify_device, 2570 .modify_port = mlx4_ib_modify_port, 2571 .modify_qp = mlx4_ib_modify_qp, 2572 .modify_srq = mlx4_ib_modify_srq, 2573 .poll_cq = mlx4_ib_poll_cq, 2574 .post_recv = mlx4_ib_post_recv, 2575 .post_send = mlx4_ib_post_send, 2576 .post_srq_recv = mlx4_ib_post_srq_recv, 2577 .process_mad = mlx4_ib_process_mad, 2578 .query_ah = mlx4_ib_query_ah, 2579 .query_device = mlx4_ib_query_device, 2580 .query_gid = mlx4_ib_query_gid, 2581 .query_pkey = mlx4_ib_query_pkey, 2582 .query_port = mlx4_ib_query_port, 2583 .query_qp = mlx4_ib_query_qp, 2584 .query_srq = mlx4_ib_query_srq, 2585 .reg_user_mr = mlx4_ib_reg_user_mr, 2586 .req_notify_cq = mlx4_ib_arm_cq, 2587 .rereg_user_mr = mlx4_ib_rereg_user_mr, 2588 .resize_cq = mlx4_ib_resize_cq, 2589 2590 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah), 2591 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq), 2592 INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd), 2593 INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq), 2594 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext), 2595 }; 2596 2597 static const struct ib_device_ops mlx4_ib_dev_wq_ops = { 2598 .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table, 2599 .create_wq = mlx4_ib_create_wq, 2600 .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table, 2601 .destroy_wq = mlx4_ib_destroy_wq, 2602 .modify_wq = mlx4_ib_modify_wq, 2603 }; 2604 2605 static const struct ib_device_ops mlx4_ib_dev_fmr_ops = { 2606 .alloc_fmr = mlx4_ib_fmr_alloc, 2607 .dealloc_fmr = mlx4_ib_fmr_dealloc, 2608 .map_phys_fmr = mlx4_ib_map_phys_fmr, 2609 .unmap_fmr = mlx4_ib_unmap_fmr, 2610 }; 2611 2612 static const struct ib_device_ops mlx4_ib_dev_mw_ops = { 2613 .alloc_mw = mlx4_ib_alloc_mw, 2614 .dealloc_mw = mlx4_ib_dealloc_mw, 2615 }; 2616 2617 static const struct ib_device_ops mlx4_ib_dev_xrc_ops = { 2618 .alloc_xrcd = mlx4_ib_alloc_xrcd, 2619 .dealloc_xrcd = mlx4_ib_dealloc_xrcd, 2620 }; 2621 2622 static const struct ib_device_ops mlx4_ib_dev_fs_ops = { 2623 .create_flow = mlx4_ib_create_flow, 2624 .destroy_flow = mlx4_ib_destroy_flow, 2625 }; 2626 2627 static void *mlx4_ib_add(struct mlx4_dev *dev) 2628 { 2629 struct mlx4_ib_dev *ibdev; 2630 int num_ports = 0; 2631 int i, j; 2632 int err; 2633 struct mlx4_ib_iboe *iboe; 2634 int ib_num_ports = 0; 2635 int num_req_counters; 2636 int allocated; 2637 u32 counter_index; 2638 struct counter_index *new_counter_index = NULL; 2639 2640 pr_info_once("%s", mlx4_ib_version); 2641 2642 num_ports = 0; 2643 mlx4_foreach_ib_transport_port(i, dev) 2644 num_ports++; 2645 2646 /* No point in registering a device with no ports... */ 2647 if (num_ports == 0) 2648 return NULL; 2649 2650 ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev); 2651 if (!ibdev) { 2652 dev_err(&dev->persist->pdev->dev, 2653 "Device struct alloc failed\n"); 2654 return NULL; 2655 } 2656 2657 iboe = &ibdev->iboe; 2658 2659 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2660 goto err_dealloc; 2661 2662 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2663 goto err_pd; 2664 2665 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2666 PAGE_SIZE); 2667 if (!ibdev->uar_map) 2668 goto err_uar; 2669 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2670 2671 ibdev->dev = dev; 2672 ibdev->bond_next_port = 0; 2673 2674 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2675 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2676 ibdev->num_ports = num_ports; 2677 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2678 1 : ibdev->num_ports; 2679 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2680 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2681 2682 ibdev->ib_dev.uverbs_cmd_mask = 2683 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2684 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2685 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2686 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2687 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2688 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2689 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2690 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2691 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2692 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2693 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2694 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2695 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2696 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2697 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2698 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2699 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2700 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2701 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2702 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2703 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2704 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2705 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2706 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2707 2708 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops); 2709 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2710 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 2711 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2712 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2713 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2714 2715 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2716 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2717 IB_LINK_LAYER_ETHERNET) || 2718 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2719 IB_LINK_LAYER_ETHERNET))) { 2720 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2721 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2722 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2723 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2724 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2725 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2726 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops); 2727 } 2728 2729 if (!mlx4_is_slave(ibdev->dev)) 2730 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fmr_ops); 2731 2732 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2733 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2734 ibdev->ib_dev.uverbs_cmd_mask |= 2735 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2736 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2737 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops); 2738 } 2739 2740 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2741 ibdev->ib_dev.uverbs_cmd_mask |= 2742 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2743 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2744 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops); 2745 } 2746 2747 if (check_flow_steering_support(dev)) { 2748 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2749 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2750 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2751 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2752 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops); 2753 } 2754 2755 if (!dev->caps.userspace_caps) 2756 ibdev->ib_dev.ops.uverbs_abi_ver = 2757 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2758 2759 mlx4_ib_alloc_eqs(dev, ibdev); 2760 2761 spin_lock_init(&iboe->lock); 2762 2763 if (init_node_data(ibdev)) 2764 goto err_map; 2765 mlx4_init_sl2vl_tbl(ibdev); 2766 2767 for (i = 0; i < ibdev->num_ports; ++i) { 2768 mutex_init(&ibdev->counters_table[i].mutex); 2769 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2770 iboe->last_port_state[i] = IB_PORT_DOWN; 2771 } 2772 2773 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2774 for (i = 0; i < num_req_counters; ++i) { 2775 mutex_init(&ibdev->qp1_proxy_lock[i]); 2776 allocated = 0; 2777 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2778 IB_LINK_LAYER_ETHERNET) { 2779 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2780 MLX4_RES_USAGE_DRIVER); 2781 /* if failed to allocate a new counter, use default */ 2782 if (err) 2783 counter_index = 2784 mlx4_get_default_counter_index(dev, 2785 i + 1); 2786 else 2787 allocated = 1; 2788 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2789 counter_index = mlx4_get_default_counter_index(dev, 2790 i + 1); 2791 } 2792 new_counter_index = kmalloc(sizeof(*new_counter_index), 2793 GFP_KERNEL); 2794 if (!new_counter_index) { 2795 if (allocated) 2796 mlx4_counter_free(ibdev->dev, counter_index); 2797 goto err_counter; 2798 } 2799 new_counter_index->index = counter_index; 2800 new_counter_index->allocated = allocated; 2801 list_add_tail(&new_counter_index->list, 2802 &ibdev->counters_table[i].counters_list); 2803 ibdev->counters_table[i].default_counter = counter_index; 2804 pr_info("counter index %d for port %d allocated %d\n", 2805 counter_index, i + 1, allocated); 2806 } 2807 if (mlx4_is_bonded(dev)) 2808 for (i = 1; i < ibdev->num_ports ; ++i) { 2809 new_counter_index = 2810 kmalloc(sizeof(struct counter_index), 2811 GFP_KERNEL); 2812 if (!new_counter_index) 2813 goto err_counter; 2814 new_counter_index->index = counter_index; 2815 new_counter_index->allocated = 0; 2816 list_add_tail(&new_counter_index->list, 2817 &ibdev->counters_table[i].counters_list); 2818 ibdev->counters_table[i].default_counter = 2819 counter_index; 2820 } 2821 2822 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2823 ib_num_ports++; 2824 2825 spin_lock_init(&ibdev->sm_lock); 2826 mutex_init(&ibdev->cap_mask_mutex); 2827 INIT_LIST_HEAD(&ibdev->qp_list); 2828 spin_lock_init(&ibdev->reset_flow_resource_lock); 2829 2830 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2831 ib_num_ports) { 2832 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2833 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2834 MLX4_IB_UC_STEER_QPN_ALIGN, 2835 &ibdev->steer_qpn_base, 0, 2836 MLX4_RES_USAGE_DRIVER); 2837 if (err) 2838 goto err_counter; 2839 2840 ibdev->ib_uc_qpns_bitmap = 2841 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2842 sizeof(long), 2843 GFP_KERNEL); 2844 if (!ibdev->ib_uc_qpns_bitmap) 2845 goto err_steer_qp_release; 2846 2847 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2848 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2849 ibdev->steer_qpn_count); 2850 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2851 dev, ibdev->steer_qpn_base, 2852 ibdev->steer_qpn_base + 2853 ibdev->steer_qpn_count - 1); 2854 if (err) 2855 goto err_steer_free_bitmap; 2856 } else { 2857 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2858 ibdev->steer_qpn_count); 2859 } 2860 } 2861 2862 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2863 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2864 2865 if (mlx4_ib_alloc_diag_counters(ibdev)) 2866 goto err_steer_free_bitmap; 2867 2868 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group); 2869 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d")) 2870 goto err_diag_counters; 2871 2872 if (mlx4_ib_mad_init(ibdev)) 2873 goto err_reg; 2874 2875 if (mlx4_ib_init_sriov(ibdev)) 2876 goto err_mad; 2877 2878 if (!iboe->nb.notifier_call) { 2879 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2880 err = register_netdevice_notifier(&iboe->nb); 2881 if (err) { 2882 iboe->nb.notifier_call = NULL; 2883 goto err_notif; 2884 } 2885 } 2886 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2887 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2888 if (err) 2889 goto err_notif; 2890 } 2891 2892 ibdev->ib_active = true; 2893 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2894 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2895 &ibdev->ib_dev); 2896 2897 if (mlx4_is_mfunc(ibdev->dev)) 2898 init_pkeys(ibdev); 2899 2900 /* create paravirt contexts for any VFs which are active */ 2901 if (mlx4_is_master(ibdev->dev)) { 2902 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2903 if (j == mlx4_master_func_num(ibdev->dev)) 2904 continue; 2905 if (mlx4_is_slave_active(ibdev->dev, j)) 2906 do_slave_init(ibdev, j, 1); 2907 } 2908 } 2909 return ibdev; 2910 2911 err_notif: 2912 if (ibdev->iboe.nb.notifier_call) { 2913 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2914 pr_warn("failure unregistering notifier\n"); 2915 ibdev->iboe.nb.notifier_call = NULL; 2916 } 2917 flush_workqueue(wq); 2918 2919 mlx4_ib_close_sriov(ibdev); 2920 2921 err_mad: 2922 mlx4_ib_mad_cleanup(ibdev); 2923 2924 err_reg: 2925 ib_unregister_device(&ibdev->ib_dev); 2926 2927 err_diag_counters: 2928 mlx4_ib_diag_cleanup(ibdev); 2929 2930 err_steer_free_bitmap: 2931 kfree(ibdev->ib_uc_qpns_bitmap); 2932 2933 err_steer_qp_release: 2934 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2935 ibdev->steer_qpn_count); 2936 err_counter: 2937 for (i = 0; i < ibdev->num_ports; ++i) 2938 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2939 2940 err_map: 2941 mlx4_ib_free_eqs(dev, ibdev); 2942 iounmap(ibdev->uar_map); 2943 2944 err_uar: 2945 mlx4_uar_free(dev, &ibdev->priv_uar); 2946 2947 err_pd: 2948 mlx4_pd_free(dev, ibdev->priv_pdn); 2949 2950 err_dealloc: 2951 ib_dealloc_device(&ibdev->ib_dev); 2952 2953 return NULL; 2954 } 2955 2956 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2957 { 2958 int offset; 2959 2960 WARN_ON(!dev->ib_uc_qpns_bitmap); 2961 2962 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2963 dev->steer_qpn_count, 2964 get_count_order(count)); 2965 if (offset < 0) 2966 return offset; 2967 2968 *qpn = dev->steer_qpn_base + offset; 2969 return 0; 2970 } 2971 2972 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 2973 { 2974 if (!qpn || 2975 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 2976 return; 2977 2978 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 2979 qpn, dev->steer_qpn_base)) 2980 /* not supposed to be here */ 2981 return; 2982 2983 bitmap_release_region(dev->ib_uc_qpns_bitmap, 2984 qpn - dev->steer_qpn_base, 2985 get_count_order(count)); 2986 } 2987 2988 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 2989 int is_attach) 2990 { 2991 int err; 2992 size_t flow_size; 2993 struct ib_flow_attr *flow = NULL; 2994 struct ib_flow_spec_ib *ib_spec; 2995 2996 if (is_attach) { 2997 flow_size = sizeof(struct ib_flow_attr) + 2998 sizeof(struct ib_flow_spec_ib); 2999 flow = kzalloc(flow_size, GFP_KERNEL); 3000 if (!flow) 3001 return -ENOMEM; 3002 flow->port = mqp->port; 3003 flow->num_of_specs = 1; 3004 flow->size = flow_size; 3005 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3006 ib_spec->type = IB_FLOW_SPEC_IB; 3007 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3008 /* Add an empty rule for IB L2 */ 3009 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3010 3011 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3012 IB_FLOW_DOMAIN_NIC, 3013 MLX4_FS_REGULAR, 3014 &mqp->reg_id); 3015 } else { 3016 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3017 } 3018 kfree(flow); 3019 return err; 3020 } 3021 3022 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3023 { 3024 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3025 int p; 3026 int i; 3027 3028 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3029 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3030 ibdev->ib_active = false; 3031 flush_workqueue(wq); 3032 3033 if (ibdev->iboe.nb.notifier_call) { 3034 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3035 pr_warn("failure unregistering notifier\n"); 3036 ibdev->iboe.nb.notifier_call = NULL; 3037 } 3038 3039 mlx4_ib_close_sriov(ibdev); 3040 mlx4_ib_mad_cleanup(ibdev); 3041 ib_unregister_device(&ibdev->ib_dev); 3042 mlx4_ib_diag_cleanup(ibdev); 3043 3044 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3045 ibdev->steer_qpn_count); 3046 kfree(ibdev->ib_uc_qpns_bitmap); 3047 3048 iounmap(ibdev->uar_map); 3049 for (p = 0; p < ibdev->num_ports; ++p) 3050 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3051 3052 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3053 mlx4_CLOSE_PORT(dev, p); 3054 3055 mlx4_ib_free_eqs(dev, ibdev); 3056 3057 mlx4_uar_free(dev, &ibdev->priv_uar); 3058 mlx4_pd_free(dev, ibdev->priv_pdn); 3059 ib_dealloc_device(&ibdev->ib_dev); 3060 } 3061 3062 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3063 { 3064 struct mlx4_ib_demux_work **dm = NULL; 3065 struct mlx4_dev *dev = ibdev->dev; 3066 int i; 3067 unsigned long flags; 3068 struct mlx4_active_ports actv_ports; 3069 unsigned int ports; 3070 unsigned int first_port; 3071 3072 if (!mlx4_is_master(dev)) 3073 return; 3074 3075 actv_ports = mlx4_get_active_ports(dev, slave); 3076 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3077 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3078 3079 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3080 if (!dm) 3081 return; 3082 3083 for (i = 0; i < ports; i++) { 3084 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3085 if (!dm[i]) { 3086 while (--i >= 0) 3087 kfree(dm[i]); 3088 goto out; 3089 } 3090 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3091 dm[i]->port = first_port + i + 1; 3092 dm[i]->slave = slave; 3093 dm[i]->do_init = do_init; 3094 dm[i]->dev = ibdev; 3095 } 3096 /* initialize or tear down tunnel QPs for the slave */ 3097 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3098 if (!ibdev->sriov.is_going_down) { 3099 for (i = 0; i < ports; i++) 3100 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3101 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3102 } else { 3103 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3104 for (i = 0; i < ports; i++) 3105 kfree(dm[i]); 3106 } 3107 out: 3108 kfree(dm); 3109 return; 3110 } 3111 3112 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3113 { 3114 struct mlx4_ib_qp *mqp; 3115 unsigned long flags_qp; 3116 unsigned long flags_cq; 3117 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3118 struct list_head cq_notify_list; 3119 struct mlx4_cq *mcq; 3120 unsigned long flags; 3121 3122 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3123 INIT_LIST_HEAD(&cq_notify_list); 3124 3125 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3126 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3127 3128 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3129 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3130 if (mqp->sq.tail != mqp->sq.head) { 3131 send_mcq = to_mcq(mqp->ibqp.send_cq); 3132 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3133 if (send_mcq->mcq.comp && 3134 mqp->ibqp.send_cq->comp_handler) { 3135 if (!send_mcq->mcq.reset_notify_added) { 3136 send_mcq->mcq.reset_notify_added = 1; 3137 list_add_tail(&send_mcq->mcq.reset_notify, 3138 &cq_notify_list); 3139 } 3140 } 3141 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3142 } 3143 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3144 /* Now, handle the QP's receive queue */ 3145 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3146 /* no handling is needed for SRQ */ 3147 if (!mqp->ibqp.srq) { 3148 if (mqp->rq.tail != mqp->rq.head) { 3149 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3150 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3151 if (recv_mcq->mcq.comp && 3152 mqp->ibqp.recv_cq->comp_handler) { 3153 if (!recv_mcq->mcq.reset_notify_added) { 3154 recv_mcq->mcq.reset_notify_added = 1; 3155 list_add_tail(&recv_mcq->mcq.reset_notify, 3156 &cq_notify_list); 3157 } 3158 } 3159 spin_unlock_irqrestore(&recv_mcq->lock, 3160 flags_cq); 3161 } 3162 } 3163 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3164 } 3165 3166 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3167 mcq->comp(mcq); 3168 } 3169 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3170 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3171 } 3172 3173 static void handle_bonded_port_state_event(struct work_struct *work) 3174 { 3175 struct ib_event_work *ew = 3176 container_of(work, struct ib_event_work, work); 3177 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3178 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3179 int i; 3180 struct ib_event ibev; 3181 3182 kfree(ew); 3183 spin_lock_bh(&ibdev->iboe.lock); 3184 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3185 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3186 enum ib_port_state curr_port_state; 3187 3188 if (!curr_netdev) 3189 continue; 3190 3191 curr_port_state = 3192 (netif_running(curr_netdev) && 3193 netif_carrier_ok(curr_netdev)) ? 3194 IB_PORT_ACTIVE : IB_PORT_DOWN; 3195 3196 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3197 curr_port_state : IB_PORT_ACTIVE; 3198 } 3199 spin_unlock_bh(&ibdev->iboe.lock); 3200 3201 ibev.device = &ibdev->ib_dev; 3202 ibev.element.port_num = 1; 3203 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3204 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3205 3206 ib_dispatch_event(&ibev); 3207 } 3208 3209 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3210 { 3211 u64 sl2vl; 3212 int err; 3213 3214 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3215 if (err) { 3216 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3217 port, err); 3218 sl2vl = 0; 3219 } 3220 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3221 } 3222 3223 static void ib_sl2vl_update_work(struct work_struct *work) 3224 { 3225 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3226 struct mlx4_ib_dev *mdev = ew->ib_dev; 3227 int port = ew->port; 3228 3229 mlx4_ib_sl2vl_update(mdev, port); 3230 3231 kfree(ew); 3232 } 3233 3234 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3235 int port) 3236 { 3237 struct ib_event_work *ew; 3238 3239 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3240 if (ew) { 3241 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3242 ew->port = port; 3243 ew->ib_dev = ibdev; 3244 queue_work(wq, &ew->work); 3245 } 3246 } 3247 3248 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3249 enum mlx4_dev_event event, unsigned long param) 3250 { 3251 struct ib_event ibev; 3252 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3253 struct mlx4_eqe *eqe = NULL; 3254 struct ib_event_work *ew; 3255 int p = 0; 3256 3257 if (mlx4_is_bonded(dev) && 3258 ((event == MLX4_DEV_EVENT_PORT_UP) || 3259 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3260 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3261 if (!ew) 3262 return; 3263 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3264 ew->ib_dev = ibdev; 3265 queue_work(wq, &ew->work); 3266 return; 3267 } 3268 3269 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3270 eqe = (struct mlx4_eqe *)param; 3271 else 3272 p = (int) param; 3273 3274 switch (event) { 3275 case MLX4_DEV_EVENT_PORT_UP: 3276 if (p > ibdev->num_ports) 3277 return; 3278 if (!mlx4_is_slave(dev) && 3279 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3280 IB_LINK_LAYER_INFINIBAND) { 3281 if (mlx4_is_master(dev)) 3282 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3283 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3284 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3285 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3286 } 3287 ibev.event = IB_EVENT_PORT_ACTIVE; 3288 break; 3289 3290 case MLX4_DEV_EVENT_PORT_DOWN: 3291 if (p > ibdev->num_ports) 3292 return; 3293 ibev.event = IB_EVENT_PORT_ERR; 3294 break; 3295 3296 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3297 ibdev->ib_active = false; 3298 ibev.event = IB_EVENT_DEVICE_FATAL; 3299 mlx4_ib_handle_catas_error(ibdev); 3300 break; 3301 3302 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3303 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3304 if (!ew) 3305 break; 3306 3307 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3308 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3309 ew->ib_dev = ibdev; 3310 /* need to queue only for port owner, which uses GEN_EQE */ 3311 if (mlx4_is_master(dev)) 3312 queue_work(wq, &ew->work); 3313 else 3314 handle_port_mgmt_change_event(&ew->work); 3315 return; 3316 3317 case MLX4_DEV_EVENT_SLAVE_INIT: 3318 /* here, p is the slave id */ 3319 do_slave_init(ibdev, p, 1); 3320 if (mlx4_is_master(dev)) { 3321 int i; 3322 3323 for (i = 1; i <= ibdev->num_ports; i++) { 3324 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3325 == IB_LINK_LAYER_INFINIBAND) 3326 mlx4_ib_slave_alias_guid_event(ibdev, 3327 p, i, 3328 1); 3329 } 3330 } 3331 return; 3332 3333 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3334 if (mlx4_is_master(dev)) { 3335 int i; 3336 3337 for (i = 1; i <= ibdev->num_ports; i++) { 3338 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3339 == IB_LINK_LAYER_INFINIBAND) 3340 mlx4_ib_slave_alias_guid_event(ibdev, 3341 p, i, 3342 0); 3343 } 3344 } 3345 /* here, p is the slave id */ 3346 do_slave_init(ibdev, p, 0); 3347 return; 3348 3349 default: 3350 return; 3351 } 3352 3353 ibev.device = ibdev_ptr; 3354 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3355 3356 ib_dispatch_event(&ibev); 3357 } 3358 3359 static struct mlx4_interface mlx4_ib_interface = { 3360 .add = mlx4_ib_add, 3361 .remove = mlx4_ib_remove, 3362 .event = mlx4_ib_event, 3363 .protocol = MLX4_PROT_IB_IPV6, 3364 .flags = MLX4_INTFF_BONDING 3365 }; 3366 3367 static int __init mlx4_ib_init(void) 3368 { 3369 int err; 3370 3371 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3372 if (!wq) 3373 return -ENOMEM; 3374 3375 err = mlx4_ib_mcg_init(); 3376 if (err) 3377 goto clean_wq; 3378 3379 err = mlx4_register_interface(&mlx4_ib_interface); 3380 if (err) 3381 goto clean_mcg; 3382 3383 return 0; 3384 3385 clean_mcg: 3386 mlx4_ib_mcg_destroy(); 3387 3388 clean_wq: 3389 destroy_workqueue(wq); 3390 return err; 3391 } 3392 3393 static void __exit mlx4_ib_cleanup(void) 3394 { 3395 mlx4_unregister_interface(&mlx4_ib_interface); 3396 mlx4_ib_mcg_destroy(); 3397 destroy_workqueue(wq); 3398 } 3399 3400 module_init(mlx4_ib_init); 3401 module_exit(mlx4_ib_cleanup); 3402