1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 250 { 251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 252 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 253 struct mlx4_port_gid_table *port_gid_table; 254 int free = -1, found = -1; 255 int ret = 0; 256 int hw_update = 0; 257 int i; 258 struct gid_entry *gids = NULL; 259 260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 261 return -EINVAL; 262 263 if (attr->port_num > MLX4_MAX_PORTS) 264 return -EINVAL; 265 266 if (!context) 267 return -EINVAL; 268 269 port_gid_table = &iboe->gids[attr->port_num - 1]; 270 spin_lock_bh(&iboe->lock); 271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 272 if (!memcmp(&port_gid_table->gids[i].gid, 273 &attr->gid, sizeof(attr->gid)) && 274 port_gid_table->gids[i].gid_type == attr->gid_type) { 275 found = i; 276 break; 277 } 278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 279 free = i; /* HW has space */ 280 } 281 282 if (found < 0) { 283 if (free < 0) { 284 ret = -ENOSPC; 285 } else { 286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 287 if (!port_gid_table->gids[free].ctx) { 288 ret = -ENOMEM; 289 } else { 290 *context = port_gid_table->gids[free].ctx; 291 memcpy(&port_gid_table->gids[free].gid, 292 &attr->gid, sizeof(attr->gid)); 293 port_gid_table->gids[free].gid_type = attr->gid_type; 294 port_gid_table->gids[free].ctx->real_index = free; 295 port_gid_table->gids[free].ctx->refcount = 1; 296 hw_update = 1; 297 } 298 } 299 } else { 300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 301 *context = ctx; 302 ctx->refcount++; 303 } 304 if (!ret && hw_update) { 305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 306 GFP_ATOMIC); 307 if (!gids) { 308 ret = -ENOMEM; 309 } else { 310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 312 gids[i].gid_type = port_gid_table->gids[i].gid_type; 313 } 314 } 315 } 316 spin_unlock_bh(&iboe->lock); 317 318 if (!ret && hw_update) { 319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 320 kfree(gids); 321 } 322 323 return ret; 324 } 325 326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 327 { 328 struct gid_cache_context *ctx = *context; 329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 330 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 331 struct mlx4_port_gid_table *port_gid_table; 332 int ret = 0; 333 int hw_update = 0; 334 struct gid_entry *gids = NULL; 335 336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 337 return -EINVAL; 338 339 if (attr->port_num > MLX4_MAX_PORTS) 340 return -EINVAL; 341 342 port_gid_table = &iboe->gids[attr->port_num - 1]; 343 spin_lock_bh(&iboe->lock); 344 if (ctx) { 345 ctx->refcount--; 346 if (!ctx->refcount) { 347 unsigned int real_index = ctx->real_index; 348 349 memset(&port_gid_table->gids[real_index].gid, 0, 350 sizeof(port_gid_table->gids[real_index].gid)); 351 kfree(port_gid_table->gids[real_index].ctx); 352 port_gid_table->gids[real_index].ctx = NULL; 353 hw_update = 1; 354 } 355 } 356 if (!ret && hw_update) { 357 int i; 358 359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 360 GFP_ATOMIC); 361 if (!gids) { 362 ret = -ENOMEM; 363 } else { 364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 365 memcpy(&gids[i].gid, 366 &port_gid_table->gids[i].gid, 367 sizeof(union ib_gid)); 368 gids[i].gid_type = 369 port_gid_table->gids[i].gid_type; 370 } 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 const struct ib_gid_attr *attr) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 struct mlx4_port_gid_table *port_gid_table; 388 int real_index = -EINVAL; 389 int i; 390 unsigned long flags; 391 u8 port_num = attr->port_num; 392 393 if (port_num > MLX4_MAX_PORTS) 394 return -EINVAL; 395 396 if (mlx4_is_bonded(ibdev->dev)) 397 port_num = 1; 398 399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 400 return attr->index; 401 402 spin_lock_irqsave(&iboe->lock, flags); 403 port_gid_table = &iboe->gids[port_num - 1]; 404 405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 406 if (!memcmp(&port_gid_table->gids[i].gid, 407 &attr->gid, sizeof(attr->gid)) && 408 attr->gid_type == port_gid_table->gids[i].gid_type) { 409 ctx = port_gid_table->gids[i].ctx; 410 break; 411 } 412 if (ctx) 413 real_index = ctx->real_index; 414 spin_unlock_irqrestore(&iboe->lock, flags); 415 return real_index; 416 } 417 418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 419 sizeof(((type *)0)->fld) <= (sz)) 420 421 static int mlx4_ib_query_device(struct ib_device *ibdev, 422 struct ib_device_attr *props, 423 struct ib_udata *uhw) 424 { 425 struct mlx4_ib_dev *dev = to_mdev(ibdev); 426 struct ib_smp *in_mad = NULL; 427 struct ib_smp *out_mad = NULL; 428 int err; 429 int have_ib_ports; 430 struct mlx4_uverbs_ex_query_device cmd; 431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 432 struct mlx4_clock_params clock_params; 433 434 if (uhw->inlen) { 435 if (uhw->inlen < sizeof(cmd)) 436 return -EINVAL; 437 438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 439 if (err) 440 return err; 441 442 if (cmd.comp_mask) 443 return -EINVAL; 444 445 if (cmd.reserved) 446 return -EINVAL; 447 } 448 449 resp.response_length = offsetof(typeof(resp), response_length) + 450 sizeof(resp.response_length); 451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 453 err = -ENOMEM; 454 if (!in_mad || !out_mad) 455 goto out; 456 457 init_query_mad(in_mad); 458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 459 460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 461 1, NULL, NULL, in_mad, out_mad); 462 if (err) 463 goto out; 464 465 memset(props, 0, sizeof *props); 466 467 have_ib_ports = num_ib_ports(dev->dev); 468 469 props->fw_ver = dev->dev->caps.fw_ver; 470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 471 IB_DEVICE_PORT_ACTIVE_EVENT | 472 IB_DEVICE_SYS_IMAGE_GUID | 473 IB_DEVICE_RC_RNR_NAK_GEN | 474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 485 if (dev->dev->caps.max_gso_sz && 486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 488 props->device_cap_flags |= IB_DEVICE_UD_TSO; 489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 496 props->device_cap_flags |= IB_DEVICE_XRC; 497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 502 else 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 504 } 505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 507 508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 509 510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 511 0xffffff; 512 props->vendor_part_id = dev->dev->persist->pdev->device; 513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 515 516 props->max_mr_size = ~0ull; 517 props->page_size_cap = dev->dev->caps.page_size_cap; 518 props->max_qp = dev->dev->quotas.qp; 519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 520 props->max_send_sge = 521 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 522 props->max_recv_sge = 523 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 524 props->max_sge_rd = MLX4_MAX_SGE_RD; 525 props->max_cq = dev->dev->quotas.cq; 526 props->max_cqe = dev->dev->caps.max_cqes; 527 props->max_mr = dev->dev->quotas.mpt; 528 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 529 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 530 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 531 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 532 props->max_srq = dev->dev->quotas.srq; 533 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 534 props->max_srq_sge = dev->dev->caps.max_srq_sge; 535 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 536 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 537 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 538 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 539 props->masked_atomic_cap = props->atomic_cap; 540 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 541 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 542 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 543 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 544 props->max_mcast_grp; 545 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 546 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 547 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 548 props->max_ah = INT_MAX; 549 550 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 551 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 552 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 553 props->rss_caps.max_rwq_indirection_tables = 554 props->max_qp; 555 props->rss_caps.max_rwq_indirection_table_size = 556 dev->dev->caps.max_rss_tbl_sz; 557 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 558 props->max_wq_type_rq = props->max_qp; 559 } 560 561 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 562 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 563 } 564 565 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 566 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 567 568 if (!mlx4_is_slave(dev->dev)) 569 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 570 571 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 572 resp.response_length += sizeof(resp.hca_core_clock_offset); 573 if (!err && !mlx4_is_slave(dev->dev)) { 574 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 575 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 576 } 577 } 578 579 if (uhw->outlen >= resp.response_length + 580 sizeof(resp.max_inl_recv_sz)) { 581 resp.response_length += sizeof(resp.max_inl_recv_sz); 582 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 583 sizeof(struct mlx4_wqe_data_seg); 584 } 585 586 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 587 if (props->rss_caps.supported_qpts) { 588 resp.rss_caps.rx_hash_function = 589 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 590 591 resp.rss_caps.rx_hash_fields_mask = 592 MLX4_IB_RX_HASH_SRC_IPV4 | 593 MLX4_IB_RX_HASH_DST_IPV4 | 594 MLX4_IB_RX_HASH_SRC_IPV6 | 595 MLX4_IB_RX_HASH_DST_IPV6 | 596 MLX4_IB_RX_HASH_SRC_PORT_TCP | 597 MLX4_IB_RX_HASH_DST_PORT_TCP | 598 MLX4_IB_RX_HASH_SRC_PORT_UDP | 599 MLX4_IB_RX_HASH_DST_PORT_UDP; 600 601 if (dev->dev->caps.tunnel_offload_mode == 602 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 603 resp.rss_caps.rx_hash_fields_mask |= 604 MLX4_IB_RX_HASH_INNER; 605 } 606 resp.response_length = offsetof(typeof(resp), rss_caps) + 607 sizeof(resp.rss_caps); 608 } 609 610 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 611 if (dev->dev->caps.max_gso_sz && 612 ((mlx4_ib_port_link_layer(ibdev, 1) == 613 IB_LINK_LAYER_ETHERNET) || 614 (mlx4_ib_port_link_layer(ibdev, 2) == 615 IB_LINK_LAYER_ETHERNET))) { 616 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 617 resp.tso_caps.supported_qpts |= 618 1 << IB_QPT_RAW_PACKET; 619 } 620 resp.response_length = offsetof(typeof(resp), tso_caps) + 621 sizeof(resp.tso_caps); 622 } 623 624 if (uhw->outlen) { 625 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 626 if (err) 627 goto out; 628 } 629 out: 630 kfree(in_mad); 631 kfree(out_mad); 632 633 return err; 634 } 635 636 static enum rdma_link_layer 637 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 638 { 639 struct mlx4_dev *dev = to_mdev(device)->dev; 640 641 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 642 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 643 } 644 645 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 646 struct ib_port_attr *props, int netw_view) 647 { 648 struct ib_smp *in_mad = NULL; 649 struct ib_smp *out_mad = NULL; 650 int ext_active_speed; 651 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 652 int err = -ENOMEM; 653 654 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 655 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 656 if (!in_mad || !out_mad) 657 goto out; 658 659 init_query_mad(in_mad); 660 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 661 in_mad->attr_mod = cpu_to_be32(port); 662 663 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 664 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 665 666 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 667 in_mad, out_mad); 668 if (err) 669 goto out; 670 671 672 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 673 props->lmc = out_mad->data[34] & 0x7; 674 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 675 props->sm_sl = out_mad->data[36] & 0xf; 676 props->state = out_mad->data[32] & 0xf; 677 props->phys_state = out_mad->data[33] >> 4; 678 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 679 if (netw_view) 680 props->gid_tbl_len = out_mad->data[50]; 681 else 682 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 683 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 684 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 685 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 686 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 687 props->active_width = out_mad->data[31] & 0xf; 688 props->active_speed = out_mad->data[35] >> 4; 689 props->max_mtu = out_mad->data[41] & 0xf; 690 props->active_mtu = out_mad->data[36] >> 4; 691 props->subnet_timeout = out_mad->data[51] & 0x1f; 692 props->max_vl_num = out_mad->data[37] >> 4; 693 props->init_type_reply = out_mad->data[41] >> 4; 694 695 /* Check if extended speeds (EDR/FDR/...) are supported */ 696 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 697 ext_active_speed = out_mad->data[62] >> 4; 698 699 switch (ext_active_speed) { 700 case 1: 701 props->active_speed = IB_SPEED_FDR; 702 break; 703 case 2: 704 props->active_speed = IB_SPEED_EDR; 705 break; 706 } 707 } 708 709 /* If reported active speed is QDR, check if is FDR-10 */ 710 if (props->active_speed == IB_SPEED_QDR) { 711 init_query_mad(in_mad); 712 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 713 in_mad->attr_mod = cpu_to_be32(port); 714 715 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 716 NULL, NULL, in_mad, out_mad); 717 if (err) 718 goto out; 719 720 /* Checking LinkSpeedActive for FDR-10 */ 721 if (out_mad->data[15] & 0x1) 722 props->active_speed = IB_SPEED_FDR10; 723 } 724 725 /* Avoid wrong speed value returned by FW if the IB link is down. */ 726 if (props->state == IB_PORT_DOWN) 727 props->active_speed = IB_SPEED_SDR; 728 729 out: 730 kfree(in_mad); 731 kfree(out_mad); 732 return err; 733 } 734 735 static u8 state_to_phys_state(enum ib_port_state state) 736 { 737 return state == IB_PORT_ACTIVE ? 5 : 3; 738 } 739 740 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 741 struct ib_port_attr *props) 742 { 743 744 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 745 struct mlx4_ib_iboe *iboe = &mdev->iboe; 746 struct net_device *ndev; 747 enum ib_mtu tmp; 748 struct mlx4_cmd_mailbox *mailbox; 749 int err = 0; 750 int is_bonded = mlx4_is_bonded(mdev->dev); 751 752 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 753 if (IS_ERR(mailbox)) 754 return PTR_ERR(mailbox); 755 756 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 757 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 758 MLX4_CMD_WRAPPED); 759 if (err) 760 goto out; 761 762 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 763 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 764 IB_WIDTH_4X : IB_WIDTH_1X; 765 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 766 IB_SPEED_FDR : IB_SPEED_QDR; 767 props->port_cap_flags = IB_PORT_CM_SUP; 768 props->ip_gids = true; 769 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 770 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 771 props->pkey_tbl_len = 1; 772 props->max_mtu = IB_MTU_4096; 773 props->max_vl_num = 2; 774 props->state = IB_PORT_DOWN; 775 props->phys_state = state_to_phys_state(props->state); 776 props->active_mtu = IB_MTU_256; 777 spin_lock_bh(&iboe->lock); 778 ndev = iboe->netdevs[port - 1]; 779 if (ndev && is_bonded) { 780 rcu_read_lock(); /* required to get upper dev */ 781 ndev = netdev_master_upper_dev_get_rcu(ndev); 782 rcu_read_unlock(); 783 } 784 if (!ndev) 785 goto out_unlock; 786 787 tmp = iboe_get_mtu(ndev->mtu); 788 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 789 790 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 791 IB_PORT_ACTIVE : IB_PORT_DOWN; 792 props->phys_state = state_to_phys_state(props->state); 793 out_unlock: 794 spin_unlock_bh(&iboe->lock); 795 out: 796 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 797 return err; 798 } 799 800 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 801 struct ib_port_attr *props, int netw_view) 802 { 803 int err; 804 805 /* props being zeroed by the caller, avoid zeroing it here */ 806 807 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 808 ib_link_query_port(ibdev, port, props, netw_view) : 809 eth_link_query_port(ibdev, port, props); 810 811 return err; 812 } 813 814 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 815 struct ib_port_attr *props) 816 { 817 /* returns host view */ 818 return __mlx4_ib_query_port(ibdev, port, props, 0); 819 } 820 821 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 822 union ib_gid *gid, int netw_view) 823 { 824 struct ib_smp *in_mad = NULL; 825 struct ib_smp *out_mad = NULL; 826 int err = -ENOMEM; 827 struct mlx4_ib_dev *dev = to_mdev(ibdev); 828 int clear = 0; 829 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 830 831 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 832 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 833 if (!in_mad || !out_mad) 834 goto out; 835 836 init_query_mad(in_mad); 837 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 838 in_mad->attr_mod = cpu_to_be32(port); 839 840 if (mlx4_is_mfunc(dev->dev) && netw_view) 841 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 842 843 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 844 if (err) 845 goto out; 846 847 memcpy(gid->raw, out_mad->data + 8, 8); 848 849 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 850 if (index) { 851 /* For any index > 0, return the null guid */ 852 err = 0; 853 clear = 1; 854 goto out; 855 } 856 } 857 858 init_query_mad(in_mad); 859 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 860 in_mad->attr_mod = cpu_to_be32(index / 8); 861 862 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 863 NULL, NULL, in_mad, out_mad); 864 if (err) 865 goto out; 866 867 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 868 869 out: 870 if (clear) 871 memset(gid->raw + 8, 0, 8); 872 kfree(in_mad); 873 kfree(out_mad); 874 return err; 875 } 876 877 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 878 union ib_gid *gid) 879 { 880 if (rdma_protocol_ib(ibdev, port)) 881 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 882 return 0; 883 } 884 885 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 886 { 887 union sl2vl_tbl_to_u64 sl2vl64; 888 struct ib_smp *in_mad = NULL; 889 struct ib_smp *out_mad = NULL; 890 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 891 int err = -ENOMEM; 892 int jj; 893 894 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 895 *sl2vl_tbl = 0; 896 return 0; 897 } 898 899 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 900 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 901 if (!in_mad || !out_mad) 902 goto out; 903 904 init_query_mad(in_mad); 905 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 906 in_mad->attr_mod = 0; 907 908 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 909 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 910 911 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 912 in_mad, out_mad); 913 if (err) 914 goto out; 915 916 for (jj = 0; jj < 8; jj++) 917 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 918 *sl2vl_tbl = sl2vl64.sl64; 919 920 out: 921 kfree(in_mad); 922 kfree(out_mad); 923 return err; 924 } 925 926 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 927 { 928 u64 sl2vl; 929 int i; 930 int err; 931 932 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 933 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 934 continue; 935 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 936 if (err) { 937 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 938 i, err); 939 sl2vl = 0; 940 } 941 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 942 } 943 } 944 945 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 946 u16 *pkey, int netw_view) 947 { 948 struct ib_smp *in_mad = NULL; 949 struct ib_smp *out_mad = NULL; 950 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 951 int err = -ENOMEM; 952 953 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 954 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 955 if (!in_mad || !out_mad) 956 goto out; 957 958 init_query_mad(in_mad); 959 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 960 in_mad->attr_mod = cpu_to_be32(index / 32); 961 962 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 963 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 964 965 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 966 in_mad, out_mad); 967 if (err) 968 goto out; 969 970 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 971 972 out: 973 kfree(in_mad); 974 kfree(out_mad); 975 return err; 976 } 977 978 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 979 { 980 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 981 } 982 983 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 984 struct ib_device_modify *props) 985 { 986 struct mlx4_cmd_mailbox *mailbox; 987 unsigned long flags; 988 989 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 990 return -EOPNOTSUPP; 991 992 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 993 return 0; 994 995 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 996 return -EOPNOTSUPP; 997 998 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 999 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1000 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1001 1002 /* 1003 * If possible, pass node desc to FW, so it can generate 1004 * a 144 trap. If cmd fails, just ignore. 1005 */ 1006 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1007 if (IS_ERR(mailbox)) 1008 return 0; 1009 1010 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1011 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1012 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1013 1014 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1015 1016 return 0; 1017 } 1018 1019 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1020 u32 cap_mask) 1021 { 1022 struct mlx4_cmd_mailbox *mailbox; 1023 int err; 1024 1025 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1026 if (IS_ERR(mailbox)) 1027 return PTR_ERR(mailbox); 1028 1029 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1030 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1031 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1032 } else { 1033 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1034 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1035 } 1036 1037 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1038 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1039 MLX4_CMD_WRAPPED); 1040 1041 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1042 return err; 1043 } 1044 1045 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1046 struct ib_port_modify *props) 1047 { 1048 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1049 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1050 struct ib_port_attr attr; 1051 u32 cap_mask; 1052 int err; 1053 1054 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1055 * of whether port link layer is ETH or IB. For ETH ports, qkey 1056 * violations and port capabilities are not meaningful. 1057 */ 1058 if (is_eth) 1059 return 0; 1060 1061 mutex_lock(&mdev->cap_mask_mutex); 1062 1063 err = ib_query_port(ibdev, port, &attr); 1064 if (err) 1065 goto out; 1066 1067 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1068 ~props->clr_port_cap_mask; 1069 1070 err = mlx4_ib_SET_PORT(mdev, port, 1071 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1072 cap_mask); 1073 1074 out: 1075 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1076 return err; 1077 } 1078 1079 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1080 struct ib_udata *udata) 1081 { 1082 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1083 struct mlx4_ib_ucontext *context; 1084 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1085 struct mlx4_ib_alloc_ucontext_resp resp; 1086 int err; 1087 1088 if (!dev->ib_active) 1089 return ERR_PTR(-EAGAIN); 1090 1091 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1092 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1093 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1094 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1095 } else { 1096 resp.dev_caps = dev->dev->caps.userspace_caps; 1097 resp.qp_tab_size = dev->dev->caps.num_qps; 1098 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1099 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1100 resp.cqe_size = dev->dev->caps.cqe_size; 1101 } 1102 1103 context = kzalloc(sizeof(*context), GFP_KERNEL); 1104 if (!context) 1105 return ERR_PTR(-ENOMEM); 1106 1107 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1108 if (err) { 1109 kfree(context); 1110 return ERR_PTR(err); 1111 } 1112 1113 INIT_LIST_HEAD(&context->db_page_list); 1114 mutex_init(&context->db_page_mutex); 1115 1116 INIT_LIST_HEAD(&context->wqn_ranges_list); 1117 mutex_init(&context->wqn_ranges_mutex); 1118 1119 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1120 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1121 else 1122 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1123 1124 if (err) { 1125 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1126 kfree(context); 1127 return ERR_PTR(-EFAULT); 1128 } 1129 1130 return &context->ibucontext; 1131 } 1132 1133 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1134 { 1135 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1136 1137 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1138 kfree(context); 1139 1140 return 0; 1141 } 1142 1143 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1144 { 1145 /* vma_open is called when a new VMA is created on top of our VMA. 1146 * This is done through either mremap flow or split_vma (usually due 1147 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1148 * vma, as this VMA is strongly hardware related. Therefore we set the 1149 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1150 * calling us again and trying to do incorrect actions. We assume that 1151 * the original vma size is exactly a single page that there will be no 1152 * "splitting" operations on. 1153 */ 1154 area->vm_ops = NULL; 1155 } 1156 1157 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1158 { 1159 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1160 1161 /* It's guaranteed that all VMAs opened on a FD are closed before the 1162 * file itself is closed, therefore no sync is needed with the regular 1163 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1164 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1165 * The close operation is usually called under mm->mmap_sem except when 1166 * process is exiting. The exiting case is handled explicitly as part 1167 * of mlx4_ib_disassociate_ucontext. 1168 */ 1169 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1170 area->vm_private_data; 1171 1172 /* set the vma context pointer to null in the mlx4_ib driver's private 1173 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1174 */ 1175 mlx4_ib_vma_priv_data->vma = NULL; 1176 } 1177 1178 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1179 .open = mlx4_ib_vma_open, 1180 .close = mlx4_ib_vma_close 1181 }; 1182 1183 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1184 { 1185 int i; 1186 struct vm_area_struct *vma; 1187 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1188 1189 /* need to protect from a race on closing the vma as part of 1190 * mlx4_ib_vma_close(). 1191 */ 1192 for (i = 0; i < HW_BAR_COUNT; i++) { 1193 vma = context->hw_bar_info[i].vma; 1194 if (!vma) 1195 continue; 1196 1197 zap_vma_ptes(context->hw_bar_info[i].vma, 1198 context->hw_bar_info[i].vma->vm_start, PAGE_SIZE); 1199 1200 context->hw_bar_info[i].vma->vm_flags &= 1201 ~(VM_SHARED | VM_MAYSHARE); 1202 /* context going to be destroyed, should not access ops any more */ 1203 context->hw_bar_info[i].vma->vm_ops = NULL; 1204 } 1205 } 1206 1207 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1208 struct mlx4_ib_vma_private_data *vma_private_data) 1209 { 1210 vma_private_data->vma = vma; 1211 vma->vm_private_data = vma_private_data; 1212 vma->vm_ops = &mlx4_ib_vm_ops; 1213 } 1214 1215 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1216 { 1217 struct mlx4_ib_dev *dev = to_mdev(context->device); 1218 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1219 1220 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1221 return -EINVAL; 1222 1223 if (vma->vm_pgoff == 0) { 1224 /* We prevent double mmaping on same context */ 1225 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1226 return -EINVAL; 1227 1228 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1229 1230 if (io_remap_pfn_range(vma, vma->vm_start, 1231 to_mucontext(context)->uar.pfn, 1232 PAGE_SIZE, vma->vm_page_prot)) 1233 return -EAGAIN; 1234 1235 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1236 1237 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1238 /* We prevent double mmaping on same context */ 1239 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1240 return -EINVAL; 1241 1242 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1243 1244 if (io_remap_pfn_range(vma, vma->vm_start, 1245 to_mucontext(context)->uar.pfn + 1246 dev->dev->caps.num_uars, 1247 PAGE_SIZE, vma->vm_page_prot)) 1248 return -EAGAIN; 1249 1250 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1251 1252 } else if (vma->vm_pgoff == 3) { 1253 struct mlx4_clock_params params; 1254 int ret; 1255 1256 /* We prevent double mmaping on same context */ 1257 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1258 return -EINVAL; 1259 1260 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1261 1262 if (ret) 1263 return ret; 1264 1265 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1266 if (io_remap_pfn_range(vma, vma->vm_start, 1267 (pci_resource_start(dev->dev->persist->pdev, 1268 params.bar) + 1269 params.offset) 1270 >> PAGE_SHIFT, 1271 PAGE_SIZE, vma->vm_page_prot)) 1272 return -EAGAIN; 1273 1274 mlx4_ib_set_vma_data(vma, 1275 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1276 } else { 1277 return -EINVAL; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1284 struct ib_ucontext *context, 1285 struct ib_udata *udata) 1286 { 1287 struct mlx4_ib_pd *pd; 1288 int err; 1289 1290 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 1291 if (!pd) 1292 return ERR_PTR(-ENOMEM); 1293 1294 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1295 if (err) { 1296 kfree(pd); 1297 return ERR_PTR(err); 1298 } 1299 1300 if (context) 1301 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1302 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1303 kfree(pd); 1304 return ERR_PTR(-EFAULT); 1305 } 1306 return &pd->ibpd; 1307 } 1308 1309 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1310 { 1311 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1312 kfree(pd); 1313 1314 return 0; 1315 } 1316 1317 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1318 struct ib_ucontext *context, 1319 struct ib_udata *udata) 1320 { 1321 struct mlx4_ib_xrcd *xrcd; 1322 struct ib_cq_init_attr cq_attr = {}; 1323 int err; 1324 1325 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1326 return ERR_PTR(-ENOSYS); 1327 1328 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1329 if (!xrcd) 1330 return ERR_PTR(-ENOMEM); 1331 1332 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1333 if (err) 1334 goto err1; 1335 1336 xrcd->pd = ib_alloc_pd(ibdev, 0); 1337 if (IS_ERR(xrcd->pd)) { 1338 err = PTR_ERR(xrcd->pd); 1339 goto err2; 1340 } 1341 1342 cq_attr.cqe = 1; 1343 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1344 if (IS_ERR(xrcd->cq)) { 1345 err = PTR_ERR(xrcd->cq); 1346 goto err3; 1347 } 1348 1349 return &xrcd->ibxrcd; 1350 1351 err3: 1352 ib_dealloc_pd(xrcd->pd); 1353 err2: 1354 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1355 err1: 1356 kfree(xrcd); 1357 return ERR_PTR(err); 1358 } 1359 1360 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1361 { 1362 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1363 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1364 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1365 kfree(xrcd); 1366 1367 return 0; 1368 } 1369 1370 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1371 { 1372 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1373 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1374 struct mlx4_ib_gid_entry *ge; 1375 1376 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1377 if (!ge) 1378 return -ENOMEM; 1379 1380 ge->gid = *gid; 1381 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1382 ge->port = mqp->port; 1383 ge->added = 1; 1384 } 1385 1386 mutex_lock(&mqp->mutex); 1387 list_add_tail(&ge->list, &mqp->gid_list); 1388 mutex_unlock(&mqp->mutex); 1389 1390 return 0; 1391 } 1392 1393 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1394 struct mlx4_ib_counters *ctr_table) 1395 { 1396 struct counter_index *counter, *tmp_count; 1397 1398 mutex_lock(&ctr_table->mutex); 1399 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1400 list) { 1401 if (counter->allocated) 1402 mlx4_counter_free(ibdev->dev, counter->index); 1403 list_del(&counter->list); 1404 kfree(counter); 1405 } 1406 mutex_unlock(&ctr_table->mutex); 1407 } 1408 1409 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1410 union ib_gid *gid) 1411 { 1412 struct net_device *ndev; 1413 int ret = 0; 1414 1415 if (!mqp->port) 1416 return 0; 1417 1418 spin_lock_bh(&mdev->iboe.lock); 1419 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1420 if (ndev) 1421 dev_hold(ndev); 1422 spin_unlock_bh(&mdev->iboe.lock); 1423 1424 if (ndev) { 1425 ret = 1; 1426 dev_put(ndev); 1427 } 1428 1429 return ret; 1430 } 1431 1432 struct mlx4_ib_steering { 1433 struct list_head list; 1434 struct mlx4_flow_reg_id reg_id; 1435 union ib_gid gid; 1436 }; 1437 1438 #define LAST_ETH_FIELD vlan_tag 1439 #define LAST_IB_FIELD sl 1440 #define LAST_IPV4_FIELD dst_ip 1441 #define LAST_TCP_UDP_FIELD src_port 1442 1443 /* Field is the last supported field */ 1444 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1445 memchr_inv((void *)&filter.field +\ 1446 sizeof(filter.field), 0,\ 1447 sizeof(filter) -\ 1448 offsetof(typeof(filter), field) -\ 1449 sizeof(filter.field)) 1450 1451 static int parse_flow_attr(struct mlx4_dev *dev, 1452 u32 qp_num, 1453 union ib_flow_spec *ib_spec, 1454 struct _rule_hw *mlx4_spec) 1455 { 1456 enum mlx4_net_trans_rule_id type; 1457 1458 switch (ib_spec->type) { 1459 case IB_FLOW_SPEC_ETH: 1460 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1461 return -ENOTSUPP; 1462 1463 type = MLX4_NET_TRANS_RULE_ID_ETH; 1464 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1465 ETH_ALEN); 1466 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1467 ETH_ALEN); 1468 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1469 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1470 break; 1471 case IB_FLOW_SPEC_IB: 1472 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1473 return -ENOTSUPP; 1474 1475 type = MLX4_NET_TRANS_RULE_ID_IB; 1476 mlx4_spec->ib.l3_qpn = 1477 cpu_to_be32(qp_num); 1478 mlx4_spec->ib.qpn_mask = 1479 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1480 break; 1481 1482 1483 case IB_FLOW_SPEC_IPV4: 1484 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1485 return -ENOTSUPP; 1486 1487 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1488 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1489 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1490 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1491 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1492 break; 1493 1494 case IB_FLOW_SPEC_TCP: 1495 case IB_FLOW_SPEC_UDP: 1496 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1497 return -ENOTSUPP; 1498 1499 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1500 MLX4_NET_TRANS_RULE_ID_TCP : 1501 MLX4_NET_TRANS_RULE_ID_UDP; 1502 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1503 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1504 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1505 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1506 break; 1507 1508 default: 1509 return -EINVAL; 1510 } 1511 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1512 mlx4_hw_rule_sz(dev, type) < 0) 1513 return -EINVAL; 1514 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1515 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1516 return mlx4_hw_rule_sz(dev, type); 1517 } 1518 1519 struct default_rules { 1520 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1521 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1522 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1523 __u8 link_layer; 1524 }; 1525 static const struct default_rules default_table[] = { 1526 { 1527 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1528 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1529 .rules_create_list = {IB_FLOW_SPEC_IB}, 1530 .link_layer = IB_LINK_LAYER_INFINIBAND 1531 } 1532 }; 1533 1534 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1535 struct ib_flow_attr *flow_attr) 1536 { 1537 int i, j, k; 1538 void *ib_flow; 1539 const struct default_rules *pdefault_rules = default_table; 1540 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1541 1542 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1543 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1544 memset(&field_types, 0, sizeof(field_types)); 1545 1546 if (link_layer != pdefault_rules->link_layer) 1547 continue; 1548 1549 ib_flow = flow_attr + 1; 1550 /* we assume the specs are sorted */ 1551 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1552 j < flow_attr->num_of_specs; k++) { 1553 union ib_flow_spec *current_flow = 1554 (union ib_flow_spec *)ib_flow; 1555 1556 /* same layer but different type */ 1557 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1558 (pdefault_rules->mandatory_fields[k] & 1559 IB_FLOW_SPEC_LAYER_MASK)) && 1560 (current_flow->type != 1561 pdefault_rules->mandatory_fields[k])) 1562 goto out; 1563 1564 /* same layer, try match next one */ 1565 if (current_flow->type == 1566 pdefault_rules->mandatory_fields[k]) { 1567 j++; 1568 ib_flow += 1569 ((union ib_flow_spec *)ib_flow)->size; 1570 } 1571 } 1572 1573 ib_flow = flow_attr + 1; 1574 for (j = 0; j < flow_attr->num_of_specs; 1575 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1576 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1577 /* same layer and same type */ 1578 if (((union ib_flow_spec *)ib_flow)->type == 1579 pdefault_rules->mandatory_not_fields[k]) 1580 goto out; 1581 1582 return i; 1583 } 1584 out: 1585 return -1; 1586 } 1587 1588 static int __mlx4_ib_create_default_rules( 1589 struct mlx4_ib_dev *mdev, 1590 struct ib_qp *qp, 1591 const struct default_rules *pdefault_rules, 1592 struct _rule_hw *mlx4_spec) { 1593 int size = 0; 1594 int i; 1595 1596 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1597 int ret; 1598 union ib_flow_spec ib_spec; 1599 switch (pdefault_rules->rules_create_list[i]) { 1600 case 0: 1601 /* no rule */ 1602 continue; 1603 case IB_FLOW_SPEC_IB: 1604 ib_spec.type = IB_FLOW_SPEC_IB; 1605 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1606 1607 break; 1608 default: 1609 /* invalid rule */ 1610 return -EINVAL; 1611 } 1612 /* We must put empty rule, qpn is being ignored */ 1613 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1614 mlx4_spec); 1615 if (ret < 0) { 1616 pr_info("invalid parsing\n"); 1617 return -EINVAL; 1618 } 1619 1620 mlx4_spec = (void *)mlx4_spec + ret; 1621 size += ret; 1622 } 1623 return size; 1624 } 1625 1626 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1627 int domain, 1628 enum mlx4_net_trans_promisc_mode flow_type, 1629 u64 *reg_id) 1630 { 1631 int ret, i; 1632 int size = 0; 1633 void *ib_flow; 1634 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1635 struct mlx4_cmd_mailbox *mailbox; 1636 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1637 int default_flow; 1638 1639 static const u16 __mlx4_domain[] = { 1640 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1641 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1642 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1643 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1644 }; 1645 1646 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1647 pr_err("Invalid priority value %d\n", flow_attr->priority); 1648 return -EINVAL; 1649 } 1650 1651 if (domain >= IB_FLOW_DOMAIN_NUM) { 1652 pr_err("Invalid domain value %d\n", domain); 1653 return -EINVAL; 1654 } 1655 1656 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1657 return -EINVAL; 1658 1659 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1660 if (IS_ERR(mailbox)) 1661 return PTR_ERR(mailbox); 1662 ctrl = mailbox->buf; 1663 1664 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1665 flow_attr->priority); 1666 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1667 ctrl->port = flow_attr->port; 1668 ctrl->qpn = cpu_to_be32(qp->qp_num); 1669 1670 ib_flow = flow_attr + 1; 1671 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1672 /* Add default flows */ 1673 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1674 if (default_flow >= 0) { 1675 ret = __mlx4_ib_create_default_rules( 1676 mdev, qp, default_table + default_flow, 1677 mailbox->buf + size); 1678 if (ret < 0) { 1679 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1680 return -EINVAL; 1681 } 1682 size += ret; 1683 } 1684 for (i = 0; i < flow_attr->num_of_specs; i++) { 1685 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1686 mailbox->buf + size); 1687 if (ret < 0) { 1688 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1689 return -EINVAL; 1690 } 1691 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1692 size += ret; 1693 } 1694 1695 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1696 flow_attr->num_of_specs == 1) { 1697 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1698 enum ib_flow_spec_type header_spec = 1699 ((union ib_flow_spec *)(flow_attr + 1))->type; 1700 1701 if (header_spec == IB_FLOW_SPEC_ETH) 1702 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1703 } 1704 1705 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1706 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1707 MLX4_CMD_NATIVE); 1708 if (ret == -ENOMEM) 1709 pr_err("mcg table is full. Fail to register network rule.\n"); 1710 else if (ret == -ENXIO) 1711 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1712 else if (ret) 1713 pr_err("Invalid argument. Fail to register network rule.\n"); 1714 1715 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1716 return ret; 1717 } 1718 1719 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1720 { 1721 int err; 1722 err = mlx4_cmd(dev, reg_id, 0, 0, 1723 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1724 MLX4_CMD_NATIVE); 1725 if (err) 1726 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1727 reg_id); 1728 return err; 1729 } 1730 1731 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1732 u64 *reg_id) 1733 { 1734 void *ib_flow; 1735 union ib_flow_spec *ib_spec; 1736 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1737 int err = 0; 1738 1739 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1740 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1741 return 0; /* do nothing */ 1742 1743 ib_flow = flow_attr + 1; 1744 ib_spec = (union ib_flow_spec *)ib_flow; 1745 1746 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1747 return 0; /* do nothing */ 1748 1749 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1750 flow_attr->port, qp->qp_num, 1751 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1752 reg_id); 1753 return err; 1754 } 1755 1756 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1757 struct ib_flow_attr *flow_attr, 1758 enum mlx4_net_trans_promisc_mode *type) 1759 { 1760 int err = 0; 1761 1762 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1763 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1764 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1765 return -EOPNOTSUPP; 1766 } 1767 1768 if (flow_attr->num_of_specs == 0) { 1769 type[0] = MLX4_FS_MC_SNIFFER; 1770 type[1] = MLX4_FS_UC_SNIFFER; 1771 } else { 1772 union ib_flow_spec *ib_spec; 1773 1774 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1775 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1776 return -EINVAL; 1777 1778 /* if all is zero than MC and UC */ 1779 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1780 type[0] = MLX4_FS_MC_SNIFFER; 1781 type[1] = MLX4_FS_UC_SNIFFER; 1782 } else { 1783 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1784 ib_spec->eth.mask.dst_mac[1], 1785 ib_spec->eth.mask.dst_mac[2], 1786 ib_spec->eth.mask.dst_mac[3], 1787 ib_spec->eth.mask.dst_mac[4], 1788 ib_spec->eth.mask.dst_mac[5]}; 1789 1790 /* Above xor was only on MC bit, non empty mask is valid 1791 * only if this bit is set and rest are zero. 1792 */ 1793 if (!is_zero_ether_addr(&mac[0])) 1794 return -EINVAL; 1795 1796 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1797 type[0] = MLX4_FS_MC_SNIFFER; 1798 else 1799 type[0] = MLX4_FS_UC_SNIFFER; 1800 } 1801 } 1802 1803 return err; 1804 } 1805 1806 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1807 struct ib_flow_attr *flow_attr, 1808 int domain, struct ib_udata *udata) 1809 { 1810 int err = 0, i = 0, j = 0; 1811 struct mlx4_ib_flow *mflow; 1812 enum mlx4_net_trans_promisc_mode type[2]; 1813 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1814 int is_bonded = mlx4_is_bonded(dev); 1815 1816 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1817 return ERR_PTR(-EINVAL); 1818 1819 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1820 return ERR_PTR(-EOPNOTSUPP); 1821 1822 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1823 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1824 return ERR_PTR(-EOPNOTSUPP); 1825 1826 if (udata && 1827 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1828 return ERR_PTR(-EOPNOTSUPP); 1829 1830 memset(type, 0, sizeof(type)); 1831 1832 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1833 if (!mflow) { 1834 err = -ENOMEM; 1835 goto err_free; 1836 } 1837 1838 switch (flow_attr->type) { 1839 case IB_FLOW_ATTR_NORMAL: 1840 /* If dont trap flag (continue match) is set, under specific 1841 * condition traffic be replicated to given qp, 1842 * without stealing it 1843 */ 1844 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1845 err = mlx4_ib_add_dont_trap_rule(dev, 1846 flow_attr, 1847 type); 1848 if (err) 1849 goto err_free; 1850 } else { 1851 type[0] = MLX4_FS_REGULAR; 1852 } 1853 break; 1854 1855 case IB_FLOW_ATTR_ALL_DEFAULT: 1856 type[0] = MLX4_FS_ALL_DEFAULT; 1857 break; 1858 1859 case IB_FLOW_ATTR_MC_DEFAULT: 1860 type[0] = MLX4_FS_MC_DEFAULT; 1861 break; 1862 1863 case IB_FLOW_ATTR_SNIFFER: 1864 type[0] = MLX4_FS_MIRROR_RX_PORT; 1865 type[1] = MLX4_FS_MIRROR_SX_PORT; 1866 break; 1867 1868 default: 1869 err = -EINVAL; 1870 goto err_free; 1871 } 1872 1873 while (i < ARRAY_SIZE(type) && type[i]) { 1874 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1875 &mflow->reg_id[i].id); 1876 if (err) 1877 goto err_create_flow; 1878 if (is_bonded) { 1879 /* Application always sees one port so the mirror rule 1880 * must be on port #2 1881 */ 1882 flow_attr->port = 2; 1883 err = __mlx4_ib_create_flow(qp, flow_attr, 1884 domain, type[j], 1885 &mflow->reg_id[j].mirror); 1886 flow_attr->port = 1; 1887 if (err) 1888 goto err_create_flow; 1889 j++; 1890 } 1891 1892 i++; 1893 } 1894 1895 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1896 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1897 &mflow->reg_id[i].id); 1898 if (err) 1899 goto err_create_flow; 1900 1901 if (is_bonded) { 1902 flow_attr->port = 2; 1903 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1904 &mflow->reg_id[j].mirror); 1905 flow_attr->port = 1; 1906 if (err) 1907 goto err_create_flow; 1908 j++; 1909 } 1910 /* function to create mirror rule */ 1911 i++; 1912 } 1913 1914 return &mflow->ibflow; 1915 1916 err_create_flow: 1917 while (i) { 1918 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1919 mflow->reg_id[i].id); 1920 i--; 1921 } 1922 1923 while (j) { 1924 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1925 mflow->reg_id[j].mirror); 1926 j--; 1927 } 1928 err_free: 1929 kfree(mflow); 1930 return ERR_PTR(err); 1931 } 1932 1933 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1934 { 1935 int err, ret = 0; 1936 int i = 0; 1937 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1938 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1939 1940 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1941 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1942 if (err) 1943 ret = err; 1944 if (mflow->reg_id[i].mirror) { 1945 err = __mlx4_ib_destroy_flow(mdev->dev, 1946 mflow->reg_id[i].mirror); 1947 if (err) 1948 ret = err; 1949 } 1950 i++; 1951 } 1952 1953 kfree(mflow); 1954 return ret; 1955 } 1956 1957 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1958 { 1959 int err; 1960 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1961 struct mlx4_dev *dev = mdev->dev; 1962 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1963 struct mlx4_ib_steering *ib_steering = NULL; 1964 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1965 struct mlx4_flow_reg_id reg_id; 1966 1967 if (mdev->dev->caps.steering_mode == 1968 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1969 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1970 if (!ib_steering) 1971 return -ENOMEM; 1972 } 1973 1974 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1975 !!(mqp->flags & 1976 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1977 prot, ®_id.id); 1978 if (err) { 1979 pr_err("multicast attach op failed, err %d\n", err); 1980 goto err_malloc; 1981 } 1982 1983 reg_id.mirror = 0; 1984 if (mlx4_is_bonded(dev)) { 1985 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1986 (mqp->port == 1) ? 2 : 1, 1987 !!(mqp->flags & 1988 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1989 prot, ®_id.mirror); 1990 if (err) 1991 goto err_add; 1992 } 1993 1994 err = add_gid_entry(ibqp, gid); 1995 if (err) 1996 goto err_add; 1997 1998 if (ib_steering) { 1999 memcpy(ib_steering->gid.raw, gid->raw, 16); 2000 ib_steering->reg_id = reg_id; 2001 mutex_lock(&mqp->mutex); 2002 list_add(&ib_steering->list, &mqp->steering_rules); 2003 mutex_unlock(&mqp->mutex); 2004 } 2005 return 0; 2006 2007 err_add: 2008 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2009 prot, reg_id.id); 2010 if (reg_id.mirror) 2011 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2012 prot, reg_id.mirror); 2013 err_malloc: 2014 kfree(ib_steering); 2015 2016 return err; 2017 } 2018 2019 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2020 { 2021 struct mlx4_ib_gid_entry *ge; 2022 struct mlx4_ib_gid_entry *tmp; 2023 struct mlx4_ib_gid_entry *ret = NULL; 2024 2025 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2026 if (!memcmp(raw, ge->gid.raw, 16)) { 2027 ret = ge; 2028 break; 2029 } 2030 } 2031 2032 return ret; 2033 } 2034 2035 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2036 { 2037 int err; 2038 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2039 struct mlx4_dev *dev = mdev->dev; 2040 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2041 struct net_device *ndev; 2042 struct mlx4_ib_gid_entry *ge; 2043 struct mlx4_flow_reg_id reg_id = {0, 0}; 2044 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2045 2046 if (mdev->dev->caps.steering_mode == 2047 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2048 struct mlx4_ib_steering *ib_steering; 2049 2050 mutex_lock(&mqp->mutex); 2051 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2052 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2053 list_del(&ib_steering->list); 2054 break; 2055 } 2056 } 2057 mutex_unlock(&mqp->mutex); 2058 if (&ib_steering->list == &mqp->steering_rules) { 2059 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2060 return -EINVAL; 2061 } 2062 reg_id = ib_steering->reg_id; 2063 kfree(ib_steering); 2064 } 2065 2066 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2067 prot, reg_id.id); 2068 if (err) 2069 return err; 2070 2071 if (mlx4_is_bonded(dev)) { 2072 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2073 prot, reg_id.mirror); 2074 if (err) 2075 return err; 2076 } 2077 2078 mutex_lock(&mqp->mutex); 2079 ge = find_gid_entry(mqp, gid->raw); 2080 if (ge) { 2081 spin_lock_bh(&mdev->iboe.lock); 2082 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2083 if (ndev) 2084 dev_hold(ndev); 2085 spin_unlock_bh(&mdev->iboe.lock); 2086 if (ndev) 2087 dev_put(ndev); 2088 list_del(&ge->list); 2089 kfree(ge); 2090 } else 2091 pr_warn("could not find mgid entry\n"); 2092 2093 mutex_unlock(&mqp->mutex); 2094 2095 return 0; 2096 } 2097 2098 static int init_node_data(struct mlx4_ib_dev *dev) 2099 { 2100 struct ib_smp *in_mad = NULL; 2101 struct ib_smp *out_mad = NULL; 2102 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2103 int err = -ENOMEM; 2104 2105 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2106 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2107 if (!in_mad || !out_mad) 2108 goto out; 2109 2110 init_query_mad(in_mad); 2111 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2112 if (mlx4_is_master(dev->dev)) 2113 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2114 2115 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2116 if (err) 2117 goto out; 2118 2119 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2120 2121 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2122 2123 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2124 if (err) 2125 goto out; 2126 2127 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2128 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2129 2130 out: 2131 kfree(in_mad); 2132 kfree(out_mad); 2133 return err; 2134 } 2135 2136 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2137 char *buf) 2138 { 2139 struct mlx4_ib_dev *dev = 2140 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2141 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2142 } 2143 2144 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2145 char *buf) 2146 { 2147 struct mlx4_ib_dev *dev = 2148 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2149 return sprintf(buf, "%x\n", dev->dev->rev_id); 2150 } 2151 2152 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2153 char *buf) 2154 { 2155 struct mlx4_ib_dev *dev = 2156 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2157 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2158 dev->dev->board_id); 2159 } 2160 2161 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2162 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2163 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2164 2165 static struct device_attribute *mlx4_class_attributes[] = { 2166 &dev_attr_hw_rev, 2167 &dev_attr_hca_type, 2168 &dev_attr_board_id 2169 }; 2170 2171 struct diag_counter { 2172 const char *name; 2173 u32 offset; 2174 }; 2175 2176 #define DIAG_COUNTER(_name, _offset) \ 2177 { .name = #_name, .offset = _offset } 2178 2179 static const struct diag_counter diag_basic[] = { 2180 DIAG_COUNTER(rq_num_lle, 0x00), 2181 DIAG_COUNTER(sq_num_lle, 0x04), 2182 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2183 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2184 DIAG_COUNTER(rq_num_lpe, 0x18), 2185 DIAG_COUNTER(sq_num_lpe, 0x1C), 2186 DIAG_COUNTER(rq_num_wrfe, 0x20), 2187 DIAG_COUNTER(sq_num_wrfe, 0x24), 2188 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2189 DIAG_COUNTER(sq_num_bre, 0x34), 2190 DIAG_COUNTER(sq_num_rire, 0x44), 2191 DIAG_COUNTER(rq_num_rire, 0x48), 2192 DIAG_COUNTER(sq_num_rae, 0x4C), 2193 DIAG_COUNTER(rq_num_rae, 0x50), 2194 DIAG_COUNTER(sq_num_roe, 0x54), 2195 DIAG_COUNTER(sq_num_tree, 0x5C), 2196 DIAG_COUNTER(sq_num_rree, 0x64), 2197 DIAG_COUNTER(rq_num_rnr, 0x68), 2198 DIAG_COUNTER(sq_num_rnr, 0x6C), 2199 DIAG_COUNTER(rq_num_oos, 0x100), 2200 DIAG_COUNTER(sq_num_oos, 0x104), 2201 }; 2202 2203 static const struct diag_counter diag_ext[] = { 2204 DIAG_COUNTER(rq_num_dup, 0x130), 2205 DIAG_COUNTER(sq_num_to, 0x134), 2206 }; 2207 2208 static const struct diag_counter diag_device_only[] = { 2209 DIAG_COUNTER(num_cqovf, 0x1A0), 2210 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2211 }; 2212 2213 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2214 u8 port_num) 2215 { 2216 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2217 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2218 2219 if (!diag[!!port_num].name) 2220 return NULL; 2221 2222 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2223 diag[!!port_num].num_counters, 2224 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2225 } 2226 2227 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2228 struct rdma_hw_stats *stats, 2229 u8 port, int index) 2230 { 2231 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2232 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2233 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2234 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2235 int ret; 2236 int i; 2237 2238 ret = mlx4_query_diag_counters(dev->dev, 2239 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2240 diag[!!port].offset, hw_value, 2241 diag[!!port].num_counters, port); 2242 2243 if (ret) 2244 return ret; 2245 2246 for (i = 0; i < diag[!!port].num_counters; i++) 2247 stats->value[i] = hw_value[i]; 2248 2249 return diag[!!port].num_counters; 2250 } 2251 2252 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2253 const char ***name, 2254 u32 **offset, 2255 u32 *num, 2256 bool port) 2257 { 2258 u32 num_counters; 2259 2260 num_counters = ARRAY_SIZE(diag_basic); 2261 2262 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2263 num_counters += ARRAY_SIZE(diag_ext); 2264 2265 if (!port) 2266 num_counters += ARRAY_SIZE(diag_device_only); 2267 2268 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2269 if (!*name) 2270 return -ENOMEM; 2271 2272 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2273 if (!*offset) 2274 goto err_name; 2275 2276 *num = num_counters; 2277 2278 return 0; 2279 2280 err_name: 2281 kfree(*name); 2282 return -ENOMEM; 2283 } 2284 2285 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2286 const char **name, 2287 u32 *offset, 2288 bool port) 2289 { 2290 int i; 2291 int j; 2292 2293 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2294 name[i] = diag_basic[i].name; 2295 offset[i] = diag_basic[i].offset; 2296 } 2297 2298 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2299 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2300 name[j] = diag_ext[i].name; 2301 offset[j] = diag_ext[i].offset; 2302 } 2303 } 2304 2305 if (!port) { 2306 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2307 name[j] = diag_device_only[i].name; 2308 offset[j] = diag_device_only[i].offset; 2309 } 2310 } 2311 } 2312 2313 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2314 { 2315 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2316 int i; 2317 int ret; 2318 bool per_port = !!(ibdev->dev->caps.flags2 & 2319 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2320 2321 if (mlx4_is_slave(ibdev->dev)) 2322 return 0; 2323 2324 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2325 /* i == 1 means we are building port counters */ 2326 if (i && !per_port) 2327 continue; 2328 2329 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2330 &diag[i].offset, 2331 &diag[i].num_counters, i); 2332 if (ret) 2333 goto err_alloc; 2334 2335 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2336 diag[i].offset, i); 2337 } 2338 2339 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2340 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2341 2342 return 0; 2343 2344 err_alloc: 2345 if (i) { 2346 kfree(diag[i - 1].name); 2347 kfree(diag[i - 1].offset); 2348 } 2349 2350 return ret; 2351 } 2352 2353 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2354 { 2355 int i; 2356 2357 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2358 kfree(ibdev->diag_counters[i].offset); 2359 kfree(ibdev->diag_counters[i].name); 2360 } 2361 } 2362 2363 #define MLX4_IB_INVALID_MAC ((u64)-1) 2364 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2365 struct net_device *dev, 2366 int port) 2367 { 2368 u64 new_smac = 0; 2369 u64 release_mac = MLX4_IB_INVALID_MAC; 2370 struct mlx4_ib_qp *qp; 2371 2372 read_lock(&dev_base_lock); 2373 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2374 read_unlock(&dev_base_lock); 2375 2376 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2377 2378 /* no need for update QP1 and mac registration in non-SRIOV */ 2379 if (!mlx4_is_mfunc(ibdev->dev)) 2380 return; 2381 2382 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2383 qp = ibdev->qp1_proxy[port - 1]; 2384 if (qp) { 2385 int new_smac_index; 2386 u64 old_smac; 2387 struct mlx4_update_qp_params update_params; 2388 2389 mutex_lock(&qp->mutex); 2390 old_smac = qp->pri.smac; 2391 if (new_smac == old_smac) 2392 goto unlock; 2393 2394 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2395 2396 if (new_smac_index < 0) 2397 goto unlock; 2398 2399 update_params.smac_index = new_smac_index; 2400 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2401 &update_params)) { 2402 release_mac = new_smac; 2403 goto unlock; 2404 } 2405 /* if old port was zero, no mac was yet registered for this QP */ 2406 if (qp->pri.smac_port) 2407 release_mac = old_smac; 2408 qp->pri.smac = new_smac; 2409 qp->pri.smac_port = port; 2410 qp->pri.smac_index = new_smac_index; 2411 } 2412 2413 unlock: 2414 if (release_mac != MLX4_IB_INVALID_MAC) 2415 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2416 if (qp) 2417 mutex_unlock(&qp->mutex); 2418 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2419 } 2420 2421 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2422 struct net_device *dev, 2423 unsigned long event) 2424 2425 { 2426 struct mlx4_ib_iboe *iboe; 2427 int update_qps_port = -1; 2428 int port; 2429 2430 ASSERT_RTNL(); 2431 2432 iboe = &ibdev->iboe; 2433 2434 spin_lock_bh(&iboe->lock); 2435 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2436 2437 iboe->netdevs[port - 1] = 2438 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2439 2440 if (dev == iboe->netdevs[port - 1] && 2441 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2442 event == NETDEV_UP || event == NETDEV_CHANGE)) 2443 update_qps_port = port; 2444 2445 } 2446 spin_unlock_bh(&iboe->lock); 2447 2448 if (update_qps_port > 0) 2449 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2450 } 2451 2452 static int mlx4_ib_netdev_event(struct notifier_block *this, 2453 unsigned long event, void *ptr) 2454 { 2455 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2456 struct mlx4_ib_dev *ibdev; 2457 2458 if (!net_eq(dev_net(dev), &init_net)) 2459 return NOTIFY_DONE; 2460 2461 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2462 mlx4_ib_scan_netdevs(ibdev, dev, event); 2463 2464 return NOTIFY_DONE; 2465 } 2466 2467 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2468 { 2469 int port; 2470 int slave; 2471 int i; 2472 2473 if (mlx4_is_master(ibdev->dev)) { 2474 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2475 ++slave) { 2476 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2477 for (i = 0; 2478 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2479 ++i) { 2480 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2481 /* master has the identity virt2phys pkey mapping */ 2482 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2483 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2484 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2485 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2486 } 2487 } 2488 } 2489 /* initialize pkey cache */ 2490 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2491 for (i = 0; 2492 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2493 ++i) 2494 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2495 (i) ? 0 : 0xFFFF; 2496 } 2497 } 2498 } 2499 2500 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2501 { 2502 int i, j, eq = 0, total_eqs = 0; 2503 2504 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2505 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2506 if (!ibdev->eq_table) 2507 return; 2508 2509 for (i = 1; i <= dev->caps.num_ports; i++) { 2510 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2511 j++, total_eqs++) { 2512 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2513 continue; 2514 ibdev->eq_table[eq] = total_eqs; 2515 if (!mlx4_assign_eq(dev, i, 2516 &ibdev->eq_table[eq])) 2517 eq++; 2518 else 2519 ibdev->eq_table[eq] = -1; 2520 } 2521 } 2522 2523 for (i = eq; i < dev->caps.num_comp_vectors; 2524 ibdev->eq_table[i++] = -1) 2525 ; 2526 2527 /* Advertise the new number of EQs to clients */ 2528 ibdev->ib_dev.num_comp_vectors = eq; 2529 } 2530 2531 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2532 { 2533 int i; 2534 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2535 2536 /* no eqs were allocated */ 2537 if (!ibdev->eq_table) 2538 return; 2539 2540 /* Reset the advertised EQ number */ 2541 ibdev->ib_dev.num_comp_vectors = 0; 2542 2543 for (i = 0; i < total_eqs; i++) 2544 mlx4_release_eq(dev, ibdev->eq_table[i]); 2545 2546 kfree(ibdev->eq_table); 2547 ibdev->eq_table = NULL; 2548 } 2549 2550 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2551 struct ib_port_immutable *immutable) 2552 { 2553 struct ib_port_attr attr; 2554 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2555 int err; 2556 2557 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2558 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2559 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2560 } else { 2561 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2562 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2563 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2564 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2565 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2566 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2567 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2568 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2569 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2570 } 2571 2572 err = ib_query_port(ibdev, port_num, &attr); 2573 if (err) 2574 return err; 2575 2576 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2577 immutable->gid_tbl_len = attr.gid_tbl_len; 2578 2579 return 0; 2580 } 2581 2582 static void get_fw_ver_str(struct ib_device *device, char *str) 2583 { 2584 struct mlx4_ib_dev *dev = 2585 container_of(device, struct mlx4_ib_dev, ib_dev); 2586 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2587 (int) (dev->dev->caps.fw_ver >> 32), 2588 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2589 (int) dev->dev->caps.fw_ver & 0xffff); 2590 } 2591 2592 static void *mlx4_ib_add(struct mlx4_dev *dev) 2593 { 2594 struct mlx4_ib_dev *ibdev; 2595 int num_ports = 0; 2596 int i, j; 2597 int err; 2598 struct mlx4_ib_iboe *iboe; 2599 int ib_num_ports = 0; 2600 int num_req_counters; 2601 int allocated; 2602 u32 counter_index; 2603 struct counter_index *new_counter_index = NULL; 2604 2605 pr_info_once("%s", mlx4_ib_version); 2606 2607 num_ports = 0; 2608 mlx4_foreach_ib_transport_port(i, dev) 2609 num_ports++; 2610 2611 /* No point in registering a device with no ports... */ 2612 if (num_ports == 0) 2613 return NULL; 2614 2615 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2616 if (!ibdev) { 2617 dev_err(&dev->persist->pdev->dev, 2618 "Device struct alloc failed\n"); 2619 return NULL; 2620 } 2621 2622 iboe = &ibdev->iboe; 2623 2624 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2625 goto err_dealloc; 2626 2627 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2628 goto err_pd; 2629 2630 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2631 PAGE_SIZE); 2632 if (!ibdev->uar_map) 2633 goto err_uar; 2634 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2635 2636 ibdev->dev = dev; 2637 ibdev->bond_next_port = 0; 2638 2639 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2640 ibdev->ib_dev.owner = THIS_MODULE; 2641 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2642 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2643 ibdev->num_ports = num_ports; 2644 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2645 1 : ibdev->num_ports; 2646 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2647 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2648 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2649 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2650 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2651 2652 if (dev->caps.userspace_caps) 2653 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2654 else 2655 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2656 2657 ibdev->ib_dev.uverbs_cmd_mask = 2658 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2659 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2660 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2661 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2662 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2663 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2664 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2665 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2666 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2667 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2668 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2669 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2670 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2671 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2672 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2673 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2674 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2675 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2676 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2677 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2678 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2679 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2680 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2681 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2682 2683 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2684 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2685 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2686 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2687 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2688 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2689 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2690 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2691 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2692 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2693 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2694 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2695 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2696 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2697 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2698 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2699 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2700 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2701 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2702 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2703 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2704 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2705 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2706 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2707 ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq; 2708 ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq; 2709 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2710 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2711 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2712 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2713 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2714 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2715 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2716 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2717 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2718 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2719 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2720 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2721 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2722 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2723 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2724 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2725 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2726 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2727 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2728 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2729 2730 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2731 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2732 2733 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2734 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2735 IB_LINK_LAYER_ETHERNET) || 2736 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2737 IB_LINK_LAYER_ETHERNET))) { 2738 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2739 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2740 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2741 ibdev->ib_dev.create_rwq_ind_table = 2742 mlx4_ib_create_rwq_ind_table; 2743 ibdev->ib_dev.destroy_rwq_ind_table = 2744 mlx4_ib_destroy_rwq_ind_table; 2745 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2746 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2747 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2748 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2749 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2750 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2751 } 2752 2753 if (!mlx4_is_slave(ibdev->dev)) { 2754 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2755 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2756 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2757 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2758 } 2759 2760 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2761 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2762 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2763 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2764 2765 ibdev->ib_dev.uverbs_cmd_mask |= 2766 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2767 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2768 } 2769 2770 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2771 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2772 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2773 ibdev->ib_dev.uverbs_cmd_mask |= 2774 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2775 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2776 } 2777 2778 if (check_flow_steering_support(dev)) { 2779 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2780 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2781 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2782 2783 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2784 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2785 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2786 } 2787 2788 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2789 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2790 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2791 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2792 2793 mlx4_ib_alloc_eqs(dev, ibdev); 2794 2795 spin_lock_init(&iboe->lock); 2796 2797 if (init_node_data(ibdev)) 2798 goto err_map; 2799 mlx4_init_sl2vl_tbl(ibdev); 2800 2801 for (i = 0; i < ibdev->num_ports; ++i) { 2802 mutex_init(&ibdev->counters_table[i].mutex); 2803 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2804 } 2805 2806 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2807 for (i = 0; i < num_req_counters; ++i) { 2808 mutex_init(&ibdev->qp1_proxy_lock[i]); 2809 allocated = 0; 2810 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2811 IB_LINK_LAYER_ETHERNET) { 2812 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2813 MLX4_RES_USAGE_DRIVER); 2814 /* if failed to allocate a new counter, use default */ 2815 if (err) 2816 counter_index = 2817 mlx4_get_default_counter_index(dev, 2818 i + 1); 2819 else 2820 allocated = 1; 2821 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2822 counter_index = mlx4_get_default_counter_index(dev, 2823 i + 1); 2824 } 2825 new_counter_index = kmalloc(sizeof(*new_counter_index), 2826 GFP_KERNEL); 2827 if (!new_counter_index) { 2828 if (allocated) 2829 mlx4_counter_free(ibdev->dev, counter_index); 2830 goto err_counter; 2831 } 2832 new_counter_index->index = counter_index; 2833 new_counter_index->allocated = allocated; 2834 list_add_tail(&new_counter_index->list, 2835 &ibdev->counters_table[i].counters_list); 2836 ibdev->counters_table[i].default_counter = counter_index; 2837 pr_info("counter index %d for port %d allocated %d\n", 2838 counter_index, i + 1, allocated); 2839 } 2840 if (mlx4_is_bonded(dev)) 2841 for (i = 1; i < ibdev->num_ports ; ++i) { 2842 new_counter_index = 2843 kmalloc(sizeof(struct counter_index), 2844 GFP_KERNEL); 2845 if (!new_counter_index) 2846 goto err_counter; 2847 new_counter_index->index = counter_index; 2848 new_counter_index->allocated = 0; 2849 list_add_tail(&new_counter_index->list, 2850 &ibdev->counters_table[i].counters_list); 2851 ibdev->counters_table[i].default_counter = 2852 counter_index; 2853 } 2854 2855 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2856 ib_num_ports++; 2857 2858 spin_lock_init(&ibdev->sm_lock); 2859 mutex_init(&ibdev->cap_mask_mutex); 2860 INIT_LIST_HEAD(&ibdev->qp_list); 2861 spin_lock_init(&ibdev->reset_flow_resource_lock); 2862 2863 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2864 ib_num_ports) { 2865 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2866 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2867 MLX4_IB_UC_STEER_QPN_ALIGN, 2868 &ibdev->steer_qpn_base, 0, 2869 MLX4_RES_USAGE_DRIVER); 2870 if (err) 2871 goto err_counter; 2872 2873 ibdev->ib_uc_qpns_bitmap = 2874 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2875 sizeof(long), 2876 GFP_KERNEL); 2877 if (!ibdev->ib_uc_qpns_bitmap) 2878 goto err_steer_qp_release; 2879 2880 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2881 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2882 ibdev->steer_qpn_count); 2883 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2884 dev, ibdev->steer_qpn_base, 2885 ibdev->steer_qpn_base + 2886 ibdev->steer_qpn_count - 1); 2887 if (err) 2888 goto err_steer_free_bitmap; 2889 } else { 2890 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2891 ibdev->steer_qpn_count); 2892 } 2893 } 2894 2895 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2896 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2897 2898 if (mlx4_ib_alloc_diag_counters(ibdev)) 2899 goto err_steer_free_bitmap; 2900 2901 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4; 2902 if (ib_register_device(&ibdev->ib_dev, NULL)) 2903 goto err_diag_counters; 2904 2905 if (mlx4_ib_mad_init(ibdev)) 2906 goto err_reg; 2907 2908 if (mlx4_ib_init_sriov(ibdev)) 2909 goto err_mad; 2910 2911 if (!iboe->nb.notifier_call) { 2912 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2913 err = register_netdevice_notifier(&iboe->nb); 2914 if (err) { 2915 iboe->nb.notifier_call = NULL; 2916 goto err_notif; 2917 } 2918 } 2919 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2920 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2921 if (err) 2922 goto err_notif; 2923 } 2924 2925 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2926 if (device_create_file(&ibdev->ib_dev.dev, 2927 mlx4_class_attributes[j])) 2928 goto err_notif; 2929 } 2930 2931 ibdev->ib_active = true; 2932 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2933 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2934 &ibdev->ib_dev); 2935 2936 if (mlx4_is_mfunc(ibdev->dev)) 2937 init_pkeys(ibdev); 2938 2939 /* create paravirt contexts for any VFs which are active */ 2940 if (mlx4_is_master(ibdev->dev)) { 2941 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2942 if (j == mlx4_master_func_num(ibdev->dev)) 2943 continue; 2944 if (mlx4_is_slave_active(ibdev->dev, j)) 2945 do_slave_init(ibdev, j, 1); 2946 } 2947 } 2948 return ibdev; 2949 2950 err_notif: 2951 if (ibdev->iboe.nb.notifier_call) { 2952 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2953 pr_warn("failure unregistering notifier\n"); 2954 ibdev->iboe.nb.notifier_call = NULL; 2955 } 2956 flush_workqueue(wq); 2957 2958 mlx4_ib_close_sriov(ibdev); 2959 2960 err_mad: 2961 mlx4_ib_mad_cleanup(ibdev); 2962 2963 err_reg: 2964 ib_unregister_device(&ibdev->ib_dev); 2965 2966 err_diag_counters: 2967 mlx4_ib_diag_cleanup(ibdev); 2968 2969 err_steer_free_bitmap: 2970 kfree(ibdev->ib_uc_qpns_bitmap); 2971 2972 err_steer_qp_release: 2973 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2974 ibdev->steer_qpn_count); 2975 err_counter: 2976 for (i = 0; i < ibdev->num_ports; ++i) 2977 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2978 2979 err_map: 2980 mlx4_ib_free_eqs(dev, ibdev); 2981 iounmap(ibdev->uar_map); 2982 2983 err_uar: 2984 mlx4_uar_free(dev, &ibdev->priv_uar); 2985 2986 err_pd: 2987 mlx4_pd_free(dev, ibdev->priv_pdn); 2988 2989 err_dealloc: 2990 ib_dealloc_device(&ibdev->ib_dev); 2991 2992 return NULL; 2993 } 2994 2995 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2996 { 2997 int offset; 2998 2999 WARN_ON(!dev->ib_uc_qpns_bitmap); 3000 3001 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 3002 dev->steer_qpn_count, 3003 get_count_order(count)); 3004 if (offset < 0) 3005 return offset; 3006 3007 *qpn = dev->steer_qpn_base + offset; 3008 return 0; 3009 } 3010 3011 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 3012 { 3013 if (!qpn || 3014 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 3015 return; 3016 3017 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 3018 qpn, dev->steer_qpn_base)) 3019 /* not supposed to be here */ 3020 return; 3021 3022 bitmap_release_region(dev->ib_uc_qpns_bitmap, 3023 qpn - dev->steer_qpn_base, 3024 get_count_order(count)); 3025 } 3026 3027 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 3028 int is_attach) 3029 { 3030 int err; 3031 size_t flow_size; 3032 struct ib_flow_attr *flow = NULL; 3033 struct ib_flow_spec_ib *ib_spec; 3034 3035 if (is_attach) { 3036 flow_size = sizeof(struct ib_flow_attr) + 3037 sizeof(struct ib_flow_spec_ib); 3038 flow = kzalloc(flow_size, GFP_KERNEL); 3039 if (!flow) 3040 return -ENOMEM; 3041 flow->port = mqp->port; 3042 flow->num_of_specs = 1; 3043 flow->size = flow_size; 3044 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3045 ib_spec->type = IB_FLOW_SPEC_IB; 3046 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3047 /* Add an empty rule for IB L2 */ 3048 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3049 3050 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3051 IB_FLOW_DOMAIN_NIC, 3052 MLX4_FS_REGULAR, 3053 &mqp->reg_id); 3054 } else { 3055 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3056 } 3057 kfree(flow); 3058 return err; 3059 } 3060 3061 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3062 { 3063 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3064 int p; 3065 int i; 3066 3067 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3068 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3069 ibdev->ib_active = false; 3070 flush_workqueue(wq); 3071 3072 mlx4_ib_close_sriov(ibdev); 3073 mlx4_ib_mad_cleanup(ibdev); 3074 ib_unregister_device(&ibdev->ib_dev); 3075 mlx4_ib_diag_cleanup(ibdev); 3076 if (ibdev->iboe.nb.notifier_call) { 3077 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3078 pr_warn("failure unregistering notifier\n"); 3079 ibdev->iboe.nb.notifier_call = NULL; 3080 } 3081 3082 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3083 ibdev->steer_qpn_count); 3084 kfree(ibdev->ib_uc_qpns_bitmap); 3085 3086 iounmap(ibdev->uar_map); 3087 for (p = 0; p < ibdev->num_ports; ++p) 3088 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3089 3090 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3091 mlx4_CLOSE_PORT(dev, p); 3092 3093 mlx4_ib_free_eqs(dev, ibdev); 3094 3095 mlx4_uar_free(dev, &ibdev->priv_uar); 3096 mlx4_pd_free(dev, ibdev->priv_pdn); 3097 ib_dealloc_device(&ibdev->ib_dev); 3098 } 3099 3100 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3101 { 3102 struct mlx4_ib_demux_work **dm = NULL; 3103 struct mlx4_dev *dev = ibdev->dev; 3104 int i; 3105 unsigned long flags; 3106 struct mlx4_active_ports actv_ports; 3107 unsigned int ports; 3108 unsigned int first_port; 3109 3110 if (!mlx4_is_master(dev)) 3111 return; 3112 3113 actv_ports = mlx4_get_active_ports(dev, slave); 3114 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3115 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3116 3117 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3118 if (!dm) 3119 return; 3120 3121 for (i = 0; i < ports; i++) { 3122 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3123 if (!dm[i]) { 3124 while (--i >= 0) 3125 kfree(dm[i]); 3126 goto out; 3127 } 3128 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3129 dm[i]->port = first_port + i + 1; 3130 dm[i]->slave = slave; 3131 dm[i]->do_init = do_init; 3132 dm[i]->dev = ibdev; 3133 } 3134 /* initialize or tear down tunnel QPs for the slave */ 3135 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3136 if (!ibdev->sriov.is_going_down) { 3137 for (i = 0; i < ports; i++) 3138 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3139 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3140 } else { 3141 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3142 for (i = 0; i < ports; i++) 3143 kfree(dm[i]); 3144 } 3145 out: 3146 kfree(dm); 3147 return; 3148 } 3149 3150 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3151 { 3152 struct mlx4_ib_qp *mqp; 3153 unsigned long flags_qp; 3154 unsigned long flags_cq; 3155 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3156 struct list_head cq_notify_list; 3157 struct mlx4_cq *mcq; 3158 unsigned long flags; 3159 3160 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3161 INIT_LIST_HEAD(&cq_notify_list); 3162 3163 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3164 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3165 3166 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3167 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3168 if (mqp->sq.tail != mqp->sq.head) { 3169 send_mcq = to_mcq(mqp->ibqp.send_cq); 3170 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3171 if (send_mcq->mcq.comp && 3172 mqp->ibqp.send_cq->comp_handler) { 3173 if (!send_mcq->mcq.reset_notify_added) { 3174 send_mcq->mcq.reset_notify_added = 1; 3175 list_add_tail(&send_mcq->mcq.reset_notify, 3176 &cq_notify_list); 3177 } 3178 } 3179 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3180 } 3181 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3182 /* Now, handle the QP's receive queue */ 3183 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3184 /* no handling is needed for SRQ */ 3185 if (!mqp->ibqp.srq) { 3186 if (mqp->rq.tail != mqp->rq.head) { 3187 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3188 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3189 if (recv_mcq->mcq.comp && 3190 mqp->ibqp.recv_cq->comp_handler) { 3191 if (!recv_mcq->mcq.reset_notify_added) { 3192 recv_mcq->mcq.reset_notify_added = 1; 3193 list_add_tail(&recv_mcq->mcq.reset_notify, 3194 &cq_notify_list); 3195 } 3196 } 3197 spin_unlock_irqrestore(&recv_mcq->lock, 3198 flags_cq); 3199 } 3200 } 3201 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3202 } 3203 3204 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3205 mcq->comp(mcq); 3206 } 3207 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3208 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3209 } 3210 3211 static void handle_bonded_port_state_event(struct work_struct *work) 3212 { 3213 struct ib_event_work *ew = 3214 container_of(work, struct ib_event_work, work); 3215 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3216 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3217 int i; 3218 struct ib_event ibev; 3219 3220 kfree(ew); 3221 spin_lock_bh(&ibdev->iboe.lock); 3222 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3223 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3224 enum ib_port_state curr_port_state; 3225 3226 if (!curr_netdev) 3227 continue; 3228 3229 curr_port_state = 3230 (netif_running(curr_netdev) && 3231 netif_carrier_ok(curr_netdev)) ? 3232 IB_PORT_ACTIVE : IB_PORT_DOWN; 3233 3234 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3235 curr_port_state : IB_PORT_ACTIVE; 3236 } 3237 spin_unlock_bh(&ibdev->iboe.lock); 3238 3239 ibev.device = &ibdev->ib_dev; 3240 ibev.element.port_num = 1; 3241 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3242 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3243 3244 ib_dispatch_event(&ibev); 3245 } 3246 3247 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3248 { 3249 u64 sl2vl; 3250 int err; 3251 3252 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3253 if (err) { 3254 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3255 port, err); 3256 sl2vl = 0; 3257 } 3258 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3259 } 3260 3261 static void ib_sl2vl_update_work(struct work_struct *work) 3262 { 3263 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3264 struct mlx4_ib_dev *mdev = ew->ib_dev; 3265 int port = ew->port; 3266 3267 mlx4_ib_sl2vl_update(mdev, port); 3268 3269 kfree(ew); 3270 } 3271 3272 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3273 int port) 3274 { 3275 struct ib_event_work *ew; 3276 3277 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3278 if (ew) { 3279 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3280 ew->port = port; 3281 ew->ib_dev = ibdev; 3282 queue_work(wq, &ew->work); 3283 } 3284 } 3285 3286 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3287 enum mlx4_dev_event event, unsigned long param) 3288 { 3289 struct ib_event ibev; 3290 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3291 struct mlx4_eqe *eqe = NULL; 3292 struct ib_event_work *ew; 3293 int p = 0; 3294 3295 if (mlx4_is_bonded(dev) && 3296 ((event == MLX4_DEV_EVENT_PORT_UP) || 3297 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3298 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3299 if (!ew) 3300 return; 3301 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3302 ew->ib_dev = ibdev; 3303 queue_work(wq, &ew->work); 3304 return; 3305 } 3306 3307 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3308 eqe = (struct mlx4_eqe *)param; 3309 else 3310 p = (int) param; 3311 3312 switch (event) { 3313 case MLX4_DEV_EVENT_PORT_UP: 3314 if (p > ibdev->num_ports) 3315 return; 3316 if (!mlx4_is_slave(dev) && 3317 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3318 IB_LINK_LAYER_INFINIBAND) { 3319 if (mlx4_is_master(dev)) 3320 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3321 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3322 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3323 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3324 } 3325 ibev.event = IB_EVENT_PORT_ACTIVE; 3326 break; 3327 3328 case MLX4_DEV_EVENT_PORT_DOWN: 3329 if (p > ibdev->num_ports) 3330 return; 3331 ibev.event = IB_EVENT_PORT_ERR; 3332 break; 3333 3334 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3335 ibdev->ib_active = false; 3336 ibev.event = IB_EVENT_DEVICE_FATAL; 3337 mlx4_ib_handle_catas_error(ibdev); 3338 break; 3339 3340 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3341 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3342 if (!ew) 3343 break; 3344 3345 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3346 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3347 ew->ib_dev = ibdev; 3348 /* need to queue only for port owner, which uses GEN_EQE */ 3349 if (mlx4_is_master(dev)) 3350 queue_work(wq, &ew->work); 3351 else 3352 handle_port_mgmt_change_event(&ew->work); 3353 return; 3354 3355 case MLX4_DEV_EVENT_SLAVE_INIT: 3356 /* here, p is the slave id */ 3357 do_slave_init(ibdev, p, 1); 3358 if (mlx4_is_master(dev)) { 3359 int i; 3360 3361 for (i = 1; i <= ibdev->num_ports; i++) { 3362 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3363 == IB_LINK_LAYER_INFINIBAND) 3364 mlx4_ib_slave_alias_guid_event(ibdev, 3365 p, i, 3366 1); 3367 } 3368 } 3369 return; 3370 3371 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3372 if (mlx4_is_master(dev)) { 3373 int i; 3374 3375 for (i = 1; i <= ibdev->num_ports; i++) { 3376 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3377 == IB_LINK_LAYER_INFINIBAND) 3378 mlx4_ib_slave_alias_guid_event(ibdev, 3379 p, i, 3380 0); 3381 } 3382 } 3383 /* here, p is the slave id */ 3384 do_slave_init(ibdev, p, 0); 3385 return; 3386 3387 default: 3388 return; 3389 } 3390 3391 ibev.device = ibdev_ptr; 3392 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3393 3394 ib_dispatch_event(&ibev); 3395 } 3396 3397 static struct mlx4_interface mlx4_ib_interface = { 3398 .add = mlx4_ib_add, 3399 .remove = mlx4_ib_remove, 3400 .event = mlx4_ib_event, 3401 .protocol = MLX4_PROT_IB_IPV6, 3402 .flags = MLX4_INTFF_BONDING 3403 }; 3404 3405 static int __init mlx4_ib_init(void) 3406 { 3407 int err; 3408 3409 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3410 if (!wq) 3411 return -ENOMEM; 3412 3413 err = mlx4_ib_mcg_init(); 3414 if (err) 3415 goto clean_wq; 3416 3417 err = mlx4_register_interface(&mlx4_ib_interface); 3418 if (err) 3419 goto clean_mcg; 3420 3421 return 0; 3422 3423 clean_mcg: 3424 mlx4_ib_mcg_destroy(); 3425 3426 clean_wq: 3427 destroy_workqueue(wq); 3428 return err; 3429 } 3430 3431 static void __exit mlx4_ib_cleanup(void) 3432 { 3433 mlx4_unregister_interface(&mlx4_ib_interface); 3434 mlx4_ib_mcg_destroy(); 3435 destroy_workqueue(wq); 3436 } 3437 3438 module_init(mlx4_ib_init); 3439 module_exit(mlx4_ib_cleanup); 3440