1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 else 223 memset(&gid_tbl[i].gid, 0, 12); 224 } 225 } 226 227 err = mlx4_cmd(dev, mailbox->dma, 228 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 229 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 230 MLX4_CMD_WRAPPED); 231 if (mlx4_is_bonded(dev)) 232 err += mlx4_cmd(dev, mailbox->dma, 233 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 234 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 235 MLX4_CMD_WRAPPED); 236 237 mlx4_free_cmd_mailbox(dev, mailbox); 238 return err; 239 } 240 241 static int mlx4_ib_update_gids(struct gid_entry *gids, 242 struct mlx4_ib_dev *ibdev, 243 u8 port_num) 244 { 245 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 246 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 247 248 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 249 } 250 251 static int mlx4_ib_add_gid(struct ib_device *device, 252 u8 port_num, 253 unsigned int index, 254 const union ib_gid *gid, 255 const struct ib_gid_attr *attr, 256 void **context) 257 { 258 struct mlx4_ib_dev *ibdev = to_mdev(device); 259 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 260 struct mlx4_port_gid_table *port_gid_table; 261 int free = -1, found = -1; 262 int ret = 0; 263 int hw_update = 0; 264 int i; 265 struct gid_entry *gids = NULL; 266 267 if (!rdma_cap_roce_gid_table(device, port_num)) 268 return -EINVAL; 269 270 if (port_num > MLX4_MAX_PORTS) 271 return -EINVAL; 272 273 if (!context) 274 return -EINVAL; 275 276 port_gid_table = &iboe->gids[port_num - 1]; 277 spin_lock_bh(&iboe->lock); 278 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 279 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) && 280 (port_gid_table->gids[i].gid_type == attr->gid_type)) { 281 found = i; 282 break; 283 } 284 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid))) 285 free = i; /* HW has space */ 286 } 287 288 if (found < 0) { 289 if (free < 0) { 290 ret = -ENOSPC; 291 } else { 292 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 293 if (!port_gid_table->gids[free].ctx) { 294 ret = -ENOMEM; 295 } else { 296 *context = port_gid_table->gids[free].ctx; 297 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid)); 298 port_gid_table->gids[free].gid_type = attr->gid_type; 299 port_gid_table->gids[free].ctx->real_index = free; 300 port_gid_table->gids[free].ctx->refcount = 1; 301 hw_update = 1; 302 } 303 } 304 } else { 305 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 306 *context = ctx; 307 ctx->refcount++; 308 } 309 if (!ret && hw_update) { 310 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 311 if (!gids) { 312 ret = -ENOMEM; 313 } else { 314 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 315 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 316 gids[i].gid_type = port_gid_table->gids[i].gid_type; 317 } 318 } 319 } 320 spin_unlock_bh(&iboe->lock); 321 322 if (!ret && hw_update) { 323 ret = mlx4_ib_update_gids(gids, ibdev, port_num); 324 kfree(gids); 325 } 326 327 return ret; 328 } 329 330 static int mlx4_ib_del_gid(struct ib_device *device, 331 u8 port_num, 332 unsigned int index, 333 void **context) 334 { 335 struct gid_cache_context *ctx = *context; 336 struct mlx4_ib_dev *ibdev = to_mdev(device); 337 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 338 struct mlx4_port_gid_table *port_gid_table; 339 int ret = 0; 340 int hw_update = 0; 341 struct gid_entry *gids = NULL; 342 343 if (!rdma_cap_roce_gid_table(device, port_num)) 344 return -EINVAL; 345 346 if (port_num > MLX4_MAX_PORTS) 347 return -EINVAL; 348 349 port_gid_table = &iboe->gids[port_num - 1]; 350 spin_lock_bh(&iboe->lock); 351 if (ctx) { 352 ctx->refcount--; 353 if (!ctx->refcount) { 354 unsigned int real_index = ctx->real_index; 355 356 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid)); 357 kfree(port_gid_table->gids[real_index].ctx); 358 port_gid_table->gids[real_index].ctx = NULL; 359 hw_update = 1; 360 } 361 } 362 if (!ret && hw_update) { 363 int i; 364 365 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 366 if (!gids) { 367 ret = -ENOMEM; 368 } else { 369 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) 370 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 u8 port_num, int index) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 union ib_gid gid; 388 struct mlx4_port_gid_table *port_gid_table; 389 int real_index = -EINVAL; 390 int i; 391 int ret; 392 unsigned long flags; 393 struct ib_gid_attr attr; 394 395 if (port_num > MLX4_MAX_PORTS) 396 return -EINVAL; 397 398 if (mlx4_is_bonded(ibdev->dev)) 399 port_num = 1; 400 401 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 402 return index; 403 404 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr); 405 if (ret) 406 return ret; 407 408 if (attr.ndev) 409 dev_put(attr.ndev); 410 411 if (!memcmp(&gid, &zgid, sizeof(gid))) 412 return -EINVAL; 413 414 spin_lock_irqsave(&iboe->lock, flags); 415 port_gid_table = &iboe->gids[port_num - 1]; 416 417 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 418 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) && 419 attr.gid_type == port_gid_table->gids[i].gid_type) { 420 ctx = port_gid_table->gids[i].ctx; 421 break; 422 } 423 if (ctx) 424 real_index = ctx->real_index; 425 spin_unlock_irqrestore(&iboe->lock, flags); 426 return real_index; 427 } 428 429 static int mlx4_ib_query_device(struct ib_device *ibdev, 430 struct ib_device_attr *props, 431 struct ib_udata *uhw) 432 { 433 struct mlx4_ib_dev *dev = to_mdev(ibdev); 434 struct ib_smp *in_mad = NULL; 435 struct ib_smp *out_mad = NULL; 436 int err; 437 int have_ib_ports; 438 struct mlx4_uverbs_ex_query_device cmd; 439 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 440 struct mlx4_clock_params clock_params; 441 442 if (uhw->inlen) { 443 if (uhw->inlen < sizeof(cmd)) 444 return -EINVAL; 445 446 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 447 if (err) 448 return err; 449 450 if (cmd.comp_mask) 451 return -EINVAL; 452 453 if (cmd.reserved) 454 return -EINVAL; 455 } 456 457 resp.response_length = offsetof(typeof(resp), response_length) + 458 sizeof(resp.response_length); 459 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 460 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 461 err = -ENOMEM; 462 if (!in_mad || !out_mad) 463 goto out; 464 465 init_query_mad(in_mad); 466 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 467 468 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 469 1, NULL, NULL, in_mad, out_mad); 470 if (err) 471 goto out; 472 473 memset(props, 0, sizeof *props); 474 475 have_ib_ports = num_ib_ports(dev->dev); 476 477 props->fw_ver = dev->dev->caps.fw_ver; 478 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 479 IB_DEVICE_PORT_ACTIVE_EVENT | 480 IB_DEVICE_SYS_IMAGE_GUID | 481 IB_DEVICE_RC_RNR_NAK_GEN | 482 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 484 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 486 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 488 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 489 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 490 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 491 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 492 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 493 if (dev->dev->caps.max_gso_sz && 494 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 495 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 496 props->device_cap_flags |= IB_DEVICE_UD_TSO; 497 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 498 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 499 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 500 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 501 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 502 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 503 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 504 props->device_cap_flags |= IB_DEVICE_XRC; 505 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 506 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 507 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 508 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 509 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 510 else 511 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 512 } 513 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 514 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 515 516 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 517 518 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 519 0xffffff; 520 props->vendor_part_id = dev->dev->persist->pdev->device; 521 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 522 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 523 524 props->max_mr_size = ~0ull; 525 props->page_size_cap = dev->dev->caps.page_size_cap; 526 props->max_qp = dev->dev->quotas.qp; 527 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 528 props->max_sge = min(dev->dev->caps.max_sq_sg, 529 dev->dev->caps.max_rq_sg); 530 props->max_sge_rd = MLX4_MAX_SGE_RD; 531 props->max_cq = dev->dev->quotas.cq; 532 props->max_cqe = dev->dev->caps.max_cqes; 533 props->max_mr = dev->dev->quotas.mpt; 534 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 535 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 536 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 537 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 538 props->max_srq = dev->dev->quotas.srq; 539 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 540 props->max_srq_sge = dev->dev->caps.max_srq_sge; 541 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 542 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 543 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 544 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 545 props->masked_atomic_cap = props->atomic_cap; 546 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 547 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 548 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 549 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 550 props->max_mcast_grp; 551 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 552 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 553 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 554 props->max_ah = INT_MAX; 555 556 if ((dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 557 (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 558 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET)) { 559 props->rss_caps.max_rwq_indirection_tables = props->max_qp; 560 props->rss_caps.max_rwq_indirection_table_size = 561 dev->dev->caps.max_rss_tbl_sz; 562 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 563 props->max_wq_type_rq = props->max_qp; 564 } 565 566 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 567 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 568 569 if (!mlx4_is_slave(dev->dev)) 570 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 571 572 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 573 resp.response_length += sizeof(resp.hca_core_clock_offset); 574 if (!err && !mlx4_is_slave(dev->dev)) { 575 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP; 576 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 577 } 578 } 579 580 if (uhw->outlen >= resp.response_length + 581 sizeof(resp.max_inl_recv_sz)) { 582 resp.response_length += sizeof(resp.max_inl_recv_sz); 583 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 584 sizeof(struct mlx4_wqe_data_seg); 585 } 586 587 if (uhw->outlen >= resp.response_length + sizeof(resp.rss_caps)) { 588 resp.response_length += sizeof(resp.rss_caps); 589 if (props->rss_caps.supported_qpts) { 590 resp.rss_caps.rx_hash_function = 591 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 592 593 resp.rss_caps.rx_hash_fields_mask = 594 MLX4_IB_RX_HASH_SRC_IPV4 | 595 MLX4_IB_RX_HASH_DST_IPV4 | 596 MLX4_IB_RX_HASH_SRC_IPV6 | 597 MLX4_IB_RX_HASH_DST_IPV6 | 598 MLX4_IB_RX_HASH_SRC_PORT_TCP | 599 MLX4_IB_RX_HASH_DST_PORT_TCP | 600 MLX4_IB_RX_HASH_SRC_PORT_UDP | 601 MLX4_IB_RX_HASH_DST_PORT_UDP; 602 603 if (dev->dev->caps.tunnel_offload_mode == 604 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 605 resp.rss_caps.rx_hash_fields_mask |= 606 MLX4_IB_RX_HASH_INNER; 607 } 608 } 609 610 if (uhw->outlen) { 611 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 612 if (err) 613 goto out; 614 } 615 out: 616 kfree(in_mad); 617 kfree(out_mad); 618 619 return err; 620 } 621 622 static enum rdma_link_layer 623 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 624 { 625 struct mlx4_dev *dev = to_mdev(device)->dev; 626 627 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 628 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 629 } 630 631 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 632 struct ib_port_attr *props, int netw_view) 633 { 634 struct ib_smp *in_mad = NULL; 635 struct ib_smp *out_mad = NULL; 636 int ext_active_speed; 637 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 638 int err = -ENOMEM; 639 640 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 641 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 642 if (!in_mad || !out_mad) 643 goto out; 644 645 init_query_mad(in_mad); 646 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 647 in_mad->attr_mod = cpu_to_be32(port); 648 649 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 650 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 651 652 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 653 in_mad, out_mad); 654 if (err) 655 goto out; 656 657 658 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 659 props->lmc = out_mad->data[34] & 0x7; 660 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 661 props->sm_sl = out_mad->data[36] & 0xf; 662 props->state = out_mad->data[32] & 0xf; 663 props->phys_state = out_mad->data[33] >> 4; 664 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 665 if (netw_view) 666 props->gid_tbl_len = out_mad->data[50]; 667 else 668 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 669 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 670 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 671 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 672 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 673 props->active_width = out_mad->data[31] & 0xf; 674 props->active_speed = out_mad->data[35] >> 4; 675 props->max_mtu = out_mad->data[41] & 0xf; 676 props->active_mtu = out_mad->data[36] >> 4; 677 props->subnet_timeout = out_mad->data[51] & 0x1f; 678 props->max_vl_num = out_mad->data[37] >> 4; 679 props->init_type_reply = out_mad->data[41] >> 4; 680 681 /* Check if extended speeds (EDR/FDR/...) are supported */ 682 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 683 ext_active_speed = out_mad->data[62] >> 4; 684 685 switch (ext_active_speed) { 686 case 1: 687 props->active_speed = IB_SPEED_FDR; 688 break; 689 case 2: 690 props->active_speed = IB_SPEED_EDR; 691 break; 692 } 693 } 694 695 /* If reported active speed is QDR, check if is FDR-10 */ 696 if (props->active_speed == IB_SPEED_QDR) { 697 init_query_mad(in_mad); 698 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 699 in_mad->attr_mod = cpu_to_be32(port); 700 701 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 702 NULL, NULL, in_mad, out_mad); 703 if (err) 704 goto out; 705 706 /* Checking LinkSpeedActive for FDR-10 */ 707 if (out_mad->data[15] & 0x1) 708 props->active_speed = IB_SPEED_FDR10; 709 } 710 711 /* Avoid wrong speed value returned by FW if the IB link is down. */ 712 if (props->state == IB_PORT_DOWN) 713 props->active_speed = IB_SPEED_SDR; 714 715 out: 716 kfree(in_mad); 717 kfree(out_mad); 718 return err; 719 } 720 721 static u8 state_to_phys_state(enum ib_port_state state) 722 { 723 return state == IB_PORT_ACTIVE ? 5 : 3; 724 } 725 726 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 727 struct ib_port_attr *props) 728 { 729 730 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 731 struct mlx4_ib_iboe *iboe = &mdev->iboe; 732 struct net_device *ndev; 733 enum ib_mtu tmp; 734 struct mlx4_cmd_mailbox *mailbox; 735 int err = 0; 736 int is_bonded = mlx4_is_bonded(mdev->dev); 737 738 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 739 if (IS_ERR(mailbox)) 740 return PTR_ERR(mailbox); 741 742 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 743 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 744 MLX4_CMD_WRAPPED); 745 if (err) 746 goto out; 747 748 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 749 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 750 IB_WIDTH_4X : IB_WIDTH_1X; 751 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 752 IB_SPEED_FDR : IB_SPEED_QDR; 753 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; 754 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 755 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 756 props->pkey_tbl_len = 1; 757 props->max_mtu = IB_MTU_4096; 758 props->max_vl_num = 2; 759 props->state = IB_PORT_DOWN; 760 props->phys_state = state_to_phys_state(props->state); 761 props->active_mtu = IB_MTU_256; 762 spin_lock_bh(&iboe->lock); 763 ndev = iboe->netdevs[port - 1]; 764 if (ndev && is_bonded) { 765 rcu_read_lock(); /* required to get upper dev */ 766 ndev = netdev_master_upper_dev_get_rcu(ndev); 767 rcu_read_unlock(); 768 } 769 if (!ndev) 770 goto out_unlock; 771 772 tmp = iboe_get_mtu(ndev->mtu); 773 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 774 775 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 776 IB_PORT_ACTIVE : IB_PORT_DOWN; 777 props->phys_state = state_to_phys_state(props->state); 778 out_unlock: 779 spin_unlock_bh(&iboe->lock); 780 out: 781 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 782 return err; 783 } 784 785 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 786 struct ib_port_attr *props, int netw_view) 787 { 788 int err; 789 790 /* props being zeroed by the caller, avoid zeroing it here */ 791 792 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 793 ib_link_query_port(ibdev, port, props, netw_view) : 794 eth_link_query_port(ibdev, port, props); 795 796 return err; 797 } 798 799 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 800 struct ib_port_attr *props) 801 { 802 /* returns host view */ 803 return __mlx4_ib_query_port(ibdev, port, props, 0); 804 } 805 806 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 807 union ib_gid *gid, int netw_view) 808 { 809 struct ib_smp *in_mad = NULL; 810 struct ib_smp *out_mad = NULL; 811 int err = -ENOMEM; 812 struct mlx4_ib_dev *dev = to_mdev(ibdev); 813 int clear = 0; 814 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 815 816 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 817 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 818 if (!in_mad || !out_mad) 819 goto out; 820 821 init_query_mad(in_mad); 822 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 823 in_mad->attr_mod = cpu_to_be32(port); 824 825 if (mlx4_is_mfunc(dev->dev) && netw_view) 826 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 827 828 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 829 if (err) 830 goto out; 831 832 memcpy(gid->raw, out_mad->data + 8, 8); 833 834 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 835 if (index) { 836 /* For any index > 0, return the null guid */ 837 err = 0; 838 clear = 1; 839 goto out; 840 } 841 } 842 843 init_query_mad(in_mad); 844 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 845 in_mad->attr_mod = cpu_to_be32(index / 8); 846 847 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 848 NULL, NULL, in_mad, out_mad); 849 if (err) 850 goto out; 851 852 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 853 854 out: 855 if (clear) 856 memset(gid->raw + 8, 0, 8); 857 kfree(in_mad); 858 kfree(out_mad); 859 return err; 860 } 861 862 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 863 union ib_gid *gid) 864 { 865 int ret; 866 867 if (rdma_protocol_ib(ibdev, port)) 868 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 869 870 if (!rdma_protocol_roce(ibdev, port)) 871 return -ENODEV; 872 873 if (!rdma_cap_roce_gid_table(ibdev, port)) 874 return -ENODEV; 875 876 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL); 877 if (ret == -EAGAIN) { 878 memcpy(gid, &zgid, sizeof(*gid)); 879 return 0; 880 } 881 882 return ret; 883 } 884 885 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 886 { 887 union sl2vl_tbl_to_u64 sl2vl64; 888 struct ib_smp *in_mad = NULL; 889 struct ib_smp *out_mad = NULL; 890 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 891 int err = -ENOMEM; 892 int jj; 893 894 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 895 *sl2vl_tbl = 0; 896 return 0; 897 } 898 899 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 900 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 901 if (!in_mad || !out_mad) 902 goto out; 903 904 init_query_mad(in_mad); 905 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 906 in_mad->attr_mod = 0; 907 908 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 909 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 910 911 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 912 in_mad, out_mad); 913 if (err) 914 goto out; 915 916 for (jj = 0; jj < 8; jj++) 917 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 918 *sl2vl_tbl = sl2vl64.sl64; 919 920 out: 921 kfree(in_mad); 922 kfree(out_mad); 923 return err; 924 } 925 926 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 927 { 928 u64 sl2vl; 929 int i; 930 int err; 931 932 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 933 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 934 continue; 935 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 936 if (err) { 937 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 938 i, err); 939 sl2vl = 0; 940 } 941 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 942 } 943 } 944 945 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 946 u16 *pkey, int netw_view) 947 { 948 struct ib_smp *in_mad = NULL; 949 struct ib_smp *out_mad = NULL; 950 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 951 int err = -ENOMEM; 952 953 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 954 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 955 if (!in_mad || !out_mad) 956 goto out; 957 958 init_query_mad(in_mad); 959 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 960 in_mad->attr_mod = cpu_to_be32(index / 32); 961 962 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 963 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 964 965 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 966 in_mad, out_mad); 967 if (err) 968 goto out; 969 970 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 971 972 out: 973 kfree(in_mad); 974 kfree(out_mad); 975 return err; 976 } 977 978 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 979 { 980 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 981 } 982 983 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 984 struct ib_device_modify *props) 985 { 986 struct mlx4_cmd_mailbox *mailbox; 987 unsigned long flags; 988 989 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 990 return -EOPNOTSUPP; 991 992 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 993 return 0; 994 995 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 996 return -EOPNOTSUPP; 997 998 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 999 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1000 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1001 1002 /* 1003 * If possible, pass node desc to FW, so it can generate 1004 * a 144 trap. If cmd fails, just ignore. 1005 */ 1006 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1007 if (IS_ERR(mailbox)) 1008 return 0; 1009 1010 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1011 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1012 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1013 1014 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1015 1016 return 0; 1017 } 1018 1019 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1020 u32 cap_mask) 1021 { 1022 struct mlx4_cmd_mailbox *mailbox; 1023 int err; 1024 1025 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1026 if (IS_ERR(mailbox)) 1027 return PTR_ERR(mailbox); 1028 1029 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1030 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1031 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1032 } else { 1033 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1034 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1035 } 1036 1037 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1038 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1039 MLX4_CMD_WRAPPED); 1040 1041 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1042 return err; 1043 } 1044 1045 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1046 struct ib_port_modify *props) 1047 { 1048 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1049 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1050 struct ib_port_attr attr; 1051 u32 cap_mask; 1052 int err; 1053 1054 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1055 * of whether port link layer is ETH or IB. For ETH ports, qkey 1056 * violations and port capabilities are not meaningful. 1057 */ 1058 if (is_eth) 1059 return 0; 1060 1061 mutex_lock(&mdev->cap_mask_mutex); 1062 1063 err = ib_query_port(ibdev, port, &attr); 1064 if (err) 1065 goto out; 1066 1067 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1068 ~props->clr_port_cap_mask; 1069 1070 err = mlx4_ib_SET_PORT(mdev, port, 1071 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1072 cap_mask); 1073 1074 out: 1075 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1076 return err; 1077 } 1078 1079 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1080 struct ib_udata *udata) 1081 { 1082 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1083 struct mlx4_ib_ucontext *context; 1084 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1085 struct mlx4_ib_alloc_ucontext_resp resp; 1086 int err; 1087 1088 if (!dev->ib_active) 1089 return ERR_PTR(-EAGAIN); 1090 1091 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1092 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1093 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1094 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1095 } else { 1096 resp.dev_caps = dev->dev->caps.userspace_caps; 1097 resp.qp_tab_size = dev->dev->caps.num_qps; 1098 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1099 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1100 resp.cqe_size = dev->dev->caps.cqe_size; 1101 } 1102 1103 context = kzalloc(sizeof(*context), GFP_KERNEL); 1104 if (!context) 1105 return ERR_PTR(-ENOMEM); 1106 1107 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1108 if (err) { 1109 kfree(context); 1110 return ERR_PTR(err); 1111 } 1112 1113 INIT_LIST_HEAD(&context->db_page_list); 1114 mutex_init(&context->db_page_mutex); 1115 1116 INIT_LIST_HEAD(&context->wqn_ranges_list); 1117 mutex_init(&context->wqn_ranges_mutex); 1118 1119 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1120 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1121 else 1122 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1123 1124 if (err) { 1125 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1126 kfree(context); 1127 return ERR_PTR(-EFAULT); 1128 } 1129 1130 return &context->ibucontext; 1131 } 1132 1133 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1134 { 1135 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1136 1137 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1138 kfree(context); 1139 1140 return 0; 1141 } 1142 1143 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1144 { 1145 /* vma_open is called when a new VMA is created on top of our VMA. 1146 * This is done through either mremap flow or split_vma (usually due 1147 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1148 * vma, as this VMA is strongly hardware related. Therefore we set the 1149 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1150 * calling us again and trying to do incorrect actions. We assume that 1151 * the original vma size is exactly a single page that there will be no 1152 * "splitting" operations on. 1153 */ 1154 area->vm_ops = NULL; 1155 } 1156 1157 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1158 { 1159 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1160 1161 /* It's guaranteed that all VMAs opened on a FD are closed before the 1162 * file itself is closed, therefore no sync is needed with the regular 1163 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1164 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1165 * The close operation is usually called under mm->mmap_sem except when 1166 * process is exiting. The exiting case is handled explicitly as part 1167 * of mlx4_ib_disassociate_ucontext. 1168 */ 1169 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1170 area->vm_private_data; 1171 1172 /* set the vma context pointer to null in the mlx4_ib driver's private 1173 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1174 */ 1175 mlx4_ib_vma_priv_data->vma = NULL; 1176 } 1177 1178 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1179 .open = mlx4_ib_vma_open, 1180 .close = mlx4_ib_vma_close 1181 }; 1182 1183 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1184 { 1185 int i; 1186 int ret = 0; 1187 struct vm_area_struct *vma; 1188 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1189 struct task_struct *owning_process = NULL; 1190 struct mm_struct *owning_mm = NULL; 1191 1192 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1193 if (!owning_process) 1194 return; 1195 1196 owning_mm = get_task_mm(owning_process); 1197 if (!owning_mm) { 1198 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1199 while (1) { 1200 /* make sure that task is dead before returning, it may 1201 * prevent a rare case of module down in parallel to a 1202 * call to mlx4_ib_vma_close. 1203 */ 1204 put_task_struct(owning_process); 1205 usleep_range(1000, 2000); 1206 owning_process = get_pid_task(ibcontext->tgid, 1207 PIDTYPE_PID); 1208 if (!owning_process || 1209 owning_process->state == TASK_DEAD) { 1210 pr_info("disassociate ucontext done, task was terminated\n"); 1211 /* in case task was dead need to release the task struct */ 1212 if (owning_process) 1213 put_task_struct(owning_process); 1214 return; 1215 } 1216 } 1217 } 1218 1219 /* need to protect from a race on closing the vma as part of 1220 * mlx4_ib_vma_close(). 1221 */ 1222 down_write(&owning_mm->mmap_sem); 1223 for (i = 0; i < HW_BAR_COUNT; i++) { 1224 vma = context->hw_bar_info[i].vma; 1225 if (!vma) 1226 continue; 1227 1228 ret = zap_vma_ptes(context->hw_bar_info[i].vma, 1229 context->hw_bar_info[i].vma->vm_start, 1230 PAGE_SIZE); 1231 if (ret) { 1232 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret); 1233 BUG_ON(1); 1234 } 1235 1236 context->hw_bar_info[i].vma->vm_flags &= 1237 ~(VM_SHARED | VM_MAYSHARE); 1238 /* context going to be destroyed, should not access ops any more */ 1239 context->hw_bar_info[i].vma->vm_ops = NULL; 1240 } 1241 1242 up_write(&owning_mm->mmap_sem); 1243 mmput(owning_mm); 1244 put_task_struct(owning_process); 1245 } 1246 1247 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1248 struct mlx4_ib_vma_private_data *vma_private_data) 1249 { 1250 vma_private_data->vma = vma; 1251 vma->vm_private_data = vma_private_data; 1252 vma->vm_ops = &mlx4_ib_vm_ops; 1253 } 1254 1255 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1256 { 1257 struct mlx4_ib_dev *dev = to_mdev(context->device); 1258 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1259 1260 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1261 return -EINVAL; 1262 1263 if (vma->vm_pgoff == 0) { 1264 /* We prevent double mmaping on same context */ 1265 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1266 return -EINVAL; 1267 1268 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1269 1270 if (io_remap_pfn_range(vma, vma->vm_start, 1271 to_mucontext(context)->uar.pfn, 1272 PAGE_SIZE, vma->vm_page_prot)) 1273 return -EAGAIN; 1274 1275 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1276 1277 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1278 /* We prevent double mmaping on same context */ 1279 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1280 return -EINVAL; 1281 1282 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1283 1284 if (io_remap_pfn_range(vma, vma->vm_start, 1285 to_mucontext(context)->uar.pfn + 1286 dev->dev->caps.num_uars, 1287 PAGE_SIZE, vma->vm_page_prot)) 1288 return -EAGAIN; 1289 1290 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1291 1292 } else if (vma->vm_pgoff == 3) { 1293 struct mlx4_clock_params params; 1294 int ret; 1295 1296 /* We prevent double mmaping on same context */ 1297 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1298 return -EINVAL; 1299 1300 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1301 1302 if (ret) 1303 return ret; 1304 1305 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1306 if (io_remap_pfn_range(vma, vma->vm_start, 1307 (pci_resource_start(dev->dev->persist->pdev, 1308 params.bar) + 1309 params.offset) 1310 >> PAGE_SHIFT, 1311 PAGE_SIZE, vma->vm_page_prot)) 1312 return -EAGAIN; 1313 1314 mlx4_ib_set_vma_data(vma, 1315 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1316 } else { 1317 return -EINVAL; 1318 } 1319 1320 return 0; 1321 } 1322 1323 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1324 struct ib_ucontext *context, 1325 struct ib_udata *udata) 1326 { 1327 struct mlx4_ib_pd *pd; 1328 int err; 1329 1330 pd = kmalloc(sizeof *pd, GFP_KERNEL); 1331 if (!pd) 1332 return ERR_PTR(-ENOMEM); 1333 1334 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1335 if (err) { 1336 kfree(pd); 1337 return ERR_PTR(err); 1338 } 1339 1340 if (context) 1341 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1342 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1343 kfree(pd); 1344 return ERR_PTR(-EFAULT); 1345 } 1346 1347 return &pd->ibpd; 1348 } 1349 1350 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1351 { 1352 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1353 kfree(pd); 1354 1355 return 0; 1356 } 1357 1358 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1359 struct ib_ucontext *context, 1360 struct ib_udata *udata) 1361 { 1362 struct mlx4_ib_xrcd *xrcd; 1363 struct ib_cq_init_attr cq_attr = {}; 1364 int err; 1365 1366 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1367 return ERR_PTR(-ENOSYS); 1368 1369 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1370 if (!xrcd) 1371 return ERR_PTR(-ENOMEM); 1372 1373 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1374 if (err) 1375 goto err1; 1376 1377 xrcd->pd = ib_alloc_pd(ibdev, 0); 1378 if (IS_ERR(xrcd->pd)) { 1379 err = PTR_ERR(xrcd->pd); 1380 goto err2; 1381 } 1382 1383 cq_attr.cqe = 1; 1384 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1385 if (IS_ERR(xrcd->cq)) { 1386 err = PTR_ERR(xrcd->cq); 1387 goto err3; 1388 } 1389 1390 return &xrcd->ibxrcd; 1391 1392 err3: 1393 ib_dealloc_pd(xrcd->pd); 1394 err2: 1395 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1396 err1: 1397 kfree(xrcd); 1398 return ERR_PTR(err); 1399 } 1400 1401 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1402 { 1403 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1404 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1405 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1406 kfree(xrcd); 1407 1408 return 0; 1409 } 1410 1411 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1412 { 1413 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1414 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1415 struct mlx4_ib_gid_entry *ge; 1416 1417 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1418 if (!ge) 1419 return -ENOMEM; 1420 1421 ge->gid = *gid; 1422 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1423 ge->port = mqp->port; 1424 ge->added = 1; 1425 } 1426 1427 mutex_lock(&mqp->mutex); 1428 list_add_tail(&ge->list, &mqp->gid_list); 1429 mutex_unlock(&mqp->mutex); 1430 1431 return 0; 1432 } 1433 1434 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1435 struct mlx4_ib_counters *ctr_table) 1436 { 1437 struct counter_index *counter, *tmp_count; 1438 1439 mutex_lock(&ctr_table->mutex); 1440 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1441 list) { 1442 if (counter->allocated) 1443 mlx4_counter_free(ibdev->dev, counter->index); 1444 list_del(&counter->list); 1445 kfree(counter); 1446 } 1447 mutex_unlock(&ctr_table->mutex); 1448 } 1449 1450 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1451 union ib_gid *gid) 1452 { 1453 struct net_device *ndev; 1454 int ret = 0; 1455 1456 if (!mqp->port) 1457 return 0; 1458 1459 spin_lock_bh(&mdev->iboe.lock); 1460 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1461 if (ndev) 1462 dev_hold(ndev); 1463 spin_unlock_bh(&mdev->iboe.lock); 1464 1465 if (ndev) { 1466 ret = 1; 1467 dev_put(ndev); 1468 } 1469 1470 return ret; 1471 } 1472 1473 struct mlx4_ib_steering { 1474 struct list_head list; 1475 struct mlx4_flow_reg_id reg_id; 1476 union ib_gid gid; 1477 }; 1478 1479 #define LAST_ETH_FIELD vlan_tag 1480 #define LAST_IB_FIELD sl 1481 #define LAST_IPV4_FIELD dst_ip 1482 #define LAST_TCP_UDP_FIELD src_port 1483 1484 /* Field is the last supported field */ 1485 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1486 memchr_inv((void *)&filter.field +\ 1487 sizeof(filter.field), 0,\ 1488 sizeof(filter) -\ 1489 offsetof(typeof(filter), field) -\ 1490 sizeof(filter.field)) 1491 1492 static int parse_flow_attr(struct mlx4_dev *dev, 1493 u32 qp_num, 1494 union ib_flow_spec *ib_spec, 1495 struct _rule_hw *mlx4_spec) 1496 { 1497 enum mlx4_net_trans_rule_id type; 1498 1499 switch (ib_spec->type) { 1500 case IB_FLOW_SPEC_ETH: 1501 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1502 return -ENOTSUPP; 1503 1504 type = MLX4_NET_TRANS_RULE_ID_ETH; 1505 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1506 ETH_ALEN); 1507 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1508 ETH_ALEN); 1509 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1510 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1511 break; 1512 case IB_FLOW_SPEC_IB: 1513 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1514 return -ENOTSUPP; 1515 1516 type = MLX4_NET_TRANS_RULE_ID_IB; 1517 mlx4_spec->ib.l3_qpn = 1518 cpu_to_be32(qp_num); 1519 mlx4_spec->ib.qpn_mask = 1520 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1521 break; 1522 1523 1524 case IB_FLOW_SPEC_IPV4: 1525 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1526 return -ENOTSUPP; 1527 1528 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1529 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1530 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1531 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1532 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1533 break; 1534 1535 case IB_FLOW_SPEC_TCP: 1536 case IB_FLOW_SPEC_UDP: 1537 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1538 return -ENOTSUPP; 1539 1540 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1541 MLX4_NET_TRANS_RULE_ID_TCP : 1542 MLX4_NET_TRANS_RULE_ID_UDP; 1543 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1544 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1545 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1546 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1547 break; 1548 1549 default: 1550 return -EINVAL; 1551 } 1552 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1553 mlx4_hw_rule_sz(dev, type) < 0) 1554 return -EINVAL; 1555 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1556 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1557 return mlx4_hw_rule_sz(dev, type); 1558 } 1559 1560 struct default_rules { 1561 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1562 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1563 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1564 __u8 link_layer; 1565 }; 1566 static const struct default_rules default_table[] = { 1567 { 1568 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1569 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1570 .rules_create_list = {IB_FLOW_SPEC_IB}, 1571 .link_layer = IB_LINK_LAYER_INFINIBAND 1572 } 1573 }; 1574 1575 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1576 struct ib_flow_attr *flow_attr) 1577 { 1578 int i, j, k; 1579 void *ib_flow; 1580 const struct default_rules *pdefault_rules = default_table; 1581 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1582 1583 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1584 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1585 memset(&field_types, 0, sizeof(field_types)); 1586 1587 if (link_layer != pdefault_rules->link_layer) 1588 continue; 1589 1590 ib_flow = flow_attr + 1; 1591 /* we assume the specs are sorted */ 1592 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1593 j < flow_attr->num_of_specs; k++) { 1594 union ib_flow_spec *current_flow = 1595 (union ib_flow_spec *)ib_flow; 1596 1597 /* same layer but different type */ 1598 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1599 (pdefault_rules->mandatory_fields[k] & 1600 IB_FLOW_SPEC_LAYER_MASK)) && 1601 (current_flow->type != 1602 pdefault_rules->mandatory_fields[k])) 1603 goto out; 1604 1605 /* same layer, try match next one */ 1606 if (current_flow->type == 1607 pdefault_rules->mandatory_fields[k]) { 1608 j++; 1609 ib_flow += 1610 ((union ib_flow_spec *)ib_flow)->size; 1611 } 1612 } 1613 1614 ib_flow = flow_attr + 1; 1615 for (j = 0; j < flow_attr->num_of_specs; 1616 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1617 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1618 /* same layer and same type */ 1619 if (((union ib_flow_spec *)ib_flow)->type == 1620 pdefault_rules->mandatory_not_fields[k]) 1621 goto out; 1622 1623 return i; 1624 } 1625 out: 1626 return -1; 1627 } 1628 1629 static int __mlx4_ib_create_default_rules( 1630 struct mlx4_ib_dev *mdev, 1631 struct ib_qp *qp, 1632 const struct default_rules *pdefault_rules, 1633 struct _rule_hw *mlx4_spec) { 1634 int size = 0; 1635 int i; 1636 1637 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1638 int ret; 1639 union ib_flow_spec ib_spec; 1640 switch (pdefault_rules->rules_create_list[i]) { 1641 case 0: 1642 /* no rule */ 1643 continue; 1644 case IB_FLOW_SPEC_IB: 1645 ib_spec.type = IB_FLOW_SPEC_IB; 1646 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1647 1648 break; 1649 default: 1650 /* invalid rule */ 1651 return -EINVAL; 1652 } 1653 /* We must put empty rule, qpn is being ignored */ 1654 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1655 mlx4_spec); 1656 if (ret < 0) { 1657 pr_info("invalid parsing\n"); 1658 return -EINVAL; 1659 } 1660 1661 mlx4_spec = (void *)mlx4_spec + ret; 1662 size += ret; 1663 } 1664 return size; 1665 } 1666 1667 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1668 int domain, 1669 enum mlx4_net_trans_promisc_mode flow_type, 1670 u64 *reg_id) 1671 { 1672 int ret, i; 1673 int size = 0; 1674 void *ib_flow; 1675 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1676 struct mlx4_cmd_mailbox *mailbox; 1677 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1678 int default_flow; 1679 1680 static const u16 __mlx4_domain[] = { 1681 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1682 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1683 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1684 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1685 }; 1686 1687 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1688 pr_err("Invalid priority value %d\n", flow_attr->priority); 1689 return -EINVAL; 1690 } 1691 1692 if (domain >= IB_FLOW_DOMAIN_NUM) { 1693 pr_err("Invalid domain value %d\n", domain); 1694 return -EINVAL; 1695 } 1696 1697 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1698 return -EINVAL; 1699 1700 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1701 if (IS_ERR(mailbox)) 1702 return PTR_ERR(mailbox); 1703 ctrl = mailbox->buf; 1704 1705 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1706 flow_attr->priority); 1707 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1708 ctrl->port = flow_attr->port; 1709 ctrl->qpn = cpu_to_be32(qp->qp_num); 1710 1711 ib_flow = flow_attr + 1; 1712 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1713 /* Add default flows */ 1714 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1715 if (default_flow >= 0) { 1716 ret = __mlx4_ib_create_default_rules( 1717 mdev, qp, default_table + default_flow, 1718 mailbox->buf + size); 1719 if (ret < 0) { 1720 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1721 return -EINVAL; 1722 } 1723 size += ret; 1724 } 1725 for (i = 0; i < flow_attr->num_of_specs; i++) { 1726 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1727 mailbox->buf + size); 1728 if (ret < 0) { 1729 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1730 return -EINVAL; 1731 } 1732 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1733 size += ret; 1734 } 1735 1736 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1737 flow_attr->num_of_specs == 1) { 1738 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1739 enum ib_flow_spec_type header_spec = 1740 ((union ib_flow_spec *)(flow_attr + 1))->type; 1741 1742 if (header_spec == IB_FLOW_SPEC_ETH) 1743 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1744 } 1745 1746 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1747 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1748 MLX4_CMD_NATIVE); 1749 if (ret == -ENOMEM) 1750 pr_err("mcg table is full. Fail to register network rule.\n"); 1751 else if (ret == -ENXIO) 1752 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1753 else if (ret) 1754 pr_err("Invalid argument. Fail to register network rule.\n"); 1755 1756 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1757 return ret; 1758 } 1759 1760 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1761 { 1762 int err; 1763 err = mlx4_cmd(dev, reg_id, 0, 0, 1764 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1765 MLX4_CMD_NATIVE); 1766 if (err) 1767 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1768 reg_id); 1769 return err; 1770 } 1771 1772 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1773 u64 *reg_id) 1774 { 1775 void *ib_flow; 1776 union ib_flow_spec *ib_spec; 1777 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1778 int err = 0; 1779 1780 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1781 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1782 return 0; /* do nothing */ 1783 1784 ib_flow = flow_attr + 1; 1785 ib_spec = (union ib_flow_spec *)ib_flow; 1786 1787 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1788 return 0; /* do nothing */ 1789 1790 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1791 flow_attr->port, qp->qp_num, 1792 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1793 reg_id); 1794 return err; 1795 } 1796 1797 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1798 struct ib_flow_attr *flow_attr, 1799 enum mlx4_net_trans_promisc_mode *type) 1800 { 1801 int err = 0; 1802 1803 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1804 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1805 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1806 return -EOPNOTSUPP; 1807 } 1808 1809 if (flow_attr->num_of_specs == 0) { 1810 type[0] = MLX4_FS_MC_SNIFFER; 1811 type[1] = MLX4_FS_UC_SNIFFER; 1812 } else { 1813 union ib_flow_spec *ib_spec; 1814 1815 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1816 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1817 return -EINVAL; 1818 1819 /* if all is zero than MC and UC */ 1820 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1821 type[0] = MLX4_FS_MC_SNIFFER; 1822 type[1] = MLX4_FS_UC_SNIFFER; 1823 } else { 1824 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1825 ib_spec->eth.mask.dst_mac[1], 1826 ib_spec->eth.mask.dst_mac[2], 1827 ib_spec->eth.mask.dst_mac[3], 1828 ib_spec->eth.mask.dst_mac[4], 1829 ib_spec->eth.mask.dst_mac[5]}; 1830 1831 /* Above xor was only on MC bit, non empty mask is valid 1832 * only if this bit is set and rest are zero. 1833 */ 1834 if (!is_zero_ether_addr(&mac[0])) 1835 return -EINVAL; 1836 1837 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1838 type[0] = MLX4_FS_MC_SNIFFER; 1839 else 1840 type[0] = MLX4_FS_UC_SNIFFER; 1841 } 1842 } 1843 1844 return err; 1845 } 1846 1847 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1848 struct ib_flow_attr *flow_attr, 1849 int domain) 1850 { 1851 int err = 0, i = 0, j = 0; 1852 struct mlx4_ib_flow *mflow; 1853 enum mlx4_net_trans_promisc_mode type[2]; 1854 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1855 int is_bonded = mlx4_is_bonded(dev); 1856 1857 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1858 return ERR_PTR(-EINVAL); 1859 1860 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1861 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1862 return ERR_PTR(-EOPNOTSUPP); 1863 1864 memset(type, 0, sizeof(type)); 1865 1866 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1867 if (!mflow) { 1868 err = -ENOMEM; 1869 goto err_free; 1870 } 1871 1872 switch (flow_attr->type) { 1873 case IB_FLOW_ATTR_NORMAL: 1874 /* If dont trap flag (continue match) is set, under specific 1875 * condition traffic be replicated to given qp, 1876 * without stealing it 1877 */ 1878 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1879 err = mlx4_ib_add_dont_trap_rule(dev, 1880 flow_attr, 1881 type); 1882 if (err) 1883 goto err_free; 1884 } else { 1885 type[0] = MLX4_FS_REGULAR; 1886 } 1887 break; 1888 1889 case IB_FLOW_ATTR_ALL_DEFAULT: 1890 type[0] = MLX4_FS_ALL_DEFAULT; 1891 break; 1892 1893 case IB_FLOW_ATTR_MC_DEFAULT: 1894 type[0] = MLX4_FS_MC_DEFAULT; 1895 break; 1896 1897 case IB_FLOW_ATTR_SNIFFER: 1898 type[0] = MLX4_FS_MIRROR_RX_PORT; 1899 type[1] = MLX4_FS_MIRROR_SX_PORT; 1900 break; 1901 1902 default: 1903 err = -EINVAL; 1904 goto err_free; 1905 } 1906 1907 while (i < ARRAY_SIZE(type) && type[i]) { 1908 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1909 &mflow->reg_id[i].id); 1910 if (err) 1911 goto err_create_flow; 1912 if (is_bonded) { 1913 /* Application always sees one port so the mirror rule 1914 * must be on port #2 1915 */ 1916 flow_attr->port = 2; 1917 err = __mlx4_ib_create_flow(qp, flow_attr, 1918 domain, type[j], 1919 &mflow->reg_id[j].mirror); 1920 flow_attr->port = 1; 1921 if (err) 1922 goto err_create_flow; 1923 j++; 1924 } 1925 1926 i++; 1927 } 1928 1929 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1930 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1931 &mflow->reg_id[i].id); 1932 if (err) 1933 goto err_create_flow; 1934 1935 if (is_bonded) { 1936 flow_attr->port = 2; 1937 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1938 &mflow->reg_id[j].mirror); 1939 flow_attr->port = 1; 1940 if (err) 1941 goto err_create_flow; 1942 j++; 1943 } 1944 /* function to create mirror rule */ 1945 i++; 1946 } 1947 1948 return &mflow->ibflow; 1949 1950 err_create_flow: 1951 while (i) { 1952 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1953 mflow->reg_id[i].id); 1954 i--; 1955 } 1956 1957 while (j) { 1958 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1959 mflow->reg_id[j].mirror); 1960 j--; 1961 } 1962 err_free: 1963 kfree(mflow); 1964 return ERR_PTR(err); 1965 } 1966 1967 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1968 { 1969 int err, ret = 0; 1970 int i = 0; 1971 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1972 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1973 1974 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1975 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1976 if (err) 1977 ret = err; 1978 if (mflow->reg_id[i].mirror) { 1979 err = __mlx4_ib_destroy_flow(mdev->dev, 1980 mflow->reg_id[i].mirror); 1981 if (err) 1982 ret = err; 1983 } 1984 i++; 1985 } 1986 1987 kfree(mflow); 1988 return ret; 1989 } 1990 1991 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1992 { 1993 int err; 1994 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1995 struct mlx4_dev *dev = mdev->dev; 1996 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1997 struct mlx4_ib_steering *ib_steering = NULL; 1998 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1999 struct mlx4_flow_reg_id reg_id; 2000 2001 if (mdev->dev->caps.steering_mode == 2002 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2003 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 2004 if (!ib_steering) 2005 return -ENOMEM; 2006 } 2007 2008 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 2009 !!(mqp->flags & 2010 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 2011 prot, ®_id.id); 2012 if (err) { 2013 pr_err("multicast attach op failed, err %d\n", err); 2014 goto err_malloc; 2015 } 2016 2017 reg_id.mirror = 0; 2018 if (mlx4_is_bonded(dev)) { 2019 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 2020 (mqp->port == 1) ? 2 : 1, 2021 !!(mqp->flags & 2022 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 2023 prot, ®_id.mirror); 2024 if (err) 2025 goto err_add; 2026 } 2027 2028 err = add_gid_entry(ibqp, gid); 2029 if (err) 2030 goto err_add; 2031 2032 if (ib_steering) { 2033 memcpy(ib_steering->gid.raw, gid->raw, 16); 2034 ib_steering->reg_id = reg_id; 2035 mutex_lock(&mqp->mutex); 2036 list_add(&ib_steering->list, &mqp->steering_rules); 2037 mutex_unlock(&mqp->mutex); 2038 } 2039 return 0; 2040 2041 err_add: 2042 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2043 prot, reg_id.id); 2044 if (reg_id.mirror) 2045 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2046 prot, reg_id.mirror); 2047 err_malloc: 2048 kfree(ib_steering); 2049 2050 return err; 2051 } 2052 2053 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2054 { 2055 struct mlx4_ib_gid_entry *ge; 2056 struct mlx4_ib_gid_entry *tmp; 2057 struct mlx4_ib_gid_entry *ret = NULL; 2058 2059 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2060 if (!memcmp(raw, ge->gid.raw, 16)) { 2061 ret = ge; 2062 break; 2063 } 2064 } 2065 2066 return ret; 2067 } 2068 2069 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2070 { 2071 int err; 2072 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2073 struct mlx4_dev *dev = mdev->dev; 2074 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2075 struct net_device *ndev; 2076 struct mlx4_ib_gid_entry *ge; 2077 struct mlx4_flow_reg_id reg_id = {0, 0}; 2078 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2079 2080 if (mdev->dev->caps.steering_mode == 2081 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2082 struct mlx4_ib_steering *ib_steering; 2083 2084 mutex_lock(&mqp->mutex); 2085 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2086 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2087 list_del(&ib_steering->list); 2088 break; 2089 } 2090 } 2091 mutex_unlock(&mqp->mutex); 2092 if (&ib_steering->list == &mqp->steering_rules) { 2093 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2094 return -EINVAL; 2095 } 2096 reg_id = ib_steering->reg_id; 2097 kfree(ib_steering); 2098 } 2099 2100 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2101 prot, reg_id.id); 2102 if (err) 2103 return err; 2104 2105 if (mlx4_is_bonded(dev)) { 2106 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2107 prot, reg_id.mirror); 2108 if (err) 2109 return err; 2110 } 2111 2112 mutex_lock(&mqp->mutex); 2113 ge = find_gid_entry(mqp, gid->raw); 2114 if (ge) { 2115 spin_lock_bh(&mdev->iboe.lock); 2116 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2117 if (ndev) 2118 dev_hold(ndev); 2119 spin_unlock_bh(&mdev->iboe.lock); 2120 if (ndev) 2121 dev_put(ndev); 2122 list_del(&ge->list); 2123 kfree(ge); 2124 } else 2125 pr_warn("could not find mgid entry\n"); 2126 2127 mutex_unlock(&mqp->mutex); 2128 2129 return 0; 2130 } 2131 2132 static int init_node_data(struct mlx4_ib_dev *dev) 2133 { 2134 struct ib_smp *in_mad = NULL; 2135 struct ib_smp *out_mad = NULL; 2136 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2137 int err = -ENOMEM; 2138 2139 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2140 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2141 if (!in_mad || !out_mad) 2142 goto out; 2143 2144 init_query_mad(in_mad); 2145 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2146 if (mlx4_is_master(dev->dev)) 2147 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2148 2149 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2150 if (err) 2151 goto out; 2152 2153 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2154 2155 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2156 2157 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2158 if (err) 2159 goto out; 2160 2161 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2162 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2163 2164 out: 2165 kfree(in_mad); 2166 kfree(out_mad); 2167 return err; 2168 } 2169 2170 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2171 char *buf) 2172 { 2173 struct mlx4_ib_dev *dev = 2174 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2175 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2176 } 2177 2178 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2179 char *buf) 2180 { 2181 struct mlx4_ib_dev *dev = 2182 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2183 return sprintf(buf, "%x\n", dev->dev->rev_id); 2184 } 2185 2186 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2187 char *buf) 2188 { 2189 struct mlx4_ib_dev *dev = 2190 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2191 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2192 dev->dev->board_id); 2193 } 2194 2195 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2196 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2197 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2198 2199 static struct device_attribute *mlx4_class_attributes[] = { 2200 &dev_attr_hw_rev, 2201 &dev_attr_hca_type, 2202 &dev_attr_board_id 2203 }; 2204 2205 struct diag_counter { 2206 const char *name; 2207 u32 offset; 2208 }; 2209 2210 #define DIAG_COUNTER(_name, _offset) \ 2211 { .name = #_name, .offset = _offset } 2212 2213 static const struct diag_counter diag_basic[] = { 2214 DIAG_COUNTER(rq_num_lle, 0x00), 2215 DIAG_COUNTER(sq_num_lle, 0x04), 2216 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2217 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2218 DIAG_COUNTER(rq_num_lpe, 0x18), 2219 DIAG_COUNTER(sq_num_lpe, 0x1C), 2220 DIAG_COUNTER(rq_num_wrfe, 0x20), 2221 DIAG_COUNTER(sq_num_wrfe, 0x24), 2222 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2223 DIAG_COUNTER(sq_num_bre, 0x34), 2224 DIAG_COUNTER(sq_num_rire, 0x44), 2225 DIAG_COUNTER(rq_num_rire, 0x48), 2226 DIAG_COUNTER(sq_num_rae, 0x4C), 2227 DIAG_COUNTER(rq_num_rae, 0x50), 2228 DIAG_COUNTER(sq_num_roe, 0x54), 2229 DIAG_COUNTER(sq_num_tree, 0x5C), 2230 DIAG_COUNTER(sq_num_rree, 0x64), 2231 DIAG_COUNTER(rq_num_rnr, 0x68), 2232 DIAG_COUNTER(sq_num_rnr, 0x6C), 2233 DIAG_COUNTER(rq_num_oos, 0x100), 2234 DIAG_COUNTER(sq_num_oos, 0x104), 2235 }; 2236 2237 static const struct diag_counter diag_ext[] = { 2238 DIAG_COUNTER(rq_num_dup, 0x130), 2239 DIAG_COUNTER(sq_num_to, 0x134), 2240 }; 2241 2242 static const struct diag_counter diag_device_only[] = { 2243 DIAG_COUNTER(num_cqovf, 0x1A0), 2244 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2245 }; 2246 2247 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2248 u8 port_num) 2249 { 2250 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2251 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2252 2253 if (!diag[!!port_num].name) 2254 return NULL; 2255 2256 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2257 diag[!!port_num].num_counters, 2258 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2259 } 2260 2261 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2262 struct rdma_hw_stats *stats, 2263 u8 port, int index) 2264 { 2265 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2266 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2267 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2268 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2269 int ret; 2270 int i; 2271 2272 ret = mlx4_query_diag_counters(dev->dev, 2273 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2274 diag[!!port].offset, hw_value, 2275 diag[!!port].num_counters, port); 2276 2277 if (ret) 2278 return ret; 2279 2280 for (i = 0; i < diag[!!port].num_counters; i++) 2281 stats->value[i] = hw_value[i]; 2282 2283 return diag[!!port].num_counters; 2284 } 2285 2286 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2287 const char ***name, 2288 u32 **offset, 2289 u32 *num, 2290 bool port) 2291 { 2292 u32 num_counters; 2293 2294 num_counters = ARRAY_SIZE(diag_basic); 2295 2296 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2297 num_counters += ARRAY_SIZE(diag_ext); 2298 2299 if (!port) 2300 num_counters += ARRAY_SIZE(diag_device_only); 2301 2302 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2303 if (!*name) 2304 return -ENOMEM; 2305 2306 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2307 if (!*offset) 2308 goto err_name; 2309 2310 *num = num_counters; 2311 2312 return 0; 2313 2314 err_name: 2315 kfree(*name); 2316 return -ENOMEM; 2317 } 2318 2319 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2320 const char **name, 2321 u32 *offset, 2322 bool port) 2323 { 2324 int i; 2325 int j; 2326 2327 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2328 name[i] = diag_basic[i].name; 2329 offset[i] = diag_basic[i].offset; 2330 } 2331 2332 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2333 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2334 name[j] = diag_ext[i].name; 2335 offset[j] = diag_ext[i].offset; 2336 } 2337 } 2338 2339 if (!port) { 2340 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2341 name[j] = diag_device_only[i].name; 2342 offset[j] = diag_device_only[i].offset; 2343 } 2344 } 2345 } 2346 2347 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2348 { 2349 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2350 int i; 2351 int ret; 2352 bool per_port = !!(ibdev->dev->caps.flags2 & 2353 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2354 2355 if (mlx4_is_slave(ibdev->dev)) 2356 return 0; 2357 2358 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2359 /* i == 1 means we are building port counters */ 2360 if (i && !per_port) 2361 continue; 2362 2363 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2364 &diag[i].offset, 2365 &diag[i].num_counters, i); 2366 if (ret) 2367 goto err_alloc; 2368 2369 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2370 diag[i].offset, i); 2371 } 2372 2373 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2374 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2375 2376 return 0; 2377 2378 err_alloc: 2379 if (i) { 2380 kfree(diag[i - 1].name); 2381 kfree(diag[i - 1].offset); 2382 } 2383 2384 return ret; 2385 } 2386 2387 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2388 { 2389 int i; 2390 2391 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2392 kfree(ibdev->diag_counters[i].offset); 2393 kfree(ibdev->diag_counters[i].name); 2394 } 2395 } 2396 2397 #define MLX4_IB_INVALID_MAC ((u64)-1) 2398 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2399 struct net_device *dev, 2400 int port) 2401 { 2402 u64 new_smac = 0; 2403 u64 release_mac = MLX4_IB_INVALID_MAC; 2404 struct mlx4_ib_qp *qp; 2405 2406 read_lock(&dev_base_lock); 2407 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2408 read_unlock(&dev_base_lock); 2409 2410 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2411 2412 /* no need for update QP1 and mac registration in non-SRIOV */ 2413 if (!mlx4_is_mfunc(ibdev->dev)) 2414 return; 2415 2416 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2417 qp = ibdev->qp1_proxy[port - 1]; 2418 if (qp) { 2419 int new_smac_index; 2420 u64 old_smac; 2421 struct mlx4_update_qp_params update_params; 2422 2423 mutex_lock(&qp->mutex); 2424 old_smac = qp->pri.smac; 2425 if (new_smac == old_smac) 2426 goto unlock; 2427 2428 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2429 2430 if (new_smac_index < 0) 2431 goto unlock; 2432 2433 update_params.smac_index = new_smac_index; 2434 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2435 &update_params)) { 2436 release_mac = new_smac; 2437 goto unlock; 2438 } 2439 /* if old port was zero, no mac was yet registered for this QP */ 2440 if (qp->pri.smac_port) 2441 release_mac = old_smac; 2442 qp->pri.smac = new_smac; 2443 qp->pri.smac_port = port; 2444 qp->pri.smac_index = new_smac_index; 2445 } 2446 2447 unlock: 2448 if (release_mac != MLX4_IB_INVALID_MAC) 2449 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2450 if (qp) 2451 mutex_unlock(&qp->mutex); 2452 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2453 } 2454 2455 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2456 struct net_device *dev, 2457 unsigned long event) 2458 2459 { 2460 struct mlx4_ib_iboe *iboe; 2461 int update_qps_port = -1; 2462 int port; 2463 2464 ASSERT_RTNL(); 2465 2466 iboe = &ibdev->iboe; 2467 2468 spin_lock_bh(&iboe->lock); 2469 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2470 2471 iboe->netdevs[port - 1] = 2472 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2473 2474 if (dev == iboe->netdevs[port - 1] && 2475 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2476 event == NETDEV_UP || event == NETDEV_CHANGE)) 2477 update_qps_port = port; 2478 2479 } 2480 spin_unlock_bh(&iboe->lock); 2481 2482 if (update_qps_port > 0) 2483 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2484 } 2485 2486 static int mlx4_ib_netdev_event(struct notifier_block *this, 2487 unsigned long event, void *ptr) 2488 { 2489 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2490 struct mlx4_ib_dev *ibdev; 2491 2492 if (!net_eq(dev_net(dev), &init_net)) 2493 return NOTIFY_DONE; 2494 2495 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2496 mlx4_ib_scan_netdevs(ibdev, dev, event); 2497 2498 return NOTIFY_DONE; 2499 } 2500 2501 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2502 { 2503 int port; 2504 int slave; 2505 int i; 2506 2507 if (mlx4_is_master(ibdev->dev)) { 2508 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2509 ++slave) { 2510 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2511 for (i = 0; 2512 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2513 ++i) { 2514 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2515 /* master has the identity virt2phys pkey mapping */ 2516 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2517 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2518 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2519 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2520 } 2521 } 2522 } 2523 /* initialize pkey cache */ 2524 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2525 for (i = 0; 2526 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2527 ++i) 2528 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2529 (i) ? 0 : 0xFFFF; 2530 } 2531 } 2532 } 2533 2534 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2535 { 2536 int i, j, eq = 0, total_eqs = 0; 2537 2538 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2539 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2540 if (!ibdev->eq_table) 2541 return; 2542 2543 for (i = 1; i <= dev->caps.num_ports; i++) { 2544 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2545 j++, total_eqs++) { 2546 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2547 continue; 2548 ibdev->eq_table[eq] = total_eqs; 2549 if (!mlx4_assign_eq(dev, i, 2550 &ibdev->eq_table[eq])) 2551 eq++; 2552 else 2553 ibdev->eq_table[eq] = -1; 2554 } 2555 } 2556 2557 for (i = eq; i < dev->caps.num_comp_vectors; 2558 ibdev->eq_table[i++] = -1) 2559 ; 2560 2561 /* Advertise the new number of EQs to clients */ 2562 ibdev->ib_dev.num_comp_vectors = eq; 2563 } 2564 2565 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2566 { 2567 int i; 2568 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2569 2570 /* no eqs were allocated */ 2571 if (!ibdev->eq_table) 2572 return; 2573 2574 /* Reset the advertised EQ number */ 2575 ibdev->ib_dev.num_comp_vectors = 0; 2576 2577 for (i = 0; i < total_eqs; i++) 2578 mlx4_release_eq(dev, ibdev->eq_table[i]); 2579 2580 kfree(ibdev->eq_table); 2581 ibdev->eq_table = NULL; 2582 } 2583 2584 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2585 struct ib_port_immutable *immutable) 2586 { 2587 struct ib_port_attr attr; 2588 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2589 int err; 2590 2591 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2592 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2593 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2594 } else { 2595 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2596 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2597 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2598 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2599 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2600 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2601 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2602 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2603 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2604 } 2605 2606 err = ib_query_port(ibdev, port_num, &attr); 2607 if (err) 2608 return err; 2609 2610 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2611 immutable->gid_tbl_len = attr.gid_tbl_len; 2612 2613 return 0; 2614 } 2615 2616 static void get_fw_ver_str(struct ib_device *device, char *str) 2617 { 2618 struct mlx4_ib_dev *dev = 2619 container_of(device, struct mlx4_ib_dev, ib_dev); 2620 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2621 (int) (dev->dev->caps.fw_ver >> 32), 2622 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2623 (int) dev->dev->caps.fw_ver & 0xffff); 2624 } 2625 2626 static void *mlx4_ib_add(struct mlx4_dev *dev) 2627 { 2628 struct mlx4_ib_dev *ibdev; 2629 int num_ports = 0; 2630 int i, j; 2631 int err; 2632 struct mlx4_ib_iboe *iboe; 2633 int ib_num_ports = 0; 2634 int num_req_counters; 2635 int allocated; 2636 u32 counter_index; 2637 struct counter_index *new_counter_index = NULL; 2638 2639 pr_info_once("%s", mlx4_ib_version); 2640 2641 num_ports = 0; 2642 mlx4_foreach_ib_transport_port(i, dev) 2643 num_ports++; 2644 2645 /* No point in registering a device with no ports... */ 2646 if (num_ports == 0) 2647 return NULL; 2648 2649 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2650 if (!ibdev) { 2651 dev_err(&dev->persist->pdev->dev, 2652 "Device struct alloc failed\n"); 2653 return NULL; 2654 } 2655 2656 iboe = &ibdev->iboe; 2657 2658 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2659 goto err_dealloc; 2660 2661 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2662 goto err_pd; 2663 2664 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2665 PAGE_SIZE); 2666 if (!ibdev->uar_map) 2667 goto err_uar; 2668 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2669 2670 ibdev->dev = dev; 2671 ibdev->bond_next_port = 0; 2672 2673 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2674 ibdev->ib_dev.owner = THIS_MODULE; 2675 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2676 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2677 ibdev->num_ports = num_ports; 2678 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2679 1 : ibdev->num_ports; 2680 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2681 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2682 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2683 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2684 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2685 2686 if (dev->caps.userspace_caps) 2687 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2688 else 2689 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2690 2691 ibdev->ib_dev.uverbs_cmd_mask = 2692 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2693 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2694 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2695 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2696 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2697 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2698 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2699 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2700 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2701 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2702 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2703 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2704 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2705 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2706 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2707 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2708 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2709 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2710 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2711 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2712 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2713 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2714 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2715 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2716 2717 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2718 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2719 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2720 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2721 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2722 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2723 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2724 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2725 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2726 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2727 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2728 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2729 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2730 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2731 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2732 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2733 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2734 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2735 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2736 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2737 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2738 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2739 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2740 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2741 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2742 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2743 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2744 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2745 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2746 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2747 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2748 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2749 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2750 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2751 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2752 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2753 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2754 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2755 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2756 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2757 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2758 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2759 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2760 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2761 2762 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2763 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2764 2765 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2766 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2767 IB_LINK_LAYER_ETHERNET) || 2768 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2769 IB_LINK_LAYER_ETHERNET))) { 2770 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2771 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2772 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2773 ibdev->ib_dev.create_rwq_ind_table = 2774 mlx4_ib_create_rwq_ind_table; 2775 ibdev->ib_dev.destroy_rwq_ind_table = 2776 mlx4_ib_destroy_rwq_ind_table; 2777 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2778 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2779 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2780 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2781 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2782 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2783 } 2784 2785 if (!mlx4_is_slave(ibdev->dev)) { 2786 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2787 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2788 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2789 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2790 } 2791 2792 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2793 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2794 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2795 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2796 2797 ibdev->ib_dev.uverbs_cmd_mask |= 2798 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2799 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2800 } 2801 2802 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2803 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2804 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2805 ibdev->ib_dev.uverbs_cmd_mask |= 2806 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2807 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2808 } 2809 2810 if (check_flow_steering_support(dev)) { 2811 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2812 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2813 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2814 2815 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2816 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2817 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2818 } 2819 2820 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2821 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2822 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2823 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2824 2825 mlx4_ib_alloc_eqs(dev, ibdev); 2826 2827 spin_lock_init(&iboe->lock); 2828 2829 if (init_node_data(ibdev)) 2830 goto err_map; 2831 mlx4_init_sl2vl_tbl(ibdev); 2832 2833 for (i = 0; i < ibdev->num_ports; ++i) { 2834 mutex_init(&ibdev->counters_table[i].mutex); 2835 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2836 } 2837 2838 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2839 for (i = 0; i < num_req_counters; ++i) { 2840 mutex_init(&ibdev->qp1_proxy_lock[i]); 2841 allocated = 0; 2842 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2843 IB_LINK_LAYER_ETHERNET) { 2844 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2845 MLX4_RES_USAGE_DRIVER); 2846 /* if failed to allocate a new counter, use default */ 2847 if (err) 2848 counter_index = 2849 mlx4_get_default_counter_index(dev, 2850 i + 1); 2851 else 2852 allocated = 1; 2853 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2854 counter_index = mlx4_get_default_counter_index(dev, 2855 i + 1); 2856 } 2857 new_counter_index = kmalloc(sizeof(*new_counter_index), 2858 GFP_KERNEL); 2859 if (!new_counter_index) { 2860 if (allocated) 2861 mlx4_counter_free(ibdev->dev, counter_index); 2862 goto err_counter; 2863 } 2864 new_counter_index->index = counter_index; 2865 new_counter_index->allocated = allocated; 2866 list_add_tail(&new_counter_index->list, 2867 &ibdev->counters_table[i].counters_list); 2868 ibdev->counters_table[i].default_counter = counter_index; 2869 pr_info("counter index %d for port %d allocated %d\n", 2870 counter_index, i + 1, allocated); 2871 } 2872 if (mlx4_is_bonded(dev)) 2873 for (i = 1; i < ibdev->num_ports ; ++i) { 2874 new_counter_index = 2875 kmalloc(sizeof(struct counter_index), 2876 GFP_KERNEL); 2877 if (!new_counter_index) 2878 goto err_counter; 2879 new_counter_index->index = counter_index; 2880 new_counter_index->allocated = 0; 2881 list_add_tail(&new_counter_index->list, 2882 &ibdev->counters_table[i].counters_list); 2883 ibdev->counters_table[i].default_counter = 2884 counter_index; 2885 } 2886 2887 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2888 ib_num_ports++; 2889 2890 spin_lock_init(&ibdev->sm_lock); 2891 mutex_init(&ibdev->cap_mask_mutex); 2892 INIT_LIST_HEAD(&ibdev->qp_list); 2893 spin_lock_init(&ibdev->reset_flow_resource_lock); 2894 2895 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2896 ib_num_ports) { 2897 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2898 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2899 MLX4_IB_UC_STEER_QPN_ALIGN, 2900 &ibdev->steer_qpn_base, 0, 2901 MLX4_RES_USAGE_DRIVER); 2902 if (err) 2903 goto err_counter; 2904 2905 ibdev->ib_uc_qpns_bitmap = 2906 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) * 2907 sizeof(long), 2908 GFP_KERNEL); 2909 if (!ibdev->ib_uc_qpns_bitmap) 2910 goto err_steer_qp_release; 2911 2912 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2913 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2914 ibdev->steer_qpn_count); 2915 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2916 dev, ibdev->steer_qpn_base, 2917 ibdev->steer_qpn_base + 2918 ibdev->steer_qpn_count - 1); 2919 if (err) 2920 goto err_steer_free_bitmap; 2921 } else { 2922 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2923 ibdev->steer_qpn_count); 2924 } 2925 } 2926 2927 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2928 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2929 2930 if (mlx4_ib_alloc_diag_counters(ibdev)) 2931 goto err_steer_free_bitmap; 2932 2933 if (ib_register_device(&ibdev->ib_dev, NULL)) 2934 goto err_diag_counters; 2935 2936 if (mlx4_ib_mad_init(ibdev)) 2937 goto err_reg; 2938 2939 if (mlx4_ib_init_sriov(ibdev)) 2940 goto err_mad; 2941 2942 if (!iboe->nb.notifier_call) { 2943 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2944 err = register_netdevice_notifier(&iboe->nb); 2945 if (err) { 2946 iboe->nb.notifier_call = NULL; 2947 goto err_notif; 2948 } 2949 } 2950 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2951 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2952 if (err) 2953 goto err_notif; 2954 } 2955 2956 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2957 if (device_create_file(&ibdev->ib_dev.dev, 2958 mlx4_class_attributes[j])) 2959 goto err_notif; 2960 } 2961 2962 ibdev->ib_active = true; 2963 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2964 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2965 &ibdev->ib_dev); 2966 2967 if (mlx4_is_mfunc(ibdev->dev)) 2968 init_pkeys(ibdev); 2969 2970 /* create paravirt contexts for any VFs which are active */ 2971 if (mlx4_is_master(ibdev->dev)) { 2972 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2973 if (j == mlx4_master_func_num(ibdev->dev)) 2974 continue; 2975 if (mlx4_is_slave_active(ibdev->dev, j)) 2976 do_slave_init(ibdev, j, 1); 2977 } 2978 } 2979 return ibdev; 2980 2981 err_notif: 2982 if (ibdev->iboe.nb.notifier_call) { 2983 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2984 pr_warn("failure unregistering notifier\n"); 2985 ibdev->iboe.nb.notifier_call = NULL; 2986 } 2987 flush_workqueue(wq); 2988 2989 mlx4_ib_close_sriov(ibdev); 2990 2991 err_mad: 2992 mlx4_ib_mad_cleanup(ibdev); 2993 2994 err_reg: 2995 ib_unregister_device(&ibdev->ib_dev); 2996 2997 err_diag_counters: 2998 mlx4_ib_diag_cleanup(ibdev); 2999 3000 err_steer_free_bitmap: 3001 kfree(ibdev->ib_uc_qpns_bitmap); 3002 3003 err_steer_qp_release: 3004 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3005 ibdev->steer_qpn_count); 3006 err_counter: 3007 for (i = 0; i < ibdev->num_ports; ++i) 3008 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 3009 3010 err_map: 3011 mlx4_ib_free_eqs(dev, ibdev); 3012 iounmap(ibdev->uar_map); 3013 3014 err_uar: 3015 mlx4_uar_free(dev, &ibdev->priv_uar); 3016 3017 err_pd: 3018 mlx4_pd_free(dev, ibdev->priv_pdn); 3019 3020 err_dealloc: 3021 ib_dealloc_device(&ibdev->ib_dev); 3022 3023 return NULL; 3024 } 3025 3026 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 3027 { 3028 int offset; 3029 3030 WARN_ON(!dev->ib_uc_qpns_bitmap); 3031 3032 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 3033 dev->steer_qpn_count, 3034 get_count_order(count)); 3035 if (offset < 0) 3036 return offset; 3037 3038 *qpn = dev->steer_qpn_base + offset; 3039 return 0; 3040 } 3041 3042 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 3043 { 3044 if (!qpn || 3045 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 3046 return; 3047 3048 BUG_ON(qpn < dev->steer_qpn_base); 3049 3050 bitmap_release_region(dev->ib_uc_qpns_bitmap, 3051 qpn - dev->steer_qpn_base, 3052 get_count_order(count)); 3053 } 3054 3055 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 3056 int is_attach) 3057 { 3058 int err; 3059 size_t flow_size; 3060 struct ib_flow_attr *flow = NULL; 3061 struct ib_flow_spec_ib *ib_spec; 3062 3063 if (is_attach) { 3064 flow_size = sizeof(struct ib_flow_attr) + 3065 sizeof(struct ib_flow_spec_ib); 3066 flow = kzalloc(flow_size, GFP_KERNEL); 3067 if (!flow) 3068 return -ENOMEM; 3069 flow->port = mqp->port; 3070 flow->num_of_specs = 1; 3071 flow->size = flow_size; 3072 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3073 ib_spec->type = IB_FLOW_SPEC_IB; 3074 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3075 /* Add an empty rule for IB L2 */ 3076 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3077 3078 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3079 IB_FLOW_DOMAIN_NIC, 3080 MLX4_FS_REGULAR, 3081 &mqp->reg_id); 3082 } else { 3083 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3084 } 3085 kfree(flow); 3086 return err; 3087 } 3088 3089 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3090 { 3091 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3092 int p; 3093 int i; 3094 3095 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3096 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3097 ibdev->ib_active = false; 3098 flush_workqueue(wq); 3099 3100 mlx4_ib_close_sriov(ibdev); 3101 mlx4_ib_mad_cleanup(ibdev); 3102 ib_unregister_device(&ibdev->ib_dev); 3103 mlx4_ib_diag_cleanup(ibdev); 3104 if (ibdev->iboe.nb.notifier_call) { 3105 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3106 pr_warn("failure unregistering notifier\n"); 3107 ibdev->iboe.nb.notifier_call = NULL; 3108 } 3109 3110 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3111 ibdev->steer_qpn_count); 3112 kfree(ibdev->ib_uc_qpns_bitmap); 3113 3114 iounmap(ibdev->uar_map); 3115 for (p = 0; p < ibdev->num_ports; ++p) 3116 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3117 3118 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3119 mlx4_CLOSE_PORT(dev, p); 3120 3121 mlx4_ib_free_eqs(dev, ibdev); 3122 3123 mlx4_uar_free(dev, &ibdev->priv_uar); 3124 mlx4_pd_free(dev, ibdev->priv_pdn); 3125 ib_dealloc_device(&ibdev->ib_dev); 3126 } 3127 3128 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3129 { 3130 struct mlx4_ib_demux_work **dm = NULL; 3131 struct mlx4_dev *dev = ibdev->dev; 3132 int i; 3133 unsigned long flags; 3134 struct mlx4_active_ports actv_ports; 3135 unsigned int ports; 3136 unsigned int first_port; 3137 3138 if (!mlx4_is_master(dev)) 3139 return; 3140 3141 actv_ports = mlx4_get_active_ports(dev, slave); 3142 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3143 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3144 3145 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3146 if (!dm) 3147 return; 3148 3149 for (i = 0; i < ports; i++) { 3150 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3151 if (!dm[i]) { 3152 while (--i >= 0) 3153 kfree(dm[i]); 3154 goto out; 3155 } 3156 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3157 dm[i]->port = first_port + i + 1; 3158 dm[i]->slave = slave; 3159 dm[i]->do_init = do_init; 3160 dm[i]->dev = ibdev; 3161 } 3162 /* initialize or tear down tunnel QPs for the slave */ 3163 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3164 if (!ibdev->sriov.is_going_down) { 3165 for (i = 0; i < ports; i++) 3166 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3167 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3168 } else { 3169 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3170 for (i = 0; i < ports; i++) 3171 kfree(dm[i]); 3172 } 3173 out: 3174 kfree(dm); 3175 return; 3176 } 3177 3178 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3179 { 3180 struct mlx4_ib_qp *mqp; 3181 unsigned long flags_qp; 3182 unsigned long flags_cq; 3183 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3184 struct list_head cq_notify_list; 3185 struct mlx4_cq *mcq; 3186 unsigned long flags; 3187 3188 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3189 INIT_LIST_HEAD(&cq_notify_list); 3190 3191 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3192 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3193 3194 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3195 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3196 if (mqp->sq.tail != mqp->sq.head) { 3197 send_mcq = to_mcq(mqp->ibqp.send_cq); 3198 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3199 if (send_mcq->mcq.comp && 3200 mqp->ibqp.send_cq->comp_handler) { 3201 if (!send_mcq->mcq.reset_notify_added) { 3202 send_mcq->mcq.reset_notify_added = 1; 3203 list_add_tail(&send_mcq->mcq.reset_notify, 3204 &cq_notify_list); 3205 } 3206 } 3207 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3208 } 3209 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3210 /* Now, handle the QP's receive queue */ 3211 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3212 /* no handling is needed for SRQ */ 3213 if (!mqp->ibqp.srq) { 3214 if (mqp->rq.tail != mqp->rq.head) { 3215 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3216 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3217 if (recv_mcq->mcq.comp && 3218 mqp->ibqp.recv_cq->comp_handler) { 3219 if (!recv_mcq->mcq.reset_notify_added) { 3220 recv_mcq->mcq.reset_notify_added = 1; 3221 list_add_tail(&recv_mcq->mcq.reset_notify, 3222 &cq_notify_list); 3223 } 3224 } 3225 spin_unlock_irqrestore(&recv_mcq->lock, 3226 flags_cq); 3227 } 3228 } 3229 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3230 } 3231 3232 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3233 mcq->comp(mcq); 3234 } 3235 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3236 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3237 } 3238 3239 static void handle_bonded_port_state_event(struct work_struct *work) 3240 { 3241 struct ib_event_work *ew = 3242 container_of(work, struct ib_event_work, work); 3243 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3244 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3245 int i; 3246 struct ib_event ibev; 3247 3248 kfree(ew); 3249 spin_lock_bh(&ibdev->iboe.lock); 3250 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3251 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3252 enum ib_port_state curr_port_state; 3253 3254 if (!curr_netdev) 3255 continue; 3256 3257 curr_port_state = 3258 (netif_running(curr_netdev) && 3259 netif_carrier_ok(curr_netdev)) ? 3260 IB_PORT_ACTIVE : IB_PORT_DOWN; 3261 3262 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3263 curr_port_state : IB_PORT_ACTIVE; 3264 } 3265 spin_unlock_bh(&ibdev->iboe.lock); 3266 3267 ibev.device = &ibdev->ib_dev; 3268 ibev.element.port_num = 1; 3269 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3270 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3271 3272 ib_dispatch_event(&ibev); 3273 } 3274 3275 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3276 { 3277 u64 sl2vl; 3278 int err; 3279 3280 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3281 if (err) { 3282 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3283 port, err); 3284 sl2vl = 0; 3285 } 3286 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3287 } 3288 3289 static void ib_sl2vl_update_work(struct work_struct *work) 3290 { 3291 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3292 struct mlx4_ib_dev *mdev = ew->ib_dev; 3293 int port = ew->port; 3294 3295 mlx4_ib_sl2vl_update(mdev, port); 3296 3297 kfree(ew); 3298 } 3299 3300 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3301 int port) 3302 { 3303 struct ib_event_work *ew; 3304 3305 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3306 if (ew) { 3307 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3308 ew->port = port; 3309 ew->ib_dev = ibdev; 3310 queue_work(wq, &ew->work); 3311 } 3312 } 3313 3314 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3315 enum mlx4_dev_event event, unsigned long param) 3316 { 3317 struct ib_event ibev; 3318 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3319 struct mlx4_eqe *eqe = NULL; 3320 struct ib_event_work *ew; 3321 int p = 0; 3322 3323 if (mlx4_is_bonded(dev) && 3324 ((event == MLX4_DEV_EVENT_PORT_UP) || 3325 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3326 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3327 if (!ew) 3328 return; 3329 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3330 ew->ib_dev = ibdev; 3331 queue_work(wq, &ew->work); 3332 return; 3333 } 3334 3335 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3336 eqe = (struct mlx4_eqe *)param; 3337 else 3338 p = (int) param; 3339 3340 switch (event) { 3341 case MLX4_DEV_EVENT_PORT_UP: 3342 if (p > ibdev->num_ports) 3343 return; 3344 if (!mlx4_is_slave(dev) && 3345 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3346 IB_LINK_LAYER_INFINIBAND) { 3347 if (mlx4_is_master(dev)) 3348 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3349 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3350 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3351 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3352 } 3353 ibev.event = IB_EVENT_PORT_ACTIVE; 3354 break; 3355 3356 case MLX4_DEV_EVENT_PORT_DOWN: 3357 if (p > ibdev->num_ports) 3358 return; 3359 ibev.event = IB_EVENT_PORT_ERR; 3360 break; 3361 3362 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3363 ibdev->ib_active = false; 3364 ibev.event = IB_EVENT_DEVICE_FATAL; 3365 mlx4_ib_handle_catas_error(ibdev); 3366 break; 3367 3368 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3369 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3370 if (!ew) 3371 break; 3372 3373 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3374 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3375 ew->ib_dev = ibdev; 3376 /* need to queue only for port owner, which uses GEN_EQE */ 3377 if (mlx4_is_master(dev)) 3378 queue_work(wq, &ew->work); 3379 else 3380 handle_port_mgmt_change_event(&ew->work); 3381 return; 3382 3383 case MLX4_DEV_EVENT_SLAVE_INIT: 3384 /* here, p is the slave id */ 3385 do_slave_init(ibdev, p, 1); 3386 if (mlx4_is_master(dev)) { 3387 int i; 3388 3389 for (i = 1; i <= ibdev->num_ports; i++) { 3390 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3391 == IB_LINK_LAYER_INFINIBAND) 3392 mlx4_ib_slave_alias_guid_event(ibdev, 3393 p, i, 3394 1); 3395 } 3396 } 3397 return; 3398 3399 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3400 if (mlx4_is_master(dev)) { 3401 int i; 3402 3403 for (i = 1; i <= ibdev->num_ports; i++) { 3404 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3405 == IB_LINK_LAYER_INFINIBAND) 3406 mlx4_ib_slave_alias_guid_event(ibdev, 3407 p, i, 3408 0); 3409 } 3410 } 3411 /* here, p is the slave id */ 3412 do_slave_init(ibdev, p, 0); 3413 return; 3414 3415 default: 3416 return; 3417 } 3418 3419 ibev.device = ibdev_ptr; 3420 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3421 3422 ib_dispatch_event(&ibev); 3423 } 3424 3425 static struct mlx4_interface mlx4_ib_interface = { 3426 .add = mlx4_ib_add, 3427 .remove = mlx4_ib_remove, 3428 .event = mlx4_ib_event, 3429 .protocol = MLX4_PROT_IB_IPV6, 3430 .flags = MLX4_INTFF_BONDING 3431 }; 3432 3433 static int __init mlx4_ib_init(void) 3434 { 3435 int err; 3436 3437 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3438 if (!wq) 3439 return -ENOMEM; 3440 3441 err = mlx4_ib_mcg_init(); 3442 if (err) 3443 goto clean_wq; 3444 3445 err = mlx4_register_interface(&mlx4_ib_interface); 3446 if (err) 3447 goto clean_mcg; 3448 3449 return 0; 3450 3451 clean_mcg: 3452 mlx4_ib_mcg_destroy(); 3453 3454 clean_wq: 3455 destroy_workqueue(wq); 3456 return err; 3457 } 3458 3459 static void __exit mlx4_ib_cleanup(void) 3460 { 3461 mlx4_unregister_interface(&mlx4_ib_interface); 3462 mlx4_ib_mcg_destroy(); 3463 destroy_workqueue(wq); 3464 } 3465 3466 module_init(mlx4_ib_init); 3467 module_exit(mlx4_ib_cleanup); 3468