1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u32 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, 133 u32 port_num) 134 { 135 struct mlx4_ib_dev *ibdev = to_mdev(device); 136 struct net_device *dev; 137 138 rcu_read_lock(); 139 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 140 141 if (dev) { 142 if (mlx4_is_bonded(ibdev->dev)) { 143 struct net_device *upper = NULL; 144 145 upper = netdev_master_upper_dev_get_rcu(dev); 146 if (upper) { 147 struct net_device *active; 148 149 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 150 if (active) 151 dev = active; 152 } 153 } 154 } 155 if (dev) 156 dev_hold(dev); 157 158 rcu_read_unlock(); 159 return dev; 160 } 161 162 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 163 struct mlx4_ib_dev *ibdev, 164 u32 port_num) 165 { 166 struct mlx4_cmd_mailbox *mailbox; 167 int err; 168 struct mlx4_dev *dev = ibdev->dev; 169 int i; 170 union ib_gid *gid_tbl; 171 172 mailbox = mlx4_alloc_cmd_mailbox(dev); 173 if (IS_ERR(mailbox)) 174 return -ENOMEM; 175 176 gid_tbl = mailbox->buf; 177 178 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 179 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 180 181 err = mlx4_cmd(dev, mailbox->dma, 182 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 183 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 184 MLX4_CMD_WRAPPED); 185 if (mlx4_is_bonded(dev)) 186 err += mlx4_cmd(dev, mailbox->dma, 187 MLX4_SET_PORT_GID_TABLE << 8 | 2, 188 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 189 MLX4_CMD_WRAPPED); 190 191 mlx4_free_cmd_mailbox(dev, mailbox); 192 return err; 193 } 194 195 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 196 struct mlx4_ib_dev *ibdev, 197 u32 port_num) 198 { 199 struct mlx4_cmd_mailbox *mailbox; 200 int err; 201 struct mlx4_dev *dev = ibdev->dev; 202 int i; 203 struct { 204 union ib_gid gid; 205 __be32 rsrvd1[2]; 206 __be16 rsrvd2; 207 u8 type; 208 u8 version; 209 __be32 rsrvd3; 210 } *gid_tbl; 211 212 mailbox = mlx4_alloc_cmd_mailbox(dev); 213 if (IS_ERR(mailbox)) 214 return -ENOMEM; 215 216 gid_tbl = mailbox->buf; 217 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 218 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 219 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 220 gid_tbl[i].version = 2; 221 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 222 gid_tbl[i].type = 1; 223 } 224 } 225 226 err = mlx4_cmd(dev, mailbox->dma, 227 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 228 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 229 MLX4_CMD_WRAPPED); 230 if (mlx4_is_bonded(dev)) 231 err += mlx4_cmd(dev, mailbox->dma, 232 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 233 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 234 MLX4_CMD_WRAPPED); 235 236 mlx4_free_cmd_mailbox(dev, mailbox); 237 return err; 238 } 239 240 static int mlx4_ib_update_gids(struct gid_entry *gids, 241 struct mlx4_ib_dev *ibdev, 242 u32 port_num) 243 { 244 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 245 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 246 247 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 248 } 249 250 static void free_gid_entry(struct gid_entry *entry) 251 { 252 memset(&entry->gid, 0, sizeof(entry->gid)); 253 kfree(entry->ctx); 254 entry->ctx = NULL; 255 } 256 257 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 258 { 259 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 260 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 261 struct mlx4_port_gid_table *port_gid_table; 262 int free = -1, found = -1; 263 int ret = 0; 264 int hw_update = 0; 265 int i; 266 struct gid_entry *gids = NULL; 267 u16 vlan_id = 0xffff; 268 u8 mac[ETH_ALEN]; 269 270 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 271 return -EINVAL; 272 273 if (attr->port_num > MLX4_MAX_PORTS) 274 return -EINVAL; 275 276 if (!context) 277 return -EINVAL; 278 279 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 280 if (ret) 281 return ret; 282 port_gid_table = &iboe->gids[attr->port_num - 1]; 283 spin_lock_bh(&iboe->lock); 284 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 285 if (!memcmp(&port_gid_table->gids[i].gid, 286 &attr->gid, sizeof(attr->gid)) && 287 port_gid_table->gids[i].gid_type == attr->gid_type && 288 port_gid_table->gids[i].vlan_id == vlan_id) { 289 found = i; 290 break; 291 } 292 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 293 free = i; /* HW has space */ 294 } 295 296 if (found < 0) { 297 if (free < 0) { 298 ret = -ENOSPC; 299 } else { 300 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 301 if (!port_gid_table->gids[free].ctx) { 302 ret = -ENOMEM; 303 } else { 304 *context = port_gid_table->gids[free].ctx; 305 memcpy(&port_gid_table->gids[free].gid, 306 &attr->gid, sizeof(attr->gid)); 307 port_gid_table->gids[free].gid_type = attr->gid_type; 308 port_gid_table->gids[free].vlan_id = vlan_id; 309 port_gid_table->gids[free].ctx->real_index = free; 310 port_gid_table->gids[free].ctx->refcount = 1; 311 hw_update = 1; 312 } 313 } 314 } else { 315 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 316 *context = ctx; 317 ctx->refcount++; 318 } 319 if (!ret && hw_update) { 320 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 321 GFP_ATOMIC); 322 if (!gids) { 323 ret = -ENOMEM; 324 *context = NULL; 325 free_gid_entry(&port_gid_table->gids[free]); 326 } else { 327 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 328 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 329 gids[i].gid_type = port_gid_table->gids[i].gid_type; 330 } 331 } 332 } 333 spin_unlock_bh(&iboe->lock); 334 335 if (!ret && hw_update) { 336 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 337 if (ret) { 338 spin_lock_bh(&iboe->lock); 339 *context = NULL; 340 free_gid_entry(&port_gid_table->gids[free]); 341 spin_unlock_bh(&iboe->lock); 342 } 343 kfree(gids); 344 } 345 346 return ret; 347 } 348 349 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 350 { 351 struct gid_cache_context *ctx = *context; 352 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 353 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 354 struct mlx4_port_gid_table *port_gid_table; 355 int ret = 0; 356 int hw_update = 0; 357 struct gid_entry *gids = NULL; 358 359 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 360 return -EINVAL; 361 362 if (attr->port_num > MLX4_MAX_PORTS) 363 return -EINVAL; 364 365 port_gid_table = &iboe->gids[attr->port_num - 1]; 366 spin_lock_bh(&iboe->lock); 367 if (ctx) { 368 ctx->refcount--; 369 if (!ctx->refcount) { 370 unsigned int real_index = ctx->real_index; 371 372 free_gid_entry(&port_gid_table->gids[real_index]); 373 hw_update = 1; 374 } 375 } 376 if (!ret && hw_update) { 377 int i; 378 379 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 380 GFP_ATOMIC); 381 if (!gids) { 382 ret = -ENOMEM; 383 } else { 384 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 385 memcpy(&gids[i].gid, 386 &port_gid_table->gids[i].gid, 387 sizeof(union ib_gid)); 388 gids[i].gid_type = 389 port_gid_table->gids[i].gid_type; 390 } 391 } 392 } 393 spin_unlock_bh(&iboe->lock); 394 395 if (!ret && hw_update) { 396 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 397 kfree(gids); 398 } 399 return ret; 400 } 401 402 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 403 const struct ib_gid_attr *attr) 404 { 405 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 406 struct gid_cache_context *ctx = NULL; 407 struct mlx4_port_gid_table *port_gid_table; 408 int real_index = -EINVAL; 409 int i; 410 unsigned long flags; 411 u32 port_num = attr->port_num; 412 413 if (port_num > MLX4_MAX_PORTS) 414 return -EINVAL; 415 416 if (mlx4_is_bonded(ibdev->dev)) 417 port_num = 1; 418 419 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 420 return attr->index; 421 422 spin_lock_irqsave(&iboe->lock, flags); 423 port_gid_table = &iboe->gids[port_num - 1]; 424 425 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 426 if (!memcmp(&port_gid_table->gids[i].gid, 427 &attr->gid, sizeof(attr->gid)) && 428 attr->gid_type == port_gid_table->gids[i].gid_type) { 429 ctx = port_gid_table->gids[i].ctx; 430 break; 431 } 432 if (ctx) 433 real_index = ctx->real_index; 434 spin_unlock_irqrestore(&iboe->lock, flags); 435 return real_index; 436 } 437 438 static int mlx4_ib_query_device(struct ib_device *ibdev, 439 struct ib_device_attr *props, 440 struct ib_udata *uhw) 441 { 442 struct mlx4_ib_dev *dev = to_mdev(ibdev); 443 struct ib_smp *in_mad = NULL; 444 struct ib_smp *out_mad = NULL; 445 int err; 446 int have_ib_ports; 447 struct mlx4_uverbs_ex_query_device cmd; 448 struct mlx4_uverbs_ex_query_device_resp resp = {}; 449 struct mlx4_clock_params clock_params; 450 451 if (uhw->inlen) { 452 if (uhw->inlen < sizeof(cmd)) 453 return -EINVAL; 454 455 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 456 if (err) 457 return err; 458 459 if (cmd.comp_mask) 460 return -EINVAL; 461 462 if (cmd.reserved) 463 return -EINVAL; 464 } 465 466 resp.response_length = offsetof(typeof(resp), response_length) + 467 sizeof(resp.response_length); 468 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 469 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 470 err = -ENOMEM; 471 if (!in_mad || !out_mad) 472 goto out; 473 474 init_query_mad(in_mad); 475 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 476 477 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 478 1, NULL, NULL, in_mad, out_mad); 479 if (err) 480 goto out; 481 482 memset(props, 0, sizeof *props); 483 484 have_ib_ports = num_ib_ports(dev->dev); 485 486 props->fw_ver = dev->dev->caps.fw_ver; 487 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 488 IB_DEVICE_PORT_ACTIVE_EVENT | 489 IB_DEVICE_SYS_IMAGE_GUID | 490 IB_DEVICE_RC_RNR_NAK_GEN | 491 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 492 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 493 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 494 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 495 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 496 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 497 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 498 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 499 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 500 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 501 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 502 if (dev->dev->caps.max_gso_sz && 503 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 504 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 505 props->device_cap_flags |= IB_DEVICE_UD_TSO; 506 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 507 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 508 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 509 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 510 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 511 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 512 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 513 props->device_cap_flags |= IB_DEVICE_XRC; 514 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 515 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 516 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 517 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 518 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 519 else 520 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 521 } 522 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 523 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 524 525 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 526 527 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 528 0xffffff; 529 props->vendor_part_id = dev->dev->persist->pdev->device; 530 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 531 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 532 533 props->max_mr_size = ~0ull; 534 props->page_size_cap = dev->dev->caps.page_size_cap; 535 props->max_qp = dev->dev->quotas.qp; 536 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 537 props->max_send_sge = 538 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 539 props->max_recv_sge = 540 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 541 props->max_sge_rd = MLX4_MAX_SGE_RD; 542 props->max_cq = dev->dev->quotas.cq; 543 props->max_cqe = dev->dev->caps.max_cqes; 544 props->max_mr = dev->dev->quotas.mpt; 545 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 546 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 547 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 548 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 549 props->max_srq = dev->dev->quotas.srq; 550 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 551 props->max_srq_sge = dev->dev->caps.max_srq_sge; 552 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 553 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 554 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 555 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 556 props->masked_atomic_cap = props->atomic_cap; 557 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 558 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 559 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 560 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 561 props->max_mcast_grp; 562 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 563 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 564 props->max_ah = INT_MAX; 565 566 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 567 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 568 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 569 props->rss_caps.max_rwq_indirection_tables = 570 props->max_qp; 571 props->rss_caps.max_rwq_indirection_table_size = 572 dev->dev->caps.max_rss_tbl_sz; 573 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 574 props->max_wq_type_rq = props->max_qp; 575 } 576 577 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 578 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 579 } 580 581 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 582 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 583 584 if (!mlx4_is_slave(dev->dev)) 585 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 586 587 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 588 resp.response_length += sizeof(resp.hca_core_clock_offset); 589 if (!err && !mlx4_is_slave(dev->dev)) { 590 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 591 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 592 } 593 } 594 595 if (uhw->outlen >= resp.response_length + 596 sizeof(resp.max_inl_recv_sz)) { 597 resp.response_length += sizeof(resp.max_inl_recv_sz); 598 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 599 sizeof(struct mlx4_wqe_data_seg); 600 } 601 602 if (offsetofend(typeof(resp), rss_caps) <= uhw->outlen) { 603 if (props->rss_caps.supported_qpts) { 604 resp.rss_caps.rx_hash_function = 605 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 606 607 resp.rss_caps.rx_hash_fields_mask = 608 MLX4_IB_RX_HASH_SRC_IPV4 | 609 MLX4_IB_RX_HASH_DST_IPV4 | 610 MLX4_IB_RX_HASH_SRC_IPV6 | 611 MLX4_IB_RX_HASH_DST_IPV6 | 612 MLX4_IB_RX_HASH_SRC_PORT_TCP | 613 MLX4_IB_RX_HASH_DST_PORT_TCP | 614 MLX4_IB_RX_HASH_SRC_PORT_UDP | 615 MLX4_IB_RX_HASH_DST_PORT_UDP; 616 617 if (dev->dev->caps.tunnel_offload_mode == 618 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 619 resp.rss_caps.rx_hash_fields_mask |= 620 MLX4_IB_RX_HASH_INNER; 621 } 622 resp.response_length = offsetof(typeof(resp), rss_caps) + 623 sizeof(resp.rss_caps); 624 } 625 626 if (offsetofend(typeof(resp), tso_caps) <= uhw->outlen) { 627 if (dev->dev->caps.max_gso_sz && 628 ((mlx4_ib_port_link_layer(ibdev, 1) == 629 IB_LINK_LAYER_ETHERNET) || 630 (mlx4_ib_port_link_layer(ibdev, 2) == 631 IB_LINK_LAYER_ETHERNET))) { 632 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 633 resp.tso_caps.supported_qpts |= 634 1 << IB_QPT_RAW_PACKET; 635 } 636 resp.response_length = offsetof(typeof(resp), tso_caps) + 637 sizeof(resp.tso_caps); 638 } 639 640 if (uhw->outlen) { 641 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 642 if (err) 643 goto out; 644 } 645 out: 646 kfree(in_mad); 647 kfree(out_mad); 648 649 return err; 650 } 651 652 static enum rdma_link_layer 653 mlx4_ib_port_link_layer(struct ib_device *device, u32 port_num) 654 { 655 struct mlx4_dev *dev = to_mdev(device)->dev; 656 657 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 658 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 659 } 660 661 static int ib_link_query_port(struct ib_device *ibdev, u32 port, 662 struct ib_port_attr *props, int netw_view) 663 { 664 struct ib_smp *in_mad = NULL; 665 struct ib_smp *out_mad = NULL; 666 int ext_active_speed; 667 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 668 int err = -ENOMEM; 669 670 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 671 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 672 if (!in_mad || !out_mad) 673 goto out; 674 675 init_query_mad(in_mad); 676 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 677 in_mad->attr_mod = cpu_to_be32(port); 678 679 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 680 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 681 682 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 683 in_mad, out_mad); 684 if (err) 685 goto out; 686 687 688 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 689 props->lmc = out_mad->data[34] & 0x7; 690 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 691 props->sm_sl = out_mad->data[36] & 0xf; 692 props->state = out_mad->data[32] & 0xf; 693 props->phys_state = out_mad->data[33] >> 4; 694 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 695 if (netw_view) 696 props->gid_tbl_len = out_mad->data[50]; 697 else 698 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 699 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 700 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 701 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 702 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 703 props->active_width = out_mad->data[31] & 0xf; 704 props->active_speed = out_mad->data[35] >> 4; 705 props->max_mtu = out_mad->data[41] & 0xf; 706 props->active_mtu = out_mad->data[36] >> 4; 707 props->subnet_timeout = out_mad->data[51] & 0x1f; 708 props->max_vl_num = out_mad->data[37] >> 4; 709 props->init_type_reply = out_mad->data[41] >> 4; 710 711 /* Check if extended speeds (EDR/FDR/...) are supported */ 712 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 713 ext_active_speed = out_mad->data[62] >> 4; 714 715 switch (ext_active_speed) { 716 case 1: 717 props->active_speed = IB_SPEED_FDR; 718 break; 719 case 2: 720 props->active_speed = IB_SPEED_EDR; 721 break; 722 } 723 } 724 725 /* If reported active speed is QDR, check if is FDR-10 */ 726 if (props->active_speed == IB_SPEED_QDR) { 727 init_query_mad(in_mad); 728 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 729 in_mad->attr_mod = cpu_to_be32(port); 730 731 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 732 NULL, NULL, in_mad, out_mad); 733 if (err) 734 goto out; 735 736 /* Checking LinkSpeedActive for FDR-10 */ 737 if (out_mad->data[15] & 0x1) 738 props->active_speed = IB_SPEED_FDR10; 739 } 740 741 /* Avoid wrong speed value returned by FW if the IB link is down. */ 742 if (props->state == IB_PORT_DOWN) 743 props->active_speed = IB_SPEED_SDR; 744 745 out: 746 kfree(in_mad); 747 kfree(out_mad); 748 return err; 749 } 750 751 static u8 state_to_phys_state(enum ib_port_state state) 752 { 753 return state == IB_PORT_ACTIVE ? 754 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 755 } 756 757 static int eth_link_query_port(struct ib_device *ibdev, u32 port, 758 struct ib_port_attr *props) 759 { 760 761 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 762 struct mlx4_ib_iboe *iboe = &mdev->iboe; 763 struct net_device *ndev; 764 enum ib_mtu tmp; 765 struct mlx4_cmd_mailbox *mailbox; 766 int err = 0; 767 int is_bonded = mlx4_is_bonded(mdev->dev); 768 769 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 770 if (IS_ERR(mailbox)) 771 return PTR_ERR(mailbox); 772 773 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 774 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 775 MLX4_CMD_WRAPPED); 776 if (err) 777 goto out; 778 779 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 780 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 781 IB_WIDTH_4X : IB_WIDTH_1X; 782 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 783 IB_SPEED_FDR : IB_SPEED_QDR; 784 props->port_cap_flags = IB_PORT_CM_SUP; 785 props->ip_gids = true; 786 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 787 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 788 if (mdev->dev->caps.pkey_table_len[port]) 789 props->pkey_tbl_len = 1; 790 props->max_mtu = IB_MTU_4096; 791 props->max_vl_num = 2; 792 props->state = IB_PORT_DOWN; 793 props->phys_state = state_to_phys_state(props->state); 794 props->active_mtu = IB_MTU_256; 795 spin_lock_bh(&iboe->lock); 796 ndev = iboe->netdevs[port - 1]; 797 if (ndev && is_bonded) { 798 rcu_read_lock(); /* required to get upper dev */ 799 ndev = netdev_master_upper_dev_get_rcu(ndev); 800 rcu_read_unlock(); 801 } 802 if (!ndev) 803 goto out_unlock; 804 805 tmp = iboe_get_mtu(ndev->mtu); 806 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 807 808 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 809 IB_PORT_ACTIVE : IB_PORT_DOWN; 810 props->phys_state = state_to_phys_state(props->state); 811 out_unlock: 812 spin_unlock_bh(&iboe->lock); 813 out: 814 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 815 return err; 816 } 817 818 int __mlx4_ib_query_port(struct ib_device *ibdev, u32 port, 819 struct ib_port_attr *props, int netw_view) 820 { 821 int err; 822 823 /* props being zeroed by the caller, avoid zeroing it here */ 824 825 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 826 ib_link_query_port(ibdev, port, props, netw_view) : 827 eth_link_query_port(ibdev, port, props); 828 829 return err; 830 } 831 832 static int mlx4_ib_query_port(struct ib_device *ibdev, u32 port, 833 struct ib_port_attr *props) 834 { 835 /* returns host view */ 836 return __mlx4_ib_query_port(ibdev, port, props, 0); 837 } 838 839 int __mlx4_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 840 union ib_gid *gid, int netw_view) 841 { 842 struct ib_smp *in_mad = NULL; 843 struct ib_smp *out_mad = NULL; 844 int err = -ENOMEM; 845 struct mlx4_ib_dev *dev = to_mdev(ibdev); 846 int clear = 0; 847 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 848 849 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 850 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 851 if (!in_mad || !out_mad) 852 goto out; 853 854 init_query_mad(in_mad); 855 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 856 in_mad->attr_mod = cpu_to_be32(port); 857 858 if (mlx4_is_mfunc(dev->dev) && netw_view) 859 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 860 861 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 862 if (err) 863 goto out; 864 865 memcpy(gid->raw, out_mad->data + 8, 8); 866 867 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 868 if (index) { 869 /* For any index > 0, return the null guid */ 870 err = 0; 871 clear = 1; 872 goto out; 873 } 874 } 875 876 init_query_mad(in_mad); 877 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 878 in_mad->attr_mod = cpu_to_be32(index / 8); 879 880 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 881 NULL, NULL, in_mad, out_mad); 882 if (err) 883 goto out; 884 885 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 886 887 out: 888 if (clear) 889 memset(gid->raw + 8, 0, 8); 890 kfree(in_mad); 891 kfree(out_mad); 892 return err; 893 } 894 895 static int mlx4_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 896 union ib_gid *gid) 897 { 898 if (rdma_protocol_ib(ibdev, port)) 899 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 900 return 0; 901 } 902 903 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u32 port, 904 u64 *sl2vl_tbl) 905 { 906 union sl2vl_tbl_to_u64 sl2vl64; 907 struct ib_smp *in_mad = NULL; 908 struct ib_smp *out_mad = NULL; 909 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 910 int err = -ENOMEM; 911 int jj; 912 913 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 914 *sl2vl_tbl = 0; 915 return 0; 916 } 917 918 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 919 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 920 if (!in_mad || !out_mad) 921 goto out; 922 923 init_query_mad(in_mad); 924 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 925 in_mad->attr_mod = 0; 926 927 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 928 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 929 930 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 931 in_mad, out_mad); 932 if (err) 933 goto out; 934 935 for (jj = 0; jj < 8; jj++) 936 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 937 *sl2vl_tbl = sl2vl64.sl64; 938 939 out: 940 kfree(in_mad); 941 kfree(out_mad); 942 return err; 943 } 944 945 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 946 { 947 u64 sl2vl; 948 int i; 949 int err; 950 951 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 952 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 953 continue; 954 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 955 if (err) { 956 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 957 i, err); 958 sl2vl = 0; 959 } 960 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 961 } 962 } 963 964 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 965 u16 *pkey, int netw_view) 966 { 967 struct ib_smp *in_mad = NULL; 968 struct ib_smp *out_mad = NULL; 969 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 970 int err = -ENOMEM; 971 972 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 973 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 974 if (!in_mad || !out_mad) 975 goto out; 976 977 init_query_mad(in_mad); 978 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 979 in_mad->attr_mod = cpu_to_be32(index / 32); 980 981 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 982 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 983 984 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 985 in_mad, out_mad); 986 if (err) 987 goto out; 988 989 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 990 991 out: 992 kfree(in_mad); 993 kfree(out_mad); 994 return err; 995 } 996 997 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 998 u16 *pkey) 999 { 1000 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 1001 } 1002 1003 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 1004 struct ib_device_modify *props) 1005 { 1006 struct mlx4_cmd_mailbox *mailbox; 1007 unsigned long flags; 1008 1009 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1010 return -EOPNOTSUPP; 1011 1012 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1013 return 0; 1014 1015 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 1016 return -EOPNOTSUPP; 1017 1018 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 1019 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1020 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1021 1022 /* 1023 * If possible, pass node desc to FW, so it can generate 1024 * a 144 trap. If cmd fails, just ignore. 1025 */ 1026 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1027 if (IS_ERR(mailbox)) 1028 return 0; 1029 1030 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1031 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1032 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1033 1034 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1035 1036 return 0; 1037 } 1038 1039 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u32 port, 1040 int reset_qkey_viols, u32 cap_mask) 1041 { 1042 struct mlx4_cmd_mailbox *mailbox; 1043 int err; 1044 1045 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1046 if (IS_ERR(mailbox)) 1047 return PTR_ERR(mailbox); 1048 1049 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1050 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1051 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1052 } else { 1053 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1054 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1055 } 1056 1057 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1058 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1059 MLX4_CMD_WRAPPED); 1060 1061 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1062 return err; 1063 } 1064 1065 static int mlx4_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1066 struct ib_port_modify *props) 1067 { 1068 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1069 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1070 struct ib_port_attr attr; 1071 u32 cap_mask; 1072 int err; 1073 1074 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1075 * of whether port link layer is ETH or IB. For ETH ports, qkey 1076 * violations and port capabilities are not meaningful. 1077 */ 1078 if (is_eth) 1079 return 0; 1080 1081 mutex_lock(&mdev->cap_mask_mutex); 1082 1083 err = ib_query_port(ibdev, port, &attr); 1084 if (err) 1085 goto out; 1086 1087 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1088 ~props->clr_port_cap_mask; 1089 1090 err = mlx4_ib_SET_PORT(mdev, port, 1091 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1092 cap_mask); 1093 1094 out: 1095 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1096 return err; 1097 } 1098 1099 static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx, 1100 struct ib_udata *udata) 1101 { 1102 struct ib_device *ibdev = uctx->device; 1103 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1104 struct mlx4_ib_ucontext *context = to_mucontext(uctx); 1105 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1106 struct mlx4_ib_alloc_ucontext_resp resp; 1107 int err; 1108 1109 if (!dev->ib_active) 1110 return -EAGAIN; 1111 1112 if (ibdev->ops.uverbs_abi_ver == 1113 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1114 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1115 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1116 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1117 } else { 1118 resp.dev_caps = dev->dev->caps.userspace_caps; 1119 resp.qp_tab_size = dev->dev->caps.num_qps; 1120 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1121 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1122 resp.cqe_size = dev->dev->caps.cqe_size; 1123 } 1124 1125 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1126 if (err) 1127 return err; 1128 1129 INIT_LIST_HEAD(&context->db_page_list); 1130 mutex_init(&context->db_page_mutex); 1131 1132 INIT_LIST_HEAD(&context->wqn_ranges_list); 1133 mutex_init(&context->wqn_ranges_mutex); 1134 1135 if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1136 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1137 else 1138 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1139 1140 if (err) { 1141 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1142 return -EFAULT; 1143 } 1144 1145 return err; 1146 } 1147 1148 static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1149 { 1150 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1151 1152 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1153 } 1154 1155 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1156 { 1157 } 1158 1159 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1160 { 1161 struct mlx4_ib_dev *dev = to_mdev(context->device); 1162 1163 switch (vma->vm_pgoff) { 1164 case 0: 1165 return rdma_user_mmap_io(context, vma, 1166 to_mucontext(context)->uar.pfn, 1167 PAGE_SIZE, 1168 pgprot_noncached(vma->vm_page_prot), 1169 NULL); 1170 1171 case 1: 1172 if (dev->dev->caps.bf_reg_size == 0) 1173 return -EINVAL; 1174 return rdma_user_mmap_io( 1175 context, vma, 1176 to_mucontext(context)->uar.pfn + 1177 dev->dev->caps.num_uars, 1178 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot), 1179 NULL); 1180 1181 case 3: { 1182 struct mlx4_clock_params params; 1183 int ret; 1184 1185 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1186 if (ret) 1187 return ret; 1188 1189 return rdma_user_mmap_io( 1190 context, vma, 1191 (pci_resource_start(dev->dev->persist->pdev, 1192 params.bar) + 1193 params.offset) >> 1194 PAGE_SHIFT, 1195 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot), 1196 NULL); 1197 } 1198 1199 default: 1200 return -EINVAL; 1201 } 1202 } 1203 1204 static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1205 { 1206 struct mlx4_ib_pd *pd = to_mpd(ibpd); 1207 struct ib_device *ibdev = ibpd->device; 1208 int err; 1209 1210 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1211 if (err) 1212 return err; 1213 1214 if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) { 1215 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1216 return -EFAULT; 1217 } 1218 return 0; 1219 } 1220 1221 static int mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1222 { 1223 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1224 return 0; 1225 } 1226 1227 static int mlx4_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 1228 { 1229 struct mlx4_ib_dev *dev = to_mdev(ibxrcd->device); 1230 struct mlx4_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 1231 struct ib_cq_init_attr cq_attr = {}; 1232 int err; 1233 1234 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1235 return -EOPNOTSUPP; 1236 1237 err = mlx4_xrcd_alloc(dev->dev, &xrcd->xrcdn); 1238 if (err) 1239 return err; 1240 1241 xrcd->pd = ib_alloc_pd(ibxrcd->device, 0); 1242 if (IS_ERR(xrcd->pd)) { 1243 err = PTR_ERR(xrcd->pd); 1244 goto err2; 1245 } 1246 1247 cq_attr.cqe = 1; 1248 xrcd->cq = ib_create_cq(ibxrcd->device, NULL, NULL, xrcd, &cq_attr); 1249 if (IS_ERR(xrcd->cq)) { 1250 err = PTR_ERR(xrcd->cq); 1251 goto err3; 1252 } 1253 1254 return 0; 1255 1256 err3: 1257 ib_dealloc_pd(xrcd->pd); 1258 err2: 1259 mlx4_xrcd_free(dev->dev, xrcd->xrcdn); 1260 return err; 1261 } 1262 1263 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 1264 { 1265 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1266 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1267 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1268 return 0; 1269 } 1270 1271 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1272 { 1273 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1274 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1275 struct mlx4_ib_gid_entry *ge; 1276 1277 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1278 if (!ge) 1279 return -ENOMEM; 1280 1281 ge->gid = *gid; 1282 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1283 ge->port = mqp->port; 1284 ge->added = 1; 1285 } 1286 1287 mutex_lock(&mqp->mutex); 1288 list_add_tail(&ge->list, &mqp->gid_list); 1289 mutex_unlock(&mqp->mutex); 1290 1291 return 0; 1292 } 1293 1294 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1295 struct mlx4_ib_counters *ctr_table) 1296 { 1297 struct counter_index *counter, *tmp_count; 1298 1299 mutex_lock(&ctr_table->mutex); 1300 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1301 list) { 1302 if (counter->allocated) 1303 mlx4_counter_free(ibdev->dev, counter->index); 1304 list_del(&counter->list); 1305 kfree(counter); 1306 } 1307 mutex_unlock(&ctr_table->mutex); 1308 } 1309 1310 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1311 union ib_gid *gid) 1312 { 1313 struct net_device *ndev; 1314 int ret = 0; 1315 1316 if (!mqp->port) 1317 return 0; 1318 1319 spin_lock_bh(&mdev->iboe.lock); 1320 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1321 if (ndev) 1322 dev_hold(ndev); 1323 spin_unlock_bh(&mdev->iboe.lock); 1324 1325 if (ndev) { 1326 ret = 1; 1327 dev_put(ndev); 1328 } 1329 1330 return ret; 1331 } 1332 1333 struct mlx4_ib_steering { 1334 struct list_head list; 1335 struct mlx4_flow_reg_id reg_id; 1336 union ib_gid gid; 1337 }; 1338 1339 #define LAST_ETH_FIELD vlan_tag 1340 #define LAST_IB_FIELD sl 1341 #define LAST_IPV4_FIELD dst_ip 1342 #define LAST_TCP_UDP_FIELD src_port 1343 1344 /* Field is the last supported field */ 1345 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1346 memchr_inv((void *)&filter.field +\ 1347 sizeof(filter.field), 0,\ 1348 sizeof(filter) -\ 1349 offsetof(typeof(filter), field) -\ 1350 sizeof(filter.field)) 1351 1352 static int parse_flow_attr(struct mlx4_dev *dev, 1353 u32 qp_num, 1354 union ib_flow_spec *ib_spec, 1355 struct _rule_hw *mlx4_spec) 1356 { 1357 enum mlx4_net_trans_rule_id type; 1358 1359 switch (ib_spec->type) { 1360 case IB_FLOW_SPEC_ETH: 1361 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1362 return -ENOTSUPP; 1363 1364 type = MLX4_NET_TRANS_RULE_ID_ETH; 1365 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1366 ETH_ALEN); 1367 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1368 ETH_ALEN); 1369 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1370 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1371 break; 1372 case IB_FLOW_SPEC_IB: 1373 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1374 return -ENOTSUPP; 1375 1376 type = MLX4_NET_TRANS_RULE_ID_IB; 1377 mlx4_spec->ib.l3_qpn = 1378 cpu_to_be32(qp_num); 1379 mlx4_spec->ib.qpn_mask = 1380 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1381 break; 1382 1383 1384 case IB_FLOW_SPEC_IPV4: 1385 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1386 return -ENOTSUPP; 1387 1388 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1389 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1390 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1391 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1392 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1393 break; 1394 1395 case IB_FLOW_SPEC_TCP: 1396 case IB_FLOW_SPEC_UDP: 1397 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1398 return -ENOTSUPP; 1399 1400 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1401 MLX4_NET_TRANS_RULE_ID_TCP : 1402 MLX4_NET_TRANS_RULE_ID_UDP; 1403 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1404 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1405 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1406 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1407 break; 1408 1409 default: 1410 return -EINVAL; 1411 } 1412 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1413 mlx4_hw_rule_sz(dev, type) < 0) 1414 return -EINVAL; 1415 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1416 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1417 return mlx4_hw_rule_sz(dev, type); 1418 } 1419 1420 struct default_rules { 1421 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1422 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1423 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1424 __u8 link_layer; 1425 }; 1426 static const struct default_rules default_table[] = { 1427 { 1428 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1429 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1430 .rules_create_list = {IB_FLOW_SPEC_IB}, 1431 .link_layer = IB_LINK_LAYER_INFINIBAND 1432 } 1433 }; 1434 1435 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1436 struct ib_flow_attr *flow_attr) 1437 { 1438 int i, j, k; 1439 void *ib_flow; 1440 const struct default_rules *pdefault_rules = default_table; 1441 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1442 1443 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1444 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1445 memset(&field_types, 0, sizeof(field_types)); 1446 1447 if (link_layer != pdefault_rules->link_layer) 1448 continue; 1449 1450 ib_flow = flow_attr + 1; 1451 /* we assume the specs are sorted */ 1452 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1453 j < flow_attr->num_of_specs; k++) { 1454 union ib_flow_spec *current_flow = 1455 (union ib_flow_spec *)ib_flow; 1456 1457 /* same layer but different type */ 1458 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1459 (pdefault_rules->mandatory_fields[k] & 1460 IB_FLOW_SPEC_LAYER_MASK)) && 1461 (current_flow->type != 1462 pdefault_rules->mandatory_fields[k])) 1463 goto out; 1464 1465 /* same layer, try match next one */ 1466 if (current_flow->type == 1467 pdefault_rules->mandatory_fields[k]) { 1468 j++; 1469 ib_flow += 1470 ((union ib_flow_spec *)ib_flow)->size; 1471 } 1472 } 1473 1474 ib_flow = flow_attr + 1; 1475 for (j = 0; j < flow_attr->num_of_specs; 1476 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1477 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1478 /* same layer and same type */ 1479 if (((union ib_flow_spec *)ib_flow)->type == 1480 pdefault_rules->mandatory_not_fields[k]) 1481 goto out; 1482 1483 return i; 1484 } 1485 out: 1486 return -1; 1487 } 1488 1489 static int __mlx4_ib_create_default_rules( 1490 struct mlx4_ib_dev *mdev, 1491 struct ib_qp *qp, 1492 const struct default_rules *pdefault_rules, 1493 struct _rule_hw *mlx4_spec) { 1494 int size = 0; 1495 int i; 1496 1497 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1498 union ib_flow_spec ib_spec = {}; 1499 int ret; 1500 1501 switch (pdefault_rules->rules_create_list[i]) { 1502 case 0: 1503 /* no rule */ 1504 continue; 1505 case IB_FLOW_SPEC_IB: 1506 ib_spec.type = IB_FLOW_SPEC_IB; 1507 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1508 1509 break; 1510 default: 1511 /* invalid rule */ 1512 return -EINVAL; 1513 } 1514 /* We must put empty rule, qpn is being ignored */ 1515 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1516 mlx4_spec); 1517 if (ret < 0) { 1518 pr_info("invalid parsing\n"); 1519 return -EINVAL; 1520 } 1521 1522 mlx4_spec = (void *)mlx4_spec + ret; 1523 size += ret; 1524 } 1525 return size; 1526 } 1527 1528 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1529 int domain, 1530 enum mlx4_net_trans_promisc_mode flow_type, 1531 u64 *reg_id) 1532 { 1533 int ret, i; 1534 int size = 0; 1535 void *ib_flow; 1536 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1537 struct mlx4_cmd_mailbox *mailbox; 1538 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1539 int default_flow; 1540 1541 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1542 pr_err("Invalid priority value %d\n", flow_attr->priority); 1543 return -EINVAL; 1544 } 1545 1546 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1547 return -EINVAL; 1548 1549 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1550 if (IS_ERR(mailbox)) 1551 return PTR_ERR(mailbox); 1552 ctrl = mailbox->buf; 1553 1554 ctrl->prio = cpu_to_be16(domain | flow_attr->priority); 1555 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1556 ctrl->port = flow_attr->port; 1557 ctrl->qpn = cpu_to_be32(qp->qp_num); 1558 1559 ib_flow = flow_attr + 1; 1560 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1561 /* Add default flows */ 1562 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1563 if (default_flow >= 0) { 1564 ret = __mlx4_ib_create_default_rules( 1565 mdev, qp, default_table + default_flow, 1566 mailbox->buf + size); 1567 if (ret < 0) { 1568 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1569 return -EINVAL; 1570 } 1571 size += ret; 1572 } 1573 for (i = 0; i < flow_attr->num_of_specs; i++) { 1574 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1575 mailbox->buf + size); 1576 if (ret < 0) { 1577 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1578 return -EINVAL; 1579 } 1580 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1581 size += ret; 1582 } 1583 1584 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1585 flow_attr->num_of_specs == 1) { 1586 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1587 enum ib_flow_spec_type header_spec = 1588 ((union ib_flow_spec *)(flow_attr + 1))->type; 1589 1590 if (header_spec == IB_FLOW_SPEC_ETH) 1591 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1592 } 1593 1594 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1595 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1596 MLX4_CMD_NATIVE); 1597 if (ret == -ENOMEM) 1598 pr_err("mcg table is full. Fail to register network rule.\n"); 1599 else if (ret == -ENXIO) 1600 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1601 else if (ret) 1602 pr_err("Invalid argument. Fail to register network rule.\n"); 1603 1604 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1605 return ret; 1606 } 1607 1608 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1609 { 1610 int err; 1611 err = mlx4_cmd(dev, reg_id, 0, 0, 1612 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1613 MLX4_CMD_NATIVE); 1614 if (err) 1615 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1616 reg_id); 1617 return err; 1618 } 1619 1620 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1621 u64 *reg_id) 1622 { 1623 void *ib_flow; 1624 union ib_flow_spec *ib_spec; 1625 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1626 int err = 0; 1627 1628 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1629 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1630 return 0; /* do nothing */ 1631 1632 ib_flow = flow_attr + 1; 1633 ib_spec = (union ib_flow_spec *)ib_flow; 1634 1635 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1636 return 0; /* do nothing */ 1637 1638 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1639 flow_attr->port, qp->qp_num, 1640 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1641 reg_id); 1642 return err; 1643 } 1644 1645 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1646 struct ib_flow_attr *flow_attr, 1647 enum mlx4_net_trans_promisc_mode *type) 1648 { 1649 int err = 0; 1650 1651 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1652 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1653 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1654 return -EOPNOTSUPP; 1655 } 1656 1657 if (flow_attr->num_of_specs == 0) { 1658 type[0] = MLX4_FS_MC_SNIFFER; 1659 type[1] = MLX4_FS_UC_SNIFFER; 1660 } else { 1661 union ib_flow_spec *ib_spec; 1662 1663 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1664 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1665 return -EINVAL; 1666 1667 /* if all is zero than MC and UC */ 1668 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1669 type[0] = MLX4_FS_MC_SNIFFER; 1670 type[1] = MLX4_FS_UC_SNIFFER; 1671 } else { 1672 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1673 ib_spec->eth.mask.dst_mac[1], 1674 ib_spec->eth.mask.dst_mac[2], 1675 ib_spec->eth.mask.dst_mac[3], 1676 ib_spec->eth.mask.dst_mac[4], 1677 ib_spec->eth.mask.dst_mac[5]}; 1678 1679 /* Above xor was only on MC bit, non empty mask is valid 1680 * only if this bit is set and rest are zero. 1681 */ 1682 if (!is_zero_ether_addr(&mac[0])) 1683 return -EINVAL; 1684 1685 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1686 type[0] = MLX4_FS_MC_SNIFFER; 1687 else 1688 type[0] = MLX4_FS_UC_SNIFFER; 1689 } 1690 } 1691 1692 return err; 1693 } 1694 1695 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1696 struct ib_flow_attr *flow_attr, 1697 struct ib_udata *udata) 1698 { 1699 int err = 0, i = 0, j = 0; 1700 struct mlx4_ib_flow *mflow; 1701 enum mlx4_net_trans_promisc_mode type[2]; 1702 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1703 int is_bonded = mlx4_is_bonded(dev); 1704 1705 if (!rdma_is_port_valid(qp->device, flow_attr->port)) 1706 return ERR_PTR(-EINVAL); 1707 1708 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1709 return ERR_PTR(-EOPNOTSUPP); 1710 1711 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1712 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1713 return ERR_PTR(-EOPNOTSUPP); 1714 1715 if (udata && 1716 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1717 return ERR_PTR(-EOPNOTSUPP); 1718 1719 memset(type, 0, sizeof(type)); 1720 1721 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1722 if (!mflow) { 1723 err = -ENOMEM; 1724 goto err_free; 1725 } 1726 1727 switch (flow_attr->type) { 1728 case IB_FLOW_ATTR_NORMAL: 1729 /* If dont trap flag (continue match) is set, under specific 1730 * condition traffic be replicated to given qp, 1731 * without stealing it 1732 */ 1733 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1734 err = mlx4_ib_add_dont_trap_rule(dev, 1735 flow_attr, 1736 type); 1737 if (err) 1738 goto err_free; 1739 } else { 1740 type[0] = MLX4_FS_REGULAR; 1741 } 1742 break; 1743 1744 case IB_FLOW_ATTR_ALL_DEFAULT: 1745 type[0] = MLX4_FS_ALL_DEFAULT; 1746 break; 1747 1748 case IB_FLOW_ATTR_MC_DEFAULT: 1749 type[0] = MLX4_FS_MC_DEFAULT; 1750 break; 1751 1752 case IB_FLOW_ATTR_SNIFFER: 1753 type[0] = MLX4_FS_MIRROR_RX_PORT; 1754 type[1] = MLX4_FS_MIRROR_SX_PORT; 1755 break; 1756 1757 default: 1758 err = -EINVAL; 1759 goto err_free; 1760 } 1761 1762 while (i < ARRAY_SIZE(type) && type[i]) { 1763 err = __mlx4_ib_create_flow(qp, flow_attr, MLX4_DOMAIN_UVERBS, 1764 type[i], &mflow->reg_id[i].id); 1765 if (err) 1766 goto err_create_flow; 1767 if (is_bonded) { 1768 /* Application always sees one port so the mirror rule 1769 * must be on port #2 1770 */ 1771 flow_attr->port = 2; 1772 err = __mlx4_ib_create_flow(qp, flow_attr, 1773 MLX4_DOMAIN_UVERBS, type[j], 1774 &mflow->reg_id[j].mirror); 1775 flow_attr->port = 1; 1776 if (err) 1777 goto err_create_flow; 1778 j++; 1779 } 1780 1781 i++; 1782 } 1783 1784 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1785 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1786 &mflow->reg_id[i].id); 1787 if (err) 1788 goto err_create_flow; 1789 1790 if (is_bonded) { 1791 flow_attr->port = 2; 1792 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1793 &mflow->reg_id[j].mirror); 1794 flow_attr->port = 1; 1795 if (err) 1796 goto err_create_flow; 1797 j++; 1798 } 1799 /* function to create mirror rule */ 1800 i++; 1801 } 1802 1803 return &mflow->ibflow; 1804 1805 err_create_flow: 1806 while (i) { 1807 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1808 mflow->reg_id[i].id); 1809 i--; 1810 } 1811 1812 while (j) { 1813 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1814 mflow->reg_id[j].mirror); 1815 j--; 1816 } 1817 err_free: 1818 kfree(mflow); 1819 return ERR_PTR(err); 1820 } 1821 1822 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1823 { 1824 int err, ret = 0; 1825 int i = 0; 1826 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1827 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1828 1829 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1830 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1831 if (err) 1832 ret = err; 1833 if (mflow->reg_id[i].mirror) { 1834 err = __mlx4_ib_destroy_flow(mdev->dev, 1835 mflow->reg_id[i].mirror); 1836 if (err) 1837 ret = err; 1838 } 1839 i++; 1840 } 1841 1842 kfree(mflow); 1843 return ret; 1844 } 1845 1846 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1847 { 1848 int err; 1849 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1850 struct mlx4_dev *dev = mdev->dev; 1851 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1852 struct mlx4_ib_steering *ib_steering = NULL; 1853 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1854 struct mlx4_flow_reg_id reg_id; 1855 1856 if (mdev->dev->caps.steering_mode == 1857 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1858 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1859 if (!ib_steering) 1860 return -ENOMEM; 1861 } 1862 1863 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1864 !!(mqp->flags & 1865 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1866 prot, ®_id.id); 1867 if (err) { 1868 pr_err("multicast attach op failed, err %d\n", err); 1869 goto err_malloc; 1870 } 1871 1872 reg_id.mirror = 0; 1873 if (mlx4_is_bonded(dev)) { 1874 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1875 (mqp->port == 1) ? 2 : 1, 1876 !!(mqp->flags & 1877 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1878 prot, ®_id.mirror); 1879 if (err) 1880 goto err_add; 1881 } 1882 1883 err = add_gid_entry(ibqp, gid); 1884 if (err) 1885 goto err_add; 1886 1887 if (ib_steering) { 1888 memcpy(ib_steering->gid.raw, gid->raw, 16); 1889 ib_steering->reg_id = reg_id; 1890 mutex_lock(&mqp->mutex); 1891 list_add(&ib_steering->list, &mqp->steering_rules); 1892 mutex_unlock(&mqp->mutex); 1893 } 1894 return 0; 1895 1896 err_add: 1897 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1898 prot, reg_id.id); 1899 if (reg_id.mirror) 1900 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1901 prot, reg_id.mirror); 1902 err_malloc: 1903 kfree(ib_steering); 1904 1905 return err; 1906 } 1907 1908 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 1909 { 1910 struct mlx4_ib_gid_entry *ge; 1911 struct mlx4_ib_gid_entry *tmp; 1912 struct mlx4_ib_gid_entry *ret = NULL; 1913 1914 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1915 if (!memcmp(raw, ge->gid.raw, 16)) { 1916 ret = ge; 1917 break; 1918 } 1919 } 1920 1921 return ret; 1922 } 1923 1924 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1925 { 1926 int err; 1927 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1928 struct mlx4_dev *dev = mdev->dev; 1929 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1930 struct net_device *ndev; 1931 struct mlx4_ib_gid_entry *ge; 1932 struct mlx4_flow_reg_id reg_id = {0, 0}; 1933 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1934 1935 if (mdev->dev->caps.steering_mode == 1936 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1937 struct mlx4_ib_steering *ib_steering; 1938 1939 mutex_lock(&mqp->mutex); 1940 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 1941 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 1942 list_del(&ib_steering->list); 1943 break; 1944 } 1945 } 1946 mutex_unlock(&mqp->mutex); 1947 if (&ib_steering->list == &mqp->steering_rules) { 1948 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 1949 return -EINVAL; 1950 } 1951 reg_id = ib_steering->reg_id; 1952 kfree(ib_steering); 1953 } 1954 1955 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1956 prot, reg_id.id); 1957 if (err) 1958 return err; 1959 1960 if (mlx4_is_bonded(dev)) { 1961 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1962 prot, reg_id.mirror); 1963 if (err) 1964 return err; 1965 } 1966 1967 mutex_lock(&mqp->mutex); 1968 ge = find_gid_entry(mqp, gid->raw); 1969 if (ge) { 1970 spin_lock_bh(&mdev->iboe.lock); 1971 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 1972 if (ndev) 1973 dev_hold(ndev); 1974 spin_unlock_bh(&mdev->iboe.lock); 1975 if (ndev) 1976 dev_put(ndev); 1977 list_del(&ge->list); 1978 kfree(ge); 1979 } else 1980 pr_warn("could not find mgid entry\n"); 1981 1982 mutex_unlock(&mqp->mutex); 1983 1984 return 0; 1985 } 1986 1987 static int init_node_data(struct mlx4_ib_dev *dev) 1988 { 1989 struct ib_smp *in_mad = NULL; 1990 struct ib_smp *out_mad = NULL; 1991 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 1992 int err = -ENOMEM; 1993 1994 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 1995 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 1996 if (!in_mad || !out_mad) 1997 goto out; 1998 1999 init_query_mad(in_mad); 2000 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2001 if (mlx4_is_master(dev->dev)) 2002 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2003 2004 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2005 if (err) 2006 goto out; 2007 2008 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2009 2010 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2011 2012 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2013 if (err) 2014 goto out; 2015 2016 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2017 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2018 2019 out: 2020 kfree(in_mad); 2021 kfree(out_mad); 2022 return err; 2023 } 2024 2025 static ssize_t hca_type_show(struct device *device, 2026 struct device_attribute *attr, char *buf) 2027 { 2028 struct mlx4_ib_dev *dev = 2029 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2030 2031 return sysfs_emit(buf, "MT%d\n", dev->dev->persist->pdev->device); 2032 } 2033 static DEVICE_ATTR_RO(hca_type); 2034 2035 static ssize_t hw_rev_show(struct device *device, 2036 struct device_attribute *attr, char *buf) 2037 { 2038 struct mlx4_ib_dev *dev = 2039 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2040 2041 return sysfs_emit(buf, "%x\n", dev->dev->rev_id); 2042 } 2043 static DEVICE_ATTR_RO(hw_rev); 2044 2045 static ssize_t board_id_show(struct device *device, 2046 struct device_attribute *attr, char *buf) 2047 { 2048 struct mlx4_ib_dev *dev = 2049 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2050 2051 return sysfs_emit(buf, "%.*s\n", MLX4_BOARD_ID_LEN, dev->dev->board_id); 2052 } 2053 static DEVICE_ATTR_RO(board_id); 2054 2055 static struct attribute *mlx4_class_attributes[] = { 2056 &dev_attr_hw_rev.attr, 2057 &dev_attr_hca_type.attr, 2058 &dev_attr_board_id.attr, 2059 NULL 2060 }; 2061 2062 static const struct attribute_group mlx4_attr_group = { 2063 .attrs = mlx4_class_attributes, 2064 }; 2065 2066 struct diag_counter { 2067 const char *name; 2068 u32 offset; 2069 }; 2070 2071 #define DIAG_COUNTER(_name, _offset) \ 2072 { .name = #_name, .offset = _offset } 2073 2074 static const struct diag_counter diag_basic[] = { 2075 DIAG_COUNTER(rq_num_lle, 0x00), 2076 DIAG_COUNTER(sq_num_lle, 0x04), 2077 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2078 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2079 DIAG_COUNTER(rq_num_lpe, 0x18), 2080 DIAG_COUNTER(sq_num_lpe, 0x1C), 2081 DIAG_COUNTER(rq_num_wrfe, 0x20), 2082 DIAG_COUNTER(sq_num_wrfe, 0x24), 2083 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2084 DIAG_COUNTER(sq_num_bre, 0x34), 2085 DIAG_COUNTER(sq_num_rire, 0x44), 2086 DIAG_COUNTER(rq_num_rire, 0x48), 2087 DIAG_COUNTER(sq_num_rae, 0x4C), 2088 DIAG_COUNTER(rq_num_rae, 0x50), 2089 DIAG_COUNTER(sq_num_roe, 0x54), 2090 DIAG_COUNTER(sq_num_tree, 0x5C), 2091 DIAG_COUNTER(sq_num_rree, 0x64), 2092 DIAG_COUNTER(rq_num_rnr, 0x68), 2093 DIAG_COUNTER(sq_num_rnr, 0x6C), 2094 DIAG_COUNTER(rq_num_oos, 0x100), 2095 DIAG_COUNTER(sq_num_oos, 0x104), 2096 }; 2097 2098 static const struct diag_counter diag_ext[] = { 2099 DIAG_COUNTER(rq_num_dup, 0x130), 2100 DIAG_COUNTER(sq_num_to, 0x134), 2101 }; 2102 2103 static const struct diag_counter diag_device_only[] = { 2104 DIAG_COUNTER(num_cqovf, 0x1A0), 2105 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2106 }; 2107 2108 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2109 u32 port_num) 2110 { 2111 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2112 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2113 2114 if (!diag[!!port_num].name) 2115 return NULL; 2116 2117 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2118 diag[!!port_num].num_counters, 2119 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2120 } 2121 2122 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2123 struct rdma_hw_stats *stats, 2124 u32 port, int index) 2125 { 2126 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2127 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2128 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2129 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2130 int ret; 2131 int i; 2132 2133 ret = mlx4_query_diag_counters(dev->dev, 2134 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2135 diag[!!port].offset, hw_value, 2136 diag[!!port].num_counters, port); 2137 2138 if (ret) 2139 return ret; 2140 2141 for (i = 0; i < diag[!!port].num_counters; i++) 2142 stats->value[i] = hw_value[i]; 2143 2144 return diag[!!port].num_counters; 2145 } 2146 2147 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2148 const char ***name, 2149 u32 **offset, 2150 u32 *num, 2151 bool port) 2152 { 2153 u32 num_counters; 2154 2155 num_counters = ARRAY_SIZE(diag_basic); 2156 2157 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2158 num_counters += ARRAY_SIZE(diag_ext); 2159 2160 if (!port) 2161 num_counters += ARRAY_SIZE(diag_device_only); 2162 2163 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2164 if (!*name) 2165 return -ENOMEM; 2166 2167 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2168 if (!*offset) 2169 goto err_name; 2170 2171 *num = num_counters; 2172 2173 return 0; 2174 2175 err_name: 2176 kfree(*name); 2177 return -ENOMEM; 2178 } 2179 2180 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2181 const char **name, 2182 u32 *offset, 2183 bool port) 2184 { 2185 int i; 2186 int j; 2187 2188 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2189 name[i] = diag_basic[i].name; 2190 offset[i] = diag_basic[i].offset; 2191 } 2192 2193 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2194 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2195 name[j] = diag_ext[i].name; 2196 offset[j] = diag_ext[i].offset; 2197 } 2198 } 2199 2200 if (!port) { 2201 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2202 name[j] = diag_device_only[i].name; 2203 offset[j] = diag_device_only[i].offset; 2204 } 2205 } 2206 } 2207 2208 static const struct ib_device_ops mlx4_ib_hw_stats_ops = { 2209 .alloc_hw_stats = mlx4_ib_alloc_hw_stats, 2210 .get_hw_stats = mlx4_ib_get_hw_stats, 2211 }; 2212 2213 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2214 { 2215 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2216 int i; 2217 int ret; 2218 bool per_port = !!(ibdev->dev->caps.flags2 & 2219 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2220 2221 if (mlx4_is_slave(ibdev->dev)) 2222 return 0; 2223 2224 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2225 /* i == 1 means we are building port counters */ 2226 if (i && !per_port) 2227 continue; 2228 2229 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2230 &diag[i].offset, 2231 &diag[i].num_counters, i); 2232 if (ret) 2233 goto err_alloc; 2234 2235 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2236 diag[i].offset, i); 2237 } 2238 2239 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops); 2240 2241 return 0; 2242 2243 err_alloc: 2244 if (i) { 2245 kfree(diag[i - 1].name); 2246 kfree(diag[i - 1].offset); 2247 } 2248 2249 return ret; 2250 } 2251 2252 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2253 { 2254 int i; 2255 2256 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2257 kfree(ibdev->diag_counters[i].offset); 2258 kfree(ibdev->diag_counters[i].name); 2259 } 2260 } 2261 2262 #define MLX4_IB_INVALID_MAC ((u64)-1) 2263 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2264 struct net_device *dev, 2265 int port) 2266 { 2267 u64 new_smac = 0; 2268 u64 release_mac = MLX4_IB_INVALID_MAC; 2269 struct mlx4_ib_qp *qp; 2270 2271 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2272 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2273 2274 /* no need for update QP1 and mac registration in non-SRIOV */ 2275 if (!mlx4_is_mfunc(ibdev->dev)) 2276 return; 2277 2278 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2279 qp = ibdev->qp1_proxy[port - 1]; 2280 if (qp) { 2281 int new_smac_index; 2282 u64 old_smac; 2283 struct mlx4_update_qp_params update_params; 2284 2285 mutex_lock(&qp->mutex); 2286 old_smac = qp->pri.smac; 2287 if (new_smac == old_smac) 2288 goto unlock; 2289 2290 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2291 2292 if (new_smac_index < 0) 2293 goto unlock; 2294 2295 update_params.smac_index = new_smac_index; 2296 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2297 &update_params)) { 2298 release_mac = new_smac; 2299 goto unlock; 2300 } 2301 /* if old port was zero, no mac was yet registered for this QP */ 2302 if (qp->pri.smac_port) 2303 release_mac = old_smac; 2304 qp->pri.smac = new_smac; 2305 qp->pri.smac_port = port; 2306 qp->pri.smac_index = new_smac_index; 2307 } 2308 2309 unlock: 2310 if (release_mac != MLX4_IB_INVALID_MAC) 2311 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2312 if (qp) 2313 mutex_unlock(&qp->mutex); 2314 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2315 } 2316 2317 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2318 struct net_device *dev, 2319 unsigned long event) 2320 2321 { 2322 struct mlx4_ib_iboe *iboe; 2323 int update_qps_port = -1; 2324 int port; 2325 2326 ASSERT_RTNL(); 2327 2328 iboe = &ibdev->iboe; 2329 2330 spin_lock_bh(&iboe->lock); 2331 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2332 2333 iboe->netdevs[port - 1] = 2334 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2335 2336 if (dev == iboe->netdevs[port - 1] && 2337 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2338 event == NETDEV_UP || event == NETDEV_CHANGE)) 2339 update_qps_port = port; 2340 2341 if (dev == iboe->netdevs[port - 1] && 2342 (event == NETDEV_UP || event == NETDEV_DOWN)) { 2343 enum ib_port_state port_state; 2344 struct ib_event ibev = { }; 2345 2346 if (ib_get_cached_port_state(&ibdev->ib_dev, port, 2347 &port_state)) 2348 continue; 2349 2350 if (event == NETDEV_UP && 2351 (port_state != IB_PORT_ACTIVE || 2352 iboe->last_port_state[port - 1] != IB_PORT_DOWN)) 2353 continue; 2354 if (event == NETDEV_DOWN && 2355 (port_state != IB_PORT_DOWN || 2356 iboe->last_port_state[port - 1] != IB_PORT_ACTIVE)) 2357 continue; 2358 iboe->last_port_state[port - 1] = port_state; 2359 2360 ibev.device = &ibdev->ib_dev; 2361 ibev.element.port_num = port; 2362 ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE : 2363 IB_EVENT_PORT_ERR; 2364 ib_dispatch_event(&ibev); 2365 } 2366 2367 } 2368 spin_unlock_bh(&iboe->lock); 2369 2370 if (update_qps_port > 0) 2371 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2372 } 2373 2374 static int mlx4_ib_netdev_event(struct notifier_block *this, 2375 unsigned long event, void *ptr) 2376 { 2377 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2378 struct mlx4_ib_dev *ibdev; 2379 2380 if (!net_eq(dev_net(dev), &init_net)) 2381 return NOTIFY_DONE; 2382 2383 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2384 mlx4_ib_scan_netdevs(ibdev, dev, event); 2385 2386 return NOTIFY_DONE; 2387 } 2388 2389 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2390 { 2391 int port; 2392 int slave; 2393 int i; 2394 2395 if (mlx4_is_master(ibdev->dev)) { 2396 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2397 ++slave) { 2398 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2399 for (i = 0; 2400 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2401 ++i) { 2402 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2403 /* master has the identity virt2phys pkey mapping */ 2404 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2405 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2406 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2407 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2408 } 2409 } 2410 } 2411 /* initialize pkey cache */ 2412 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2413 for (i = 0; 2414 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2415 ++i) 2416 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2417 (i) ? 0 : 0xFFFF; 2418 } 2419 } 2420 } 2421 2422 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2423 { 2424 int i, j, eq = 0, total_eqs = 0; 2425 2426 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2427 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2428 if (!ibdev->eq_table) 2429 return; 2430 2431 for (i = 1; i <= dev->caps.num_ports; i++) { 2432 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2433 j++, total_eqs++) { 2434 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2435 continue; 2436 ibdev->eq_table[eq] = total_eqs; 2437 if (!mlx4_assign_eq(dev, i, 2438 &ibdev->eq_table[eq])) 2439 eq++; 2440 else 2441 ibdev->eq_table[eq] = -1; 2442 } 2443 } 2444 2445 for (i = eq; i < dev->caps.num_comp_vectors; 2446 ibdev->eq_table[i++] = -1) 2447 ; 2448 2449 /* Advertise the new number of EQs to clients */ 2450 ibdev->ib_dev.num_comp_vectors = eq; 2451 } 2452 2453 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2454 { 2455 int i; 2456 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2457 2458 /* no eqs were allocated */ 2459 if (!ibdev->eq_table) 2460 return; 2461 2462 /* Reset the advertised EQ number */ 2463 ibdev->ib_dev.num_comp_vectors = 0; 2464 2465 for (i = 0; i < total_eqs; i++) 2466 mlx4_release_eq(dev, ibdev->eq_table[i]); 2467 2468 kfree(ibdev->eq_table); 2469 ibdev->eq_table = NULL; 2470 } 2471 2472 static int mlx4_port_immutable(struct ib_device *ibdev, u32 port_num, 2473 struct ib_port_immutable *immutable) 2474 { 2475 struct ib_port_attr attr; 2476 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2477 int err; 2478 2479 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2480 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2481 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2482 } else { 2483 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2484 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2485 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2486 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2487 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2488 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2489 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2490 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2491 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2492 } 2493 2494 err = ib_query_port(ibdev, port_num, &attr); 2495 if (err) 2496 return err; 2497 2498 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2499 immutable->gid_tbl_len = attr.gid_tbl_len; 2500 2501 return 0; 2502 } 2503 2504 static void get_fw_ver_str(struct ib_device *device, char *str) 2505 { 2506 struct mlx4_ib_dev *dev = 2507 container_of(device, struct mlx4_ib_dev, ib_dev); 2508 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2509 (int) (dev->dev->caps.fw_ver >> 32), 2510 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2511 (int) dev->dev->caps.fw_ver & 0xffff); 2512 } 2513 2514 static const struct ib_device_ops mlx4_ib_dev_ops = { 2515 .owner = THIS_MODULE, 2516 .driver_id = RDMA_DRIVER_MLX4, 2517 .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION, 2518 2519 .add_gid = mlx4_ib_add_gid, 2520 .alloc_mr = mlx4_ib_alloc_mr, 2521 .alloc_pd = mlx4_ib_alloc_pd, 2522 .alloc_ucontext = mlx4_ib_alloc_ucontext, 2523 .attach_mcast = mlx4_ib_mcg_attach, 2524 .create_ah = mlx4_ib_create_ah, 2525 .create_cq = mlx4_ib_create_cq, 2526 .create_qp = mlx4_ib_create_qp, 2527 .create_srq = mlx4_ib_create_srq, 2528 .dealloc_pd = mlx4_ib_dealloc_pd, 2529 .dealloc_ucontext = mlx4_ib_dealloc_ucontext, 2530 .del_gid = mlx4_ib_del_gid, 2531 .dereg_mr = mlx4_ib_dereg_mr, 2532 .destroy_ah = mlx4_ib_destroy_ah, 2533 .destroy_cq = mlx4_ib_destroy_cq, 2534 .destroy_qp = mlx4_ib_destroy_qp, 2535 .destroy_srq = mlx4_ib_destroy_srq, 2536 .detach_mcast = mlx4_ib_mcg_detach, 2537 .disassociate_ucontext = mlx4_ib_disassociate_ucontext, 2538 .drain_rq = mlx4_ib_drain_rq, 2539 .drain_sq = mlx4_ib_drain_sq, 2540 .get_dev_fw_str = get_fw_ver_str, 2541 .get_dma_mr = mlx4_ib_get_dma_mr, 2542 .get_link_layer = mlx4_ib_port_link_layer, 2543 .get_netdev = mlx4_ib_get_netdev, 2544 .get_port_immutable = mlx4_port_immutable, 2545 .map_mr_sg = mlx4_ib_map_mr_sg, 2546 .mmap = mlx4_ib_mmap, 2547 .modify_cq = mlx4_ib_modify_cq, 2548 .modify_device = mlx4_ib_modify_device, 2549 .modify_port = mlx4_ib_modify_port, 2550 .modify_qp = mlx4_ib_modify_qp, 2551 .modify_srq = mlx4_ib_modify_srq, 2552 .poll_cq = mlx4_ib_poll_cq, 2553 .post_recv = mlx4_ib_post_recv, 2554 .post_send = mlx4_ib_post_send, 2555 .post_srq_recv = mlx4_ib_post_srq_recv, 2556 .process_mad = mlx4_ib_process_mad, 2557 .query_ah = mlx4_ib_query_ah, 2558 .query_device = mlx4_ib_query_device, 2559 .query_gid = mlx4_ib_query_gid, 2560 .query_pkey = mlx4_ib_query_pkey, 2561 .query_port = mlx4_ib_query_port, 2562 .query_qp = mlx4_ib_query_qp, 2563 .query_srq = mlx4_ib_query_srq, 2564 .reg_user_mr = mlx4_ib_reg_user_mr, 2565 .req_notify_cq = mlx4_ib_arm_cq, 2566 .rereg_user_mr = mlx4_ib_rereg_user_mr, 2567 .resize_cq = mlx4_ib_resize_cq, 2568 2569 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah), 2570 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq), 2571 INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd), 2572 INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq), 2573 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext), 2574 }; 2575 2576 static const struct ib_device_ops mlx4_ib_dev_wq_ops = { 2577 .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table, 2578 .create_wq = mlx4_ib_create_wq, 2579 .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table, 2580 .destroy_wq = mlx4_ib_destroy_wq, 2581 .modify_wq = mlx4_ib_modify_wq, 2582 2583 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx4_ib_rwq_ind_table, 2584 ib_rwq_ind_tbl), 2585 }; 2586 2587 static const struct ib_device_ops mlx4_ib_dev_mw_ops = { 2588 .alloc_mw = mlx4_ib_alloc_mw, 2589 .dealloc_mw = mlx4_ib_dealloc_mw, 2590 2591 INIT_RDMA_OBJ_SIZE(ib_mw, mlx4_ib_mw, ibmw), 2592 }; 2593 2594 static const struct ib_device_ops mlx4_ib_dev_xrc_ops = { 2595 .alloc_xrcd = mlx4_ib_alloc_xrcd, 2596 .dealloc_xrcd = mlx4_ib_dealloc_xrcd, 2597 2598 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx4_ib_xrcd, ibxrcd), 2599 }; 2600 2601 static const struct ib_device_ops mlx4_ib_dev_fs_ops = { 2602 .create_flow = mlx4_ib_create_flow, 2603 .destroy_flow = mlx4_ib_destroy_flow, 2604 }; 2605 2606 static void *mlx4_ib_add(struct mlx4_dev *dev) 2607 { 2608 struct mlx4_ib_dev *ibdev; 2609 int num_ports = 0; 2610 int i, j; 2611 int err; 2612 struct mlx4_ib_iboe *iboe; 2613 int ib_num_ports = 0; 2614 int num_req_counters; 2615 int allocated; 2616 u32 counter_index; 2617 struct counter_index *new_counter_index = NULL; 2618 2619 pr_info_once("%s", mlx4_ib_version); 2620 2621 num_ports = 0; 2622 mlx4_foreach_ib_transport_port(i, dev) 2623 num_ports++; 2624 2625 /* No point in registering a device with no ports... */ 2626 if (num_ports == 0) 2627 return NULL; 2628 2629 ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev); 2630 if (!ibdev) { 2631 dev_err(&dev->persist->pdev->dev, 2632 "Device struct alloc failed\n"); 2633 return NULL; 2634 } 2635 2636 iboe = &ibdev->iboe; 2637 2638 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2639 goto err_dealloc; 2640 2641 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2642 goto err_pd; 2643 2644 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2645 PAGE_SIZE); 2646 if (!ibdev->uar_map) 2647 goto err_uar; 2648 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2649 2650 ibdev->dev = dev; 2651 ibdev->bond_next_port = 0; 2652 2653 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2654 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2655 ibdev->num_ports = num_ports; 2656 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2657 1 : ibdev->num_ports; 2658 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2659 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2660 2661 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops); 2662 2663 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2664 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2665 IB_LINK_LAYER_ETHERNET) || 2666 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2667 IB_LINK_LAYER_ETHERNET))) 2668 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops); 2669 2670 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2671 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2672 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops); 2673 2674 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2675 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops); 2676 } 2677 2678 if (check_flow_steering_support(dev)) { 2679 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2680 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops); 2681 } 2682 2683 if (!dev->caps.userspace_caps) 2684 ibdev->ib_dev.ops.uverbs_abi_ver = 2685 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2686 2687 mlx4_ib_alloc_eqs(dev, ibdev); 2688 2689 spin_lock_init(&iboe->lock); 2690 2691 if (init_node_data(ibdev)) 2692 goto err_map; 2693 mlx4_init_sl2vl_tbl(ibdev); 2694 2695 for (i = 0; i < ibdev->num_ports; ++i) { 2696 mutex_init(&ibdev->counters_table[i].mutex); 2697 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2698 iboe->last_port_state[i] = IB_PORT_DOWN; 2699 } 2700 2701 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2702 for (i = 0; i < num_req_counters; ++i) { 2703 mutex_init(&ibdev->qp1_proxy_lock[i]); 2704 allocated = 0; 2705 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2706 IB_LINK_LAYER_ETHERNET) { 2707 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2708 MLX4_RES_USAGE_DRIVER); 2709 /* if failed to allocate a new counter, use default */ 2710 if (err) 2711 counter_index = 2712 mlx4_get_default_counter_index(dev, 2713 i + 1); 2714 else 2715 allocated = 1; 2716 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2717 counter_index = mlx4_get_default_counter_index(dev, 2718 i + 1); 2719 } 2720 new_counter_index = kmalloc(sizeof(*new_counter_index), 2721 GFP_KERNEL); 2722 if (!new_counter_index) { 2723 if (allocated) 2724 mlx4_counter_free(ibdev->dev, counter_index); 2725 goto err_counter; 2726 } 2727 new_counter_index->index = counter_index; 2728 new_counter_index->allocated = allocated; 2729 list_add_tail(&new_counter_index->list, 2730 &ibdev->counters_table[i].counters_list); 2731 ibdev->counters_table[i].default_counter = counter_index; 2732 pr_info("counter index %d for port %d allocated %d\n", 2733 counter_index, i + 1, allocated); 2734 } 2735 if (mlx4_is_bonded(dev)) 2736 for (i = 1; i < ibdev->num_ports ; ++i) { 2737 new_counter_index = 2738 kmalloc(sizeof(struct counter_index), 2739 GFP_KERNEL); 2740 if (!new_counter_index) 2741 goto err_counter; 2742 new_counter_index->index = counter_index; 2743 new_counter_index->allocated = 0; 2744 list_add_tail(&new_counter_index->list, 2745 &ibdev->counters_table[i].counters_list); 2746 ibdev->counters_table[i].default_counter = 2747 counter_index; 2748 } 2749 2750 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2751 ib_num_ports++; 2752 2753 spin_lock_init(&ibdev->sm_lock); 2754 mutex_init(&ibdev->cap_mask_mutex); 2755 INIT_LIST_HEAD(&ibdev->qp_list); 2756 spin_lock_init(&ibdev->reset_flow_resource_lock); 2757 2758 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2759 ib_num_ports) { 2760 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2761 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2762 MLX4_IB_UC_STEER_QPN_ALIGN, 2763 &ibdev->steer_qpn_base, 0, 2764 MLX4_RES_USAGE_DRIVER); 2765 if (err) 2766 goto err_counter; 2767 2768 ibdev->ib_uc_qpns_bitmap = 2769 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2770 sizeof(long), 2771 GFP_KERNEL); 2772 if (!ibdev->ib_uc_qpns_bitmap) 2773 goto err_steer_qp_release; 2774 2775 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2776 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2777 ibdev->steer_qpn_count); 2778 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2779 dev, ibdev->steer_qpn_base, 2780 ibdev->steer_qpn_base + 2781 ibdev->steer_qpn_count - 1); 2782 if (err) 2783 goto err_steer_free_bitmap; 2784 } else { 2785 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2786 ibdev->steer_qpn_count); 2787 } 2788 } 2789 2790 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2791 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2792 2793 if (mlx4_ib_alloc_diag_counters(ibdev)) 2794 goto err_steer_free_bitmap; 2795 2796 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group); 2797 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d", 2798 &dev->persist->pdev->dev)) 2799 goto err_diag_counters; 2800 2801 if (mlx4_ib_mad_init(ibdev)) 2802 goto err_reg; 2803 2804 if (mlx4_ib_init_sriov(ibdev)) 2805 goto err_mad; 2806 2807 if (!iboe->nb.notifier_call) { 2808 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2809 err = register_netdevice_notifier(&iboe->nb); 2810 if (err) { 2811 iboe->nb.notifier_call = NULL; 2812 goto err_notif; 2813 } 2814 } 2815 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2816 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2817 if (err) 2818 goto err_notif; 2819 } 2820 2821 ibdev->ib_active = true; 2822 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2823 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2824 &ibdev->ib_dev); 2825 2826 if (mlx4_is_mfunc(ibdev->dev)) 2827 init_pkeys(ibdev); 2828 2829 /* create paravirt contexts for any VFs which are active */ 2830 if (mlx4_is_master(ibdev->dev)) { 2831 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2832 if (j == mlx4_master_func_num(ibdev->dev)) 2833 continue; 2834 if (mlx4_is_slave_active(ibdev->dev, j)) 2835 do_slave_init(ibdev, j, 1); 2836 } 2837 } 2838 return ibdev; 2839 2840 err_notif: 2841 if (ibdev->iboe.nb.notifier_call) { 2842 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2843 pr_warn("failure unregistering notifier\n"); 2844 ibdev->iboe.nb.notifier_call = NULL; 2845 } 2846 flush_workqueue(wq); 2847 2848 mlx4_ib_close_sriov(ibdev); 2849 2850 err_mad: 2851 mlx4_ib_mad_cleanup(ibdev); 2852 2853 err_reg: 2854 ib_unregister_device(&ibdev->ib_dev); 2855 2856 err_diag_counters: 2857 mlx4_ib_diag_cleanup(ibdev); 2858 2859 err_steer_free_bitmap: 2860 kfree(ibdev->ib_uc_qpns_bitmap); 2861 2862 err_steer_qp_release: 2863 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2864 ibdev->steer_qpn_count); 2865 err_counter: 2866 for (i = 0; i < ibdev->num_ports; ++i) 2867 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2868 2869 err_map: 2870 mlx4_ib_free_eqs(dev, ibdev); 2871 iounmap(ibdev->uar_map); 2872 2873 err_uar: 2874 mlx4_uar_free(dev, &ibdev->priv_uar); 2875 2876 err_pd: 2877 mlx4_pd_free(dev, ibdev->priv_pdn); 2878 2879 err_dealloc: 2880 ib_dealloc_device(&ibdev->ib_dev); 2881 2882 return NULL; 2883 } 2884 2885 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2886 { 2887 int offset; 2888 2889 WARN_ON(!dev->ib_uc_qpns_bitmap); 2890 2891 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2892 dev->steer_qpn_count, 2893 get_count_order(count)); 2894 if (offset < 0) 2895 return offset; 2896 2897 *qpn = dev->steer_qpn_base + offset; 2898 return 0; 2899 } 2900 2901 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 2902 { 2903 if (!qpn || 2904 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 2905 return; 2906 2907 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 2908 qpn, dev->steer_qpn_base)) 2909 /* not supposed to be here */ 2910 return; 2911 2912 bitmap_release_region(dev->ib_uc_qpns_bitmap, 2913 qpn - dev->steer_qpn_base, 2914 get_count_order(count)); 2915 } 2916 2917 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 2918 int is_attach) 2919 { 2920 int err; 2921 size_t flow_size; 2922 struct ib_flow_attr *flow = NULL; 2923 struct ib_flow_spec_ib *ib_spec; 2924 2925 if (is_attach) { 2926 flow_size = sizeof(struct ib_flow_attr) + 2927 sizeof(struct ib_flow_spec_ib); 2928 flow = kzalloc(flow_size, GFP_KERNEL); 2929 if (!flow) 2930 return -ENOMEM; 2931 flow->port = mqp->port; 2932 flow->num_of_specs = 1; 2933 flow->size = flow_size; 2934 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 2935 ib_spec->type = IB_FLOW_SPEC_IB; 2936 ib_spec->size = sizeof(struct ib_flow_spec_ib); 2937 /* Add an empty rule for IB L2 */ 2938 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 2939 2940 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, MLX4_DOMAIN_NIC, 2941 MLX4_FS_REGULAR, &mqp->reg_id); 2942 } else { 2943 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 2944 } 2945 kfree(flow); 2946 return err; 2947 } 2948 2949 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 2950 { 2951 struct mlx4_ib_dev *ibdev = ibdev_ptr; 2952 int p; 2953 int i; 2954 2955 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2956 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 2957 ibdev->ib_active = false; 2958 flush_workqueue(wq); 2959 2960 if (ibdev->iboe.nb.notifier_call) { 2961 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2962 pr_warn("failure unregistering notifier\n"); 2963 ibdev->iboe.nb.notifier_call = NULL; 2964 } 2965 2966 mlx4_ib_close_sriov(ibdev); 2967 mlx4_ib_mad_cleanup(ibdev); 2968 ib_unregister_device(&ibdev->ib_dev); 2969 mlx4_ib_diag_cleanup(ibdev); 2970 2971 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2972 ibdev->steer_qpn_count); 2973 kfree(ibdev->ib_uc_qpns_bitmap); 2974 2975 iounmap(ibdev->uar_map); 2976 for (p = 0; p < ibdev->num_ports; ++p) 2977 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 2978 2979 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 2980 mlx4_CLOSE_PORT(dev, p); 2981 2982 mlx4_ib_free_eqs(dev, ibdev); 2983 2984 mlx4_uar_free(dev, &ibdev->priv_uar); 2985 mlx4_pd_free(dev, ibdev->priv_pdn); 2986 ib_dealloc_device(&ibdev->ib_dev); 2987 } 2988 2989 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 2990 { 2991 struct mlx4_ib_demux_work **dm = NULL; 2992 struct mlx4_dev *dev = ibdev->dev; 2993 int i; 2994 unsigned long flags; 2995 struct mlx4_active_ports actv_ports; 2996 unsigned int ports; 2997 unsigned int first_port; 2998 2999 if (!mlx4_is_master(dev)) 3000 return; 3001 3002 actv_ports = mlx4_get_active_ports(dev, slave); 3003 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3004 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3005 3006 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3007 if (!dm) 3008 return; 3009 3010 for (i = 0; i < ports; i++) { 3011 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3012 if (!dm[i]) { 3013 while (--i >= 0) 3014 kfree(dm[i]); 3015 goto out; 3016 } 3017 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3018 dm[i]->port = first_port + i + 1; 3019 dm[i]->slave = slave; 3020 dm[i]->do_init = do_init; 3021 dm[i]->dev = ibdev; 3022 } 3023 /* initialize or tear down tunnel QPs for the slave */ 3024 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3025 if (!ibdev->sriov.is_going_down) { 3026 for (i = 0; i < ports; i++) 3027 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3028 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3029 } else { 3030 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3031 for (i = 0; i < ports; i++) 3032 kfree(dm[i]); 3033 } 3034 out: 3035 kfree(dm); 3036 return; 3037 } 3038 3039 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3040 { 3041 struct mlx4_ib_qp *mqp; 3042 unsigned long flags_qp; 3043 unsigned long flags_cq; 3044 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3045 struct list_head cq_notify_list; 3046 struct mlx4_cq *mcq; 3047 unsigned long flags; 3048 3049 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3050 INIT_LIST_HEAD(&cq_notify_list); 3051 3052 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3053 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3054 3055 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3056 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3057 if (mqp->sq.tail != mqp->sq.head) { 3058 send_mcq = to_mcq(mqp->ibqp.send_cq); 3059 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3060 if (send_mcq->mcq.comp && 3061 mqp->ibqp.send_cq->comp_handler) { 3062 if (!send_mcq->mcq.reset_notify_added) { 3063 send_mcq->mcq.reset_notify_added = 1; 3064 list_add_tail(&send_mcq->mcq.reset_notify, 3065 &cq_notify_list); 3066 } 3067 } 3068 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3069 } 3070 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3071 /* Now, handle the QP's receive queue */ 3072 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3073 /* no handling is needed for SRQ */ 3074 if (!mqp->ibqp.srq) { 3075 if (mqp->rq.tail != mqp->rq.head) { 3076 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3077 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3078 if (recv_mcq->mcq.comp && 3079 mqp->ibqp.recv_cq->comp_handler) { 3080 if (!recv_mcq->mcq.reset_notify_added) { 3081 recv_mcq->mcq.reset_notify_added = 1; 3082 list_add_tail(&recv_mcq->mcq.reset_notify, 3083 &cq_notify_list); 3084 } 3085 } 3086 spin_unlock_irqrestore(&recv_mcq->lock, 3087 flags_cq); 3088 } 3089 } 3090 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3091 } 3092 3093 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3094 mcq->comp(mcq); 3095 } 3096 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3097 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3098 } 3099 3100 static void handle_bonded_port_state_event(struct work_struct *work) 3101 { 3102 struct ib_event_work *ew = 3103 container_of(work, struct ib_event_work, work); 3104 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3105 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3106 int i; 3107 struct ib_event ibev; 3108 3109 kfree(ew); 3110 spin_lock_bh(&ibdev->iboe.lock); 3111 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3112 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3113 enum ib_port_state curr_port_state; 3114 3115 if (!curr_netdev) 3116 continue; 3117 3118 curr_port_state = 3119 (netif_running(curr_netdev) && 3120 netif_carrier_ok(curr_netdev)) ? 3121 IB_PORT_ACTIVE : IB_PORT_DOWN; 3122 3123 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3124 curr_port_state : IB_PORT_ACTIVE; 3125 } 3126 spin_unlock_bh(&ibdev->iboe.lock); 3127 3128 ibev.device = &ibdev->ib_dev; 3129 ibev.element.port_num = 1; 3130 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3131 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3132 3133 ib_dispatch_event(&ibev); 3134 } 3135 3136 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3137 { 3138 u64 sl2vl; 3139 int err; 3140 3141 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3142 if (err) { 3143 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3144 port, err); 3145 sl2vl = 0; 3146 } 3147 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3148 } 3149 3150 static void ib_sl2vl_update_work(struct work_struct *work) 3151 { 3152 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3153 struct mlx4_ib_dev *mdev = ew->ib_dev; 3154 int port = ew->port; 3155 3156 mlx4_ib_sl2vl_update(mdev, port); 3157 3158 kfree(ew); 3159 } 3160 3161 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3162 int port) 3163 { 3164 struct ib_event_work *ew; 3165 3166 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3167 if (ew) { 3168 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3169 ew->port = port; 3170 ew->ib_dev = ibdev; 3171 queue_work(wq, &ew->work); 3172 } 3173 } 3174 3175 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3176 enum mlx4_dev_event event, unsigned long param) 3177 { 3178 struct ib_event ibev; 3179 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3180 struct mlx4_eqe *eqe = NULL; 3181 struct ib_event_work *ew; 3182 int p = 0; 3183 3184 if (mlx4_is_bonded(dev) && 3185 ((event == MLX4_DEV_EVENT_PORT_UP) || 3186 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3187 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3188 if (!ew) 3189 return; 3190 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3191 ew->ib_dev = ibdev; 3192 queue_work(wq, &ew->work); 3193 return; 3194 } 3195 3196 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3197 eqe = (struct mlx4_eqe *)param; 3198 else 3199 p = (int) param; 3200 3201 switch (event) { 3202 case MLX4_DEV_EVENT_PORT_UP: 3203 if (p > ibdev->num_ports) 3204 return; 3205 if (!mlx4_is_slave(dev) && 3206 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3207 IB_LINK_LAYER_INFINIBAND) { 3208 if (mlx4_is_master(dev)) 3209 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3210 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3211 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3212 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3213 } 3214 ibev.event = IB_EVENT_PORT_ACTIVE; 3215 break; 3216 3217 case MLX4_DEV_EVENT_PORT_DOWN: 3218 if (p > ibdev->num_ports) 3219 return; 3220 ibev.event = IB_EVENT_PORT_ERR; 3221 break; 3222 3223 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3224 ibdev->ib_active = false; 3225 ibev.event = IB_EVENT_DEVICE_FATAL; 3226 mlx4_ib_handle_catas_error(ibdev); 3227 break; 3228 3229 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3230 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3231 if (!ew) 3232 break; 3233 3234 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3235 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3236 ew->ib_dev = ibdev; 3237 /* need to queue only for port owner, which uses GEN_EQE */ 3238 if (mlx4_is_master(dev)) 3239 queue_work(wq, &ew->work); 3240 else 3241 handle_port_mgmt_change_event(&ew->work); 3242 return; 3243 3244 case MLX4_DEV_EVENT_SLAVE_INIT: 3245 /* here, p is the slave id */ 3246 do_slave_init(ibdev, p, 1); 3247 if (mlx4_is_master(dev)) { 3248 int i; 3249 3250 for (i = 1; i <= ibdev->num_ports; i++) { 3251 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3252 == IB_LINK_LAYER_INFINIBAND) 3253 mlx4_ib_slave_alias_guid_event(ibdev, 3254 p, i, 3255 1); 3256 } 3257 } 3258 return; 3259 3260 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3261 if (mlx4_is_master(dev)) { 3262 int i; 3263 3264 for (i = 1; i <= ibdev->num_ports; i++) { 3265 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3266 == IB_LINK_LAYER_INFINIBAND) 3267 mlx4_ib_slave_alias_guid_event(ibdev, 3268 p, i, 3269 0); 3270 } 3271 } 3272 /* here, p is the slave id */ 3273 do_slave_init(ibdev, p, 0); 3274 return; 3275 3276 default: 3277 return; 3278 } 3279 3280 ibev.device = ibdev_ptr; 3281 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3282 3283 ib_dispatch_event(&ibev); 3284 } 3285 3286 static struct mlx4_interface mlx4_ib_interface = { 3287 .add = mlx4_ib_add, 3288 .remove = mlx4_ib_remove, 3289 .event = mlx4_ib_event, 3290 .protocol = MLX4_PROT_IB_IPV6, 3291 .flags = MLX4_INTFF_BONDING 3292 }; 3293 3294 static int __init mlx4_ib_init(void) 3295 { 3296 int err; 3297 3298 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3299 if (!wq) 3300 return -ENOMEM; 3301 3302 err = mlx4_ib_mcg_init(); 3303 if (err) 3304 goto clean_wq; 3305 3306 err = mlx4_register_interface(&mlx4_ib_interface); 3307 if (err) 3308 goto clean_mcg; 3309 3310 return 0; 3311 3312 clean_mcg: 3313 mlx4_ib_mcg_destroy(); 3314 3315 clean_wq: 3316 destroy_workqueue(wq); 3317 return err; 3318 } 3319 3320 static void __exit mlx4_ib_cleanup(void) 3321 { 3322 mlx4_unregister_interface(&mlx4_ib_interface); 3323 mlx4_ib_mcg_destroy(); 3324 destroy_workqueue(wq); 3325 } 3326 3327 module_init(mlx4_ib_init); 3328 module_exit(mlx4_ib_cleanup); 3329