1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static int mlx4_ib_add_gid(const union ib_gid *gid, 250 const struct ib_gid_attr *attr, 251 void **context) 252 { 253 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 254 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 255 struct mlx4_port_gid_table *port_gid_table; 256 int free = -1, found = -1; 257 int ret = 0; 258 int hw_update = 0; 259 int i; 260 struct gid_entry *gids = NULL; 261 262 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 263 return -EINVAL; 264 265 if (attr->port_num > MLX4_MAX_PORTS) 266 return -EINVAL; 267 268 if (!context) 269 return -EINVAL; 270 271 port_gid_table = &iboe->gids[attr->port_num - 1]; 272 spin_lock_bh(&iboe->lock); 273 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 274 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) && 275 (port_gid_table->gids[i].gid_type == attr->gid_type)) { 276 found = i; 277 break; 278 } 279 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid))) 280 free = i; /* HW has space */ 281 } 282 283 if (found < 0) { 284 if (free < 0) { 285 ret = -ENOSPC; 286 } else { 287 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 288 if (!port_gid_table->gids[free].ctx) { 289 ret = -ENOMEM; 290 } else { 291 *context = port_gid_table->gids[free].ctx; 292 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid)); 293 port_gid_table->gids[free].gid_type = attr->gid_type; 294 port_gid_table->gids[free].ctx->real_index = free; 295 port_gid_table->gids[free].ctx->refcount = 1; 296 hw_update = 1; 297 } 298 } 299 } else { 300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 301 *context = ctx; 302 ctx->refcount++; 303 } 304 if (!ret && hw_update) { 305 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 306 if (!gids) { 307 ret = -ENOMEM; 308 } else { 309 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 310 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 311 gids[i].gid_type = port_gid_table->gids[i].gid_type; 312 } 313 } 314 } 315 spin_unlock_bh(&iboe->lock); 316 317 if (!ret && hw_update) { 318 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 319 kfree(gids); 320 } 321 322 return ret; 323 } 324 325 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 326 { 327 struct gid_cache_context *ctx = *context; 328 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 329 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 330 struct mlx4_port_gid_table *port_gid_table; 331 int ret = 0; 332 int hw_update = 0; 333 struct gid_entry *gids = NULL; 334 335 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 336 return -EINVAL; 337 338 if (attr->port_num > MLX4_MAX_PORTS) 339 return -EINVAL; 340 341 port_gid_table = &iboe->gids[attr->port_num - 1]; 342 spin_lock_bh(&iboe->lock); 343 if (ctx) { 344 ctx->refcount--; 345 if (!ctx->refcount) { 346 unsigned int real_index = ctx->real_index; 347 348 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid)); 349 kfree(port_gid_table->gids[real_index].ctx); 350 port_gid_table->gids[real_index].ctx = NULL; 351 hw_update = 1; 352 } 353 } 354 if (!ret && hw_update) { 355 int i; 356 357 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC); 358 if (!gids) { 359 ret = -ENOMEM; 360 } else { 361 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 362 memcpy(&gids[i].gid, 363 &port_gid_table->gids[i].gid, 364 sizeof(union ib_gid)); 365 gids[i].gid_type = 366 port_gid_table->gids[i].gid_type; 367 } 368 } 369 } 370 spin_unlock_bh(&iboe->lock); 371 372 if (!ret && hw_update) { 373 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 374 kfree(gids); 375 } 376 return ret; 377 } 378 379 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 380 u8 port_num, int index) 381 { 382 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 383 struct gid_cache_context *ctx = NULL; 384 union ib_gid gid; 385 struct mlx4_port_gid_table *port_gid_table; 386 int real_index = -EINVAL; 387 int i; 388 int ret; 389 unsigned long flags; 390 struct ib_gid_attr attr; 391 392 if (port_num > MLX4_MAX_PORTS) 393 return -EINVAL; 394 395 if (mlx4_is_bonded(ibdev->dev)) 396 port_num = 1; 397 398 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 399 return index; 400 401 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (attr.ndev) 406 dev_put(attr.ndev); 407 408 spin_lock_irqsave(&iboe->lock, flags); 409 port_gid_table = &iboe->gids[port_num - 1]; 410 411 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 412 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) && 413 attr.gid_type == port_gid_table->gids[i].gid_type) { 414 ctx = port_gid_table->gids[i].ctx; 415 break; 416 } 417 if (ctx) 418 real_index = ctx->real_index; 419 spin_unlock_irqrestore(&iboe->lock, flags); 420 return real_index; 421 } 422 423 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 424 sizeof(((type *)0)->fld) <= (sz)) 425 426 static int mlx4_ib_query_device(struct ib_device *ibdev, 427 struct ib_device_attr *props, 428 struct ib_udata *uhw) 429 { 430 struct mlx4_ib_dev *dev = to_mdev(ibdev); 431 struct ib_smp *in_mad = NULL; 432 struct ib_smp *out_mad = NULL; 433 int err; 434 int have_ib_ports; 435 struct mlx4_uverbs_ex_query_device cmd; 436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 437 struct mlx4_clock_params clock_params; 438 439 if (uhw->inlen) { 440 if (uhw->inlen < sizeof(cmd)) 441 return -EINVAL; 442 443 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 444 if (err) 445 return err; 446 447 if (cmd.comp_mask) 448 return -EINVAL; 449 450 if (cmd.reserved) 451 return -EINVAL; 452 } 453 454 resp.response_length = offsetof(typeof(resp), response_length) + 455 sizeof(resp.response_length); 456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 458 err = -ENOMEM; 459 if (!in_mad || !out_mad) 460 goto out; 461 462 init_query_mad(in_mad); 463 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 464 465 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 466 1, NULL, NULL, in_mad, out_mad); 467 if (err) 468 goto out; 469 470 memset(props, 0, sizeof *props); 471 472 have_ib_ports = num_ib_ports(dev->dev); 473 474 props->fw_ver = dev->dev->caps.fw_ver; 475 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 476 IB_DEVICE_PORT_ACTIVE_EVENT | 477 IB_DEVICE_SYS_IMAGE_GUID | 478 IB_DEVICE_RC_RNR_NAK_GEN | 479 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 480 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 481 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 482 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 483 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 484 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 485 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 486 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 487 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 488 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 489 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 490 if (dev->dev->caps.max_gso_sz && 491 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 492 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 493 props->device_cap_flags |= IB_DEVICE_UD_TSO; 494 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 495 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 496 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 497 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 498 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 499 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 500 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 501 props->device_cap_flags |= IB_DEVICE_XRC; 502 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 504 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 505 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 506 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 507 else 508 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 509 } 510 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 511 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 512 513 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 514 515 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 516 0xffffff; 517 props->vendor_part_id = dev->dev->persist->pdev->device; 518 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 519 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 520 521 props->max_mr_size = ~0ull; 522 props->page_size_cap = dev->dev->caps.page_size_cap; 523 props->max_qp = dev->dev->quotas.qp; 524 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 525 props->max_sge = min(dev->dev->caps.max_sq_sg, 526 dev->dev->caps.max_rq_sg); 527 props->max_sge_rd = MLX4_MAX_SGE_RD; 528 props->max_cq = dev->dev->quotas.cq; 529 props->max_cqe = dev->dev->caps.max_cqes; 530 props->max_mr = dev->dev->quotas.mpt; 531 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 532 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 533 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 534 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 535 props->max_srq = dev->dev->quotas.srq; 536 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 537 props->max_srq_sge = dev->dev->caps.max_srq_sge; 538 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 539 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 540 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 541 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 542 props->masked_atomic_cap = props->atomic_cap; 543 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 544 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 545 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 546 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 547 props->max_mcast_grp; 548 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 549 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 550 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 551 props->max_ah = INT_MAX; 552 553 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 554 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 555 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 556 props->rss_caps.max_rwq_indirection_tables = 557 props->max_qp; 558 props->rss_caps.max_rwq_indirection_table_size = 559 dev->dev->caps.max_rss_tbl_sz; 560 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 561 props->max_wq_type_rq = props->max_qp; 562 } 563 564 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 565 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 566 } 567 568 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 569 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 570 571 if (!mlx4_is_slave(dev->dev)) 572 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 573 574 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 575 resp.response_length += sizeof(resp.hca_core_clock_offset); 576 if (!err && !mlx4_is_slave(dev->dev)) { 577 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 578 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 579 } 580 } 581 582 if (uhw->outlen >= resp.response_length + 583 sizeof(resp.max_inl_recv_sz)) { 584 resp.response_length += sizeof(resp.max_inl_recv_sz); 585 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 586 sizeof(struct mlx4_wqe_data_seg); 587 } 588 589 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 590 if (props->rss_caps.supported_qpts) { 591 resp.rss_caps.rx_hash_function = 592 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 593 594 resp.rss_caps.rx_hash_fields_mask = 595 MLX4_IB_RX_HASH_SRC_IPV4 | 596 MLX4_IB_RX_HASH_DST_IPV4 | 597 MLX4_IB_RX_HASH_SRC_IPV6 | 598 MLX4_IB_RX_HASH_DST_IPV6 | 599 MLX4_IB_RX_HASH_SRC_PORT_TCP | 600 MLX4_IB_RX_HASH_DST_PORT_TCP | 601 MLX4_IB_RX_HASH_SRC_PORT_UDP | 602 MLX4_IB_RX_HASH_DST_PORT_UDP; 603 604 if (dev->dev->caps.tunnel_offload_mode == 605 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 606 resp.rss_caps.rx_hash_fields_mask |= 607 MLX4_IB_RX_HASH_INNER; 608 } 609 resp.response_length = offsetof(typeof(resp), rss_caps) + 610 sizeof(resp.rss_caps); 611 } 612 613 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 614 if (dev->dev->caps.max_gso_sz && 615 ((mlx4_ib_port_link_layer(ibdev, 1) == 616 IB_LINK_LAYER_ETHERNET) || 617 (mlx4_ib_port_link_layer(ibdev, 2) == 618 IB_LINK_LAYER_ETHERNET))) { 619 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 620 resp.tso_caps.supported_qpts |= 621 1 << IB_QPT_RAW_PACKET; 622 } 623 resp.response_length = offsetof(typeof(resp), tso_caps) + 624 sizeof(resp.tso_caps); 625 } 626 627 if (uhw->outlen) { 628 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 629 if (err) 630 goto out; 631 } 632 out: 633 kfree(in_mad); 634 kfree(out_mad); 635 636 return err; 637 } 638 639 static enum rdma_link_layer 640 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 641 { 642 struct mlx4_dev *dev = to_mdev(device)->dev; 643 644 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 645 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 646 } 647 648 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 649 struct ib_port_attr *props, int netw_view) 650 { 651 struct ib_smp *in_mad = NULL; 652 struct ib_smp *out_mad = NULL; 653 int ext_active_speed; 654 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 655 int err = -ENOMEM; 656 657 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 658 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 659 if (!in_mad || !out_mad) 660 goto out; 661 662 init_query_mad(in_mad); 663 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 664 in_mad->attr_mod = cpu_to_be32(port); 665 666 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 667 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 668 669 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 670 in_mad, out_mad); 671 if (err) 672 goto out; 673 674 675 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 676 props->lmc = out_mad->data[34] & 0x7; 677 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 678 props->sm_sl = out_mad->data[36] & 0xf; 679 props->state = out_mad->data[32] & 0xf; 680 props->phys_state = out_mad->data[33] >> 4; 681 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 682 if (netw_view) 683 props->gid_tbl_len = out_mad->data[50]; 684 else 685 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 686 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 687 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 688 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 689 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 690 props->active_width = out_mad->data[31] & 0xf; 691 props->active_speed = out_mad->data[35] >> 4; 692 props->max_mtu = out_mad->data[41] & 0xf; 693 props->active_mtu = out_mad->data[36] >> 4; 694 props->subnet_timeout = out_mad->data[51] & 0x1f; 695 props->max_vl_num = out_mad->data[37] >> 4; 696 props->init_type_reply = out_mad->data[41] >> 4; 697 698 /* Check if extended speeds (EDR/FDR/...) are supported */ 699 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 700 ext_active_speed = out_mad->data[62] >> 4; 701 702 switch (ext_active_speed) { 703 case 1: 704 props->active_speed = IB_SPEED_FDR; 705 break; 706 case 2: 707 props->active_speed = IB_SPEED_EDR; 708 break; 709 } 710 } 711 712 /* If reported active speed is QDR, check if is FDR-10 */ 713 if (props->active_speed == IB_SPEED_QDR) { 714 init_query_mad(in_mad); 715 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 716 in_mad->attr_mod = cpu_to_be32(port); 717 718 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 719 NULL, NULL, in_mad, out_mad); 720 if (err) 721 goto out; 722 723 /* Checking LinkSpeedActive for FDR-10 */ 724 if (out_mad->data[15] & 0x1) 725 props->active_speed = IB_SPEED_FDR10; 726 } 727 728 /* Avoid wrong speed value returned by FW if the IB link is down. */ 729 if (props->state == IB_PORT_DOWN) 730 props->active_speed = IB_SPEED_SDR; 731 732 out: 733 kfree(in_mad); 734 kfree(out_mad); 735 return err; 736 } 737 738 static u8 state_to_phys_state(enum ib_port_state state) 739 { 740 return state == IB_PORT_ACTIVE ? 5 : 3; 741 } 742 743 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 744 struct ib_port_attr *props) 745 { 746 747 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 748 struct mlx4_ib_iboe *iboe = &mdev->iboe; 749 struct net_device *ndev; 750 enum ib_mtu tmp; 751 struct mlx4_cmd_mailbox *mailbox; 752 int err = 0; 753 int is_bonded = mlx4_is_bonded(mdev->dev); 754 755 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 756 if (IS_ERR(mailbox)) 757 return PTR_ERR(mailbox); 758 759 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 760 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 761 MLX4_CMD_WRAPPED); 762 if (err) 763 goto out; 764 765 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 766 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 767 IB_WIDTH_4X : IB_WIDTH_1X; 768 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 769 IB_SPEED_FDR : IB_SPEED_QDR; 770 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; 771 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 772 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 773 props->pkey_tbl_len = 1; 774 props->max_mtu = IB_MTU_4096; 775 props->max_vl_num = 2; 776 props->state = IB_PORT_DOWN; 777 props->phys_state = state_to_phys_state(props->state); 778 props->active_mtu = IB_MTU_256; 779 spin_lock_bh(&iboe->lock); 780 ndev = iboe->netdevs[port - 1]; 781 if (ndev && is_bonded) { 782 rcu_read_lock(); /* required to get upper dev */ 783 ndev = netdev_master_upper_dev_get_rcu(ndev); 784 rcu_read_unlock(); 785 } 786 if (!ndev) 787 goto out_unlock; 788 789 tmp = iboe_get_mtu(ndev->mtu); 790 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 791 792 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 793 IB_PORT_ACTIVE : IB_PORT_DOWN; 794 props->phys_state = state_to_phys_state(props->state); 795 out_unlock: 796 spin_unlock_bh(&iboe->lock); 797 out: 798 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 799 return err; 800 } 801 802 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 803 struct ib_port_attr *props, int netw_view) 804 { 805 int err; 806 807 /* props being zeroed by the caller, avoid zeroing it here */ 808 809 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 810 ib_link_query_port(ibdev, port, props, netw_view) : 811 eth_link_query_port(ibdev, port, props); 812 813 return err; 814 } 815 816 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 817 struct ib_port_attr *props) 818 { 819 /* returns host view */ 820 return __mlx4_ib_query_port(ibdev, port, props, 0); 821 } 822 823 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 824 union ib_gid *gid, int netw_view) 825 { 826 struct ib_smp *in_mad = NULL; 827 struct ib_smp *out_mad = NULL; 828 int err = -ENOMEM; 829 struct mlx4_ib_dev *dev = to_mdev(ibdev); 830 int clear = 0; 831 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 832 833 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 834 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 835 if (!in_mad || !out_mad) 836 goto out; 837 838 init_query_mad(in_mad); 839 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 840 in_mad->attr_mod = cpu_to_be32(port); 841 842 if (mlx4_is_mfunc(dev->dev) && netw_view) 843 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 844 845 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 846 if (err) 847 goto out; 848 849 memcpy(gid->raw, out_mad->data + 8, 8); 850 851 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 852 if (index) { 853 /* For any index > 0, return the null guid */ 854 err = 0; 855 clear = 1; 856 goto out; 857 } 858 } 859 860 init_query_mad(in_mad); 861 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 862 in_mad->attr_mod = cpu_to_be32(index / 8); 863 864 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 865 NULL, NULL, in_mad, out_mad); 866 if (err) 867 goto out; 868 869 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 870 871 out: 872 if (clear) 873 memset(gid->raw + 8, 0, 8); 874 kfree(in_mad); 875 kfree(out_mad); 876 return err; 877 } 878 879 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 880 union ib_gid *gid) 881 { 882 if (rdma_protocol_ib(ibdev, port)) 883 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 884 return 0; 885 } 886 887 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 888 { 889 union sl2vl_tbl_to_u64 sl2vl64; 890 struct ib_smp *in_mad = NULL; 891 struct ib_smp *out_mad = NULL; 892 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 893 int err = -ENOMEM; 894 int jj; 895 896 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 897 *sl2vl_tbl = 0; 898 return 0; 899 } 900 901 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 902 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 903 if (!in_mad || !out_mad) 904 goto out; 905 906 init_query_mad(in_mad); 907 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 908 in_mad->attr_mod = 0; 909 910 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 911 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 912 913 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 914 in_mad, out_mad); 915 if (err) 916 goto out; 917 918 for (jj = 0; jj < 8; jj++) 919 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 920 *sl2vl_tbl = sl2vl64.sl64; 921 922 out: 923 kfree(in_mad); 924 kfree(out_mad); 925 return err; 926 } 927 928 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 929 { 930 u64 sl2vl; 931 int i; 932 int err; 933 934 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 935 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 936 continue; 937 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 938 if (err) { 939 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 940 i, err); 941 sl2vl = 0; 942 } 943 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 944 } 945 } 946 947 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 948 u16 *pkey, int netw_view) 949 { 950 struct ib_smp *in_mad = NULL; 951 struct ib_smp *out_mad = NULL; 952 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 953 int err = -ENOMEM; 954 955 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 956 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 957 if (!in_mad || !out_mad) 958 goto out; 959 960 init_query_mad(in_mad); 961 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 962 in_mad->attr_mod = cpu_to_be32(index / 32); 963 964 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 965 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 966 967 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 968 in_mad, out_mad); 969 if (err) 970 goto out; 971 972 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 973 974 out: 975 kfree(in_mad); 976 kfree(out_mad); 977 return err; 978 } 979 980 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 981 { 982 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 983 } 984 985 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 986 struct ib_device_modify *props) 987 { 988 struct mlx4_cmd_mailbox *mailbox; 989 unsigned long flags; 990 991 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 992 return -EOPNOTSUPP; 993 994 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 995 return 0; 996 997 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 998 return -EOPNOTSUPP; 999 1000 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 1001 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1002 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1003 1004 /* 1005 * If possible, pass node desc to FW, so it can generate 1006 * a 144 trap. If cmd fails, just ignore. 1007 */ 1008 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1009 if (IS_ERR(mailbox)) 1010 return 0; 1011 1012 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1013 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1014 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1015 1016 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1017 1018 return 0; 1019 } 1020 1021 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1022 u32 cap_mask) 1023 { 1024 struct mlx4_cmd_mailbox *mailbox; 1025 int err; 1026 1027 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1028 if (IS_ERR(mailbox)) 1029 return PTR_ERR(mailbox); 1030 1031 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1032 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1033 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1034 } else { 1035 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1036 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1037 } 1038 1039 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1040 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1041 MLX4_CMD_WRAPPED); 1042 1043 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1044 return err; 1045 } 1046 1047 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1048 struct ib_port_modify *props) 1049 { 1050 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1051 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1052 struct ib_port_attr attr; 1053 u32 cap_mask; 1054 int err; 1055 1056 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1057 * of whether port link layer is ETH or IB. For ETH ports, qkey 1058 * violations and port capabilities are not meaningful. 1059 */ 1060 if (is_eth) 1061 return 0; 1062 1063 mutex_lock(&mdev->cap_mask_mutex); 1064 1065 err = ib_query_port(ibdev, port, &attr); 1066 if (err) 1067 goto out; 1068 1069 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1070 ~props->clr_port_cap_mask; 1071 1072 err = mlx4_ib_SET_PORT(mdev, port, 1073 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1074 cap_mask); 1075 1076 out: 1077 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1078 return err; 1079 } 1080 1081 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1082 struct ib_udata *udata) 1083 { 1084 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1085 struct mlx4_ib_ucontext *context; 1086 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1087 struct mlx4_ib_alloc_ucontext_resp resp; 1088 int err; 1089 1090 if (!dev->ib_active) 1091 return ERR_PTR(-EAGAIN); 1092 1093 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1094 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1095 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1096 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1097 } else { 1098 resp.dev_caps = dev->dev->caps.userspace_caps; 1099 resp.qp_tab_size = dev->dev->caps.num_qps; 1100 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1101 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1102 resp.cqe_size = dev->dev->caps.cqe_size; 1103 } 1104 1105 context = kzalloc(sizeof(*context), GFP_KERNEL); 1106 if (!context) 1107 return ERR_PTR(-ENOMEM); 1108 1109 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1110 if (err) { 1111 kfree(context); 1112 return ERR_PTR(err); 1113 } 1114 1115 INIT_LIST_HEAD(&context->db_page_list); 1116 mutex_init(&context->db_page_mutex); 1117 1118 INIT_LIST_HEAD(&context->wqn_ranges_list); 1119 mutex_init(&context->wqn_ranges_mutex); 1120 1121 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1122 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1123 else 1124 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1125 1126 if (err) { 1127 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1128 kfree(context); 1129 return ERR_PTR(-EFAULT); 1130 } 1131 1132 return &context->ibucontext; 1133 } 1134 1135 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1136 { 1137 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1138 1139 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1140 kfree(context); 1141 1142 return 0; 1143 } 1144 1145 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1146 { 1147 /* vma_open is called when a new VMA is created on top of our VMA. 1148 * This is done through either mremap flow or split_vma (usually due 1149 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1150 * vma, as this VMA is strongly hardware related. Therefore we set the 1151 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1152 * calling us again and trying to do incorrect actions. We assume that 1153 * the original vma size is exactly a single page that there will be no 1154 * "splitting" operations on. 1155 */ 1156 area->vm_ops = NULL; 1157 } 1158 1159 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1160 { 1161 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1162 1163 /* It's guaranteed that all VMAs opened on a FD are closed before the 1164 * file itself is closed, therefore no sync is needed with the regular 1165 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1166 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1167 * The close operation is usually called under mm->mmap_sem except when 1168 * process is exiting. The exiting case is handled explicitly as part 1169 * of mlx4_ib_disassociate_ucontext. 1170 */ 1171 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1172 area->vm_private_data; 1173 1174 /* set the vma context pointer to null in the mlx4_ib driver's private 1175 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1176 */ 1177 mlx4_ib_vma_priv_data->vma = NULL; 1178 } 1179 1180 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1181 .open = mlx4_ib_vma_open, 1182 .close = mlx4_ib_vma_close 1183 }; 1184 1185 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1186 { 1187 int i; 1188 int ret = 0; 1189 struct vm_area_struct *vma; 1190 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1191 struct task_struct *owning_process = NULL; 1192 struct mm_struct *owning_mm = NULL; 1193 1194 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1195 if (!owning_process) 1196 return; 1197 1198 owning_mm = get_task_mm(owning_process); 1199 if (!owning_mm) { 1200 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1201 while (1) { 1202 /* make sure that task is dead before returning, it may 1203 * prevent a rare case of module down in parallel to a 1204 * call to mlx4_ib_vma_close. 1205 */ 1206 put_task_struct(owning_process); 1207 usleep_range(1000, 2000); 1208 owning_process = get_pid_task(ibcontext->tgid, 1209 PIDTYPE_PID); 1210 if (!owning_process || 1211 owning_process->state == TASK_DEAD) { 1212 pr_info("disassociate ucontext done, task was terminated\n"); 1213 /* in case task was dead need to release the task struct */ 1214 if (owning_process) 1215 put_task_struct(owning_process); 1216 return; 1217 } 1218 } 1219 } 1220 1221 /* need to protect from a race on closing the vma as part of 1222 * mlx4_ib_vma_close(). 1223 */ 1224 down_write(&owning_mm->mmap_sem); 1225 for (i = 0; i < HW_BAR_COUNT; i++) { 1226 vma = context->hw_bar_info[i].vma; 1227 if (!vma) 1228 continue; 1229 1230 ret = zap_vma_ptes(context->hw_bar_info[i].vma, 1231 context->hw_bar_info[i].vma->vm_start, 1232 PAGE_SIZE); 1233 if (ret) { 1234 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret); 1235 BUG_ON(1); 1236 } 1237 1238 context->hw_bar_info[i].vma->vm_flags &= 1239 ~(VM_SHARED | VM_MAYSHARE); 1240 /* context going to be destroyed, should not access ops any more */ 1241 context->hw_bar_info[i].vma->vm_ops = NULL; 1242 } 1243 1244 up_write(&owning_mm->mmap_sem); 1245 mmput(owning_mm); 1246 put_task_struct(owning_process); 1247 } 1248 1249 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1250 struct mlx4_ib_vma_private_data *vma_private_data) 1251 { 1252 vma_private_data->vma = vma; 1253 vma->vm_private_data = vma_private_data; 1254 vma->vm_ops = &mlx4_ib_vm_ops; 1255 } 1256 1257 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1258 { 1259 struct mlx4_ib_dev *dev = to_mdev(context->device); 1260 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1261 1262 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1263 return -EINVAL; 1264 1265 if (vma->vm_pgoff == 0) { 1266 /* We prevent double mmaping on same context */ 1267 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1268 return -EINVAL; 1269 1270 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1271 1272 if (io_remap_pfn_range(vma, vma->vm_start, 1273 to_mucontext(context)->uar.pfn, 1274 PAGE_SIZE, vma->vm_page_prot)) 1275 return -EAGAIN; 1276 1277 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1278 1279 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1280 /* We prevent double mmaping on same context */ 1281 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1282 return -EINVAL; 1283 1284 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1285 1286 if (io_remap_pfn_range(vma, vma->vm_start, 1287 to_mucontext(context)->uar.pfn + 1288 dev->dev->caps.num_uars, 1289 PAGE_SIZE, vma->vm_page_prot)) 1290 return -EAGAIN; 1291 1292 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1293 1294 } else if (vma->vm_pgoff == 3) { 1295 struct mlx4_clock_params params; 1296 int ret; 1297 1298 /* We prevent double mmaping on same context */ 1299 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1300 return -EINVAL; 1301 1302 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1303 1304 if (ret) 1305 return ret; 1306 1307 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1308 if (io_remap_pfn_range(vma, vma->vm_start, 1309 (pci_resource_start(dev->dev->persist->pdev, 1310 params.bar) + 1311 params.offset) 1312 >> PAGE_SHIFT, 1313 PAGE_SIZE, vma->vm_page_prot)) 1314 return -EAGAIN; 1315 1316 mlx4_ib_set_vma_data(vma, 1317 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1318 } else { 1319 return -EINVAL; 1320 } 1321 1322 return 0; 1323 } 1324 1325 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1326 struct ib_ucontext *context, 1327 struct ib_udata *udata) 1328 { 1329 struct mlx4_ib_pd *pd; 1330 int err; 1331 1332 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 1333 if (!pd) 1334 return ERR_PTR(-ENOMEM); 1335 1336 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1337 if (err) { 1338 kfree(pd); 1339 return ERR_PTR(err); 1340 } 1341 1342 if (context) 1343 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1344 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1345 kfree(pd); 1346 return ERR_PTR(-EFAULT); 1347 } 1348 return &pd->ibpd; 1349 } 1350 1351 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1352 { 1353 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1354 kfree(pd); 1355 1356 return 0; 1357 } 1358 1359 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1360 struct ib_ucontext *context, 1361 struct ib_udata *udata) 1362 { 1363 struct mlx4_ib_xrcd *xrcd; 1364 struct ib_cq_init_attr cq_attr = {}; 1365 int err; 1366 1367 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1368 return ERR_PTR(-ENOSYS); 1369 1370 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1371 if (!xrcd) 1372 return ERR_PTR(-ENOMEM); 1373 1374 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1375 if (err) 1376 goto err1; 1377 1378 xrcd->pd = ib_alloc_pd(ibdev, 0); 1379 if (IS_ERR(xrcd->pd)) { 1380 err = PTR_ERR(xrcd->pd); 1381 goto err2; 1382 } 1383 1384 cq_attr.cqe = 1; 1385 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1386 if (IS_ERR(xrcd->cq)) { 1387 err = PTR_ERR(xrcd->cq); 1388 goto err3; 1389 } 1390 1391 return &xrcd->ibxrcd; 1392 1393 err3: 1394 ib_dealloc_pd(xrcd->pd); 1395 err2: 1396 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1397 err1: 1398 kfree(xrcd); 1399 return ERR_PTR(err); 1400 } 1401 1402 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1403 { 1404 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1405 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1406 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1407 kfree(xrcd); 1408 1409 return 0; 1410 } 1411 1412 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1413 { 1414 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1415 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1416 struct mlx4_ib_gid_entry *ge; 1417 1418 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1419 if (!ge) 1420 return -ENOMEM; 1421 1422 ge->gid = *gid; 1423 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1424 ge->port = mqp->port; 1425 ge->added = 1; 1426 } 1427 1428 mutex_lock(&mqp->mutex); 1429 list_add_tail(&ge->list, &mqp->gid_list); 1430 mutex_unlock(&mqp->mutex); 1431 1432 return 0; 1433 } 1434 1435 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1436 struct mlx4_ib_counters *ctr_table) 1437 { 1438 struct counter_index *counter, *tmp_count; 1439 1440 mutex_lock(&ctr_table->mutex); 1441 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1442 list) { 1443 if (counter->allocated) 1444 mlx4_counter_free(ibdev->dev, counter->index); 1445 list_del(&counter->list); 1446 kfree(counter); 1447 } 1448 mutex_unlock(&ctr_table->mutex); 1449 } 1450 1451 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1452 union ib_gid *gid) 1453 { 1454 struct net_device *ndev; 1455 int ret = 0; 1456 1457 if (!mqp->port) 1458 return 0; 1459 1460 spin_lock_bh(&mdev->iboe.lock); 1461 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1462 if (ndev) 1463 dev_hold(ndev); 1464 spin_unlock_bh(&mdev->iboe.lock); 1465 1466 if (ndev) { 1467 ret = 1; 1468 dev_put(ndev); 1469 } 1470 1471 return ret; 1472 } 1473 1474 struct mlx4_ib_steering { 1475 struct list_head list; 1476 struct mlx4_flow_reg_id reg_id; 1477 union ib_gid gid; 1478 }; 1479 1480 #define LAST_ETH_FIELD vlan_tag 1481 #define LAST_IB_FIELD sl 1482 #define LAST_IPV4_FIELD dst_ip 1483 #define LAST_TCP_UDP_FIELD src_port 1484 1485 /* Field is the last supported field */ 1486 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1487 memchr_inv((void *)&filter.field +\ 1488 sizeof(filter.field), 0,\ 1489 sizeof(filter) -\ 1490 offsetof(typeof(filter), field) -\ 1491 sizeof(filter.field)) 1492 1493 static int parse_flow_attr(struct mlx4_dev *dev, 1494 u32 qp_num, 1495 union ib_flow_spec *ib_spec, 1496 struct _rule_hw *mlx4_spec) 1497 { 1498 enum mlx4_net_trans_rule_id type; 1499 1500 switch (ib_spec->type) { 1501 case IB_FLOW_SPEC_ETH: 1502 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1503 return -ENOTSUPP; 1504 1505 type = MLX4_NET_TRANS_RULE_ID_ETH; 1506 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1507 ETH_ALEN); 1508 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1509 ETH_ALEN); 1510 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1511 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1512 break; 1513 case IB_FLOW_SPEC_IB: 1514 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1515 return -ENOTSUPP; 1516 1517 type = MLX4_NET_TRANS_RULE_ID_IB; 1518 mlx4_spec->ib.l3_qpn = 1519 cpu_to_be32(qp_num); 1520 mlx4_spec->ib.qpn_mask = 1521 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1522 break; 1523 1524 1525 case IB_FLOW_SPEC_IPV4: 1526 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1527 return -ENOTSUPP; 1528 1529 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1530 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1531 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1532 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1533 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1534 break; 1535 1536 case IB_FLOW_SPEC_TCP: 1537 case IB_FLOW_SPEC_UDP: 1538 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1539 return -ENOTSUPP; 1540 1541 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1542 MLX4_NET_TRANS_RULE_ID_TCP : 1543 MLX4_NET_TRANS_RULE_ID_UDP; 1544 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1545 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1546 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1547 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1548 break; 1549 1550 default: 1551 return -EINVAL; 1552 } 1553 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1554 mlx4_hw_rule_sz(dev, type) < 0) 1555 return -EINVAL; 1556 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1557 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1558 return mlx4_hw_rule_sz(dev, type); 1559 } 1560 1561 struct default_rules { 1562 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1563 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1564 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1565 __u8 link_layer; 1566 }; 1567 static const struct default_rules default_table[] = { 1568 { 1569 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1570 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1571 .rules_create_list = {IB_FLOW_SPEC_IB}, 1572 .link_layer = IB_LINK_LAYER_INFINIBAND 1573 } 1574 }; 1575 1576 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1577 struct ib_flow_attr *flow_attr) 1578 { 1579 int i, j, k; 1580 void *ib_flow; 1581 const struct default_rules *pdefault_rules = default_table; 1582 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1583 1584 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1585 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1586 memset(&field_types, 0, sizeof(field_types)); 1587 1588 if (link_layer != pdefault_rules->link_layer) 1589 continue; 1590 1591 ib_flow = flow_attr + 1; 1592 /* we assume the specs are sorted */ 1593 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1594 j < flow_attr->num_of_specs; k++) { 1595 union ib_flow_spec *current_flow = 1596 (union ib_flow_spec *)ib_flow; 1597 1598 /* same layer but different type */ 1599 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1600 (pdefault_rules->mandatory_fields[k] & 1601 IB_FLOW_SPEC_LAYER_MASK)) && 1602 (current_flow->type != 1603 pdefault_rules->mandatory_fields[k])) 1604 goto out; 1605 1606 /* same layer, try match next one */ 1607 if (current_flow->type == 1608 pdefault_rules->mandatory_fields[k]) { 1609 j++; 1610 ib_flow += 1611 ((union ib_flow_spec *)ib_flow)->size; 1612 } 1613 } 1614 1615 ib_flow = flow_attr + 1; 1616 for (j = 0; j < flow_attr->num_of_specs; 1617 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1618 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1619 /* same layer and same type */ 1620 if (((union ib_flow_spec *)ib_flow)->type == 1621 pdefault_rules->mandatory_not_fields[k]) 1622 goto out; 1623 1624 return i; 1625 } 1626 out: 1627 return -1; 1628 } 1629 1630 static int __mlx4_ib_create_default_rules( 1631 struct mlx4_ib_dev *mdev, 1632 struct ib_qp *qp, 1633 const struct default_rules *pdefault_rules, 1634 struct _rule_hw *mlx4_spec) { 1635 int size = 0; 1636 int i; 1637 1638 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1639 int ret; 1640 union ib_flow_spec ib_spec; 1641 switch (pdefault_rules->rules_create_list[i]) { 1642 case 0: 1643 /* no rule */ 1644 continue; 1645 case IB_FLOW_SPEC_IB: 1646 ib_spec.type = IB_FLOW_SPEC_IB; 1647 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1648 1649 break; 1650 default: 1651 /* invalid rule */ 1652 return -EINVAL; 1653 } 1654 /* We must put empty rule, qpn is being ignored */ 1655 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1656 mlx4_spec); 1657 if (ret < 0) { 1658 pr_info("invalid parsing\n"); 1659 return -EINVAL; 1660 } 1661 1662 mlx4_spec = (void *)mlx4_spec + ret; 1663 size += ret; 1664 } 1665 return size; 1666 } 1667 1668 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1669 int domain, 1670 enum mlx4_net_trans_promisc_mode flow_type, 1671 u64 *reg_id) 1672 { 1673 int ret, i; 1674 int size = 0; 1675 void *ib_flow; 1676 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1677 struct mlx4_cmd_mailbox *mailbox; 1678 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1679 int default_flow; 1680 1681 static const u16 __mlx4_domain[] = { 1682 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1683 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1684 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1685 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1686 }; 1687 1688 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1689 pr_err("Invalid priority value %d\n", flow_attr->priority); 1690 return -EINVAL; 1691 } 1692 1693 if (domain >= IB_FLOW_DOMAIN_NUM) { 1694 pr_err("Invalid domain value %d\n", domain); 1695 return -EINVAL; 1696 } 1697 1698 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1699 return -EINVAL; 1700 1701 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1702 if (IS_ERR(mailbox)) 1703 return PTR_ERR(mailbox); 1704 ctrl = mailbox->buf; 1705 1706 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1707 flow_attr->priority); 1708 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1709 ctrl->port = flow_attr->port; 1710 ctrl->qpn = cpu_to_be32(qp->qp_num); 1711 1712 ib_flow = flow_attr + 1; 1713 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1714 /* Add default flows */ 1715 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1716 if (default_flow >= 0) { 1717 ret = __mlx4_ib_create_default_rules( 1718 mdev, qp, default_table + default_flow, 1719 mailbox->buf + size); 1720 if (ret < 0) { 1721 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1722 return -EINVAL; 1723 } 1724 size += ret; 1725 } 1726 for (i = 0; i < flow_attr->num_of_specs; i++) { 1727 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1728 mailbox->buf + size); 1729 if (ret < 0) { 1730 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1731 return -EINVAL; 1732 } 1733 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1734 size += ret; 1735 } 1736 1737 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1738 flow_attr->num_of_specs == 1) { 1739 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1740 enum ib_flow_spec_type header_spec = 1741 ((union ib_flow_spec *)(flow_attr + 1))->type; 1742 1743 if (header_spec == IB_FLOW_SPEC_ETH) 1744 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1745 } 1746 1747 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1748 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1749 MLX4_CMD_NATIVE); 1750 if (ret == -ENOMEM) 1751 pr_err("mcg table is full. Fail to register network rule.\n"); 1752 else if (ret == -ENXIO) 1753 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1754 else if (ret) 1755 pr_err("Invalid argument. Fail to register network rule.\n"); 1756 1757 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1758 return ret; 1759 } 1760 1761 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1762 { 1763 int err; 1764 err = mlx4_cmd(dev, reg_id, 0, 0, 1765 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1766 MLX4_CMD_NATIVE); 1767 if (err) 1768 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1769 reg_id); 1770 return err; 1771 } 1772 1773 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1774 u64 *reg_id) 1775 { 1776 void *ib_flow; 1777 union ib_flow_spec *ib_spec; 1778 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1779 int err = 0; 1780 1781 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1782 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1783 return 0; /* do nothing */ 1784 1785 ib_flow = flow_attr + 1; 1786 ib_spec = (union ib_flow_spec *)ib_flow; 1787 1788 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1789 return 0; /* do nothing */ 1790 1791 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1792 flow_attr->port, qp->qp_num, 1793 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1794 reg_id); 1795 return err; 1796 } 1797 1798 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1799 struct ib_flow_attr *flow_attr, 1800 enum mlx4_net_trans_promisc_mode *type) 1801 { 1802 int err = 0; 1803 1804 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1805 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1806 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1807 return -EOPNOTSUPP; 1808 } 1809 1810 if (flow_attr->num_of_specs == 0) { 1811 type[0] = MLX4_FS_MC_SNIFFER; 1812 type[1] = MLX4_FS_UC_SNIFFER; 1813 } else { 1814 union ib_flow_spec *ib_spec; 1815 1816 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1817 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1818 return -EINVAL; 1819 1820 /* if all is zero than MC and UC */ 1821 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1822 type[0] = MLX4_FS_MC_SNIFFER; 1823 type[1] = MLX4_FS_UC_SNIFFER; 1824 } else { 1825 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1826 ib_spec->eth.mask.dst_mac[1], 1827 ib_spec->eth.mask.dst_mac[2], 1828 ib_spec->eth.mask.dst_mac[3], 1829 ib_spec->eth.mask.dst_mac[4], 1830 ib_spec->eth.mask.dst_mac[5]}; 1831 1832 /* Above xor was only on MC bit, non empty mask is valid 1833 * only if this bit is set and rest are zero. 1834 */ 1835 if (!is_zero_ether_addr(&mac[0])) 1836 return -EINVAL; 1837 1838 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1839 type[0] = MLX4_FS_MC_SNIFFER; 1840 else 1841 type[0] = MLX4_FS_UC_SNIFFER; 1842 } 1843 } 1844 1845 return err; 1846 } 1847 1848 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1849 struct ib_flow_attr *flow_attr, 1850 int domain) 1851 { 1852 int err = 0, i = 0, j = 0; 1853 struct mlx4_ib_flow *mflow; 1854 enum mlx4_net_trans_promisc_mode type[2]; 1855 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1856 int is_bonded = mlx4_is_bonded(dev); 1857 1858 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1859 return ERR_PTR(-EINVAL); 1860 1861 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1862 return ERR_PTR(-EOPNOTSUPP); 1863 1864 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1865 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1866 return ERR_PTR(-EOPNOTSUPP); 1867 1868 memset(type, 0, sizeof(type)); 1869 1870 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1871 if (!mflow) { 1872 err = -ENOMEM; 1873 goto err_free; 1874 } 1875 1876 switch (flow_attr->type) { 1877 case IB_FLOW_ATTR_NORMAL: 1878 /* If dont trap flag (continue match) is set, under specific 1879 * condition traffic be replicated to given qp, 1880 * without stealing it 1881 */ 1882 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1883 err = mlx4_ib_add_dont_trap_rule(dev, 1884 flow_attr, 1885 type); 1886 if (err) 1887 goto err_free; 1888 } else { 1889 type[0] = MLX4_FS_REGULAR; 1890 } 1891 break; 1892 1893 case IB_FLOW_ATTR_ALL_DEFAULT: 1894 type[0] = MLX4_FS_ALL_DEFAULT; 1895 break; 1896 1897 case IB_FLOW_ATTR_MC_DEFAULT: 1898 type[0] = MLX4_FS_MC_DEFAULT; 1899 break; 1900 1901 case IB_FLOW_ATTR_SNIFFER: 1902 type[0] = MLX4_FS_MIRROR_RX_PORT; 1903 type[1] = MLX4_FS_MIRROR_SX_PORT; 1904 break; 1905 1906 default: 1907 err = -EINVAL; 1908 goto err_free; 1909 } 1910 1911 while (i < ARRAY_SIZE(type) && type[i]) { 1912 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1913 &mflow->reg_id[i].id); 1914 if (err) 1915 goto err_create_flow; 1916 if (is_bonded) { 1917 /* Application always sees one port so the mirror rule 1918 * must be on port #2 1919 */ 1920 flow_attr->port = 2; 1921 err = __mlx4_ib_create_flow(qp, flow_attr, 1922 domain, type[j], 1923 &mflow->reg_id[j].mirror); 1924 flow_attr->port = 1; 1925 if (err) 1926 goto err_create_flow; 1927 j++; 1928 } 1929 1930 i++; 1931 } 1932 1933 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1934 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1935 &mflow->reg_id[i].id); 1936 if (err) 1937 goto err_create_flow; 1938 1939 if (is_bonded) { 1940 flow_attr->port = 2; 1941 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1942 &mflow->reg_id[j].mirror); 1943 flow_attr->port = 1; 1944 if (err) 1945 goto err_create_flow; 1946 j++; 1947 } 1948 /* function to create mirror rule */ 1949 i++; 1950 } 1951 1952 return &mflow->ibflow; 1953 1954 err_create_flow: 1955 while (i) { 1956 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1957 mflow->reg_id[i].id); 1958 i--; 1959 } 1960 1961 while (j) { 1962 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1963 mflow->reg_id[j].mirror); 1964 j--; 1965 } 1966 err_free: 1967 kfree(mflow); 1968 return ERR_PTR(err); 1969 } 1970 1971 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1972 { 1973 int err, ret = 0; 1974 int i = 0; 1975 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1976 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1977 1978 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1979 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1980 if (err) 1981 ret = err; 1982 if (mflow->reg_id[i].mirror) { 1983 err = __mlx4_ib_destroy_flow(mdev->dev, 1984 mflow->reg_id[i].mirror); 1985 if (err) 1986 ret = err; 1987 } 1988 i++; 1989 } 1990 1991 kfree(mflow); 1992 return ret; 1993 } 1994 1995 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1996 { 1997 int err; 1998 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1999 struct mlx4_dev *dev = mdev->dev; 2000 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2001 struct mlx4_ib_steering *ib_steering = NULL; 2002 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2003 struct mlx4_flow_reg_id reg_id; 2004 2005 if (mdev->dev->caps.steering_mode == 2006 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2007 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 2008 if (!ib_steering) 2009 return -ENOMEM; 2010 } 2011 2012 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 2013 !!(mqp->flags & 2014 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 2015 prot, ®_id.id); 2016 if (err) { 2017 pr_err("multicast attach op failed, err %d\n", err); 2018 goto err_malloc; 2019 } 2020 2021 reg_id.mirror = 0; 2022 if (mlx4_is_bonded(dev)) { 2023 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 2024 (mqp->port == 1) ? 2 : 1, 2025 !!(mqp->flags & 2026 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 2027 prot, ®_id.mirror); 2028 if (err) 2029 goto err_add; 2030 } 2031 2032 err = add_gid_entry(ibqp, gid); 2033 if (err) 2034 goto err_add; 2035 2036 if (ib_steering) { 2037 memcpy(ib_steering->gid.raw, gid->raw, 16); 2038 ib_steering->reg_id = reg_id; 2039 mutex_lock(&mqp->mutex); 2040 list_add(&ib_steering->list, &mqp->steering_rules); 2041 mutex_unlock(&mqp->mutex); 2042 } 2043 return 0; 2044 2045 err_add: 2046 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2047 prot, reg_id.id); 2048 if (reg_id.mirror) 2049 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2050 prot, reg_id.mirror); 2051 err_malloc: 2052 kfree(ib_steering); 2053 2054 return err; 2055 } 2056 2057 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2058 { 2059 struct mlx4_ib_gid_entry *ge; 2060 struct mlx4_ib_gid_entry *tmp; 2061 struct mlx4_ib_gid_entry *ret = NULL; 2062 2063 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2064 if (!memcmp(raw, ge->gid.raw, 16)) { 2065 ret = ge; 2066 break; 2067 } 2068 } 2069 2070 return ret; 2071 } 2072 2073 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2074 { 2075 int err; 2076 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2077 struct mlx4_dev *dev = mdev->dev; 2078 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2079 struct net_device *ndev; 2080 struct mlx4_ib_gid_entry *ge; 2081 struct mlx4_flow_reg_id reg_id = {0, 0}; 2082 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2083 2084 if (mdev->dev->caps.steering_mode == 2085 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2086 struct mlx4_ib_steering *ib_steering; 2087 2088 mutex_lock(&mqp->mutex); 2089 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2090 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2091 list_del(&ib_steering->list); 2092 break; 2093 } 2094 } 2095 mutex_unlock(&mqp->mutex); 2096 if (&ib_steering->list == &mqp->steering_rules) { 2097 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2098 return -EINVAL; 2099 } 2100 reg_id = ib_steering->reg_id; 2101 kfree(ib_steering); 2102 } 2103 2104 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2105 prot, reg_id.id); 2106 if (err) 2107 return err; 2108 2109 if (mlx4_is_bonded(dev)) { 2110 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2111 prot, reg_id.mirror); 2112 if (err) 2113 return err; 2114 } 2115 2116 mutex_lock(&mqp->mutex); 2117 ge = find_gid_entry(mqp, gid->raw); 2118 if (ge) { 2119 spin_lock_bh(&mdev->iboe.lock); 2120 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2121 if (ndev) 2122 dev_hold(ndev); 2123 spin_unlock_bh(&mdev->iboe.lock); 2124 if (ndev) 2125 dev_put(ndev); 2126 list_del(&ge->list); 2127 kfree(ge); 2128 } else 2129 pr_warn("could not find mgid entry\n"); 2130 2131 mutex_unlock(&mqp->mutex); 2132 2133 return 0; 2134 } 2135 2136 static int init_node_data(struct mlx4_ib_dev *dev) 2137 { 2138 struct ib_smp *in_mad = NULL; 2139 struct ib_smp *out_mad = NULL; 2140 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2141 int err = -ENOMEM; 2142 2143 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2144 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2145 if (!in_mad || !out_mad) 2146 goto out; 2147 2148 init_query_mad(in_mad); 2149 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2150 if (mlx4_is_master(dev->dev)) 2151 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2152 2153 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2154 if (err) 2155 goto out; 2156 2157 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2158 2159 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2160 2161 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2162 if (err) 2163 goto out; 2164 2165 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2166 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2167 2168 out: 2169 kfree(in_mad); 2170 kfree(out_mad); 2171 return err; 2172 } 2173 2174 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2175 char *buf) 2176 { 2177 struct mlx4_ib_dev *dev = 2178 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2179 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2180 } 2181 2182 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2183 char *buf) 2184 { 2185 struct mlx4_ib_dev *dev = 2186 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2187 return sprintf(buf, "%x\n", dev->dev->rev_id); 2188 } 2189 2190 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2191 char *buf) 2192 { 2193 struct mlx4_ib_dev *dev = 2194 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2195 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2196 dev->dev->board_id); 2197 } 2198 2199 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2200 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2201 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2202 2203 static struct device_attribute *mlx4_class_attributes[] = { 2204 &dev_attr_hw_rev, 2205 &dev_attr_hca_type, 2206 &dev_attr_board_id 2207 }; 2208 2209 struct diag_counter { 2210 const char *name; 2211 u32 offset; 2212 }; 2213 2214 #define DIAG_COUNTER(_name, _offset) \ 2215 { .name = #_name, .offset = _offset } 2216 2217 static const struct diag_counter diag_basic[] = { 2218 DIAG_COUNTER(rq_num_lle, 0x00), 2219 DIAG_COUNTER(sq_num_lle, 0x04), 2220 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2221 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2222 DIAG_COUNTER(rq_num_lpe, 0x18), 2223 DIAG_COUNTER(sq_num_lpe, 0x1C), 2224 DIAG_COUNTER(rq_num_wrfe, 0x20), 2225 DIAG_COUNTER(sq_num_wrfe, 0x24), 2226 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2227 DIAG_COUNTER(sq_num_bre, 0x34), 2228 DIAG_COUNTER(sq_num_rire, 0x44), 2229 DIAG_COUNTER(rq_num_rire, 0x48), 2230 DIAG_COUNTER(sq_num_rae, 0x4C), 2231 DIAG_COUNTER(rq_num_rae, 0x50), 2232 DIAG_COUNTER(sq_num_roe, 0x54), 2233 DIAG_COUNTER(sq_num_tree, 0x5C), 2234 DIAG_COUNTER(sq_num_rree, 0x64), 2235 DIAG_COUNTER(rq_num_rnr, 0x68), 2236 DIAG_COUNTER(sq_num_rnr, 0x6C), 2237 DIAG_COUNTER(rq_num_oos, 0x100), 2238 DIAG_COUNTER(sq_num_oos, 0x104), 2239 }; 2240 2241 static const struct diag_counter diag_ext[] = { 2242 DIAG_COUNTER(rq_num_dup, 0x130), 2243 DIAG_COUNTER(sq_num_to, 0x134), 2244 }; 2245 2246 static const struct diag_counter diag_device_only[] = { 2247 DIAG_COUNTER(num_cqovf, 0x1A0), 2248 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2249 }; 2250 2251 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2252 u8 port_num) 2253 { 2254 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2255 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2256 2257 if (!diag[!!port_num].name) 2258 return NULL; 2259 2260 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2261 diag[!!port_num].num_counters, 2262 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2263 } 2264 2265 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2266 struct rdma_hw_stats *stats, 2267 u8 port, int index) 2268 { 2269 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2270 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2271 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2272 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2273 int ret; 2274 int i; 2275 2276 ret = mlx4_query_diag_counters(dev->dev, 2277 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2278 diag[!!port].offset, hw_value, 2279 diag[!!port].num_counters, port); 2280 2281 if (ret) 2282 return ret; 2283 2284 for (i = 0; i < diag[!!port].num_counters; i++) 2285 stats->value[i] = hw_value[i]; 2286 2287 return diag[!!port].num_counters; 2288 } 2289 2290 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2291 const char ***name, 2292 u32 **offset, 2293 u32 *num, 2294 bool port) 2295 { 2296 u32 num_counters; 2297 2298 num_counters = ARRAY_SIZE(diag_basic); 2299 2300 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2301 num_counters += ARRAY_SIZE(diag_ext); 2302 2303 if (!port) 2304 num_counters += ARRAY_SIZE(diag_device_only); 2305 2306 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2307 if (!*name) 2308 return -ENOMEM; 2309 2310 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2311 if (!*offset) 2312 goto err_name; 2313 2314 *num = num_counters; 2315 2316 return 0; 2317 2318 err_name: 2319 kfree(*name); 2320 return -ENOMEM; 2321 } 2322 2323 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2324 const char **name, 2325 u32 *offset, 2326 bool port) 2327 { 2328 int i; 2329 int j; 2330 2331 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2332 name[i] = diag_basic[i].name; 2333 offset[i] = diag_basic[i].offset; 2334 } 2335 2336 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2337 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2338 name[j] = diag_ext[i].name; 2339 offset[j] = diag_ext[i].offset; 2340 } 2341 } 2342 2343 if (!port) { 2344 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2345 name[j] = diag_device_only[i].name; 2346 offset[j] = diag_device_only[i].offset; 2347 } 2348 } 2349 } 2350 2351 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2352 { 2353 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2354 int i; 2355 int ret; 2356 bool per_port = !!(ibdev->dev->caps.flags2 & 2357 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2358 2359 if (mlx4_is_slave(ibdev->dev)) 2360 return 0; 2361 2362 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2363 /* i == 1 means we are building port counters */ 2364 if (i && !per_port) 2365 continue; 2366 2367 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2368 &diag[i].offset, 2369 &diag[i].num_counters, i); 2370 if (ret) 2371 goto err_alloc; 2372 2373 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2374 diag[i].offset, i); 2375 } 2376 2377 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2378 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2379 2380 return 0; 2381 2382 err_alloc: 2383 if (i) { 2384 kfree(diag[i - 1].name); 2385 kfree(diag[i - 1].offset); 2386 } 2387 2388 return ret; 2389 } 2390 2391 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2392 { 2393 int i; 2394 2395 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2396 kfree(ibdev->diag_counters[i].offset); 2397 kfree(ibdev->diag_counters[i].name); 2398 } 2399 } 2400 2401 #define MLX4_IB_INVALID_MAC ((u64)-1) 2402 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2403 struct net_device *dev, 2404 int port) 2405 { 2406 u64 new_smac = 0; 2407 u64 release_mac = MLX4_IB_INVALID_MAC; 2408 struct mlx4_ib_qp *qp; 2409 2410 read_lock(&dev_base_lock); 2411 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2412 read_unlock(&dev_base_lock); 2413 2414 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2415 2416 /* no need for update QP1 and mac registration in non-SRIOV */ 2417 if (!mlx4_is_mfunc(ibdev->dev)) 2418 return; 2419 2420 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2421 qp = ibdev->qp1_proxy[port - 1]; 2422 if (qp) { 2423 int new_smac_index; 2424 u64 old_smac; 2425 struct mlx4_update_qp_params update_params; 2426 2427 mutex_lock(&qp->mutex); 2428 old_smac = qp->pri.smac; 2429 if (new_smac == old_smac) 2430 goto unlock; 2431 2432 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2433 2434 if (new_smac_index < 0) 2435 goto unlock; 2436 2437 update_params.smac_index = new_smac_index; 2438 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2439 &update_params)) { 2440 release_mac = new_smac; 2441 goto unlock; 2442 } 2443 /* if old port was zero, no mac was yet registered for this QP */ 2444 if (qp->pri.smac_port) 2445 release_mac = old_smac; 2446 qp->pri.smac = new_smac; 2447 qp->pri.smac_port = port; 2448 qp->pri.smac_index = new_smac_index; 2449 } 2450 2451 unlock: 2452 if (release_mac != MLX4_IB_INVALID_MAC) 2453 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2454 if (qp) 2455 mutex_unlock(&qp->mutex); 2456 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2457 } 2458 2459 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2460 struct net_device *dev, 2461 unsigned long event) 2462 2463 { 2464 struct mlx4_ib_iboe *iboe; 2465 int update_qps_port = -1; 2466 int port; 2467 2468 ASSERT_RTNL(); 2469 2470 iboe = &ibdev->iboe; 2471 2472 spin_lock_bh(&iboe->lock); 2473 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2474 2475 iboe->netdevs[port - 1] = 2476 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2477 2478 if (dev == iboe->netdevs[port - 1] && 2479 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2480 event == NETDEV_UP || event == NETDEV_CHANGE)) 2481 update_qps_port = port; 2482 2483 } 2484 spin_unlock_bh(&iboe->lock); 2485 2486 if (update_qps_port > 0) 2487 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2488 } 2489 2490 static int mlx4_ib_netdev_event(struct notifier_block *this, 2491 unsigned long event, void *ptr) 2492 { 2493 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2494 struct mlx4_ib_dev *ibdev; 2495 2496 if (!net_eq(dev_net(dev), &init_net)) 2497 return NOTIFY_DONE; 2498 2499 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2500 mlx4_ib_scan_netdevs(ibdev, dev, event); 2501 2502 return NOTIFY_DONE; 2503 } 2504 2505 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2506 { 2507 int port; 2508 int slave; 2509 int i; 2510 2511 if (mlx4_is_master(ibdev->dev)) { 2512 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2513 ++slave) { 2514 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2515 for (i = 0; 2516 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2517 ++i) { 2518 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2519 /* master has the identity virt2phys pkey mapping */ 2520 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2521 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2522 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2523 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2524 } 2525 } 2526 } 2527 /* initialize pkey cache */ 2528 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2529 for (i = 0; 2530 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2531 ++i) 2532 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2533 (i) ? 0 : 0xFFFF; 2534 } 2535 } 2536 } 2537 2538 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2539 { 2540 int i, j, eq = 0, total_eqs = 0; 2541 2542 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2543 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2544 if (!ibdev->eq_table) 2545 return; 2546 2547 for (i = 1; i <= dev->caps.num_ports; i++) { 2548 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2549 j++, total_eqs++) { 2550 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2551 continue; 2552 ibdev->eq_table[eq] = total_eqs; 2553 if (!mlx4_assign_eq(dev, i, 2554 &ibdev->eq_table[eq])) 2555 eq++; 2556 else 2557 ibdev->eq_table[eq] = -1; 2558 } 2559 } 2560 2561 for (i = eq; i < dev->caps.num_comp_vectors; 2562 ibdev->eq_table[i++] = -1) 2563 ; 2564 2565 /* Advertise the new number of EQs to clients */ 2566 ibdev->ib_dev.num_comp_vectors = eq; 2567 } 2568 2569 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2570 { 2571 int i; 2572 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2573 2574 /* no eqs were allocated */ 2575 if (!ibdev->eq_table) 2576 return; 2577 2578 /* Reset the advertised EQ number */ 2579 ibdev->ib_dev.num_comp_vectors = 0; 2580 2581 for (i = 0; i < total_eqs; i++) 2582 mlx4_release_eq(dev, ibdev->eq_table[i]); 2583 2584 kfree(ibdev->eq_table); 2585 ibdev->eq_table = NULL; 2586 } 2587 2588 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2589 struct ib_port_immutable *immutable) 2590 { 2591 struct ib_port_attr attr; 2592 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2593 int err; 2594 2595 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2596 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2597 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2598 } else { 2599 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2600 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2601 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2602 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2603 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2604 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2605 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2606 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2607 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2608 } 2609 2610 err = ib_query_port(ibdev, port_num, &attr); 2611 if (err) 2612 return err; 2613 2614 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2615 immutable->gid_tbl_len = attr.gid_tbl_len; 2616 2617 return 0; 2618 } 2619 2620 static void get_fw_ver_str(struct ib_device *device, char *str) 2621 { 2622 struct mlx4_ib_dev *dev = 2623 container_of(device, struct mlx4_ib_dev, ib_dev); 2624 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2625 (int) (dev->dev->caps.fw_ver >> 32), 2626 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2627 (int) dev->dev->caps.fw_ver & 0xffff); 2628 } 2629 2630 static void *mlx4_ib_add(struct mlx4_dev *dev) 2631 { 2632 struct mlx4_ib_dev *ibdev; 2633 int num_ports = 0; 2634 int i, j; 2635 int err; 2636 struct mlx4_ib_iboe *iboe; 2637 int ib_num_ports = 0; 2638 int num_req_counters; 2639 int allocated; 2640 u32 counter_index; 2641 struct counter_index *new_counter_index = NULL; 2642 2643 pr_info_once("%s", mlx4_ib_version); 2644 2645 num_ports = 0; 2646 mlx4_foreach_ib_transport_port(i, dev) 2647 num_ports++; 2648 2649 /* No point in registering a device with no ports... */ 2650 if (num_ports == 0) 2651 return NULL; 2652 2653 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2654 if (!ibdev) { 2655 dev_err(&dev->persist->pdev->dev, 2656 "Device struct alloc failed\n"); 2657 return NULL; 2658 } 2659 2660 iboe = &ibdev->iboe; 2661 2662 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2663 goto err_dealloc; 2664 2665 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2666 goto err_pd; 2667 2668 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2669 PAGE_SIZE); 2670 if (!ibdev->uar_map) 2671 goto err_uar; 2672 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2673 2674 ibdev->dev = dev; 2675 ibdev->bond_next_port = 0; 2676 2677 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2678 ibdev->ib_dev.owner = THIS_MODULE; 2679 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2680 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2681 ibdev->num_ports = num_ports; 2682 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2683 1 : ibdev->num_ports; 2684 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2685 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2686 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2687 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2688 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2689 2690 if (dev->caps.userspace_caps) 2691 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2692 else 2693 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2694 2695 ibdev->ib_dev.uverbs_cmd_mask = 2696 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2697 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2698 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2699 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2700 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2701 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2702 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2703 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2704 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2705 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2706 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2707 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2708 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2709 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2710 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2711 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2712 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2713 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2714 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2715 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2716 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2717 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2718 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2719 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2720 2721 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2722 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2723 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2724 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2725 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2726 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2727 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2728 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2729 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2730 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2731 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2732 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2733 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2734 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2735 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2736 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2737 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2738 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2739 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2740 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2741 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2742 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2743 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2744 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2745 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2746 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2747 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2748 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2749 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2750 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2751 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2752 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2753 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2754 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2755 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2756 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2757 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2758 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2759 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2760 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2761 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2762 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2763 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2764 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2765 2766 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2767 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2768 2769 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2770 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2771 IB_LINK_LAYER_ETHERNET) || 2772 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2773 IB_LINK_LAYER_ETHERNET))) { 2774 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2775 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2776 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2777 ibdev->ib_dev.create_rwq_ind_table = 2778 mlx4_ib_create_rwq_ind_table; 2779 ibdev->ib_dev.destroy_rwq_ind_table = 2780 mlx4_ib_destroy_rwq_ind_table; 2781 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2782 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2783 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2784 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2785 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2786 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2787 } 2788 2789 if (!mlx4_is_slave(ibdev->dev)) { 2790 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2791 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2792 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2793 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2794 } 2795 2796 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2797 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2798 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2799 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2800 2801 ibdev->ib_dev.uverbs_cmd_mask |= 2802 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2803 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2804 } 2805 2806 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2807 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2808 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2809 ibdev->ib_dev.uverbs_cmd_mask |= 2810 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2811 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2812 } 2813 2814 if (check_flow_steering_support(dev)) { 2815 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2816 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2817 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2818 2819 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2820 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2821 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2822 } 2823 2824 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2825 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2826 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2827 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2828 2829 mlx4_ib_alloc_eqs(dev, ibdev); 2830 2831 spin_lock_init(&iboe->lock); 2832 2833 if (init_node_data(ibdev)) 2834 goto err_map; 2835 mlx4_init_sl2vl_tbl(ibdev); 2836 2837 for (i = 0; i < ibdev->num_ports; ++i) { 2838 mutex_init(&ibdev->counters_table[i].mutex); 2839 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2840 } 2841 2842 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2843 for (i = 0; i < num_req_counters; ++i) { 2844 mutex_init(&ibdev->qp1_proxy_lock[i]); 2845 allocated = 0; 2846 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2847 IB_LINK_LAYER_ETHERNET) { 2848 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2849 MLX4_RES_USAGE_DRIVER); 2850 /* if failed to allocate a new counter, use default */ 2851 if (err) 2852 counter_index = 2853 mlx4_get_default_counter_index(dev, 2854 i + 1); 2855 else 2856 allocated = 1; 2857 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2858 counter_index = mlx4_get_default_counter_index(dev, 2859 i + 1); 2860 } 2861 new_counter_index = kmalloc(sizeof(*new_counter_index), 2862 GFP_KERNEL); 2863 if (!new_counter_index) { 2864 if (allocated) 2865 mlx4_counter_free(ibdev->dev, counter_index); 2866 goto err_counter; 2867 } 2868 new_counter_index->index = counter_index; 2869 new_counter_index->allocated = allocated; 2870 list_add_tail(&new_counter_index->list, 2871 &ibdev->counters_table[i].counters_list); 2872 ibdev->counters_table[i].default_counter = counter_index; 2873 pr_info("counter index %d for port %d allocated %d\n", 2874 counter_index, i + 1, allocated); 2875 } 2876 if (mlx4_is_bonded(dev)) 2877 for (i = 1; i < ibdev->num_ports ; ++i) { 2878 new_counter_index = 2879 kmalloc(sizeof(struct counter_index), 2880 GFP_KERNEL); 2881 if (!new_counter_index) 2882 goto err_counter; 2883 new_counter_index->index = counter_index; 2884 new_counter_index->allocated = 0; 2885 list_add_tail(&new_counter_index->list, 2886 &ibdev->counters_table[i].counters_list); 2887 ibdev->counters_table[i].default_counter = 2888 counter_index; 2889 } 2890 2891 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2892 ib_num_ports++; 2893 2894 spin_lock_init(&ibdev->sm_lock); 2895 mutex_init(&ibdev->cap_mask_mutex); 2896 INIT_LIST_HEAD(&ibdev->qp_list); 2897 spin_lock_init(&ibdev->reset_flow_resource_lock); 2898 2899 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2900 ib_num_ports) { 2901 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2902 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2903 MLX4_IB_UC_STEER_QPN_ALIGN, 2904 &ibdev->steer_qpn_base, 0, 2905 MLX4_RES_USAGE_DRIVER); 2906 if (err) 2907 goto err_counter; 2908 2909 ibdev->ib_uc_qpns_bitmap = 2910 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) * 2911 sizeof(long), 2912 GFP_KERNEL); 2913 if (!ibdev->ib_uc_qpns_bitmap) 2914 goto err_steer_qp_release; 2915 2916 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2917 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2918 ibdev->steer_qpn_count); 2919 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2920 dev, ibdev->steer_qpn_base, 2921 ibdev->steer_qpn_base + 2922 ibdev->steer_qpn_count - 1); 2923 if (err) 2924 goto err_steer_free_bitmap; 2925 } else { 2926 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2927 ibdev->steer_qpn_count); 2928 } 2929 } 2930 2931 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2932 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2933 2934 if (mlx4_ib_alloc_diag_counters(ibdev)) 2935 goto err_steer_free_bitmap; 2936 2937 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4; 2938 if (ib_register_device(&ibdev->ib_dev, NULL)) 2939 goto err_diag_counters; 2940 2941 if (mlx4_ib_mad_init(ibdev)) 2942 goto err_reg; 2943 2944 if (mlx4_ib_init_sriov(ibdev)) 2945 goto err_mad; 2946 2947 if (!iboe->nb.notifier_call) { 2948 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2949 err = register_netdevice_notifier(&iboe->nb); 2950 if (err) { 2951 iboe->nb.notifier_call = NULL; 2952 goto err_notif; 2953 } 2954 } 2955 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2956 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2957 if (err) 2958 goto err_notif; 2959 } 2960 2961 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2962 if (device_create_file(&ibdev->ib_dev.dev, 2963 mlx4_class_attributes[j])) 2964 goto err_notif; 2965 } 2966 2967 ibdev->ib_active = true; 2968 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2969 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2970 &ibdev->ib_dev); 2971 2972 if (mlx4_is_mfunc(ibdev->dev)) 2973 init_pkeys(ibdev); 2974 2975 /* create paravirt contexts for any VFs which are active */ 2976 if (mlx4_is_master(ibdev->dev)) { 2977 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2978 if (j == mlx4_master_func_num(ibdev->dev)) 2979 continue; 2980 if (mlx4_is_slave_active(ibdev->dev, j)) 2981 do_slave_init(ibdev, j, 1); 2982 } 2983 } 2984 return ibdev; 2985 2986 err_notif: 2987 if (ibdev->iboe.nb.notifier_call) { 2988 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2989 pr_warn("failure unregistering notifier\n"); 2990 ibdev->iboe.nb.notifier_call = NULL; 2991 } 2992 flush_workqueue(wq); 2993 2994 mlx4_ib_close_sriov(ibdev); 2995 2996 err_mad: 2997 mlx4_ib_mad_cleanup(ibdev); 2998 2999 err_reg: 3000 ib_unregister_device(&ibdev->ib_dev); 3001 3002 err_diag_counters: 3003 mlx4_ib_diag_cleanup(ibdev); 3004 3005 err_steer_free_bitmap: 3006 kfree(ibdev->ib_uc_qpns_bitmap); 3007 3008 err_steer_qp_release: 3009 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3010 ibdev->steer_qpn_count); 3011 err_counter: 3012 for (i = 0; i < ibdev->num_ports; ++i) 3013 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 3014 3015 err_map: 3016 mlx4_ib_free_eqs(dev, ibdev); 3017 iounmap(ibdev->uar_map); 3018 3019 err_uar: 3020 mlx4_uar_free(dev, &ibdev->priv_uar); 3021 3022 err_pd: 3023 mlx4_pd_free(dev, ibdev->priv_pdn); 3024 3025 err_dealloc: 3026 ib_dealloc_device(&ibdev->ib_dev); 3027 3028 return NULL; 3029 } 3030 3031 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 3032 { 3033 int offset; 3034 3035 WARN_ON(!dev->ib_uc_qpns_bitmap); 3036 3037 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 3038 dev->steer_qpn_count, 3039 get_count_order(count)); 3040 if (offset < 0) 3041 return offset; 3042 3043 *qpn = dev->steer_qpn_base + offset; 3044 return 0; 3045 } 3046 3047 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 3048 { 3049 if (!qpn || 3050 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 3051 return; 3052 3053 BUG_ON(qpn < dev->steer_qpn_base); 3054 3055 bitmap_release_region(dev->ib_uc_qpns_bitmap, 3056 qpn - dev->steer_qpn_base, 3057 get_count_order(count)); 3058 } 3059 3060 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 3061 int is_attach) 3062 { 3063 int err; 3064 size_t flow_size; 3065 struct ib_flow_attr *flow = NULL; 3066 struct ib_flow_spec_ib *ib_spec; 3067 3068 if (is_attach) { 3069 flow_size = sizeof(struct ib_flow_attr) + 3070 sizeof(struct ib_flow_spec_ib); 3071 flow = kzalloc(flow_size, GFP_KERNEL); 3072 if (!flow) 3073 return -ENOMEM; 3074 flow->port = mqp->port; 3075 flow->num_of_specs = 1; 3076 flow->size = flow_size; 3077 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3078 ib_spec->type = IB_FLOW_SPEC_IB; 3079 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3080 /* Add an empty rule for IB L2 */ 3081 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3082 3083 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3084 IB_FLOW_DOMAIN_NIC, 3085 MLX4_FS_REGULAR, 3086 &mqp->reg_id); 3087 } else { 3088 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3089 } 3090 kfree(flow); 3091 return err; 3092 } 3093 3094 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3095 { 3096 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3097 int p; 3098 int i; 3099 3100 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3101 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3102 ibdev->ib_active = false; 3103 flush_workqueue(wq); 3104 3105 mlx4_ib_close_sriov(ibdev); 3106 mlx4_ib_mad_cleanup(ibdev); 3107 ib_unregister_device(&ibdev->ib_dev); 3108 mlx4_ib_diag_cleanup(ibdev); 3109 if (ibdev->iboe.nb.notifier_call) { 3110 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3111 pr_warn("failure unregistering notifier\n"); 3112 ibdev->iboe.nb.notifier_call = NULL; 3113 } 3114 3115 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3116 ibdev->steer_qpn_count); 3117 kfree(ibdev->ib_uc_qpns_bitmap); 3118 3119 iounmap(ibdev->uar_map); 3120 for (p = 0; p < ibdev->num_ports; ++p) 3121 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3122 3123 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3124 mlx4_CLOSE_PORT(dev, p); 3125 3126 mlx4_ib_free_eqs(dev, ibdev); 3127 3128 mlx4_uar_free(dev, &ibdev->priv_uar); 3129 mlx4_pd_free(dev, ibdev->priv_pdn); 3130 ib_dealloc_device(&ibdev->ib_dev); 3131 } 3132 3133 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3134 { 3135 struct mlx4_ib_demux_work **dm = NULL; 3136 struct mlx4_dev *dev = ibdev->dev; 3137 int i; 3138 unsigned long flags; 3139 struct mlx4_active_ports actv_ports; 3140 unsigned int ports; 3141 unsigned int first_port; 3142 3143 if (!mlx4_is_master(dev)) 3144 return; 3145 3146 actv_ports = mlx4_get_active_ports(dev, slave); 3147 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3148 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3149 3150 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3151 if (!dm) 3152 return; 3153 3154 for (i = 0; i < ports; i++) { 3155 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3156 if (!dm[i]) { 3157 while (--i >= 0) 3158 kfree(dm[i]); 3159 goto out; 3160 } 3161 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3162 dm[i]->port = first_port + i + 1; 3163 dm[i]->slave = slave; 3164 dm[i]->do_init = do_init; 3165 dm[i]->dev = ibdev; 3166 } 3167 /* initialize or tear down tunnel QPs for the slave */ 3168 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3169 if (!ibdev->sriov.is_going_down) { 3170 for (i = 0; i < ports; i++) 3171 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3172 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3173 } else { 3174 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3175 for (i = 0; i < ports; i++) 3176 kfree(dm[i]); 3177 } 3178 out: 3179 kfree(dm); 3180 return; 3181 } 3182 3183 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3184 { 3185 struct mlx4_ib_qp *mqp; 3186 unsigned long flags_qp; 3187 unsigned long flags_cq; 3188 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3189 struct list_head cq_notify_list; 3190 struct mlx4_cq *mcq; 3191 unsigned long flags; 3192 3193 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3194 INIT_LIST_HEAD(&cq_notify_list); 3195 3196 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3197 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3198 3199 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3200 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3201 if (mqp->sq.tail != mqp->sq.head) { 3202 send_mcq = to_mcq(mqp->ibqp.send_cq); 3203 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3204 if (send_mcq->mcq.comp && 3205 mqp->ibqp.send_cq->comp_handler) { 3206 if (!send_mcq->mcq.reset_notify_added) { 3207 send_mcq->mcq.reset_notify_added = 1; 3208 list_add_tail(&send_mcq->mcq.reset_notify, 3209 &cq_notify_list); 3210 } 3211 } 3212 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3213 } 3214 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3215 /* Now, handle the QP's receive queue */ 3216 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3217 /* no handling is needed for SRQ */ 3218 if (!mqp->ibqp.srq) { 3219 if (mqp->rq.tail != mqp->rq.head) { 3220 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3221 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3222 if (recv_mcq->mcq.comp && 3223 mqp->ibqp.recv_cq->comp_handler) { 3224 if (!recv_mcq->mcq.reset_notify_added) { 3225 recv_mcq->mcq.reset_notify_added = 1; 3226 list_add_tail(&recv_mcq->mcq.reset_notify, 3227 &cq_notify_list); 3228 } 3229 } 3230 spin_unlock_irqrestore(&recv_mcq->lock, 3231 flags_cq); 3232 } 3233 } 3234 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3235 } 3236 3237 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3238 mcq->comp(mcq); 3239 } 3240 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3241 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3242 } 3243 3244 static void handle_bonded_port_state_event(struct work_struct *work) 3245 { 3246 struct ib_event_work *ew = 3247 container_of(work, struct ib_event_work, work); 3248 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3249 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3250 int i; 3251 struct ib_event ibev; 3252 3253 kfree(ew); 3254 spin_lock_bh(&ibdev->iboe.lock); 3255 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3256 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3257 enum ib_port_state curr_port_state; 3258 3259 if (!curr_netdev) 3260 continue; 3261 3262 curr_port_state = 3263 (netif_running(curr_netdev) && 3264 netif_carrier_ok(curr_netdev)) ? 3265 IB_PORT_ACTIVE : IB_PORT_DOWN; 3266 3267 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3268 curr_port_state : IB_PORT_ACTIVE; 3269 } 3270 spin_unlock_bh(&ibdev->iboe.lock); 3271 3272 ibev.device = &ibdev->ib_dev; 3273 ibev.element.port_num = 1; 3274 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3275 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3276 3277 ib_dispatch_event(&ibev); 3278 } 3279 3280 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3281 { 3282 u64 sl2vl; 3283 int err; 3284 3285 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3286 if (err) { 3287 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3288 port, err); 3289 sl2vl = 0; 3290 } 3291 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3292 } 3293 3294 static void ib_sl2vl_update_work(struct work_struct *work) 3295 { 3296 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3297 struct mlx4_ib_dev *mdev = ew->ib_dev; 3298 int port = ew->port; 3299 3300 mlx4_ib_sl2vl_update(mdev, port); 3301 3302 kfree(ew); 3303 } 3304 3305 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3306 int port) 3307 { 3308 struct ib_event_work *ew; 3309 3310 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3311 if (ew) { 3312 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3313 ew->port = port; 3314 ew->ib_dev = ibdev; 3315 queue_work(wq, &ew->work); 3316 } 3317 } 3318 3319 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3320 enum mlx4_dev_event event, unsigned long param) 3321 { 3322 struct ib_event ibev; 3323 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3324 struct mlx4_eqe *eqe = NULL; 3325 struct ib_event_work *ew; 3326 int p = 0; 3327 3328 if (mlx4_is_bonded(dev) && 3329 ((event == MLX4_DEV_EVENT_PORT_UP) || 3330 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3331 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3332 if (!ew) 3333 return; 3334 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3335 ew->ib_dev = ibdev; 3336 queue_work(wq, &ew->work); 3337 return; 3338 } 3339 3340 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3341 eqe = (struct mlx4_eqe *)param; 3342 else 3343 p = (int) param; 3344 3345 switch (event) { 3346 case MLX4_DEV_EVENT_PORT_UP: 3347 if (p > ibdev->num_ports) 3348 return; 3349 if (!mlx4_is_slave(dev) && 3350 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3351 IB_LINK_LAYER_INFINIBAND) { 3352 if (mlx4_is_master(dev)) 3353 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3354 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3355 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3356 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3357 } 3358 ibev.event = IB_EVENT_PORT_ACTIVE; 3359 break; 3360 3361 case MLX4_DEV_EVENT_PORT_DOWN: 3362 if (p > ibdev->num_ports) 3363 return; 3364 ibev.event = IB_EVENT_PORT_ERR; 3365 break; 3366 3367 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3368 ibdev->ib_active = false; 3369 ibev.event = IB_EVENT_DEVICE_FATAL; 3370 mlx4_ib_handle_catas_error(ibdev); 3371 break; 3372 3373 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3374 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3375 if (!ew) 3376 break; 3377 3378 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3379 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3380 ew->ib_dev = ibdev; 3381 /* need to queue only for port owner, which uses GEN_EQE */ 3382 if (mlx4_is_master(dev)) 3383 queue_work(wq, &ew->work); 3384 else 3385 handle_port_mgmt_change_event(&ew->work); 3386 return; 3387 3388 case MLX4_DEV_EVENT_SLAVE_INIT: 3389 /* here, p is the slave id */ 3390 do_slave_init(ibdev, p, 1); 3391 if (mlx4_is_master(dev)) { 3392 int i; 3393 3394 for (i = 1; i <= ibdev->num_ports; i++) { 3395 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3396 == IB_LINK_LAYER_INFINIBAND) 3397 mlx4_ib_slave_alias_guid_event(ibdev, 3398 p, i, 3399 1); 3400 } 3401 } 3402 return; 3403 3404 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3405 if (mlx4_is_master(dev)) { 3406 int i; 3407 3408 for (i = 1; i <= ibdev->num_ports; i++) { 3409 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3410 == IB_LINK_LAYER_INFINIBAND) 3411 mlx4_ib_slave_alias_guid_event(ibdev, 3412 p, i, 3413 0); 3414 } 3415 } 3416 /* here, p is the slave id */ 3417 do_slave_init(ibdev, p, 0); 3418 return; 3419 3420 default: 3421 return; 3422 } 3423 3424 ibev.device = ibdev_ptr; 3425 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3426 3427 ib_dispatch_event(&ibev); 3428 } 3429 3430 static struct mlx4_interface mlx4_ib_interface = { 3431 .add = mlx4_ib_add, 3432 .remove = mlx4_ib_remove, 3433 .event = mlx4_ib_event, 3434 .protocol = MLX4_PROT_IB_IPV6, 3435 .flags = MLX4_INTFF_BONDING 3436 }; 3437 3438 static int __init mlx4_ib_init(void) 3439 { 3440 int err; 3441 3442 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3443 if (!wq) 3444 return -ENOMEM; 3445 3446 err = mlx4_ib_mcg_init(); 3447 if (err) 3448 goto clean_wq; 3449 3450 err = mlx4_register_interface(&mlx4_ib_interface); 3451 if (err) 3452 goto clean_mcg; 3453 3454 return 0; 3455 3456 clean_mcg: 3457 mlx4_ib_mcg_destroy(); 3458 3459 clean_wq: 3460 destroy_workqueue(wq); 3461 return err; 3462 } 3463 3464 static void __exit mlx4_ib_cleanup(void) 3465 { 3466 mlx4_unregister_interface(&mlx4_ib_interface); 3467 mlx4_ib_mcg_destroy(); 3468 destroy_workqueue(wq); 3469 } 3470 3471 module_init(mlx4_ib_init); 3472 module_exit(mlx4_ib_cleanup); 3473