1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 250 { 251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 252 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 253 struct mlx4_port_gid_table *port_gid_table; 254 int free = -1, found = -1; 255 int ret = 0; 256 int hw_update = 0; 257 int i; 258 struct gid_entry *gids = NULL; 259 260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 261 return -EINVAL; 262 263 if (attr->port_num > MLX4_MAX_PORTS) 264 return -EINVAL; 265 266 if (!context) 267 return -EINVAL; 268 269 port_gid_table = &iboe->gids[attr->port_num - 1]; 270 spin_lock_bh(&iboe->lock); 271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 272 if (!memcmp(&port_gid_table->gids[i].gid, 273 &attr->gid, sizeof(attr->gid)) && 274 port_gid_table->gids[i].gid_type == attr->gid_type) { 275 found = i; 276 break; 277 } 278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 279 free = i; /* HW has space */ 280 } 281 282 if (found < 0) { 283 if (free < 0) { 284 ret = -ENOSPC; 285 } else { 286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 287 if (!port_gid_table->gids[free].ctx) { 288 ret = -ENOMEM; 289 } else { 290 *context = port_gid_table->gids[free].ctx; 291 memcpy(&port_gid_table->gids[free].gid, 292 &attr->gid, sizeof(attr->gid)); 293 port_gid_table->gids[free].gid_type = attr->gid_type; 294 port_gid_table->gids[free].ctx->real_index = free; 295 port_gid_table->gids[free].ctx->refcount = 1; 296 hw_update = 1; 297 } 298 } 299 } else { 300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 301 *context = ctx; 302 ctx->refcount++; 303 } 304 if (!ret && hw_update) { 305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 306 GFP_ATOMIC); 307 if (!gids) { 308 ret = -ENOMEM; 309 } else { 310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 312 gids[i].gid_type = port_gid_table->gids[i].gid_type; 313 } 314 } 315 } 316 spin_unlock_bh(&iboe->lock); 317 318 if (!ret && hw_update) { 319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 320 kfree(gids); 321 } 322 323 return ret; 324 } 325 326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 327 { 328 struct gid_cache_context *ctx = *context; 329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 330 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 331 struct mlx4_port_gid_table *port_gid_table; 332 int ret = 0; 333 int hw_update = 0; 334 struct gid_entry *gids = NULL; 335 336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 337 return -EINVAL; 338 339 if (attr->port_num > MLX4_MAX_PORTS) 340 return -EINVAL; 341 342 port_gid_table = &iboe->gids[attr->port_num - 1]; 343 spin_lock_bh(&iboe->lock); 344 if (ctx) { 345 ctx->refcount--; 346 if (!ctx->refcount) { 347 unsigned int real_index = ctx->real_index; 348 349 memset(&port_gid_table->gids[real_index].gid, 0, 350 sizeof(port_gid_table->gids[real_index].gid)); 351 kfree(port_gid_table->gids[real_index].ctx); 352 port_gid_table->gids[real_index].ctx = NULL; 353 hw_update = 1; 354 } 355 } 356 if (!ret && hw_update) { 357 int i; 358 359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 360 GFP_ATOMIC); 361 if (!gids) { 362 ret = -ENOMEM; 363 } else { 364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 365 memcpy(&gids[i].gid, 366 &port_gid_table->gids[i].gid, 367 sizeof(union ib_gid)); 368 gids[i].gid_type = 369 port_gid_table->gids[i].gid_type; 370 } 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 const struct ib_gid_attr *attr) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 struct mlx4_port_gid_table *port_gid_table; 388 int real_index = -EINVAL; 389 int i; 390 unsigned long flags; 391 u8 port_num = attr->port_num; 392 393 if (port_num > MLX4_MAX_PORTS) 394 return -EINVAL; 395 396 if (mlx4_is_bonded(ibdev->dev)) 397 port_num = 1; 398 399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 400 return attr->index; 401 402 spin_lock_irqsave(&iboe->lock, flags); 403 port_gid_table = &iboe->gids[port_num - 1]; 404 405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 406 if (!memcmp(&port_gid_table->gids[i].gid, 407 &attr->gid, sizeof(attr->gid)) && 408 attr->gid_type == port_gid_table->gids[i].gid_type) { 409 ctx = port_gid_table->gids[i].ctx; 410 break; 411 } 412 if (ctx) 413 real_index = ctx->real_index; 414 spin_unlock_irqrestore(&iboe->lock, flags); 415 return real_index; 416 } 417 418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 419 sizeof(((type *)0)->fld) <= (sz)) 420 421 static int mlx4_ib_query_device(struct ib_device *ibdev, 422 struct ib_device_attr *props, 423 struct ib_udata *uhw) 424 { 425 struct mlx4_ib_dev *dev = to_mdev(ibdev); 426 struct ib_smp *in_mad = NULL; 427 struct ib_smp *out_mad = NULL; 428 int err; 429 int have_ib_ports; 430 struct mlx4_uverbs_ex_query_device cmd; 431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 432 struct mlx4_clock_params clock_params; 433 434 if (uhw->inlen) { 435 if (uhw->inlen < sizeof(cmd)) 436 return -EINVAL; 437 438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 439 if (err) 440 return err; 441 442 if (cmd.comp_mask) 443 return -EINVAL; 444 445 if (cmd.reserved) 446 return -EINVAL; 447 } 448 449 resp.response_length = offsetof(typeof(resp), response_length) + 450 sizeof(resp.response_length); 451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 453 err = -ENOMEM; 454 if (!in_mad || !out_mad) 455 goto out; 456 457 init_query_mad(in_mad); 458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 459 460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 461 1, NULL, NULL, in_mad, out_mad); 462 if (err) 463 goto out; 464 465 memset(props, 0, sizeof *props); 466 467 have_ib_ports = num_ib_ports(dev->dev); 468 469 props->fw_ver = dev->dev->caps.fw_ver; 470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 471 IB_DEVICE_PORT_ACTIVE_EVENT | 472 IB_DEVICE_SYS_IMAGE_GUID | 473 IB_DEVICE_RC_RNR_NAK_GEN | 474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 485 if (dev->dev->caps.max_gso_sz && 486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 488 props->device_cap_flags |= IB_DEVICE_UD_TSO; 489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 496 props->device_cap_flags |= IB_DEVICE_XRC; 497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 502 else 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 504 } 505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 507 508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 509 510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 511 0xffffff; 512 props->vendor_part_id = dev->dev->persist->pdev->device; 513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 515 516 props->max_mr_size = ~0ull; 517 props->page_size_cap = dev->dev->caps.page_size_cap; 518 props->max_qp = dev->dev->quotas.qp; 519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 520 props->max_send_sge = 521 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 522 props->max_recv_sge = 523 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 524 props->max_sge_rd = MLX4_MAX_SGE_RD; 525 props->max_cq = dev->dev->quotas.cq; 526 props->max_cqe = dev->dev->caps.max_cqes; 527 props->max_mr = dev->dev->quotas.mpt; 528 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 529 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 530 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 531 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 532 props->max_srq = dev->dev->quotas.srq; 533 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 534 props->max_srq_sge = dev->dev->caps.max_srq_sge; 535 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 536 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 537 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 538 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 539 props->masked_atomic_cap = props->atomic_cap; 540 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 541 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 542 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 543 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 544 props->max_mcast_grp; 545 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 546 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 547 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 548 props->max_ah = INT_MAX; 549 550 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 551 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 552 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 553 props->rss_caps.max_rwq_indirection_tables = 554 props->max_qp; 555 props->rss_caps.max_rwq_indirection_table_size = 556 dev->dev->caps.max_rss_tbl_sz; 557 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 558 props->max_wq_type_rq = props->max_qp; 559 } 560 561 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 562 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 563 } 564 565 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 566 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 567 568 if (!mlx4_is_slave(dev->dev)) 569 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 570 571 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 572 resp.response_length += sizeof(resp.hca_core_clock_offset); 573 if (!err && !mlx4_is_slave(dev->dev)) { 574 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 575 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 576 } 577 } 578 579 if (uhw->outlen >= resp.response_length + 580 sizeof(resp.max_inl_recv_sz)) { 581 resp.response_length += sizeof(resp.max_inl_recv_sz); 582 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 583 sizeof(struct mlx4_wqe_data_seg); 584 } 585 586 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 587 if (props->rss_caps.supported_qpts) { 588 resp.rss_caps.rx_hash_function = 589 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 590 591 resp.rss_caps.rx_hash_fields_mask = 592 MLX4_IB_RX_HASH_SRC_IPV4 | 593 MLX4_IB_RX_HASH_DST_IPV4 | 594 MLX4_IB_RX_HASH_SRC_IPV6 | 595 MLX4_IB_RX_HASH_DST_IPV6 | 596 MLX4_IB_RX_HASH_SRC_PORT_TCP | 597 MLX4_IB_RX_HASH_DST_PORT_TCP | 598 MLX4_IB_RX_HASH_SRC_PORT_UDP | 599 MLX4_IB_RX_HASH_DST_PORT_UDP; 600 601 if (dev->dev->caps.tunnel_offload_mode == 602 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 603 resp.rss_caps.rx_hash_fields_mask |= 604 MLX4_IB_RX_HASH_INNER; 605 } 606 resp.response_length = offsetof(typeof(resp), rss_caps) + 607 sizeof(resp.rss_caps); 608 } 609 610 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 611 if (dev->dev->caps.max_gso_sz && 612 ((mlx4_ib_port_link_layer(ibdev, 1) == 613 IB_LINK_LAYER_ETHERNET) || 614 (mlx4_ib_port_link_layer(ibdev, 2) == 615 IB_LINK_LAYER_ETHERNET))) { 616 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 617 resp.tso_caps.supported_qpts |= 618 1 << IB_QPT_RAW_PACKET; 619 } 620 resp.response_length = offsetof(typeof(resp), tso_caps) + 621 sizeof(resp.tso_caps); 622 } 623 624 if (uhw->outlen) { 625 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 626 if (err) 627 goto out; 628 } 629 out: 630 kfree(in_mad); 631 kfree(out_mad); 632 633 return err; 634 } 635 636 static enum rdma_link_layer 637 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 638 { 639 struct mlx4_dev *dev = to_mdev(device)->dev; 640 641 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 642 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 643 } 644 645 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 646 struct ib_port_attr *props, int netw_view) 647 { 648 struct ib_smp *in_mad = NULL; 649 struct ib_smp *out_mad = NULL; 650 int ext_active_speed; 651 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 652 int err = -ENOMEM; 653 654 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 655 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 656 if (!in_mad || !out_mad) 657 goto out; 658 659 init_query_mad(in_mad); 660 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 661 in_mad->attr_mod = cpu_to_be32(port); 662 663 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 664 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 665 666 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 667 in_mad, out_mad); 668 if (err) 669 goto out; 670 671 672 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 673 props->lmc = out_mad->data[34] & 0x7; 674 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 675 props->sm_sl = out_mad->data[36] & 0xf; 676 props->state = out_mad->data[32] & 0xf; 677 props->phys_state = out_mad->data[33] >> 4; 678 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 679 if (netw_view) 680 props->gid_tbl_len = out_mad->data[50]; 681 else 682 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 683 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 684 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 685 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 686 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 687 props->active_width = out_mad->data[31] & 0xf; 688 props->active_speed = out_mad->data[35] >> 4; 689 props->max_mtu = out_mad->data[41] & 0xf; 690 props->active_mtu = out_mad->data[36] >> 4; 691 props->subnet_timeout = out_mad->data[51] & 0x1f; 692 props->max_vl_num = out_mad->data[37] >> 4; 693 props->init_type_reply = out_mad->data[41] >> 4; 694 695 /* Check if extended speeds (EDR/FDR/...) are supported */ 696 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 697 ext_active_speed = out_mad->data[62] >> 4; 698 699 switch (ext_active_speed) { 700 case 1: 701 props->active_speed = IB_SPEED_FDR; 702 break; 703 case 2: 704 props->active_speed = IB_SPEED_EDR; 705 break; 706 } 707 } 708 709 /* If reported active speed is QDR, check if is FDR-10 */ 710 if (props->active_speed == IB_SPEED_QDR) { 711 init_query_mad(in_mad); 712 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 713 in_mad->attr_mod = cpu_to_be32(port); 714 715 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 716 NULL, NULL, in_mad, out_mad); 717 if (err) 718 goto out; 719 720 /* Checking LinkSpeedActive for FDR-10 */ 721 if (out_mad->data[15] & 0x1) 722 props->active_speed = IB_SPEED_FDR10; 723 } 724 725 /* Avoid wrong speed value returned by FW if the IB link is down. */ 726 if (props->state == IB_PORT_DOWN) 727 props->active_speed = IB_SPEED_SDR; 728 729 out: 730 kfree(in_mad); 731 kfree(out_mad); 732 return err; 733 } 734 735 static u8 state_to_phys_state(enum ib_port_state state) 736 { 737 return state == IB_PORT_ACTIVE ? 5 : 3; 738 } 739 740 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 741 struct ib_port_attr *props) 742 { 743 744 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 745 struct mlx4_ib_iboe *iboe = &mdev->iboe; 746 struct net_device *ndev; 747 enum ib_mtu tmp; 748 struct mlx4_cmd_mailbox *mailbox; 749 int err = 0; 750 int is_bonded = mlx4_is_bonded(mdev->dev); 751 752 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 753 if (IS_ERR(mailbox)) 754 return PTR_ERR(mailbox); 755 756 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 757 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 758 MLX4_CMD_WRAPPED); 759 if (err) 760 goto out; 761 762 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 763 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 764 IB_WIDTH_4X : IB_WIDTH_1X; 765 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 766 IB_SPEED_FDR : IB_SPEED_QDR; 767 props->port_cap_flags = IB_PORT_CM_SUP; 768 props->ip_gids = true; 769 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 770 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 771 props->pkey_tbl_len = 1; 772 props->max_mtu = IB_MTU_4096; 773 props->max_vl_num = 2; 774 props->state = IB_PORT_DOWN; 775 props->phys_state = state_to_phys_state(props->state); 776 props->active_mtu = IB_MTU_256; 777 spin_lock_bh(&iboe->lock); 778 ndev = iboe->netdevs[port - 1]; 779 if (ndev && is_bonded) { 780 rcu_read_lock(); /* required to get upper dev */ 781 ndev = netdev_master_upper_dev_get_rcu(ndev); 782 rcu_read_unlock(); 783 } 784 if (!ndev) 785 goto out_unlock; 786 787 tmp = iboe_get_mtu(ndev->mtu); 788 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 789 790 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 791 IB_PORT_ACTIVE : IB_PORT_DOWN; 792 props->phys_state = state_to_phys_state(props->state); 793 out_unlock: 794 spin_unlock_bh(&iboe->lock); 795 out: 796 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 797 return err; 798 } 799 800 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 801 struct ib_port_attr *props, int netw_view) 802 { 803 int err; 804 805 /* props being zeroed by the caller, avoid zeroing it here */ 806 807 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 808 ib_link_query_port(ibdev, port, props, netw_view) : 809 eth_link_query_port(ibdev, port, props); 810 811 return err; 812 } 813 814 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 815 struct ib_port_attr *props) 816 { 817 /* returns host view */ 818 return __mlx4_ib_query_port(ibdev, port, props, 0); 819 } 820 821 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 822 union ib_gid *gid, int netw_view) 823 { 824 struct ib_smp *in_mad = NULL; 825 struct ib_smp *out_mad = NULL; 826 int err = -ENOMEM; 827 struct mlx4_ib_dev *dev = to_mdev(ibdev); 828 int clear = 0; 829 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 830 831 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 832 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 833 if (!in_mad || !out_mad) 834 goto out; 835 836 init_query_mad(in_mad); 837 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 838 in_mad->attr_mod = cpu_to_be32(port); 839 840 if (mlx4_is_mfunc(dev->dev) && netw_view) 841 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 842 843 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 844 if (err) 845 goto out; 846 847 memcpy(gid->raw, out_mad->data + 8, 8); 848 849 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 850 if (index) { 851 /* For any index > 0, return the null guid */ 852 err = 0; 853 clear = 1; 854 goto out; 855 } 856 } 857 858 init_query_mad(in_mad); 859 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 860 in_mad->attr_mod = cpu_to_be32(index / 8); 861 862 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 863 NULL, NULL, in_mad, out_mad); 864 if (err) 865 goto out; 866 867 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 868 869 out: 870 if (clear) 871 memset(gid->raw + 8, 0, 8); 872 kfree(in_mad); 873 kfree(out_mad); 874 return err; 875 } 876 877 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 878 union ib_gid *gid) 879 { 880 if (rdma_protocol_ib(ibdev, port)) 881 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 882 return 0; 883 } 884 885 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 886 { 887 union sl2vl_tbl_to_u64 sl2vl64; 888 struct ib_smp *in_mad = NULL; 889 struct ib_smp *out_mad = NULL; 890 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 891 int err = -ENOMEM; 892 int jj; 893 894 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 895 *sl2vl_tbl = 0; 896 return 0; 897 } 898 899 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 900 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 901 if (!in_mad || !out_mad) 902 goto out; 903 904 init_query_mad(in_mad); 905 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 906 in_mad->attr_mod = 0; 907 908 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 909 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 910 911 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 912 in_mad, out_mad); 913 if (err) 914 goto out; 915 916 for (jj = 0; jj < 8; jj++) 917 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 918 *sl2vl_tbl = sl2vl64.sl64; 919 920 out: 921 kfree(in_mad); 922 kfree(out_mad); 923 return err; 924 } 925 926 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 927 { 928 u64 sl2vl; 929 int i; 930 int err; 931 932 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 933 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 934 continue; 935 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 936 if (err) { 937 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 938 i, err); 939 sl2vl = 0; 940 } 941 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 942 } 943 } 944 945 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 946 u16 *pkey, int netw_view) 947 { 948 struct ib_smp *in_mad = NULL; 949 struct ib_smp *out_mad = NULL; 950 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 951 int err = -ENOMEM; 952 953 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 954 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 955 if (!in_mad || !out_mad) 956 goto out; 957 958 init_query_mad(in_mad); 959 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 960 in_mad->attr_mod = cpu_to_be32(index / 32); 961 962 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 963 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 964 965 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 966 in_mad, out_mad); 967 if (err) 968 goto out; 969 970 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 971 972 out: 973 kfree(in_mad); 974 kfree(out_mad); 975 return err; 976 } 977 978 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 979 { 980 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 981 } 982 983 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 984 struct ib_device_modify *props) 985 { 986 struct mlx4_cmd_mailbox *mailbox; 987 unsigned long flags; 988 989 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 990 return -EOPNOTSUPP; 991 992 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 993 return 0; 994 995 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 996 return -EOPNOTSUPP; 997 998 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 999 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1000 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1001 1002 /* 1003 * If possible, pass node desc to FW, so it can generate 1004 * a 144 trap. If cmd fails, just ignore. 1005 */ 1006 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1007 if (IS_ERR(mailbox)) 1008 return 0; 1009 1010 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1011 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1012 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1013 1014 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1015 1016 return 0; 1017 } 1018 1019 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1020 u32 cap_mask) 1021 { 1022 struct mlx4_cmd_mailbox *mailbox; 1023 int err; 1024 1025 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1026 if (IS_ERR(mailbox)) 1027 return PTR_ERR(mailbox); 1028 1029 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1030 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1031 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1032 } else { 1033 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1034 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1035 } 1036 1037 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1038 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1039 MLX4_CMD_WRAPPED); 1040 1041 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1042 return err; 1043 } 1044 1045 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1046 struct ib_port_modify *props) 1047 { 1048 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1049 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1050 struct ib_port_attr attr; 1051 u32 cap_mask; 1052 int err; 1053 1054 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1055 * of whether port link layer is ETH or IB. For ETH ports, qkey 1056 * violations and port capabilities are not meaningful. 1057 */ 1058 if (is_eth) 1059 return 0; 1060 1061 mutex_lock(&mdev->cap_mask_mutex); 1062 1063 err = ib_query_port(ibdev, port, &attr); 1064 if (err) 1065 goto out; 1066 1067 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1068 ~props->clr_port_cap_mask; 1069 1070 err = mlx4_ib_SET_PORT(mdev, port, 1071 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1072 cap_mask); 1073 1074 out: 1075 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1076 return err; 1077 } 1078 1079 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1080 struct ib_udata *udata) 1081 { 1082 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1083 struct mlx4_ib_ucontext *context; 1084 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1085 struct mlx4_ib_alloc_ucontext_resp resp; 1086 int err; 1087 1088 if (!dev->ib_active) 1089 return ERR_PTR(-EAGAIN); 1090 1091 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1092 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1093 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1094 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1095 } else { 1096 resp.dev_caps = dev->dev->caps.userspace_caps; 1097 resp.qp_tab_size = dev->dev->caps.num_qps; 1098 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1099 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1100 resp.cqe_size = dev->dev->caps.cqe_size; 1101 } 1102 1103 context = kzalloc(sizeof(*context), GFP_KERNEL); 1104 if (!context) 1105 return ERR_PTR(-ENOMEM); 1106 1107 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1108 if (err) { 1109 kfree(context); 1110 return ERR_PTR(err); 1111 } 1112 1113 INIT_LIST_HEAD(&context->db_page_list); 1114 mutex_init(&context->db_page_mutex); 1115 1116 INIT_LIST_HEAD(&context->wqn_ranges_list); 1117 mutex_init(&context->wqn_ranges_mutex); 1118 1119 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1120 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1121 else 1122 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1123 1124 if (err) { 1125 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1126 kfree(context); 1127 return ERR_PTR(-EFAULT); 1128 } 1129 1130 return &context->ibucontext; 1131 } 1132 1133 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1134 { 1135 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1136 1137 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1138 kfree(context); 1139 1140 return 0; 1141 } 1142 1143 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1144 { 1145 } 1146 1147 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1148 { 1149 struct mlx4_ib_dev *dev = to_mdev(context->device); 1150 1151 switch (vma->vm_pgoff) { 1152 case 0: 1153 return rdma_user_mmap_io(context, vma, 1154 to_mucontext(context)->uar.pfn, 1155 PAGE_SIZE, 1156 pgprot_noncached(vma->vm_page_prot)); 1157 1158 case 1: 1159 if (dev->dev->caps.bf_reg_size == 0) 1160 return -EINVAL; 1161 return rdma_user_mmap_io( 1162 context, vma, 1163 to_mucontext(context)->uar.pfn + 1164 dev->dev->caps.num_uars, 1165 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot)); 1166 1167 case 3: { 1168 struct mlx4_clock_params params; 1169 int ret; 1170 1171 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1172 if (ret) 1173 return ret; 1174 1175 return rdma_user_mmap_io( 1176 context, vma, 1177 (pci_resource_start(dev->dev->persist->pdev, 1178 params.bar) + 1179 params.offset) >> 1180 PAGE_SHIFT, 1181 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot)); 1182 } 1183 1184 default: 1185 return -EINVAL; 1186 } 1187 } 1188 1189 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1190 struct ib_ucontext *context, 1191 struct ib_udata *udata) 1192 { 1193 struct mlx4_ib_pd *pd; 1194 int err; 1195 1196 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 1197 if (!pd) 1198 return ERR_PTR(-ENOMEM); 1199 1200 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1201 if (err) { 1202 kfree(pd); 1203 return ERR_PTR(err); 1204 } 1205 1206 if (context) 1207 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1208 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1209 kfree(pd); 1210 return ERR_PTR(-EFAULT); 1211 } 1212 return &pd->ibpd; 1213 } 1214 1215 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1216 { 1217 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1218 kfree(pd); 1219 1220 return 0; 1221 } 1222 1223 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1224 struct ib_ucontext *context, 1225 struct ib_udata *udata) 1226 { 1227 struct mlx4_ib_xrcd *xrcd; 1228 struct ib_cq_init_attr cq_attr = {}; 1229 int err; 1230 1231 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1232 return ERR_PTR(-ENOSYS); 1233 1234 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1235 if (!xrcd) 1236 return ERR_PTR(-ENOMEM); 1237 1238 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1239 if (err) 1240 goto err1; 1241 1242 xrcd->pd = ib_alloc_pd(ibdev, 0); 1243 if (IS_ERR(xrcd->pd)) { 1244 err = PTR_ERR(xrcd->pd); 1245 goto err2; 1246 } 1247 1248 cq_attr.cqe = 1; 1249 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1250 if (IS_ERR(xrcd->cq)) { 1251 err = PTR_ERR(xrcd->cq); 1252 goto err3; 1253 } 1254 1255 return &xrcd->ibxrcd; 1256 1257 err3: 1258 ib_dealloc_pd(xrcd->pd); 1259 err2: 1260 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1261 err1: 1262 kfree(xrcd); 1263 return ERR_PTR(err); 1264 } 1265 1266 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1267 { 1268 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1269 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1270 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1271 kfree(xrcd); 1272 1273 return 0; 1274 } 1275 1276 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1277 { 1278 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1279 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1280 struct mlx4_ib_gid_entry *ge; 1281 1282 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1283 if (!ge) 1284 return -ENOMEM; 1285 1286 ge->gid = *gid; 1287 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1288 ge->port = mqp->port; 1289 ge->added = 1; 1290 } 1291 1292 mutex_lock(&mqp->mutex); 1293 list_add_tail(&ge->list, &mqp->gid_list); 1294 mutex_unlock(&mqp->mutex); 1295 1296 return 0; 1297 } 1298 1299 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1300 struct mlx4_ib_counters *ctr_table) 1301 { 1302 struct counter_index *counter, *tmp_count; 1303 1304 mutex_lock(&ctr_table->mutex); 1305 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1306 list) { 1307 if (counter->allocated) 1308 mlx4_counter_free(ibdev->dev, counter->index); 1309 list_del(&counter->list); 1310 kfree(counter); 1311 } 1312 mutex_unlock(&ctr_table->mutex); 1313 } 1314 1315 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1316 union ib_gid *gid) 1317 { 1318 struct net_device *ndev; 1319 int ret = 0; 1320 1321 if (!mqp->port) 1322 return 0; 1323 1324 spin_lock_bh(&mdev->iboe.lock); 1325 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1326 if (ndev) 1327 dev_hold(ndev); 1328 spin_unlock_bh(&mdev->iboe.lock); 1329 1330 if (ndev) { 1331 ret = 1; 1332 dev_put(ndev); 1333 } 1334 1335 return ret; 1336 } 1337 1338 struct mlx4_ib_steering { 1339 struct list_head list; 1340 struct mlx4_flow_reg_id reg_id; 1341 union ib_gid gid; 1342 }; 1343 1344 #define LAST_ETH_FIELD vlan_tag 1345 #define LAST_IB_FIELD sl 1346 #define LAST_IPV4_FIELD dst_ip 1347 #define LAST_TCP_UDP_FIELD src_port 1348 1349 /* Field is the last supported field */ 1350 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1351 memchr_inv((void *)&filter.field +\ 1352 sizeof(filter.field), 0,\ 1353 sizeof(filter) -\ 1354 offsetof(typeof(filter), field) -\ 1355 sizeof(filter.field)) 1356 1357 static int parse_flow_attr(struct mlx4_dev *dev, 1358 u32 qp_num, 1359 union ib_flow_spec *ib_spec, 1360 struct _rule_hw *mlx4_spec) 1361 { 1362 enum mlx4_net_trans_rule_id type; 1363 1364 switch (ib_spec->type) { 1365 case IB_FLOW_SPEC_ETH: 1366 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1367 return -ENOTSUPP; 1368 1369 type = MLX4_NET_TRANS_RULE_ID_ETH; 1370 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1371 ETH_ALEN); 1372 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1373 ETH_ALEN); 1374 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1375 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1376 break; 1377 case IB_FLOW_SPEC_IB: 1378 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1379 return -ENOTSUPP; 1380 1381 type = MLX4_NET_TRANS_RULE_ID_IB; 1382 mlx4_spec->ib.l3_qpn = 1383 cpu_to_be32(qp_num); 1384 mlx4_spec->ib.qpn_mask = 1385 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1386 break; 1387 1388 1389 case IB_FLOW_SPEC_IPV4: 1390 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1391 return -ENOTSUPP; 1392 1393 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1394 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1395 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1396 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1397 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1398 break; 1399 1400 case IB_FLOW_SPEC_TCP: 1401 case IB_FLOW_SPEC_UDP: 1402 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1403 return -ENOTSUPP; 1404 1405 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1406 MLX4_NET_TRANS_RULE_ID_TCP : 1407 MLX4_NET_TRANS_RULE_ID_UDP; 1408 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1409 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1410 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1411 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1412 break; 1413 1414 default: 1415 return -EINVAL; 1416 } 1417 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1418 mlx4_hw_rule_sz(dev, type) < 0) 1419 return -EINVAL; 1420 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1421 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1422 return mlx4_hw_rule_sz(dev, type); 1423 } 1424 1425 struct default_rules { 1426 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1427 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1428 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1429 __u8 link_layer; 1430 }; 1431 static const struct default_rules default_table[] = { 1432 { 1433 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1434 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1435 .rules_create_list = {IB_FLOW_SPEC_IB}, 1436 .link_layer = IB_LINK_LAYER_INFINIBAND 1437 } 1438 }; 1439 1440 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1441 struct ib_flow_attr *flow_attr) 1442 { 1443 int i, j, k; 1444 void *ib_flow; 1445 const struct default_rules *pdefault_rules = default_table; 1446 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1447 1448 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1449 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1450 memset(&field_types, 0, sizeof(field_types)); 1451 1452 if (link_layer != pdefault_rules->link_layer) 1453 continue; 1454 1455 ib_flow = flow_attr + 1; 1456 /* we assume the specs are sorted */ 1457 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1458 j < flow_attr->num_of_specs; k++) { 1459 union ib_flow_spec *current_flow = 1460 (union ib_flow_spec *)ib_flow; 1461 1462 /* same layer but different type */ 1463 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1464 (pdefault_rules->mandatory_fields[k] & 1465 IB_FLOW_SPEC_LAYER_MASK)) && 1466 (current_flow->type != 1467 pdefault_rules->mandatory_fields[k])) 1468 goto out; 1469 1470 /* same layer, try match next one */ 1471 if (current_flow->type == 1472 pdefault_rules->mandatory_fields[k]) { 1473 j++; 1474 ib_flow += 1475 ((union ib_flow_spec *)ib_flow)->size; 1476 } 1477 } 1478 1479 ib_flow = flow_attr + 1; 1480 for (j = 0; j < flow_attr->num_of_specs; 1481 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1482 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1483 /* same layer and same type */ 1484 if (((union ib_flow_spec *)ib_flow)->type == 1485 pdefault_rules->mandatory_not_fields[k]) 1486 goto out; 1487 1488 return i; 1489 } 1490 out: 1491 return -1; 1492 } 1493 1494 static int __mlx4_ib_create_default_rules( 1495 struct mlx4_ib_dev *mdev, 1496 struct ib_qp *qp, 1497 const struct default_rules *pdefault_rules, 1498 struct _rule_hw *mlx4_spec) { 1499 int size = 0; 1500 int i; 1501 1502 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1503 int ret; 1504 union ib_flow_spec ib_spec; 1505 switch (pdefault_rules->rules_create_list[i]) { 1506 case 0: 1507 /* no rule */ 1508 continue; 1509 case IB_FLOW_SPEC_IB: 1510 ib_spec.type = IB_FLOW_SPEC_IB; 1511 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1512 1513 break; 1514 default: 1515 /* invalid rule */ 1516 return -EINVAL; 1517 } 1518 /* We must put empty rule, qpn is being ignored */ 1519 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1520 mlx4_spec); 1521 if (ret < 0) { 1522 pr_info("invalid parsing\n"); 1523 return -EINVAL; 1524 } 1525 1526 mlx4_spec = (void *)mlx4_spec + ret; 1527 size += ret; 1528 } 1529 return size; 1530 } 1531 1532 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1533 int domain, 1534 enum mlx4_net_trans_promisc_mode flow_type, 1535 u64 *reg_id) 1536 { 1537 int ret, i; 1538 int size = 0; 1539 void *ib_flow; 1540 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1541 struct mlx4_cmd_mailbox *mailbox; 1542 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1543 int default_flow; 1544 1545 static const u16 __mlx4_domain[] = { 1546 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1547 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1548 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1549 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1550 }; 1551 1552 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1553 pr_err("Invalid priority value %d\n", flow_attr->priority); 1554 return -EINVAL; 1555 } 1556 1557 if (domain >= IB_FLOW_DOMAIN_NUM) { 1558 pr_err("Invalid domain value %d\n", domain); 1559 return -EINVAL; 1560 } 1561 1562 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1563 return -EINVAL; 1564 1565 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1566 if (IS_ERR(mailbox)) 1567 return PTR_ERR(mailbox); 1568 ctrl = mailbox->buf; 1569 1570 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1571 flow_attr->priority); 1572 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1573 ctrl->port = flow_attr->port; 1574 ctrl->qpn = cpu_to_be32(qp->qp_num); 1575 1576 ib_flow = flow_attr + 1; 1577 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1578 /* Add default flows */ 1579 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1580 if (default_flow >= 0) { 1581 ret = __mlx4_ib_create_default_rules( 1582 mdev, qp, default_table + default_flow, 1583 mailbox->buf + size); 1584 if (ret < 0) { 1585 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1586 return -EINVAL; 1587 } 1588 size += ret; 1589 } 1590 for (i = 0; i < flow_attr->num_of_specs; i++) { 1591 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1592 mailbox->buf + size); 1593 if (ret < 0) { 1594 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1595 return -EINVAL; 1596 } 1597 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1598 size += ret; 1599 } 1600 1601 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1602 flow_attr->num_of_specs == 1) { 1603 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1604 enum ib_flow_spec_type header_spec = 1605 ((union ib_flow_spec *)(flow_attr + 1))->type; 1606 1607 if (header_spec == IB_FLOW_SPEC_ETH) 1608 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1609 } 1610 1611 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1612 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1613 MLX4_CMD_NATIVE); 1614 if (ret == -ENOMEM) 1615 pr_err("mcg table is full. Fail to register network rule.\n"); 1616 else if (ret == -ENXIO) 1617 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1618 else if (ret) 1619 pr_err("Invalid argument. Fail to register network rule.\n"); 1620 1621 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1622 return ret; 1623 } 1624 1625 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1626 { 1627 int err; 1628 err = mlx4_cmd(dev, reg_id, 0, 0, 1629 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1630 MLX4_CMD_NATIVE); 1631 if (err) 1632 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1633 reg_id); 1634 return err; 1635 } 1636 1637 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1638 u64 *reg_id) 1639 { 1640 void *ib_flow; 1641 union ib_flow_spec *ib_spec; 1642 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1643 int err = 0; 1644 1645 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1646 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1647 return 0; /* do nothing */ 1648 1649 ib_flow = flow_attr + 1; 1650 ib_spec = (union ib_flow_spec *)ib_flow; 1651 1652 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1653 return 0; /* do nothing */ 1654 1655 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1656 flow_attr->port, qp->qp_num, 1657 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1658 reg_id); 1659 return err; 1660 } 1661 1662 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1663 struct ib_flow_attr *flow_attr, 1664 enum mlx4_net_trans_promisc_mode *type) 1665 { 1666 int err = 0; 1667 1668 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1669 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1670 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1671 return -EOPNOTSUPP; 1672 } 1673 1674 if (flow_attr->num_of_specs == 0) { 1675 type[0] = MLX4_FS_MC_SNIFFER; 1676 type[1] = MLX4_FS_UC_SNIFFER; 1677 } else { 1678 union ib_flow_spec *ib_spec; 1679 1680 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1681 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1682 return -EINVAL; 1683 1684 /* if all is zero than MC and UC */ 1685 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1686 type[0] = MLX4_FS_MC_SNIFFER; 1687 type[1] = MLX4_FS_UC_SNIFFER; 1688 } else { 1689 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1690 ib_spec->eth.mask.dst_mac[1], 1691 ib_spec->eth.mask.dst_mac[2], 1692 ib_spec->eth.mask.dst_mac[3], 1693 ib_spec->eth.mask.dst_mac[4], 1694 ib_spec->eth.mask.dst_mac[5]}; 1695 1696 /* Above xor was only on MC bit, non empty mask is valid 1697 * only if this bit is set and rest are zero. 1698 */ 1699 if (!is_zero_ether_addr(&mac[0])) 1700 return -EINVAL; 1701 1702 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1703 type[0] = MLX4_FS_MC_SNIFFER; 1704 else 1705 type[0] = MLX4_FS_UC_SNIFFER; 1706 } 1707 } 1708 1709 return err; 1710 } 1711 1712 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1713 struct ib_flow_attr *flow_attr, 1714 int domain, struct ib_udata *udata) 1715 { 1716 int err = 0, i = 0, j = 0; 1717 struct mlx4_ib_flow *mflow; 1718 enum mlx4_net_trans_promisc_mode type[2]; 1719 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1720 int is_bonded = mlx4_is_bonded(dev); 1721 1722 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1723 return ERR_PTR(-EINVAL); 1724 1725 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1726 return ERR_PTR(-EOPNOTSUPP); 1727 1728 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1729 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1730 return ERR_PTR(-EOPNOTSUPP); 1731 1732 if (udata && 1733 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1734 return ERR_PTR(-EOPNOTSUPP); 1735 1736 memset(type, 0, sizeof(type)); 1737 1738 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1739 if (!mflow) { 1740 err = -ENOMEM; 1741 goto err_free; 1742 } 1743 1744 switch (flow_attr->type) { 1745 case IB_FLOW_ATTR_NORMAL: 1746 /* If dont trap flag (continue match) is set, under specific 1747 * condition traffic be replicated to given qp, 1748 * without stealing it 1749 */ 1750 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1751 err = mlx4_ib_add_dont_trap_rule(dev, 1752 flow_attr, 1753 type); 1754 if (err) 1755 goto err_free; 1756 } else { 1757 type[0] = MLX4_FS_REGULAR; 1758 } 1759 break; 1760 1761 case IB_FLOW_ATTR_ALL_DEFAULT: 1762 type[0] = MLX4_FS_ALL_DEFAULT; 1763 break; 1764 1765 case IB_FLOW_ATTR_MC_DEFAULT: 1766 type[0] = MLX4_FS_MC_DEFAULT; 1767 break; 1768 1769 case IB_FLOW_ATTR_SNIFFER: 1770 type[0] = MLX4_FS_MIRROR_RX_PORT; 1771 type[1] = MLX4_FS_MIRROR_SX_PORT; 1772 break; 1773 1774 default: 1775 err = -EINVAL; 1776 goto err_free; 1777 } 1778 1779 while (i < ARRAY_SIZE(type) && type[i]) { 1780 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1781 &mflow->reg_id[i].id); 1782 if (err) 1783 goto err_create_flow; 1784 if (is_bonded) { 1785 /* Application always sees one port so the mirror rule 1786 * must be on port #2 1787 */ 1788 flow_attr->port = 2; 1789 err = __mlx4_ib_create_flow(qp, flow_attr, 1790 domain, type[j], 1791 &mflow->reg_id[j].mirror); 1792 flow_attr->port = 1; 1793 if (err) 1794 goto err_create_flow; 1795 j++; 1796 } 1797 1798 i++; 1799 } 1800 1801 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1802 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1803 &mflow->reg_id[i].id); 1804 if (err) 1805 goto err_create_flow; 1806 1807 if (is_bonded) { 1808 flow_attr->port = 2; 1809 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1810 &mflow->reg_id[j].mirror); 1811 flow_attr->port = 1; 1812 if (err) 1813 goto err_create_flow; 1814 j++; 1815 } 1816 /* function to create mirror rule */ 1817 i++; 1818 } 1819 1820 return &mflow->ibflow; 1821 1822 err_create_flow: 1823 while (i) { 1824 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1825 mflow->reg_id[i].id); 1826 i--; 1827 } 1828 1829 while (j) { 1830 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1831 mflow->reg_id[j].mirror); 1832 j--; 1833 } 1834 err_free: 1835 kfree(mflow); 1836 return ERR_PTR(err); 1837 } 1838 1839 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1840 { 1841 int err, ret = 0; 1842 int i = 0; 1843 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1844 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1845 1846 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1847 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1848 if (err) 1849 ret = err; 1850 if (mflow->reg_id[i].mirror) { 1851 err = __mlx4_ib_destroy_flow(mdev->dev, 1852 mflow->reg_id[i].mirror); 1853 if (err) 1854 ret = err; 1855 } 1856 i++; 1857 } 1858 1859 kfree(mflow); 1860 return ret; 1861 } 1862 1863 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1864 { 1865 int err; 1866 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1867 struct mlx4_dev *dev = mdev->dev; 1868 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1869 struct mlx4_ib_steering *ib_steering = NULL; 1870 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1871 struct mlx4_flow_reg_id reg_id; 1872 1873 if (mdev->dev->caps.steering_mode == 1874 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1875 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1876 if (!ib_steering) 1877 return -ENOMEM; 1878 } 1879 1880 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1881 !!(mqp->flags & 1882 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1883 prot, ®_id.id); 1884 if (err) { 1885 pr_err("multicast attach op failed, err %d\n", err); 1886 goto err_malloc; 1887 } 1888 1889 reg_id.mirror = 0; 1890 if (mlx4_is_bonded(dev)) { 1891 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1892 (mqp->port == 1) ? 2 : 1, 1893 !!(mqp->flags & 1894 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1895 prot, ®_id.mirror); 1896 if (err) 1897 goto err_add; 1898 } 1899 1900 err = add_gid_entry(ibqp, gid); 1901 if (err) 1902 goto err_add; 1903 1904 if (ib_steering) { 1905 memcpy(ib_steering->gid.raw, gid->raw, 16); 1906 ib_steering->reg_id = reg_id; 1907 mutex_lock(&mqp->mutex); 1908 list_add(&ib_steering->list, &mqp->steering_rules); 1909 mutex_unlock(&mqp->mutex); 1910 } 1911 return 0; 1912 1913 err_add: 1914 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1915 prot, reg_id.id); 1916 if (reg_id.mirror) 1917 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1918 prot, reg_id.mirror); 1919 err_malloc: 1920 kfree(ib_steering); 1921 1922 return err; 1923 } 1924 1925 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 1926 { 1927 struct mlx4_ib_gid_entry *ge; 1928 struct mlx4_ib_gid_entry *tmp; 1929 struct mlx4_ib_gid_entry *ret = NULL; 1930 1931 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1932 if (!memcmp(raw, ge->gid.raw, 16)) { 1933 ret = ge; 1934 break; 1935 } 1936 } 1937 1938 return ret; 1939 } 1940 1941 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1942 { 1943 int err; 1944 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1945 struct mlx4_dev *dev = mdev->dev; 1946 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1947 struct net_device *ndev; 1948 struct mlx4_ib_gid_entry *ge; 1949 struct mlx4_flow_reg_id reg_id = {0, 0}; 1950 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1951 1952 if (mdev->dev->caps.steering_mode == 1953 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1954 struct mlx4_ib_steering *ib_steering; 1955 1956 mutex_lock(&mqp->mutex); 1957 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 1958 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 1959 list_del(&ib_steering->list); 1960 break; 1961 } 1962 } 1963 mutex_unlock(&mqp->mutex); 1964 if (&ib_steering->list == &mqp->steering_rules) { 1965 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 1966 return -EINVAL; 1967 } 1968 reg_id = ib_steering->reg_id; 1969 kfree(ib_steering); 1970 } 1971 1972 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1973 prot, reg_id.id); 1974 if (err) 1975 return err; 1976 1977 if (mlx4_is_bonded(dev)) { 1978 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1979 prot, reg_id.mirror); 1980 if (err) 1981 return err; 1982 } 1983 1984 mutex_lock(&mqp->mutex); 1985 ge = find_gid_entry(mqp, gid->raw); 1986 if (ge) { 1987 spin_lock_bh(&mdev->iboe.lock); 1988 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 1989 if (ndev) 1990 dev_hold(ndev); 1991 spin_unlock_bh(&mdev->iboe.lock); 1992 if (ndev) 1993 dev_put(ndev); 1994 list_del(&ge->list); 1995 kfree(ge); 1996 } else 1997 pr_warn("could not find mgid entry\n"); 1998 1999 mutex_unlock(&mqp->mutex); 2000 2001 return 0; 2002 } 2003 2004 static int init_node_data(struct mlx4_ib_dev *dev) 2005 { 2006 struct ib_smp *in_mad = NULL; 2007 struct ib_smp *out_mad = NULL; 2008 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2009 int err = -ENOMEM; 2010 2011 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2012 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2013 if (!in_mad || !out_mad) 2014 goto out; 2015 2016 init_query_mad(in_mad); 2017 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2018 if (mlx4_is_master(dev->dev)) 2019 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2020 2021 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2022 if (err) 2023 goto out; 2024 2025 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2026 2027 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2028 2029 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2030 if (err) 2031 goto out; 2032 2033 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2034 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2035 2036 out: 2037 kfree(in_mad); 2038 kfree(out_mad); 2039 return err; 2040 } 2041 2042 static ssize_t hca_type_show(struct device *device, 2043 struct device_attribute *attr, char *buf) 2044 { 2045 struct mlx4_ib_dev *dev = 2046 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2047 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2048 } 2049 static DEVICE_ATTR_RO(hca_type); 2050 2051 static ssize_t hw_rev_show(struct device *device, 2052 struct device_attribute *attr, char *buf) 2053 { 2054 struct mlx4_ib_dev *dev = 2055 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2056 return sprintf(buf, "%x\n", dev->dev->rev_id); 2057 } 2058 static DEVICE_ATTR_RO(hw_rev); 2059 2060 static ssize_t board_id_show(struct device *device, 2061 struct device_attribute *attr, char *buf) 2062 { 2063 struct mlx4_ib_dev *dev = 2064 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2065 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2066 dev->dev->board_id); 2067 } 2068 static DEVICE_ATTR_RO(board_id); 2069 2070 static struct attribute *mlx4_class_attributes[] = { 2071 &dev_attr_hw_rev.attr, 2072 &dev_attr_hca_type.attr, 2073 &dev_attr_board_id.attr, 2074 NULL 2075 }; 2076 2077 static const struct attribute_group mlx4_attr_group = { 2078 .attrs = mlx4_class_attributes, 2079 }; 2080 2081 struct diag_counter { 2082 const char *name; 2083 u32 offset; 2084 }; 2085 2086 #define DIAG_COUNTER(_name, _offset) \ 2087 { .name = #_name, .offset = _offset } 2088 2089 static const struct diag_counter diag_basic[] = { 2090 DIAG_COUNTER(rq_num_lle, 0x00), 2091 DIAG_COUNTER(sq_num_lle, 0x04), 2092 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2093 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2094 DIAG_COUNTER(rq_num_lpe, 0x18), 2095 DIAG_COUNTER(sq_num_lpe, 0x1C), 2096 DIAG_COUNTER(rq_num_wrfe, 0x20), 2097 DIAG_COUNTER(sq_num_wrfe, 0x24), 2098 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2099 DIAG_COUNTER(sq_num_bre, 0x34), 2100 DIAG_COUNTER(sq_num_rire, 0x44), 2101 DIAG_COUNTER(rq_num_rire, 0x48), 2102 DIAG_COUNTER(sq_num_rae, 0x4C), 2103 DIAG_COUNTER(rq_num_rae, 0x50), 2104 DIAG_COUNTER(sq_num_roe, 0x54), 2105 DIAG_COUNTER(sq_num_tree, 0x5C), 2106 DIAG_COUNTER(sq_num_rree, 0x64), 2107 DIAG_COUNTER(rq_num_rnr, 0x68), 2108 DIAG_COUNTER(sq_num_rnr, 0x6C), 2109 DIAG_COUNTER(rq_num_oos, 0x100), 2110 DIAG_COUNTER(sq_num_oos, 0x104), 2111 }; 2112 2113 static const struct diag_counter diag_ext[] = { 2114 DIAG_COUNTER(rq_num_dup, 0x130), 2115 DIAG_COUNTER(sq_num_to, 0x134), 2116 }; 2117 2118 static const struct diag_counter diag_device_only[] = { 2119 DIAG_COUNTER(num_cqovf, 0x1A0), 2120 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2121 }; 2122 2123 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2124 u8 port_num) 2125 { 2126 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2127 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2128 2129 if (!diag[!!port_num].name) 2130 return NULL; 2131 2132 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2133 diag[!!port_num].num_counters, 2134 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2135 } 2136 2137 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2138 struct rdma_hw_stats *stats, 2139 u8 port, int index) 2140 { 2141 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2142 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2143 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2144 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2145 int ret; 2146 int i; 2147 2148 ret = mlx4_query_diag_counters(dev->dev, 2149 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2150 diag[!!port].offset, hw_value, 2151 diag[!!port].num_counters, port); 2152 2153 if (ret) 2154 return ret; 2155 2156 for (i = 0; i < diag[!!port].num_counters; i++) 2157 stats->value[i] = hw_value[i]; 2158 2159 return diag[!!port].num_counters; 2160 } 2161 2162 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2163 const char ***name, 2164 u32 **offset, 2165 u32 *num, 2166 bool port) 2167 { 2168 u32 num_counters; 2169 2170 num_counters = ARRAY_SIZE(diag_basic); 2171 2172 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2173 num_counters += ARRAY_SIZE(diag_ext); 2174 2175 if (!port) 2176 num_counters += ARRAY_SIZE(diag_device_only); 2177 2178 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2179 if (!*name) 2180 return -ENOMEM; 2181 2182 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2183 if (!*offset) 2184 goto err_name; 2185 2186 *num = num_counters; 2187 2188 return 0; 2189 2190 err_name: 2191 kfree(*name); 2192 return -ENOMEM; 2193 } 2194 2195 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2196 const char **name, 2197 u32 *offset, 2198 bool port) 2199 { 2200 int i; 2201 int j; 2202 2203 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2204 name[i] = diag_basic[i].name; 2205 offset[i] = diag_basic[i].offset; 2206 } 2207 2208 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2209 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2210 name[j] = diag_ext[i].name; 2211 offset[j] = diag_ext[i].offset; 2212 } 2213 } 2214 2215 if (!port) { 2216 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2217 name[j] = diag_device_only[i].name; 2218 offset[j] = diag_device_only[i].offset; 2219 } 2220 } 2221 } 2222 2223 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2224 { 2225 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2226 int i; 2227 int ret; 2228 bool per_port = !!(ibdev->dev->caps.flags2 & 2229 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2230 2231 if (mlx4_is_slave(ibdev->dev)) 2232 return 0; 2233 2234 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2235 /* i == 1 means we are building port counters */ 2236 if (i && !per_port) 2237 continue; 2238 2239 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2240 &diag[i].offset, 2241 &diag[i].num_counters, i); 2242 if (ret) 2243 goto err_alloc; 2244 2245 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2246 diag[i].offset, i); 2247 } 2248 2249 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2250 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2251 2252 return 0; 2253 2254 err_alloc: 2255 if (i) { 2256 kfree(diag[i - 1].name); 2257 kfree(diag[i - 1].offset); 2258 } 2259 2260 return ret; 2261 } 2262 2263 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2264 { 2265 int i; 2266 2267 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2268 kfree(ibdev->diag_counters[i].offset); 2269 kfree(ibdev->diag_counters[i].name); 2270 } 2271 } 2272 2273 #define MLX4_IB_INVALID_MAC ((u64)-1) 2274 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2275 struct net_device *dev, 2276 int port) 2277 { 2278 u64 new_smac = 0; 2279 u64 release_mac = MLX4_IB_INVALID_MAC; 2280 struct mlx4_ib_qp *qp; 2281 2282 read_lock(&dev_base_lock); 2283 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2284 read_unlock(&dev_base_lock); 2285 2286 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2287 2288 /* no need for update QP1 and mac registration in non-SRIOV */ 2289 if (!mlx4_is_mfunc(ibdev->dev)) 2290 return; 2291 2292 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2293 qp = ibdev->qp1_proxy[port - 1]; 2294 if (qp) { 2295 int new_smac_index; 2296 u64 old_smac; 2297 struct mlx4_update_qp_params update_params; 2298 2299 mutex_lock(&qp->mutex); 2300 old_smac = qp->pri.smac; 2301 if (new_smac == old_smac) 2302 goto unlock; 2303 2304 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2305 2306 if (new_smac_index < 0) 2307 goto unlock; 2308 2309 update_params.smac_index = new_smac_index; 2310 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2311 &update_params)) { 2312 release_mac = new_smac; 2313 goto unlock; 2314 } 2315 /* if old port was zero, no mac was yet registered for this QP */ 2316 if (qp->pri.smac_port) 2317 release_mac = old_smac; 2318 qp->pri.smac = new_smac; 2319 qp->pri.smac_port = port; 2320 qp->pri.smac_index = new_smac_index; 2321 } 2322 2323 unlock: 2324 if (release_mac != MLX4_IB_INVALID_MAC) 2325 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2326 if (qp) 2327 mutex_unlock(&qp->mutex); 2328 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2329 } 2330 2331 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2332 struct net_device *dev, 2333 unsigned long event) 2334 2335 { 2336 struct mlx4_ib_iboe *iboe; 2337 int update_qps_port = -1; 2338 int port; 2339 2340 ASSERT_RTNL(); 2341 2342 iboe = &ibdev->iboe; 2343 2344 spin_lock_bh(&iboe->lock); 2345 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2346 2347 iboe->netdevs[port - 1] = 2348 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2349 2350 if (dev == iboe->netdevs[port - 1] && 2351 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2352 event == NETDEV_UP || event == NETDEV_CHANGE)) 2353 update_qps_port = port; 2354 2355 } 2356 spin_unlock_bh(&iboe->lock); 2357 2358 if (update_qps_port > 0) 2359 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2360 } 2361 2362 static int mlx4_ib_netdev_event(struct notifier_block *this, 2363 unsigned long event, void *ptr) 2364 { 2365 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2366 struct mlx4_ib_dev *ibdev; 2367 2368 if (!net_eq(dev_net(dev), &init_net)) 2369 return NOTIFY_DONE; 2370 2371 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2372 mlx4_ib_scan_netdevs(ibdev, dev, event); 2373 2374 return NOTIFY_DONE; 2375 } 2376 2377 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2378 { 2379 int port; 2380 int slave; 2381 int i; 2382 2383 if (mlx4_is_master(ibdev->dev)) { 2384 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2385 ++slave) { 2386 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2387 for (i = 0; 2388 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2389 ++i) { 2390 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2391 /* master has the identity virt2phys pkey mapping */ 2392 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2393 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2394 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2395 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2396 } 2397 } 2398 } 2399 /* initialize pkey cache */ 2400 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2401 for (i = 0; 2402 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2403 ++i) 2404 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2405 (i) ? 0 : 0xFFFF; 2406 } 2407 } 2408 } 2409 2410 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2411 { 2412 int i, j, eq = 0, total_eqs = 0; 2413 2414 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2415 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2416 if (!ibdev->eq_table) 2417 return; 2418 2419 for (i = 1; i <= dev->caps.num_ports; i++) { 2420 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2421 j++, total_eqs++) { 2422 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2423 continue; 2424 ibdev->eq_table[eq] = total_eqs; 2425 if (!mlx4_assign_eq(dev, i, 2426 &ibdev->eq_table[eq])) 2427 eq++; 2428 else 2429 ibdev->eq_table[eq] = -1; 2430 } 2431 } 2432 2433 for (i = eq; i < dev->caps.num_comp_vectors; 2434 ibdev->eq_table[i++] = -1) 2435 ; 2436 2437 /* Advertise the new number of EQs to clients */ 2438 ibdev->ib_dev.num_comp_vectors = eq; 2439 } 2440 2441 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2442 { 2443 int i; 2444 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2445 2446 /* no eqs were allocated */ 2447 if (!ibdev->eq_table) 2448 return; 2449 2450 /* Reset the advertised EQ number */ 2451 ibdev->ib_dev.num_comp_vectors = 0; 2452 2453 for (i = 0; i < total_eqs; i++) 2454 mlx4_release_eq(dev, ibdev->eq_table[i]); 2455 2456 kfree(ibdev->eq_table); 2457 ibdev->eq_table = NULL; 2458 } 2459 2460 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2461 struct ib_port_immutable *immutable) 2462 { 2463 struct ib_port_attr attr; 2464 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2465 int err; 2466 2467 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2468 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2469 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2470 } else { 2471 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2472 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2473 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2474 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2475 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2476 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2477 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2478 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2479 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2480 } 2481 2482 err = ib_query_port(ibdev, port_num, &attr); 2483 if (err) 2484 return err; 2485 2486 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2487 immutable->gid_tbl_len = attr.gid_tbl_len; 2488 2489 return 0; 2490 } 2491 2492 static void get_fw_ver_str(struct ib_device *device, char *str) 2493 { 2494 struct mlx4_ib_dev *dev = 2495 container_of(device, struct mlx4_ib_dev, ib_dev); 2496 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2497 (int) (dev->dev->caps.fw_ver >> 32), 2498 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2499 (int) dev->dev->caps.fw_ver & 0xffff); 2500 } 2501 2502 static void *mlx4_ib_add(struct mlx4_dev *dev) 2503 { 2504 struct mlx4_ib_dev *ibdev; 2505 int num_ports = 0; 2506 int i, j; 2507 int err; 2508 struct mlx4_ib_iboe *iboe; 2509 int ib_num_ports = 0; 2510 int num_req_counters; 2511 int allocated; 2512 u32 counter_index; 2513 struct counter_index *new_counter_index = NULL; 2514 2515 pr_info_once("%s", mlx4_ib_version); 2516 2517 num_ports = 0; 2518 mlx4_foreach_ib_transport_port(i, dev) 2519 num_ports++; 2520 2521 /* No point in registering a device with no ports... */ 2522 if (num_ports == 0) 2523 return NULL; 2524 2525 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2526 if (!ibdev) { 2527 dev_err(&dev->persist->pdev->dev, 2528 "Device struct alloc failed\n"); 2529 return NULL; 2530 } 2531 2532 iboe = &ibdev->iboe; 2533 2534 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2535 goto err_dealloc; 2536 2537 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2538 goto err_pd; 2539 2540 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2541 PAGE_SIZE); 2542 if (!ibdev->uar_map) 2543 goto err_uar; 2544 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2545 2546 ibdev->dev = dev; 2547 ibdev->bond_next_port = 0; 2548 2549 ibdev->ib_dev.owner = THIS_MODULE; 2550 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2551 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2552 ibdev->num_ports = num_ports; 2553 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2554 1 : ibdev->num_ports; 2555 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2556 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2557 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2558 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2559 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2560 2561 if (dev->caps.userspace_caps) 2562 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2563 else 2564 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2565 2566 ibdev->ib_dev.uverbs_cmd_mask = 2567 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2568 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2569 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2570 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2571 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2572 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2573 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2574 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2575 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2576 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2577 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2578 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2579 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2580 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2581 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2582 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2583 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2584 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2585 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2586 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2587 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2588 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2589 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2590 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2591 2592 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2593 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2594 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2595 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2596 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2597 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2598 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2599 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2600 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2601 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2602 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2603 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2604 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2605 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2606 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2607 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2608 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2609 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2610 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2611 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2612 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2613 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2614 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2615 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2616 ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq; 2617 ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq; 2618 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2619 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2620 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2621 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2622 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2623 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2624 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2625 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2626 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2627 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2628 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2629 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2630 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2631 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2632 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2633 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2634 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2635 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2636 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2637 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2638 2639 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2640 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2641 2642 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2643 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2644 IB_LINK_LAYER_ETHERNET) || 2645 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2646 IB_LINK_LAYER_ETHERNET))) { 2647 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2648 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2649 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2650 ibdev->ib_dev.create_rwq_ind_table = 2651 mlx4_ib_create_rwq_ind_table; 2652 ibdev->ib_dev.destroy_rwq_ind_table = 2653 mlx4_ib_destroy_rwq_ind_table; 2654 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2655 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2656 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2657 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2658 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2659 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2660 } 2661 2662 if (!mlx4_is_slave(ibdev->dev)) { 2663 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2664 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2665 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2666 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2667 } 2668 2669 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2670 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2671 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2672 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2673 2674 ibdev->ib_dev.uverbs_cmd_mask |= 2675 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2676 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2677 } 2678 2679 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2680 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2681 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2682 ibdev->ib_dev.uverbs_cmd_mask |= 2683 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2684 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2685 } 2686 2687 if (check_flow_steering_support(dev)) { 2688 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2689 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2690 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2691 2692 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2693 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2694 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2695 } 2696 2697 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2698 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2699 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2700 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2701 2702 mlx4_ib_alloc_eqs(dev, ibdev); 2703 2704 spin_lock_init(&iboe->lock); 2705 2706 if (init_node_data(ibdev)) 2707 goto err_map; 2708 mlx4_init_sl2vl_tbl(ibdev); 2709 2710 for (i = 0; i < ibdev->num_ports; ++i) { 2711 mutex_init(&ibdev->counters_table[i].mutex); 2712 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2713 } 2714 2715 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2716 for (i = 0; i < num_req_counters; ++i) { 2717 mutex_init(&ibdev->qp1_proxy_lock[i]); 2718 allocated = 0; 2719 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2720 IB_LINK_LAYER_ETHERNET) { 2721 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2722 MLX4_RES_USAGE_DRIVER); 2723 /* if failed to allocate a new counter, use default */ 2724 if (err) 2725 counter_index = 2726 mlx4_get_default_counter_index(dev, 2727 i + 1); 2728 else 2729 allocated = 1; 2730 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2731 counter_index = mlx4_get_default_counter_index(dev, 2732 i + 1); 2733 } 2734 new_counter_index = kmalloc(sizeof(*new_counter_index), 2735 GFP_KERNEL); 2736 if (!new_counter_index) { 2737 if (allocated) 2738 mlx4_counter_free(ibdev->dev, counter_index); 2739 goto err_counter; 2740 } 2741 new_counter_index->index = counter_index; 2742 new_counter_index->allocated = allocated; 2743 list_add_tail(&new_counter_index->list, 2744 &ibdev->counters_table[i].counters_list); 2745 ibdev->counters_table[i].default_counter = counter_index; 2746 pr_info("counter index %d for port %d allocated %d\n", 2747 counter_index, i + 1, allocated); 2748 } 2749 if (mlx4_is_bonded(dev)) 2750 for (i = 1; i < ibdev->num_ports ; ++i) { 2751 new_counter_index = 2752 kmalloc(sizeof(struct counter_index), 2753 GFP_KERNEL); 2754 if (!new_counter_index) 2755 goto err_counter; 2756 new_counter_index->index = counter_index; 2757 new_counter_index->allocated = 0; 2758 list_add_tail(&new_counter_index->list, 2759 &ibdev->counters_table[i].counters_list); 2760 ibdev->counters_table[i].default_counter = 2761 counter_index; 2762 } 2763 2764 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2765 ib_num_ports++; 2766 2767 spin_lock_init(&ibdev->sm_lock); 2768 mutex_init(&ibdev->cap_mask_mutex); 2769 INIT_LIST_HEAD(&ibdev->qp_list); 2770 spin_lock_init(&ibdev->reset_flow_resource_lock); 2771 2772 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2773 ib_num_ports) { 2774 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2775 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2776 MLX4_IB_UC_STEER_QPN_ALIGN, 2777 &ibdev->steer_qpn_base, 0, 2778 MLX4_RES_USAGE_DRIVER); 2779 if (err) 2780 goto err_counter; 2781 2782 ibdev->ib_uc_qpns_bitmap = 2783 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2784 sizeof(long), 2785 GFP_KERNEL); 2786 if (!ibdev->ib_uc_qpns_bitmap) 2787 goto err_steer_qp_release; 2788 2789 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2790 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2791 ibdev->steer_qpn_count); 2792 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2793 dev, ibdev->steer_qpn_base, 2794 ibdev->steer_qpn_base + 2795 ibdev->steer_qpn_count - 1); 2796 if (err) 2797 goto err_steer_free_bitmap; 2798 } else { 2799 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2800 ibdev->steer_qpn_count); 2801 } 2802 } 2803 2804 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2805 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2806 2807 if (mlx4_ib_alloc_diag_counters(ibdev)) 2808 goto err_steer_free_bitmap; 2809 2810 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group); 2811 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4; 2812 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d", NULL)) 2813 goto err_diag_counters; 2814 2815 if (mlx4_ib_mad_init(ibdev)) 2816 goto err_reg; 2817 2818 if (mlx4_ib_init_sriov(ibdev)) 2819 goto err_mad; 2820 2821 if (!iboe->nb.notifier_call) { 2822 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2823 err = register_netdevice_notifier(&iboe->nb); 2824 if (err) { 2825 iboe->nb.notifier_call = NULL; 2826 goto err_notif; 2827 } 2828 } 2829 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2830 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2831 if (err) 2832 goto err_notif; 2833 } 2834 2835 ibdev->ib_active = true; 2836 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2837 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2838 &ibdev->ib_dev); 2839 2840 if (mlx4_is_mfunc(ibdev->dev)) 2841 init_pkeys(ibdev); 2842 2843 /* create paravirt contexts for any VFs which are active */ 2844 if (mlx4_is_master(ibdev->dev)) { 2845 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2846 if (j == mlx4_master_func_num(ibdev->dev)) 2847 continue; 2848 if (mlx4_is_slave_active(ibdev->dev, j)) 2849 do_slave_init(ibdev, j, 1); 2850 } 2851 } 2852 return ibdev; 2853 2854 err_notif: 2855 if (ibdev->iboe.nb.notifier_call) { 2856 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2857 pr_warn("failure unregistering notifier\n"); 2858 ibdev->iboe.nb.notifier_call = NULL; 2859 } 2860 flush_workqueue(wq); 2861 2862 mlx4_ib_close_sriov(ibdev); 2863 2864 err_mad: 2865 mlx4_ib_mad_cleanup(ibdev); 2866 2867 err_reg: 2868 ib_unregister_device(&ibdev->ib_dev); 2869 2870 err_diag_counters: 2871 mlx4_ib_diag_cleanup(ibdev); 2872 2873 err_steer_free_bitmap: 2874 kfree(ibdev->ib_uc_qpns_bitmap); 2875 2876 err_steer_qp_release: 2877 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2878 ibdev->steer_qpn_count); 2879 err_counter: 2880 for (i = 0; i < ibdev->num_ports; ++i) 2881 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2882 2883 err_map: 2884 mlx4_ib_free_eqs(dev, ibdev); 2885 iounmap(ibdev->uar_map); 2886 2887 err_uar: 2888 mlx4_uar_free(dev, &ibdev->priv_uar); 2889 2890 err_pd: 2891 mlx4_pd_free(dev, ibdev->priv_pdn); 2892 2893 err_dealloc: 2894 ib_dealloc_device(&ibdev->ib_dev); 2895 2896 return NULL; 2897 } 2898 2899 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2900 { 2901 int offset; 2902 2903 WARN_ON(!dev->ib_uc_qpns_bitmap); 2904 2905 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2906 dev->steer_qpn_count, 2907 get_count_order(count)); 2908 if (offset < 0) 2909 return offset; 2910 2911 *qpn = dev->steer_qpn_base + offset; 2912 return 0; 2913 } 2914 2915 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 2916 { 2917 if (!qpn || 2918 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 2919 return; 2920 2921 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 2922 qpn, dev->steer_qpn_base)) 2923 /* not supposed to be here */ 2924 return; 2925 2926 bitmap_release_region(dev->ib_uc_qpns_bitmap, 2927 qpn - dev->steer_qpn_base, 2928 get_count_order(count)); 2929 } 2930 2931 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 2932 int is_attach) 2933 { 2934 int err; 2935 size_t flow_size; 2936 struct ib_flow_attr *flow = NULL; 2937 struct ib_flow_spec_ib *ib_spec; 2938 2939 if (is_attach) { 2940 flow_size = sizeof(struct ib_flow_attr) + 2941 sizeof(struct ib_flow_spec_ib); 2942 flow = kzalloc(flow_size, GFP_KERNEL); 2943 if (!flow) 2944 return -ENOMEM; 2945 flow->port = mqp->port; 2946 flow->num_of_specs = 1; 2947 flow->size = flow_size; 2948 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 2949 ib_spec->type = IB_FLOW_SPEC_IB; 2950 ib_spec->size = sizeof(struct ib_flow_spec_ib); 2951 /* Add an empty rule for IB L2 */ 2952 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 2953 2954 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 2955 IB_FLOW_DOMAIN_NIC, 2956 MLX4_FS_REGULAR, 2957 &mqp->reg_id); 2958 } else { 2959 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 2960 } 2961 kfree(flow); 2962 return err; 2963 } 2964 2965 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 2966 { 2967 struct mlx4_ib_dev *ibdev = ibdev_ptr; 2968 int p; 2969 int i; 2970 2971 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2972 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 2973 ibdev->ib_active = false; 2974 flush_workqueue(wq); 2975 2976 mlx4_ib_close_sriov(ibdev); 2977 mlx4_ib_mad_cleanup(ibdev); 2978 ib_unregister_device(&ibdev->ib_dev); 2979 mlx4_ib_diag_cleanup(ibdev); 2980 if (ibdev->iboe.nb.notifier_call) { 2981 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2982 pr_warn("failure unregistering notifier\n"); 2983 ibdev->iboe.nb.notifier_call = NULL; 2984 } 2985 2986 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2987 ibdev->steer_qpn_count); 2988 kfree(ibdev->ib_uc_qpns_bitmap); 2989 2990 iounmap(ibdev->uar_map); 2991 for (p = 0; p < ibdev->num_ports; ++p) 2992 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 2993 2994 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 2995 mlx4_CLOSE_PORT(dev, p); 2996 2997 mlx4_ib_free_eqs(dev, ibdev); 2998 2999 mlx4_uar_free(dev, &ibdev->priv_uar); 3000 mlx4_pd_free(dev, ibdev->priv_pdn); 3001 ib_dealloc_device(&ibdev->ib_dev); 3002 } 3003 3004 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3005 { 3006 struct mlx4_ib_demux_work **dm = NULL; 3007 struct mlx4_dev *dev = ibdev->dev; 3008 int i; 3009 unsigned long flags; 3010 struct mlx4_active_ports actv_ports; 3011 unsigned int ports; 3012 unsigned int first_port; 3013 3014 if (!mlx4_is_master(dev)) 3015 return; 3016 3017 actv_ports = mlx4_get_active_ports(dev, slave); 3018 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3019 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3020 3021 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3022 if (!dm) 3023 return; 3024 3025 for (i = 0; i < ports; i++) { 3026 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3027 if (!dm[i]) { 3028 while (--i >= 0) 3029 kfree(dm[i]); 3030 goto out; 3031 } 3032 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3033 dm[i]->port = first_port + i + 1; 3034 dm[i]->slave = slave; 3035 dm[i]->do_init = do_init; 3036 dm[i]->dev = ibdev; 3037 } 3038 /* initialize or tear down tunnel QPs for the slave */ 3039 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3040 if (!ibdev->sriov.is_going_down) { 3041 for (i = 0; i < ports; i++) 3042 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3043 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3044 } else { 3045 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3046 for (i = 0; i < ports; i++) 3047 kfree(dm[i]); 3048 } 3049 out: 3050 kfree(dm); 3051 return; 3052 } 3053 3054 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3055 { 3056 struct mlx4_ib_qp *mqp; 3057 unsigned long flags_qp; 3058 unsigned long flags_cq; 3059 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3060 struct list_head cq_notify_list; 3061 struct mlx4_cq *mcq; 3062 unsigned long flags; 3063 3064 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3065 INIT_LIST_HEAD(&cq_notify_list); 3066 3067 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3068 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3069 3070 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3071 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3072 if (mqp->sq.tail != mqp->sq.head) { 3073 send_mcq = to_mcq(mqp->ibqp.send_cq); 3074 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3075 if (send_mcq->mcq.comp && 3076 mqp->ibqp.send_cq->comp_handler) { 3077 if (!send_mcq->mcq.reset_notify_added) { 3078 send_mcq->mcq.reset_notify_added = 1; 3079 list_add_tail(&send_mcq->mcq.reset_notify, 3080 &cq_notify_list); 3081 } 3082 } 3083 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3084 } 3085 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3086 /* Now, handle the QP's receive queue */ 3087 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3088 /* no handling is needed for SRQ */ 3089 if (!mqp->ibqp.srq) { 3090 if (mqp->rq.tail != mqp->rq.head) { 3091 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3092 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3093 if (recv_mcq->mcq.comp && 3094 mqp->ibqp.recv_cq->comp_handler) { 3095 if (!recv_mcq->mcq.reset_notify_added) { 3096 recv_mcq->mcq.reset_notify_added = 1; 3097 list_add_tail(&recv_mcq->mcq.reset_notify, 3098 &cq_notify_list); 3099 } 3100 } 3101 spin_unlock_irqrestore(&recv_mcq->lock, 3102 flags_cq); 3103 } 3104 } 3105 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3106 } 3107 3108 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3109 mcq->comp(mcq); 3110 } 3111 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3112 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3113 } 3114 3115 static void handle_bonded_port_state_event(struct work_struct *work) 3116 { 3117 struct ib_event_work *ew = 3118 container_of(work, struct ib_event_work, work); 3119 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3120 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3121 int i; 3122 struct ib_event ibev; 3123 3124 kfree(ew); 3125 spin_lock_bh(&ibdev->iboe.lock); 3126 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3127 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3128 enum ib_port_state curr_port_state; 3129 3130 if (!curr_netdev) 3131 continue; 3132 3133 curr_port_state = 3134 (netif_running(curr_netdev) && 3135 netif_carrier_ok(curr_netdev)) ? 3136 IB_PORT_ACTIVE : IB_PORT_DOWN; 3137 3138 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3139 curr_port_state : IB_PORT_ACTIVE; 3140 } 3141 spin_unlock_bh(&ibdev->iboe.lock); 3142 3143 ibev.device = &ibdev->ib_dev; 3144 ibev.element.port_num = 1; 3145 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3146 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3147 3148 ib_dispatch_event(&ibev); 3149 } 3150 3151 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3152 { 3153 u64 sl2vl; 3154 int err; 3155 3156 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3157 if (err) { 3158 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3159 port, err); 3160 sl2vl = 0; 3161 } 3162 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3163 } 3164 3165 static void ib_sl2vl_update_work(struct work_struct *work) 3166 { 3167 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3168 struct mlx4_ib_dev *mdev = ew->ib_dev; 3169 int port = ew->port; 3170 3171 mlx4_ib_sl2vl_update(mdev, port); 3172 3173 kfree(ew); 3174 } 3175 3176 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3177 int port) 3178 { 3179 struct ib_event_work *ew; 3180 3181 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3182 if (ew) { 3183 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3184 ew->port = port; 3185 ew->ib_dev = ibdev; 3186 queue_work(wq, &ew->work); 3187 } 3188 } 3189 3190 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3191 enum mlx4_dev_event event, unsigned long param) 3192 { 3193 struct ib_event ibev; 3194 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3195 struct mlx4_eqe *eqe = NULL; 3196 struct ib_event_work *ew; 3197 int p = 0; 3198 3199 if (mlx4_is_bonded(dev) && 3200 ((event == MLX4_DEV_EVENT_PORT_UP) || 3201 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3202 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3203 if (!ew) 3204 return; 3205 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3206 ew->ib_dev = ibdev; 3207 queue_work(wq, &ew->work); 3208 return; 3209 } 3210 3211 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3212 eqe = (struct mlx4_eqe *)param; 3213 else 3214 p = (int) param; 3215 3216 switch (event) { 3217 case MLX4_DEV_EVENT_PORT_UP: 3218 if (p > ibdev->num_ports) 3219 return; 3220 if (!mlx4_is_slave(dev) && 3221 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3222 IB_LINK_LAYER_INFINIBAND) { 3223 if (mlx4_is_master(dev)) 3224 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3225 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3226 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3227 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3228 } 3229 ibev.event = IB_EVENT_PORT_ACTIVE; 3230 break; 3231 3232 case MLX4_DEV_EVENT_PORT_DOWN: 3233 if (p > ibdev->num_ports) 3234 return; 3235 ibev.event = IB_EVENT_PORT_ERR; 3236 break; 3237 3238 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3239 ibdev->ib_active = false; 3240 ibev.event = IB_EVENT_DEVICE_FATAL; 3241 mlx4_ib_handle_catas_error(ibdev); 3242 break; 3243 3244 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3245 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3246 if (!ew) 3247 break; 3248 3249 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3250 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3251 ew->ib_dev = ibdev; 3252 /* need to queue only for port owner, which uses GEN_EQE */ 3253 if (mlx4_is_master(dev)) 3254 queue_work(wq, &ew->work); 3255 else 3256 handle_port_mgmt_change_event(&ew->work); 3257 return; 3258 3259 case MLX4_DEV_EVENT_SLAVE_INIT: 3260 /* here, p is the slave id */ 3261 do_slave_init(ibdev, p, 1); 3262 if (mlx4_is_master(dev)) { 3263 int i; 3264 3265 for (i = 1; i <= ibdev->num_ports; i++) { 3266 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3267 == IB_LINK_LAYER_INFINIBAND) 3268 mlx4_ib_slave_alias_guid_event(ibdev, 3269 p, i, 3270 1); 3271 } 3272 } 3273 return; 3274 3275 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3276 if (mlx4_is_master(dev)) { 3277 int i; 3278 3279 for (i = 1; i <= ibdev->num_ports; i++) { 3280 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3281 == IB_LINK_LAYER_INFINIBAND) 3282 mlx4_ib_slave_alias_guid_event(ibdev, 3283 p, i, 3284 0); 3285 } 3286 } 3287 /* here, p is the slave id */ 3288 do_slave_init(ibdev, p, 0); 3289 return; 3290 3291 default: 3292 return; 3293 } 3294 3295 ibev.device = ibdev_ptr; 3296 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3297 3298 ib_dispatch_event(&ibev); 3299 } 3300 3301 static struct mlx4_interface mlx4_ib_interface = { 3302 .add = mlx4_ib_add, 3303 .remove = mlx4_ib_remove, 3304 .event = mlx4_ib_event, 3305 .protocol = MLX4_PROT_IB_IPV6, 3306 .flags = MLX4_INTFF_BONDING 3307 }; 3308 3309 static int __init mlx4_ib_init(void) 3310 { 3311 int err; 3312 3313 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3314 if (!wq) 3315 return -ENOMEM; 3316 3317 err = mlx4_ib_mcg_init(); 3318 if (err) 3319 goto clean_wq; 3320 3321 err = mlx4_register_interface(&mlx4_ib_interface); 3322 if (err) 3323 goto clean_mcg; 3324 3325 return 0; 3326 3327 clean_mcg: 3328 mlx4_ib_mcg_destroy(); 3329 3330 clean_wq: 3331 destroy_workqueue(wq); 3332 return err; 3333 } 3334 3335 static void __exit mlx4_ib_cleanup(void) 3336 { 3337 mlx4_unregister_interface(&mlx4_ib_interface); 3338 mlx4_ib_mcg_destroy(); 3339 destroy_workqueue(wq); 3340 } 3341 3342 module_init(mlx4_ib_init); 3343 module_exit(mlx4_ib_cleanup); 3344