1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_mad.h> 34 #include <rdma/ib_smi.h> 35 #include <rdma/ib_sa.h> 36 #include <rdma/ib_cache.h> 37 38 #include <linux/random.h> 39 #include <linux/mlx4/cmd.h> 40 #include <linux/gfp.h> 41 #include <rdma/ib_pma.h> 42 #include <linux/ip.h> 43 #include <net/ipv6.h> 44 45 #include <linux/mlx4/driver.h> 46 #include "mlx4_ib.h" 47 48 enum { 49 MLX4_IB_VENDOR_CLASS1 = 0x9, 50 MLX4_IB_VENDOR_CLASS2 = 0xa 51 }; 52 53 #define MLX4_TUN_SEND_WRID_SHIFT 34 54 #define MLX4_TUN_QPN_SHIFT 32 55 #define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT) 56 #define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT) 57 58 #define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1) 59 #define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3) 60 61 /* Port mgmt change event handling */ 62 63 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr) 64 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask) 65 #define NUM_IDX_IN_PKEY_TBL_BLK 32 66 #define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */ 67 #define GUID_TBL_BLK_NUM_ENTRIES 8 68 #define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES) 69 70 struct mlx4_mad_rcv_buf { 71 struct ib_grh grh; 72 u8 payload[256]; 73 } __packed; 74 75 struct mlx4_mad_snd_buf { 76 u8 payload[256]; 77 } __packed; 78 79 struct mlx4_tunnel_mad { 80 struct ib_grh grh; 81 struct mlx4_ib_tunnel_header hdr; 82 struct ib_mad mad; 83 } __packed; 84 85 struct mlx4_rcv_tunnel_mad { 86 struct mlx4_rcv_tunnel_hdr hdr; 87 struct ib_grh grh; 88 struct ib_mad mad; 89 } __packed; 90 91 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num); 92 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num); 93 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 94 int block, u32 change_bitmap); 95 96 __be64 mlx4_ib_gen_node_guid(void) 97 { 98 #define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40)) 99 return cpu_to_be64(NODE_GUID_HI | prandom_u32()); 100 } 101 102 __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx) 103 { 104 return cpu_to_be64(atomic_inc_return(&ctx->tid)) | 105 cpu_to_be64(0xff00000000000000LL); 106 } 107 108 int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, 109 int port, const struct ib_wc *in_wc, 110 const struct ib_grh *in_grh, 111 const void *in_mad, void *response_mad) 112 { 113 struct mlx4_cmd_mailbox *inmailbox, *outmailbox; 114 void *inbox; 115 int err; 116 u32 in_modifier = port; 117 u8 op_modifier = 0; 118 119 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 120 if (IS_ERR(inmailbox)) 121 return PTR_ERR(inmailbox); 122 inbox = inmailbox->buf; 123 124 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 125 if (IS_ERR(outmailbox)) { 126 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 127 return PTR_ERR(outmailbox); 128 } 129 130 memcpy(inbox, in_mad, 256); 131 132 /* 133 * Key check traps can't be generated unless we have in_wc to 134 * tell us where to send the trap. 135 */ 136 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc) 137 op_modifier |= 0x1; 138 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc) 139 op_modifier |= 0x2; 140 if (mlx4_is_mfunc(dev->dev) && 141 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc)) 142 op_modifier |= 0x8; 143 144 if (in_wc) { 145 struct { 146 __be32 my_qpn; 147 u32 reserved1; 148 __be32 rqpn; 149 u8 sl; 150 u8 g_path; 151 u16 reserved2[2]; 152 __be16 pkey; 153 u32 reserved3[11]; 154 u8 grh[40]; 155 } *ext_info; 156 157 memset(inbox + 256, 0, 256); 158 ext_info = inbox + 256; 159 160 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num); 161 ext_info->rqpn = cpu_to_be32(in_wc->src_qp); 162 ext_info->sl = in_wc->sl << 4; 163 ext_info->g_path = in_wc->dlid_path_bits | 164 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 165 ext_info->pkey = cpu_to_be16(in_wc->pkey_index); 166 167 if (in_grh) 168 memcpy(ext_info->grh, in_grh, 40); 169 170 op_modifier |= 0x4; 171 172 in_modifier |= ib_lid_cpu16(in_wc->slid) << 16; 173 } 174 175 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier, 176 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier, 177 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, 178 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED); 179 180 if (!err) 181 memcpy(response_mad, outmailbox->buf, 256); 182 183 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 184 mlx4_free_cmd_mailbox(dev->dev, outmailbox); 185 186 return err; 187 } 188 189 static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl) 190 { 191 struct ib_ah *new_ah; 192 struct rdma_ah_attr ah_attr; 193 unsigned long flags; 194 195 if (!dev->send_agent[port_num - 1][0]) 196 return; 197 198 memset(&ah_attr, 0, sizeof ah_attr); 199 ah_attr.type = rdma_ah_find_type(&dev->ib_dev, port_num); 200 rdma_ah_set_dlid(&ah_attr, lid); 201 rdma_ah_set_sl(&ah_attr, sl); 202 rdma_ah_set_port_num(&ah_attr, port_num); 203 204 new_ah = rdma_create_ah(dev->send_agent[port_num - 1][0]->qp->pd, 205 &ah_attr, 0); 206 if (IS_ERR(new_ah)) 207 return; 208 209 spin_lock_irqsave(&dev->sm_lock, flags); 210 if (dev->sm_ah[port_num - 1]) 211 rdma_destroy_ah(dev->sm_ah[port_num - 1], 0); 212 dev->sm_ah[port_num - 1] = new_ah; 213 spin_unlock_irqrestore(&dev->sm_lock, flags); 214 } 215 216 /* 217 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can 218 * synthesize LID change, Client-Rereg, GID change, and P_Key change events. 219 */ 220 static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad, 221 u16 prev_lid) 222 { 223 struct ib_port_info *pinfo; 224 u16 lid; 225 __be16 *base; 226 u32 bn, pkey_change_bitmap; 227 int i; 228 229 230 struct mlx4_ib_dev *dev = to_mdev(ibdev); 231 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 232 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 233 mad->mad_hdr.method == IB_MGMT_METHOD_SET) 234 switch (mad->mad_hdr.attr_id) { 235 case IB_SMP_ATTR_PORT_INFO: 236 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 237 return; 238 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data; 239 lid = be16_to_cpu(pinfo->lid); 240 241 update_sm_ah(dev, port_num, 242 be16_to_cpu(pinfo->sm_lid), 243 pinfo->neighbormtu_mastersmsl & 0xf); 244 245 if (pinfo->clientrereg_resv_subnetto & 0x80) 246 handle_client_rereg_event(dev, port_num); 247 248 if (prev_lid != lid) 249 handle_lid_change_event(dev, port_num); 250 break; 251 252 case IB_SMP_ATTR_PKEY_TABLE: 253 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 254 return; 255 if (!mlx4_is_mfunc(dev->dev)) { 256 mlx4_ib_dispatch_event(dev, port_num, 257 IB_EVENT_PKEY_CHANGE); 258 break; 259 } 260 261 /* at this point, we are running in the master. 262 * Slaves do not receive SMPs. 263 */ 264 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF; 265 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]); 266 pkey_change_bitmap = 0; 267 for (i = 0; i < 32; i++) { 268 pr_debug("PKEY[%d] = x%x\n", 269 i + bn*32, be16_to_cpu(base[i])); 270 if (be16_to_cpu(base[i]) != 271 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) { 272 pkey_change_bitmap |= (1 << i); 273 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] = 274 be16_to_cpu(base[i]); 275 } 276 } 277 pr_debug("PKEY Change event: port=%d, " 278 "block=0x%x, change_bitmap=0x%x\n", 279 port_num, bn, pkey_change_bitmap); 280 281 if (pkey_change_bitmap) { 282 mlx4_ib_dispatch_event(dev, port_num, 283 IB_EVENT_PKEY_CHANGE); 284 if (!dev->sriov.is_going_down) 285 __propagate_pkey_ev(dev, port_num, bn, 286 pkey_change_bitmap); 287 } 288 break; 289 290 case IB_SMP_ATTR_GUID_INFO: 291 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 292 return; 293 /* paravirtualized master's guid is guid 0 -- does not change */ 294 if (!mlx4_is_master(dev->dev)) 295 mlx4_ib_dispatch_event(dev, port_num, 296 IB_EVENT_GID_CHANGE); 297 /*if master, notify relevant slaves*/ 298 if (mlx4_is_master(dev->dev) && 299 !dev->sriov.is_going_down) { 300 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod); 301 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num, 302 (u8 *)(&((struct ib_smp *)mad)->data)); 303 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num, 304 (u8 *)(&((struct ib_smp *)mad)->data)); 305 } 306 break; 307 308 case IB_SMP_ATTR_SL_TO_VL_TABLE: 309 /* cache sl to vl mapping changes for use in 310 * filling QP1 LRH VL field when sending packets 311 */ 312 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV && 313 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT) 314 return; 315 if (!mlx4_is_slave(dev->dev)) { 316 union sl2vl_tbl_to_u64 sl2vl64; 317 int jj; 318 319 for (jj = 0; jj < 8; jj++) { 320 sl2vl64.sl8[jj] = ((struct ib_smp *)mad)->data[jj]; 321 pr_debug("port %u, sl2vl[%d] = %02x\n", 322 port_num, jj, sl2vl64.sl8[jj]); 323 } 324 atomic64_set(&dev->sl2vl[port_num - 1], sl2vl64.sl64); 325 } 326 break; 327 328 default: 329 break; 330 } 331 } 332 333 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 334 int block, u32 change_bitmap) 335 { 336 int i, ix, slave, err; 337 int have_event = 0; 338 339 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) { 340 if (slave == mlx4_master_func_num(dev->dev)) 341 continue; 342 if (!mlx4_is_slave_active(dev->dev, slave)) 343 continue; 344 345 have_event = 0; 346 for (i = 0; i < 32; i++) { 347 if (!(change_bitmap & (1 << i))) 348 continue; 349 for (ix = 0; 350 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) { 351 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1] 352 [ix] == i + 32 * block) { 353 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num); 354 pr_debug("propagate_pkey_ev: slave %d," 355 " port %d, ix %d (%d)\n", 356 slave, port_num, ix, err); 357 have_event = 1; 358 break; 359 } 360 } 361 if (have_event) 362 break; 363 } 364 } 365 } 366 367 static void node_desc_override(struct ib_device *dev, 368 struct ib_mad *mad) 369 { 370 unsigned long flags; 371 372 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 373 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 374 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP && 375 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) { 376 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags); 377 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 378 IB_DEVICE_NODE_DESC_MAX); 379 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags); 380 } 381 } 382 383 static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad) 384 { 385 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED; 386 struct ib_mad_send_buf *send_buf; 387 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn]; 388 int ret; 389 unsigned long flags; 390 391 if (agent) { 392 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 393 IB_MGMT_MAD_DATA, GFP_ATOMIC, 394 IB_MGMT_BASE_VERSION); 395 if (IS_ERR(send_buf)) 396 return; 397 /* 398 * We rely here on the fact that MLX QPs don't use the 399 * address handle after the send is posted (this is 400 * wrong following the IB spec strictly, but we know 401 * it's OK for our devices). 402 */ 403 spin_lock_irqsave(&dev->sm_lock, flags); 404 memcpy(send_buf->mad, mad, sizeof *mad); 405 if ((send_buf->ah = dev->sm_ah[port_num - 1])) 406 ret = ib_post_send_mad(send_buf, NULL); 407 else 408 ret = -EINVAL; 409 spin_unlock_irqrestore(&dev->sm_lock, flags); 410 411 if (ret) 412 ib_free_send_mad(send_buf); 413 } 414 } 415 416 static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave, 417 struct ib_sa_mad *sa_mad) 418 { 419 int ret = 0; 420 421 /* dispatch to different sa handlers */ 422 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 423 case IB_SA_ATTR_MC_MEMBER_REC: 424 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad); 425 break; 426 default: 427 break; 428 } 429 return ret; 430 } 431 432 int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid) 433 { 434 struct mlx4_ib_dev *dev = to_mdev(ibdev); 435 int i; 436 437 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 438 if (dev->sriov.demux[port - 1].guid_cache[i] == guid) 439 return i; 440 } 441 return -1; 442 } 443 444 445 static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave, 446 u8 port, u16 pkey, u16 *ix) 447 { 448 int i, ret; 449 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF; 450 u16 slot_pkey; 451 452 if (slave == mlx4_master_func_num(dev->dev)) 453 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix); 454 455 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1; 456 457 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) { 458 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix) 459 continue; 460 461 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i]; 462 463 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey); 464 if (ret) 465 continue; 466 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) { 467 if (slot_pkey & 0x8000) { 468 *ix = (u16) pkey_ix; 469 return 0; 470 } else { 471 /* take first partial pkey index found */ 472 if (partial_ix == 0xFF) 473 partial_ix = pkey_ix; 474 } 475 } 476 } 477 478 if (partial_ix < 0xFF) { 479 *ix = (u16) partial_ix; 480 return 0; 481 } 482 483 return -EINVAL; 484 } 485 486 static int get_gids_from_l3_hdr(struct ib_grh *grh, union ib_gid *sgid, 487 union ib_gid *dgid) 488 { 489 int version = ib_get_rdma_header_version((const union rdma_network_hdr *)grh); 490 enum rdma_network_type net_type; 491 492 if (version == 4) 493 net_type = RDMA_NETWORK_IPV4; 494 else if (version == 6) 495 net_type = RDMA_NETWORK_IPV6; 496 else 497 return -EINVAL; 498 499 return ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type, 500 sgid, dgid); 501 } 502 503 int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, 504 enum ib_qp_type dest_qpt, struct ib_wc *wc, 505 struct ib_grh *grh, struct ib_mad *mad) 506 { 507 struct ib_sge list; 508 struct ib_ud_wr wr; 509 const struct ib_send_wr *bad_wr; 510 struct mlx4_ib_demux_pv_ctx *tun_ctx; 511 struct mlx4_ib_demux_pv_qp *tun_qp; 512 struct mlx4_rcv_tunnel_mad *tun_mad; 513 struct rdma_ah_attr attr; 514 struct ib_ah *ah; 515 struct ib_qp *src_qp = NULL; 516 unsigned tun_tx_ix = 0; 517 int dqpn; 518 int ret = 0; 519 u16 tun_pkey_ix; 520 u16 cached_pkey; 521 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 522 523 if (dest_qpt > IB_QPT_GSI) 524 return -EINVAL; 525 526 tun_ctx = dev->sriov.demux[port-1].tun[slave]; 527 528 /* check if proxy qp created */ 529 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE) 530 return -EAGAIN; 531 532 if (!dest_qpt) 533 tun_qp = &tun_ctx->qp[0]; 534 else 535 tun_qp = &tun_ctx->qp[1]; 536 537 /* compute P_Key index to put in tunnel header for slave */ 538 if (dest_qpt) { 539 u16 pkey_ix; 540 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey); 541 if (ret) 542 return -EINVAL; 543 544 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix); 545 if (ret) 546 return -EINVAL; 547 tun_pkey_ix = pkey_ix; 548 } else 549 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 550 551 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1; 552 553 /* get tunnel tx data buf for slave */ 554 src_qp = tun_qp->qp; 555 556 /* create ah. Just need an empty one with the port num for the post send. 557 * The driver will set the force loopback bit in post_send */ 558 memset(&attr, 0, sizeof attr); 559 attr.type = rdma_ah_find_type(&dev->ib_dev, port); 560 561 rdma_ah_set_port_num(&attr, port); 562 if (is_eth) { 563 union ib_gid sgid; 564 union ib_gid dgid; 565 566 if (get_gids_from_l3_hdr(grh, &sgid, &dgid)) 567 return -EINVAL; 568 rdma_ah_set_grh(&attr, &dgid, 0, 0, 0, 0); 569 } 570 ah = rdma_create_ah(tun_ctx->pd, &attr, 0); 571 if (IS_ERR(ah)) 572 return -ENOMEM; 573 574 /* allocate tunnel tx buf after pass failure returns */ 575 spin_lock(&tun_qp->tx_lock); 576 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >= 577 (MLX4_NUM_TUNNEL_BUFS - 1)) 578 ret = -EAGAIN; 579 else 580 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 581 spin_unlock(&tun_qp->tx_lock); 582 if (ret) 583 goto end; 584 585 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr); 586 if (tun_qp->tx_ring[tun_tx_ix].ah) 587 rdma_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah, 0); 588 tun_qp->tx_ring[tun_tx_ix].ah = ah; 589 ib_dma_sync_single_for_cpu(&dev->ib_dev, 590 tun_qp->tx_ring[tun_tx_ix].buf.map, 591 sizeof (struct mlx4_rcv_tunnel_mad), 592 DMA_TO_DEVICE); 593 594 /* copy over to tunnel buffer */ 595 if (grh) 596 memcpy(&tun_mad->grh, grh, sizeof *grh); 597 memcpy(&tun_mad->mad, mad, sizeof *mad); 598 599 /* adjust tunnel data */ 600 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix); 601 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF); 602 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0; 603 604 if (is_eth) { 605 u16 vlan = 0; 606 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan, 607 NULL)) { 608 /* VST mode */ 609 if (vlan != wc->vlan_id) 610 /* Packet vlan is not the VST-assigned vlan. 611 * Drop the packet. 612 */ 613 goto out; 614 else 615 /* Remove the vlan tag before forwarding 616 * the packet to the VF. 617 */ 618 vlan = 0xffff; 619 } else { 620 vlan = wc->vlan_id; 621 } 622 623 tun_mad->hdr.sl_vid = cpu_to_be16(vlan); 624 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4); 625 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2); 626 } else { 627 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12); 628 tun_mad->hdr.slid_mac_47_32 = ib_lid_be16(wc->slid); 629 } 630 631 ib_dma_sync_single_for_device(&dev->ib_dev, 632 tun_qp->tx_ring[tun_tx_ix].buf.map, 633 sizeof (struct mlx4_rcv_tunnel_mad), 634 DMA_TO_DEVICE); 635 636 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map; 637 list.length = sizeof (struct mlx4_rcv_tunnel_mad); 638 list.lkey = tun_ctx->pd->local_dma_lkey; 639 640 wr.ah = ah; 641 wr.port_num = port; 642 wr.remote_qkey = IB_QP_SET_QKEY; 643 wr.remote_qpn = dqpn; 644 wr.wr.next = NULL; 645 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt); 646 wr.wr.sg_list = &list; 647 wr.wr.num_sge = 1; 648 wr.wr.opcode = IB_WR_SEND; 649 wr.wr.send_flags = IB_SEND_SIGNALED; 650 651 ret = ib_post_send(src_qp, &wr.wr, &bad_wr); 652 if (!ret) 653 return 0; 654 out: 655 spin_lock(&tun_qp->tx_lock); 656 tun_qp->tx_ix_tail++; 657 spin_unlock(&tun_qp->tx_lock); 658 tun_qp->tx_ring[tun_tx_ix].ah = NULL; 659 end: 660 rdma_destroy_ah(ah, 0); 661 return ret; 662 } 663 664 static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, 665 struct ib_wc *wc, struct ib_grh *grh, 666 struct ib_mad *mad) 667 { 668 struct mlx4_ib_dev *dev = to_mdev(ibdev); 669 int err, other_port; 670 int slave = -1; 671 u8 *slave_id; 672 int is_eth = 0; 673 674 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND) 675 is_eth = 0; 676 else 677 is_eth = 1; 678 679 if (is_eth) { 680 union ib_gid dgid; 681 union ib_gid sgid; 682 683 if (get_gids_from_l3_hdr(grh, &sgid, &dgid)) 684 return -EINVAL; 685 if (!(wc->wc_flags & IB_WC_GRH)) { 686 mlx4_ib_warn(ibdev, "RoCE grh not present.\n"); 687 return -EINVAL; 688 } 689 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) { 690 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); 691 return -EINVAL; 692 } 693 err = mlx4_get_slave_from_roce_gid(dev->dev, port, dgid.raw, &slave); 694 if (err && mlx4_is_mf_bonded(dev->dev)) { 695 other_port = (port == 1) ? 2 : 1; 696 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, dgid.raw, &slave); 697 if (!err) { 698 port = other_port; 699 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n", 700 slave, grh->dgid.raw, port, other_port); 701 } 702 } 703 if (err) { 704 mlx4_ib_warn(ibdev, "failed matching grh\n"); 705 return -ENOENT; 706 } 707 if (slave >= dev->dev->caps.sqp_demux) { 708 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 709 slave, dev->dev->caps.sqp_demux); 710 return -ENOENT; 711 } 712 713 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad)) 714 return 0; 715 716 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 717 if (err) 718 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 719 slave, err); 720 return 0; 721 } 722 723 /* Initially assume that this mad is for us */ 724 slave = mlx4_master_func_num(dev->dev); 725 726 /* See if the slave id is encoded in a response mad */ 727 if (mad->mad_hdr.method & 0x80) { 728 slave_id = (u8 *) &mad->mad_hdr.tid; 729 slave = *slave_id; 730 if (slave != 255) /*255 indicates the dom0*/ 731 *slave_id = 0; /* remap tid */ 732 } 733 734 /* If a grh is present, we demux according to it */ 735 if (wc->wc_flags & IB_WC_GRH) { 736 if (grh->dgid.global.interface_id == 737 cpu_to_be64(IB_SA_WELL_KNOWN_GUID) && 738 grh->dgid.global.subnet_prefix == cpu_to_be64( 739 atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix))) { 740 slave = 0; 741 } else { 742 slave = mlx4_ib_find_real_gid(ibdev, port, 743 grh->dgid.global.interface_id); 744 if (slave < 0) { 745 mlx4_ib_warn(ibdev, "failed matching grh\n"); 746 return -ENOENT; 747 } 748 } 749 } 750 /* Class-specific handling */ 751 switch (mad->mad_hdr.mgmt_class) { 752 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 753 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 754 /* 255 indicates the dom0 */ 755 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) { 756 if (!mlx4_vf_smi_enabled(dev->dev, slave, port)) 757 return -EPERM; 758 /* for a VF. drop unsolicited MADs */ 759 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) { 760 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n", 761 slave, mad->mad_hdr.mgmt_class, 762 mad->mad_hdr.method); 763 return -EINVAL; 764 } 765 } 766 break; 767 case IB_MGMT_CLASS_SUBN_ADM: 768 if (mlx4_ib_demux_sa_handler(ibdev, port, slave, 769 (struct ib_sa_mad *) mad)) 770 return 0; 771 break; 772 case IB_MGMT_CLASS_CM: 773 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad)) 774 return 0; 775 break; 776 case IB_MGMT_CLASS_DEVICE_MGMT: 777 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP) 778 return 0; 779 break; 780 default: 781 /* Drop unsupported classes for slaves in tunnel mode */ 782 if (slave != mlx4_master_func_num(dev->dev)) { 783 pr_debug("dropping unsupported ingress mad from class:%d " 784 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave); 785 return 0; 786 } 787 } 788 /*make sure that no slave==255 was not handled yet.*/ 789 if (slave >= dev->dev->caps.sqp_demux) { 790 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 791 slave, dev->dev->caps.sqp_demux); 792 return -ENOENT; 793 } 794 795 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 796 if (err) 797 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 798 slave, err); 799 return 0; 800 } 801 802 static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 803 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 804 const struct ib_mad *in_mad, struct ib_mad *out_mad) 805 { 806 u16 slid, prev_lid = 0; 807 int err; 808 struct ib_port_attr pattr; 809 810 if (in_wc && in_wc->qp) { 811 pr_debug("received MAD: port:%d slid:%d sqpn:%d " 812 "dlid_bits:%d dqpn:%d wc_flags:0x%x tid:%016llx cls:%x mtd:%x atr:%x\n", 813 port_num, 814 in_wc->slid, in_wc->src_qp, 815 in_wc->dlid_path_bits, 816 in_wc->qp->qp_num, 817 in_wc->wc_flags, 818 be64_to_cpu(in_mad->mad_hdr.tid), 819 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method, 820 be16_to_cpu(in_mad->mad_hdr.attr_id)); 821 if (in_wc->wc_flags & IB_WC_GRH) { 822 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n", 823 be64_to_cpu(in_grh->sgid.global.subnet_prefix), 824 be64_to_cpu(in_grh->sgid.global.interface_id)); 825 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n", 826 be64_to_cpu(in_grh->dgid.global.subnet_prefix), 827 be64_to_cpu(in_grh->dgid.global.interface_id)); 828 } 829 } 830 831 slid = in_wc ? ib_lid_cpu16(in_wc->slid) : be16_to_cpu(IB_LID_PERMISSIVE); 832 833 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) { 834 forward_trap(to_mdev(ibdev), port_num, in_mad); 835 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 836 } 837 838 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 839 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) { 840 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 841 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET && 842 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS) 843 return IB_MAD_RESULT_SUCCESS; 844 845 /* 846 * Don't process SMInfo queries -- the SMA can't handle them. 847 */ 848 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO) 849 return IB_MAD_RESULT_SUCCESS; 850 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT || 851 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 || 852 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 || 853 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) { 854 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 855 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET) 856 return IB_MAD_RESULT_SUCCESS; 857 } else 858 return IB_MAD_RESULT_SUCCESS; 859 860 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 861 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 862 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET && 863 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO && 864 !ib_query_port(ibdev, port_num, &pattr)) 865 prev_lid = ib_lid_cpu16(pattr.lid); 866 867 err = mlx4_MAD_IFC(to_mdev(ibdev), 868 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) | 869 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) | 870 MLX4_MAD_IFC_NET_VIEW, 871 port_num, in_wc, in_grh, in_mad, out_mad); 872 if (err) 873 return IB_MAD_RESULT_FAILURE; 874 875 if (!out_mad->mad_hdr.status) { 876 smp_snoop(ibdev, port_num, in_mad, prev_lid); 877 /* slaves get node desc from FW */ 878 if (!mlx4_is_slave(to_mdev(ibdev)->dev)) 879 node_desc_override(ibdev, out_mad); 880 } 881 882 /* set return bit in status of directed route responses */ 883 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) 884 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15); 885 886 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) 887 /* no response for trap repress */ 888 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 889 890 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 891 } 892 893 static void edit_counter(struct mlx4_counter *cnt, void *counters, 894 __be16 attr_id) 895 { 896 switch (attr_id) { 897 case IB_PMA_PORT_COUNTERS: 898 { 899 struct ib_pma_portcounters *pma_cnt = 900 (struct ib_pma_portcounters *)counters; 901 902 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data, 903 (be64_to_cpu(cnt->tx_bytes) >> 2)); 904 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data, 905 (be64_to_cpu(cnt->rx_bytes) >> 2)); 906 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets, 907 be64_to_cpu(cnt->tx_frames)); 908 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets, 909 be64_to_cpu(cnt->rx_frames)); 910 break; 911 } 912 case IB_PMA_PORT_COUNTERS_EXT: 913 { 914 struct ib_pma_portcounters_ext *pma_cnt_ext = 915 (struct ib_pma_portcounters_ext *)counters; 916 917 pma_cnt_ext->port_xmit_data = 918 cpu_to_be64(be64_to_cpu(cnt->tx_bytes) >> 2); 919 pma_cnt_ext->port_rcv_data = 920 cpu_to_be64(be64_to_cpu(cnt->rx_bytes) >> 2); 921 pma_cnt_ext->port_xmit_packets = cnt->tx_frames; 922 pma_cnt_ext->port_rcv_packets = cnt->rx_frames; 923 break; 924 } 925 } 926 } 927 928 static int iboe_process_mad_port_info(void *out_mad) 929 { 930 struct ib_class_port_info cpi = {}; 931 932 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 933 memcpy(out_mad, &cpi, sizeof(cpi)); 934 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 935 } 936 937 static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 938 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 939 const struct ib_mad *in_mad, struct ib_mad *out_mad) 940 { 941 struct mlx4_counter counter_stats; 942 struct mlx4_ib_dev *dev = to_mdev(ibdev); 943 struct counter_index *tmp_counter; 944 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0; 945 946 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 947 return -EINVAL; 948 949 if (in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO) 950 return iboe_process_mad_port_info((void *)(out_mad->data + 40)); 951 952 memset(&counter_stats, 0, sizeof(counter_stats)); 953 mutex_lock(&dev->counters_table[port_num - 1].mutex); 954 list_for_each_entry(tmp_counter, 955 &dev->counters_table[port_num - 1].counters_list, 956 list) { 957 err = mlx4_get_counter_stats(dev->dev, 958 tmp_counter->index, 959 &counter_stats, 0); 960 if (err) { 961 err = IB_MAD_RESULT_FAILURE; 962 stats_avail = 0; 963 break; 964 } 965 stats_avail = 1; 966 } 967 mutex_unlock(&dev->counters_table[port_num - 1].mutex); 968 if (stats_avail) { 969 memset(out_mad->data, 0, sizeof out_mad->data); 970 switch (counter_stats.counter_mode & 0xf) { 971 case 0: 972 edit_counter(&counter_stats, 973 (void *)(out_mad->data + 40), 974 in_mad->mad_hdr.attr_id); 975 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 976 break; 977 default: 978 err = IB_MAD_RESULT_FAILURE; 979 } 980 } 981 982 return err; 983 } 984 985 int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 986 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 987 const struct ib_mad_hdr *in, size_t in_mad_size, 988 struct ib_mad_hdr *out, size_t *out_mad_size, 989 u16 *out_mad_pkey_index) 990 { 991 struct mlx4_ib_dev *dev = to_mdev(ibdev); 992 const struct ib_mad *in_mad = (const struct ib_mad *)in; 993 struct ib_mad *out_mad = (struct ib_mad *)out; 994 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num); 995 996 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) || 997 *out_mad_size != sizeof(*out_mad))) 998 return IB_MAD_RESULT_FAILURE; 999 1000 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA 1001 * queries, should be called only by VFs and for that specific purpose 1002 */ 1003 if (link == IB_LINK_LAYER_INFINIBAND) { 1004 if (mlx4_is_slave(dev->dev) && 1005 (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT && 1006 (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS || 1007 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT || 1008 in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO))) 1009 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 1010 in_grh, in_mad, out_mad); 1011 1012 return ib_process_mad(ibdev, mad_flags, port_num, in_wc, 1013 in_grh, in_mad, out_mad); 1014 } 1015 1016 if (link == IB_LINK_LAYER_ETHERNET) 1017 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 1018 in_grh, in_mad, out_mad); 1019 1020 return -EINVAL; 1021 } 1022 1023 static void send_handler(struct ib_mad_agent *agent, 1024 struct ib_mad_send_wc *mad_send_wc) 1025 { 1026 if (mad_send_wc->send_buf->context[0]) 1027 rdma_destroy_ah(mad_send_wc->send_buf->context[0], 0); 1028 ib_free_send_mad(mad_send_wc->send_buf); 1029 } 1030 1031 int mlx4_ib_mad_init(struct mlx4_ib_dev *dev) 1032 { 1033 struct ib_mad_agent *agent; 1034 int p, q; 1035 int ret; 1036 enum rdma_link_layer ll; 1037 1038 for (p = 0; p < dev->num_ports; ++p) { 1039 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1); 1040 for (q = 0; q <= 1; ++q) { 1041 if (ll == IB_LINK_LAYER_INFINIBAND) { 1042 agent = ib_register_mad_agent(&dev->ib_dev, p + 1, 1043 q ? IB_QPT_GSI : IB_QPT_SMI, 1044 NULL, 0, send_handler, 1045 NULL, NULL, 0); 1046 if (IS_ERR(agent)) { 1047 ret = PTR_ERR(agent); 1048 goto err; 1049 } 1050 dev->send_agent[p][q] = agent; 1051 } else 1052 dev->send_agent[p][q] = NULL; 1053 } 1054 } 1055 1056 return 0; 1057 1058 err: 1059 for (p = 0; p < dev->num_ports; ++p) 1060 for (q = 0; q <= 1; ++q) 1061 if (dev->send_agent[p][q]) 1062 ib_unregister_mad_agent(dev->send_agent[p][q]); 1063 1064 return ret; 1065 } 1066 1067 void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev) 1068 { 1069 struct ib_mad_agent *agent; 1070 int p, q; 1071 1072 for (p = 0; p < dev->num_ports; ++p) { 1073 for (q = 0; q <= 1; ++q) { 1074 agent = dev->send_agent[p][q]; 1075 if (agent) { 1076 dev->send_agent[p][q] = NULL; 1077 ib_unregister_mad_agent(agent); 1078 } 1079 } 1080 1081 if (dev->sm_ah[p]) 1082 rdma_destroy_ah(dev->sm_ah[p], 0); 1083 } 1084 } 1085 1086 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num) 1087 { 1088 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE); 1089 1090 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1091 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1092 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK); 1093 } 1094 1095 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num) 1096 { 1097 /* re-configure the alias-guid and mcg's */ 1098 if (mlx4_is_master(dev->dev)) { 1099 mlx4_ib_invalidate_all_guid_record(dev, port_num); 1100 1101 if (!dev->sriov.is_going_down) { 1102 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0); 1103 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1104 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK); 1105 } 1106 } 1107 1108 /* Update the sl to vl table from inside client rereg 1109 * only if in secure-host mode (snooping is not possible) 1110 * and the sl-to-vl change event is not generated by FW. 1111 */ 1112 if (!mlx4_is_slave(dev->dev) && 1113 dev->dev->flags & MLX4_FLAG_SECURE_HOST && 1114 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) { 1115 if (mlx4_is_master(dev->dev)) 1116 /* already in work queue from mlx4_ib_event queueing 1117 * mlx4_handle_port_mgmt_change_event, which calls 1118 * this procedure. Therefore, call sl2vl_update directly. 1119 */ 1120 mlx4_ib_sl2vl_update(dev, port_num); 1121 else 1122 mlx4_sched_ib_sl2vl_update_work(dev, port_num); 1123 } 1124 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER); 1125 } 1126 1127 static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 1128 struct mlx4_eqe *eqe) 1129 { 1130 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe), 1131 GET_MASK_FROM_EQE(eqe)); 1132 } 1133 1134 static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num, 1135 u32 guid_tbl_blk_num, u32 change_bitmap) 1136 { 1137 struct ib_smp *in_mad = NULL; 1138 struct ib_smp *out_mad = NULL; 1139 u16 i; 1140 1141 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev)) 1142 return; 1143 1144 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL); 1145 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 1146 if (!in_mad || !out_mad) 1147 goto out; 1148 1149 guid_tbl_blk_num *= 4; 1150 1151 for (i = 0; i < 4; i++) { 1152 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff))) 1153 continue; 1154 memset(in_mad, 0, sizeof *in_mad); 1155 memset(out_mad, 0, sizeof *out_mad); 1156 1157 in_mad->base_version = 1; 1158 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1159 in_mad->class_version = 1; 1160 in_mad->method = IB_MGMT_METHOD_GET; 1161 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 1162 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i); 1163 1164 if (mlx4_MAD_IFC(dev, 1165 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW, 1166 port_num, NULL, NULL, in_mad, out_mad)) { 1167 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n"); 1168 goto out; 1169 } 1170 1171 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i, 1172 port_num, 1173 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1174 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i, 1175 port_num, 1176 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1177 } 1178 1179 out: 1180 kfree(in_mad); 1181 kfree(out_mad); 1182 return; 1183 } 1184 1185 void handle_port_mgmt_change_event(struct work_struct *work) 1186 { 1187 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 1188 struct mlx4_ib_dev *dev = ew->ib_dev; 1189 struct mlx4_eqe *eqe = &(ew->ib_eqe); 1190 u8 port = eqe->event.port_mgmt_change.port; 1191 u32 changed_attr; 1192 u32 tbl_block; 1193 u32 change_bitmap; 1194 1195 switch (eqe->subtype) { 1196 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO: 1197 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr); 1198 1199 /* Update the SM ah - This should be done before handling 1200 the other changed attributes so that MADs can be sent to the SM */ 1201 if (changed_attr & MSTR_SM_CHANGE_MASK) { 1202 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid); 1203 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf; 1204 update_sm_ah(dev, port, lid, sl); 1205 } 1206 1207 /* Check if it is a lid change event */ 1208 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK) 1209 handle_lid_change_event(dev, port); 1210 1211 /* Generate GUID changed event */ 1212 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) { 1213 if (mlx4_is_master(dev->dev)) { 1214 union ib_gid gid; 1215 int err = 0; 1216 1217 if (!eqe->event.port_mgmt_change.params.port_info.gid_prefix) 1218 err = __mlx4_ib_query_gid(&dev->ib_dev, port, 0, &gid, 1); 1219 else 1220 gid.global.subnet_prefix = 1221 eqe->event.port_mgmt_change.params.port_info.gid_prefix; 1222 if (err) { 1223 pr_warn("Could not change QP1 subnet prefix for port %d: query_gid error (%d)\n", 1224 port, err); 1225 } else { 1226 pr_debug("Changing QP1 subnet prefix for port %d. old=0x%llx. new=0x%llx\n", 1227 port, 1228 (u64)atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix), 1229 be64_to_cpu(gid.global.subnet_prefix)); 1230 atomic64_set(&dev->sriov.demux[port - 1].subnet_prefix, 1231 be64_to_cpu(gid.global.subnet_prefix)); 1232 } 1233 } 1234 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1235 /*if master, notify all slaves*/ 1236 if (mlx4_is_master(dev->dev)) 1237 mlx4_gen_slaves_port_mgt_ev(dev->dev, port, 1238 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK); 1239 } 1240 1241 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK) 1242 handle_client_rereg_event(dev, port); 1243 break; 1244 1245 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE: 1246 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE); 1247 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1248 propagate_pkey_ev(dev, port, eqe); 1249 break; 1250 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO: 1251 /* paravirtualized master's guid is guid 0 -- does not change */ 1252 if (!mlx4_is_master(dev->dev)) 1253 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1254 /*if master, notify relevant slaves*/ 1255 else if (!dev->sriov.is_going_down) { 1256 tbl_block = GET_BLK_PTR_FROM_EQE(eqe); 1257 change_bitmap = GET_MASK_FROM_EQE(eqe); 1258 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap); 1259 } 1260 break; 1261 1262 case MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP: 1263 /* cache sl to vl mapping changes for use in 1264 * filling QP1 LRH VL field when sending packets 1265 */ 1266 if (!mlx4_is_slave(dev->dev)) { 1267 union sl2vl_tbl_to_u64 sl2vl64; 1268 int jj; 1269 1270 for (jj = 0; jj < 8; jj++) { 1271 sl2vl64.sl8[jj] = 1272 eqe->event.port_mgmt_change.params.sl2vl_tbl_change_info.sl2vl_table[jj]; 1273 pr_debug("port %u, sl2vl[%d] = %02x\n", 1274 port, jj, sl2vl64.sl8[jj]); 1275 } 1276 atomic64_set(&dev->sl2vl[port - 1], sl2vl64.sl64); 1277 } 1278 break; 1279 default: 1280 pr_warn("Unsupported subtype 0x%x for " 1281 "Port Management Change event\n", eqe->subtype); 1282 } 1283 1284 kfree(ew); 1285 } 1286 1287 void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, 1288 enum ib_event_type type) 1289 { 1290 struct ib_event event; 1291 1292 event.device = &dev->ib_dev; 1293 event.element.port_num = port_num; 1294 event.event = type; 1295 1296 ib_dispatch_event(&event); 1297 } 1298 1299 static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg) 1300 { 1301 unsigned long flags; 1302 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context; 1303 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1304 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 1305 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE) 1306 queue_work(ctx->wq, &ctx->work); 1307 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 1308 } 1309 1310 static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx, 1311 struct mlx4_ib_demux_pv_qp *tun_qp, 1312 int index) 1313 { 1314 struct ib_sge sg_list; 1315 struct ib_recv_wr recv_wr; 1316 const struct ib_recv_wr *bad_recv_wr; 1317 int size; 1318 1319 size = (tun_qp->qp->qp_type == IB_QPT_UD) ? 1320 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf); 1321 1322 sg_list.addr = tun_qp->ring[index].map; 1323 sg_list.length = size; 1324 sg_list.lkey = ctx->pd->local_dma_lkey; 1325 1326 recv_wr.next = NULL; 1327 recv_wr.sg_list = &sg_list; 1328 recv_wr.num_sge = 1; 1329 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV | 1330 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt); 1331 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map, 1332 size, DMA_FROM_DEVICE); 1333 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr); 1334 } 1335 1336 static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port, 1337 int slave, struct ib_sa_mad *sa_mad) 1338 { 1339 int ret = 0; 1340 1341 /* dispatch to different sa handlers */ 1342 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 1343 case IB_SA_ATTR_MC_MEMBER_REC: 1344 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad); 1345 break; 1346 default: 1347 break; 1348 } 1349 return ret; 1350 } 1351 1352 static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave) 1353 { 1354 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave; 1355 1356 return (qpn >= proxy_start && qpn <= proxy_start + 1); 1357 } 1358 1359 1360 int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, 1361 enum ib_qp_type dest_qpt, u16 pkey_index, 1362 u32 remote_qpn, u32 qkey, struct rdma_ah_attr *attr, 1363 u8 *s_mac, u16 vlan_id, struct ib_mad *mad) 1364 { 1365 struct ib_sge list; 1366 struct ib_ud_wr wr; 1367 const struct ib_send_wr *bad_wr; 1368 struct mlx4_ib_demux_pv_ctx *sqp_ctx; 1369 struct mlx4_ib_demux_pv_qp *sqp; 1370 struct mlx4_mad_snd_buf *sqp_mad; 1371 struct ib_ah *ah; 1372 struct ib_qp *send_qp = NULL; 1373 unsigned wire_tx_ix = 0; 1374 u16 wire_pkey_ix; 1375 int src_qpnum; 1376 int ret; 1377 1378 sqp_ctx = dev->sriov.sqps[port-1]; 1379 1380 /* check if proxy qp created */ 1381 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE) 1382 return -EAGAIN; 1383 1384 if (dest_qpt == IB_QPT_SMI) { 1385 src_qpnum = 0; 1386 sqp = &sqp_ctx->qp[0]; 1387 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 1388 } else { 1389 src_qpnum = 1; 1390 sqp = &sqp_ctx->qp[1]; 1391 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index]; 1392 } 1393 1394 send_qp = sqp->qp; 1395 1396 ah = rdma_zalloc_drv_obj(sqp_ctx->pd->device, ib_ah); 1397 if (!ah) 1398 return -ENOMEM; 1399 1400 ah->device = sqp_ctx->pd->device; 1401 ah->pd = sqp_ctx->pd; 1402 1403 /* create ah */ 1404 ret = mlx4_ib_create_ah_slave(ah, attr, 1405 rdma_ah_retrieve_grh(attr)->sgid_index, 1406 s_mac, vlan_id); 1407 if (ret) 1408 goto out; 1409 1410 spin_lock(&sqp->tx_lock); 1411 if (sqp->tx_ix_head - sqp->tx_ix_tail >= 1412 (MLX4_NUM_TUNNEL_BUFS - 1)) 1413 ret = -EAGAIN; 1414 else 1415 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 1416 spin_unlock(&sqp->tx_lock); 1417 if (ret) 1418 goto out; 1419 1420 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr); 1421 kfree(sqp->tx_ring[wire_tx_ix].ah); 1422 sqp->tx_ring[wire_tx_ix].ah = ah; 1423 ib_dma_sync_single_for_cpu(&dev->ib_dev, 1424 sqp->tx_ring[wire_tx_ix].buf.map, 1425 sizeof (struct mlx4_mad_snd_buf), 1426 DMA_TO_DEVICE); 1427 1428 memcpy(&sqp_mad->payload, mad, sizeof *mad); 1429 1430 ib_dma_sync_single_for_device(&dev->ib_dev, 1431 sqp->tx_ring[wire_tx_ix].buf.map, 1432 sizeof (struct mlx4_mad_snd_buf), 1433 DMA_TO_DEVICE); 1434 1435 list.addr = sqp->tx_ring[wire_tx_ix].buf.map; 1436 list.length = sizeof (struct mlx4_mad_snd_buf); 1437 list.lkey = sqp_ctx->pd->local_dma_lkey; 1438 1439 wr.ah = ah; 1440 wr.port_num = port; 1441 wr.pkey_index = wire_pkey_ix; 1442 wr.remote_qkey = qkey; 1443 wr.remote_qpn = remote_qpn; 1444 wr.wr.next = NULL; 1445 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum); 1446 wr.wr.sg_list = &list; 1447 wr.wr.num_sge = 1; 1448 wr.wr.opcode = IB_WR_SEND; 1449 wr.wr.send_flags = IB_SEND_SIGNALED; 1450 1451 ret = ib_post_send(send_qp, &wr.wr, &bad_wr); 1452 if (!ret) 1453 return 0; 1454 1455 spin_lock(&sqp->tx_lock); 1456 sqp->tx_ix_tail++; 1457 spin_unlock(&sqp->tx_lock); 1458 sqp->tx_ring[wire_tx_ix].ah = NULL; 1459 out: 1460 kfree(ah); 1461 return ret; 1462 } 1463 1464 static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port) 1465 { 1466 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1467 return slave; 1468 return mlx4_get_base_gid_ix(dev->dev, slave, port); 1469 } 1470 1471 static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port, 1472 struct rdma_ah_attr *ah_attr) 1473 { 1474 struct ib_global_route *grh = rdma_ah_retrieve_grh(ah_attr); 1475 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1476 grh->sgid_index = slave; 1477 else 1478 grh->sgid_index += get_slave_base_gid_ix(dev, slave, port); 1479 } 1480 1481 static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc) 1482 { 1483 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1484 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)]; 1485 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1); 1486 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr; 1487 struct mlx4_ib_ah ah; 1488 struct rdma_ah_attr ah_attr; 1489 u8 *slave_id; 1490 int slave; 1491 int port; 1492 u16 vlan_id; 1493 u8 qos; 1494 u8 *dmac; 1495 1496 /* Get slave that sent this packet */ 1497 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn || 1498 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX || 1499 (wc->src_qp & 0x1) != ctx->port - 1 || 1500 wc->src_qp & 0x4) { 1501 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp); 1502 return; 1503 } 1504 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8; 1505 if (slave != ctx->slave) { 1506 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: " 1507 "belongs to another slave\n", wc->src_qp); 1508 return; 1509 } 1510 1511 /* Map transaction ID */ 1512 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map, 1513 sizeof (struct mlx4_tunnel_mad), 1514 DMA_FROM_DEVICE); 1515 switch (tunnel->mad.mad_hdr.method) { 1516 case IB_MGMT_METHOD_SET: 1517 case IB_MGMT_METHOD_GET: 1518 case IB_MGMT_METHOD_REPORT: 1519 case IB_SA_METHOD_GET_TABLE: 1520 case IB_SA_METHOD_DELETE: 1521 case IB_SA_METHOD_GET_MULTI: 1522 case IB_SA_METHOD_GET_TRACE_TBL: 1523 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid; 1524 if (*slave_id) { 1525 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d " 1526 "class:%d slave:%d\n", *slave_id, 1527 tunnel->mad.mad_hdr.mgmt_class, slave); 1528 return; 1529 } else 1530 *slave_id = slave; 1531 default: 1532 /* nothing */; 1533 } 1534 1535 /* Class-specific handling */ 1536 switch (tunnel->mad.mad_hdr.mgmt_class) { 1537 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 1538 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 1539 if (slave != mlx4_master_func_num(dev->dev) && 1540 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port)) 1541 return; 1542 break; 1543 case IB_MGMT_CLASS_SUBN_ADM: 1544 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave, 1545 (struct ib_sa_mad *) &tunnel->mad)) 1546 return; 1547 break; 1548 case IB_MGMT_CLASS_CM: 1549 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave, 1550 (struct ib_mad *) &tunnel->mad)) 1551 return; 1552 break; 1553 case IB_MGMT_CLASS_DEVICE_MGMT: 1554 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET && 1555 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET) 1556 return; 1557 break; 1558 default: 1559 /* Drop unsupported classes for slaves in tunnel mode */ 1560 if (slave != mlx4_master_func_num(dev->dev)) { 1561 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d " 1562 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave); 1563 return; 1564 } 1565 } 1566 1567 /* We are using standard ib_core services to send the mad, so generate a 1568 * stadard address handle by decoding the tunnelled mlx4_ah fields */ 1569 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av)); 1570 ah.ibah.device = ctx->ib_dev; 1571 1572 port = be32_to_cpu(ah.av.ib.port_pd) >> 24; 1573 port = mlx4_slave_convert_port(dev->dev, slave, port); 1574 if (port < 0) 1575 return; 1576 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff)); 1577 ah.ibah.type = rdma_ah_find_type(&dev->ib_dev, port); 1578 1579 mlx4_ib_query_ah(&ah.ibah, &ah_attr); 1580 if (rdma_ah_get_ah_flags(&ah_attr) & IB_AH_GRH) 1581 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr); 1582 dmac = rdma_ah_retrieve_dmac(&ah_attr); 1583 if (dmac) 1584 memcpy(dmac, tunnel->hdr.mac, ETH_ALEN); 1585 vlan_id = be16_to_cpu(tunnel->hdr.vlan); 1586 /* if slave have default vlan use it */ 1587 if (mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave, 1588 &vlan_id, &qos)) 1589 rdma_ah_set_sl(&ah_attr, qos); 1590 1591 mlx4_ib_send_to_wire(dev, slave, ctx->port, 1592 is_proxy_qp0(dev, wc->src_qp, slave) ? 1593 IB_QPT_SMI : IB_QPT_GSI, 1594 be16_to_cpu(tunnel->hdr.pkey_index), 1595 be32_to_cpu(tunnel->hdr.remote_qpn), 1596 be32_to_cpu(tunnel->hdr.qkey), 1597 &ah_attr, wc->smac, vlan_id, &tunnel->mad); 1598 } 1599 1600 static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1601 enum ib_qp_type qp_type, int is_tun) 1602 { 1603 int i; 1604 struct mlx4_ib_demux_pv_qp *tun_qp; 1605 int rx_buf_size, tx_buf_size; 1606 1607 if (qp_type > IB_QPT_GSI) 1608 return -EINVAL; 1609 1610 tun_qp = &ctx->qp[qp_type]; 1611 1612 tun_qp->ring = kcalloc(MLX4_NUM_TUNNEL_BUFS, 1613 sizeof(struct mlx4_ib_buf), 1614 GFP_KERNEL); 1615 if (!tun_qp->ring) 1616 return -ENOMEM; 1617 1618 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS, 1619 sizeof (struct mlx4_ib_tun_tx_buf), 1620 GFP_KERNEL); 1621 if (!tun_qp->tx_ring) { 1622 kfree(tun_qp->ring); 1623 tun_qp->ring = NULL; 1624 return -ENOMEM; 1625 } 1626 1627 if (is_tun) { 1628 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1629 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1630 } else { 1631 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1632 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1633 } 1634 1635 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1636 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL); 1637 if (!tun_qp->ring[i].addr) 1638 goto err; 1639 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev, 1640 tun_qp->ring[i].addr, 1641 rx_buf_size, 1642 DMA_FROM_DEVICE); 1643 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) { 1644 kfree(tun_qp->ring[i].addr); 1645 goto err; 1646 } 1647 } 1648 1649 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1650 tun_qp->tx_ring[i].buf.addr = 1651 kmalloc(tx_buf_size, GFP_KERNEL); 1652 if (!tun_qp->tx_ring[i].buf.addr) 1653 goto tx_err; 1654 tun_qp->tx_ring[i].buf.map = 1655 ib_dma_map_single(ctx->ib_dev, 1656 tun_qp->tx_ring[i].buf.addr, 1657 tx_buf_size, 1658 DMA_TO_DEVICE); 1659 if (ib_dma_mapping_error(ctx->ib_dev, 1660 tun_qp->tx_ring[i].buf.map)) { 1661 kfree(tun_qp->tx_ring[i].buf.addr); 1662 goto tx_err; 1663 } 1664 tun_qp->tx_ring[i].ah = NULL; 1665 } 1666 spin_lock_init(&tun_qp->tx_lock); 1667 tun_qp->tx_ix_head = 0; 1668 tun_qp->tx_ix_tail = 0; 1669 tun_qp->proxy_qpt = qp_type; 1670 1671 return 0; 1672 1673 tx_err: 1674 while (i > 0) { 1675 --i; 1676 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1677 tx_buf_size, DMA_TO_DEVICE); 1678 kfree(tun_qp->tx_ring[i].buf.addr); 1679 } 1680 kfree(tun_qp->tx_ring); 1681 tun_qp->tx_ring = NULL; 1682 i = MLX4_NUM_TUNNEL_BUFS; 1683 err: 1684 while (i > 0) { 1685 --i; 1686 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1687 rx_buf_size, DMA_FROM_DEVICE); 1688 kfree(tun_qp->ring[i].addr); 1689 } 1690 kfree(tun_qp->ring); 1691 tun_qp->ring = NULL; 1692 return -ENOMEM; 1693 } 1694 1695 static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1696 enum ib_qp_type qp_type, int is_tun) 1697 { 1698 int i; 1699 struct mlx4_ib_demux_pv_qp *tun_qp; 1700 int rx_buf_size, tx_buf_size; 1701 1702 if (qp_type > IB_QPT_GSI) 1703 return; 1704 1705 tun_qp = &ctx->qp[qp_type]; 1706 if (is_tun) { 1707 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1708 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1709 } else { 1710 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1711 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1712 } 1713 1714 1715 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1716 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1717 rx_buf_size, DMA_FROM_DEVICE); 1718 kfree(tun_qp->ring[i].addr); 1719 } 1720 1721 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1722 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1723 tx_buf_size, DMA_TO_DEVICE); 1724 kfree(tun_qp->tx_ring[i].buf.addr); 1725 if (tun_qp->tx_ring[i].ah) 1726 rdma_destroy_ah(tun_qp->tx_ring[i].ah, 0); 1727 } 1728 kfree(tun_qp->tx_ring); 1729 kfree(tun_qp->ring); 1730 } 1731 1732 static void mlx4_ib_tunnel_comp_worker(struct work_struct *work) 1733 { 1734 struct mlx4_ib_demux_pv_ctx *ctx; 1735 struct mlx4_ib_demux_pv_qp *tun_qp; 1736 struct ib_wc wc; 1737 int ret; 1738 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1739 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1740 1741 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1742 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1743 if (wc.status == IB_WC_SUCCESS) { 1744 switch (wc.opcode) { 1745 case IB_WC_RECV: 1746 mlx4_ib_multiplex_mad(ctx, &wc); 1747 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, 1748 wc.wr_id & 1749 (MLX4_NUM_TUNNEL_BUFS - 1)); 1750 if (ret) 1751 pr_err("Failed reposting tunnel " 1752 "buf:%lld\n", wc.wr_id); 1753 break; 1754 case IB_WC_SEND: 1755 pr_debug("received tunnel send completion:" 1756 "wrid=0x%llx, status=0x%x\n", 1757 wc.wr_id, wc.status); 1758 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1759 (MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0); 1760 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1761 = NULL; 1762 spin_lock(&tun_qp->tx_lock); 1763 tun_qp->tx_ix_tail++; 1764 spin_unlock(&tun_qp->tx_lock); 1765 1766 break; 1767 default: 1768 break; 1769 } 1770 } else { 1771 pr_debug("mlx4_ib: completion error in tunnel: %d." 1772 " status = %d, wrid = 0x%llx\n", 1773 ctx->slave, wc.status, wc.wr_id); 1774 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1775 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1776 (MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0); 1777 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1778 = NULL; 1779 spin_lock(&tun_qp->tx_lock); 1780 tun_qp->tx_ix_tail++; 1781 spin_unlock(&tun_qp->tx_lock); 1782 } 1783 } 1784 } 1785 } 1786 1787 static void pv_qp_event_handler(struct ib_event *event, void *qp_context) 1788 { 1789 struct mlx4_ib_demux_pv_ctx *sqp = qp_context; 1790 1791 /* It's worse than that! He's dead, Jim! */ 1792 pr_err("Fatal error (%d) on a MAD QP on port %d\n", 1793 event->event, sqp->port); 1794 } 1795 1796 static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx, 1797 enum ib_qp_type qp_type, int create_tun) 1798 { 1799 int i, ret; 1800 struct mlx4_ib_demux_pv_qp *tun_qp; 1801 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr; 1802 struct ib_qp_attr attr; 1803 int qp_attr_mask_INIT; 1804 1805 if (qp_type > IB_QPT_GSI) 1806 return -EINVAL; 1807 1808 tun_qp = &ctx->qp[qp_type]; 1809 1810 memset(&qp_init_attr, 0, sizeof qp_init_attr); 1811 qp_init_attr.init_attr.send_cq = ctx->cq; 1812 qp_init_attr.init_attr.recv_cq = ctx->cq; 1813 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 1814 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS; 1815 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS; 1816 qp_init_attr.init_attr.cap.max_send_sge = 1; 1817 qp_init_attr.init_attr.cap.max_recv_sge = 1; 1818 if (create_tun) { 1819 qp_init_attr.init_attr.qp_type = IB_QPT_UD; 1820 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP; 1821 qp_init_attr.port = ctx->port; 1822 qp_init_attr.slave = ctx->slave; 1823 qp_init_attr.proxy_qp_type = qp_type; 1824 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | 1825 IB_QP_QKEY | IB_QP_PORT; 1826 } else { 1827 qp_init_attr.init_attr.qp_type = qp_type; 1828 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP; 1829 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY; 1830 } 1831 qp_init_attr.init_attr.port_num = ctx->port; 1832 qp_init_attr.init_attr.qp_context = ctx; 1833 qp_init_attr.init_attr.event_handler = pv_qp_event_handler; 1834 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr); 1835 if (IS_ERR(tun_qp->qp)) { 1836 ret = PTR_ERR(tun_qp->qp); 1837 tun_qp->qp = NULL; 1838 pr_err("Couldn't create %s QP (%d)\n", 1839 create_tun ? "tunnel" : "special", ret); 1840 return ret; 1841 } 1842 1843 memset(&attr, 0, sizeof attr); 1844 attr.qp_state = IB_QPS_INIT; 1845 ret = 0; 1846 if (create_tun) 1847 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave, 1848 ctx->port, IB_DEFAULT_PKEY_FULL, 1849 &attr.pkey_index); 1850 if (ret || !create_tun) 1851 attr.pkey_index = 1852 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0]; 1853 attr.qkey = IB_QP1_QKEY; 1854 attr.port_num = ctx->port; 1855 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT); 1856 if (ret) { 1857 pr_err("Couldn't change %s qp state to INIT (%d)\n", 1858 create_tun ? "tunnel" : "special", ret); 1859 goto err_qp; 1860 } 1861 attr.qp_state = IB_QPS_RTR; 1862 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE); 1863 if (ret) { 1864 pr_err("Couldn't change %s qp state to RTR (%d)\n", 1865 create_tun ? "tunnel" : "special", ret); 1866 goto err_qp; 1867 } 1868 attr.qp_state = IB_QPS_RTS; 1869 attr.sq_psn = 0; 1870 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN); 1871 if (ret) { 1872 pr_err("Couldn't change %s qp state to RTS (%d)\n", 1873 create_tun ? "tunnel" : "special", ret); 1874 goto err_qp; 1875 } 1876 1877 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1878 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i); 1879 if (ret) { 1880 pr_err(" mlx4_ib_post_pv_buf error" 1881 " (err = %d, i = %d)\n", ret, i); 1882 goto err_qp; 1883 } 1884 } 1885 return 0; 1886 1887 err_qp: 1888 ib_destroy_qp(tun_qp->qp); 1889 tun_qp->qp = NULL; 1890 return ret; 1891 } 1892 1893 /* 1894 * IB MAD completion callback for real SQPs 1895 */ 1896 static void mlx4_ib_sqp_comp_worker(struct work_struct *work) 1897 { 1898 struct mlx4_ib_demux_pv_ctx *ctx; 1899 struct mlx4_ib_demux_pv_qp *sqp; 1900 struct ib_wc wc; 1901 struct ib_grh *grh; 1902 struct ib_mad *mad; 1903 1904 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1905 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1906 1907 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1908 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1909 if (wc.status == IB_WC_SUCCESS) { 1910 switch (wc.opcode) { 1911 case IB_WC_SEND: 1912 kfree(sqp->tx_ring[wc.wr_id & 1913 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1914 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1915 = NULL; 1916 spin_lock(&sqp->tx_lock); 1917 sqp->tx_ix_tail++; 1918 spin_unlock(&sqp->tx_lock); 1919 break; 1920 case IB_WC_RECV: 1921 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *) 1922 (sqp->ring[wc.wr_id & 1923 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload); 1924 grh = &(((struct mlx4_mad_rcv_buf *) 1925 (sqp->ring[wc.wr_id & 1926 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh); 1927 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad); 1928 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id & 1929 (MLX4_NUM_TUNNEL_BUFS - 1))) 1930 pr_err("Failed reposting SQP " 1931 "buf:%lld\n", wc.wr_id); 1932 break; 1933 default: 1934 break; 1935 } 1936 } else { 1937 pr_debug("mlx4_ib: completion error in tunnel: %d." 1938 " status = %d, wrid = 0x%llx\n", 1939 ctx->slave, wc.status, wc.wr_id); 1940 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1941 kfree(sqp->tx_ring[wc.wr_id & 1942 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1943 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1944 = NULL; 1945 spin_lock(&sqp->tx_lock); 1946 sqp->tx_ix_tail++; 1947 spin_unlock(&sqp->tx_lock); 1948 } 1949 } 1950 } 1951 } 1952 1953 static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port, 1954 struct mlx4_ib_demux_pv_ctx **ret_ctx) 1955 { 1956 struct mlx4_ib_demux_pv_ctx *ctx; 1957 1958 *ret_ctx = NULL; 1959 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL); 1960 if (!ctx) 1961 return -ENOMEM; 1962 1963 ctx->ib_dev = &dev->ib_dev; 1964 ctx->port = port; 1965 ctx->slave = slave; 1966 *ret_ctx = ctx; 1967 return 0; 1968 } 1969 1970 static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port) 1971 { 1972 if (dev->sriov.demux[port - 1].tun[slave]) { 1973 kfree(dev->sriov.demux[port - 1].tun[slave]); 1974 dev->sriov.demux[port - 1].tun[slave] = NULL; 1975 } 1976 } 1977 1978 static int create_pv_resources(struct ib_device *ibdev, int slave, int port, 1979 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx) 1980 { 1981 int ret, cq_size; 1982 struct ib_cq_init_attr cq_attr = {}; 1983 1984 if (ctx->state != DEMUX_PV_STATE_DOWN) 1985 return -EEXIST; 1986 1987 ctx->state = DEMUX_PV_STATE_STARTING; 1988 /* have QP0 only if link layer is IB */ 1989 if (rdma_port_get_link_layer(ibdev, ctx->port) == 1990 IB_LINK_LAYER_INFINIBAND) 1991 ctx->has_smi = 1; 1992 1993 if (ctx->has_smi) { 1994 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun); 1995 if (ret) { 1996 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret); 1997 goto err_out; 1998 } 1999 } 2000 2001 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun); 2002 if (ret) { 2003 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret); 2004 goto err_out_qp0; 2005 } 2006 2007 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS; 2008 if (ctx->has_smi) 2009 cq_size *= 2; 2010 2011 cq_attr.cqe = cq_size; 2012 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler, 2013 NULL, ctx, &cq_attr); 2014 if (IS_ERR(ctx->cq)) { 2015 ret = PTR_ERR(ctx->cq); 2016 pr_err("Couldn't create tunnel CQ (%d)\n", ret); 2017 goto err_buf; 2018 } 2019 2020 ctx->pd = ib_alloc_pd(ctx->ib_dev, 0); 2021 if (IS_ERR(ctx->pd)) { 2022 ret = PTR_ERR(ctx->pd); 2023 pr_err("Couldn't create tunnel PD (%d)\n", ret); 2024 goto err_cq; 2025 } 2026 2027 if (ctx->has_smi) { 2028 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun); 2029 if (ret) { 2030 pr_err("Couldn't create %s QP0 (%d)\n", 2031 create_tun ? "tunnel for" : "", ret); 2032 goto err_pd; 2033 } 2034 } 2035 2036 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun); 2037 if (ret) { 2038 pr_err("Couldn't create %s QP1 (%d)\n", 2039 create_tun ? "tunnel for" : "", ret); 2040 goto err_qp0; 2041 } 2042 2043 if (create_tun) 2044 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker); 2045 else 2046 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker); 2047 2048 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq; 2049 2050 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 2051 if (ret) { 2052 pr_err("Couldn't arm tunnel cq (%d)\n", ret); 2053 goto err_wq; 2054 } 2055 ctx->state = DEMUX_PV_STATE_ACTIVE; 2056 return 0; 2057 2058 err_wq: 2059 ctx->wq = NULL; 2060 ib_destroy_qp(ctx->qp[1].qp); 2061 ctx->qp[1].qp = NULL; 2062 2063 2064 err_qp0: 2065 if (ctx->has_smi) 2066 ib_destroy_qp(ctx->qp[0].qp); 2067 ctx->qp[0].qp = NULL; 2068 2069 err_pd: 2070 ib_dealloc_pd(ctx->pd); 2071 ctx->pd = NULL; 2072 2073 err_cq: 2074 ib_destroy_cq(ctx->cq); 2075 ctx->cq = NULL; 2076 2077 err_buf: 2078 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun); 2079 2080 err_out_qp0: 2081 if (ctx->has_smi) 2082 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun); 2083 err_out: 2084 ctx->state = DEMUX_PV_STATE_DOWN; 2085 return ret; 2086 } 2087 2088 static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port, 2089 struct mlx4_ib_demux_pv_ctx *ctx, int flush) 2090 { 2091 if (!ctx) 2092 return; 2093 if (ctx->state > DEMUX_PV_STATE_DOWN) { 2094 ctx->state = DEMUX_PV_STATE_DOWNING; 2095 if (flush) 2096 flush_workqueue(ctx->wq); 2097 if (ctx->has_smi) { 2098 ib_destroy_qp(ctx->qp[0].qp); 2099 ctx->qp[0].qp = NULL; 2100 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1); 2101 } 2102 ib_destroy_qp(ctx->qp[1].qp); 2103 ctx->qp[1].qp = NULL; 2104 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1); 2105 ib_dealloc_pd(ctx->pd); 2106 ctx->pd = NULL; 2107 ib_destroy_cq(ctx->cq); 2108 ctx->cq = NULL; 2109 ctx->state = DEMUX_PV_STATE_DOWN; 2110 } 2111 } 2112 2113 static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave, 2114 int port, int do_init) 2115 { 2116 int ret = 0; 2117 2118 if (!do_init) { 2119 clean_vf_mcast(&dev->sriov.demux[port - 1], slave); 2120 /* for master, destroy real sqp resources */ 2121 if (slave == mlx4_master_func_num(dev->dev)) 2122 destroy_pv_resources(dev, slave, port, 2123 dev->sriov.sqps[port - 1], 1); 2124 /* destroy the tunnel qp resources */ 2125 destroy_pv_resources(dev, slave, port, 2126 dev->sriov.demux[port - 1].tun[slave], 1); 2127 return 0; 2128 } 2129 2130 /* create the tunnel qp resources */ 2131 ret = create_pv_resources(&dev->ib_dev, slave, port, 1, 2132 dev->sriov.demux[port - 1].tun[slave]); 2133 2134 /* for master, create the real sqp resources */ 2135 if (!ret && slave == mlx4_master_func_num(dev->dev)) 2136 ret = create_pv_resources(&dev->ib_dev, slave, port, 0, 2137 dev->sriov.sqps[port - 1]); 2138 return ret; 2139 } 2140 2141 void mlx4_ib_tunnels_update_work(struct work_struct *work) 2142 { 2143 struct mlx4_ib_demux_work *dmxw; 2144 2145 dmxw = container_of(work, struct mlx4_ib_demux_work, work); 2146 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port, 2147 dmxw->do_init); 2148 kfree(dmxw); 2149 return; 2150 } 2151 2152 static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev, 2153 struct mlx4_ib_demux_ctx *ctx, 2154 int port) 2155 { 2156 char name[12]; 2157 int ret = 0; 2158 int i; 2159 2160 ctx->tun = kcalloc(dev->dev->caps.sqp_demux, 2161 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL); 2162 if (!ctx->tun) 2163 return -ENOMEM; 2164 2165 ctx->dev = dev; 2166 ctx->port = port; 2167 ctx->ib_dev = &dev->ib_dev; 2168 2169 for (i = 0; 2170 i < min(dev->dev->caps.sqp_demux, 2171 (u16)(dev->dev->persist->num_vfs + 1)); 2172 i++) { 2173 struct mlx4_active_ports actv_ports = 2174 mlx4_get_active_ports(dev->dev, i); 2175 2176 if (!test_bit(port - 1, actv_ports.ports)) 2177 continue; 2178 2179 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]); 2180 if (ret) { 2181 ret = -ENOMEM; 2182 goto err_mcg; 2183 } 2184 } 2185 2186 ret = mlx4_ib_mcg_port_init(ctx); 2187 if (ret) { 2188 pr_err("Failed initializing mcg para-virt (%d)\n", ret); 2189 goto err_mcg; 2190 } 2191 2192 snprintf(name, sizeof name, "mlx4_ibt%d", port); 2193 ctx->wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM); 2194 if (!ctx->wq) { 2195 pr_err("Failed to create tunnelling WQ for port %d\n", port); 2196 ret = -ENOMEM; 2197 goto err_wq; 2198 } 2199 2200 snprintf(name, sizeof name, "mlx4_ibud%d", port); 2201 ctx->ud_wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM); 2202 if (!ctx->ud_wq) { 2203 pr_err("Failed to create up/down WQ for port %d\n", port); 2204 ret = -ENOMEM; 2205 goto err_udwq; 2206 } 2207 2208 return 0; 2209 2210 err_udwq: 2211 destroy_workqueue(ctx->wq); 2212 ctx->wq = NULL; 2213 2214 err_wq: 2215 mlx4_ib_mcg_port_cleanup(ctx, 1); 2216 err_mcg: 2217 for (i = 0; i < dev->dev->caps.sqp_demux; i++) 2218 free_pv_object(dev, i, port); 2219 kfree(ctx->tun); 2220 ctx->tun = NULL; 2221 return ret; 2222 } 2223 2224 static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx) 2225 { 2226 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) { 2227 sqp_ctx->state = DEMUX_PV_STATE_DOWNING; 2228 flush_workqueue(sqp_ctx->wq); 2229 if (sqp_ctx->has_smi) { 2230 ib_destroy_qp(sqp_ctx->qp[0].qp); 2231 sqp_ctx->qp[0].qp = NULL; 2232 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0); 2233 } 2234 ib_destroy_qp(sqp_ctx->qp[1].qp); 2235 sqp_ctx->qp[1].qp = NULL; 2236 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0); 2237 ib_dealloc_pd(sqp_ctx->pd); 2238 sqp_ctx->pd = NULL; 2239 ib_destroy_cq(sqp_ctx->cq); 2240 sqp_ctx->cq = NULL; 2241 sqp_ctx->state = DEMUX_PV_STATE_DOWN; 2242 } 2243 } 2244 2245 static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx) 2246 { 2247 int i; 2248 if (ctx) { 2249 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 2250 mlx4_ib_mcg_port_cleanup(ctx, 1); 2251 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2252 if (!ctx->tun[i]) 2253 continue; 2254 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN) 2255 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING; 2256 } 2257 flush_workqueue(ctx->wq); 2258 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2259 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0); 2260 free_pv_object(dev, i, ctx->port); 2261 } 2262 kfree(ctx->tun); 2263 destroy_workqueue(ctx->ud_wq); 2264 destroy_workqueue(ctx->wq); 2265 } 2266 } 2267 2268 static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init) 2269 { 2270 int i; 2271 2272 if (!mlx4_is_master(dev->dev)) 2273 return; 2274 /* initialize or tear down tunnel QPs for the master */ 2275 for (i = 0; i < dev->dev->caps.num_ports; i++) 2276 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init); 2277 return; 2278 } 2279 2280 int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev) 2281 { 2282 int i = 0; 2283 int err; 2284 2285 if (!mlx4_is_mfunc(dev->dev)) 2286 return 0; 2287 2288 dev->sriov.is_going_down = 0; 2289 spin_lock_init(&dev->sriov.going_down_lock); 2290 mlx4_ib_cm_paravirt_init(dev); 2291 2292 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n"); 2293 2294 if (mlx4_is_slave(dev->dev)) { 2295 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n"); 2296 return 0; 2297 } 2298 2299 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2300 if (i == mlx4_master_func_num(dev->dev)) 2301 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid); 2302 else 2303 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid()); 2304 } 2305 2306 err = mlx4_ib_init_alias_guid_service(dev); 2307 if (err) { 2308 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n"); 2309 goto paravirt_err; 2310 } 2311 err = mlx4_ib_device_register_sysfs(dev); 2312 if (err) { 2313 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n"); 2314 goto sysfs_err; 2315 } 2316 2317 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n", 2318 dev->dev->caps.sqp_demux); 2319 for (i = 0; i < dev->num_ports; i++) { 2320 union ib_gid gid; 2321 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1); 2322 if (err) 2323 goto demux_err; 2324 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id; 2325 atomic64_set(&dev->sriov.demux[i].subnet_prefix, 2326 be64_to_cpu(gid.global.subnet_prefix)); 2327 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1, 2328 &dev->sriov.sqps[i]); 2329 if (err) 2330 goto demux_err; 2331 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1); 2332 if (err) 2333 goto free_pv; 2334 } 2335 mlx4_ib_master_tunnels(dev, 1); 2336 return 0; 2337 2338 free_pv: 2339 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2340 demux_err: 2341 while (--i >= 0) { 2342 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2343 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2344 } 2345 mlx4_ib_device_unregister_sysfs(dev); 2346 2347 sysfs_err: 2348 mlx4_ib_destroy_alias_guid_service(dev); 2349 2350 paravirt_err: 2351 mlx4_ib_cm_paravirt_clean(dev, -1); 2352 2353 return err; 2354 } 2355 2356 void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev) 2357 { 2358 int i; 2359 unsigned long flags; 2360 2361 if (!mlx4_is_mfunc(dev->dev)) 2362 return; 2363 2364 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 2365 dev->sriov.is_going_down = 1; 2366 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 2367 if (mlx4_is_master(dev->dev)) { 2368 for (i = 0; i < dev->num_ports; i++) { 2369 flush_workqueue(dev->sriov.demux[i].ud_wq); 2370 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]); 2371 kfree(dev->sriov.sqps[i]); 2372 dev->sriov.sqps[i] = NULL; 2373 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2374 } 2375 2376 mlx4_ib_cm_paravirt_clean(dev, -1); 2377 mlx4_ib_destroy_alias_guid_service(dev); 2378 mlx4_ib_device_unregister_sysfs(dev); 2379 } 2380 } 2381